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Index: rtl/BOOT_MEM.vhd
===================================================================
--- rtl/BOOT_MEM.vhd (revision 37)
+++ rtl/BOOT_MEM.vhd (nonexistent)
@@ -1,1090 +0,0 @@
--- ########################################################
--- # << ATLAS Project - Bootloader ROM >> #
--- # **************************************************** #
--- # 2kB ROM initialized with Atlas-2k bootloader. #
--- # **************************************************** #
--- # Last modified: 28.11.2014 #
--- # **************************************************** #
--- # by Stephan Nolting 4788, Hanover, Germany #
--- ########################################################
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.atlas_core_package.all;
-
-entity boot_mem is
- port (
- -- host interface --
- clk_i : in std_ulogic; -- global clock line
- i_adr_i : in std_ulogic_vector(15 downto 0); -- instruction adr
- i_dat_o : out std_ulogic_vector(15 downto 0); -- instruction out
- d_en_i : in std_ulogic; -- access enable
- d_rw_i : in std_ulogic; -- read/write
- d_adr_i : in std_ulogic_vector(15 downto 0); -- data adr
- d_dat_i : in std_ulogic_vector(15 downto 0); -- data in
- d_dat_o : out std_ulogic_vector(15 downto 0) -- data out
- );
-end boot_mem;
-
-architecture boot_mem_structure of boot_mem is
-
- -- internal constants(configuration --
- constant mem_size_c : natural := 2048; -- 2kb
- constant log2_mem_size_c : natural := log2(mem_size_c/2); -- address width (word boundary!)
-
- -- memory type --
- type mem_file_t is array (0 to (mem_size_c/2)-1) of std_ulogic_vector(15 downto 0); -- word mem!
-
- -- memory image (bootloader program) --
- ------------------------------------------------------
- constant boot_mem_file_c : mem_file_t :=
- (
- 000000 => x"bc0e", -- B
- 000001 => x"bc04", -- B
- 000002 => x"bc03", -- B
- 000003 => x"bc02", -- B
- 000004 => x"bc01", -- B
- 000005 => x"c000", -- LDIL
- 000006 => x"cc00", -- LDIH
- 000007 => x"ec8a", -- MCR
- 000008 => x"cc19", -- LDIH
- 000009 => x"ed0f", -- MCR
- 000010 => x"c520", -- LDIL
- 000011 => x"c907", -- LDIH
- 000012 => x"be73", -- BL
- 000013 => x"bc00", -- B
- 000014 => x"ec11", -- MRC
- 000015 => x"ec88", -- MCR
- 000016 => x"ec8a", -- MCR
- 000017 => x"c380", -- LDIL
- 000018 => x"cff8", -- LDIH
- 000019 => x"1c07", -- STSR
- 000020 => x"2800", -- CLR
- 000021 => x"ec08", -- MCR
- 000022 => x"ec0b", -- MCR
- 000023 => x"ec0d", -- MCR
- 000024 => x"ec00", -- MRC
- 000025 => x"ed88", -- MCR
- 000026 => x"ed8b", -- MCR
- 000027 => x"c064", -- LDIL
- 000028 => x"ed8d", -- MCR
- 000029 => x"c901", -- LDIH
- 000030 => x"ed2f", -- MCR
- 000031 => x"ec17", -- MRC
- 000032 => x"ec97", -- MRC
- 000033 => x"c160", -- LDIL
- 000034 => x"c909", -- LDIH
- 000035 => x"c18f", -- LDIL
- 000036 => x"0923", -- ADD
- 000037 => x"29b3", -- CLR
- 000038 => x"2a44", -- CLR
- 000039 => x"100a", -- SUBS
- 000040 => x"149b", -- SBCS
- 000041 => x"9003", -- BMI
- 000042 => x"0241", -- INC
- 000043 => x"bdfc", -- B
- 000044 => x"ed49", -- MCR
- 000045 => x"ec22", -- MRC
- 000046 => x"d406", -- SBR
- 000047 => x"ed0a", -- MCR
- 000048 => x"c534", -- LDIL
- 000049 => x"c905", -- LDIH
- 000050 => x"be4d", -- BL
- 000051 => x"c12a", -- LDIL
- 000052 => x"c906", -- LDIH
- 000053 => x"be4a", -- BL
- 000054 => x"ee11", -- MRC
- 000055 => x"be4c", -- BL
- 000056 => x"c13a", -- LDIL
- 000057 => x"c906", -- LDIH
- 000058 => x"be45", -- BL
- 000059 => x"ee97", -- MRC
- 000060 => x"ee17", -- MRC
- 000061 => x"be46", -- BL
- 000062 => x"0250", -- MOV
- 000063 => x"be44", -- BL
- 000064 => x"be40", -- BL
- 000065 => x"ec27", -- MRC
- 000066 => x"c083", -- LDIL
- 000067 => x"2001", -- AND
- 000068 => x"c330", -- LDIL
- 000069 => x"0b60", -- ADD
- 000070 => x"bc0f", -- B
- 000071 => x"c552", -- LDIL
- 000072 => x"c906", -- LDIH
- 000073 => x"be36", -- BL
- 000074 => x"c144", -- LDIL
- 000075 => x"c907", -- LDIH
- 000076 => x"be33", -- BL
- 000077 => x"c50a", -- LDIL
- 000078 => x"c907", -- LDIH
- 000079 => x"be30", -- BL
- 000080 => x"be32", -- BL
- 000081 => x"0300", -- MOV
- 000082 => x"0080", -- MOV
- 000083 => x"be2e", -- BL
- 000084 => x"be2c", -- BL
- 000085 => x"c0b0", -- LDIL
- 000086 => x"181e", -- CMP
- 000087 => x"81f0", -- BEQ
- 000088 => x"c0b1", -- LDIL
- 000089 => x"181e", -- CMP
- 000090 => x"8085", -- BEQ
- 000091 => x"c0b2", -- LDIL
- 000092 => x"181e", -- CMP
- 000093 => x"8052", -- BEQ
- 000094 => x"c0b3", -- LDIL
- 000095 => x"181e", -- CMP
- 000096 => x"8019", -- BEQ
- 000097 => x"c0b4", -- LDIL
- 000098 => x"181e", -- CMP
- 000099 => x"8021", -- BEQ
- 000100 => x"c296", -- LDIL
- 000101 => x"ca83", -- LDIH
- 000102 => x"c0f0", -- LDIL
- 000103 => x"181e", -- CMP
- 000104 => x"f705", -- RBAEQ
- 000105 => x"c0e4", -- LDIL
- 000106 => x"181e", -- CMP
- 000107 => x"80e1", -- BEQ
- 000108 => x"c2c8", -- LDIL
- 000109 => x"ca85", -- LDIH
- 000110 => x"c0f7", -- LDIL
- 000111 => x"181e", -- CMP
- 000112 => x"f705", -- RBAEQ
- 000113 => x"c0f2", -- LDIL
- 000114 => x"181e", -- CMP
- 000115 => x"85da", -- BNE
- 000116 => x"2800", -- CLR
- 000117 => x"c080", -- LDIL
- 000118 => x"cc80", -- LDIH
- 000119 => x"ec99", -- MCR
- 000120 => x"3400", -- GT
- 000121 => x"c14a", -- LDIL
- 000122 => x"c906", -- LDIH
- 000123 => x"be04", -- BL
- 000124 => x"2800", -- CLR
- 000125 => x"2100", -- STUB
- 000126 => x"bca0", -- B
- 000127 => x"bc95", -- B
- 000128 => x"bc95", -- B
- 000129 => x"bc95", -- B
- 000130 => x"bc95", -- B
- 000131 => x"bc98", -- B
- 000132 => x"c528", -- LDIL
- 000133 => x"c906", -- LDIH
- 000134 => x"be8e", -- BL
- 000135 => x"be96", -- BL
- 000136 => x"edca", -- MCR
- 000137 => x"be94", -- BL
- 000138 => x"edc9", -- MCR
- 000139 => x"c036", -- LDIL
- 000140 => x"c805", -- LDIH
- 000141 => x"3404", -- GTL
- 000142 => x"be87", -- BL
- 000143 => x"be8d", -- BL
- 000144 => x"c47e", -- LDIL
- 000145 => x"cc4a", -- LDIH
- 000146 => x"180e", -- CMP
- 000147 => x"8486", -- BNE
- 000148 => x"be88", -- BL
- 000149 => x"3f64", -- SFT
- 000150 => x"2066", -- STUB
- 000151 => x"be85", -- BL
- 000152 => x"20e6", -- STUB
- 000153 => x"be83", -- BL
- 000154 => x"2166", -- STUB
- 000155 => x"be81", -- BL
- 000156 => x"21e6", -- STUB
- 000157 => x"be7f", -- BL
- 000158 => x"2266", -- STUB
- 000159 => x"be7d", -- BL
- 000160 => x"22e6", -- STUB
- 000161 => x"be7b", -- BL
- 000162 => x"2366", -- STUB
- 000163 => x"c280", -- LDIL
- 000164 => x"ecda", -- MCR
- 000165 => x"ec5e", -- MCR
- 000166 => x"be76", -- BL
- 000167 => x"7f5a", -- STR
- 000168 => x"ec06", -- MRC
- 000169 => x"2806", -- EOR
- 000170 => x"ec0e", -- MCR
- 000171 => x"2400", -- LDUB
- 000172 => x"1858", -- CMP
- 000173 => x"85f9", -- BNE
- 000174 => x"bc53", -- B
- 000175 => x"c100", -- LDIL
- 000176 => x"be28", -- BL
- 000177 => x"c47e", -- LDIL
- 000178 => x"cc4a", -- LDIH
- 000179 => x"180d", -- CMP
- 000180 => x"8465", -- BNE
- 000181 => x"c102", -- LDIL
- 000182 => x"be22", -- BL
- 000183 => x"2055", -- STUB
- 000184 => x"c104", -- LDIL
- 000185 => x"be1f", -- BL
- 000186 => x"20d5", -- STUB
- 000187 => x"c106", -- LDIL
- 000188 => x"be1c", -- BL
- 000189 => x"2155", -- STUB
- 000190 => x"c108", -- LDIL
- 000191 => x"be19", -- BL
- 000192 => x"21d5", -- STUB
- 000193 => x"c10a", -- LDIL
- 000194 => x"be16", -- BL
- 000195 => x"2255", -- STUB
- 000196 => x"c10c", -- LDIL
- 000197 => x"be13", -- BL
- 000198 => x"22d5", -- STUB
- 000199 => x"c10e", -- LDIL
- 000200 => x"be10", -- BL
- 000201 => x"2355", -- STUB
- 000202 => x"c200", -- LDIL
- 000203 => x"ecca", -- MCR
- 000204 => x"ec4e", -- MCR
- 000205 => x"c010", -- LDIL
- 000206 => x"0940", -- ADD
- 000207 => x"be09", -- BL
- 000208 => x"7eca", -- STR
- 000209 => x"ec06", -- MRC
- 000210 => x"2805", -- EOR
- 000211 => x"ec0e", -- MCR
- 000212 => x"2400", -- LDUB
- 000213 => x"1848", -- CMP
- 000214 => x"85f7", -- BNE
- 000215 => x"bc2a", -- B
- 000216 => x"0370", -- MOV
- 000217 => x"be3f", -- BL
- 000218 => x"3eb0", -- SFT
- 000219 => x"0121", -- INC
- 000220 => x"be3c", -- BL
- 000221 => x"26d3", -- ORR
- 000222 => x"3460", -- RET
- 000223 => x"c162", -- LDIL
- 000224 => x"c906", -- LDIH
- 000225 => x"be33", -- BL
- 000226 => x"be2c", -- BL
- 000227 => x"c47e", -- LDIL
- 000228 => x"cc4a", -- LDIH
- 000229 => x"1818", -- CMP
- 000230 => x"8433", -- BNE
- 000231 => x"be27", -- BL
- 000232 => x"3c94", -- SFT
- 000233 => x"2011", -- STUB
- 000234 => x"be24", -- BL
- 000235 => x"2091", -- STUB
- 000236 => x"be22", -- BL
- 000237 => x"2111", -- STUB
- 000238 => x"be20", -- BL
- 000239 => x"2191", -- STUB
- 000240 => x"be1e", -- BL
- 000241 => x"2211", -- STUB
- 000242 => x"be1c", -- BL
- 000243 => x"2291", -- STUB
- 000244 => x"be1a", -- BL
- 000245 => x"2311", -- STUB
- 000246 => x"2ad5", -- CLR
- 000247 => x"ecda", -- MCR
- 000248 => x"ec5e", -- MCR
- 000249 => x"be15", -- BL
- 000250 => x"7cda", -- STR
- 000251 => x"ec06", -- MRC
- 000252 => x"2801", -- EOR
- 000253 => x"ec0e", -- MCR
- 000254 => x"2400", -- LDUB
- 000255 => x"1858", -- CMP
- 000256 => x"85f9", -- BNE
- 000257 => x"ec11", -- MRC
- 000258 => x"ec8a", -- MCR
- 000259 => x"c506", -- LDIL
- 000260 => x"c906", -- LDIH
- 000261 => x"be0f", -- BL
- 000262 => x"ec06", -- MRC
- 000263 => x"2491", -- LDUB
- 000264 => x"1809", -- CMP
- 000265 => x"8015", -- BEQ
- 000266 => x"c52e", -- LDIL
- 000267 => x"c907", -- LDIH
- 000268 => x"be08", -- BL
- 000269 => x"bccf", -- B
- 000270 => x"0370", -- MOV
- 000271 => x"be08", -- BL
- 000272 => x"3c80", -- SFT
- 000273 => x"be06", -- BL
- 000274 => x"2490", -- ORR
- 000275 => x"3460", -- RET
- 000276 => x"bccb", -- B
- 000277 => x"bcd3", -- B
- 000278 => x"bcd7", -- B
- 000279 => x"bcdb", -- B
- 000280 => x"bc71", -- B
- 000281 => x"bcc0", -- B
- 000282 => x"bd33", -- B
- 000283 => x"bc6f", -- B
- 000284 => x"bcc2", -- B
- 000285 => x"bcda", -- B
- 000286 => x"c176", -- LDIL
- 000287 => x"c906", -- LDIH
- 000288 => x"bebf", -- BL
- 000289 => x"24aa", -- LDUBS
- 000290 => x"8010", -- BEQ
- 000291 => x"c0a2", -- LDIL
- 000292 => x"bec9", -- BL
- 000293 => x"24a2", -- LDUB
- 000294 => x"be20", -- BL
- 000295 => x"24b3", -- LDUB
- 000296 => x"be1e", -- BL
- 000297 => x"24c4", -- LDUB
- 000298 => x"be1c", -- BL
- 000299 => x"24d5", -- LDUB
- 000300 => x"be1a", -- BL
- 000301 => x"24e6", -- LDUB
- 000302 => x"be18", -- BL
- 000303 => x"c0a2", -- LDIL
- 000304 => x"bebd", -- BL
- 000305 => x"beb7", -- BL
- 000306 => x"c546", -- LDIL
- 000307 => x"c906", -- LDIH
- 000308 => x"beab", -- BL
- 000309 => x"ee06", -- MRC
- 000310 => x"bee6", -- BL
- 000311 => x"beb1", -- BL
- 000312 => x"beb0", -- BL
- 000313 => x"beaf", -- BL
- 000314 => x"beae", -- BL
- 000315 => x"c080", -- LDIL
- 000316 => x"ccc0", -- LDIH
- 000317 => x"1c01", -- STSR
- 000318 => x"2800", -- CLR
- 000319 => x"ed0f", -- MCR
- 000320 => x"ec88", -- MCR
- 000321 => x"ec8b", -- MCR
- 000322 => x"ec8c", -- MCR
- 000323 => x"ec8a", -- MCR
- 000324 => x"ec89", -- MCR
- 000325 => x"3400", -- GT
- 000326 => x"0370", -- MOV
- 000327 => x"3c90", -- SFT
- 000328 => x"bea5", -- BL
- 000329 => x"3c90", -- SFT
- 000330 => x"bea3", -- BL
- 000331 => x"3460", -- RET
- 000332 => x"c51a", -- LDIL
- 000333 => x"c906", -- LDIH
- 000334 => x"be91", -- BL
- 000335 => x"bea8", -- BL
- 000336 => x"c136", -- LDIL
- 000337 => x"c905", -- LDIH
- 000338 => x"3424", -- GTL
- 000339 => x"ecca", -- MCR
- 000340 => x"be94", -- BL
- 000341 => x"c280", -- LDIL
- 000342 => x"c00f", -- LDIL
- 000343 => x"2058", -- ANDS
- 000344 => x"840e", -- BNE
- 000345 => x"be8f", -- BL
- 000346 => x"c0a4", -- LDIL
- 000347 => x"be92", -- BL
- 000348 => x"ee12", -- MRC
- 000349 => x"bebf", -- BL
- 000350 => x"c0ae", -- LDIL
- 000351 => x"be8e", -- BL
- 000352 => x"0250", -- MOV
- 000353 => x"bebb", -- BL
- 000354 => x"c0ba", -- LDIL
- 000355 => x"be8a", -- BL
- 000356 => x"c0a0", -- LDIL
- 000357 => x"be88", -- BL
- 000358 => x"7a5a", -- LDR
- 000359 => x"c0a0", -- LDIL
- 000360 => x"be85", -- BL
- 000361 => x"beb3", -- BL
- 000362 => x"c00f", -- LDIL
- 000363 => x"2058", -- ANDS
- 000364 => x"8414", -- BNE
- 000365 => x"c0a0", -- LDIL
- 000366 => x"be7f", -- BL
- 000367 => x"be7e", -- BL
- 000368 => x"c010", -- LDIL
- 000369 => x"1250", -- SUB
- 000370 => x"c470", -- LDIL
- 000371 => x"2240", -- AND
- 000372 => x"c12e", -- LDIL
- 000373 => x"78c9", -- LDR
- 000374 => x"3c90", -- SFT
- 000375 => x"c880", -- LDIH
- 000376 => x"c020", -- LDIL
- 000377 => x"1818", -- CMP
- 000378 => x"f8c2", -- MVHI
- 000379 => x"be72", -- BL
- 000380 => x"c08f", -- LDIL
- 000381 => x"2014", -- AND
- 000382 => x"3409", -- TEQ
- 000383 => x"85f6", -- BNE
- 000384 => x"ec20", -- MRC
- 000385 => x"dc0f", -- STB
- 000386 => x"b804", -- BTS
- 000387 => x"c5fe", -- LDIL
- 000388 => x"343d", -- TEQ
- 000389 => x"85d1", -- BNE
- 000390 => x"be6c", -- BL
- 000391 => x"2800", -- CLR
- 000392 => x"3400", -- GT
- 000393 => x"bc54", -- B
- 000394 => x"bc92", -- B
- 000395 => x"c001", -- LDIL
- 000396 => x"ed0c", -- MCR
- 000397 => x"c050", -- LDIL
- 000398 => x"c83f", -- LDIH
- 000399 => x"ed0a", -- MCR
- 000400 => x"c000", -- LDIL
- 000401 => x"c801", -- LDIH
- 000402 => x"bea8", -- BL
- 000403 => x"c154", -- LDIL
- 000404 => x"c906", -- LDIH
- 000405 => x"be4a", -- BL
- 000406 => x"c162", -- LDIL
- 000407 => x"c906", -- LDIH
- 000408 => x"be47", -- BL
- 000409 => x"be59", -- BL
- 000410 => x"3c80", -- SFT
- 000411 => x"be57", -- BL
- 000412 => x"2410", -- ORR
- 000413 => x"c4fe", -- LDIL
- 000414 => x"ccca", -- LDIH
- 000415 => x"1809", -- CMP
- 000416 => x"8439", -- BNE
- 000417 => x"c100", -- LDIL
- 000418 => x"0290", -- MOV
- 000419 => x"be2f", -- BL
- 000420 => x"be4e", -- BL
- 000421 => x"3c80", -- SFT
- 000422 => x"be4c", -- BL
- 000423 => x"2690", -- ORR
- 000424 => x"3ed4", -- SFT
- 000425 => x"2055", -- STUB
- 000426 => x"c102", -- LDIL
- 000427 => x"be27", -- BL
- 000428 => x"be46", -- BL
- 000429 => x"3c80", -- SFT
- 000430 => x"be44", -- BL
- 000431 => x"2690", -- ORR
- 000432 => x"20d5", -- STUB
- 000433 => x"c104", -- LDIL
- 000434 => x"be20", -- BL
- 000435 => x"c106", -- LDIL
- 000436 => x"be3e", -- BL
- 000437 => x"0180", -- MOV
- 000438 => x"be8a", -- BL
- 000439 => x"0121", -- INC
- 000440 => x"c010", -- LDIL
- 000441 => x"1828", -- CMP
- 000442 => x"85fa", -- BNE
- 000443 => x"2ad5", -- CLR
- 000444 => x"be36", -- BL
- 000445 => x"0180", -- MOV
- 000446 => x"be82", -- BL
- 000447 => x"0121", -- INC
- 000448 => x"2400", -- LDUB
- 000449 => x"02d1", -- INC
- 000450 => x"1858", -- CMP
- 000451 => x"85f9", -- BNE
- 000452 => x"c001", -- LDIL
- 000453 => x"ed0c", -- MCR
- 000454 => x"c050", -- LDIL
- 000455 => x"c83f", -- LDIH
- 000456 => x"ed0a", -- MCR
- 000457 => x"c00c", -- LDIL
- 000458 => x"c801", -- LDIH
- 000459 => x"be6f", -- BL
- 000460 => x"c506", -- LDIL
- 000461 => x"c906", -- LDIH
- 000462 => x"be11", -- BL
- 000463 => x"c68e", -- LDIL
- 000464 => x"ca80", -- LDIH
- 000465 => x"3450", -- GT
- 000466 => x"0370", -- MOV
- 000467 => x"3dd0", -- SFT
- 000468 => x"be6c", -- BL
- 000469 => x"0121", -- INC
- 000470 => x"01d0", -- MOV
- 000471 => x"be69", -- BL
- 000472 => x"3460", -- RET
- 000473 => x"c512", -- LDIL
- 000474 => x"c907", -- LDIH
- 000475 => x"be04", -- BL
- 000476 => x"bcb9", -- B
- 000477 => x"bc93", -- B
- 000478 => x"bca4", -- B
- 000479 => x"01f0", -- MOV
- 000480 => x"78a9", -- LDR
- 000481 => x"3c90", -- SFT
- 000482 => x"c880", -- LDIH
- 000483 => x"3419", -- TEQ
- 000484 => x"8003", -- BEQ
- 000485 => x"be08", -- BL
- 000486 => x"bdfa", -- B
- 000487 => x"3430", -- RET
- 000488 => x"0170", -- MOV
- 000489 => x"c08d", -- LDIL
- 000490 => x"be03", -- BL
- 000491 => x"c08a", -- LDIL
- 000492 => x"03a0", -- MOV
- 000493 => x"ec22", -- MRC
- 000494 => x"dc05", -- STB
- 000495 => x"b9fe", -- BTS
- 000496 => x"ed18", -- MCR
- 000497 => x"3470", -- RET
- 000498 => x"ec20", -- MRC
- 000499 => x"dc8f", -- STBI
- 000500 => x"b9fe", -- BTS
- 000501 => x"c800", -- LDIH
- 000502 => x"3470", -- RET
- 000503 => x"0170", -- MOV
- 000504 => x"c200", -- LDIL
- 000505 => x"c184", -- LDIL
- 000506 => x"bff8", -- BL
- 000507 => x"c0c7", -- LDIL
- 000508 => x"1809", -- CMP
- 000509 => x"9003", -- BMI
- 000510 => x"c0a0", -- LDIL
- 000511 => x"1001", -- SUB
- 000512 => x"c0b0", -- LDIL
- 000513 => x"1809", -- CMP
- 000514 => x"91f8", -- BMI
- 000515 => x"c0c6", -- LDIL
- 000516 => x"1818", -- CMP
- 000517 => x"91f5", -- BMI
- 000518 => x"c0b9", -- LDIL
- 000519 => x"1818", -- CMP
- 000520 => x"a404", -- BLS
- 000521 => x"c0c1", -- LDIL
- 000522 => x"1809", -- CMP
- 000523 => x"a1ef", -- BHI
- 000524 => x"0080", -- MOV
- 000525 => x"bfe0", -- BL
- 000526 => x"c030", -- LDIL
- 000527 => x"1090", -- SUB
- 000528 => x"c009", -- LDIL
- 000529 => x"1809", -- CMP
- 000530 => x"a402", -- BLS
- 000531 => x"0497", -- DEC
- 000532 => x"3e42", -- SFT
- 000533 => x"3e42", -- SFT
- 000534 => x"3e42", -- SFT
- 000535 => x"3e42", -- SFT
- 000536 => x"2641", -- ORR
- 000537 => x"05b9", -- DECS
- 000538 => x"85e0", -- BNE
- 000539 => x"3420", -- RET
- 000540 => x"0370", -- MOV
- 000541 => x"3d42", -- SFT
- 000542 => x"3d22", -- SFT
- 000543 => x"3d22", -- SFT
- 000544 => x"3d22", -- SFT
- 000545 => x"be0f", -- BL
- 000546 => x"bfcb", -- BL
- 000547 => x"3d40", -- SFT
- 000548 => x"be0c", -- BL
- 000549 => x"bfc8", -- BL
- 000550 => x"3d45", -- SFT
- 000551 => x"3d25", -- SFT
- 000552 => x"3d25", -- SFT
- 000553 => x"3d25", -- SFT
- 000554 => x"be06", -- BL
- 000555 => x"bfc2", -- BL
- 000556 => x"0140", -- MOV
- 000557 => x"be03", -- BL
- 000558 => x"bfbf", -- BL
- 000559 => x"3460", -- RET
- 000560 => x"c08f", -- LDIL
- 000561 => x"2121", -- AND
- 000562 => x"c089", -- LDIL
- 000563 => x"181a", -- CMP
- 000564 => x"8803", -- BCS
- 000565 => x"c0b0", -- LDIL
- 000566 => x"bc02", -- B
- 000567 => x"c0b7", -- LDIL
- 000568 => x"0892", -- ADD
- 000569 => x"3470", -- RET
- 000570 => x"ed0b", -- MCR
- 000571 => x"ec22", -- MRC
- 000572 => x"dc03", -- STB
- 000573 => x"b9fe", -- BTS
- 000574 => x"ec23", -- MRC
- 000575 => x"3470", -- RET
- 000576 => x"00f0", -- MOV
- 000577 => x"c050", -- LDIL
- 000578 => x"c837", -- LDIH
- 000579 => x"ed0a", -- MCR
- 000580 => x"c001", -- LDIL
- 000581 => x"ed0c", -- MCR
- 000582 => x"c006", -- LDIL
- 000583 => x"bff3", -- BL
- 000584 => x"c050", -- LDIL
- 000585 => x"c83f", -- LDIH
- 000586 => x"ed0a", -- MCR
- 000587 => x"c000", -- LDIL
- 000588 => x"c805", -- LDIH
- 000589 => x"bfed", -- BL
- 000590 => x"dc01", -- STB
- 000591 => x"b805", -- BTS
- 000592 => x"c53e", -- LDIL
- 000593 => x"c907", -- LDIH
- 000594 => x"bf8d", -- BL
- 000595 => x"bc42", -- B
- 000596 => x"c040", -- LDIL
- 000597 => x"c83f", -- LDIH
- 000598 => x"ed0a", -- MCR
- 000599 => x"c001", -- LDIL
- 000600 => x"ed0c", -- MCR
- 000601 => x"3c20", -- SFT
- 000602 => x"c802", -- LDIH
- 000603 => x"bfdf", -- BL
- 000604 => x"03a0", -- MOV
- 000605 => x"cb80", -- LDIH
- 000606 => x"3ff0", -- SFT
- 000607 => x"0030", -- MOV
- 000608 => x"c800", -- LDIH
- 000609 => x"2407", -- ORR
- 000610 => x"bfd8", -- BL
- 000611 => x"2800", -- CLR
- 000612 => x"ed0c", -- MCR
- 000613 => x"c050", -- LDIL
- 000614 => x"c83f", -- LDIH
- 000615 => x"ed0a", -- MCR
- 000616 => x"c001", -- LDIL
- 000617 => x"ed0c", -- MCR
- 000618 => x"c000", -- LDIL
- 000619 => x"c805", -- LDIH
- 000620 => x"bfce", -- BL
- 000621 => x"dc00", -- STB
- 000622 => x"b9fc", -- BTS
- 000623 => x"3410", -- RET
- 000624 => x"00f0", -- MOV
- 000625 => x"c040", -- LDIL
- 000626 => x"c83f", -- LDIH
- 000627 => x"ed0a", -- MCR
- 000628 => x"c001", -- LDIL
- 000629 => x"ed0c", -- MCR
- 000630 => x"3c20", -- SFT
- 000631 => x"c803", -- LDIH
- 000632 => x"bfc2", -- BL
- 000633 => x"0020", -- MOV
- 000634 => x"c800", -- LDIH
- 000635 => x"3c00", -- SFT
- 000636 => x"bfbe", -- BL
- 000637 => x"29b3", -- CLR
- 000638 => x"ed3c", -- MCR
- 000639 => x"0180", -- MOV
- 000640 => x"c980", -- LDIH
- 000641 => x"3410", -- RET
- 000642 => x"e5b0", -- CDP
- 000643 => x"ec30", -- MRC
- 000644 => x"dc06", -- STB
- 000645 => x"b9fe", -- BTS
- 000646 => x"c306", -- LDIL
- 000647 => x"200e", -- ANDS
- 000648 => x"840a", -- BNE
- 000649 => x"ecb1", -- MRC
- 000650 => x"ef32", -- MRC
- 000651 => x"2800", -- CLR
- 000652 => x"009a", -- INCS
- 000653 => x"0f60", -- ADC
- 000654 => x"ed99", -- MCR
- 000655 => x"edea", -- MCR
- 000656 => x"ef34", -- MRC
- 000657 => x"3470", -- RET
- 000658 => x"c550", -- LDIL
- 000659 => x"c907", -- LDIH
- 000660 => x"bf4b", -- BL
- 000661 => x"c55e", -- LDIL
- 000662 => x"c907", -- LDIH
- 000663 => x"bf48", -- BL
- 000664 => x"bf5a", -- BL
- 000665 => x"2800", -- CLR
- 000666 => x"3400", -- GT
- 000667 => x"0170", -- MOV
- 000668 => x"bf56", -- BL
- 000669 => x"c08d", -- LDIL
- 000670 => x"1809", -- CMP
- 000671 => x"f702", -- RBAEQ
- 000672 => x"c088", -- LDIL
- 000673 => x"1809", -- CMP
- 000674 => x"8034", -- BEQ
- 000675 => x"bdf9", -- B
- 000676 => x"c528", -- LDIL
- 000677 => x"c906", -- LDIH
- 000678 => x"bf39", -- BL
- 000679 => x"bf50", -- BL
- 000680 => x"edca", -- MCR
- 000681 => x"bf4e", -- BL
- 000682 => x"edc9", -- MCR
- 000683 => x"bff0", -- BL
- 000684 => x"bf3c", -- BL
- 000685 => x"c536", -- LDIL
- 000686 => x"c906", -- LDIH
- 000687 => x"bf30", -- BL
- 000688 => x"bf47", -- BL
- 000689 => x"02c0", -- MOV
- 000690 => x"bfe9", -- BL
- 000691 => x"bf35", -- BL
- 000692 => x"345d", -- TEQ
- 000693 => x"8021", -- BEQ
- 000694 => x"06d1", -- DEC
- 000695 => x"bf31", -- BL
- 000696 => x"c0a4", -- LDIL
- 000697 => x"bf34", -- BL
- 000698 => x"ee32", -- MRC
- 000699 => x"bf61", -- BL
- 000700 => x"ee31", -- MRC
- 000701 => x"bf5f", -- BL
- 000702 => x"c0ba", -- LDIL
- 000703 => x"bf2e", -- BL
- 000704 => x"c0a0", -- LDIL
- 000705 => x"bf2c", -- BL
- 000706 => x"bfc0", -- BL
- 000707 => x"0260", -- MOV
- 000708 => x"bf58", -- BL
- 000709 => x"c320", -- LDIL
- 000710 => x"c1ae", -- LDIL
- 000711 => x"00e0", -- MOV
- 000712 => x"bf25", -- BL
- 000713 => x"3cc0", -- SFT
- 000714 => x"c880", -- LDIH
- 000715 => x"181e", -- CMP
- 000716 => x"f8c3", -- MVHI
- 000717 => x"bf20", -- BL
- 000718 => x"00c0", -- MOV
- 000719 => x"c880", -- LDIH
- 000720 => x"181e", -- CMP
- 000721 => x"f8c3", -- MVHI
- 000722 => x"bf1b", -- BL
- 000723 => x"eca0", -- MRC
- 000724 => x"dc9f", -- STBI
- 000725 => x"b9df", -- BTS
- 000726 => x"bf12", -- BL
- 000727 => x"c69a", -- LDIL
- 000728 => x"ca80", -- LDIH
- 000729 => x"3450", -- GT
- 000730 => x"0d0a", -- .DW
- 000731 => x"0d0a", -- .DW
- 000732 => x"4174", -- .DW
- 000733 => x"6c61", -- .DW
- 000734 => x"732d", -- .DW
- 000735 => x"324b", -- .DW
- 000736 => x"2042", -- .DW
- 000737 => x"6f6f", -- .DW
- 000738 => x"746c", -- .DW
- 000739 => x"6f61", -- .DW
- 000740 => x"6465", -- .DW
- 000741 => x"7220", -- .DW
- 000742 => x"2d20", -- .DW
- 000743 => x"5632", -- .DW
- 000744 => x"3031", -- .DW
- 000745 => x"3430", -- .DW
- 000746 => x"3531", -- .DW
- 000747 => x"360d", -- .DW
- 000748 => x"0a62", -- .DW
- 000749 => x"7920", -- .DW
- 000750 => x"5374", -- .DW
- 000751 => x"6570", -- .DW
- 000752 => x"6861", -- .DW
- 000753 => x"6e20", -- .DW
- 000754 => x"4e6f", -- .DW
- 000755 => x"6c74", -- .DW
- 000756 => x"696e", -- .DW
- 000757 => x"672c", -- .DW
- 000758 => x"2073", -- .DW
- 000759 => x"746e", -- .DW
- 000760 => x"6f6c", -- .DW
- 000761 => x"7469", -- .DW
- 000762 => x"6e67", -- .DW
- 000763 => x"4067", -- .DW
- 000764 => x"6d61", -- .DW
- 000765 => x"696c", -- .DW
- 000766 => x"2e63", -- .DW
- 000767 => x"6f6d", -- .DW
- 000768 => x"0d0a", -- .DW
- 000769 => x"7777", -- .DW
- 000770 => x"772e", -- .DW
- 000771 => x"6f70", -- .DW
- 000772 => x"656e", -- .DW
- 000773 => x"636f", -- .DW
- 000774 => x"7265", -- .DW
- 000775 => x"732e", -- .DW
- 000776 => x"6f72", -- .DW
- 000777 => x"672f", -- .DW
- 000778 => x"7072", -- .DW
- 000779 => x"6f6a", -- .DW
- 000780 => x"6563", -- .DW
- 000781 => x"742c", -- .DW
- 000782 => x"6174", -- .DW
- 000783 => x"6c61", -- .DW
- 000784 => x"735f", -- .DW
- 000785 => x"636f", -- .DW
- 000786 => x"7265", -- .DW
- 000787 => x"0d0a", -- .DW
- 000788 => x"0000", -- .DW
- 000789 => x"0d0a", -- .DW
- 000790 => x"426f", -- .DW
- 000791 => x"6f74", -- .DW
- 000792 => x"2070", -- .DW
- 000793 => x"6167", -- .DW
- 000794 => x"653a", -- .DW
- 000795 => x"2030", -- .DW
- 000796 => x"7800", -- .DW
- 000797 => x"0d0a", -- .DW
- 000798 => x"436c", -- .DW
- 000799 => x"6f63", -- .DW
- 000800 => x"6b28", -- .DW
- 000801 => x"487a", -- .DW
- 000802 => x"293a", -- .DW
- 000803 => x"2030", -- .DW
- 000804 => x"7800", -- .DW
- 000805 => x"426f", -- .DW
- 000806 => x"6f74", -- .DW
- 000807 => x"696e", -- .DW
- 000808 => x"670d", -- .DW
- 000809 => x"0a00", -- .DW
- 000810 => x"4275", -- .DW
- 000811 => x"726e", -- .DW
- 000812 => x"2045", -- .DW
- 000813 => x"4550", -- .DW
- 000814 => x"524f", -- .DW
- 000815 => x"4d0d", -- .DW
- 000816 => x"0a00", -- .DW
- 000817 => x"4177", -- .DW
- 000818 => x"6169", -- .DW
- 000819 => x"7469", -- .DW
- 000820 => x"6e67", -- .DW
- 000821 => x"2069", -- .DW
- 000822 => x"6d61", -- .DW
- 000823 => x"6765", -- .DW
- 000824 => x"2e2e", -- .DW
- 000825 => x"2e0d", -- .DW
- 000826 => x"0a00", -- .DW
- 000827 => x"5374", -- .DW
- 000828 => x"6172", -- .DW
- 000829 => x"7469", -- .DW
- 000830 => x"6e67", -- .DW
- 000831 => x"2069", -- .DW
- 000832 => x"6d61", -- .DW
- 000833 => x"6765", -- .DW
- 000834 => x"2000", -- .DW
- 000835 => x"446f", -- .DW
- 000836 => x"776e", -- .DW
- 000837 => x"6c6f", -- .DW
- 000838 => x"6164", -- .DW
- 000839 => x"2063", -- .DW
- 000840 => x"6f6d", -- .DW
- 000841 => x"706c", -- .DW
- 000842 => x"6574", -- .DW
- 000843 => x"650d", -- .DW
- 000844 => x"0a00", -- .DW
- 000845 => x"5061", -- .DW
- 000846 => x"6765", -- .DW
- 000847 => x"2028", -- .DW
- 000848 => x"3468", -- .DW
- 000849 => x"293a", -- .DW
- 000850 => x"2024", -- .DW
- 000851 => x"0000", -- .DW
- 000852 => x"4164", -- .DW
- 000853 => x"6472", -- .DW
- 000854 => x"2028", -- .DW
- 000855 => x"3868", -- .DW
- 000856 => x"293a", -- .DW
- 000857 => x"2024", -- .DW
- 000858 => x"0000", -- .DW
- 000859 => x"2377", -- .DW
- 000860 => x"6f72", -- .DW
- 000861 => x"6473", -- .DW
- 000862 => x"2028", -- .DW
- 000863 => x"3468", -- .DW
- 000864 => x"293a", -- .DW
- 000865 => x"2024", -- .DW
- 000866 => x"0000", -- .DW
- 000867 => x"4368", -- .DW
- 000868 => x"6563", -- .DW
- 000869 => x"6b73", -- .DW
- 000870 => x"756d", -- .DW
- 000871 => x"3a20", -- .DW
- 000872 => x"2400", -- .DW
- 000873 => x"0d0a", -- .DW
- 000874 => x"636d", -- .DW
- 000875 => x"642f", -- .DW
- 000876 => x"626f", -- .DW
- 000877 => x"6f74", -- .DW
- 000878 => x"2d73", -- .DW
- 000879 => x"7769", -- .DW
- 000880 => x"7463", -- .DW
- 000881 => x"683a", -- .DW
- 000882 => x"0d0a", -- .DW
- 000883 => x"2030", -- .DW
- 000884 => x"2f27", -- .DW
- 000885 => x"3030", -- .DW
- 000886 => x"273a", -- .DW
- 000887 => x"2028", -- .DW
- 000888 => x"5265", -- .DW
- 000889 => x"2d29", -- .DW
- 000890 => x"5374", -- .DW
- 000891 => x"6172", -- .DW
- 000892 => x"7420", -- .DW
- 000893 => x"636f", -- .DW
- 000894 => x"6e73", -- .DW
- 000895 => x"6f6c", -- .DW
- 000896 => x"650d", -- .DW
- 000897 => x"0a20", -- .DW
- 000898 => x"312f", -- .DW
- 000899 => x"2730", -- .DW
- 000900 => x"3127", -- .DW
- 000901 => x"3a20", -- .DW
- 000902 => x"426f", -- .DW
- 000903 => x"6f74", -- .DW
- 000904 => x"2055", -- .DW
- 000905 => x"4152", -- .DW
- 000906 => x"540d", -- .DW
- 000907 => x"0a20", -- .DW
- 000908 => x"322f", -- .DW
- 000909 => x"2731", -- .DW
- 000910 => x"3027", -- .DW
- 000911 => x"3a20", -- .DW
- 000912 => x"426f", -- .DW
- 000913 => x"6f74", -- .DW
- 000914 => x"2045", -- .DW
- 000915 => x"4550", -- .DW
- 000916 => x"524f", -- .DW
- 000917 => x"4d0d", -- .DW
- 000918 => x"0a20", -- .DW
- 000919 => x"332f", -- .DW
- 000920 => x"2731", -- .DW
- 000921 => x"3127", -- .DW
- 000922 => x"3a20", -- .DW
- 000923 => x"426f", -- .DW
- 000924 => x"6f74", -- .DW
- 000925 => x"206d", -- .DW
- 000926 => x"656d", -- .DW
- 000927 => x"6f72", -- .DW
- 000928 => x"790d", -- .DW
- 000929 => x"0a00", -- .DW
- 000930 => x"2034", -- .DW
- 000931 => x"3a20", -- .DW
- 000932 => x"426f", -- .DW
- 000933 => x"6f74", -- .DW
- 000934 => x"2057", -- .DW
- 000935 => x"420d", -- .DW
- 000936 => x"0a20", -- .DW
- 000937 => x"703a", -- .DW
- 000938 => x"2042", -- .DW
- 000939 => x"7572", -- .DW
- 000940 => x"6e20", -- .DW
- 000941 => x"4545", -- .DW
- 000942 => x"5052", -- .DW
- 000943 => x"4f4d", -- .DW
- 000944 => x"0d0a", -- .DW
- 000945 => x"2064", -- .DW
- 000946 => x"3a20", -- .DW
- 000947 => x"5241", -- .DW
- 000948 => x"4d20", -- .DW
- 000949 => x"6475", -- .DW
- 000950 => x"6d70", -- .DW
- 000951 => x"0d0a", -- .DW
- 000952 => x"2072", -- .DW
- 000953 => x"3a20", -- .DW
- 000954 => x"5265", -- .DW
- 000955 => x"7365", -- .DW
- 000956 => x"740d", -- .DW
- 000957 => x"0a20", -- .DW
- 000958 => x"773a", -- .DW
- 000959 => x"2057", -- .DW
- 000960 => x"4220", -- .DW
- 000961 => x"6475", -- .DW
- 000962 => x"6d70", -- .DW
- 000963 => x"0d0a", -- .DW
- 000964 => x"0000", -- .DW
- 000965 => x"636d", -- .DW
- 000966 => x"643a", -- .DW
- 000967 => x"3e20", -- .DW
- 000968 => x"0000", -- .DW
- 000969 => x"494d", -- .DW
- 000970 => x"4147", -- .DW
- 000971 => x"4520", -- .DW
- 000972 => x"4552", -- .DW
- 000973 => x"5221", -- .DW
- 000974 => x"0d0a", -- .DW
- 000975 => x"0000", -- .DW
- 000976 => x"0d0a", -- .DW
- 000977 => x"4952", -- .DW
- 000978 => x"5120", -- .DW
- 000979 => x"4552", -- .DW
- 000980 => x"5221", -- .DW
- 000981 => x"0d0a", -- .DW
- 000982 => x"0000", -- .DW
- 000983 => x"4348", -- .DW
- 000984 => x"4543", -- .DW
- 000985 => x"4b53", -- .DW
- 000986 => x"554d", -- .DW
- 000987 => x"2045", -- .DW
- 000988 => x"5252", -- .DW
- 000989 => x"210d", -- .DW
- 000990 => x"0a00", -- .DW
- 000991 => x"5350", -- .DW
- 000992 => x"492f", -- .DW
- 000993 => x"4545", -- .DW
- 000994 => x"5052", -- .DW
- 000995 => x"4f4d", -- .DW
- 000996 => x"2045", -- .DW
- 000997 => x"5252", -- .DW
- 000998 => x"210d", -- .DW
- 000999 => x"0a00", -- .DW
- 001000 => x"5742", -- .DW
- 001001 => x"2042", -- .DW
- 001002 => x"5553", -- .DW
- 001003 => x"2045", -- .DW
- 001004 => x"5252", -- .DW
- 001005 => x"210d", -- .DW
- 001006 => x"0a00", -- .DW
- 001007 => x"5072", -- .DW
- 001008 => x"6573", -- .DW
- 001009 => x"7320", -- .DW
- 001010 => x"616e", -- .DW
- 001011 => x"7920", -- .DW
- 001012 => x"6b65", -- .DW
- 001013 => x"790d", -- .DW
- 001014 => x"0a00", -- .DW
- others => x"0000" -- NOP
- );
- ------------------------------------------------------
-
-begin
-
- -- Memory Access ---------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- mem_file_access: process(clk_i)
- begin
- if rising_edge(clk_i) then
- -- data read --
- if (d_en_i = '1') then -- valid access
- if (word_mode_en_c = true) then -- read data access
- d_dat_o <= boot_mem_file_c(to_integer(unsigned(d_adr_i(log2_mem_size_c-1 downto 0))));
- else
- d_dat_o <= boot_mem_file_c(to_integer(unsigned(d_adr_i(log2_mem_size_c downto 1))));
- end if;
- end if;
- -- instruction read --
- if (word_mode_en_c = true) then
- i_dat_o <= boot_mem_file_c(to_integer(unsigned(i_adr_i(log2_mem_size_c-1 downto 0))));
- else
- i_dat_o <= boot_mem_file_c(to_integer(unsigned(i_adr_i(log2_mem_size_c downto 1))));
- end if;
- end if;
- end process mem_file_access;
-
-
-
-end boot_mem_structure;
Index: rtl/CTRL.vhd
===================================================================
--- rtl/CTRL.vhd (revision 37)
+++ rtl/CTRL.vhd (nonexistent)
@@ -1,273 +0,0 @@
--- ########################################################
--- # << ATLAS Project - CPU Control Spine >> #
--- # **************************************************** #
--- # Main control system, generating control signals #
--- # for each pipeline stage. #
--- # **************************************************** #
--- # Last modified: 28.11.2014 #
--- # **************************************************** #
--- # by Stephan Nolting 4788, Hanover, Germany #
--- ########################################################
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.atlas_core_package.all;
-
-entity ctrl is
- port (
--- ###############################################################################################
--- ## Global Control ##
--- ###############################################################################################
-
- clk_i : in std_ulogic; -- global clock line
- ce_i : in std_ulogic; -- clock enable
- rst_i : in std_ulogic; -- global reset line, sync, high-active
-
--- ###############################################################################################
--- ## Decoder Interface ##
--- ###############################################################################################
-
- op_dec_ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- decoder ctrl lines
- multi_cyc_o : out std_ulogic; -- multi-cycle indicator
- multi_cyc_req_i : in std_ulogic; -- multi-cycle request
- instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction input
- instr_reg_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction register
-
--- ###############################################################################################
--- ## Control Lines ##
--- ###############################################################################################
-
- of_ctrl_bus_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- of stage control
- ex_ctrl_bus_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- ex stage control
- ma_ctrl_bus_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- ma stage control
- wb_ctrl_bus_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- wb stage control
-
--- ###############################################################################################
--- ## Function Control ##
--- ###############################################################################################
-
- cond_true_i : in std_ulogic; -- condition is true
- valid_branch_i : in std_ulogic; -- valid branch detected
- exc_taken_i : in std_ulogic; -- exception taken
- wake_up_i : in std_ulogic; -- wake up from sleep
- exc_pos_o : out std_ulogic; -- exception would be possible
- stop_pc_o : out std_ulogic -- freeze program counter
- );
-end ctrl;
-
-architecture ctrl_structure of ctrl is
-
- -- pipeline register --
- signal ex_ctrl_ff : std_ulogic_vector(ctrl_width_c-1 downto 0);
- signal ex_ctrl_buf : std_ulogic_vector(ctrl_width_c-1 downto 0);
- signal ma_ctrl_ff : std_ulogic_vector(ctrl_width_c-1 downto 0);
- signal wb_ctrl_ff : std_ulogic_vector(ctrl_width_c-1 downto 0);
-
- -- branch arbiter --
- signal dis_cycle_ff : std_ulogic;
- signal dis_cycle : std_ulogic;
-
- -- instruction fetch arbiter --
- signal dis_if : std_ulogic;
- signal mem_dependecy : std_ulogic;
- signal multi_cyc_ff : std_ulogic;
- signal ir_backup_reg : std_ulogic_vector(data_width_c-1 downto 0);
- signal ir_backup_ctrl : std_ulogic;
-
- -- system enable/start-up control --
- signal sys_enable : std_ulogic;
- signal start_ff : std_ulogic;
- signal sleep_flag : std_ulogic;
-
-begin
-
- -- System Enable-FF ------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- system_enable: process(clk_i)
- begin
- if rising_edge(clk_i) then
- if (rst_i = '1') then
- start_ff <= '0';
- sleep_flag <= '0';
- elsif (ce_i = '1') then
- start_ff <= '1'; -- pretty amazing, huh? ;)
- if (op_dec_ctrl_i(ctrl_sleep_c) = '1') then
- sleep_flag <= '1'; -- go to sleep
- elsif (wake_up_i = '1') then
- sleep_flag <= '0'; -- wake up
- end if;
- end if;
- end if;
- end process system_enable;
-
- -- enable control --
- sys_enable <= (not sleep_flag) and start_ff;
-
-
- -- Stage 0: Pipeline Flow Arbiter ----------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- flow_arbiter: process(clk_i)
- begin
- if rising_edge(clk_i) then
- if (rst_i = '1') then
- multi_cyc_ff <= '0';
- dis_cycle_ff <= '0';
- elsif (ce_i = '1') then
- multi_cyc_ff <= multi_cyc_req_i;
- if (valid_branch_i = '1') then
- dis_cycle_ff <= '1'; -- one additional cycle for branches and system / ext interrupts
- elsif (dis_cycle_ff = '1') and (multi_cyc_req_i = '0') then -- hold when multi-cycle op required
- dis_cycle_ff <= '0';
- end if;
- end if;
- end if;
- end process flow_arbiter;
-
- -- multi cycle outut --
- multi_cyc_o <= multi_cyc_ff;
-
-
- -- temporal data dependency detector for memory-load operations --
- ---------------------------------------------------------------------
- t_ddd: process(op_dec_ctrl_i, ex_ctrl_ff)
- variable a_match_v, b_match_v : std_ulogic;
- begin
- -- operand a dependency? --
- a_match_v := '0';
- if ((op_dec_ctrl_i(ctrl_ra_3_c downto ctrl_ra_0_c) = ex_ctrl_ff(ctrl_rd_3_c downto ctrl_rd_0_c)) and (op_dec_ctrl_i(ctrl_ra_is_pc_c) = '0')) then
- a_match_v := '1';
- end if;
-
- -- operand b dependency? --
- b_match_v := '0';
- if ((op_dec_ctrl_i(ctrl_rb_3_c downto ctrl_rb_0_c) = ex_ctrl_ff(ctrl_rd_3_c downto ctrl_rd_0_c)) and (op_dec_ctrl_i(ctrl_rb_is_imm_c) = '0')) then
- b_match_v := '1';
- end if;
-
- -- memory load dependency? --
- mem_dependecy <= ex_ctrl_ff(ctrl_en_c) and ex_ctrl_ff(ctrl_rd_wb_c) and ex_ctrl_ff(ctrl_mem_acc_c) and (not ex_ctrl_ff(ctrl_mem_wr_c)) and (a_match_v or b_match_v);
- end process t_ddd;
-
-
- -- disable control --
- -- branch / exception: disable next 2 cycles
- -- mem-load dependency: insert 1 dummy cycle
- branch_slots: -- highly experimental!!!
- if (branch_slots_en_c = true) generate
- dis_cycle <= '1' when (mem_dependecy = '1') or (sys_enable = '0') else '0';
- end generate branch_slots;
- no_branch_slots:
- if (branch_slots_en_c = false) generate
- dis_cycle <= '1' when (dis_cycle_ff = '1') or (valid_branch_i = '1') or (mem_dependecy = '1') or (sys_enable = '0') else '0';
- end generate no_branch_slots;
- dis_if <= multi_cyc_req_i or sleep_flag;
- stop_pc_o <= dis_if or mem_dependecy;
-
-
- -- instruction backup register --
- ---------------------------------
- i_reg: process(clk_i)
- begin
- if rising_edge(clk_i) then
- if (rst_i = '1') then
- ir_backup_ctrl <= '0';
- ir_backup_reg <= (others => '0');
- elsif (ce_i = '1') then
- ir_backup_ctrl <= dis_if or mem_dependecy; -- = stop_pc_o
- if (ir_backup_ctrl = '0') then
- ir_backup_reg <= instr_i;
- end if;
- end if;
- end if;
- end process i_reg;
-
- -- instruction selection --
- instr_reg_o <= instr_i when (ir_backup_ctrl = '0') else ir_backup_reg;
-
-
- -- stage 1: operand fetch ------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- of_ctrl_bus_o <= op_dec_ctrl_i;
-
-
- -- Stage 2: Execution ----------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- ex_stage: process (clk_i)
- begin
- if rising_edge(clk_i) then
- if (rst_i = '1') then
- ex_ctrl_ff <= (others => '0');
- elsif (ce_i = '1') then
- ex_ctrl_ff <= op_dec_ctrl_i;
- ex_ctrl_ff(ctrl_en_c) <= op_dec_ctrl_i(ctrl_en_c) and (not dis_cycle);
- ex_ctrl_ff(ctrl_mcyc_c) <= multi_cyc_ff; -- un-interruptable multi-cycle operation?
- end if;
- end if;
- end process ex_stage;
-
-
- -- exception insertion system --
- exc_insertion: process (ex_ctrl_ff, exc_taken_i)
- begin
- ex_ctrl_buf <= ex_ctrl_ff;
- if (exc_taken_i = '1') then -- is exception? - insert link register and invalidate current operation
- ex_ctrl_buf(ctrl_rd_3_c downto ctrl_rd_0_c) <= system_mode_c & link_reg_adr_c; -- save to sys link reg
- ex_ctrl_buf(ctrl_en_c) <= '0'; -- disable it all
- ex_ctrl_buf(ctrl_link_c) <= '1'; -- link return address
- end if;
- end process exc_insertion;
-
- -- output --
- ex_ctrl_bus_o <= ex_ctrl_buf;
- exc_pos_o <= ex_ctrl_ff(ctrl_en_c) and (not ex_ctrl_ff(ctrl_mcyc_c)); -- exception would be possible and no in-interuptable op
-
-
- -- Stage 3: Memory Access ------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- ma_stage: process (clk_i)
- begin
- if rising_edge(clk_i) then
- if (rst_i = '1') then
- ma_ctrl_ff <= (others => '0');
- elsif (ce_i = '1') then
- ma_ctrl_ff <= ex_ctrl_buf;
- -- some pre-processing to shorten critical path --
- if (valid_branch_i = '0') and (ex_ctrl_buf(ctrl_branch_c) = '1') then -- unfullfilled branch
- ma_ctrl_ff(ctrl_wb_en_c) <= exc_taken_i; -- irqs may process anyway
- else -- valid reg data write-back and true condition for cond- write back or exception taken
- ma_ctrl_ff(ctrl_wb_en_c) <= (ex_ctrl_buf(ctrl_en_c) and ex_ctrl_buf(ctrl_rd_wb_c) and (ex_ctrl_buf(ctrl_cond_wb_c) nand (not cond_true_i))) or exc_taken_i;
- end if;
- ma_ctrl_ff(ctrl_rd_cp_acc_c) <= ex_ctrl_buf(ctrl_cp_acc_c) and (not ex_ctrl_buf(ctrl_cp_wr_c)); -- cp read-back
- ma_ctrl_ff(ctrl_cp_msr_rd_c) <= (ex_ctrl_buf(ctrl_cp_acc_c) and (not ex_ctrl_buf(ctrl_cp_wr_c))) or (ex_ctrl_buf(ctrl_msr_rd_c)); -- cp or msr read access
- end if;
- end if;
- end process ma_stage;
-
- -- output --
- ma_ctrl_bus_o <= ma_ctrl_ff;
-
-
- -- Stage 4: Write Back ---------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- wb_stage: process (clk_i)
- begin
- if rising_edge(clk_i) then
- if (rst_i = '1') then
- wb_ctrl_ff <= (others => '0');
- elsif (ce_i = '1') then
- wb_ctrl_ff <= ma_ctrl_ff;
- -- some pre-processing to shorten critical path --
- wb_ctrl_ff(ctrl_rd_mem_acc_c) <= ma_ctrl_ff(ctrl_mem_acc_c) and (not ma_ctrl_ff(ctrl_mem_wr_c)); -- valid memory read-back
- end if;
- end if;
- end process wb_stage;
-
- -- output --
- wb_ctrl_bus_o <= wb_ctrl_ff;
-
-
-
-end ctrl_structure;
Index: rtl/COM_0_CORE.vhd
===================================================================
--- rtl/COM_0_CORE.vhd (revision 37)
+++ rtl/COM_0_CORE.vhd (nonexistent)
@@ -1,487 +0,0 @@
--- #########################################################
--- # << ATLAS Project - Communication Controller 0 >> #
--- # ***************************************************** #
--- # -> UART (RXD, TXD) #
--- # -> SPI (8 channels) #
--- # -> Parallel IO (16 in, 16 out) #
--- # -> System IO (8 in, 8 out) #
--- # ***************************************************** #
--- # Last modified: 28.11.2014 #
--- # ***************************************************** #
--- # by Stephan Nolting 4788, Hanover, Germany #
--- #########################################################
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.atlas_core_package.all;
-
-entity com_0_core is
- port (
--- ###############################################################################################
--- ## Host Interface ##
--- ###############################################################################################
-
- clk_i : in std_ulogic; -- global clock line
- rst_i : in std_ulogic; -- global reset line, sync, high-active
- ice_i : in std_ulogic; -- interface clock enable, high-active
- w_en_i : in std_ulogic; -- write enable
- r_en_i : in std_ulogic; -- read enable
- adr_i : in std_ulogic_vector(02 downto 0); -- access address
- dat_i : in std_ulogic_vector(15 downto 0); -- write data
- dat_o : out std_ulogic_vector(15 downto 0); -- read data
-
--- ###############################################################################################
--- ## Interrupt Lines ##
--- ###############################################################################################
-
- uart_rx_irq_o : out std_ulogic; -- uart irq "data available"
- uart_tx_irq_o : out std_ulogic; -- uart irq "sending done"
- spi_irq_o : out std_ulogic; -- spi irq "transfer done"
- pio_irq_o : out std_ulogic; -- pio input pin change irq
-
--- ###############################################################################################
--- ## Communication Lines ##
--- ###############################################################################################
-
- uart_txd_o : out std_ulogic; -- uart serial output
- uart_rxd_i : in std_ulogic; -- uart serial input
- spi_mosi_o : out std_ulogic_vector(07 downto 0); -- serial data out
- spi_miso_i : in std_ulogic_vector(07 downto 0); -- serial data in
- spi_sck_o : out std_ulogic_vector(07 downto 0); -- serial clock out
- spi_cs_o : out std_ulogic_vector(07 downto 0); -- chip select (low active)
- pio_in_i : in std_ulogic_vector(15 downto 0); -- parallel input
- pio_out_o : out std_ulogic_vector(15 downto 0); -- parallel output
- sys_io_i : in std_ulogic_vector(07 downto 0); -- system input
- sys_io_o : out std_ulogic_vector(07 downto 0) -- system output
- );
-end com_0_core;
-
-architecture com_0_core_behav of com_0_core is
-
- -- Module Addresses --
- constant uart_rtx_sd_reg_c : std_ulogic_vector(02 downto 0) := "000"; -- R/W: UART RTX data + status flags
- constant uart_prsc_reg_c : std_ulogic_vector(02 downto 0) := "001"; -- R/W: UART prescaler register
- constant com_ctrl_reg_c : std_ulogic_vector(02 downto 0) := "010"; -- R/W: COM control register
- constant spi_data_reg_c : std_ulogic_vector(02 downto 0) := "011"; -- R/W: SPI RTX data register
- constant spi_cs_reg_c : std_ulogic_vector(02 downto 0) := "100"; -- R/W: SPI chip select register
- constant pio_in_reg_c : std_ulogic_vector(02 downto 0) := "101"; -- R: PIO input register
- constant pio_out_reg_c : std_ulogic_vector(02 downto 0) := "110"; -- R/W: PIO output register
- constant sys_io_reg_c : std_ulogic_vector(02 downto 0) := "111"; -- R/W: System parallel in/out
-
- -- CTRL Register --
- constant spi_cr_dir_flag_c : natural := 0; -- R/W: 0: MSB first, 1: LSB first
- constant spi_cr_cpol_c : natural := 1; -- R/W: clock polarity, 1: idle '1' clock, 0: idle '0' clock
- constant spi_cr_cpha_c : natural := 2; -- R/W: edge offset: 0: first edge, 1: second edge
- constant spi_cr_bsy_c : natural := 3; -- R: transceiver is busy when '1'
- constant spi_cr_auto_cs_c : natural := 4; -- R/W: Auto apply CS when '1'
- constant uart_tx_busy_c : natural := 5; -- R: UART transmitter is busy
- constant uart_en_c : natural := 6; -- R/W: UART enable
- constant uart_ry_ovf_c : natural := 7; -- R: UART Rx overflow corruption
- constant spi_cr_ln_lsb_c : natural := 8; -- R/W: data length lsb
- constant spi_cr_ln_msb_c : natural := 11; -- R/W: data length msb
- constant spi_cr_prsc_lsb_c : natural := 12; -- R/W: SPI clock prescaler lsb
- constant spi_cr_prsc_msb_c : natural := 15; -- R/W: SPI clock prescaler msb
-
- -- UART Control Flags (UART RTX REG) --
- constant uart_rx_ready_c : natural := 15; -- R: Data received
-
- -- uart registers --
- signal uart_rx_reg : std_ulogic_vector(07 downto 0);
- signal uart_prsc_reg : std_ulogic_vector(15 downto 0);
-
- -- uart transceiver --
- signal uart_rx_sync : std_ulogic_vector(03 downto 0);
- signal uart_tx_bsy_flag : std_ulogic;
- signal uart_dcor_flag : std_ulogic;
- signal uart_rx_bsy_flag : std_ulogic;
- signal uart_tx_sreg : std_ulogic_vector(09 downto 0);
- signal uart_rx_sreg : std_ulogic_vector(09 downto 0);
- signal uart_tx_bit_cnt : std_ulogic_vector(03 downto 0);
- signal uart_rx_bit_cnt : std_ulogic_vector(03 downto 0);
- signal uart_tx_baud_cnt : std_ulogic_vector(15 downto 0);
- signal uart_rx_baud_cnt : std_ulogic_vector(15 downto 0);
- signal uart_rx_ready : std_ulogic;
- signal uart_rx_ready_sync : std_ulogic;
-
- -- spi registers --
- signal spi_tx_reg : std_ulogic_vector(15 downto 0);
- signal spi_rx_reg : std_ulogic_vector(15 downto 0);
- signal spi_rx_reg_nxt : std_ulogic_vector(15 downto 0);
- signal spi_cs_reg : std_ulogic_vector(07 downto 0);
- signal com_config_reg : std_ulogic_vector(15 downto 0);
-
- -- spi transceiver --
- signal spi_in_buf : std_ulogic_vector(01 downto 0);
- signal spi_mosi_nxt : std_ulogic;
- signal spi_sck_nxt : std_ulogic;
- signal spi_mosi_ff : std_ulogic;
- signal spi_cs_ff : std_ulogic_vector(07 downto 0);
- signal spi_cs_ff_nxt : std_ulogic_vector(07 downto 0);
- signal spi_irq : std_ulogic;
-
- -- spi arbiter --
- type spi_arb_state_type is (idle, start_trans, transmit_0, transmit_1, finish);
- signal spi_arb_state : spi_arb_state_type;
- signal spi_arb_state_nxt : spi_arb_state_type;
- signal spi_bit_cnt : std_ulogic_vector(04 downto 0);
- signal spi_bit_cnt_nxt : std_ulogic_vector(04 downto 0);
- signal spi_rx_sft : std_ulogic_vector(15 downto 0); -- rx shift registers
- signal spi_rx_sft_nxt : std_ulogic_vector(15 downto 0); -- rx shift registers
- signal spi_tx_sft : std_ulogic_vector(15 downto 0); -- tx shift registers
- signal spi_tx_sft_nxt : std_ulogic_vector(15 downto 0); -- tx shift registers
- signal spi_prsc_cnt : std_ulogic_vector(15 downto 0);
- signal spi_prsc_cnt_nxt : std_ulogic_vector(15 downto 0);
- signal spi_busy_flag : std_ulogic;
- signal spi_busy_flag_nxt : std_ulogic;
- signal spi_sck_ff : std_ulogic;
- signal spi_miso : std_ulogic;
-
- -- pio registers --
- signal pio_out_data : std_ulogic_vector(15 downto 0);
- signal pio_in_data : std_ulogic_vector(15 downto 0);
- signal pio_sync : std_ulogic_vector(15 downto 0);
- signal sys_io_i_ff : std_ulogic_vector(07 downto 0);
- signal sys_io_o_ff : std_ulogic_vector(07 downto 0);
-
-begin
-
- -- Write Access ----------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- w_acc: process(clk_i)
- begin
- if rising_edge(clk_i) then
- if (rst_i = '1') then
- uart_prsc_reg <= (others => '0');
- com_config_reg <= (others => '0');
- spi_tx_reg <= (others => '0');
- spi_cs_reg <= (others => '0');
- pio_in_data <= (others => '0');
- pio_out_data <= (others => '0');
- pio_sync <= (others => '0');
- sys_io_o_ff <= (others => '0');
- sys_io_i_ff <= (others => '0');
- elsif (ice_i = '1') then -- interface enable
- if (w_en_i = '1') then -- register update
- case (adr_i) is
- when uart_prsc_reg_c => uart_prsc_reg <= dat_i;
- when com_ctrl_reg_c => com_config_reg <= dat_i;
- when spi_data_reg_c => spi_tx_reg <= dat_i;
- when spi_cs_reg_c => spi_cs_reg <= dat_i(07 downto 00);
- when pio_out_reg_c => pio_out_data <= dat_i;
- when sys_io_reg_c => sys_io_o_ff <= dat_i(15 downto 08);
- when others => null;
- end case;
- end if;
- end if;
- pio_sync <= pio_in_data;
- pio_in_data <= pio_in_i; -- pio input
- sys_io_i_ff <= sys_io_i;
- end if;
- end process w_acc;
-
- -- output --
- pio_out_o <= pio_out_data;
- sys_io_o <= sys_io_o_ff;
-
- -- pio input pin change irq --
- pio_irq_o <= '0' when (pio_sync = pio_in_data) else '1';
-
-
- -- Read Access -----------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- r_acc: process(adr_i, uart_tx_bsy_flag, uart_rx_ready, uart_rx_reg, uart_prsc_reg, com_config_reg, sys_io_o_ff,
- spi_busy_flag, spi_cs_reg, spi_rx_reg, pio_out_data, pio_in_data, sys_io_i_ff, uart_dcor_flag)
- begin
- case (adr_i) is
- when uart_rtx_sd_reg_c => dat_o <= (others => '0');
- dat_o(7 downto 0) <= uart_rx_reg;
- dat_o(uart_rx_ready_c) <= uart_rx_ready;
- when uart_prsc_reg_c => dat_o <= uart_prsc_reg;
- when com_ctrl_reg_c => dat_o <= com_config_reg;
- dat_o(spi_cr_bsy_c) <= spi_busy_flag;
- dat_o(uart_tx_busy_c) <= uart_tx_bsy_flag;
- dat_o(uart_ry_ovf_c) <= uart_dcor_flag;
- when spi_data_reg_c => dat_o <= spi_rx_reg;
- when spi_cs_reg_c => dat_o <= x"00" & spi_cs_reg;
- when pio_in_reg_c => dat_o <= pio_in_data;
- when pio_out_reg_c => dat_o <= pio_out_data;
- when sys_io_reg_c => dat_o <= sys_io_o_ff & sys_io_i_ff;
- when others => dat_o <= x"0000";
- end case;
- end process r_acc;
-
-
- -- UART Flag Arbiter -----------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- uart_flag_ctrl: process(clk_i)
- begin
- if rising_edge(clk_i) then
- if (rst_i = '1') then
- uart_rx_ready <= '0';
- uart_rx_ready_sync <= '0';
- uart_dcor_flag <= '0';
- else
- -- ready flag and corruption flag --
- uart_rx_ready_sync <= uart_rx_bsy_flag;
- if (uart_rx_ready = '1') and (r_en_i = '1') and (adr_i = uart_rtx_sd_reg_c) and (ice_i = '1') then
- uart_rx_ready <= '0';
- uart_dcor_flag <= '0';
- elsif (uart_rx_ready_sync = '1') and (uart_rx_bsy_flag = '0') then -- falling edge
- uart_rx_ready <= '1';
- uart_dcor_flag <= uart_rx_ready;
- end if;
- end if;
- end if;
- end process uart_flag_ctrl;
-
- -- interrupt output --
- uart_rx_irq_o <= uart_rx_ready;
- uart_tx_irq_o <= not uart_tx_bsy_flag;
-
-
- -- Transmitter Unit ------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- uart_transmitter: process(clk_i)
- begin
- if rising_edge(clk_i) then
- if (rst_i = '1') then
- uart_tx_bsy_flag <= '0';
- uart_tx_sreg <= (others => '1');
- uart_tx_bit_cnt <= (others => '0');
- uart_tx_baud_cnt <= (others => '0');
- else
- -- uart disabled
- if (com_config_reg(uart_en_c) = '0') then
- uart_tx_bsy_flag <= '0';
- uart_tx_sreg <= (others => '1');
- uart_tx_bit_cnt <= (others => '0');
- uart_tx_baud_cnt <= (others => '0');
-
- -- uart tx register --
- elsif (uart_tx_bsy_flag = '0') then
- uart_tx_bit_cnt <= "1010"; -- 10 bits
- uart_tx_baud_cnt <= uart_prsc_reg;
- if (w_en_i = '1') and (adr_i = uart_rtx_sd_reg_c) then
- uart_tx_bsy_flag <= '1';
- uart_tx_sreg <= '1' & dat_i(7 downto 0) & '0'; -- stopbit & data & startbit
- end if;
- else
- if (uart_tx_baud_cnt = x"0000") then
- uart_tx_baud_cnt <= uart_prsc_reg;
- if (uart_tx_bit_cnt /= "0000") then
- uart_tx_sreg <= '1' & uart_tx_sreg(9 downto 1);
- uart_tx_bit_cnt <= std_ulogic_vector(unsigned(uart_tx_bit_cnt) - 1);
- else
- uart_tx_bsy_flag <= '0'; -- done
- end if;
- else
- uart_tx_baud_cnt <= std_ulogic_vector(unsigned(uart_tx_baud_cnt) - 1);
- end if;
- end if;
- end if;
- end if;
- end process uart_transmitter;
-
- -- transmitter output --
- uart_txd_o <= uart_tx_sreg(0);
-
-
- -- UART Receiver Unit ----------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- uart_receiver: process(clk_i)
- begin
- if rising_edge(clk_i) then
- if (rst_i = '1') then
- uart_rx_bsy_flag <= '0';
- uart_rx_sreg <= (others => '0');
- uart_rx_bit_cnt <= (others => '0');
- uart_rx_baud_cnt <= (others => '0');
- uart_rx_sync <= (others => '1');
- uart_rx_reg <= (others => '0');
- else
- -- synchronizer --
- if (com_config_reg(uart_en_c) = '1') then
- uart_rx_sync <= uart_rxd_i & uart_rx_sync(3 downto 1);
- end if;
-
- -- uart disabled --
- if (com_config_reg(uart_en_c) = '0') then
- uart_rx_bsy_flag <= '0';
- uart_rx_sreg <= (others => '0');
- uart_rx_bit_cnt <= (others => '0');
- uart_rx_baud_cnt <= (others => '0');
- uart_rx_sync <= (others => '1');
- uart_rx_reg <= (others => '0');
-
- -- rx shift reg --
- elsif (uart_rx_bsy_flag = '0') then
- uart_rx_bit_cnt <= "1001"; -- 9 bits (startbit + 8 data bits)
- uart_rx_baud_cnt <= '0' & uart_prsc_reg(15 downto 1); -- half baud rate, sample in middle
- if (uart_rx_sync(1 downto 0) = "01") then -- start 'bit' detected (falling logical edge)
- uart_rx_bsy_flag <= '1';
- end if;
- else
- if (uart_rx_baud_cnt = x"0000") then
- uart_rx_baud_cnt <= uart_prsc_reg;
- if (uart_rx_bit_cnt /= "0000") then
- uart_rx_sreg <= uart_rx_sync(0) & uart_rx_sreg(9 downto 1);
- uart_rx_bit_cnt <= std_ulogic_vector(unsigned(uart_rx_bit_cnt) - 1);
- else
- uart_rx_bsy_flag <= '0'; -- done
- uart_rx_reg <= uart_rx_sreg(9 downto 2);
- end if;
- else
- uart_rx_baud_cnt <= std_ulogic_vector(unsigned(uart_rx_baud_cnt) - 1);
- end if;
- end if;
- end if;
- end if;
- end process uart_receiver;
-
-
- -- SPI Transceiver Unit --------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- spi_arb_sync: process(clk_i)
- begin
- if rising_edge(clk_i) then
- if (rst_i = '1') then
- spi_arb_state <= idle;
- spi_rx_sft <= (others => '0');
- spi_tx_sft <= (others => '0');
- spi_bit_cnt <= (others => '0');
- spi_prsc_cnt <= (others => '0');
- spi_rx_reg <= (others => '0');
- spi_sck_ff <= '0';
- spi_mosi_ff <= '0';
- spi_in_buf <= "00";
- spi_cs_ff <= (others => '1');
- spi_busy_flag <= '0';
- spi_irq_o <= '0';
- else
- spi_arb_state <= spi_arb_state_nxt;
- spi_rx_sft <= spi_rx_sft_nxt;
- spi_tx_sft <= spi_tx_sft_nxt;
- spi_bit_cnt <= spi_bit_cnt_nxt;
- spi_prsc_cnt <= spi_prsc_cnt_nxt;
- spi_rx_reg <= spi_rx_reg_nxt;
- spi_sck_ff <= spi_sck_nxt;
- spi_mosi_ff <= spi_mosi_nxt;
- spi_in_buf <= spi_in_buf(0) & spi_miso;
- if (com_config_reg(spi_cr_auto_cs_c) = '1') then -- auto apply chip select
- spi_cs_ff <= spi_cs_ff_nxt;
- else -- manually apply chip select
- spi_cs_ff <= not spi_cs_reg;
- end if;
- spi_busy_flag <= spi_busy_flag_nxt;
- spi_irq_o <= spi_irq;
- end if;
- end if;
- end process spi_arb_sync;
-
-
- spi_arb_comb: process(spi_arb_state, com_config_reg, spi_rx_sft, spi_tx_sft, spi_bit_cnt, spi_prsc_cnt, spi_in_buf,
- spi_rx_reg, spi_mosi_ff, spi_cs_ff, spi_cs_reg, spi_tx_reg, w_en_i, adr_i, spi_busy_flag, ice_i)
- variable prsc_match_v : std_ulogic;
- begin
- -- defaults --
- spi_arb_state_nxt <= spi_arb_state; -- arbiter state
- spi_rx_sft_nxt <= spi_rx_sft; -- rx shift register
- spi_tx_sft_nxt <= spi_tx_sft; -- tx shift register
- spi_bit_cnt_nxt <= spi_bit_cnt; -- bit counter
- spi_prsc_cnt_nxt <= spi_prsc_cnt; -- spi clock prescaler
- spi_rx_reg_nxt <= spi_rx_reg; -- complete received data
- spi_sck_nxt <= com_config_reg(spi_cr_cpol_c); -- clock polarity
- spi_mosi_nxt <= spi_mosi_ff; -- serial data output
- spi_busy_flag_nxt <= spi_busy_flag; -- busy flag
- spi_irq <= '0'; -- no interrupt
- prsc_match_v := spi_prsc_cnt(to_integer(unsigned(com_config_reg(spi_cr_prsc_msb_c downto spi_cr_prsc_lsb_c)))); -- prescaler match
-
- -- state machine --
- case (spi_arb_state) is -- idle, start_trans, transmit, end_trans
-
- when idle => -- wait for transmitter init
- spi_cs_ff_nxt <= (others => '1'); -- deselct all slaves
- spi_bit_cnt_nxt <= (others => '0');
- spi_rx_sft_nxt <= (others => '0');
- spi_prsc_cnt_nxt <= (others => '0');
- spi_mosi_nxt <= '0';
- spi_sck_nxt <= com_config_reg(spi_cr_cpol_c); -- idle clk polarity
- if (w_en_i = '1') and (adr_i = spi_data_reg_c) and (ice_i = '1') then
- spi_arb_state_nxt <= start_trans;
- spi_busy_flag_nxt <= '1';
- end if;
-
- when start_trans => -- apply slave select signal
- spi_tx_sft_nxt <= spi_tx_reg;
- spi_cs_ff_nxt <= not spi_cs_reg;
- spi_arb_state_nxt <= transmit_0;
-
- when transmit_0 => -- first half of bit transmission
- spi_cs_ff_nxt <= spi_cs_ff; -- keep cs alive
- spi_prsc_cnt_nxt <= std_ulogic_vector(unsigned(spi_prsc_cnt) + 1);
- spi_sck_nxt <= com_config_reg(spi_cr_cpol_c) xor com_config_reg(spi_cr_cpha_c);
- if (com_config_reg(spi_cr_dir_flag_c) = '0') then -- msb first
- spi_mosi_nxt <= spi_tx_sft(to_integer(unsigned(com_config_reg(spi_cr_ln_msb_c downto spi_cr_ln_lsb_c))));
- else -- lsb first
- spi_mosi_nxt <= spi_tx_sft(0);
- end if;
- if (prsc_match_v = '1') then -- first half completed
- spi_arb_state_nxt <= transmit_1;
- spi_prsc_cnt_nxt <= (others => '0');
- end if;
-
- when transmit_1 => -- second half of bit transmission
- spi_cs_ff_nxt <= spi_cs_ff; -- keep cs alive
- spi_prsc_cnt_nxt <= std_ulogic_vector(unsigned(spi_prsc_cnt) + 1);
- spi_sck_nxt <= not (com_config_reg(spi_cr_cpol_c) xor com_config_reg(spi_cr_cpha_c));
- if (prsc_match_v = '1') then -- second half completed
- spi_bit_cnt_nxt <= std_ulogic_vector(unsigned(spi_bit_cnt) + 1);
- spi_prsc_cnt_nxt <= (others => '0');
- if (com_config_reg(spi_cr_dir_flag_c) = '0') then -- msb first
- spi_tx_sft_nxt <= spi_tx_sft(14 downto 0) & '0'; -- left shift
- spi_rx_sft_nxt <= spi_rx_sft(14 downto 0) & spi_in_buf(1); -- left shift
- else -- lsb first
- spi_tx_sft_nxt <= '0' & spi_tx_sft(15 downto 1); -- right shift
- spi_rx_sft_nxt <= spi_in_buf(1) & spi_tx_sft(15 downto 1); -- right shift
- end if;
- if (to_integer(unsigned(spi_bit_cnt)) = to_integer(unsigned(com_config_reg(spi_cr_ln_msb_c downto spi_cr_ln_lsb_c)))) then
- spi_arb_state_nxt <= finish;
- else
- spi_arb_state_nxt <= transmit_0;
- end if;
- end if;
-
- when finish => -- finish transfer
- spi_cs_ff_nxt <= spi_cs_ff; -- keep cs alive
- spi_busy_flag_nxt <= '0';
- spi_rx_reg_nxt <= spi_rx_sft;
- spi_mosi_nxt <= '0';
- spi_irq <= '1'; -- irq tick
- spi_arb_state_nxt <= idle;
-
- end case;
- end process spi_arb_comb;
-
-
- -- spi io interface --
- spi_io: process(spi_cs_ff, spi_mosi_ff, spi_sck_ff, spi_miso_i)
- variable spi_miso_bus_v : std_ulogic_vector(7 downto 0);
- variable spi_miso_v : std_ulogic;
- begin
- spi_miso_bus_v := spi_miso_i and (not spi_cs_ff);
- spi_miso_v := '0';
- for i in 0 to 7 loop -- for all channels
- spi_mosi_o(i) <= spi_mosi_ff and (not spi_cs_ff(i));
- spi_cs_o(i) <= spi_cs_ff(i);
- spi_sck_o(i) <= spi_sck_ff;
- spi_miso_v := spi_miso_v or spi_miso_bus_v(i);
- end loop;
- spi_miso <= spi_miso_v;
- end process spi_io;
-
-
-
-end com_0_core_behav;
Index: rtl/SYS_0_CORE.vhd
===================================================================
--- rtl/SYS_0_CORE.vhd (revision 37)
+++ rtl/SYS_0_CORE.vhd (nonexistent)
@@ -1,281 +0,0 @@
--- #########################################################
--- # << ATLAS Project - System Controller 0 >> #
--- # ***************************************************** #
--- # -> Interrupt Controller (8 channels) #
--- # -> High Precision Timer (16+16 bit) #
--- # -> Linear-Feedback Shift Register (16 bit) #
--- # ***************************************************** #
--- # Last modified: 28.11.2014 #
--- # ***************************************************** #
--- # by Stephan Nolting 4788, Hanover, Germany #
--- #########################################################
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.atlas_core_package.all;
-
-entity sys_0_core is
- port (
--- ###############################################################################################
--- ## Host Interface ##
--- ###############################################################################################
-
- clk_i : in std_ulogic; -- global clock line
- rst_i : in std_ulogic; -- global reset line, sync, high-active
- ice_i : in std_ulogic; -- interface clock enable, high-active
- w_en_i : in std_ulogic; -- write enable
- r_en_i : in std_ulogic; -- read enable
- adr_i : in std_ulogic_vector(02 downto 0); -- access address
- dat_i : in std_ulogic_vector(15 downto 0); -- write data
- dat_o : out std_ulogic_vector(15 downto 0); -- read data
-
--- ###############################################################################################
--- ## Interrupt Lines ##
--- ###############################################################################################
-
- timer_irq_o : out std_ulogic; -- timer irq
- irq_i : in std_ulogic_vector(07 downto 0); -- irq input
- irq_o : out std_ulogic -- interrupt request
- );
-end sys_0_core;
-
-architecture sys_0_core_behav of sys_0_core is
-
- -- Module Addresses --
- constant irq_sm_reg_c : std_ulogic_vector(02 downto 0) := "000"; -- R/W: Interrupt source and mask
- constant irq_conf_reg_c : std_ulogic_vector(02 downto 0) := "001"; -- R/W: Interrupt type configuration
- -- lo byte: '1': level triggered, '0': edge triggered
- -- hi byte: '1': high level/rising edge, '0': low level/falling edge
- constant timer_cnt_reg_c : std_ulogic_vector(02 downto 0) := "010"; -- R/W: Timer counter register
- constant timer_thr_reg_c : std_ulogic_vector(02 downto 0) := "011"; -- R/W: Timer threshold register
- constant timer_prsc_reg_c : std_ulogic_vector(02 downto 0) := "100"; -- R/W: Timer prescaler register
- constant lfsr_data_reg_c : std_ulogic_vector(02 downto 0) := "101"; -- R/W: LFSR data register
- constant lfsr_poly_reg_c : std_ulogic_vector(02 downto 0) := "110"; -- R/W: LFSR polynomial register
- -- bit 15: '0' new value after read access, '1' free running mode
- constant reserved_reg_c : std_ulogic_vector(02 downto 0) := "111"; -- RESERVED
-
- -- IRQ Registers --
- signal irq_mask_reg : std_ulogic_vector(07 downto 0);
- signal irq_source_reg : std_ulogic_vector(02 downto 0);
- signal irq_conf_reg : std_ulogic_vector(15 downto 0);
-
- -- Internals --
- signal irq_sync_0 : std_ulogic_vector(07 downto 0);
- signal irq_sync_1 : std_ulogic_vector(07 downto 0);
- signal irq_raw_req : std_ulogic_vector(07 downto 0);
- signal irq_buf : std_ulogic_vector(07 downto 0);
- signal irq_id : std_ulogic_vector(02 downto 0);
- signal irq_ack_mask : std_ulogic_vector(07 downto 0);
- signal irq_ack_mask_ff : std_ulogic_vector(07 downto 0);
- signal irq_lock : std_ulogic;
-
- -- Timer Registers --
- signal tmr_cnt_reg : std_ulogic_vector(15 downto 0);
- signal tmr_thr_reg : std_ulogic_vector(15 downto 0);
- signal tmr_prsc_reg : std_ulogic_vector(15 downto 0);
- signal tmr_prsc_cnt : std_ulogic_vector(15 downto 0);
-
- -- Timer Signals --
- signal tmr_prsc_match : std_ulogic;
- signal tmr_thres_zero : std_ulogic;
-
- -- LFSR Registers --
- signal lfsr_data : std_ulogic_vector(15 downto 0);
- signal lfsr_poly : std_ulogic_vector(15 downto 0);
- signal lfsr_new : std_ulogic_vector(15 downto 0);
- signal lfsr_noise : std_ulogic;
-
-begin
-
- -- Write Access ----------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- w_acc: process(clk_i)
- begin
- if rising_edge(clk_i) then
- if (rst_i = '1') then
- irq_mask_reg <= (others => '0');
- irq_conf_reg <= (others => '0');
- tmr_cnt_reg <= (others => '0');
- tmr_thr_reg <= (others => '0');
- tmr_prsc_reg <= (others => '0');
- tmr_prsc_cnt <= (others => '0');
- lfsr_data <= (others => '0');
- lfsr_poly <= (others => '0');
- irq_sync_0 <= (others => '0');
- irq_sync_1 <= (others => '0');
- else
- -- irq ctrl write access --
- if (w_en_i = '1') and (ice_i = '1') and ((adr_i = irq_sm_reg_c) or (adr_i = irq_conf_reg_c)) then
- if (adr_i = irq_sm_reg_c) then
- irq_mask_reg <= dat_i(15 downto 08);
- else -- (adr_i = irq_conf_reg_c)
- irq_conf_reg <= dat_i;
- end if;
- end if;
- irq_sync_1 <= irq_sync_0;
- irq_sync_0 <= irq_i;
-
- -- timer write access --
- if (w_en_i = '1') and (ice_i = '1') and ((adr_i = timer_cnt_reg_c) or (adr_i = timer_thr_reg_c) or (adr_i = timer_prsc_reg_c)) then
- tmr_prsc_cnt <= (others => '0');
- if (adr_i = timer_cnt_reg_c) then
- tmr_cnt_reg <= dat_i;
- elsif (adr_i = timer_thr_reg_c) then
- tmr_thr_reg <= dat_i;
- else -- (adr_i = timer_prsc_reg_c)
- tmr_prsc_reg <= dat_i;
- end if;
- else -- auto update
- if (tmr_prsc_match = '1') or (tmr_thres_zero = '1') then -- prescaler increment
- tmr_prsc_cnt <= (others => '0');
- else
- tmr_prsc_cnt <= std_ulogic_vector(unsigned(tmr_prsc_cnt) + 1);
- end if;
- if (tmr_cnt_reg = tmr_thr_reg) then -- counter increment
- tmr_cnt_reg <= (others => '0');
- elsif (tmr_thres_zero = '0') and (tmr_prsc_match = '1') then
- tmr_cnt_reg <= std_ulogic_vector(unsigned(tmr_cnt_reg) + 1);
- end if;
- end if;
-
- -- lfsr write access --
- if (w_en_i = '1') and (ice_i = '1') and ((adr_i = lfsr_data_reg_c) or (adr_i = lfsr_poly_reg_c)) then
- if (adr_i = lfsr_data_reg_c) then
- lfsr_data <= dat_i;
- else -- (adr_i = lfsr_poly_reg_c)
- lfsr_poly <= dat_i;
- end if;
- else -- auto update
- if (lfsr_poly(15) = '0') then -- access-update?
- if (r_en_i = '1') and (adr_i = lfsr_data_reg_c) and (ice_i = '1') then
- lfsr_data <= lfsr_new;
- end if;
- else -- free-running mode
- lfsr_data <= lfsr_new;
- end if;
- end if;
- end if;
- end if;
- end process w_acc;
-
- -- timer prescaler match --
- tmr_prsc_match <= '1' when (tmr_prsc_cnt = tmr_prsc_reg) else '0';
-
- -- timer threshold zero test --
- tmr_thres_zero <= '1' when (tmr_thr_reg = x"0000") else '0';
-
- -- timer irq --
- timer_irq_o <= '1' when ((tmr_cnt_reg = tmr_thr_reg) and (tmr_thres_zero = '0')) else '0';
-
-
- -- Read Access -----------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- r_acc: process(adr_i, irq_mask_reg, irq_conf_reg, irq_source_reg, tmr_cnt_reg, tmr_thr_reg,
- tmr_prsc_reg, lfsr_data, lfsr_poly)
- begin
- case (adr_i) is
- when irq_sm_reg_c => dat_o <= irq_mask_reg & "00000" & irq_source_reg;
- when irq_conf_reg_c => dat_o <= irq_conf_reg;
- when timer_cnt_reg_c => dat_o <= tmr_cnt_reg;
- when timer_thr_reg_c => dat_o <= tmr_thr_reg;
- when timer_prsc_reg_c => dat_o <= tmr_prsc_reg;
- when lfsr_data_reg_c => dat_o <= lfsr_data;
- when lfsr_poly_reg_c => dat_o <= lfsr_poly;
- when others => dat_o <= (others => '0');
- end case;
- end process r_acc;
-
-
- -- Interrupt Detector ----------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- irq_detector: process(irq_mask_reg, irq_conf_reg, irq_sync_0, irq_sync_1)
- begin
- -- edge/level detector --
- irq_raw_req <= (others => '0');
- for i in 0 to 7 loop
- if (irq_mask_reg(i) = '1') then -- channel enabled
- if (irq_conf_reg(i) = '1') then -- level triggered
- irq_raw_req(i) <= irq_conf_reg(i+8) xnor irq_sync_0(i);
- else -- edge triggered
- if (irq_conf_reg(i+8) = '1') then -- rising edge
- irq_raw_req(i) <= irq_sync_0(i) and (not irq_sync_1(i));
- else -- falling edge
- irq_raw_req(i) <= (not irq_sync_0(i)) and irq_sync_1(i);
- end if;
- end if;
- end if;
- end loop;
- end process irq_detector;
-
-
- -- Interrupt Request Buffer ----------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- irq_buffer: process(clk_i)
- begin
- if rising_edge(clk_i) then
- if (rst_i = '1') then
- irq_buf <= (others => '0');
- irq_source_reg <= (others => '0');
- irq_ack_mask_ff <= (others => '0');
- irq_lock <= '0';
- else
- if (irq_lock = '0') then -- store id and mask until ack
- irq_ack_mask_ff <= irq_ack_mask;
- irq_source_reg <= irq_id;
- end if;
- if (r_en_i = '1') and (adr_i = irq_sm_reg_c) then -- ack on source reg read
- irq_buf <= (irq_buf or irq_raw_req) and (not irq_ack_mask_ff);
- irq_lock <= '0'; -- ack: remove lock
- else
- irq_buf <= irq_buf or irq_raw_req;
- if (irq_buf /= x"00") then
- irq_lock <= '1';
- end if;
- end if;
- end if;
- end if;
- end process irq_buffer;
-
- -- irq signal to host --
- irq_o <= irq_lock;
-
-
- -- Interrupt Priority Encoder --------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- irq_pr_enc: process(irq_buf)
- begin
- irq_id <= (others => '0');
- irq_ack_mask <= (others => '0');
- for i in 0 to 7 loop
- if (irq_buf(i) = '1') then
- irq_id <= std_ulogic_vector(to_unsigned(i,3));
- irq_ack_mask(i) <= '1';
- exit;
- end if;
- end loop;
- end process irq_pr_enc;
-
-
- -- LFSR Update -----------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- lfsr_update: process(lfsr_data, lfsr_poly, lfsr_noise)
- begin
- for i in 0 to 14 loop
- if (lfsr_poly(i) = '1') then
- lfsr_new(i) <= lfsr_data(i+1) xor lfsr_data(0);
- else
- lfsr_new(i) <= lfsr_data(i+1);
- end if;
- end loop;
- lfsr_new(15) <= lfsr_data(0) xor lfsr_noise;
- end process lfsr_update;
-
- -- external noise input --
- lfsr_noise <= '0'; -- not used yet
-
-
-
-end sys_0_core_behav;
Index: rtl/ATLAS_pkg.vhd
===================================================================
--- rtl/ATLAS_pkg.vhd (revision 37)
+++ rtl/ATLAS_pkg.vhd (nonexistent)
@@ -1,816 +0,0 @@
--- ########################################################
--- # << ATLAS Project - Project Package >> #
--- # **************************************************** #
--- # All architecture configurations, options, signal #
--- # definitions and components are listed here. #
--- # **************************************************** #
--- # Last modified: 28.11.2014 #
--- # **************************************************** #
--- # by Stephan Nolting 4788, Hanover, Germany #
--- ########################################################
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-package atlas_core_package is
-
--- Architecture Configuration for Application ---------------------------------------------
--- -------------------------------------------------------------------------------------------
- constant big_endian_c : boolean := true; -- use little/big endian memory system
- constant build_mul_c : boolean := true; -- build a dedicated MUL unit
- constant build_mul32_c : boolean := true; -- build 32-bit multiplier
- constant word_mode_en_c : boolean := false; -- use word-addressed memory system instead of byte-addressed
- constant signed_mul_c : boolean := true; -- synthesize signed or unsigned multiplier core
- constant wb_fifo_size_c : natural := 32; -- Wishbone fifo size in words (power of 2!)
-
- ---- DO NOT CHANGE ANYTHING BELOW UNLESS YOU REALLY KNOW WHAT YOU ARE DOING! ----
-
--- Architecture Constants -----------------------------------------------------------------
--- -------------------------------------------------------------------------------------------
- constant data_width_c : natural := 16; -- processing data width
- constant data_bytes_c : natural := data_width_c/8; -- processing data width in bytes
- constant align_lsb_c : natural := data_bytes_c/2; -- lsb of adr word boundary
- constant link_reg_adr_c : std_ulogic_vector(02 downto 0) := "111"; -- link reg for calls
- constant stack_pnt_adr_c : std_ulogic_vector(02 downto 0) := "110"; -- stack pointer
- constant boot_page_c : std_ulogic_vector(15 downto 0) := x"8000"; -- boot pages begin
- constant boot_adr_c : std_ulogic_vector(15 downto 0) := x"0000"; -- boot address
- constant start_page_c : std_ulogic_vector(15 downto 0) := boot_page_c; -- start page
- constant start_adr_c : std_ulogic_vector(15 downto 0) := boot_adr_c; -- start address
- constant user_mode_c : std_ulogic := '0'; -- user mode indicator
- constant system_mode_c : std_ulogic := '1'; -- system mode indicator
- constant branch_slots_en_c : boolean := false; -- use branch delay slots (highly experimental!!!)
- constant ldil_sign_ext_c : boolean := true; -- use sign extension when loading low byte
- constant reg_branches_en_c : boolean := true; -- synthesize register-based branches
- constant cond_moves_en_c : boolean := true; -- synthesize conditional moves
-
-
--- Interrupt/Exception Vectors (word-address) ---------------------------------------------
--- -------------------------------------------------------------------------------------------
- constant res_int_vec_c : std_ulogic_vector(15 downto 0) := x"0000"; -- use boot address instead!
- constant irq0_int_vec_c : std_ulogic_vector(15 downto 0) := x"0001"; -- external int line 0 IRQ
- constant irq1_int_vec_c : std_ulogic_vector(15 downto 0) := x"0002"; -- external int line 1 IRQ
- constant cmd_err_int_vec_c : std_ulogic_vector(15 downto 0) := x"0003"; -- instruction/access error
- constant swi_int_vec_c : std_ulogic_vector(15 downto 0) := x"0004"; -- software IRQ
-
-
--- Wishbone Bus Constants -----------------------------------------------------------------
--- -------------------------------------------------------------------------------------------
- constant wb_classic_cyc_c : std_ulogic_vector(2 downto 0) := "000"; -- classic cycle
- constant wb_con_bst_cyc_c : std_ulogic_vector(2 downto 0) := "001"; -- constant address burst
- constant wb_inc_bst_cyc_c : std_ulogic_vector(2 downto 0) := "010"; -- incrementing address burst
- constant wb_end_bst_cyc_c : std_ulogic_vector(2 downto 0) := "111"; -- burst end
-
-
--- Machine Status Register ----------------------------------------------------------------
--- -------------------------------------------------------------------------------------------
- constant msr_usr_z_flag_c : natural := 0; -- user mode zero flag
- constant msr_usr_c_flag_c : natural := 1; -- user mode carry flag
- constant msr_usr_o_flag_c : natural := 2; -- user mode overflow flag
- constant msr_usr_n_flag_c : natural := 3; -- user mode negative flag
- constant msr_usr_t_flag_c : natural := 4; -- user mode transfer flag
- constant msr_sys_z_flag_c : natural := 5; -- system mode zero flag
- constant msr_sys_c_flag_c : natural := 6; -- system mode carry flag
- constant msr_sys_o_flag_c : natural := 7; -- system mode overflow flag
- constant msr_sys_n_flag_c : natural := 8; -- system mode negative flag
- constant msr_sys_t_flag_c : natural := 9; -- system mode transfer flag
- constant msr_usr_cp_ptc_c : natural := 10; -- user coprocessor protection
- constant msr_xint_en_c : natural := 11; -- enable external interrupts (global)
- constant msr_xint0_en_c : natural := 12; -- enable external interrupt 0
- constant msr_xint1_en_c : natural := 13; -- enable external interrupt 1
- constant msr_svd_mode_c : natural := 14; -- saved operating mode
- constant msr_mode_flag_c : natural := 15; -- system ('1') / user ('0') mode
-
-
--- Forwarding Bus -------------------------------------------------------------------------
--- -------------------------------------------------------------------------------------------
- constant fwd_en_c : natural := 0; -- valid register signal
- constant fwd_adr_0_c : natural := 1; -- address bit 0
- constant fwd_adr_1_c : natural := 2; -- address bit 1
- constant fwd_adr_2_c : natural := 3; -- address bit 2
- constant fwd_adr_3_c : natural := 4; -- address bit 3 (bank select)
- constant fwd_dat_lsb_c : natural := 5; -- forwarding data lsb
- constant fwd_dat_msb_c : natural := 5+data_width_c-1; -- forwarding data msb
- constant fwd_width_c : natural := 5+data_width_c; -- size of forwarding bus
-
-
--- Flag Bus -------------------------------------------------------------------------------
--- -------------------------------------------------------------------------------------------
- constant flag_z_c : natural := 0; -- user mode zero flag
- constant flag_c_c : natural := 1; -- user mode carry flag
- constant flag_o_c : natural := 2; -- user mode overflow flag
- constant flag_n_c : natural := 3; -- user mode negative flag
- constant flag_t_c : natural := 4; -- user mode transfer flag
- constant flag_bus_width_c : natural := 5; -- size of flag bus
-
-
--- Main Control Bus -----------------------------------------------------------------------
--- -------------------------------------------------------------------------------------------
- -- Global Control --
- constant ctrl_en_c : natural := 0; -- valid cycle
- constant ctrl_mcyc_c : natural := 1; -- un-interruptable/atomic operation
-
- -- Operand A Register --
- constant ctrl_ra_is_pc_c : natural := 2; -- operand register A is the PC
- constant ctrl_clr_ha_c : natural := 3; -- set higher half word of A to 0 (@ 16 bit)
- constant ctrl_clr_la_c : natural := 4; -- set lower half word of A to 0 (@ 16 bit)
- constant ctrl_ra_0_c : natural := 5; -- operand register A adr bit 0
- constant ctrl_ra_1_c : natural := 6; -- operand register A adr bit 1
- constant ctrl_ra_2_c : natural := 7; -- operand register A adr bit 2
- constant ctrl_ra_3_c : natural := 8; -- operand register A adr bit 3 (bank select)
-
- -- Operand B Register --
- constant ctrl_rb_is_imm_c : natural := 9; -- operand register B is an immediate
- constant ctrl_rb_0_c : natural := 10; -- operand register B adr bit 0
- constant ctrl_rb_1_c : natural := 11; -- operand register B adr bit 1
- constant ctrl_rb_2_c : natural := 12; -- operand register B adr bit 2
- constant ctrl_rb_3_c : natural := 13; -- operand register B adr bit 3 (bank select)
-
- -- Destiantion Register --
- constant ctrl_rd_wb_c : natural := 14; -- register write back request
- constant ctrl_rd_0_c : natural := 15; -- register destination adr bit 0
- constant ctrl_rd_1_c : natural := 16; -- register destination adr bit 1
- constant ctrl_rd_2_c : natural := 17; -- register destination adr bit 2
- constant ctrl_rd_3_c : natural := 18; -- register destination adr bit 3 (bank select)
-
- -- ALU Control --
- constant ctrl_alu_fs_0_c : natural := 19; -- alu function set bit 0
- constant ctrl_alu_fs_1_c : natural := 20; -- alu function set bit 1
- constant ctrl_alu_fs_2_c : natural := 21; -- alu function set bit 2
- constant ctrl_alu_usec_c : natural := 22; -- alu use MSR(carry_flag)
- constant ctrl_alu_usez_c : natural := 23; -- alu use MSR(zero_flag)
- constant ctrl_fupdate_c : natural := 24; -- msr flag update enable
- constant ctrl_alu_cf_opt_c : natural := 25; -- option for carry in (normal/invert)
- constant ctrl_alu_zf_opt_c : natural := 26; -- option for zero in (AND/OR)
-
- -- Bit Manipulation --
- constant ctrl_tf_store_c : natural := 27; -- store bit to t-flag
- constant ctrl_tf_inv_c : natural := 28; -- invert bit to be store in t-flag
- constant ctrl_get_par_c : natural := 29; -- get parity bit
-
- -- Coprocessor Access --
- constant ctrl_cp_acc_c : natural := 30; -- coprocessor operation
- constant ctrl_cp_trans_c : natural := 31; -- coprocessor data transfer
- constant ctrl_cp_wr_c : natural := 32; -- write to coprocessor
- constant ctrl_cp_id_c : natural := 33; -- coprocessor id bit
-
- -- System Register Access --
- constant ctrl_msr_wr_c : natural := 34; -- write to mcr
- constant ctrl_msr_rd_c : natural := 35; -- read from mcr
- constant ctrl_pc_wr_c : natural := 36; -- write pc
-
- -- Branch/Context Control --
- constant ctrl_cond_0_c : natural := 37; -- condition code bit 0
- constant ctrl_cond_1_c : natural := 38; -- condition code bit 1
- constant ctrl_cond_2_c : natural := 39; -- condition code bit 2
- constant ctrl_cond_3_c : natural := 40; -- condition code bit 3
- constant ctrl_branch_c : natural := 41; -- is branch operation
- constant ctrl_link_c : natural := 42; -- store old pc to lr
- constant ctrl_syscall_c : natural := 43; -- is a system call
- constant ctrl_cmd_err_c : natural := 44; -- invalid/unauthorized operation
- constant ctrl_ctx_down_c : natural := 45; -- go to user mode
- constant ctrl_restsm_c : natural := 46; -- restore saved mode
-
- -- Memory Access --
- constant ctrl_mem_acc_c : natural := 47; -- request d-mem access
- constant ctrl_mem_wr_c : natural := 48; -- write to d-mem
- constant ctrl_mem_bpba_c : natural := 49; -- use bypassed base address
- constant ctrl_mem_daa_c : natural := 50; -- use delayed address
-
- -- Multiply Unit --
- constant ctrl_use_mul_c : natural := 51; -- use MUL unit
- constant ctrl_ext_mul_c : natural := 52; -- get high mul result
- constant ctrl_use_offs_c : natural := 53; -- use loaded offset
-
- -- Sleep command --
- constant ctrl_sleep_c : natural := 54; -- go to sleep
-
- -- Conditional write back --
- constant ctrl_cond_wb_c : natural := 55; -- is cond write back?
-
- -- Bus Size --
- constant ctrl_width_c : natural := 56; -- control bus size
-
- -- Progress Redefinitions --
- constant ctrl_wb_en_c : natural := ctrl_rd_wb_c; -- valid write back
- constant ctrl_rd_mem_acc_c : natural := ctrl_mem_acc_c; -- true mem_read
- constant ctrl_rd_cp_acc_c : natural := ctrl_cp_acc_c; -- true cp_read
- constant ctrl_cp_msr_rd_c : natural := ctrl_msr_rd_c; -- true cp or msr read access
- constant ctrl_cp_cmd_0_c : natural := ctrl_rb_0_c; -- coprocessor cmd bit 0
- constant ctrl_cp_cmd_1_c : natural := ctrl_rb_1_c; -- coprocessor cmd bit 1
- constant ctrl_cp_cmd_2_c : natural := ctrl_rb_2_c; -- coprocessor cmd bit 2
- constant ctrl_cp_ra_0_c : natural := ctrl_ra_0_c; -- coprocessor op A bit 0
- constant ctrl_cp_ra_1_c : natural := ctrl_ra_1_c; -- coprocessor op A bit 1
- constant ctrl_cp_ra_2_c : natural := ctrl_ra_2_c; -- coprocessor op A bit 2
- constant ctrl_cp_rd_0_c : natural := ctrl_rd_0_c; -- coprocessor op B / dest bit 0
- constant ctrl_cp_rd_1_c : natural := ctrl_rd_1_c; -- coprocessor op B / dest bit 1
- constant ctrl_cp_rd_2_c : natural := ctrl_rd_2_c; -- coprocessor op B / dest bit 2
- constant ctrl_re_xint_c : natural := ctrl_rb_1_c; -- re-enable ext interrupts (global)
- constant ctrl_msr_am_0_c : natural := ctrl_ra_1_c; -- MSR access mode bit 0
- constant ctrl_msr_am_1_c : natural := ctrl_ra_2_c; -- MSR access mode bit 1
-
-
--- Coprocessor Control Bus ----------------------------------------------------------------
--- -------------------------------------------------------------------------------------------
- constant cp_cmd_lsb_c : natural := 0; -- command word lsb
- constant cp_cmd_msb_c : natural := 2; -- command word msb
- constant cp_op_b_lsb_c : natural := 3; -- operand B address lsb
- constant cp_op_b_msb_c : natural := 5; -- operand B address msb
- constant cp_op_a_lsb_c : natural := 6; -- operand A / destination address lsb
- constant cp_op_a_msb_c : natural := 8; -- operand A / destination address msb
- constant cp_cmd_width_c : natural := 9; -- bus size
-
-
--- Condition Codes ------------------------------------------------------------------------
--- -------------------------------------------------------------------------------------------
- constant cond_eq_c : std_ulogic_vector(3 downto 0) := "0000"; -- equal
- constant cond_ne_c : std_ulogic_vector(3 downto 0) := "0001"; -- not equal
- constant cond_cs_c : std_ulogic_vector(3 downto 0) := "0010"; -- unsigned higher or same
- constant cond_cc_c : std_ulogic_vector(3 downto 0) := "0011"; -- unsigned lower
- constant cond_mi_c : std_ulogic_vector(3 downto 0) := "0100"; -- negative
- constant cond_pl_c : std_ulogic_vector(3 downto 0) := "0101"; -- positive or zero
- constant cond_os_c : std_ulogic_vector(3 downto 0) := "0110"; -- overflow
- constant cond_oc_c : std_ulogic_vector(3 downto 0) := "0111"; -- no overflow
- constant cond_hi_c : std_ulogic_vector(3 downto 0) := "1000"; -- unsigned higher
- constant cond_ls_c : std_ulogic_vector(3 downto 0) := "1001"; -- unsigned lower or same
- constant cond_ge_c : std_ulogic_vector(3 downto 0) := "1010"; -- greater than or equal
- constant cond_lt_c : std_ulogic_vector(3 downto 0) := "1011"; -- less than
- constant cond_gt_c : std_ulogic_vector(3 downto 0) := "1100"; -- greater than
- constant cond_le_c : std_ulogic_vector(3 downto 0) := "1101"; -- less than or equal
- constant cond_ts_c : std_ulogic_vector(3 downto 0) := "1110"; -- transfer flag set
- constant cond_al_c : std_ulogic_vector(3 downto 0) := "1111"; -- always
-
-
--- ALU Function Select --------------------------------------------------------------------
--- -------------------------------------------------------------------------------------------
- constant fs_inc_c : std_ulogic_vector(3 downto 0) := "0000"; -- add immediate
- constant fs_dec_c : std_ulogic_vector(3 downto 0) := "0001"; -- subtract immediate
- constant fs_add_c : std_ulogic_vector(3 downto 0) := "0010"; -- add
- constant fs_adc_c : std_ulogic_vector(3 downto 0) := "0011"; -- add with carry
- constant fs_sub_c : std_ulogic_vector(3 downto 0) := "0100"; -- subtract
- constant fs_sbc_c : std_ulogic_vector(3 downto 0) := "0101"; -- subtract with carry
- constant fs_cmp_c : std_ulogic_vector(3 downto 0) := "0110"; -- compare (sub)
- constant fs_cpx_c : std_ulogic_vector(3 downto 0) := "0111"; -- extende compare with flags (sbc)
- constant fs_and_c : std_ulogic_vector(3 downto 0) := "1000"; -- logical and
- constant fs_orr_c : std_ulogic_vector(3 downto 0) := "1001"; -- logical or
- constant fs_eor_c : std_ulogic_vector(3 downto 0) := "1010"; -- logical xor
- constant fs_nand_c : std_ulogic_vector(3 downto 0) := "1011"; -- logical nand
- constant fs_bic_c : std_ulogic_vector(3 downto 0) := "1100"; -- bit clear
- constant fs_teq_c : std_ulogic_vector(3 downto 0) := "1101"; -- compare by logical and
- constant fs_tst_c : std_ulogic_vector(3 downto 0) := "1110"; -- compare by logical xor
- constant fs_sft_c : std_ulogic_vector(3 downto 0) := "1111"; -- shift operation
-
- -- Pseudo Intructions --
- constant fs_ld_user_c : std_ulogic_vector(3 downto 0) := fs_orr_c; -- load from user bank
- constant fs_st_user_c : std_ulogic_vector(3 downto 0) := fs_and_c; -- store to user bank
- constant fs_ld_msr_c : std_ulogic_vector(3 downto 0) := fs_cmp_c; -- load from msr
- constant fs_st_msr_c : std_ulogic_vector(3 downto 0) := fs_cpx_c; -- store to msr
- constant fs_ld_pc_c : std_ulogic_vector(3 downto 0) := fs_tst_c; -- load from pc
- constant fs_st_pc_c : std_ulogic_vector(3 downto 0) := fs_teq_c; -- store to pc
-
- -- Elementary ALU Operations --
- constant alu_adc_c : std_ulogic_vector(2 downto 0) := "000"; -- add with carry
- constant alu_sbc_c : std_ulogic_vector(2 downto 0) := "001"; -- subtract with carry
- constant alu_bic_c : std_ulogic_vector(2 downto 0) := "010"; -- bit clear
- constant alu_sft_c : std_ulogic_vector(2 downto 0) := "011"; -- shift operation
- constant alu_and_c : std_ulogic_vector(2 downto 0) := "100"; -- logical and
- constant alu_orr_c : std_ulogic_vector(2 downto 0) := "101"; -- logical or
- constant alu_eor_c : std_ulogic_vector(2 downto 0) := "110"; -- logical xor
- constant alu_nand_c : std_ulogic_vector(2 downto 0) := "111"; -- logical nand
-
-
--- Shifter Control ------------------------------------------------------------------------
--- -------------------------------------------------------------------------------------------
- constant sft_swp_c : std_ulogic_vector(2 downto 0) := "000"; -- swap halfwords
- constant sft_asr_c : std_ulogic_vector(2 downto 0) := "001"; -- arithemtical right shift
- constant sft_rol_c : std_ulogic_vector(2 downto 0) := "010"; -- rotate left
- constant sft_ror_c : std_ulogic_vector(2 downto 0) := "011"; -- rotate right
- constant sft_lsl_c : std_ulogic_vector(2 downto 0) := "100"; -- logical shift left
- constant sft_lsr_c : std_ulogic_vector(2 downto 0) := "101"; -- logical shift right
- constant sft_rlc_c : std_ulogic_vector(2 downto 0) := "110"; -- rotate left through carry
- constant sft_rrc_c : std_ulogic_vector(2 downto 0) := "111"; -- rotate right through carry
-
-
--- Cool Stuff -----------------------------------------------------------------------------
--- -------------------------------------------------------------------------------------------
- -- S: Carrie Underwood - Thank God For The Hometowns
- -- M: Precious - Das Leben ist kostbar
- -- M: Mean Creek
- -- S: Mumford & Sons - Lover of the Light
- -- M: 127 Hours
- -- M: Hart of Dixie
- -- M: Nick und Norah - Soundtrack einer Nacht
- -- M: Joyride - S**drive
- -- S: David Nail - Whatever She's Got
- -- M: Brantley Gilbert - Bottoms Up
-
-
--- Functions ------------------------------------------------------------------------------
--- -------------------------------------------------------------------------------------------
- function log2(temp : natural) return natural; -- logarithm base 2
-
-
--- Component: Data Register File ----------------------------------------------------------
--- -------------------------------------------------------------------------------------------
- component reg_file
- port (
- -- global control --
- clk_i : in std_ulogic; -- global clock line
- ce_i : in std_ulogic; -- clock enable
- rst_i : in std_ulogic; -- global reset line, sync, high-active
-
- -- function control --
- wb_ctrl_bus_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- wb stage control
- of_ctrl_bus_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- of stage control
-
- -- data input --
- wb_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write back data
- immediate_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediates
- pc_1d_i : in std_ulogic_vector(data_width_c-1 downto 0); -- pc 1x delayed
- wb_fwd_i : in std_ulogic_vector(fwd_width_c-1 downto 0); -- wb stage forwarding path
-
- -- data output --
- op_a_data_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand a output
- op_b_data_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand b output
- op_c_data_o : out std_ulogic_vector(data_width_c-1 downto 0) -- operand c output
- );
- end component;
-
-
--- Component: Arithmetic/Logic Unit -------------------------------------------------------
--- -------------------------------------------------------------------------------------------
- component alu
- port (
- -- global control --
- clk_i : in std_ulogic; -- global clock line
- ce_i : in std_ulogic; -- clock enable
- rst_i : in std_ulogic; -- global reset line, sync, high-active
-
- -- function control --
- ex_ctrl_bus_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- stage control
- flag_bus_i : in std_ulogic_vector(flag_bus_width_c-1 downto 0); -- flag input
-
- -- data input --
- op_a_i : in std_ulogic_vector(data_width_c-1 downto 0); -- operand a input
- op_b_i : in std_ulogic_vector(data_width_c-1 downto 0); -- operand b input
- op_c_i : in std_ulogic_vector(data_width_c-1 downto 0); -- operand c input
- pc_1d_i : in std_ulogic_vector(data_width_c-1 downto 0); -- 1x delayed pc
- ma_fwd_i : in std_ulogic_vector(fwd_width_c-1 downto 0); -- ma stage forwarding path
- wb_fwd_i : in std_ulogic_vector(fwd_width_c-1 downto 0); -- wb stage forwarding path
-
- -- data output --
- flag_bus_o : out std_ulogic_vector(flag_bus_width_c-1 downto 0); -- flag output
- mask_t_flag_o : out std_ulogic; -- t-flag for mask generation
- msr_data_o : out std_ulogic_vector(data_width_c-1 downto 0); -- msr write data
- alu_res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- alu result
- mul_res_o : out std_ulogic_vector(2*data_width_c-1 downto 0); -- mul result
- bp_opa_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand a bypass
- bp_opc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand c bypass
- cp_cp0_en_o : out std_ulogic; -- access to cp0
- cp_cp1_en_o : out std_ulogic; -- access to cp1
- cp_op_o : out std_ulogic; -- data transfer/operation
- cp_rw_o : out std_ulogic; -- read/write access
- cp_cmd_o : out std_ulogic_vector(cp_cmd_width_c-1 downto 0); -- register addresses / cmd
- cp_dat_o : out std_ulogic_vector(data_width_c-1 downto 0); -- write data
- mem_req_o : out std_ulogic -- data memory access request for next cycle
- );
- end component;
-
-
--- Component: Machine Status System -------------------------------------------------------
--- -------------------------------------------------------------------------------------------
- component sys_reg
- port (
- -- global control --
- clk_i : in std_ulogic; -- global clock line
- ce_i : in std_ulogic; -- clock enable
- rst_i : in std_ulogic; -- global reset line, asyc
-
- -- function control --
- ex_ctrl_bus_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- ex stage control
- ma_ctrl_bus_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- ma stage control
- ext_int_req0_i : in std_ulogic; -- external interrupt request 0
- ext_int_req1_i : in std_ulogic; -- external interrupt request 1
-
- -- data input --
- flag_bus_i : in std_ulogic_vector(flag_bus_width_c-1 downto 0); -- flag input
- exc_pos_i : in std_ulogic; -- external interrupt would be possible
- stop_pc : in std_ulogic; -- freeze pc
- pc_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- pc write data
- msr_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- msr write data
-
- -- data output --
- flag_bus_o : out std_ulogic_vector(flag_bus_width_c-1 downto 0); -- flag output
- valid_branch_o : out std_ulogic; -- valid branch detected
- exc_executed_o : out std_ulogic; -- executed exception
- wake_up_o : out std_ulogic; -- wake-up signal
- rd_msr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data msr
- pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- pc output
- pc_1d_o : out std_ulogic_vector(data_width_c-1 downto 0); -- pc 1x delayed
- cp_ptc_o : out std_ulogic; -- user coprocessor protection
- cond_true_o : out std_ulogic; -- condition is true
- mode_o : out std_ulogic; -- current operating mode
- mode_ff_o : out std_ulogic -- delayed current mode
- );
- end component;
-
-
--- Component: Memory Access Control -------------------------------------------------------
--- -------------------------------------------------------------------------------------------
- component mem_acc
- port (
- -- global control --
- clk_i : in std_ulogic; -- global clock line
- ce_i : in std_ulogic; -- clock enable
- rst_i : in std_ulogic; -- global reset line, asyc
-
- -- function control --
- ma_ctrl_bus_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- ma stage control
-
- -- data input --
- alu_res_i : in std_ulogic_vector(data_width_c-1 downto 0); -- alu result
- mul_res_i : in std_ulogic_vector(2*data_width_c-1 downto 0); -- mul result
- adr_base_i : in std_ulogic_vector(data_width_c-1 downto 0); -- op_a bypass
- data_bp_i : in std_ulogic_vector(data_width_c-1 downto 0); -- op_b bypass
- cp_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- coprocessor rd data
- rd_msr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- read data msr
- wb_fwd_i : in std_ulogic_vector(fwd_width_c-1 downto 0); -- wb stage forwarding path
-
- -- data output --
- data_o : out std_ulogic_vector(data_width_c-1 downto 0); -- data output
- mem_adr_fb_o : out std_ulogic_vector(data_width_c-1 downto 0); -- memory address feedback
- ma_fwd_o : out std_ulogic_vector(fwd_width_c-1 downto 0); -- ma stage forwarding path
-
- -- memory (w) interface --
- mem_adr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address output
- mem_dat_o : out std_ulogic_vector(data_width_c-1 downto 0); -- write data output
- mem_rw_o : out std_ulogic -- read write
- );
- end component;
-
-
--- Component: Data Write Back Unit --------------------------------------------------------
--- -------------------------------------------------------------------------------------------
- component wb_unit
- port (
- -- global control --
- clk_i : in std_ulogic; -- global clock line
- ce_i : in std_ulogic; -- clock enable
- rst_i : in std_ulogic; -- global reset line, sync, high-active
-
- -- function control --
- wb_ctrl_bus_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- wb stage control
-
- -- data input --
- mem_wb_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
- alu_wb_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- alu read data
- mem_adr_fb_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address feedback
-
- -- data output --
- wb_data_o : out std_ulogic_vector(data_width_c-1 downto 0); -- write back data
- wb_fwd_o : out std_ulogic_vector(fwd_width_c-1 downto 0) -- wb stage forwarding path
- );
- end component;
-
-
--- Component: Control System --------------------------------------------------------------
--- -------------------------------------------------------------------------------------------
- component ctrl
- port (
- -- global control --
- clk_i : in std_ulogic; -- global clock line
- ce_i : in std_ulogic; -- clock enable
- rst_i : in std_ulogic; -- global reset line, sync, high-active
-
- -- decoder interface --
- op_dec_ctrl_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- decoder ctrl lines
- multi_cyc_o : out std_ulogic; -- multi-cycle indicator
- multi_cyc_req_i : in std_ulogic; -- multi-cycle request
- instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction input
- instr_reg_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction register
-
- -- control lines --
- of_ctrl_bus_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- of stage control
- ex_ctrl_bus_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- ex stage control
- ma_ctrl_bus_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- ma stage control
- wb_ctrl_bus_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- wb stage control
-
- -- function control --
- cond_true_i : in std_ulogic; -- condition is true
- valid_branch_i : in std_ulogic; -- valid branch detected
- exc_taken_i : in std_ulogic; -- exception taken
- wake_up_i : in std_ulogic; -- wake up from sleep
- exc_pos_o : out std_ulogic; -- exception would be possible
- stop_pc_o : out std_ulogic -- freeze program counter
- );
- end component;
-
-
--- Component: Opcode Decoder --------------------------------------------------------------
--- -------------------------------------------------------------------------------------------
- component op_dec
- port (
- -- decoder interface input --
- instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction input
- instr_adr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- corresponding address
- t_flag_i : in std_ulogic; -- t-flag input
- m_flag_i : in std_ulogic; -- mode flag input
- multi_cyc_i : in std_ulogic; -- multi-cycle indicator
- cp_ptc_i : in std_ulogic; -- user coprocessor protection
-
- -- decoder interface output --
- multi_cyc_req_o : out std_ulogic; -- multi-cycle reqest
- ctrl_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- decoder ctrl lines
- imm_o : out std_ulogic_vector(data_width_c-1 downto 0) -- immediate
- );
- end component;
-
-
--- Component: Atlas CPU Core --------------------------------------------------------------
--- -------------------------------------------------------------------------------------------
- component atlas_cpu
- port (
- -- global control --
- clk_i : in std_ulogic; -- global clock line
- rst_i : in std_ulogic; -- global reset line, sync, high-active
- ce_i : in std_ulogic; -- global clock enable, high-active
-
- -- instruction interface --
- instr_adr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction byte adr
- instr_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction input
-
- -- memory arbitration --
- sys_mode_o : out std_ulogic; -- current operating mode
- sys_int_o : out std_ulogic; -- interrupt processing
-
- -- memory system --
- mem_req_o : out std_ulogic; -- mem access in next cycle
- mem_rw_o : out std_ulogic; -- read write
- mem_adr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- data byte adr
- mem_dat_o : out std_ulogic_vector(data_width_c-1 downto 0); -- write data
- mem_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- read data
-
- -- coprocessor interface --
- usr_cp_en_o : out std_ulogic; -- access to cp0
- sys_cp_en_o : out std_ulogic; -- access to cp1
- cp_op_o : out std_ulogic; -- data transfer/processing
- cp_rw_o : out std_ulogic; -- read/write access
- cp_cmd_o : out std_ulogic_vector(cp_cmd_width_c-1 downto 0); -- register addresses / cmd
- cp_dat_o : out std_ulogic_vector(data_width_c-1 downto 0); -- write data
- cp_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- read data cp0 or cp1
-
- -- external interrupt lines --
- ext_int_0_i : in std_ulogic; -- external interrupt request 0
- ext_int_1_i : in std_ulogic -- external interrupt request 1
- );
- end component;
-
-
--- Component: System Controller Core 0 ----------------------------------------------------
--- -------------------------------------------------------------------------------------------
- component sys_0_core
- port (
- -- host interface --
- clk_i : in std_ulogic; -- global clock line
- rst_i : in std_ulogic; -- global reset line, sync, high-active
- ice_i : in std_ulogic; -- interface clock enable, high-active
- w_en_i : in std_ulogic; -- write enable
- r_en_i : in std_ulogic; -- read enable
- adr_i : in std_ulogic_vector(02 downto 0); -- access address
- dat_i : in std_ulogic_vector(15 downto 0); -- write data
- dat_o : out std_ulogic_vector(15 downto 0); -- read data
-
- -- interrupt lines --
- timer_irq_o : out std_ulogic; -- timer irq
- irq_i : in std_ulogic_vector(07 downto 0); -- irq input
- irq_o : out std_ulogic -- interrupt request
- );
- end component;
-
-
--- Component: System Controller Core 1 ----------------------------------------------------
--- -------------------------------------------------------------------------------------------
- component sys_1_core
- generic (
- -- clock speed configuration --
- clk_speed_g : std_ulogic_vector(31 downto 0) := (others => '0') -- clock speed (in hz)
- );
- port (
- -- host interface --
- clk_i : in std_ulogic; -- global clock line
- rst_i : in std_ulogic; -- global reset line, sync, high-active
- ice_i : in std_ulogic; -- interface clock enable, high-active
- w_en_i : in std_ulogic; -- write enable
- r_en_i : in std_ulogic; -- read enable
- adr_i : in std_ulogic_vector(02 downto 0); -- access address
- dat_i : in std_ulogic_vector(15 downto 0); -- write data
- dat_o : out std_ulogic_vector(15 downto 0); -- read data
- sys_mode_i : in std_ulogic; -- current operating mode
- int_exe_i : in std_ulogic; -- interrupt beeing executed
-
- -- memory interface --
- mem_ip_adr_o : out std_ulogic_vector(15 downto 0); -- instruction page
- mem_dp_adr_o : out std_ulogic_vector(15 downto 0) -- data page
- );
- end component;
-
-
--- Component: Communication Controller Core 0 ---------------------------------------------
--- -------------------------------------------------------------------------------------------
- component com_0_core
- port (
- -- host interface --
- clk_i : in std_ulogic; -- global clock line
- rst_i : in std_ulogic; -- global reset line, sync, high-active
- ice_i : in std_ulogic; -- interface clock enable, high-active
- w_en_i : in std_ulogic; -- write enable
- r_en_i : in std_ulogic; -- read enable
- adr_i : in std_ulogic_vector(02 downto 0); -- access address
- dat_i : in std_ulogic_vector(15 downto 0); -- write data
- dat_o : out std_ulogic_vector(15 downto 0); -- read data
-
- -- memory interface --
- uart_rx_irq_o : out std_ulogic; -- uart irq "data available"
- uart_tx_irq_o : out std_ulogic; -- uart irq "sending done"
- spi_irq_o : out std_ulogic; -- spi irq "transfer done"
- pio_irq_o : out std_ulogic; -- pio input pin change irq
-
- -- io interface --
- uart_txd_o : out std_ulogic; -- uart serial output
- uart_rxd_i : in std_ulogic; -- uart serial input
- spi_mosi_o : out std_ulogic_vector(07 downto 0); -- serial data out
- spi_miso_i : in std_ulogic_vector(07 downto 0); -- serial data in
- spi_sck_o : out std_ulogic_vector(07 downto 0); -- serial clock out
- spi_cs_o : out std_ulogic_vector(07 downto 0); -- chip select (low active)
- pio_in_i : in std_ulogic_vector(15 downto 0); -- parallel input
- pio_out_o : out std_ulogic_vector(15 downto 0); -- parallel output
- sys_io_i : in std_ulogic_vector(07 downto 0); -- system input
- sys_io_o : out std_ulogic_vector(07 downto 0) -- system output
- );
- end component;
-
-
--- Component: Communication Controller Core 1 ---------------------------------------------
--- -------------------------------------------------------------------------------------------
- component com_1_core
- port (
- -- host interface --
- clk_i : in std_ulogic; -- global clock line
- rst_i : in std_ulogic; -- global reset line, sync, high-active
- ice_i : in std_ulogic; -- interface clock enable, high-active
- w_en_i : in std_ulogic; -- write enable
- r_en_i : in std_ulogic; -- read enable
- cmd_exe_i : in std_ulogic; -- execute command
- adr_i : in std_ulogic_vector(02 downto 0); -- access address/command
- dat_i : in std_ulogic_vector(15 downto 0); -- write data
- dat_o : out std_ulogic_vector(15 downto 0); -- read data
- irq_o : out std_ulogic; -- interrupt request
-
- -- wishbone bus --
- wb_clk_o : out std_ulogic; -- bus clock
- wb_rst_o : out std_ulogic; -- bus reset, sync, high active
- wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
- wb_sel_o : out std_ulogic_vector(01 downto 0); -- byte select
- wb_data_o : out std_ulogic_vector(15 downto 0); -- data out
- wb_data_i : in std_ulogic_vector(15 downto 0); -- data in
- wb_we_o : out std_ulogic; -- read/write
- wb_cyc_o : out std_ulogic; -- cycle enable
- wb_stb_o : out std_ulogic; -- strobe
- wb_ack_i : in std_ulogic; -- acknowledge
- wb_err_i : in std_ulogic -- bus error
- );
- end component;
-
-
--- Component: System Coprocessor ----------------------------------------------------------
--- -------------------------------------------------------------------------------------------
- component system_cp
- generic (
- -- configuration --
- clock_speed_g : std_ulogic_vector(31 downto 0) -- clock speed in hz
- );
- port (
- -- global control --
- clk_i : in std_ulogic; -- global clock line
- rst_i : in std_ulogic; -- global reset line, sync, high-active
- ice_i : in std_ulogic; -- interface clock enable, high-active
-
- -- processor interface --
- cp_en_i : in std_ulogic; -- access coprocessor
- cp_op_i : in std_ulogic; -- data transfer/processing
- cp_rw_i : in std_ulogic; -- read/write access
- cp_cmd_i : in std_ulogic_vector(cp_cmd_width_c-1 downto 0); -- register addresses / cmd
- cp_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
- cp_dat_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
- cp_irq_o : out std_ulogic; -- unit interrupt request
- sys_mode_i : in std_ulogic; -- current operating mode
- int_exe_i : in std_ulogic; -- interrupt beeing executed
-
- -- memory interface --
- mem_ip_adr_o : out std_ulogic_vector(15 downto 0); -- instruction page
- mem_dp_adr_o : out std_ulogic_vector(15 downto 0); -- data page
-
- -- io interface --
- uart_rxd_i : in std_ulogic; -- receiver input
- uart_txd_o : out std_ulogic; -- uart transmitter output
- spi_mosi_o : out std_ulogic_vector(07 downto 0); -- serial data out
- spi_miso_i : in std_ulogic_vector(07 downto 0); -- serial data in
- spi_sck_o : out std_ulogic_vector(07 downto 0); -- serial clock out
- spi_cs_o : out std_ulogic_vector(07 downto 0); -- chip select (low active)
- pio_out_o : out std_ulogic_vector(15 downto 0); -- parallel output
- pio_in_i : in std_ulogic_vector(15 downto 0); -- parallel input
- sys_out_o : out std_ulogic_vector(07 downto 0); -- system output
- sys_in_i : in std_ulogic_vector(07 downto 0); -- system input
- irq_i : in std_ulogic; -- irq
-
- -- wishbone bus --
- wb_clk_o : out std_ulogic; -- bus clock
- wb_rst_o : out std_ulogic; -- bus reset, sync, high active
- wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
- wb_sel_o : out std_ulogic_vector(01 downto 0); -- byte select
- wb_data_o : out std_ulogic_vector(15 downto 0); -- data out
- wb_data_i : in std_ulogic_vector(15 downto 0); -- data in
- wb_we_o : out std_ulogic; -- read/write
- wb_cyc_o : out std_ulogic; -- cycle enable
- wb_stb_o : out std_ulogic; -- strobe
- wb_ack_i : in std_ulogic; -- acknowledge
- wb_err_i : in std_ulogic -- bus error
- );
- end component;
-
-
--- Component: memory gateway --------------------------------------------------------------
--- -------------------------------------------------------------------------------------------
- component mem_gate
- port (
- -- host interface --
- clk_i : in std_ulogic; -- global clock line
- rst_i : in std_ulogic; -- global reset line, sync, high-active
-
- i_adr_i : in std_ulogic_vector(15 downto 0); -- instruction adr
- i_dat_o : out std_ulogic_vector(15 downto 0); -- instruction out
- d_req_i : in std_ulogic; -- request access in next cycle
- d_rw_i : in std_ulogic; -- read/write
- d_adr_i : in std_ulogic_vector(15 downto 0); -- data adr
- d_dat_i : in std_ulogic_vector(15 downto 0); -- data in
- d_dat_o : out std_ulogic_vector(15 downto 0); -- data out
- mem_ip_adr_i : in std_ulogic_vector(15 downto 0); -- instruction page
- mem_dp_adr_i : in std_ulogic_vector(15 downto 0); -- data page
-
- -- boot rom interface --
- boot_i_adr_o : out std_ulogic_vector(15 downto 0); -- instruction adr
- boot_i_dat_i : in std_ulogic_vector(15 downto 0); -- instruction out
- boot_d_en_o : out std_ulogic; -- access enable
- boot_d_rw_o : out std_ulogic; -- read/write
- boot_d_adr_o : out std_ulogic_vector(15 downto 0); -- data adr
- boot_d_dat_o : out std_ulogic_vector(15 downto 0); -- data in
- boot_d_dat_i : in std_ulogic_vector(15 downto 0); -- data out
-
- -- memory interface --
- mem_i_page_o : out std_ulogic_vector(15 downto 0); -- instruction page
- mem_i_adr_o : out std_ulogic_vector(15 downto 0); -- instruction adr
- mem_i_dat_i : in std_ulogic_vector(15 downto 0); -- instruction out
- mem_d_en_o : out std_ulogic; -- access enable
- mem_d_rw_o : out std_ulogic; -- read/write
- mem_d_page_o : out std_ulogic_vector(15 downto 0); -- data page
- mem_d_adr_o : out std_ulogic_vector(15 downto 0); -- data adr
- mem_d_dat_o : out std_ulogic_vector(15 downto 0); -- data in
- mem_d_dat_i : in std_ulogic_vector(15 downto 0) -- data out
- );
- end component;
-
-
--- Component: Bootloader Memory -----------------------------------------------------------
--- -------------------------------------------------------------------------------------------
- component boot_mem
- port (
- -- host interface --
- clk_i : in std_ulogic; -- global clock line
- i_adr_i : in std_ulogic_vector(15 downto 0); -- instruction adr
- i_dat_o : out std_ulogic_vector(15 downto 0); -- instruction out
- d_en_i : in std_ulogic; -- access enable
- d_rw_i : in std_ulogic; -- read/write
- d_adr_i : in std_ulogic_vector(15 downto 0); -- data adr
- d_dat_i : in std_ulogic_vector(15 downto 0); -- data in
- d_dat_o : out std_ulogic_vector(15 downto 0) -- data out
- );
- end component;
-
-end atlas_core_package;
-
-package body atlas_core_package is
-
--- Function: Logarithm Base 2 -------------------------------------------------------------
--- -------------------------------------------------------------------------------------------
- function log2(temp : natural) return natural is
- begin
- for i in 0 to integer'high loop
- if (2**i >= temp) then
- return i;
- end if;
- end loop;
- return 0;
- end function log2;
-
-
-end atlas_core_package;
Index: rtl/COM_1_CORE.vhd
===================================================================
--- rtl/COM_1_CORE.vhd (revision 37)
+++ rtl/COM_1_CORE.vhd (nonexistent)
@@ -1,390 +0,0 @@
--- #########################################################
--- # << ATLAS Project - Communication Controller 1 >> #
--- # ***************************************************** #
--- # - Wishbone Bus Adapter #
--- # -> 32-bit address, 16-bit data #
--- # -> Variable Length Burst-Transfers #
--- # -> Bus access is pipelined #
--- # ***************************************************** #
--- # Last modified: 28.11.2014 #
--- # ***************************************************** #
--- # by Stephan Nolting 4788, Hanover, Germany #
--- #########################################################
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.atlas_core_package.all;
-
-entity com_1_core is
- port (
--- ###############################################################################################
--- ## Host Interface ##
--- ###############################################################################################
-
- clk_i : in std_ulogic; -- global clock line
- rst_i : in std_ulogic; -- global reset line, sync, high-active
- ice_i : in std_ulogic; -- interface clock enable, high-active
- w_en_i : in std_ulogic; -- write enable
- r_en_i : in std_ulogic; -- read enable
- cmd_exe_i : in std_ulogic; -- execute command
- adr_i : in std_ulogic_vector(02 downto 0); -- access address/command
- dat_i : in std_ulogic_vector(15 downto 0); -- write data
- dat_o : out std_ulogic_vector(15 downto 0); -- read data
- irq_o : out std_ulogic; -- interrupt request
-
--- ###############################################################################################
--- ## Wishbone Bus ##
--- ###############################################################################################
-
- wb_clk_o : out std_ulogic; -- bus clock
- wb_rst_o : out std_ulogic; -- bus reset, sync, high active
- wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
- wb_sel_o : out std_ulogic_vector(01 downto 0); -- byte select
- wb_data_o : out std_ulogic_vector(15 downto 0); -- data out
- wb_data_i : in std_ulogic_vector(15 downto 0); -- data in
- wb_we_o : out std_ulogic; -- read/write
- wb_cyc_o : out std_ulogic; -- cycle enable
- wb_stb_o : out std_ulogic; -- strobe
- wb_ack_i : in std_ulogic; -- acknowledge
--- wb_halt_i : in std_ulogic; -- halt transfer
- wb_err_i : in std_ulogic -- bus error
- );
-end com_1_core;
-
-architecture com_1_core_behav of com_1_core is
-
- -- Module Addresses --
- constant ctrl_reg_c : std_ulogic_vector(02 downto 0) := "000"; -- R/W: control register (see below)
- constant base_adr_l_reg_c : std_ulogic_vector(02 downto 0) := "001"; -- R/W: base address low
- constant base_adr_h_reg_c : std_ulogic_vector(02 downto 0) := "010"; -- R/W: base address high
- constant adr_offset_c : std_ulogic_vector(02 downto 0) := "011"; -- R/W: address offset (2's comp)
- constant rtx_fifo_c : std_ulogic_vector(02 downto 0) := "100"; -- R/W: Read/write FIFO
- constant timeout_val_c : std_ulogic_vector(02 downto 0) := "101"; -- R/W: Bus timeout cycles
-
- -- Module Operations --
- constant cmd_init_rtrans_c : std_ulogic_vector(02 downto 0) := "000"; -- start READ transfer
- constant cmd_init_wtrans_c : std_ulogic_vector(02 downto 0) := "001"; -- start WRITE transfer
-
- -- CTRL Register Bits --
- constant done_irq_c : natural := 0; -- R: Transfer done (interrupt) flag
- constant bus_err_irq_c : natural := 1; -- R: Wishbone bus error (interrupt) flag
- constant timeout_irq_c : natural := 2; -- R: Wishbone bus timeout (interrupt) flag
- constant done_irq_en_c : natural := 3; -- R/W: Allow IRQ for
- constant bus_err_en_irq_c : natural := 4; -- R/W: Allow IRQ for
- constant timeout_en_irq_c : natural := 5; -- R/W: Allow IRQ for
- constant busy_flag_c : natural := 6; -- R: Transfer in progress (busy)
- constant dir_flag_c : natural := 7; -- R: Direction of last transfer (1: write, 0: read)
- constant burst_size_lsb_c : natural := 8; -- R/W: Burst size LSB
- constant burst_size_msb_c : natural := 15; -- R/W: Burst size MSB
-
- -- Config Regs --
- signal base_adr : std_ulogic_vector(31 downto 0); -- base address
- signal adr_offset : std_ulogic_vector(15 downto 0); -- address offset (2's comp)
- signal timeout_val : std_ulogic_vector(15 downto 0); -- timeout in cycles
-
- -- arbiter --
- signal arb_busy : std_ulogic; -- arbiter busy flag
- signal dir_ctrl : std_ulogic; -- direction of current/last transfer (0:read, 1:write)
- signal burst_size : std_ulogic_vector(log2(wb_fifo_size_c)-1 downto 0);
- signal ack_cnt : std_ulogic_vector(log2(wb_fifo_size_c)-1 downto 0);
- signal wb_adr_offset : std_ulogic_vector(31 downto 0);
- signal timeout_cnt : std_ulogic_vector(15 downto 0);
-
- -- irq system --
- signal bus_err_irq_en : std_ulogic;
- signal trans_done_irq_en : std_ulogic;
- signal timeout_irq_en : std_ulogic;
- signal bus_err_irq : std_ulogic;
- signal trans_done_irq : std_ulogic;
- signal timeout_irq : std_ulogic;
-
- -- rtx fifo --
- type rtx_fifo_t is array (0 to wb_fifo_size_c-1) of std_ulogic_vector(15 downto 0);
- signal tx_fifo, rx_fifo : rtx_fifo_t := (others => (others => '0'));
- signal rx_fifo_r_pnt : std_ulogic_vector(log2(wb_fifo_size_c)-1 downto 0);
- signal rx_fifo_w_pnt : std_ulogic_vector(log2(wb_fifo_size_c)-1 downto 0);
- signal tx_fifo_r_pnt : std_ulogic_vector(log2(wb_fifo_size_c)-1 downto 0);
- signal tx_fifo_w_pnt : std_ulogic_vector(log2(wb_fifo_size_c)-1 downto 0);
-
- -- wb sync --
- signal wb_data_i_ff : std_ulogic_vector(15 downto 0); -- data in buffer
- signal wb_ack_ff : std_ulogic; -- acknowledge buffer
- signal wb_err_ff : std_ulogic; -- bus error
- signal wb_adr : std_ulogic_vector(31 downto 0);
- signal wb_adr_buf : std_ulogic_vector(31 downto 0);
- signal wb_stb_buf : std_ulogic;
- signal wb_cyc_buf : std_ulogic;
-
-begin
-
- -- Write Access ----------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- w_acc: process(clk_i)
- begin
- if rising_edge(clk_i) then
- if (rst_i = '1') then
- base_adr <= (others => '0');
- burst_size <= (others => '0');
- adr_offset <= (others => '0');
- timeout_val <= (others => '0');
- bus_err_irq_en <= '0';
- trans_done_irq_en <= '0';
- timeout_irq_en <= '0';
- elsif (ice_i = '1') then -- interface enable
- if (w_en_i = '1') and (arb_busy = '0') then -- register update only if not busy
- case (adr_i) is
- when ctrl_reg_c =>
- burst_size <= dat_i(burst_size_lsb_c+log2(wb_fifo_size_c)-1 downto burst_size_lsb_c);
- bus_err_irq_en <= dat_i(bus_err_en_irq_c);
- trans_done_irq_en <= dat_i(done_irq_en_c);
- timeout_irq_en <= dat_i(timeout_en_irq_c);
- when base_adr_l_reg_c => base_adr(15 downto 00) <= dat_i;
- when base_adr_h_reg_c => base_adr(31 downto 16) <= dat_i;
- when adr_offset_c => adr_offset <= dat_i;
- when timeout_val_c => timeout_val <= dat_i;
- when others => null;
- end case;
- end if;
- end if;
- end if;
- end process w_acc;
-
-
- -- Read Access -----------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- r_acc: process(adr_i, base_adr, adr_offset, arb_busy, dir_ctrl, burst_size, bus_err_irq_en,
- trans_done_irq_en, bus_err_irq, trans_done_irq, rx_fifo, rx_fifo_r_pnt,
- timeout_irq_en, timeout_irq, timeout_val)
- begin
- case (adr_i) is
- when ctrl_reg_c =>
- dat_o <= (others => '0');
- dat_o(busy_flag_c) <= arb_busy;
- dat_o(dir_flag_c) <= dir_ctrl;
- dat_o(bus_err_irq_c) <= bus_err_irq;
- dat_o(bus_err_en_irq_c) <= bus_err_irq_en;
- dat_o(done_irq_c) <= trans_done_irq;
- dat_o(done_irq_en_c) <= trans_done_irq_en;
- dat_o(timeout_irq_c) <= timeout_irq;
- dat_o(timeout_en_irq_c) <= timeout_irq_en;
- dat_o(burst_size_lsb_c+log2(wb_fifo_size_c)-1 downto burst_size_lsb_c) <= burst_size;
- when base_adr_l_reg_c => dat_o <= base_adr(15 downto 00);
- when base_adr_h_reg_c => dat_o <= base_adr(31 downto 16);
- when adr_offset_c => dat_o <= adr_offset;
- when rtx_fifo_c => dat_o <= rx_fifo(to_integer(unsigned(rx_fifo_r_pnt)));
- when timeout_val_c => dat_o <= timeout_val;
- when others => dat_o <= x"0000";
- end case;
- end process r_acc;
-
-
- -- Host FIFO Access ------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- fifo_acc: process(clk_i)
- begin
- if rising_edge(clk_i) then
- if (rst_i = '1') then
- tx_fifo_w_pnt <= (others => '0');
- rx_fifo_r_pnt <= (others => '0');
- elsif (ice_i = '1') then -- interface enabled
- if (adr_i = rtx_fifo_c) then -- fifo access
- if ((w_en_i and (arb_busy nand dir_ctrl)) = '1') then -- valid write to tx fifo?
- tx_fifo(to_integer(unsigned(tx_fifo_w_pnt))) <= dat_i;
- if (tx_fifo_w_pnt /= burst_size) then
- tx_fifo_w_pnt <= std_ulogic_vector(unsigned(tx_fifo_w_pnt) + 1); -- inc tx fifo write pointer
- else
- tx_fifo_w_pnt <= (others => '0');
- end if;
- end if;
- if ((r_en_i and (arb_busy nand (not dir_ctrl))) = '1') then -- valid read from rx fifo?
- if (rx_fifo_r_pnt /= burst_size) then
- rx_fifo_r_pnt <= std_ulogic_vector(unsigned(rx_fifo_r_pnt) + 1); -- inc rx fifo read pointer
- else
- rx_fifo_r_pnt <= (others => '0');
- end if;
- end if;
- end if;
- end if;
- end if;
- end process fifo_acc;
-
-
- -- Address Offset --------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- adr_offset_comp: process(adr_offset)
- begin
- wb_adr_offset(15 downto 0) <= adr_offset;
- for i in 16 to 31 loop -- sign extension
- wb_adr_offset(i) <= adr_offset(15);
- end loop;
- end process adr_offset_comp;
-
-
- -- Interrupt Output ------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- irq_o <= (bus_err_irq and bus_err_irq_en) or
- (trans_done_irq and trans_done_irq_en) or
- (timeout_irq and timeout_irq_en); -- use edge trigger!
-
-
- -- Bus Synchronizer ------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- bus_sync: process(clk_i)
- begin
- if rising_edge(clk_i) then
- if (rst_i = '1') then
- wb_data_i_ff <= (others => '0');
- wb_ack_ff <= '0';
- wb_err_ff <= '0';
- else
- wb_data_i_ff <= wb_data_i;
- wb_ack_ff <= wb_ack_i;
- wb_err_ff <= wb_err_i;
- end if;
- end if;
- end process bus_sync;
-
- -- static output --
- wb_sel_o <= (others => '1');
- wb_adr_o <= wb_adr;
- wb_clk_o <= clk_i;
- wb_rst_o <= rst_i;
-
-
- -- Bus Arbiter ------------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- bus_arbiter: process(clk_i)
- begin
- if rising_edge(clk_i) then
- if (rst_i = '1') then
- dir_ctrl <= '0';
- arb_busy <= '0';
- ack_cnt <= (others => '0');
- timeout_cnt <= (others => '0');
- tx_fifo_r_pnt <= (others => '0');
- rx_fifo_w_pnt <= (others => '0');
- bus_err_irq <= '0';
- trans_done_irq <= '0';
- timeout_irq <= '0';
- wb_data_o <= (others => '0');
- wb_adr <= (others => '0');
- wb_adr_buf <= (others => '0');
- wb_cyc_o <= '0';
- wb_stb_o <= '0';
- wb_stb_buf <= '0';
- wb_cyc_buf <= '0';
- wb_we_o <= '0';
- else
- -- idle mode ------------------------------
- if (arb_busy = '0') then
- ack_cnt <= (others => '0');
- timeout_cnt <= (others => '0');
- arb_busy <= '0';
- rx_fifo_w_pnt <= (others => '0');
- tx_fifo_r_pnt <= (others => '0');
- wb_adr <= (others => '0');
- wb_adr_buf <= base_adr;
- wb_stb_o <= '0';
- wb_stb_buf <= '0';
- wb_cyc_o <= '0';
- wb_cyc_buf <= '0';
-
- -- interface --
- if (ice_i = '1') then
- if (r_en_i = '1') and (adr_i = ctrl_reg_c) then -- read ctrl reg?
- bus_err_irq <= '0';
- trans_done_irq <= '0';
- timeout_irq <= '0';
- end if;
- if (cmd_exe_i = '1') then -- execute transfer command?
- if (adr_i = cmd_init_rtrans_c) then
- dir_ctrl <= '0'; -- read transfer
- arb_busy <= '1'; -- start!
- bus_err_irq <= '0';
- trans_done_irq <= '0';
- timeout_irq <= '0';
- wb_stb_buf <= '1';
- wb_cyc_buf <= '1';
- elsif (adr_i = cmd_init_wtrans_c) then
- dir_ctrl <= '1'; -- write transfer
- arb_busy <= '1'; -- start!
- bus_err_irq <= '0';
- trans_done_irq <= '0';
- timeout_irq <= '0';
- wb_stb_buf <= '1';
- wb_cyc_buf <= '1';
- end if;
- end if;
- end if;
-
- -- transfer in progress -------------------
- else --elsif (wb_halt_i = '0') then
- wb_we_o <= dir_ctrl;
- wb_adr <= wb_adr_buf;
- wb_stb_o <= wb_stb_buf;
- wb_cyc_o <= wb_cyc_buf;
- timeout_cnt <= std_ulogic_vector(unsigned(timeout_cnt) + 1);
-
- -- read transfer ------------------------
- if (dir_ctrl = '0') then
- if (wb_ack_ff = '1') then
- rx_fifo(to_integer(unsigned(rx_fifo_w_pnt))) <= wb_data_i_ff;
- rx_fifo_w_pnt <= std_ulogic_vector(unsigned(rx_fifo_w_pnt) + 1); -- inc rx fifo write pointer
- end if;
- if (rx_fifo_w_pnt /= burst_size) then -- all transfered?
- wb_adr_buf <= std_ulogic_vector(unsigned(wb_adr_buf) + unsigned(wb_adr_offset)); -- adr
- wb_stb_buf <= '1';
- else
- wb_stb_buf <= '0';
- end if;
-
- -- write transfer -----------------------
- else
- wb_data_o <= tx_fifo(to_integer(unsigned(tx_fifo_r_pnt)));
- if (tx_fifo_r_pnt /= burst_size) then -- all transfered?
- tx_fifo_r_pnt <= std_ulogic_vector(unsigned(tx_fifo_r_pnt) + 1); -- inc tx fifo read pointer
- wb_adr_buf <= std_ulogic_vector(unsigned(wb_adr_buf) + unsigned(wb_adr_offset)); -- adr
- wb_stb_buf <= '1';
- else
- wb_stb_buf <= '0';
- end if;
- end if;
-
- -- ack counter --
- if (wb_ack_ff = '1') then
- if (ack_cnt = burst_size) then -- yeay, finished!
- wb_cyc_buf <= '0';
- wb_cyc_o <= '0';
- arb_busy <= '0'; -- done
- trans_done_irq <= '1';
- else
- ack_cnt <= std_ulogic_vector(unsigned(ack_cnt) + 1);
- wb_cyc_buf <= '1';
- end if;
- end if;
-
- -- bus error/timeout? --
- if (wb_err_ff = '1') or (timeout_cnt = timeout_val) then
- wb_cyc_o <= '0';
- wb_cyc_buf <= '0';
- wb_stb_o <= '0';
- wb_stb_buf <= '0';
- arb_busy <= '0'; -- terminate
- trans_done_irq <= '0';
- if (wb_err_ff = '1') then
- bus_err_irq <= '1';
- else
- timeout_irq <= '1';
- end if;
- end if;
- end if;
- end if;
- end if;
- end process bus_arbiter;
-
-
-
-end com_1_core_behav;
Index: rtl/SYS_1_CORE.vhd
===================================================================
--- rtl/SYS_1_CORE.vhd (revision 37)
+++ rtl/SYS_1_CORE.vhd (nonexistent)
@@ -1,196 +0,0 @@
--- #########################################################
--- # << ATLAS Project - System Controller 1 >> #
--- # ***************************************************** #
--- # -> Memory Management Unit #
--- # -> Clock Information #
--- # ***************************************************** #
--- # Last modified: 28.11.2014 #
--- # ***************************************************** #
--- # by Stephan Nolting 4788, Hanover, Germany #
--- #########################################################
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.atlas_core_package.all;
-
-entity sys_1_core is
--- ###############################################################################################
--- ## Clock Speed Configuration ##
--- ###############################################################################################
- generic (
- clk_speed_g : std_ulogic_vector(31 downto 0) := (others => '0') -- clock speed (in Hz)
- );
- port (
--- ###############################################################################################
--- ## Host Interface ##
--- ###############################################################################################
-
- clk_i : in std_ulogic; -- global clock line
- rst_i : in std_ulogic; -- global reset line, sync, high-active
- ice_i : in std_ulogic; -- interface clock enable, high-active
- w_en_i : in std_ulogic; -- write enable
- r_en_i : in std_ulogic; -- read enable
- adr_i : in std_ulogic_vector(02 downto 0); -- access address
- dat_i : in std_ulogic_vector(15 downto 0); -- write data
- dat_o : out std_ulogic_vector(15 downto 0); -- read data
-
- sys_mode_i : in std_ulogic; -- current operating mode
- int_exe_i : in std_ulogic; -- interrupt beeing executed
-
--- ###############################################################################################
--- ## Memory Interface ##
--- ###############################################################################################
-
- mem_ip_adr_o : out std_ulogic_vector(15 downto 0); -- instruction page
- mem_dp_adr_o : out std_ulogic_vector(15 downto 0) -- data page
- );
-end sys_1_core;
-
-architecture sys_1_core_behav of sys_1_core is
-
- -- register addresses --
- constant mmu_irq_base_c : std_ulogic_vector(02 downto 0) := "000"; -- r/w: base page for irqs
- constant mmu_sys_i_page_c : std_ulogic_vector(02 downto 0) := "001"; -- r/w: system mode i page
- constant mmu_sys_d_page_c : std_ulogic_vector(02 downto 0) := "010"; -- r/w: system mode d page
- constant mmu_usr_i_page_c : std_ulogic_vector(02 downto 0) := "011"; -- r/w: user mode i page
- constant mmu_usr_d_page_c : std_ulogic_vector(02 downto 0) := "100"; -- r/w: user mode d page
- constant mmu_i_page_link_c : std_ulogic_vector(02 downto 0) := "101"; -- r: linked i page
- constant mmu_d_page_link_c : std_ulogic_vector(02 downto 0) := "110"; -- r: linked d page
- constant mmu_sys_info_c : std_ulogic_vector(02 downto 0) := "111"; -- r: system info
- -- sys info register (uses auto-pointer):
- -- 1st read access: clock speed low
- -- 2nd read access: clock speed high
-
- -- registers --
- signal mmu_irq_base : std_ulogic_vector(15 downto 0);
- signal mmu_sys_i_page : std_ulogic_vector(15 downto 0);
- signal mmu_sys_d_page : std_ulogic_vector(15 downto 0);
- signal mmu_usr_i_page : std_ulogic_vector(15 downto 0);
- signal mmu_usr_d_page : std_ulogic_vector(15 downto 0);
- signal mmu_i_page_link : std_ulogic_vector(15 downto 0);
- signal mmu_d_page_link : std_ulogic_vector(15 downto 0);
-
- -- buffers / local signals --
- signal i_sys_tmp, i_usr_tmp : std_ulogic_vector(15 downto 0);
- signal d_sys_tmp, d_usr_tmp : std_ulogic_vector(15 downto 0);
- signal mode_buf : std_ulogic_vector(01 downto 0);
- signal sys_info : std_ulogic_vector(15 downto 0);
- signal sys_info_adr : std_ulogic_vector(01 downto 0);
-
-begin
-
- -- MMU Register Update ---------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- mmu_reg_up: process(clk_i)
- begin
- if rising_edge(clk_i) then
- if (rst_i = '1') then
- mmu_irq_base <= start_page_c; -- (others => '0');
- mmu_sys_i_page <= start_page_c;
- mmu_sys_d_page <= start_page_c;
- mmu_usr_i_page <= start_page_c; -- (others => '0');
- mmu_usr_d_page <= start_page_c; -- (others => '0');
- mmu_i_page_link <= start_page_c; -- (others => '0');
- mmu_d_page_link <= start_page_c; -- (others => '0');
- i_sys_tmp <= start_page_c;
- d_sys_tmp <= start_page_c;
- i_usr_tmp <= start_page_c; -- (others => '0');
- d_usr_tmp <= start_page_c; -- (others => '0');
- mode_buf <= system_mode_c & system_mode_c; -- start in system mode
- elsif (ice_i = '1') then
-
- -- auto update --
- mode_buf <= mode_buf(0) & sys_mode_i;
- i_sys_tmp <= mmu_sys_i_page;
- d_sys_tmp <= mmu_sys_d_page;
- i_usr_tmp <= mmu_usr_i_page;
- d_usr_tmp <= mmu_usr_d_page;
-
- -- exception processing ----------------------------------------------------------
- -- ----------------------------------------------------------------------------------
- if (int_exe_i = '1') then
- mmu_sys_i_page <= mmu_irq_base; -- system-mode base page for irqs
- mmu_sys_d_page <= mmu_irq_base; -- system-mode base page for irqs
- i_sys_tmp <= mmu_irq_base; -- system-mode base page for irqs
- d_sys_tmp <= mmu_irq_base; -- system-mode base page for irqs
- if (mode_buf(1) = user_mode_c) then -- we were in usr mode
- mmu_i_page_link <= i_usr_tmp; -- save current sys i-page
- mmu_d_page_link <= d_usr_tmp; -- save current sys d-page
- else -- we were in sys mode
- mmu_i_page_link <= i_sys_tmp; -- save current sys i-page
- mmu_d_page_link <= d_sys_tmp; -- save current sys d-page
- end if;
-
- -- data transfer -----------------------------------------------------------------
- -- ----------------------------------------------------------------------------------
- elsif (w_en_i = '1') then -- valid write
- case (adr_i) is
- when mmu_irq_base_c => mmu_irq_base <= dat_i; -- system-mode base page
- when mmu_sys_i_page_c => mmu_sys_i_page <= dat_i; -- system instruction page
- when mmu_sys_d_page_c => mmu_sys_d_page <= dat_i; -- system data page
- when mmu_usr_i_page_c => mmu_usr_i_page <= dat_i; -- user instruction page
- when mmu_usr_d_page_c => mmu_usr_d_page <= dat_i; -- user data page
--- when mmu_i_page_link_c => mmu_i_page_link <= dat_i; -- instruction page link
--- when mmu_d_page_link_c => mmu_d_page_link <= dat_i; -- data page link
- when others => null; -- do nothing
- end case;
- end if;
- end if;
- end if;
- end process mmu_reg_up;
-
- -- page output --
- mem_ip_adr_o <= i_usr_tmp when (sys_mode_i = user_mode_c) else i_sys_tmp;
- mem_dp_adr_o <= d_usr_tmp when (sys_mode_i = user_mode_c) else d_sys_tmp;
-
-
- -- MMU Read Access -------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- r_acc: process(adr_i, mmu_irq_base, mmu_sys_i_page, mmu_sys_d_page, mmu_usr_i_page,
- mmu_usr_d_page, mmu_i_page_link, mmu_d_page_link, sys_info)
- begin
- case (adr_i) is
- when mmu_irq_base_c => dat_o <= mmu_irq_base; -- system-mode base page
- when mmu_sys_i_page_c => dat_o <= mmu_sys_i_page; -- system instruction page
- when mmu_sys_d_page_c => dat_o <= mmu_sys_d_page; -- system data page
- when mmu_usr_i_page_c => dat_o <= mmu_usr_i_page; -- user instruction page
- when mmu_usr_d_page_c => dat_o <= mmu_usr_d_page; -- user data page
- when mmu_i_page_link_c => dat_o <= mmu_i_page_link; -- instruction page link
- when mmu_d_page_link_c => dat_o <= mmu_d_page_link; -- data page link
- when mmu_sys_info_c => dat_o <= sys_info; -- system info
- when others => dat_o <= (others => '0'); -- dummy output
- end case;
- end process r_acc;
-
-
- -- System Info Output Control --------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- sys_info_ctrl: process(clk_i)
- begin
- if rising_edge(clk_i) then
- if (rst_i = '1') then
- sys_info_adr <= (others => '0');
- elsif (r_en_i = '1') and (ice_i = '1') and (adr_i = mmu_sys_info_c) then
- sys_info_adr <= std_ulogic_vector(unsigned(sys_info_adr) + 1);
- end if;
- end if;
- end process sys_info_ctrl;
-
- -- output selector --
- sys_info_out: process(sys_info_adr)
- begin
- case (sys_info_adr) is
- when "00" => sys_info <= clk_speed_g(15 downto 00);
- when "01" => sys_info <= clk_speed_g(31 downto 16);
- when "10" => sys_info <= clk_speed_g(15 downto 00);
- when "11" => sys_info <= clk_speed_g(31 downto 16);
- when others => sys_info <= (others => '0');
- end case;
- end process sys_info_out;
-
-
-
-end sys_1_core_behav;
Index: rtl/SYSTEM_CP.vhd
===================================================================
--- rtl/SYSTEM_CP.vhd (revision 37)
+++ rtl/SYSTEM_CP.vhd (nonexistent)
@@ -1,320 +0,0 @@
--- ########################################################
--- # << ATLAS Project - System Coprocessor >> #
--- # **************************************************** #
--- # Top entity of the system extension coprocessor. #
--- # **************************************************** #
--- # Last modified: 28.11.2014 #
--- # **************************************************** #
--- # by Stephan Nolting 4788, Hanover, Germany #
--- ########################################################
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.atlas_core_package.all;
-
-entity system_cp is
--- ###############################################################################################
--- ## Module Configuration ##
--- ###############################################################################################
- generic (
- clock_speed_g : std_ulogic_vector(31 downto 0) := x"00000000" -- clock speed in Hz
- );
- port (
--- ###############################################################################################
--- ## Global Control ##
--- ###############################################################################################
-
- clk_i : in std_ulogic; -- global clock line
- rst_i : in std_ulogic; -- global reset line, sync, high-active
- ice_i : in std_ulogic; -- interface clock enable, high-active
-
--- ###############################################################################################
--- ## Processor Interface ##
--- ###############################################################################################
-
- cp_en_i : in std_ulogic; -- access coprocessor
- cp_op_i : in std_ulogic; -- data transfer/processing
- cp_rw_i : in std_ulogic; -- read/write access
- cp_cmd_i : in std_ulogic_vector(cp_cmd_width_c-1 downto 0); -- register addresses / cmd
- cp_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write data
- cp_dat_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
- cp_irq_o : out std_ulogic; -- unit interrupt request
-
- sys_mode_i : in std_ulogic; -- current operating mode
- int_exe_i : in std_ulogic; -- interrupt beeing executed
-
--- ###############################################################################################
--- ## Memory Interface ##
--- ###############################################################################################
-
- mem_ip_adr_o : out std_ulogic_vector(15 downto 0); -- instruction page
- mem_dp_adr_o : out std_ulogic_vector(15 downto 0); -- data page
-
--- ###############################################################################################
--- ## Peripheral Communication Interface ##
--- ###############################################################################################
-
- -- uart --
- uart_rxd_i : in std_ulogic; -- receiver input
- uart_txd_o : out std_ulogic; -- uart transmitter output
-
- -- spi --
- spi_mosi_o : out std_ulogic_vector(07 downto 0); -- serial data out
- spi_miso_i : in std_ulogic_vector(07 downto 0); -- serial data in
- spi_sck_o : out std_ulogic_vector(07 downto 0); -- serial clock out
- spi_cs_o : out std_ulogic_vector(07 downto 0); -- chip select (low active)
-
- -- parallel io --
- pio_out_o : out std_ulogic_vector(15 downto 0); -- parallel output
- pio_in_i : in std_ulogic_vector(15 downto 0); -- parallel input
-
- -- system io --
- sys_out_o : out std_ulogic_vector(07 downto 0); -- system output
- sys_in_i : in std_ulogic_vector(07 downto 0); -- system input
-
- -- irqs --
- irq_i : in std_ulogic; -- IRQ
-
--- ###############################################################################################
--- ## Wishbone Bus ##
--- ###############################################################################################
-
- wb_clk_o : out std_ulogic; -- bus clock
- wb_rst_o : out std_ulogic; -- bus reset, sync, high active
- wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
- wb_sel_o : out std_ulogic_vector(01 downto 0); -- byte select
- wb_data_o : out std_ulogic_vector(15 downto 0); -- data out
- wb_data_i : in std_ulogic_vector(15 downto 0); -- data in
- wb_we_o : out std_ulogic; -- read/write
- wb_cyc_o : out std_ulogic; -- cycle enable
- wb_stb_o : out std_ulogic; -- strobe
- wb_ack_i : in std_ulogic; -- acknowledge
- wb_err_i : in std_ulogic -- bus error
- );
-end system_cp;
-
-architecture system_cp_behav of system_cp is
-
- -- module addresses --
- constant sys0_module_c : std_ulogic_vector(1 downto 0) := "00";
- constant sys1_module_c : std_ulogic_vector(1 downto 0) := "01";
- constant com0_module_c : std_ulogic_vector(1 downto 0) := "10";
- constant com1_module_c : std_ulogic_vector(1 downto 0) := "11";
-
- -- module interface --
- type module_interface_t is record
- data_o : std_ulogic_vector(data_width_c-1 downto 0);
- w_en : std_ulogic;
- r_en : std_ulogic;
- cmd_exe : std_ulogic;
- end record;
-
- signal sys_0_module : module_interface_t;
- signal sys_1_module : module_interface_t;
- signal com_0_module : module_interface_t;
- signal com_1_module : module_interface_t;
-
- -- raw interrupt signals --
- signal int_assign : std_ulogic_vector(7 downto 0);
- signal timer_irq : std_ulogic;
- signal uart_rx_irq : std_ulogic;
- signal uart_tx_irq : std_ulogic;
- signal spi_irq : std_ulogic;
- signal pio_irq : std_ulogic;
- signal wb_core_irq : std_ulogic;
-
- -- internals --
- signal read_acc : std_ulogic; -- true read access
- signal cmd_exe : std_ulogic; -- true coprocessor command
-
-begin
-
- -- Write Access Logic ----------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- ctrl_w_acc: process(cp_en_i, cp_rw_i, cp_op_i, cp_cmd_i)
- variable valid_acc_v : std_ulogic;
- begin
- -- valid write access? --
- valid_acc_v := cp_en_i and cp_rw_i and cp_op_i;
-
- -- address decoder --
- sys_0_module.w_en <= '0';
- sys_1_module.w_en <= '0';
- com_0_module.w_en <= '0';
- com_1_module.w_en <= '0';
- case (cp_cmd_i(cp_op_a_msb_c-1 downto cp_op_a_lsb_c)) is
- when sys0_module_c => sys_0_module.w_en <= valid_acc_v;
- when sys1_module_c => sys_1_module.w_en <= valid_acc_v;
- when com0_module_c => com_0_module.w_en <= valid_acc_v;
- when com1_module_c => com_1_module.w_en <= valid_acc_v;
- when others => null;
- end case;
- end process ctrl_w_acc;
-
-
- -- Read Access Logic -----------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- ctrl_r_acc: process(clk_i)
- begin
- if rising_edge(clk_i) then
- if (rst_i = '1') then
- cp_dat_o <= (others => '0');
- elsif (ice_i = '1') then -- clock enabled
- if (read_acc = '1') then -- valid read
- case (cp_cmd_i(cp_op_b_msb_c-1 downto cp_op_b_lsb_c)) is
- when sys0_module_c => cp_dat_o <= sys_0_module.data_o;
- when sys1_module_c => cp_dat_o <= sys_1_module.data_o;
- when com0_module_c => cp_dat_o <= com_0_module.data_o;
- when com1_module_c => cp_dat_o <= com_1_module.data_o;
- when others => cp_dat_o <= (others => '0');
- end case;
- else
- cp_dat_o <= (others => '0');
- end if;
- end if;
- end if;
- end process ctrl_r_acc;
-
- -- module read enable --
- read_acc <= cp_en_i and (not cp_rw_i) and cp_op_i; -- true read access
- sys_0_module.r_en <= read_acc when (cp_cmd_i(cp_op_b_msb_c-1 downto cp_op_b_lsb_c) = sys0_module_c) else '0';
- sys_1_module.r_en <= read_acc when (cp_cmd_i(cp_op_b_msb_c-1 downto cp_op_b_lsb_c) = sys1_module_c) else '0';
- com_0_module.r_en <= read_acc when (cp_cmd_i(cp_op_b_msb_c-1 downto cp_op_b_lsb_c) = com0_module_c) else '0';
- com_1_module.r_en <= read_acc when (cp_cmd_i(cp_op_b_msb_c-1 downto cp_op_b_lsb_c) = com1_module_c) else '0';
-
- -- module execute command --
- cmd_exe <= cp_en_i and (not cp_op_i); -- true coprocessor command
- sys_0_module.cmd_exe <= cmd_exe when (cp_cmd_i(cp_op_b_msb_c-1 downto cp_op_b_lsb_c) = sys0_module_c) else '0';
- sys_1_module.cmd_exe <= cmd_exe when (cp_cmd_i(cp_op_b_msb_c-1 downto cp_op_b_lsb_c) = sys1_module_c) else '0';
- com_0_module.cmd_exe <= cmd_exe when (cp_cmd_i(cp_op_b_msb_c-1 downto cp_op_b_lsb_c) = com0_module_c) else '0';
- com_1_module.cmd_exe <= cmd_exe when (cp_cmd_i(cp_op_b_msb_c-1 downto cp_op_b_lsb_c) = com1_module_c) else '0';
-
-
- -- System Controller 0 ---------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- system_ctrl_0: sys_0_core
- port map (
- -- host interface --
- clk_i => clk_i, -- global clock line
- rst_i => rst_i, -- global reset line, sync, high-active
- ice_i => ice_i, -- interface clock enable, high-active
- w_en_i => sys_0_module.w_en, -- write enable
- r_en_i => sys_0_module.r_en, -- read enable
- adr_i => cp_cmd_i(cp_cmd_msb_c downto cp_cmd_lsb_c), -- access address
- dat_i => cp_dat_i, -- write data
- dat_o => sys_0_module.data_o, -- read data
-
- -- irq lines --
- timer_irq_o => timer_irq, -- timer irq
- irq_i => int_assign, -- irq input
- irq_o => cp_irq_o -- interrupt request to cpu
- );
-
- -- irq assignment --
- int_assign(0) <= timer_irq; -- high precision timer irq
- int_assign(1) <= wb_core_irq; -- wishbone interface ctrl irq
- int_assign(2) <= uart_rx_irq; -- uart data received irq
- int_assign(3) <= uart_tx_irq; -- uart data send irq
- int_assign(4) <= spi_irq; -- spi transfer done irq
- int_assign(5) <= pio_irq; -- pio input change irq
- int_assign(6) <= '0'; -- reserved
- int_assign(7) <= irq_i; -- 'external' irq
-
-
- -- System Controller 1 ---------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- system_ctrl_1: sys_1_core
- generic map (
- clk_speed_g => clock_speed_g -- clock speed (inhz)
- )
- port map (
- -- host interface --
- clk_i => clk_i, -- global clock line
- rst_i => rst_i, -- global reset line, sync, high-active
- ice_i => ice_i, -- interface clock enable, high-active
- w_en_i => sys_1_module.w_en, -- write enable
- r_en_i => sys_1_module.r_en, -- read enable
- adr_i => cp_cmd_i(cp_cmd_msb_c downto cp_cmd_lsb_c), -- access address
- dat_i => cp_dat_i, -- write data
- dat_o => sys_1_module.data_o, -- read data
-
- -- cpu-special --
- sys_mode_i => sys_mode_i, -- current operating mode
- int_exe_i => int_exe_i, -- interrupt beeing executed
-
- -- memory interface --
- mem_ip_adr_o => mem_ip_adr_o, -- instruction page
- mem_dp_adr_o => mem_dp_adr_o -- data page
- );
-
-
- -- Communication Controller 0 --------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- communication_ctrl_0: com_0_core
- port map (
- -- host interface --
- clk_i => clk_i, -- global clock line
- rst_i => rst_i, -- global reset line, sync, high-active
- ice_i => ice_i, -- interface clock enable, high-active
- w_en_i => com_0_module.w_en, -- write enable
- r_en_i => com_0_module.r_en, -- read enable
- adr_i => cp_cmd_i(cp_cmd_msb_c downto cp_cmd_lsb_c), -- access address
- dat_i => cp_dat_i, -- write data
- dat_o => com_0_module.data_o, -- read data
-
- -- interrupt lines --
- uart_rx_irq_o => uart_rx_irq, -- uart irq "data available"
- uart_tx_irq_o => uart_tx_irq, -- uart irq "sending done"
- spi_irq_o => spi_irq, -- spi irq "transfer done"
- pio_irq_o => pio_irq, -- pio input pin change irq
-
- -- peripheral interface --
- uart_txd_o => uart_txd_o, -- uart transmitter
- uart_rxd_i => uart_rxd_i, -- uart receiver
- spi_mosi_o => spi_mosi_o, -- spi master out slave in
- spi_miso_i => spi_miso_i, -- spi master in slave out
- spi_sck_o => spi_sck_o, -- spi clock out
- spi_cs_o => spi_cs_o, -- spi chip select
- pio_in_i => pio_in_i, -- parallel input
- pio_out_o => pio_out_o, -- parallel output
- sys_io_i => sys_in_i, -- system input
- sys_io_o => sys_out_o -- system output
- );
-
-
- -- Communication Controller 1 --------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- communication_ctrl_1: com_1_core
- port map (
- -- host interface --
- wb_clk_o => wb_clk_o, -- bus clock
- wb_rst_o => wb_rst_o, -- bus reset, sync, high active
- clk_i => clk_i, -- global clock line
- rst_i => rst_i, -- global reset line, sync, high-active
- ice_i => ice_i, -- interface clock enable, high-active
- w_en_i => com_1_module.w_en, -- write enable
- r_en_i => com_1_module.r_en, -- read enable
- cmd_exe_i => com_1_module.cmd_exe,-- execute command
- adr_i => cp_cmd_i(cp_cmd_msb_c downto cp_cmd_lsb_c), -- access address/command
- dat_i => cp_dat_i, -- write data
- dat_o => com_1_module.data_o, -- read data
- irq_o => wb_core_irq, -- interrupt request
-
- -- wishbone bus --
- wb_adr_o => wb_adr_o, -- address
- wb_sel_o => wb_sel_o, -- byte select
- wb_data_o => wb_data_o, -- data out
- wb_data_i => wb_data_i, -- data in
- wb_we_o => wb_we_o, -- read/write
- wb_cyc_o => wb_cyc_o, -- cycle enable
- wb_stb_o => wb_stb_o, -- strobe
- wb_ack_i => wb_ack_i, -- acknowledge
- wb_err_i => wb_err_i -- bus error
- );
-
-
-
-end system_cp_behav;
Index: rtl/WB_UNIT.vhd
===================================================================
--- rtl/WB_UNIT.vhd (revision 37)
+++ rtl/WB_UNIT.vhd (nonexistent)
@@ -1,127 +0,0 @@
--- ########################################################
--- # << ATLAS Project - Data Write-Back >> #
--- # **************************************************** #
--- # Data write back selector for register file input. #
--- # **************************************************** #
--- # Last modified: 28.11.2014 #
--- # **************************************************** #
--- # by Stephan Nolting 4788, Hanover, Germany #
--- ########################################################
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.atlas_core_package.all;
-
-entity wb_unit is
- port (
--- ###############################################################################################
--- ## Global Control ##
--- ###############################################################################################
-
- clk_i : in std_ulogic; -- global clock line
- ce_i : in std_ulogic; -- clock enable
- rst_i : in std_ulogic; -- global reset line, sync, high-active
-
--- ###############################################################################################
--- ## Function Control ##
--- ###############################################################################################
-
- wb_ctrl_bus_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- wb stage control
-
--- ###############################################################################################
--- ## Data Input ##
--- ###############################################################################################
-
- mem_wb_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
- alu_wb_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- alu read data
- mem_adr_fb_i : in std_ulogic_vector(data_width_c-1 downto 0); -- memory address feedback
-
--- ###############################################################################################
--- ## Data Output ##
--- ###############################################################################################
-
- wb_data_o : out std_ulogic_vector(data_width_c-1 downto 0); -- write back data
- wb_fwd_o : out std_ulogic_vector(fwd_width_c-1 downto 0) -- wb stage forwarding path
- );
-end wb_unit;
-
-architecture wb_structure of wb_unit is
-
- -- pipeline register --
- signal alu_ff : std_ulogic_vector(data_width_c-1 downto 0);
-
- -- write-back source select --
- signal wb_data_int : std_ulogic_vector(data_width_c-1 downto 0);
-
- -- aligned mem data --
- signal mem_adr_fb : std_ulogic_vector(data_width_c-1 downto 0);
- signal mem_wb_dat_int : std_ulogic_vector(data_width_c-1 downto 0);
-
-begin
-
- -- Pipeline Register -----------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- pipe_reg: process(clk_i)
- begin
- if rising_edge(clk_i) then
- if (rst_i = '1') then
- alu_ff <= (others => '0');
- mem_adr_fb <= (others => '0');
- elsif (ce_i = '1') then
- alu_ff <= alu_wb_dat_i;
- mem_adr_fb <= mem_adr_fb_i;
- end if;
- end if;
- end process pipe_reg;
-
-
- -- Data Alignment --------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- dat_align: process(mem_adr_fb, mem_wb_dat_i)
- variable dat_end_v : std_ulogic_vector(data_width_c-1 downto 0);
- begin
- -- endianness converter --
- if (big_endian_c = false) then
- dat_end_v := mem_wb_dat_i(data_width_c/2-1 downto 0) & mem_wb_dat_i(data_width_c-1 downto data_width_c/2);
- else
- dat_end_v := mem_wb_dat_i;
- end if;
-
- -- unaligned access? --
- if (word_mode_en_c = false) then -- byte-addressed memory
- if (mem_adr_fb(0) = '1') then -- swap bytes
- mem_wb_dat_int <= dat_end_v(data_width_c/2-1 downto 0) & dat_end_v(data_width_c-1 downto data_width_c/2);
- else
- mem_wb_dat_int <= dat_end_v;
- end if;
- else -- word-addressed memory
- mem_wb_dat_int <= dat_end_v;
- end if;
- end process dat_align;
-
-
- -- Module Data Output ----------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- -- route mem data if valid mem-read-access
- wb_data_int <= mem_wb_dat_int when (wb_ctrl_bus_i(ctrl_rd_mem_acc_c) = '1') else alu_ff;
- wb_data_o <= wb_data_int;
-
-
- -- Forwarding Path Output ------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
-
- -- forwarding data --
- wb_fwd_o(fwd_dat_msb_c downto fwd_dat_lsb_c) <= wb_data_int;
-
- -- destination address --
- wb_fwd_o(fwd_adr_3_c downto fwd_adr_0_c) <= wb_ctrl_bus_i(ctrl_rd_3_c downto ctrl_rd_0_c);
-
- -- valid forwarding --
- wb_fwd_o(fwd_en_c) <= wb_ctrl_bus_i(ctrl_wb_en_c);
-
-
-
-end wb_structure;
Index: rtl/SYS_REG.vhd
===================================================================
--- rtl/SYS_REG.vhd (revision 37)
+++ rtl/SYS_REG.vhd (nonexistent)
@@ -1,409 +0,0 @@
--- ########################################################
--- # << ATLAS Project - System Registers >> #
--- # **************************************************** #
--- # The main system registers (MSR & PC) are located #
--- # here. Also the context control and interrupt #
--- # processing circuits are implemented within this #
--- # unit. #
--- # **************************************************** #
--- # Last modified: 28.11.2014 #
--- # **************************************************** #
--- # by Stephan Nolting 4788, Hanover, Germany #
--- ########################################################
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.atlas_core_package.all;
-
-entity sys_reg is
- port (
--- ###############################################################################################
--- ## Global Control ##
--- ###############################################################################################
-
- clk_i : in std_ulogic; -- global clock line
- ce_i : in std_ulogic; -- clock enable
- rst_i : in std_ulogic; -- global reset line, sync, high-active
-
--- ###############################################################################################
--- ## Function Control ##
--- ###############################################################################################
-
- ex_ctrl_bus_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- ex stage control
- ma_ctrl_bus_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- ma stage control
- ext_int_req0_i : in std_ulogic; -- external interrupt request 0
- ext_int_req1_i : in std_ulogic; -- external interrupt request 1
-
--- ###############################################################################################
--- ## Data Input ##
--- ###############################################################################################
-
- flag_bus_i : in std_ulogic_vector(flag_bus_width_c-1 downto 0); -- flag input
- exc_pos_i : in std_ulogic; -- exception would be possible
- stop_pc : in std_ulogic; -- freeze pc
- pc_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- pc write data
- msr_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- msr write data
-
--- ###############################################################################################
--- ## Data Output ##
--- ###############################################################################################
-
- flag_bus_o : out std_ulogic_vector(flag_bus_width_c-1 downto 0); -- flag output
- valid_branch_o : out std_ulogic; -- valid branch detected
- exc_executed_o : out std_ulogic; -- executed executed
- wake_up_o : out std_ulogic; -- wake-up signal
- rd_msr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- read data msr
- pc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- pc output
- pc_1d_o : out std_ulogic_vector(data_width_c-1 downto 0); -- pc 1x delayed
- cp_ptc_o : out std_ulogic; -- user coprocessor protection
- cond_true_o : out std_ulogic; -- condition is true
- mode_o : out std_ulogic; -- current operating mode
- mode_ff_o : out std_ulogic -- delayed current mode
- );
-end sys_reg;
-
-architecture sr_structure of sys_reg is
-
- -- system register --
- signal sys_reg_pc : std_ulogic_vector(data_width_c-1 downto 0);
- signal sys_reg_msr : std_ulogic_vector(data_width_c-1 downto 0);
- signal pc_1d_tmp : std_ulogic_vector(data_width_c-1 downto 0);
-
- -- branch system --
- signal valid_branch : std_ulogic;
-
- -- interrupt system --
- signal int_req : std_ulogic;
- signal int_vector : std_ulogic_vector(15 downto 0);
- signal xint_sync : std_ulogic_vector(01 downto 0);
-
- -- mode flag delay buffer --
- signal mode_buffer : std_ulogic_vector(02 downto 0);
-
-begin
-
- -- External Interrupt Sychronizer ----------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- xi_synchronizer: process(clk_i)
- variable valid_int_req_v : std_ulogic;
- begin
- if rising_edge(clk_i) then
- if (rst_i = '1') then
- xint_sync <= (others => '0');
- elsif (ce_i = '1') then
- xint_sync(0) <= ext_int_req0_i;
- xint_sync(1) <= ext_int_req1_i;
- end if;
- end if;
- end process xi_synchronizer;
-
-
-
- -- Exception Priority System ---------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- exc_sys: process(ex_ctrl_bus_i, xint_sync, exc_pos_i, sys_reg_msr)
- variable xint0_en_v, xint1_en_v : std_ulogic;
- variable xint0_valid_v, xint1_valid_v : std_ulogic;
- begin
- -- external interrupt enable --
- -- => external_int is possible and int_source is enabled and global_ints are enabled
- xint0_en_v := sys_reg_msr(msr_xint0_en_c);
- xint1_en_v := sys_reg_msr(msr_xint1_en_c);
- xint0_valid_v := exc_pos_i and xint0_en_v and sys_reg_msr(msr_xint_en_c);
- xint1_valid_v := exc_pos_i and xint1_en_v and sys_reg_msr(msr_xint_en_c);
-
- -- wake up signal --
- wake_up_o <= (xint0_en_v and xint_sync(0)) or (xint1_en_v and xint_sync(1));
-
- -- exception priority list and encoding --
- if ((xint0_valid_v = '1') and (xint_sync(0) = '1')) then -- external interrupt 0
- int_req <= '1';
- int_vector <= irq0_int_vec_c;
- elsif ((xint1_valid_v = '1') and (xint_sync(1) = '1')) then -- external interrupt 1
- int_req <= '1';
- int_vector <= irq1_int_vec_c;
- elsif ((exc_pos_i = '1') and (ex_ctrl_bus_i(ctrl_cmd_err_c) = '1')) then -- msr/reg/coprocessor access violation // undefined instruction
- int_req <= '1';
- int_vector <= cmd_err_int_vec_c;
- elsif ((exc_pos_i = '1') and (ex_ctrl_bus_i(ctrl_syscall_c) = '1')) then -- software interrupt / system call
- int_req <= '1';
- int_vector <= swi_int_vec_c;
- else -- no exception
- int_req <= '0';
- int_vector <= res_int_vec_c; -- irrelevant
- end if;
- end process exc_sys;
-
- -- output to cycle manager --
- exc_executed_o <= int_req;
-
-
- -- System Register Update ------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- sr_update: process(clk_i, sys_reg_msr, ex_ctrl_bus_i, mode_buffer)
- variable m_msr_acc_v : std_ulogic_vector(2 downto 0);
- begin
- -- manual msr access mode (from ex stage) --
- m_msr_acc_v := mode_buffer(1) & ex_ctrl_bus_i(ctrl_msr_am_1_c downto ctrl_msr_am_0_c);
-
- -- sync update --
- if rising_edge(clk_i) then
- if (rst_i = '1') then
- sys_reg_pc <= start_adr_c; -- start address
- sys_reg_msr <= (others => '0');
- sys_reg_msr(msr_mode_flag_c) <= system_mode_c; -- we're the king after reset
- sys_reg_msr(msr_svd_mode_c) <= system_mode_c;
- elsif (ce_i = '1') then -- clock enable
-
- -- exception msr update -------------------------------------------------
- if (int_req = '1') then -- switch to system mode
- sys_reg_msr(msr_mode_flag_c) <= system_mode_c; -- goto sytem mode
- sys_reg_msr(msr_svd_mode_c) <= mode_buffer(1); -- save current mode of instr. in ex stage
- sys_reg_msr(msr_xint_en_c) <= '0'; -- clear global xint enable flag
-
- elsif (ex_ctrl_bus_i(ctrl_en_c) = '1') then -- valid operation
- if (mode_buffer(1) = system_mode_c) then -- only system mode (instr. in ex stage)
- if (ex_ctrl_bus_i(ctrl_re_xint_c) = '1') and (ex_ctrl_bus_i(ctrl_pc_wr_c) = '1') then -- valid pc access and re-enable request?
- sys_reg_msr(msr_xint_en_c) <= '1'; -- auto re-enable global x_ints
- end if;
- end if;
-
- -- manual msr update ----------------------------------------------------
- if (ex_ctrl_bus_i(ctrl_msr_wr_c) = '1') then -- write operation
- case (m_msr_acc_v) is
- when "100" => -- system mode: full update
- sys_reg_msr <= msr_data_i;
- when "101" => -- system mode: update all alu flags
- sys_reg_msr(msr_usr_z_flag_c) <= msr_data_i(msr_usr_z_flag_c);
- sys_reg_msr(msr_usr_c_flag_c) <= msr_data_i(msr_usr_c_flag_c);
- sys_reg_msr(msr_usr_o_flag_c) <= msr_data_i(msr_usr_o_flag_c);
- sys_reg_msr(msr_usr_n_flag_c) <= msr_data_i(msr_usr_n_flag_c);
- sys_reg_msr(msr_usr_t_flag_c) <= msr_data_i(msr_usr_t_flag_c);
- sys_reg_msr(msr_sys_z_flag_c) <= msr_data_i(msr_sys_z_flag_c);
- sys_reg_msr(msr_sys_c_flag_c) <= msr_data_i(msr_sys_c_flag_c);
- sys_reg_msr(msr_sys_o_flag_c) <= msr_data_i(msr_sys_o_flag_c);
- sys_reg_msr(msr_sys_n_flag_c) <= msr_data_i(msr_sys_n_flag_c);
- sys_reg_msr(msr_sys_t_flag_c) <= msr_data_i(msr_sys_t_flag_c);
- when "110" => -- system mode: only update system alu flags
- sys_reg_msr(msr_sys_z_flag_c) <= msr_data_i(msr_sys_z_flag_c);
- sys_reg_msr(msr_sys_c_flag_c) <= msr_data_i(msr_sys_c_flag_c);
- sys_reg_msr(msr_sys_o_flag_c) <= msr_data_i(msr_sys_o_flag_c);
- sys_reg_msr(msr_sys_n_flag_c) <= msr_data_i(msr_sys_n_flag_c);
- sys_reg_msr(msr_sys_t_flag_c) <= msr_data_i(msr_sys_t_flag_c);
- when others => -- system/user mode: only update user alu flags
- sys_reg_msr(msr_usr_z_flag_c) <= msr_data_i(msr_usr_z_flag_c);
- sys_reg_msr(msr_usr_c_flag_c) <= msr_data_i(msr_usr_c_flag_c);
- sys_reg_msr(msr_usr_o_flag_c) <= msr_data_i(msr_usr_o_flag_c);
- sys_reg_msr(msr_usr_n_flag_c) <= msr_data_i(msr_usr_n_flag_c);
- sys_reg_msr(msr_usr_t_flag_c) <= msr_data_i(msr_usr_t_flag_c);
- end case;
-
- -- context change -------------------------------------------------------
- elsif (ex_ctrl_bus_i(ctrl_ctx_down_c) = '1') or (ex_ctrl_bus_i(ctrl_restsm_c) = '1') then -- context down/switch
- sys_reg_msr(msr_svd_mode_c) <= mode_buffer(1); -- save current mode of instr. in ex stage
- if (ex_ctrl_bus_i(ctrl_ctx_down_c) = '1') then
- sys_reg_msr(msr_mode_flag_c) <= user_mode_c; -- go down to user mode
- elsif (ex_ctrl_bus_i(ctrl_restsm_c) = '1') then
- sys_reg_msr(msr_mode_flag_c) <= sys_reg_msr(msr_svd_mode_c); -- restore old mode
- end if;
--- if (sys_reg_msr(msr_mode_flag_c) = system_mode_c) then -- only in system mode!
--- sys_reg_msr(msr_xint_en_c) <= ex_ctrl_bus_i(ctrl_re_xint_c); -- auto re-enable global x_ints
--- end if;
-
- -- automatic msr update -------------------------------------------------
- else
- if (mode_buffer(1) = user_mode_c) then -- user mode auto alu flag update (instr. in ex stage)
- if(ex_ctrl_bus_i(ctrl_fupdate_c) = '1') then -- allow auto update of alu flags
- sys_reg_msr(msr_usr_z_flag_c) <= flag_bus_i(flag_z_c);
- sys_reg_msr(msr_usr_c_flag_c) <= flag_bus_i(flag_c_c);
- sys_reg_msr(msr_usr_o_flag_c) <= flag_bus_i(flag_o_c);
- sys_reg_msr(msr_usr_n_flag_c) <= flag_bus_i(flag_n_c);
- end if;
- if (ex_ctrl_bus_i(ctrl_tf_store_c) = '1') then -- allow user mode update of t-flag
- sys_reg_msr(msr_usr_t_flag_c) <= flag_bus_i(flag_t_c);
- end if;
- else -- system mode auto alu flag update
- if(ex_ctrl_bus_i(ctrl_fupdate_c) = '1') then -- allow system mode auto update of alu flags
- sys_reg_msr(msr_sys_z_flag_c) <= flag_bus_i(flag_z_c);
- sys_reg_msr(msr_sys_c_flag_c) <= flag_bus_i(flag_c_c);
- sys_reg_msr(msr_sys_o_flag_c) <= flag_bus_i(flag_o_c);
- sys_reg_msr(msr_sys_n_flag_c) <= flag_bus_i(flag_n_c);
- end if;
- if (ex_ctrl_bus_i(ctrl_tf_store_c) = '1') then -- allow system mode update of t-flag
- sys_reg_msr(msr_sys_t_flag_c) <= flag_bus_i(flag_t_c);
- end if;
- end if;
- end if;
- end if;
-
- -- exception pc update --------------------------------------------------
- if (int_req = '1') then
- if (word_mode_en_c = false) then -- byte-addressed memory
- sys_reg_pc <= int_vector(14 downto 0) & '0';
- else -- word-addressed memory
- sys_reg_pc <= int_vector;
- end if;
-
- -- manual/branch pc update ----------------------------------------------
- elsif (valid_branch = '1') or ((ex_ctrl_bus_i(ctrl_en_c) = '1') and (ex_ctrl_bus_i(ctrl_ctx_down_c) = '1')) then -- valid automatic/manual update/goto user mode
- sys_reg_pc <= pc_data_i;
-
- -- automatic pc update --------------------------------------------------
- elsif (stop_pc = '0') then -- update instruction address
- if (word_mode_en_c = false) then -- byte-addressed memory
- sys_reg_pc <= std_ulogic_vector(unsigned(sys_reg_pc) + 2); -- byte increment
- else -- word-addressed memory
- sys_reg_pc <= std_ulogic_vector(unsigned(sys_reg_pc) + 1); -- word increment
- end if;
- end if;
-
- end if;
- end if;
- end process sr_update;
-
-
- -- MSR Flag Output -------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- flag_bus_o(flag_z_c) <= sys_reg_msr(msr_usr_z_flag_c) when (mode_buffer(1) = user_mode_c) else sys_reg_msr(msr_sys_z_flag_c);
- flag_bus_o(flag_c_c) <= sys_reg_msr(msr_usr_c_flag_c) when (mode_buffer(1) = user_mode_c) else sys_reg_msr(msr_sys_c_flag_c);
- flag_bus_o(flag_o_c) <= sys_reg_msr(msr_usr_o_flag_c) when (mode_buffer(1) = user_mode_c) else sys_reg_msr(msr_sys_o_flag_c);
- flag_bus_o(flag_n_c) <= sys_reg_msr(msr_usr_n_flag_c) when (mode_buffer(1) = user_mode_c) else sys_reg_msr(msr_sys_n_flag_c);
- flag_bus_o(flag_t_c) <= sys_reg_msr(msr_usr_t_flag_c) when (mode_buffer(1) = user_mode_c) else sys_reg_msr(msr_sys_t_flag_c);
-
- -- special flag output --
- mode_o <= sys_reg_msr(msr_mode_flag_c); -- current operating mode (for pc parallel access)
- mode_ff_o <= mode_buffer(2); -- delayed current operating mode (for of stage)
-
-
- -- MSR Data-Read Access --------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- msr_rd_acc: process(ma_ctrl_bus_i, sys_reg_msr, mode_buffer)
- variable msr_r_mode_v : std_ulogic_vector(2 downto 0);
- begin
- msr_r_mode_v := mode_buffer(0) & ma_ctrl_bus_i(ctrl_msr_am_1_c downto ctrl_msr_am_0_c); -- access from ma stage
- rd_msr_o <= (others => '0');
- case (msr_r_mode_v) is
- when "100" => -- system mode: full read access
- rd_msr_o <= sys_reg_msr;
- when "101" => -- system mode: only read all alu flags
- rd_msr_o(msr_sys_z_flag_c) <= sys_reg_msr(msr_sys_z_flag_c);
- rd_msr_o(msr_sys_c_flag_c) <= sys_reg_msr(msr_sys_c_flag_c);
- rd_msr_o(msr_sys_o_flag_c) <= sys_reg_msr(msr_sys_o_flag_c);
- rd_msr_o(msr_sys_n_flag_c) <= sys_reg_msr(msr_sys_n_flag_c);
- rd_msr_o(msr_sys_t_flag_c) <= sys_reg_msr(msr_sys_t_flag_c);
- rd_msr_o(msr_usr_z_flag_c) <= sys_reg_msr(msr_usr_z_flag_c);
- rd_msr_o(msr_usr_c_flag_c) <= sys_reg_msr(msr_usr_c_flag_c);
- rd_msr_o(msr_usr_o_flag_c) <= sys_reg_msr(msr_usr_o_flag_c);
- rd_msr_o(msr_usr_n_flag_c) <= sys_reg_msr(msr_usr_n_flag_c);
- rd_msr_o(msr_usr_t_flag_c) <= sys_reg_msr(msr_usr_t_flag_c);
- when "110" => -- system mode: only read system alu flags
- rd_msr_o(msr_sys_z_flag_c) <= sys_reg_msr(msr_sys_z_flag_c);
- rd_msr_o(msr_sys_c_flag_c) <= sys_reg_msr(msr_sys_c_flag_c);
- rd_msr_o(msr_sys_o_flag_c) <= sys_reg_msr(msr_sys_o_flag_c);
- rd_msr_o(msr_sys_n_flag_c) <= sys_reg_msr(msr_sys_n_flag_c);
- rd_msr_o(msr_sys_t_flag_c) <= sys_reg_msr(msr_sys_t_flag_c);
- when others => -- system/user mode: only read user alu flags
- rd_msr_o(msr_usr_z_flag_c) <= sys_reg_msr(msr_usr_z_flag_c);
- rd_msr_o(msr_usr_c_flag_c) <= sys_reg_msr(msr_usr_c_flag_c);
- rd_msr_o(msr_usr_o_flag_c) <= sys_reg_msr(msr_usr_o_flag_c);
- rd_msr_o(msr_usr_n_flag_c) <= sys_reg_msr(msr_usr_n_flag_c);
- rd_msr_o(msr_usr_t_flag_c) <= sys_reg_msr(msr_usr_t_flag_c);
- end case;
- end process msr_rd_acc;
-
-
- -- PC, M-Flag and UCP_P-Flag Delay Generator -----------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- delay_gen: process(clk_i)
- begin
- if rising_edge(clk_i) then
- if (rst_i = '1') then
- pc_1d_tmp <= (others => '0');
- mode_buffer <= (others => '0');
- cp_ptc_o <= '0';
- elsif (ce_i = '1') then
- cp_ptc_o <= sys_reg_msr(msr_usr_cp_ptc_c); -- user_coprocessor protection
- mode_buffer <= sys_reg_msr(msr_mode_flag_c) & mode_buffer(2 downto 1);
- if (stop_pc = '0') then
- pc_1d_tmp <= sys_reg_pc;
--- mode_buffer <= sys_reg_msr(msr_mode_flag_c) & mode_buffer(2 downto 1);
- end if;
- end if;
- end if;
- end process delay_gen;
-
- -- pc outputs --
- pc_out_driver: process(sys_reg_pc)
- begin
- pc_o <= sys_reg_pc;
- pc_o(0) <= '0';
- end process pc_out_driver;
- pc_1d_o <= pc_1d_tmp; -- 1x delayed
-
-
- -- Branch Detector -------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- branch_detector: process(ex_ctrl_bus_i, sys_reg_msr, int_req, mode_buffer)
- variable z_v, c_v, o_v, n_v, t_v : std_ulogic;
- variable valid_v : std_ulogic;
- variable valid_branch_v : std_ulogic;
- variable manual_branch_v : std_ulogic;
- begin
-
- -- flag isolation (instruction from ex stage) --
- if (mode_buffer(1) = user_mode_c) then -- user mode
- z_v := sys_reg_msr(msr_usr_z_flag_c);
- c_v := sys_reg_msr(msr_usr_c_flag_c);
- o_v := sys_reg_msr(msr_usr_o_flag_c);
- n_v := sys_reg_msr(msr_usr_n_flag_c);
- t_v := sys_reg_msr(msr_usr_t_flag_c);
- else -- system mode
- z_v := sys_reg_msr(msr_sys_z_flag_c);
- c_v := sys_reg_msr(msr_sys_c_flag_c);
- o_v := sys_reg_msr(msr_sys_o_flag_c);
- n_v := sys_reg_msr(msr_sys_n_flag_c);
- t_v := sys_reg_msr(msr_sys_t_flag_c);
- end if;
-
- -- condition check --
- case (ex_ctrl_bus_i(ctrl_cond_3_c downto ctrl_cond_0_c)) is
- when cond_eq_c => valid_v := z_v; -- equal
- when cond_ne_c => valid_v := not z_v; -- not equal
- when cond_cs_c => valid_v := c_v; -- unsigned higher or same
- when cond_cc_c => valid_v := not c_v; -- unsigned lower
- when cond_mi_c => valid_v := n_v; -- negative
- when cond_pl_c => valid_v := not n_v; -- positive or zero
- when cond_os_c => valid_v := o_v; -- overflow
- when cond_oc_c => valid_v := not o_v; -- no overflow
- when cond_hi_c => valid_v := c_v and (not z_v); -- unisgned higher
- when cond_ls_c => valid_v := (not c_v) or z_v; -- unsigned lower or same
- when cond_ge_c => valid_v := n_v xnor o_v; -- greater than or equal
- when cond_lt_c => valid_v := n_v xor o_v; -- less than
- when cond_gt_c => valid_v := (not z_v) and (n_v xnor o_v); -- greater than
- when cond_le_c => valid_v := z_v or (n_v xor o_v); -- less than or equal
- when cond_ts_c => valid_v := t_v; -- transfer set
- when cond_al_c => valid_v := '1'; -- always
- when others => valid_v := '0'; -- undefined = never
- end case;
-
- -- condition true output --
- cond_true_o <= valid_v;
-
- -- manual branch? --
- manual_branch_v := ex_ctrl_bus_i(ctrl_pc_wr_c);
-
- -- valid branch command? --
- valid_branch_v := ex_ctrl_bus_i(ctrl_en_c) and ((ex_ctrl_bus_i(ctrl_branch_c) and valid_v) or manual_branch_v);
-
- -- output to cycle arbiter --
- valid_branch <= valid_branch_v;-- or int_req; -- internal signal, no int_req since it is redundant
- valid_branch_o <= valid_branch_v or int_req; -- external signal
-
- end process branch_detector;
-
-
-
-end sr_structure;
Index: rtl/ATLAS_CPU.vhd
===================================================================
--- rtl/ATLAS_CPU.vhd (revision 37)
+++ rtl/ATLAS_CPU.vhd (nonexistent)
@@ -1,358 +0,0 @@
--- ########################################################
--- # << ATLAS Project - Atlas CPU Core >> #
--- # **************************************************** #
--- # This is the top entity of the CPU core. #
--- # All submodules are instantiated here. #
--- # **************************************************** #
--- # Last modified: 28.11.2014 #
--- # **************************************************** #
--- # by Stephan Nolting 4788, Hanover, Germany #
--- ########################################################
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.atlas_core_package.all;
-
-entity atlas_cpu is
- port (
--- ###############################################################################################
--- ## Global Control ##
--- ###############################################################################################
-
- clk_i : in std_ulogic; -- global clock line
- rst_i : in std_ulogic; -- global reset line, sync, high-active
- ce_i : in std_ulogic; -- clock enable, high-active
-
--- ###############################################################################################
--- ## Instruction Interface ##
--- ###############################################################################################
-
- instr_adr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction byte adr
- instr_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction input
-
--- ###############################################################################################
--- ## Data Interface ##
--- ###############################################################################################
-
- -- memory arbitration --
- sys_mode_o : out std_ulogic; -- current operating mode
- sys_int_o : out std_ulogic; -- interrupt processing
-
- -- memory system --
- mem_req_o : out std_ulogic; -- mem access in next cycle
- mem_rw_o : out std_ulogic; -- read write
- mem_adr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- data byte adr
- mem_dat_o : out std_ulogic_vector(data_width_c-1 downto 0); -- write data
- mem_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- read data
-
--- ###############################################################################################
--- ## Coprocessor Interface ##
--- ###############################################################################################
-
- usr_cp_en_o : out std_ulogic; -- access to cp0
- sys_cp_en_o : out std_ulogic; -- access to cp1
- cp_op_o : out std_ulogic; -- data transfer/processing
- cp_rw_o : out std_ulogic; -- read/write access
- cp_cmd_o : out std_ulogic_vector(cp_cmd_width_c-1 downto 0); -- register addresses / cmd
- cp_dat_o : out std_ulogic_vector(data_width_c-1 downto 0); -- write data
- cp_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- read data cp0 or cp1
-
--- ###############################################################################################
--- ## External Interrupt Lines ##
--- ###############################################################################################
-
- ext_int_0_i : in std_ulogic; -- external interrupt request 0
- ext_int_1_i : in std_ulogic -- external interrupt request 1
- );
-end atlas_cpu;
-
-architecture atlas_cpu_behav of atlas_cpu is
-
- -- global nets --
- signal g_clk : std_ulogic; -- global clock line
- signal g_rst : std_ulogic; -- global reset line
- signal g_ce : std_ulogic; -- global clock enable
-
- -- control lines --
- signal of_ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0);
- signal ex_ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0);
- signal ma_ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0);
- signal wb_ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0);
-
- -- forwarding paths --
- signal ma_fwd : std_ulogic_vector(fwd_width_c-1 downto 0);
- signal wb_fwd : std_ulogic_vector(fwd_width_c-1 downto 0);
-
- -- data lines --
- signal wb_data : std_ulogic_vector(data_width_c-1 downto 0); -- write back data
- signal op_a_data : std_ulogic_vector(data_width_c-1 downto 0); -- operand a data
- signal op_b_data : std_ulogic_vector(data_width_c-1 downto 0); -- operand b data
- signal op_c_data : std_ulogic_vector(data_width_c-1 downto 0); -- operand c data
- signal bp_a_data : std_ulogic_vector(data_width_c-1 downto 0); -- operand a bypass
- signal bp_c_data : std_ulogic_vector(data_width_c-1 downto 0); -- operand c bypass
- signal alu_res : std_ulogic_vector(data_width_c-1 downto 0); -- alu result
- signal mul_res : std_ulogic_vector(2*data_width_c-1 downto 0); -- mul result
- signal immediate : std_ulogic_vector(data_width_c-1 downto 0); -- immediate value
- signal t_flag : std_ulogic; -- transfer flag
- signal ma_data : std_ulogic_vector(data_width_c-1 downto 0); -- ma stage result
- signal mem_adr_fb : std_ulogic_vector(data_width_c-1 downto 0); -- mem adr feedback
-
- -- program counter --
- signal pc_1d : std_ulogic_vector(data_width_c-1 downto 0); -- 1x delayed pc
- signal stop_pc : std_ulogic; -- freeze pc
-
- -- flag stuff --
- signal alu_flag_i : std_ulogic_vector(flag_bus_width_c-1 downto 0); -- alu flag input
- signal alu_flag_o : std_ulogic_vector(flag_bus_width_c-1 downto 0); -- alu flag output
- signal msr_w_data : std_ulogic_vector(data_width_c-1 downto 0); -- msr write data
- signal msr_r_data : std_ulogic_vector(data_width_c-1 downto 0); -- msr read data
-
- -- control signals --
- signal valid_branch : std_ulogic; -- taken branch
- signal exc_pos : std_ulogic; -- exception would be possible
- signal exc_taken : std_ulogic; -- async interrupt taken
- signal wake_up_call : std_ulogic; -- wake up from sleep
- signal mode : std_ulogic; -- current operating mode
- signal mode_ff : std_ulogic; -- delayed current operating mode
- signal cond_true : std_ulogic; -- condition is true
-
- -- opcode decoder --
- signal op_ctrl : std_ulogic_vector(ctrl_width_c-1 downto 0); -- decoder contorl output
- signal multi_cyc : std_ulogic; -- multi-cycle indicator
- signal multi_cyc_req : std_ulogic; -- multi-cycle reqest
- signal instr_reg : std_ulogic_vector(data_width_c-1 downto 0); -- instruction register
-
- -- coprocessor --
- signal cp_ptc : std_ulogic; -- user coprocessor protection
-
-begin
-
- -- Global Signals --------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- g_clk <= clk_i;
- g_ce <= ce_i;
- g_rst <= rst_i;
-
-
- -- Opcode Decoder --------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- opcode_decoder: op_dec
- port map (
- -- decoder interface input --
- instr_i => instr_reg, -- instruction input
- instr_adr_i => pc_1d, -- corresponding address
- t_flag_i => t_flag, -- t-flag input
- m_flag_i => mode_ff, -- mode flag input
- multi_cyc_i => multi_cyc, -- multi-cycle indicator
- cp_ptc_i => cp_ptc, -- coprocessor protection
-
- -- decoder interface output --
- multi_cyc_req_o => multi_cyc_req, -- multi-cycle reqest
- ctrl_o => op_ctrl, -- decoder ctrl lines
- imm_o => immediate -- immediate
- );
-
-
- -- Control System --------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- control_spine: ctrl
- port map (
- -- global control --
- clk_i => g_clk, -- global clock line
- ce_i => g_ce, -- clock enable
- rst_i => g_rst, -- global reset line, sync, high-active
-
- -- decoder interface --
- op_dec_ctrl_i => op_ctrl, -- decoder ctrl lines
- multi_cyc_o => multi_cyc, -- multi-cycle indicator
- multi_cyc_req_i => multi_cyc_req, -- multi-cycle request
- instr_i => instr_dat_i, -- instruction input
- instr_reg_o => instr_reg, -- instruction register
-
- -- control lines --
- of_ctrl_bus_o => of_ctrl, -- of stage control
- ex_ctrl_bus_o => ex_ctrl, -- ex stage control
- ma_ctrl_bus_o => ma_ctrl, -- ma stage control
- wb_ctrl_bus_o => wb_ctrl, -- wb stage control
-
- -- function control --
- cond_true_i => cond_true, -- condition is true
- valid_branch_i => valid_branch, -- valid branch detected
- exc_taken_i => exc_taken, -- excation execute
- wake_up_i => wake_up_call, -- wake up from sleep
- exc_pos_o => exc_pos, -- exception would be possible
- stop_pc_o => stop_pc -- freeze program counter
- );
-
-
- -- Machine Status System -------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- system_reg: sys_reg
- port map (
- -- global control --
- clk_i => g_clk, -- global clock line
- ce_i => g_ce, -- clock enable
- rst_i => g_rst, -- global reset line, asyc
-
- -- function control --
- ex_ctrl_bus_i => ex_ctrl, -- ex stage control
- ma_ctrl_bus_i => ma_ctrl, -- ma stage control
- ext_int_req0_i => ext_int_0_i, -- external interrupt request 0
- ext_int_req1_i => ext_int_1_i, -- external interrupt request 1
-
- -- data input --
- flag_bus_i => alu_flag_o, -- flag input
- exc_pos_i => exc_pos, -- exception would be possible
- stop_pc => stop_pc, -- freeze pc
- pc_data_i => alu_res, -- pc write data
- msr_data_i => msr_w_data, -- msr write data
-
- -- data output --
- flag_bus_o => alu_flag_i, -- flag output
- valid_branch_o => valid_branch, -- valid branch detected
- exc_executed_o => exc_taken, -- executed exception
- wake_up_o => wake_up_call, -- wake-up signal
- rd_msr_o => msr_r_data, -- read data msr
- pc_o => instr_adr_o, -- pc output
- pc_1d_o => pc_1d, -- pc 1x delayed
- cp_ptc_o => cp_ptc, -- coprocessor protection
- cond_true_o => cond_true, -- condition is true
- mode_o => mode, -- current mode
- mode_ff_o => mode_ff -- delayed current mode
- );
-
- -- control lines --
- sys_mode_o <= mode; -- current operating mode
- sys_int_o <= exc_taken; -- exception taken
-
-
- -- OF Stage --------------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- operand_fetch: reg_file
- port map (
- -- global control --
- clk_i => g_clk, -- global clock line
- ce_i => g_ce, -- clock enable
- rst_i => g_rst, -- global reset line, sync, high-active
-
- -- function control --
- wb_ctrl_bus_i => wb_ctrl, -- wb stage control
- of_ctrl_bus_i => of_ctrl, -- of stage control
-
- -- data input --
- wb_data_i => wb_data, -- write back data
- immediate_i => immediate, -- immediates
- pc_1d_i => pc_1d, -- pc 1x delayed
- wb_fwd_i => wb_fwd, -- wb stage forwarding path
-
- -- data output --
- op_a_data_o => op_a_data, -- operand a output
- op_b_data_o => op_b_data, -- operand b output
- op_c_data_o => op_c_data -- operand c output
- );
-
-
- -- EX Stage --------------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- executor: alu
- port map (
- -- global control --
- clk_i => g_clk, -- global clock line
- ce_i => g_ce, -- clock enable
- rst_i => g_rst, -- global reset line, sync, high-active
-
- -- function control --
- ex_ctrl_bus_i => ex_ctrl, -- stage control
- flag_bus_i => alu_flag_i, -- flag input
-
- -- data input --
- op_a_i => op_a_data, -- operand a input
- op_b_i => op_b_data, -- operand b input
- op_c_i => op_c_data, -- operand c input
- pc_1d_i => pc_1d, -- 1x delayed pc
- ma_fwd_i => ma_fwd, -- ma stage forwarding path
- wb_fwd_i => wb_fwd, -- wb stage forwarding path
-
- -- data output --
- flag_bus_o => alu_flag_o, -- flag output
- mask_t_flag_o => t_flag, -- t-flag for mask generation
- msr_data_o => msr_w_data, -- msr write data
- alu_res_o => alu_res, -- alu result
- mul_res_o => mul_res, -- mul result
- bp_opa_o => bp_a_data, -- operand a bypass
- bp_opc_o => bp_c_data, -- operand c bypass
-
- -- coprocessor interface --
- cp_cp0_en_o => usr_cp_en_o, -- access to cp0
- cp_cp1_en_o => sys_cp_en_o, -- access to cp1
- cp_op_o => cp_op_o, -- data transfer/operation
- cp_rw_o => cp_rw_o, -- read/write access
- cp_cmd_o => cp_cmd_o, -- register addresses / cmd
- cp_dat_o => cp_dat_o, -- write data
-
- -- memory access --
- mem_req_o => mem_req_o -- data memory access request for next cycle
- );
-
-
- -- MA Stage --------------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- memory_access: mem_acc
- port map (
- -- global control --
- clk_i => g_clk, -- global clock line
- ce_i => g_ce, -- clock enable
- rst_i => g_rst, -- global reset line, asyc
-
- -- function control --
- ma_ctrl_bus_i => ma_ctrl, -- ma stage control
-
- -- data input --
- alu_res_i => alu_res, -- alu result
- mul_res_i => mul_res, -- mul result
- adr_base_i => bp_a_data, -- op_a bypass
- data_bp_i => bp_c_data, -- op_b bypass
- cp_data_i => cp_dat_i, -- coprocessor rd data
- rd_msr_i => msr_r_data, -- read data msr
- wb_fwd_i => wb_fwd, -- wb stage forwarding path
-
- -- data output --
- data_o => ma_data, -- data output
- mem_adr_fb_o => mem_adr_fb, -- memory address feedback
- ma_fwd_o => ma_fwd, -- ma stage forwarding path
-
- -- memory (w) interface --
- mem_adr_o => mem_adr_o, -- address output
- mem_dat_o => mem_dat_o, -- write data output
- mem_rw_o => mem_rw_o -- read write
- );
-
-
- -- WB Stage --------------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- write_back: wb_unit
- port map (
- -- global control --
- clk_i => g_clk, -- global clock line
- ce_i => g_ce, -- clock enable
- rst_i => g_rst, -- global reset line, sync, high-active
-
- -- function control --
- wb_ctrl_bus_i => wb_ctrl, -- wb stage control
-
- -- data input --
- mem_wb_dat_i => mem_dat_i, -- memory read data
- alu_wb_dat_i => ma_data, -- alu read data
- mem_adr_fb_i => mem_adr_fb, -- memory address feedback
-
- -- data output --
- wb_data_o => wb_data, -- write back data
- wb_fwd_o => wb_fwd -- wb stage forwarding path
- );
-
-
-
-end atlas_cpu_behav;
Index: rtl/ATLAS_2K_BASE_TOP.vhd
===================================================================
--- rtl/ATLAS_2K_BASE_TOP.vhd (revision 37)
+++ rtl/ATLAS_2K_BASE_TOP.vhd (nonexistent)
@@ -1,287 +0,0 @@
--- #########################################################
--- # << ATLAS Project - Basic System >> #
--- # ***************************************************** #
--- # This is the top entity of a simple implementation #
--- # of the ATLAS 2k and a compatible memory component. #
--- # #
--- # The number of pages as well as the page size can be #
--- # configured via constant in the 'USER CONFIGURATION' #
--- # section. Both values must be a number of 2! #
--- # Also, the frequency of the 'CLK_I' signal must be #
--- # declared in this section (in Hz). #
--- # #
--- # ***************************************************** #
--- # Last modified: 28.11.2014 #
--- # ***************************************************** #
--- # by Stephan Nolting 4788, Hanover, Germany #
--- #########################################################
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.atlas_core_package.all;
-
-entity atlas_2k_base_top is
- port (
--- ###############################################################################################
--- ## Global Signals ##
--- ###############################################################################################
-
- clk_i : in std_ulogic; -- global clock line
- rstn_i : in std_ulogic; -- global reset line, low-active
-
--- ###############################################################################################
--- ## IO Interface ##
--- ###############################################################################################
-
- -- uart --
- uart_rxd_i : in std_ulogic; -- receiver input
- uart_txd_o : out std_ulogic; -- uart transmitter output
-
- -- spi --
- spi_mosi_o : out std_ulogic_vector(07 downto 0); -- serial data out
- spi_miso_i : in std_ulogic_vector(07 downto 0); -- serial data in
- spi_sck_o : out std_ulogic_vector(07 downto 0); -- serial clock out
- spi_cs_o : out std_ulogic_vector(07 downto 0); -- chip select (low active)
-
- -- pio --
- pio_out_o : out std_ulogic_vector(15 downto 0); -- parallel output
- pio_in_i : in std_ulogic_vector(15 downto 0); -- parallel input
-
- -- system io (bootloader, nos, ...) --
- sys_out_o : out std_ulogic_vector(07 downto 0); -- system output
- sys_in_i : in std_ulogic_vector(07 downto 0); -- system input
-
--- ###############################################################################################
--- ## Wishbone Bus ##
--- ###############################################################################################
-
- wb_clk_o : out std_ulogic; -- bus clock
- wb_rst_o : out std_ulogic; -- bus reset, sync, high active
- wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
- wb_sel_o : out std_ulogic_vector(01 downto 0); -- byte select
- wb_data_o : out std_ulogic_vector(15 downto 0); -- data out
- wb_data_i : in std_ulogic_vector(15 downto 0); -- data in
- wb_we_o : out std_ulogic; -- read/write
- wb_cyc_o : out std_ulogic; -- cycle enable
- wb_stb_o : out std_ulogic; -- strobe
- wb_ack_i : in std_ulogic; -- acknowledge
- wb_err_i : in std_ulogic -- bus error
- );
-end atlas_2k_base_top;
-
-architecture atlas_2k_base_top_structure of atlas_2k_base_top is
-
- -- Component: Atlas-2K Processor ----------------------------------------------------------
- -- -------------------------------------------------------------------------------------------
- component atlas_2k_top
- generic (
- clk_speed_g : std_ulogic_vector(31 downto 0) := (others => '0') -- clock speed (in hz)
- );
- port (
- clk_i : in std_ulogic; -- global clock line
- rst_i : in std_ulogic; -- global reset line, sync, high-active
- ce_i : in std_ulogic; -- global clock enable, high active
- cp_en_o : out std_ulogic; -- access to cp0
- cp_ice_o : out std_ulogic; -- cp interface clock enable
- cp_op_o : out std_ulogic; -- data transfer/processing
- cp_rw_o : out std_ulogic; -- read/write access
- cp_cmd_o : out std_ulogic_vector(08 downto 0); -- register addresses / cmd
- cp_dat_o : out std_ulogic_vector(data_width_c-1 downto 0); -- write data
- cp_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- read data cp0
- mem_i_page_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction page
- mem_i_adr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction adr
- mem_i_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction input
- mem_d_en_o : out std_ulogic; -- access enable
- mem_d_rw_o : out std_ulogic; -- read/write
- mem_d_page_o : out std_ulogic_vector(data_width_c-1 downto 0); -- data page
- mem_d_adr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- data adr
- mem_d_dat_o : out std_ulogic_vector(data_width_c-1 downto 0); -- data out
- mem_d_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- data in
- critical_irq_i : in std_ulogic; -- critical error irq
- uart_rxd_i : in std_ulogic; -- receiver input
- uart_txd_o : out std_ulogic; -- uart transmitter output
- spi_mosi_o : out std_ulogic_vector(07 downto 0); -- serial data out
- spi_miso_i : in std_ulogic_vector(07 downto 0); -- serial data in
- spi_sck_o : out std_ulogic_vector(07 downto 0); -- serial clock out
- spi_cs_o : out std_ulogic_vector(07 downto 0); -- chip select (low active)
- pio_out_o : out std_ulogic_vector(15 downto 0); -- parallel output
- pio_in_i : in std_ulogic_vector(15 downto 0); -- parallel input
- sys_out_o : out std_ulogic_vector(07 downto 0); -- system parallel output
- sys_in_i : in std_ulogic_vector(07 downto 0); -- system parallel input
- irq_i : in std_ulogic; -- irq
- wb_clk_o : out std_ulogic; -- bus clock
- wb_rst_o : out std_ulogic; -- bus reset, sync, high active
- wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
- wb_sel_o : out std_ulogic_vector(01 downto 0); -- byte select
- wb_data_o : out std_ulogic_vector(15 downto 0); -- data out
- wb_data_i : in std_ulogic_vector(15 downto 0); -- data in
- wb_we_o : out std_ulogic; -- read/write
- wb_cyc_o : out std_ulogic; -- cycle enable
- wb_stb_o : out std_ulogic; -- strobe
- wb_ack_i : in std_ulogic; -- acknowledge
- wb_err_i : in std_ulogic -- bus error
- );
- end component;
-
- -- RAM ------------------------------------------------------------------------------------
- -- -------------------------------------------------------------------------------------------
- component int_ram
- generic (
- mem_size_g : natural := 256 -- memory size in words
- );
- port (
- -- host interface --
- clk_i : in std_ulogic; -- global clock line
- i_adr_i : in std_ulogic_vector(31 downto 0); -- instruction adr
- i_dat_o : out std_ulogic_vector(15 downto 0); -- instruction out
- d_en_i : in std_ulogic; -- access enable
- d_rw_i : in std_ulogic; -- read/write
- d_adr_i : in std_ulogic_vector(31 downto 0); -- data adr
- d_dat_i : in std_ulogic_vector(15 downto 0); -- data in
- d_dat_o : out std_ulogic_vector(15 downto 0) -- data out
- );
- end component;
-
--- *** USER CONFIGURATION ***
--- ***********************************************************************************************
- constant clk_speed_c : std_ulogic_vector(31 downto 0) := x"02FAF080"; -- clock speed in Hz (here =50MHz)
- constant num_pages_c : natural := 4; -- number of pages (must be a power of 2)
- constant page_size_c : natural := 4096; -- page size in bytes (must be a power of 2)
--- ***********************************************************************************************
-
- -- internals... -
- constant ram_size_c : natural := num_pages_c*page_size_c; -- internal ram size in bytes
- constant ld_pg_size_c : natural := log2(page_size_c); -- page select address width
- constant ld_num_pg_c : natural := log2(num_pages_c); -- page size address width
-
- -- global signals --
- signal g_clk : std_ulogic;
- signal g_rst : std_ulogic;
-
- -- memory interface --
- signal i_adr, d_adr : std_ulogic_vector(data_width_c-1 downto 0);
- signal i_page, d_page : std_ulogic_vector(data_width_c-1 downto 0);
- signal d_en : std_ulogic;
- signal d_rw : std_ulogic;
- signal i_dat_o, d_dat_o : std_ulogic_vector(data_width_c-1 downto 0);
- signal d_dat_i : std_ulogic_vector(data_width_c-1 downto 0);
- signal mem_d_adr : std_ulogic_vector(31 downto 0);
- signal mem_i_adr : std_ulogic_vector(31 downto 0);
-
- -- irq --
- signal critical_irq : std_ulogic;
-
-begin
-
- -- Clock/Reset -----------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- g_rst <= not rstn_i;
- g_clk <= clk_i;
-
-
- -- Core ------------------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- the_core_of_the_problem: atlas_2k_top
- generic map (
- clk_speed_g => clk_speed_c -- clock speed (in hz)
- )
- port map (
- clk_i => g_clk, -- global clock line
- rst_i => g_rst, -- global reset line, sync, high-active
- ce_i => '1', -- global clock enable, high active
-
- cp_en_o => open, -- access to cp0
- cp_ice_o => open, -- cp interface clock enable
- cp_op_o => open, -- data transfer/processing
- cp_rw_o => open, -- read/write access
- cp_cmd_o => open, -- register addresses / cmd
- cp_dat_o => open, -- write data
- cp_dat_i => x"0000", -- read data cp0
-
- mem_i_page_o => i_page, -- instruction page
- mem_i_adr_o => i_adr, -- instruction adr
- mem_i_dat_i => i_dat_o, -- instruction input
- mem_d_en_o => d_en, -- access enable
- mem_d_rw_o => d_rw, -- read/write
- mem_d_page_o => d_page, -- data page
- mem_d_adr_o => d_adr, -- data adr
- mem_d_dat_o => d_dat_i, -- data out
- mem_d_dat_i => d_dat_o, -- data in
- critical_irq_i => critical_irq, -- critical error irq
-
- uart_rxd_i => uart_rxd_i, -- receiver input
- uart_txd_o => uart_txd_o, -- uart transmitter output
-
- spi_sck_o => spi_sck_o, -- serial clock output
- spi_mosi_o => spi_mosi_o, -- serial data output
- spi_miso_i => spi_miso_i, -- serial data input
- spi_cs_o => spi_cs_o, -- device select - low-active
-
- pio_out_o => pio_out_o, -- parallel output
- pio_in_i => pio_in_i, -- parallel input
-
- sys_out_o => sys_out_o, -- system parallel output
- sys_in_i => sys_in_i, -- system parallel input
-
- irq_i => '0', -- irq - not used here
-
- wb_clk_o => wb_clk_o, -- bus clock
- wb_rst_o => wb_rst_o, -- bus reset, sync, high active
- wb_adr_o => wb_adr_o, -- address
- wb_sel_o => wb_sel_o, -- byte select
- wb_data_o => wb_data_o, -- data out
- wb_data_i => wb_data_i, -- data in
- wb_we_o => wb_we_o, -- read/write
- wb_cyc_o => wb_cyc_o, -- cycle enable
- wb_stb_o => wb_stb_o, -- strobe
- wb_ack_i => wb_ack_i, -- acknowledge
- wb_err_i => wb_err_i -- bus error
- );
-
-
- -- Memory Mapping --------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- memory_mapping: process(i_page, d_page, i_adr, d_adr)
- begin
- -- default --
- mem_i_adr <= (others => '0');
- mem_d_adr <= (others => '0');
-
- -- page address --
- mem_i_adr(ld_pg_size_c-1 downto 0) <= i_adr(ld_pg_size_c-1 downto 0);
- mem_d_adr(ld_pg_size_c-1 downto 0) <= d_adr(ld_pg_size_c-1 downto 0);
-
- -- page number --
- mem_i_adr((ld_pg_size_c+ld_num_pg_c)-1 downto ld_pg_size_c) <= i_page(ld_num_pg_c-1 downto 0);
- mem_d_adr((ld_pg_size_c+ld_num_pg_c)-1 downto ld_pg_size_c) <= d_page(ld_num_pg_c-1 downto 0);
- end process memory_mapping;
-
-
- -- Internal RAM ----------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- internal_ram: int_ram
- generic map (
- mem_size_g => ram_size_c -- memory size in bytes
- )
- port map (
- -- host interface --
- clk_i => g_clk, -- global clock line
- i_adr_i => mem_i_adr, -- instruction adr
- i_dat_o => i_dat_o, -- instruction out
- d_en_i => d_en, -- access enable
- d_rw_i => d_rw, -- read/write
- d_adr_i => mem_d_adr, -- data adr
- d_dat_i => d_dat_i, -- data in
- d_dat_o => d_dat_o -- data out
- );
-
-
- -- User Section ----------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- critical_irq <= '0';
-
-
-end atlas_2k_base_top_structure;
Index: rtl/REG_FILE.vhd
===================================================================
--- rtl/REG_FILE.vhd (revision 37)
+++ rtl/REG_FILE.vhd (nonexistent)
@@ -1,109 +0,0 @@
--- ########################################################
--- # << ATLAS Project - Data Register File >> #
--- # **************************************************** #
--- # Main data register file, organized in two bank, #
--- # separated for each operating mode. Each bank holds #
--- # 8 16-bit data registers. #
--- # **************************************************** #
--- # Last modified: 28.11.2014 #
--- # **************************************************** #
--- # by Stephan Nolting 4788, Hanover, Germany #
--- ########################################################
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.atlas_core_package.all;
-
-entity reg_file is
- port (
--- ###############################################################################################
--- ## Global Control ##
--- ###############################################################################################
-
- clk_i : in std_ulogic; -- global clock line
- ce_i : in std_ulogic; -- clock enable
- rst_i : in std_ulogic; -- global reset line, sync, high-active
-
--- ###############################################################################################
--- ## Function Control ##
--- ###############################################################################################
-
- wb_ctrl_bus_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- wb stage control
- of_ctrl_bus_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- of stage control
-
--- ###############################################################################################
--- ## Data Input ##
--- ###############################################################################################
-
- wb_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- write back data
- immediate_i : in std_ulogic_vector(data_width_c-1 downto 0); -- immediates
- pc_1d_i : in std_ulogic_vector(data_width_c-1 downto 0); -- pc 1x delayed
- wb_fwd_i : in std_ulogic_vector(fwd_width_c-1 downto 0); -- WB stage forwarding path
-
--- ###############################################################################################
--- ## Data Output ##
--- ###############################################################################################
-
- op_a_data_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand a output
- op_b_data_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand b output
- op_c_data_o : out std_ulogic_vector(data_width_c-1 downto 0) -- operand c output
- );
-end reg_file;
-
-architecture rf_structure of reg_file is
-
- -- register file --
- type reg_file_mem_type is array (2*8-1 downto 0) of std_ulogic_vector(data_width_c-1 downto 0);
- signal reg_file_mem : reg_file_mem_type := (others => (others => '0'));
-
- -- operand multiplexer --
- signal op_a_int : std_ulogic_vector(data_width_c-1 downto 0);
- signal op_b_int : std_ulogic_vector(data_width_c-1 downto 0);
-
-begin
-
- -- Data Register File ----------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- data_register_file: process(clk_i)
- begin
- -- sync write access --
- if rising_edge(clk_i) then
- if (wb_ctrl_bus_i(ctrl_wb_en_c) = '1') and (ce_i = '1') then -- valid write back
- reg_file_mem(to_integer(unsigned(wb_ctrl_bus_i(ctrl_rd_3_c downto ctrl_rd_0_c)))) <= wb_data_i;
- end if;
- end if;
- end process data_register_file;
-
-
- -- Operand Fetch Forwarding Unit -----------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- of_fwd: process(wb_fwd_i, of_ctrl_bus_i, reg_file_mem)
- begin
- -- operand a forwarding --
- if (wb_fwd_i(fwd_en_c) = '1') and (of_ctrl_bus_i(ctrl_ra_3_c downto ctrl_ra_0_c) = wb_fwd_i(fwd_adr_3_c downto fwd_adr_0_c)) then
- op_a_int <= wb_fwd_i(fwd_dat_msb_c downto fwd_dat_lsb_c);
- else
- op_a_int <= reg_file_mem(to_integer(unsigned(of_ctrl_bus_i(ctrl_ra_3_c downto ctrl_ra_0_c))));
- end if;
-
- -- operand b forwarding --
- if (wb_fwd_i(fwd_en_c) = '1') and (of_ctrl_bus_i(ctrl_rb_3_c downto ctrl_rb_0_c) = wb_fwd_i(fwd_adr_3_c downto fwd_adr_0_c)) then
- op_b_int <= wb_fwd_i(fwd_dat_msb_c downto fwd_dat_lsb_c);
- else
- op_b_int <= reg_file_mem(to_integer(unsigned(of_ctrl_bus_i(ctrl_rb_3_c downto ctrl_rb_0_c))));
- end if;
- end process of_fwd;
-
-
- -- Operand Multiplexer ---------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- op_a_data_o <= pc_1d_i when (of_ctrl_bus_i(ctrl_ra_is_pc_c) = '1') else op_a_int;
- op_b_data_o <= immediate_i when (of_ctrl_bus_i(ctrl_rb_is_imm_c) = '1') else op_b_int;
- op_c_data_o <= op_b_int;
-
-
-
-end rf_structure;
Index: rtl/MEM_GATE.vhd
===================================================================
--- rtl/MEM_GATE.vhd (revision 37)
+++ rtl/MEM_GATE.vhd (nonexistent)
@@ -1,105 +0,0 @@
--- ########################################################
--- # << ATLAS Project - Memory Gateway >> #
--- # **************************************************** #
--- # Gateway between CPU instruction/data interface and #
--- # bootloader ROM / memory/IO bus system. #
--- # **************************************************** #
--- # Last modified: 28.11.2014 #
--- # **************************************************** #
--- # by Stephan Nolting 4788, Hanover, Germany #
--- ########################################################
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.atlas_core_package.all;
-
-entity mem_gate is
- port (
- -- host interface --
- clk_i : in std_ulogic; -- global clock line
- rst_i : in std_ulogic; -- global reset line, sync, high-active
-
- i_adr_i : in std_ulogic_vector(15 downto 0); -- instruction adr
- i_dat_o : out std_ulogic_vector(15 downto 0); -- instruction out
- d_req_i : in std_ulogic; -- request access in next cycle
- d_rw_i : in std_ulogic; -- read/write
- d_adr_i : in std_ulogic_vector(15 downto 0); -- data adr
- d_dat_i : in std_ulogic_vector(15 downto 0); -- data in
- d_dat_o : out std_ulogic_vector(15 downto 0); -- data out
- mem_ip_adr_i : in std_ulogic_vector(15 downto 0); -- instruction page
- mem_dp_adr_i : in std_ulogic_vector(15 downto 0); -- data page
-
- -- boot rom interface --
- boot_i_adr_o : out std_ulogic_vector(15 downto 0); -- instruction adr
- boot_i_dat_i : in std_ulogic_vector(15 downto 0); -- instruction out
- boot_d_en_o : out std_ulogic; -- access enable
- boot_d_rw_o : out std_ulogic; -- read/write
- boot_d_adr_o : out std_ulogic_vector(15 downto 0); -- data adr
- boot_d_dat_o : out std_ulogic_vector(15 downto 0); -- data in
- boot_d_dat_i : in std_ulogic_vector(15 downto 0); -- data out
-
- -- memory interface --
- mem_i_page_o : out std_ulogic_vector(15 downto 0); -- instruction page
- mem_i_adr_o : out std_ulogic_vector(15 downto 0); -- instruction adr
- mem_i_dat_i : in std_ulogic_vector(15 downto 0); -- instruction out
- mem_d_en_o : out std_ulogic; -- access enable
- mem_d_rw_o : out std_ulogic; -- read/write
- mem_d_page_o : out std_ulogic_vector(15 downto 0); -- data page
- mem_d_adr_o : out std_ulogic_vector(15 downto 0); -- data adr
- mem_d_dat_o : out std_ulogic_vector(15 downto 0); -- data in
- mem_d_dat_i : in std_ulogic_vector(15 downto 0) -- data out
- );
-end mem_gate;
-
-architecture mem_gate_behav of mem_gate is
-
- -- local signals --
- signal mem_dacc_ff : std_ulogic;
- signal d_gate_sel : std_ulogic;
- signal i_gate_sel : std_ulogic;
-
-begin
-
- -- Gateway ---------------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- mem_acc_flag: process(clk_i)
- begin
- if rising_edge(clk_i) then
- if (rst_i = '1') then
- mem_dacc_ff <= '0';
- else
- mem_dacc_ff <= d_req_i;
- end if;
- end if;
- end process mem_acc_flag;
-
- -- switch --
- i_gate_sel <= '1' when (mem_ip_adr_i(15) = boot_page_c(15)) else '0';
- d_gate_sel <= '1' when (mem_dp_adr_i(15) = boot_page_c(15)) else '0';
-
- -- bootloader rom --
- boot_i_adr_o <= i_adr_i;
- boot_d_en_o <= mem_dacc_ff when (d_gate_sel = '1') else '0';
- boot_d_adr_o <= d_adr_i when (mem_dacc_ff = '1') and (d_gate_sel = '1') else (others => '0'); -- to reduce switching activity
- boot_d_dat_o <= d_dat_i when (mem_dacc_ff = '1') and (d_gate_sel = '1') else (others => '0'); -- to reduce switching activity
- boot_d_rw_o <= d_rw_i;
-
- -- memory system --
- mem_i_page_o <= '0' & mem_ip_adr_i(14 downto 0);
- mem_i_adr_o <= i_adr_i;
- mem_d_en_o <= mem_dacc_ff when (d_gate_sel = '0') else '0';
- mem_d_page_o <= '0' & mem_dp_adr_i(14 downto 0);
- mem_d_adr_o <= d_adr_i when (mem_dacc_ff = '1') and (d_gate_sel = '0') else (others => '0'); -- to reduce switching activity
- mem_d_dat_o <= d_dat_i when (mem_dacc_ff = '1') and (d_gate_sel = '0') else (others => '0'); -- to reduce switching activity
- mem_d_rw_o <= d_rw_i;
-
- -- cpu --
- i_dat_o <= boot_i_dat_i when (i_gate_sel = '1') else mem_i_dat_i;
- d_dat_o <= boot_d_dat_i when (d_gate_sel = '1') else mem_d_dat_i;
-
-
-
-end mem_gate_behav;
Index: rtl/ALU.vhd
===================================================================
--- rtl/ALU.vhd (revision 37)
+++ rtl/ALU.vhd (nonexistent)
@@ -1,452 +0,0 @@
--- ########################################################
--- # << ATLAS Project - Arithmetical/Logical Unit >> #
--- # **************************************************** #
--- # The main data processing is done here. Also the CP #
--- # interface emerges from this unit. #
--- # **************************************************** #
--- # Last modified: 28.11.2014 #
--- # **************************************************** #
--- # by Stephan Nolting 4788, Hanover, Germany #
--- ########################################################
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.atlas_core_package.all;
-
-entity alu is
- port (
--- ###############################################################################################
--- ## Global Control ##
--- ###############################################################################################
-
- clk_i : in std_ulogic; -- global clock line
- ce_i : in std_ulogic; -- clock enable
- rst_i : in std_ulogic; -- global reset line, sync, high-active
-
--- ###############################################################################################
--- ## Function Control ##
--- ###############################################################################################
-
- ex_ctrl_bus_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- stage control
- flag_bus_i : in std_ulogic_vector(flag_bus_width_c-1 downto 0); -- flag input
-
--- ###############################################################################################
--- ## Data Input ##
--- ###############################################################################################
-
- op_a_i : in std_ulogic_vector(data_width_c-1 downto 0); -- operand a input
- op_b_i : in std_ulogic_vector(data_width_c-1 downto 0); -- operand b input
- op_c_i : in std_ulogic_vector(data_width_c-1 downto 0); -- operand c input
-
- pc_1d_i : in std_ulogic_vector(data_width_c-1 downto 0); -- 1x delayed pc
-
- ma_fwd_i : in std_ulogic_vector(fwd_width_c-1 downto 0); -- ma stage forwarding path
- wb_fwd_i : in std_ulogic_vector(fwd_width_c-1 downto 0); -- wb stage forwarding path
-
--- ###############################################################################################
--- ## Data Output ##
--- ###############################################################################################
-
- flag_bus_o : out std_ulogic_vector(flag_bus_width_c-1 downto 0); -- flag output
- mask_t_flag_o : out std_ulogic; -- t-flag for mask generation
-
- msr_data_o : out std_ulogic_vector(data_width_c-1 downto 0); -- msr write data
- alu_res_o : out std_ulogic_vector(data_width_c-1 downto 0); -- alu result
- mul_res_o : out std_ulogic_vector(2*data_width_c-1 downto 0); -- mul result
- bp_opa_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand a bypass
- bp_opc_o : out std_ulogic_vector(data_width_c-1 downto 0); -- operand c bypass
-
- cp_cp0_en_o : out std_ulogic; -- access to cp0
- cp_cp1_en_o : out std_ulogic; -- access to cp1
- cp_op_o : out std_ulogic; -- data transfer/operation
- cp_rw_o : out std_ulogic; -- read/write access
- cp_cmd_o : out std_ulogic_vector(cp_cmd_width_c-1 downto 0); -- register addresses / cmd
- cp_dat_o : out std_ulogic_vector(data_width_c-1 downto 0); -- write data
-
- mem_req_o : out std_ulogic -- data memory access request for next cycle
- );
-end alu;
-
-architecture alu_structure of alu is
-
- -- pipeline register --
- signal op_a_ff : std_ulogic_vector(data_width_c-1 downto 0);
- signal op_b_ff : std_ulogic_vector(data_width_c-1 downto 0);
- signal op_c_ff : std_ulogic_vector(data_width_c-1 downto 0);
-
- -- functional units output --
- signal fu_arith_res : std_ulogic_vector(data_width_c-1 downto 0);
- signal fu_arith_flg : std_ulogic_vector(1 downto 0); -- overflow & carry
- signal fu_logic_res : std_ulogic_vector(data_width_c-1 downto 0);
- signal fu_logic_flg : std_ulogic_vector(1 downto 0);
- signal fu_shift_res : std_ulogic_vector(data_width_c-1 downto 0);
- signal fu_shift_flg : std_ulogic_vector(1 downto 0);
-
- -- internal data lines --
- signal op_a_int : std_ulogic_vector(data_width_c-1 downto 0);
- signal op_b_int : std_ulogic_vector(data_width_c-1 downto 0);
- signal op_c_int : std_ulogic_vector(data_width_c-1 downto 0);
- signal alu_res_int : std_ulogic_vector(data_width_c-1 downto 0);
- signal t_flag_func : std_ulogic;
- signal parity_bit : std_ulogic;
- signal transf_int : std_ulogic;
- signal sel_bit : std_ulogic;
- signal inv_bit : std_ulogic;
- signal is_zero : std_ulogic;
- signal extnd_zero : std_ulogic;
-
- -- multiplier --
- signal mul_op_a : std_ulogic_vector(data_width_c-1 downto 0);
- signal mul_op_b : std_ulogic_vector(data_width_c-1 downto 0);
-
-begin
-
- -- Pipeline Register -----------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- pipe_reg: process(clk_i)
- begin
- if rising_edge(clk_i) then
- if (rst_i = '1') then
- op_a_ff <= (others => '0');
- op_b_ff <= (others => '0');
- op_c_ff <= (others => '0');
- elsif (ce_i = '1') then
- op_a_ff <= op_a_i;
- op_b_ff <= op_b_i;
- op_c_ff <= op_c_i;
- end if;
- end if;
- end process pipe_reg;
-
-
- -- Execution Forwarding Unit ---------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- ex_fwd: process(ma_fwd_i, wb_fwd_i, ex_ctrl_bus_i, op_a_ff, op_b_ff, op_c_ff)
- variable op_a_ma_match_v : std_ulogic;
- variable op_b_ma_match_v : std_ulogic;
- variable op_a_wb_match_v : std_ulogic;
- variable op_b_wb_match_v : std_ulogic;
- variable op_c_wb_match_v : std_ulogic;
- variable op_a_tmp_v : std_ulogic_vector(data_width_c-1 downto 0);
- begin
-
- -- data from early stages -> higher priority than data from later stages
- -- no forwarding when op_a is the pc
- -- no forwarding when op_b is an immediate
-
- -- local data dependency detectors --
- op_a_ma_match_v := '0';
- if (ma_fwd_i(fwd_en_c) = '1') and (ex_ctrl_bus_i(ctrl_ra_is_pc_c) = '0') and (ex_ctrl_bus_i(ctrl_ra_3_c downto ctrl_ra_0_c) = ma_fwd_i(fwd_adr_3_c downto fwd_adr_0_c)) then
- op_a_ma_match_v := '1';
- end if;
- op_a_wb_match_v := '0';
- if (wb_fwd_i(fwd_en_c) = '1') and (ex_ctrl_bus_i(ctrl_ra_is_pc_c) = '0') and (ex_ctrl_bus_i(ctrl_ra_3_c downto ctrl_ra_0_c) = wb_fwd_i(fwd_adr_3_c downto fwd_adr_0_c)) then
- op_a_wb_match_v := '1';
- end if;
-
- op_b_ma_match_v := '0';
- if (ma_fwd_i(fwd_en_c) = '1') and (ex_ctrl_bus_i(ctrl_rb_is_imm_c) = '0') and (ex_ctrl_bus_i(ctrl_rb_3_c downto ctrl_rb_0_c) = ma_fwd_i(fwd_adr_3_c downto fwd_adr_0_c)) then
- op_b_ma_match_v := '1';
- end if;
- op_b_wb_match_v := '0';
- if (wb_fwd_i(fwd_en_c) = '1') and (ex_ctrl_bus_i(ctrl_rb_is_imm_c) = '0') and (ex_ctrl_bus_i(ctrl_rb_3_c downto ctrl_rb_0_c) = wb_fwd_i(fwd_adr_3_c downto fwd_adr_0_c)) then
- op_b_wb_match_v := '1';
- end if;
-
- op_c_wb_match_v := '0';
- if (wb_fwd_i(fwd_en_c) = '1') and (ex_ctrl_bus_i(ctrl_rb_3_c downto ctrl_rb_0_c) = wb_fwd_i(fwd_adr_3_c downto fwd_adr_0_c)) then
- op_c_wb_match_v := '1';
- end if;
-
- -- op a gating --
- if (ex_ctrl_bus_i(ctrl_en_c) = '1') then
- -- op a forwarding --
- if (op_a_ma_match_v = '1') then
- op_a_tmp_v := ma_fwd_i(fwd_dat_msb_c downto fwd_dat_lsb_c); -- ma stage
- elsif (op_a_wb_match_v = '1') then
- op_a_tmp_v := wb_fwd_i(fwd_dat_msb_c downto fwd_dat_lsb_c); -- wb stage
- else
- op_a_tmp_v := op_a_ff;
- end if;
- else
- op_a_tmp_v := (others => '0');
- end if;
-
- -- op a mask unit --
- op_a_int <= op_a_tmp_v;
- if (ex_ctrl_bus_i(ctrl_clr_ha_c) = '1') then -- clear high half word
- op_a_int(data_width_c-1 downto data_width_c/2) <= (others => '0');
- end if;
- if (ex_ctrl_bus_i(ctrl_clr_la_c) = '1') then -- clear low half word
- op_a_int(data_width_c/2-1 downto 0) <= (others => '0');
- end if;
-
- -- op b gating --
- if (ex_ctrl_bus_i(ctrl_en_c) = '1') then
- -- op b forwarding --
- if (op_b_ma_match_v = '1') then
- op_b_int <= ma_fwd_i(fwd_dat_msb_c downto fwd_dat_lsb_c); -- ma stage
- elsif (op_b_wb_match_v = '1') then
- op_b_int <= wb_fwd_i(fwd_dat_msb_c downto fwd_dat_lsb_c); -- wb stage
- else
- op_b_int <= op_b_ff;
- end if;
- else
- op_b_int <= (others => '0');
- end if;
-
- -- op c forwarding --
- if (op_c_wb_match_v = '1') then
- op_c_int <= wb_fwd_i(fwd_dat_msb_c downto fwd_dat_lsb_c); -- wb stage
- else
- op_c_int <= op_c_ff;
- end if;
-
- end process ex_fwd;
-
-
- -- Functional Unit: Arithmetic Core --------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- fu_arithmetic_core: process(ex_ctrl_bus_i, op_a_int, op_b_int, flag_bus_i)
- variable op_a_v, op_b_v : std_ulogic_vector(data_width_c-1 downto 0);
- variable cflag_v : std_ulogic;
- variable add_a_v, add_b_v : std_ulogic_vector(data_width_c downto 0);
- variable add_cf_in_v : std_ulogic_vector(0 downto 0);
- variable adder_c_sel_v : std_ulogic;
- variable adder_carry_in_v : std_ulogic;
- variable adder_tmp_v : std_ulogic_vector(data_width_c downto 0);
- begin
-
- -- operand insulation --
- op_a_v := (others => '0');
- op_b_v := (others => '0');
- cflag_v := '0';
- if (ex_ctrl_bus_i(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) = alu_adc_c) or
- (ex_ctrl_bus_i(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) = alu_sbc_c) then
- op_a_v := op_a_int;
- op_b_v := op_b_int;
- cflag_v := flag_bus_i(flag_c_c);
- end if;
-
- -- add/sub select --
- if (ex_ctrl_bus_i(ctrl_alu_cf_opt_c) = '0') then -- propagate carry_in
- adder_c_sel_v := cflag_v;
- else -- invert carry_in
- adder_c_sel_v := not cflag_v;
- end if;
- add_a_v := '0' & op_a_v;
- adder_carry_in_v := adder_c_sel_v and ex_ctrl_bus_i(ctrl_alu_usec_c);
- case (ex_ctrl_bus_i(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c)) is
- when alu_sbc_c => -- (+op_a) + (-op_b) {+ (-carry)}
- add_b_v := '0' & (not op_b_v);
- add_cf_in_v(0) := not adder_carry_in_v;
- when alu_adc_c => -- (+op_a) + (+op_b) {+ (+carry)}
- add_b_v := '0' & op_b_v;
- add_cf_in_v(0) := adder_carry_in_v;
- when others => -- other function set, adder irrelevant
- add_b_v := '0' & op_b_v;
- add_cf_in_v(0) := adder_carry_in_v;
- end case;
-
- -- adder core --
- adder_tmp_v := std_ulogic_vector(unsigned(add_a_v) + unsigned(add_b_v) + unsigned(add_cf_in_v(0 downto 0)));
- fu_arith_res <= adder_tmp_v(data_width_c-1 downto 0); -- result, msb of adder_tmp_v is carry bit
-
- -- adder flag carry output logic --
- case (ex_ctrl_bus_i(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c)) is
- when alu_adc_c => -- add
- fu_arith_flg(0) <= adder_tmp_v(data_width_c);
- when alu_sbc_c => -- sub
- fu_arith_flg(0) <= not adder_tmp_v(data_width_c);
- when others => -- other function set, adder irrelevant
- fu_arith_flg(0) <= adder_tmp_v(data_width_c);
- end case;
-
- -- arithmetic overflow flag --
- fu_arith_flg(1) <= ((not add_a_v(data_width_c-1)) and (not add_b_v(data_width_c-1)) and ( adder_tmp_v(data_width_c-1))) or
- (( add_a_v(data_width_c-1)) and ( add_b_v(data_width_c-1)) and (not adder_tmp_v(data_width_c-1)));
- end process fu_arithmetic_core;
-
-
- -- Functional Unit: Shifter Core -----------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- fu_shifter_core: process(ex_ctrl_bus_i, op_a_int, op_b_ff, flag_bus_i)
- variable op_a_v, op_b_v : std_ulogic_vector(data_width_c-1 downto 0);
- variable cflag_v : std_ulogic;
- variable shifter_dat_v : std_ulogic_vector(data_width_c-1 downto 0);
- variable shifter_carry_v : std_ulogic;
- variable shifter_ovf_v : std_ulogic;
- begin
-
- -- operand insulation --
- op_a_v := (others => '0');
- op_b_v := (others => '0');
- cflag_v := '0';
- if (ex_ctrl_bus_i(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) = alu_sft_c) then
- op_a_v := op_a_int;
- op_b_v := op_b_ff;
- cflag_v := flag_bus_i(flag_c_c);
- end if;
-
- -- shifter core --
- case (op_b_v(2 downto 0)) is
- when sft_asr_c => -- arithmetical right shift
- shifter_dat_v := op_a_v(data_width_c-1) & op_a_v(data_width_c-1 downto 1);
- fu_shift_flg(0) <= op_a_v(0);
- when sft_rol_c => -- rotate left
- shifter_dat_v := op_a_v(data_width_c-2 downto 0) & op_a_v(data_width_c-1);
- fu_shift_flg(0) <= op_a_v(data_width_c-1);
- when sft_ror_c => -- rotate right
- shifter_dat_v := op_a_v(0) & op_a_v(data_width_c-1 downto 1);
- fu_shift_flg(0) <= op_a_v(0);
- when sft_lsl_c => -- logical shift left
- shifter_dat_v := op_a_v(data_width_c-2 downto 0) & '0';
- fu_shift_flg(0) <= op_a_v(data_width_c-1);
- when sft_lsr_c => -- logical shift right
- shifter_dat_v := '0' & op_a_v(data_width_c-1 downto 1);
- fu_shift_flg(0) <= op_a_v(0);
- when sft_rlc_c => -- rotate left through carry
- shifter_dat_v := op_a_v(data_width_c-2 downto 0) & cflag_v;
- fu_shift_flg(0) <= op_a_v(data_width_c-1);
- when sft_rrc_c => -- rotate right through carry
- shifter_dat_v := cflag_v & op_a_v(data_width_c-1 downto 1);
- fu_shift_flg(0) <= op_a_v(0);
- when others => -- swap halfwords (sft_swp_c)
- shifter_dat_v := op_a_v(data_width_c/2-1 downto 0) & op_a_v(data_width_c-1 downto data_width_c/2);
- fu_shift_flg(0) <= op_a_v(data_width_c-1);
- end case;
- fu_shift_res <= shifter_dat_v;
-
- -- overflow flag --
- fu_shift_flg(1) <= op_a_v(data_width_c-1) xor shifter_dat_v(data_width_c-1);
-
- end process fu_shifter_core;
-
-
- -- Functional Unit: Logical Core -----------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- fu_logic_core: process(ex_ctrl_bus_i, op_a_int, op_b_int, flag_bus_i)
- begin
- -- keep flags --
- fu_logic_flg(0) <= flag_bus_i(flag_c_c);
- fu_logic_flg(1) <= flag_bus_i(flag_o_c);
-
- -- logic function --
- case (ex_ctrl_bus_i(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c)) is
- when alu_and_c => fu_logic_res <= op_a_int and op_b_int;
- when alu_nand_c => fu_logic_res <= op_a_int nand op_b_int;
- when alu_orr_c => fu_logic_res <= op_a_int or op_b_int;
- when alu_eor_c => fu_logic_res <= op_a_int xor op_b_int;
- when alu_bic_c => fu_logic_res <= op_a_int and (not op_b_int);
- when others => fu_logic_res <= (others => '0');
- fu_logic_flg(0) <= '0';
- fu_logic_flg(1) <= '0';
- end case;
- end process fu_logic_core;
-
-
- -- Function Selector -----------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- -- data result --
- alu_res_int <= fu_arith_res or fu_shift_res or fu_logic_res;
-
- -- carry flag --
- flag_bus_o(flag_c_c) <= fu_arith_flg(0) or fu_shift_flg(0) or fu_logic_flg(0);
-
- -- overflow flag --
- flag_bus_o(flag_o_c) <= fu_arith_flg(1) or fu_shift_flg(1) or fu_logic_flg(0);
-
-
- -- Parity Computation ----------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- parity_gen: process(op_a_int)
- variable par_v : std_ulogic;
- begin
- par_v := '0';
- for i in 0 to data_width_c-1 loop
- par_v := par_v xor op_a_int(i);
- end loop;
- parity_bit <= par_v;
- end process parity_gen;
-
-
- -- Additional Flag Computation -------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
-
- -- zero detector --
- -- ladies and gentleman, the critical path!
- is_zero <= '1' when (to_integer(unsigned(alu_res_int)) = 0) else '0'; -- zero detector
- extnd_zero <= (flag_bus_i(flag_z_c) and is_zero) when (ex_ctrl_bus_i(ctrl_alu_zf_opt_c) = '0') else (flag_bus_i(flag_z_c) or is_zero); -- extended zero detector
- flag_bus_o(flag_z_c) <= extnd_zero when (ex_ctrl_bus_i(ctrl_alu_usez_c) = '1') else is_zero; -- (extended) zero flag
-
- -- negative flag --
- flag_bus_o(flag_n_c) <= alu_res_int(data_width_c-1); -- negative flag
-
- -- t-flag update --
- sel_bit <= op_a_int(to_integer(unsigned(op_b_int(3 downto 0)))); -- selected bit
- t_flag_func <= parity_bit when (ex_ctrl_bus_i(ctrl_get_par_c) = '1') else sel_bit; -- parity or selected bit
- inv_bit <= (not t_flag_func) when (ex_ctrl_bus_i(ctrl_tf_inv_c) = '1') else t_flag_func; -- invert bit?
- transf_int <= inv_bit when (ex_ctrl_bus_i(ctrl_tf_store_c) = '1') else flag_bus_i(flag_t_c); -- transfer flag
- flag_bus_o(flag_t_c) <= transf_int;
-
- -- t-flag for mask generation (this is some kind of forwarding to the opcode decoder) --
- mask_t_flag_o <= transf_int when (ex_ctrl_bus_i(ctrl_en_c) = '1') and (ex_ctrl_bus_i(ctrl_tf_store_c) = '1') else flag_bus_i(flag_t_c);
-
-
- -- Multiplier Kernel (signed) --------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- -- operand gating --
- mul_op_a <= op_a_int when (ex_ctrl_bus_i(ctrl_use_mul_c) = '1') else (others => '0');
- mul_op_b <= op_b_int when (ex_ctrl_bus_i(ctrl_use_mul_c) = '1') else (others => '0');
-
- -- multiplier core (signed!) --
- mul_buffer: process(clk_i)
- begin
- if rising_edge(clk_i) then
- if (rst_i = '1') then
- mul_res_o <= (others => '0');
- elsif (ce_i = '1') then
- if (build_mul_c = true) then
- if (signed_mul_c = true) then
- mul_res_o <= std_ulogic_vector(signed(mul_op_a) * signed(mul_op_b));
- else
- mul_res_o <= std_ulogic_vector(unsigned(mul_op_a) * unsigned(mul_op_b));
- end if;
- else
- mul_res_o <= (others => '0');
- end if;
- end if;
- end if;
- end process mul_buffer;
-
-
- -- Module Data Output ----------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
-
- -- coprocessor interface --
- cp_cp0_en_o <= ex_ctrl_bus_i(ctrl_en_c) and ex_ctrl_bus_i(ctrl_cp_acc_c) and (not ex_ctrl_bus_i(ctrl_cp_id_c)); -- cp 0 access
- cp_cp1_en_o <= ex_ctrl_bus_i(ctrl_en_c) and ex_ctrl_bus_i(ctrl_cp_acc_c) and ex_ctrl_bus_i(ctrl_cp_id_c); -- cp 1 access
- cp_op_o <= ex_ctrl_bus_i(ctrl_cp_trans_c); -- data transfer / cp operation
- cp_dat_o <= op_a_int; -- data output
- cp_rw_o <= ex_ctrl_bus_i(ctrl_cp_wr_c); -- read/write transfer
- cp_cmd_o(cp_op_a_msb_c downto cp_op_a_lsb_c) <= ex_ctrl_bus_i(ctrl_cp_rd_2_c downto ctrl_cp_rd_0_c) when (ex_ctrl_bus_i(ctrl_cp_acc_c) = '1') else (others => '0'); -- cp destination / op a reg
- cp_cmd_o(cp_op_b_msb_c downto cp_op_b_lsb_c) <= ex_ctrl_bus_i(ctrl_cp_ra_2_c downto ctrl_cp_ra_0_c) when (ex_ctrl_bus_i(ctrl_cp_acc_c) = '1') else (others => '0'); -- cp op b reg
- cp_cmd_o(cp_cmd_msb_c downto cp_cmd_lsb_c) <= ex_ctrl_bus_i(ctrl_cp_cmd_2_c downto ctrl_cp_cmd_0_c) when (ex_ctrl_bus_i(ctrl_cp_acc_c) = '1') else (others => '0'); -- cp command
-
- -- data output --
- msr_data_o <= op_b_int; -- msr write data
- alu_res_o <= alu_res_int; -- alu result
- bp_opa_o <= op_a_int; -- operand a bypass out (address base for mem access)
-
- -- link_address/mem_w_data port --
- bp_opc_o <= pc_1d_i when (ex_ctrl_bus_i(ctrl_link_c) = '1') else op_c_int; -- operand c bypass out (data for mem write access) or link address
-
- -- memory system --
- mem_req_o <= ex_ctrl_bus_i(ctrl_en_c) and ex_ctrl_bus_i(ctrl_mem_acc_c); -- mem access in next cycle
-
-
-
-end alu_structure;
Index: rtl/ATLAS_2K_TOP.vhd
===================================================================
--- rtl/ATLAS_2K_TOP.vhd (revision 37)
+++ rtl/ATLAS_2K_TOP.vhd (nonexistent)
@@ -1,329 +0,0 @@
--- ########################################################
--- # << ATLAS Project - ATLAS 2k Processor >> #
--- # **************************************************** #
--- # This is the top entity oth ATLAS 2k processor. #
--- # See the core's data sheet for more information. #
--- # **************************************************** #
--- # Last modified: 28.11.2014 #
--- # **************************************************** #
--- # by Stephan Nolting 4788, Hanover, Germany #
--- ########################################################
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.atlas_core_package.all;
-
-entity atlas_2k_top is
--- ###############################################################################################
--- ## Configuration ##
--- ###############################################################################################
- generic (
- clk_speed_g : std_ulogic_vector(31 downto 0) := x"00000000" -- clock speed (in Hz)
- );
--- ###############################################################################################
--- ## Global Control ##
--- ###############################################################################################
- port (
- clk_i : in std_ulogic; -- global clock line
- rst_i : in std_ulogic; -- global reset line, sync, high-active
- ce_i : in std_ulogic; -- global clock enable, high active
-
--- ###############################################################################################
--- ## Coprocessor Interface ##
--- ###############################################################################################
-
- cp_en_o : out std_ulogic; -- access to cp0
- cp_ice_o : out std_ulogic; -- cp interface clock enable
- cp_op_o : out std_ulogic; -- data transfer/processing
- cp_rw_o : out std_ulogic; -- read/write access
- cp_cmd_o : out std_ulogic_vector(08 downto 0); -- register addresses / cmd
- cp_dat_o : out std_ulogic_vector(data_width_c-1 downto 0); -- write data
- cp_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- read data cp0
-
--- ###############################################################################################
--- ## Memory Interface ##
--- ###############################################################################################
-
- mem_i_page_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction page
- mem_i_adr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction adr
- mem_i_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction input
-
- mem_d_en_o : out std_ulogic; -- access enable
- mem_d_rw_o : out std_ulogic; -- read/write
- mem_d_page_o : out std_ulogic_vector(data_width_c-1 downto 0); -- data page
- mem_d_adr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- data adr
- mem_d_dat_o : out std_ulogic_vector(data_width_c-1 downto 0); -- data out
- mem_d_dat_i : in std_ulogic_vector(data_width_c-1 downto 0); -- data in
-
- critical_irq_i : in std_ulogic; -- critical error irq
-
--- ###############################################################################################
--- ## IO Interface ##
--- ###############################################################################################
-
- -- uart --
- uart_rxd_i : in std_ulogic; -- uart receiver input
- uart_txd_o : out std_ulogic; -- uart transmitter output
-
- -- spi --
- spi_mosi_o : out std_ulogic_vector(07 downto 0); -- serial data out
- spi_miso_i : in std_ulogic_vector(07 downto 0); -- serial data in
- spi_sck_o : out std_ulogic_vector(07 downto 0); -- serial clock out
- spi_cs_o : out std_ulogic_vector(07 downto 0); -- chip select (low active)
-
- -- parallel io --
- pio_out_o : out std_ulogic_vector(15 downto 0); -- parallel output
- pio_in_i : in std_ulogic_vector(15 downto 0); -- parallel input
-
- -- system io --
- sys_out_o : out std_ulogic_vector(07 downto 0); -- system output
- sys_in_i : in std_ulogic_vector(07 downto 0); -- system input
-
- -- irqs --
- irq_i : in std_ulogic; -- irq
-
--- ###############################################################################################
--- ## Wishbone Bus ##
--- ###############################################################################################
-
- wb_clk_o : out std_ulogic; -- bus clock
- wb_rst_o : out std_ulogic; -- bus reset, sync, high active
- wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
- wb_sel_o : out std_ulogic_vector(01 downto 0); -- byte select
- wb_data_o : out std_ulogic_vector(15 downto 0); -- data out
- wb_data_i : in std_ulogic_vector(15 downto 0); -- data in
- wb_we_o : out std_ulogic; -- read/write
- wb_cyc_o : out std_ulogic; -- cycle enable
- wb_stb_o : out std_ulogic; -- strobe
- wb_ack_i : in std_ulogic; -- acknowledge
- wb_err_i : in std_ulogic -- bus error
- );
-end atlas_2k_top;
-
-architecture atlas_2k_top_behav of atlas_2k_top is
-
- -- global control --
- signal sys_mode : std_ulogic; -- current processor mode
- signal sys_int_exe : std_ulogic; -- processing irq
-
- -- coprocessor signals --
- signal usr_cp_en : std_ulogic; -- access user coprocessor
- signal sys_cp_en : std_ulogic; -- access system coprocessor
- signal cp_op : std_ulogic; -- transfer/data processing
- signal cp_rw : std_ulogic; -- read/write access
- signal cp_cmd : std_ulogic_vector(08 downto 0); -- register addresses / cmd
- signal cp_w_data : std_ulogic_vector(data_width_c-1 downto 0); -- write data
- signal sys_cp_drb : std_ulogic_vector(data_width_c-1 downto 0); -- system coprocessor data readback
- signal cp_data_rb : std_ulogic_vector(data_width_c-1 downto 0); -- coprocessor data readback
-
- -- cpu bus --
- signal cpu_d_req : std_ulogic; -- data access request
- signal cpu_d_rw : std_ulogic; -- read/write access
- signal cpu_d_adr : std_ulogic_vector(data_width_c-1 downto 0); -- access address
- signal cpu_d_w_data : std_ulogic_vector(data_width_c-1 downto 0); -- write data
- signal cpu_d_r_data : std_ulogic_vector(data_width_c-1 downto 0); -- read data
- signal cpu_i_adr : std_ulogic_vector(data_width_c-1 downto 0); -- instruction address
- signal cpu_i_data : std_ulogic_vector(data_width_c-1 downto 0); -- instruction word
- signal cp_dat_i_sync : std_ulogic_vector(data_width_c-1 downto 0); -- external input sync
-
- -- mmu --
- signal i_page : std_ulogic_vector(data_width_c-1 downto 0); -- instruction page
- signal d_page : std_ulogic_vector(data_width_c-1 downto 0); -- data page
-
- -- boot mem --
- signal boot_i_adr : std_ulogic_vector(15 downto 0); -- instruction adr
- signal boot_i_dat : std_ulogic_vector(15 downto 0); -- instruction out
- signal boot_d_en : std_ulogic; -- access enable
- signal boot_d_rw : std_ulogic; -- read/write
- signal boot_d_adr : std_ulogic_vector(15 downto 0); -- data adr
- signal boot_d_dat_o : std_ulogic_vector(15 downto 0); -- data in
- signal boot_d_dat_i : std_ulogic_vector(15 downto 0); -- data out
-
- -- irq lines --
- signal sys_cp_irq : std_ulogic; -- irq from system coprocessor
-
-begin
-
- -- Atlas CPU Core --------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- cpu_core: atlas_cpu
- port map (
- -- global control --
- clk_i => clk_i, -- global clock line
- rst_i => rst_i, -- global reset line, sync, high-active
- ce_i => ce_i, -- clock enable
-
- -- instruction interface --
- instr_adr_o => cpu_i_adr, -- instruction byte adr
- instr_dat_i => cpu_i_data, -- instruction input
-
- -- data interface --
- sys_mode_o => sys_mode, -- current operating mode
- sys_int_o => sys_int_exe, -- interrupt processing
- mem_req_o => cpu_d_req, -- mem access in next cycle
- mem_rw_o => cpu_d_rw, -- read write
- mem_adr_o => cpu_d_adr, -- data byte adr
- mem_dat_o => cpu_d_w_data, -- write data
- mem_dat_i => cpu_d_r_data, -- read data
-
- -- coprocessor interface --
- usr_cp_en_o => usr_cp_en, -- access to cp0
- sys_cp_en_o => sys_cp_en, -- access to cp1
- cp_op_o => cp_op, -- data transfer/processing
- cp_rw_o => cp_rw, -- read/write access
- cp_cmd_o => cp_cmd, -- register addresses / cmd
- cp_dat_o => cp_w_data, -- write data
- cp_dat_i => cp_data_rb, -- read data cp0 or cp1
-
- -- interrupt lines --
- ext_int_0_i => critical_irq_i, -- critical error irq
- ext_int_1_i => sys_cp_irq -- sys cp irq
- );
-
- -- external cp data in sync --
- cp_dat_in_sync: process (clk_i)
- begin
- if rising_edge(clk_i) then
- if (rst_i = '1') then
- cp_dat_i_sync <= (others => '0');
- elsif (ce_i = '1') then
- if (usr_cp_en = '1') then
- cp_dat_i_sync <= cp_dat_i;
- else
- cp_dat_i_sync <= (others => '0');
- end if;
- end if;
- end if;
- end process cp_dat_in_sync;
-
- -- external coprocessor interface --
- cp_en_o <= usr_cp_en;
- cp_op_o <= cp_op;
- cp_rw_o <= cp_rw;
- cp_cmd_o <= cp_cmd;
- cp_dat_o <= cp_w_data;
- cp_data_rb <= sys_cp_drb or cp_dat_i_sync;
- cp_ice_o <= ce_i;
-
-
- -- System Coprocessor ----------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- system_coprocessor: system_cp
- generic map (
- clock_speed_g => clk_speed_g -- clock speed in hz
- )
- port map (
- -- global control --
- clk_i => clk_i, -- global clock line
- rst_i => rst_i, -- global reset line, sync, high-active
- ice_i => ce_i, -- interface clock enable, high-active
-
- -- processor interface --
- cp_en_i => sys_cp_en, -- access coprocessor
- cp_op_i => cp_op, -- data transfer/processing
- cp_rw_i => cp_rw, -- read/write access
- cp_cmd_i => cp_cmd, -- register addresses / cmd
- cp_dat_i => cp_w_data, -- write data
- cp_dat_o => sys_cp_drb, -- read data
- cp_irq_o => sys_cp_irq, -- unit interrupt request
-
- sys_mode_i => sys_mode, -- current operating mode
- int_exe_i => sys_int_exe, -- interrupt beeing executed
-
- -- memory interface --
- mem_ip_adr_o => i_page, -- instruction page
- mem_dp_adr_o => d_page, -- data page
-
- -- io interface --
- uart_rxd_i => uart_rxd_i, -- receiver input
- uart_txd_o => uart_txd_o, -- uart transmitter output
- spi_sck_o => spi_sck_o, -- serial clock output
- spi_mosi_o => spi_mosi_o, -- serial data output
- spi_miso_i => spi_miso_i, -- serial data input
- spi_cs_o => spi_cs_o, -- device select
- pio_out_o => pio_out_o, -- parallel output
- pio_in_i => pio_in_i, -- parallel input
-
- -- system io --
- sys_out_o => sys_out_o, -- system parallel output
- sys_in_i => sys_in_i, -- system parallel input
-
- -- irq lines --
- irq_i => irq_i, -- external irq
-
- -- wishbone bus --
- wb_clk_o => wb_clk_o, -- bus clock
- wb_rst_o => wb_rst_o, -- bus reset, sync, high active
- wb_adr_o => wb_adr_o, -- address
- wb_sel_o => wb_sel_o, -- byte select
- wb_data_o => wb_data_o, -- data out
- wb_data_i => wb_data_i, -- data in
- wb_we_o => wb_we_o, -- read/write
- wb_cyc_o => wb_cyc_o, -- cycle enable
- wb_stb_o => wb_stb_o, -- strobe
- wb_ack_i => wb_ack_i, -- acknowledge
- wb_err_i => wb_err_i -- bus error
- );
-
-
- -- Memory Gate -----------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- memory_gate: mem_gate
- port map (
- -- host interface --
- clk_i => clk_i, -- global clock line
- rst_i => rst_i, -- global reset line, sync, high-active
-
- i_adr_i => cpu_i_adr, -- instruction adr
- i_dat_o => cpu_i_data, -- instruction out
- d_req_i => cpu_d_req, -- request access in next cycle
- d_rw_i => cpu_d_rw, -- read/write
- d_adr_i => cpu_d_adr, -- data adr
- d_dat_i => cpu_d_w_data, -- data in
- d_dat_o => cpu_d_r_data, -- data out
- mem_ip_adr_i => i_page, -- instruction page
- mem_dp_adr_i => d_page, -- data page
-
- -- boot rom interface --
- boot_i_adr_o => boot_i_adr, -- instruction adr
- boot_i_dat_i => boot_i_dat, -- instruction out
- boot_d_en_o => boot_d_en, -- access enable
- boot_d_rw_o => boot_d_rw, -- read/write
- boot_d_adr_o => boot_d_adr, -- data adr
- boot_d_dat_o => boot_d_dat_o, -- data in
- boot_d_dat_i => boot_d_dat_i, -- data out
-
- -- memory interface --
- mem_i_page_o => mem_i_page_o, -- instruction page
- mem_i_adr_o => mem_i_adr_o, -- instruction adr
- mem_i_dat_i => mem_i_dat_i, -- instruction out
- mem_d_en_o => mem_d_en_o, -- access enable
- mem_d_rw_o => mem_d_rw_o, -- read/write
- mem_d_page_o => mem_d_page_o, -- instruction page
- mem_d_adr_o => mem_d_adr_o, -- data adr
- mem_d_dat_o => mem_d_dat_o, -- data in
- mem_d_dat_i => mem_d_dat_i -- data out
- );
-
-
- -- Bootloader Memory -----------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- bootloader_mem: boot_mem
- port map (
- -- host interface --
- clk_i => clk_i, -- global clock line
- i_adr_i => boot_i_adr, -- instruction adr
- i_dat_o => boot_i_dat, -- instruction out
- d_en_i => boot_d_en, -- access enable
- d_rw_i => boot_d_rw, -- read/write
- d_adr_i => boot_d_adr, -- data adr
- d_dat_i => boot_d_dat_o, -- data in
- d_dat_o => boot_d_dat_i -- data out
- );
-
-
-
-end atlas_2k_top_behav;
Index: rtl/MEM_ACC.vhd
===================================================================
--- rtl/MEM_ACC.vhd (revision 37)
+++ rtl/MEM_ACC.vhd (nonexistent)
@@ -1,202 +0,0 @@
--- ########################################################
--- # << ATLAS Project - Memory Access System >> #
--- # **************************************************** #
--- # This unit generates all neccessary signals for the #
--- # data memory interface. Furthermore, internal data #
--- # switching networks are located here. #
--- # **************************************************** #
--- # Last modified: 28.11.2014 #
--- # **************************************************** #
--- # by Stephan Nolting 4788, Hanover, Germany #
--- ########################################################
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.atlas_core_package.all;
-
-entity MEM_ACC is
- port (
--- ###############################################################################################
--- ## Global Control ##
--- ###############################################################################################
-
- clk_i : in std_ulogic; -- global clock line
- ce_i : in std_ulogic; -- clock enable
- rst_i : in std_ulogic; -- global reset line, sync, high-active
-
--- ###############################################################################################
--- ## Function Control ##
--- ###############################################################################################
-
- ma_ctrl_bus_i : in std_ulogic_vector(ctrl_width_c-1 downto 0); -- ma stage control
-
--- ###############################################################################################
--- ## Data Input ##
--- ###############################################################################################
-
- alu_res_i : in std_ulogic_vector(data_width_c-1 downto 0); -- alu result
- mul_res_i : in std_ulogic_vector(2*data_width_c-1 downto 0); -- mul result
- adr_base_i : in std_ulogic_vector(data_width_c-1 downto 0); -- op_a bypass
- data_bp_i : in std_ulogic_vector(data_width_c-1 downto 0); -- op_b bypass
- cp_data_i : in std_ulogic_vector(data_width_c-1 downto 0); -- coprocessor rd data
- rd_msr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- read data msr
-
- wb_fwd_i : in std_ulogic_vector(fwd_width_c-1 downto 0); -- wb stage forwarding path
-
--- ###############################################################################################
--- ## Data Output ##
--- ###############################################################################################
-
- data_o : out std_ulogic_vector(data_width_c-1 downto 0); -- data output
- mem_adr_fb_o : out std_ulogic_vector(data_width_c-1 downto 0); -- memory address feedback
-
- ma_fwd_o : out std_ulogic_vector(fwd_width_c-1 downto 0); -- ma stage forwarding path
-
--- ###############################################################################################
--- ## Memory (w) Interface ##
--- ###############################################################################################
-
- mem_adr_o : out std_ulogic_vector(data_width_c-1 downto 0); -- address output
- mem_dat_o : out std_ulogic_vector(data_width_c-1 downto 0); -- write data output
- mem_rw_o : out std_ulogic -- read write
- );
-end mem_acc;
-
-architecture ma_structure of mem_acc is
-
- -- pipeline register --
- signal alu_res_ff : std_ulogic_vector(data_width_c-1 downto 0);
- signal adr_base_ff : std_ulogic_vector(data_width_c-1 downto 0);
- signal data_bp_ff : std_ulogic_vector(data_width_c-1 downto 0);
-
- -- alu data buffer --
- signal alu_res_buf : std_ulogic_vector(data_width_c-1 downto 0);
-
- -- internal signals --
- signal data_bp_int : std_ulogic_vector(data_width_c-1 downto 0);
- signal alu_mac_dat : std_ulogic_vector(data_width_c-1 downto 0);
- signal sys_cp_r_dat : std_ulogic_vector(data_width_c-1 downto 0);
- signal sys_cp_alu_r_dat : std_ulogic_vector(data_width_c-1 downto 0);
- signal mul_res_int : std_ulogic_vector(data_width_c-1 downto 0);
-
-begin
-
- -- Pipeline Register -----------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- pipe_reg: process(clk_i)
- begin
- if rising_edge(clk_i) then
- if (rst_i = '1') then
- alu_res_ff <= (others => '0');
- adr_base_ff <= (others => '0');
- data_bp_ff <= (others => '0');
- alu_res_buf <= (others => '0');
- elsif (ce_i = '1') then
- alu_res_ff <= alu_res_i;
- adr_base_ff <= adr_base_i;
- data_bp_ff <= data_bp_i;
- alu_res_buf <= alu_res_ff;
- end if;
- end if;
- end process pipe_reg;
-
-
- -- Memory Access Forwarding Unit -----------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- ma_fwd: process(wb_fwd_i, ma_ctrl_bus_i, data_bp_ff)
- begin
- -- memory write data (op_b) forwarding --
- if (wb_fwd_i(fwd_en_c) = '1') and (ma_ctrl_bus_i(ctrl_mcyc_c) = '0') and (ma_ctrl_bus_i(ctrl_rb_3_c downto ctrl_rb_0_c) = wb_fwd_i(fwd_adr_3_c downto fwd_adr_0_c)) then
- data_bp_int <= wb_fwd_i(fwd_dat_msb_c downto fwd_dat_lsb_c); -- wb stage
- else
- data_bp_int <= data_bp_ff;
- end if;
- end process ma_fwd;
-
-
- -- Memory Address Generator and Data Alignment ---------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- w_mem_acc: process(ma_ctrl_bus_i, alu_res_buf, adr_base_ff, alu_res_ff, data_bp_int)
- variable mem_adr_v : std_ulogic_vector(data_width_c-1 downto 0);
- variable dat_end_v : std_ulogic_vector(data_width_c-1 downto 0);
- begin
- -- address origin --
- if (ma_ctrl_bus_i(ctrl_mem_daa_c) = '1') then
- mem_adr_v := alu_res_buf; -- use delayed address
- elsif (ma_ctrl_bus_i(ctrl_mem_bpba_c) = '1') then
- mem_adr_v := adr_base_ff; -- use bypassed address
- else
- mem_adr_v := alu_res_ff;
- end if;
- mem_adr_fb_o <= mem_adr_v; -- data alignment address
- mem_adr_o <= mem_adr_v; -- memory address output
-
- -- endianness converter --
- if (big_endian_c = false) then
- dat_end_v := data_bp_int(data_width_c/2-1 downto 0) & data_bp_int(data_width_c-1 downto data_width_c/2);
- else
- dat_end_v := data_bp_int;
- end if;
-
- -- data alignment --
- if (word_mode_en_c = false) then -- byte-addressed memory
- if (mem_adr_v(0) = '1') then -- unaligned? -> swap bytes
- mem_dat_o <= dat_end_v(data_width_c/2-1 downto 0) & dat_end_v(data_width_c-1 downto data_width_c/2);
- else -- aligned
- mem_dat_o <= dat_end_v;
- end if;
- else -- word-addressed memory
- mem_dat_o <= dat_end_v;
- end if;
- end process w_mem_acc;
-
- -- r/w control --
- mem_rw_o <= ma_ctrl_bus_i(ctrl_mem_wr_c) and ma_ctrl_bus_i(ctrl_en_c);
-
-
- -- Stage Data Multiplexer ------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- no_mul_unit: -- syntheszie no mul unit at all
- if (build_mul_c = false) generate
- mul_res_int <= (others => '0');
- alu_mac_dat <= alu_res_ff;
- end generate no_mul_unit;
-
- synhesize_mul16_unit: -- synthesize 16-bit mul unit
- if (build_mul_c = true) and (build_mul32_c = false) generate
- mul_res_int <= (others => '0');
- alu_mac_dat <= mul_res_i(15 downto 0) when (ma_ctrl_bus_i(ctrl_use_mul_c) = '1') else alu_res_ff;
- end generate synhesize_mul16_unit;
-
- synhesize_mul32_unit: -- synthesize 32-bit mul unit
- if (build_mul_c = true) and (build_mul32_c = true) generate
- mul_res_int <= mul_res_i(31 downto 16) when (ma_ctrl_bus_i(ctrl_ext_mul_c) = '1') else mul_res_i(15 downto 0);
- alu_mac_dat <= mul_res_int when (ma_ctrl_bus_i(ctrl_use_mul_c) = '1') else alu_res_ff;
- end generate synhesize_mul32_unit;
-
- -- coprocessor input --
- sys_cp_r_dat <= cp_data_i when (ma_ctrl_bus_i(ctrl_rd_cp_acc_c) = '1') else rd_msr_i;
-
- -- multiplexers --
- sys_cp_alu_r_dat <= sys_cp_r_dat when (ma_ctrl_bus_i(ctrl_cp_msr_rd_c) = '1') else alu_mac_dat;
- data_o <= data_bp_ff when (ma_ctrl_bus_i(ctrl_link_c) = '1') else sys_cp_alu_r_dat;
-
-
- -- Forwarding Path Output ------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
-
- -- forwarding data --
- ma_fwd_o(fwd_dat_msb_c downto fwd_dat_lsb_c) <= sys_cp_alu_r_dat;
-
- -- destination address --
- ma_fwd_o(fwd_adr_3_c downto fwd_adr_0_c) <= ma_ctrl_bus_i(ctrl_rd_3_c downto ctrl_rd_0_c);
-
- -- valid forwarding --
- ma_fwd_o(fwd_en_c) <= ma_ctrl_bus_i(ctrl_wb_en_c);
-
-
-
-end MA_STRUCTURE;
Index: rtl/INT_RAM.vhd
===================================================================
--- rtl/INT_RAM.vhd (revision 37)
+++ rtl/INT_RAM.vhd (nonexistent)
@@ -1,97 +0,0 @@
--- ########################################################
--- # << ATLAS Project - Demo RAM >> #
--- # **************************************************** #
--- # Core-compatible example RAM component. #
--- # **************************************************** #
--- # Last modified: 28.11.2014 #
--- # **************************************************** #
--- # by Stephan Nolting 4788, Hanover, Germany #
--- ########################################################
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.atlas_core_package.all;
-
-entity int_ram is
- generic (
- mem_size_g : natural := 256 -- memory size in bytes
- );
- port (
- -- host interface --
- clk_i : in std_ulogic; -- global clock line
- i_adr_i : in std_ulogic_vector(31 downto 0); -- instruction adr
- i_dat_o : out std_ulogic_vector(15 downto 0); -- instruction out
- d_en_i : in std_ulogic; -- access enable
- d_rw_i : in std_ulogic; -- read/write
- d_adr_i : in std_ulogic_vector(31 downto 0); -- data adr
- d_dat_i : in std_ulogic_vector(15 downto 0); -- data in
- d_dat_o : out std_ulogic_vector(15 downto 0) -- data out
- );
-end int_ram;
-
-architecture int_ram_structure of int_ram is
-
- -- internal constants --
- constant log2_mem_size_c : natural := log2(mem_size_g/2); -- address width
-
- -- memory type --
- type int_mem_file_t is array (0 to (mem_size_g/2)-1) of std_ulogic_vector(data_width_c-1 downto 0);
-
--- ======================================================================
- signal mem_file : int_mem_file_t; -- use this for implementation
--- signal mem_file : int_mem_file_t := -- use this for simulation
--- (
--- others => x"0000" -- nop
--- );
--- ======================================================================
-
- -- ram attribute to inhibit bypass-logic - altera only! --
- attribute ramstyle : string;
- attribute ramstyle of mem_file : signal is "no_rw_check";
-
-begin
-
- -- Data Memory Access ----------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- mem_file_d_access: process(clk_i)
- begin
- if rising_edge(clk_i) then
- -- data read/write --
- if (d_en_i = '1') then -- valid access
- if (d_rw_i = '1') then -- write data access
- if (word_mode_en_c = true) then
- mem_file(to_integer(unsigned(d_adr_i(log2_mem_size_c-1 downto 0)))) <= d_dat_i;
- else
- mem_file(to_integer(unsigned(d_adr_i(log2_mem_size_c downto 1)))) <= d_dat_i;
- end if;
- end if;
- end if;
- if (word_mode_en_c = true) then
- d_dat_o <= mem_file(to_integer(unsigned(d_adr_i(log2_mem_size_c-1 downto 0))));
- else
- d_dat_o <= mem_file(to_integer(unsigned(d_adr_i(log2_mem_size_c downto 1))));
- end if;
- end if;
- end process mem_file_d_access;
-
-
- -- Instruction Memory Access ---------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- mem_file_i_access: process(clk_i)
- begin
- if rising_edge(clk_i) then
- -- instruction read --
- if (word_mode_en_c = true) then
- i_dat_o <= mem_file(to_integer(unsigned(i_adr_i(log2_mem_size_c-1 downto 0))));
- else
- i_dat_o <= mem_file(to_integer(unsigned(i_adr_i(log2_mem_size_c downto 1))));
- end if;
- end if;
- end process mem_file_i_access;
-
-
-
-end int_ram_structure;
Index: rtl/OP_DEC.vhd
===================================================================
--- rtl/OP_DEC.vhd (revision 37)
+++ rtl/OP_DEC.vhd (nonexistent)
@@ -1,526 +0,0 @@
--- ########################################################
--- # << ATLAS Project - OpCode Decoder >> #
--- # **************************************************** #
--- # OpCode (instruction) decoding unit. #
--- # **************************************************** #
--- # Last modified: 28.11.2014 #
--- # **************************************************** #
--- # by Stephan Nolting 4788, Hanover, Germany #
--- ########################################################
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-library work;
-use work.atlas_core_package.all;
-
-entity op_dec is
- port (
--- ###############################################################################################
--- ## Decoder Interface Input ##
--- ###############################################################################################
-
- instr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- instruction input
- instr_adr_i : in std_ulogic_vector(data_width_c-1 downto 0); -- corresponding address
- t_flag_i : in std_ulogic; -- t-flag input
- m_flag_i : in std_ulogic; -- mode flag input
- multi_cyc_i : in std_ulogic; -- multi-cycle indicator
- cp_ptc_i : in std_ulogic; -- user coprocessor protection
-
--- ###############################################################################################
--- ## Decoder Interface Output ##
--- ###############################################################################################
-
- multi_cyc_req_o : out std_ulogic; -- multi-cycle reqest
- ctrl_o : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- decoder ctrl lines
- imm_o : out std_ulogic_vector(data_width_c-1 downto 0) -- immediate
- );
-end op_dec;
-
-architecture op_dec_structure of op_dec is
-
- -- formated instruction --
- signal instr_int : std_ulogic_vector(15 downto 0);
-
-begin
-
- -- Data Format Converter -------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- data_conv: process(instr_i, instr_adr_i)
- variable instr_sel_v : std_ulogic_vector(31 downto 0);
- variable instr_tmp_v : std_ulogic_vector(15 downto 0);
- begin
- instr_sel_v := (others => '0');
- for i in 0 to data_width_c-1 loop
- instr_sel_v(i) := instr_i(i);
- end loop;
- if (data_width_c = 16) then -- 16-bit mode
- instr_tmp_v := instr_sel_v(15 downto 0);
- else -- 32-bit mode
- if (instr_adr_i(1) = '0') then
- instr_tmp_v := instr_sel_v(15 downto 0);
- else
- instr_tmp_v := instr_sel_v(31 downto 16);
- end if;
- end if;
- if (big_endian_c = false) then -- endian converter
- instr_int <= instr_tmp_v(7 downto 0) & instr_tmp_v(15 downto 8);
- else
- instr_int <= instr_tmp_v;
- end if;
- end process data_conv;
-
-
- -- Opcode Decoder --------------------------------------------------------------------------------------
- -- --------------------------------------------------------------------------------------------------------
- opcode_decoder: process(instr_int, multi_cyc_i, t_flag_i, m_flag_i, cp_ptc_i)
- variable mem_acc_temp_v : std_ulogic_vector(3 downto 0);
- variable redundant_reg_v : std_ulogic;
- begin
-
- -- defaults --
- imm_o <= (others => '0'); -- zero immediate
- multi_cyc_req_o <= '0'; -- no multi-cycle operation
- ctrl_o <= (others => '0'); -- all signals disabled
- ctrl_o(ctrl_en_c) <= '1'; -- but we're enabled ^^
- ctrl_o(ctrl_cp_id_c) <= instr_int(10); -- coprocessor id
- ctrl_o(ctrl_ra_3_c downto ctrl_ra_0_c) <= m_flag_i & instr_int(6 downto 4); -- operand a register
- ctrl_o(ctrl_rb_3_c downto ctrl_rb_0_c) <= m_flag_i & instr_int(2 downto 0); -- operand b register
- ctrl_o(ctrl_rd_3_c downto ctrl_rd_0_c) <= m_flag_i & instr_int(9 downto 7); -- destination register
- ctrl_o(ctrl_cond_3_c downto ctrl_cond_0_c) <= instr_int(13 downto 10); -- branch condition
-
- -- both operands have same addresses? --
- redundant_reg_v := '0';
- if (instr_int(6 downto 4) = instr_int(2 downto 0)) then
- redundant_reg_v := '1';
- end if;
-
- -- decoder --
- case (instr_int(15 downto 14)) is
-
- when "00" => -- class 0: alu data processing // bank / pc / msr transfer
- -- ==============================================================================
- ctrl_o(ctrl_rd_wb_c) <= '1'; -- allow write back
- ctrl_o(ctrl_fupdate_c) <= instr_int(3); -- flag update
- imm_o(2 downto 0) <= instr_int(2 downto 0); -- 3-bit immediate
- if (instr_int(13 downto 10) = fs_inc_c) or (instr_int(13 downto 10) = fs_dec_c) or (instr_int(13 downto 10) = fs_sft_c) then
- ctrl_o(ctrl_rb_is_imm_c) <= '1'; -- yes, this is an immediate
- end if;
- -- mapping to alu elementary operation --
- case (instr_int(13 downto 10)) is
-
- when fs_orr_c => -- logical or // load from user bank register if redundant
- ctrl_o(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_orr_c; -- logical or
- if (redundant_reg_v = '1') then -- user bank load
- ctrl_o(ctrl_ra_3_c) <= user_mode_c; -- load from user bank
- ctrl_o(ctrl_rb_3_c) <= user_mode_c; -- load from user bank
- if (m_flag_i = user_mode_c) then -- unauthorized access
- ctrl_o(ctrl_cmd_err_c) <= '1'; -- access violation - cmd_err trap
- end if;
- end if;
-
- when fs_and_c => -- logical and // store to user bank register if redundant
- ctrl_o(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_and_c; -- logical and
- if (redundant_reg_v = '1') then -- user bank store
- ctrl_o(ctrl_rd_3_c) <= user_mode_c; -- store to user bank
- if (m_flag_i = user_mode_c) then -- unauthorized access
- ctrl_o(ctrl_cmd_err_c) <= '1'; -- access violation - cmd_err trap
- end if;
- end if;
-
- when fs_cmp_c => -- compare by sbtraction // load from msr if s = 0
- ctrl_o(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_sbc_c; -- compare by subtraction
- ctrl_o(ctrl_rd_wb_c) <= '0'; -- disable write back
- ctrl_o(ctrl_msr_am_1_c) <= instr_int(6);
- ctrl_o(ctrl_msr_am_0_c) <= instr_int(5);
- if (instr_int(3) = '0') then -- load from msr
- if (instr_int(6 downto 5) /= "11") and (m_flag_i = user_mode_c) then
- ctrl_o(ctrl_cmd_err_c) <= '1'; -- access violation - cmd_err trap
- end if;
- ctrl_o(ctrl_msr_rd_c) <= '1'; -- read msr
- ctrl_o(ctrl_rd_wb_c) <= '1'; -- re-enable write back
- end if;
-
- when fs_cpx_c => -- extended compare with flags // store to msr if s = 0
- ctrl_o(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_sbc_c; -- compare by subtraction with flags
- ctrl_o(ctrl_alu_usec_c) <= '1'; -- use carry input
- ctrl_o(ctrl_alu_usez_c) <= '1'; -- use zero input
- ctrl_o(ctrl_rd_wb_c) <= '0'; -- disable write back
- ctrl_o(ctrl_msr_am_1_c) <= instr_int(6); -- only for msr immediate write access
- ctrl_o(ctrl_msr_am_0_c) <= instr_int(5); -- only for msr immediate write access
- ctrl_o(ctrl_alu_cf_opt_c) <= instr_int(9); -- invert carry flag option?
- ctrl_o(ctrl_alu_zf_opt_c) <= instr_int(8); -- use old zero flag option?
- imm_o(msr_sys_z_flag_c) <= instr_int(0); -- only for msr immediate write access
- imm_o(msr_usr_z_flag_c) <= instr_int(0); -- only for msr immediate write access
- imm_o(msr_sys_c_flag_c) <= instr_int(1); -- only for msr immediate write access
- imm_o(msr_usr_c_flag_c) <= instr_int(1); -- only for msr immediate write access
- imm_o(msr_sys_o_flag_c) <= instr_int(2); -- only for msr immediate write access
- imm_o(msr_usr_o_flag_c) <= instr_int(2); -- only for msr immediate write access
- imm_o(msr_sys_n_flag_c) <= instr_int(7); -- only for msr immediate write access
- imm_o(msr_usr_n_flag_c) <= instr_int(7); -- only for msr immediate write access
- imm_o(msr_sys_t_flag_c) <= instr_int(8); -- only for msr immediate write access
- imm_o(msr_usr_t_flag_c) <= instr_int(8); -- only for msr immediate write access
- if (instr_int(3) = '0') then -- store to msr
- if ((m_flag_i = user_mode_c) and (instr_int(6 downto 5) /= "11")) then
- ctrl_o(ctrl_cmd_err_c) <= '1'; -- access violation -> cmd_err trap
- end if;
- if(multi_cyc_i = '0') then
- ctrl_o(ctrl_msr_wr_c) <= '1'; -- write msr
- multi_cyc_req_o <= '1'; -- we need a dummy cycle afterwards
- ctrl_o(ctrl_rb_is_imm_c) <= instr_int(4); -- store immediate
- else
- ctrl_o(ctrl_en_c) <= '0'; -- insert empty cycle
- end if;
- end if;
-
- when fs_tst_c => -- compare by logical xor // load from pc if s = 0
- ctrl_o(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_eor_c; -- compare by logical xor
- ctrl_o(ctrl_rd_wb_c) <= '0'; -- disable write back
- if (instr_int(3) = '0') then -- load from pc
- ctrl_o(ctrl_ra_is_pc_c) <= '1'; -- read pc
- ctrl_o(ctrl_rb_is_imm_c) <= instr_int(3); -- this is an immediate
- ctrl_o(ctrl_rd_wb_c) <= '1'; -- re-enable write back
- end if;
-
- when fs_teq_c => -- compare by logical and // store to pc if s = 0
- ctrl_o(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_and_c; -- compare by logical and
- ctrl_o(ctrl_rd_3_c downto ctrl_rd_0_c) <= m_flag_i & link_reg_adr_c; -- link register
- ctrl_o(ctrl_rd_wb_c) <= '0'; -- disable write back
- if (instr_int(3) = '0') then -- store to pc
- if ((m_flag_i = user_mode_c) and ((instr_int(1 downto 0) /= "00") or (instr_int(7) = '1'))) then
- ctrl_o(ctrl_cmd_err_c) <= '1'; -- access violation - cmd_err trap
- end if;
- ctrl_o(ctrl_pc_wr_c) <= '1'; -- write pc
- ctrl_o(ctrl_rb_is_imm_c) <= '1'; -- this is an immediate
- imm_o <= (others => '0'); -- zero
- ctrl_o(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_orr_c; -- logical or with 0
- ctrl_o(ctrl_ctx_down_c) <= instr_int(0); -- goto user mode when bit 0 = '1'
- ctrl_o(ctrl_re_xint_c) <= instr_int(1); -- re-enable global xint flag
- ctrl_o(ctrl_link_c) <= instr_int(2); -- link
- ctrl_o(ctrl_rd_wb_c) <= instr_int(2); -- allow write back for linking
- ctrl_o(ctrl_restsm_c) <= instr_int(7); -- restore saved mode
- end if;
-
- when fs_inc_c | fs_add_c => -- immediate addition // addition
- ctrl_o(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_adc_c;
-
- when fs_dec_c => -- immediate subtraction
- ctrl_o(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_sbc_c;
-
- when fs_sub_c => -- subtraction
- ctrl_o(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_sbc_c;
- if (redundant_reg_v = '1') then -- sub instruction with ra = rb: rd = 0 - ra (neg rd, ra)
- ctrl_o(ctrl_clr_la_c) <= '1'; -- set low byte of a to 0
- ctrl_o(ctrl_clr_ha_c) <= '1'; -- set high byte of a to 0
- end if;
-
- when fs_adc_c => -- addition with carry
- ctrl_o(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_adc_c;
- ctrl_o(ctrl_alu_usec_c) <= '1'; -- use carry input
-
- when fs_sbc_c => -- subtraction with carry
- ctrl_o(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_sbc_c;
- ctrl_o(ctrl_alu_usec_c) <= '1'; -- use carry input
- if (redundant_reg_v = '1') then -- sbc instruction with ra = rb: rd = 0 - ra - c (nec rd, ra)
- ctrl_o(ctrl_clr_la_c) <= '1'; -- set low byte of a to 0
- ctrl_o(ctrl_clr_ha_c) <= '1'; -- set high byte of a to 0
- end if;
-
- when fs_eor_c => -- logical xor
- ctrl_o(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_eor_c;
-
- when fs_nand_c => -- logical not-and
- ctrl_o(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_nand_c;
-
- when fs_bic_c => -- bit clear
- ctrl_o(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_bic_c;
-
- when fs_sft_c => -- shift operation
- ctrl_o(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_sft_c;
-
- when others => -- undefined
- null; -- use defaults
-
- end case;
-
-
- when "01" => -- class 1: memory access
- -- ==============================================================================
- imm_o(2 downto 0) <= instr_int(2 downto 0); -- immediate offset
- if (instr_int(12) = '1') then
- ctrl_o(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_adc_c; -- add index
- else
- ctrl_o(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_sbc_c; -- sub index
- end if;
- mem_acc_temp_v := instr_int(10) & instr_int(3) & instr_int(13) & instr_int(11); -- l,i,p,w
- case (mem_acc_temp_v) is
-
- when "0000" | "0100" => -- load, imm/reg offset, pre, no wb
- ctrl_o(ctrl_mem_acc_c) <= '1'; -- this is a memory access
- ctrl_o(ctrl_rb_is_imm_c) <= instr_int(3); -- this is an immediate
- ctrl_o(ctrl_rd_wb_c) <= '1'; -- allow data write back
-
- when "0001" | "0101" => -- load, imm/reg offset, pre, do wb
- ctrl_o(ctrl_rb_is_imm_c) <= instr_int(3); -- this is an immediate
- ctrl_o(ctrl_rd_wb_c) <= '1'; -- allow data write back
- if (multi_cyc_i = '0') then -- fist cycle: add/sub r_base, r_base, offset
- ctrl_o(ctrl_rd_3_c downto ctrl_rd_0_c) <= m_flag_i & instr_int(6 downto 4); -- base adr
- multi_cyc_req_o <= '1'; -- prepare second cycle
- else -- second cycle: ld r_data, [r_base]
- ctrl_o(ctrl_mem_acc_c) <= '1'; -- this is a memory access
- ctrl_o(ctrl_mem_bpba_c) <= '1'; -- use bypassed adr from prev cycle
- end if;
-
- when "0011" | "0111" => -- load, imm/reg offset, post, do wb
- ctrl_o(ctrl_rb_is_imm_c) <= instr_int(3); -- this is an immediate
- ctrl_o(ctrl_rd_wb_c) <= '1'; -- allow data write back
- if (multi_cyc_i = '0') then -- fist cycle: ld r_data, [r_base]
- ctrl_o(ctrl_mem_acc_c) <= '1'; -- this is a memory access
- ctrl_o(ctrl_mem_bpba_c) <= '1'; -- use bypassed adr from prev cycle
- multi_cyc_req_o <= '1'; -- prepare second cycle
- else -- second cycle: add/sub r_base, r_base, offset
- ctrl_o(ctrl_rd_3_c downto ctrl_rd_0_c) <= m_flag_i & instr_int(6 downto 4); -- base adr
- end if;
-
- when "1000" | "1001" => -- store, reg offset, pre, (no) wb
- if (multi_cyc_i = '0') then -- fist cycle: add/sub r_base, r_base, r_offset
- ctrl_o(ctrl_rd_3_c downto ctrl_rd_0_c) <= m_flag_i & instr_int(6 downto 4); -- base adr
- ctrl_o(ctrl_rd_wb_c) <= instr_int(11); -- write back base?
- multi_cyc_req_o <= '1'; -- prepare second cycle
- else -- second cycle: st r_data, [r_base]
- ctrl_o(ctrl_rb_3_c downto ctrl_rb_0_c) <= m_flag_i & instr_int(9 downto 7); -- store data
- ctrl_o(ctrl_mem_daa_c) <= '1'; -- use delayed adr from prev cycle
- ctrl_o(ctrl_mem_acc_c) <= '1'; -- this is a memory access
- ctrl_o(ctrl_mem_wr_c) <= '1'; -- write access
- end if;
-
- when "1011" => -- store, reg offset, post, do wb
- if (multi_cyc_i = '0') then -- fist cycle: st r_data, [r_base]
- ctrl_o(ctrl_rb_3_c downto ctrl_rb_0_c) <= m_flag_i & instr_int(9 downto 7); -- store data
- ctrl_o(ctrl_mem_bpba_c) <= '1'; -- use bypassed adr from prev cycle
- ctrl_o(ctrl_mem_acc_c) <= '1'; -- this is a memory access
- ctrl_o(ctrl_mem_wr_c) <= '1'; -- write access
- multi_cyc_req_o <= '1'; -- prepare second cycle
- else -- second cycle: add/sub r_base, r_base, r_offset
- ctrl_o(ctrl_rd_3_c downto ctrl_rd_0_c) <= m_flag_i & instr_int(6 downto 4); -- base adr
- ctrl_o(ctrl_rd_wb_c) <= '1'; -- write back base
- end if;
-
- when "1100" | "1101" | "1111" => -- store, imm offset, pre/post, (no) wb
- ctrl_o(ctrl_rd_3_c downto ctrl_rd_0_c) <= m_flag_i & instr_int(6 downto 4); -- base adr
- ctrl_o(ctrl_rb_3_c downto ctrl_rb_0_c) <= m_flag_i & instr_int(9 downto 7); -- store data
- ctrl_o(ctrl_rb_is_imm_c) <= '1'; -- this is an immediate
- ctrl_o(ctrl_mem_acc_c) <= '1'; -- this is a memory access
- ctrl_o(ctrl_mem_wr_c) <= '1'; -- write access
- ctrl_o(ctrl_mem_bpba_c) <= instr_int(13); -- use bypassed adr base
- ctrl_o(ctrl_rd_wb_c) <= instr_int(11); -- write back base
-
- -- data swap operations r_b => m[r_a] => r_d --------------------------------
- when "0010" | "0110" | "1010" | "1110" => -- load/store, imm/reg offset, post, no wb [redundant!]
- ctrl_o(ctrl_mem_acc_c) <= '1'; -- this is a memory access
- ctrl_o(ctrl_mem_bpba_c) <= '1'; -- use bypassed adr from prev cycle
- ctrl_o(ctrl_rb_is_imm_c) <= '1'; -- this is an immediate (pseudo)
- if (multi_cyc_i = '0') then -- first cycle: ld r_d, [r_a]
- ctrl_o(ctrl_rd_wb_c) <= '1'; -- write back base
- multi_cyc_req_o <= '1'; -- prepare second cycle
- else -- second cycle: st r_b, [r_a]
- ctrl_o(ctrl_mem_wr_c) <= '1'; -- write access
- end if;
-
- when others => -- undefined
- null; -- wayne ^^
-
- end case;
-
-
- when "10" => -- class 2: branch and link
- -- ==============================================================================
- ctrl_o(ctrl_branch_c) <= '1'; -- this is a branch
- ctrl_o(ctrl_link_c) <= instr_int(9); -- link?
- ctrl_o(ctrl_ra_is_pc_c) <= '1'; -- operand a is the pc
- ctrl_o(ctrl_rb_is_imm_c) <= '1'; -- operand b is an immediate
- ctrl_o(ctrl_rd_wb_c) <= instr_int(9); -- allow write back for linking
- ctrl_o(ctrl_rd_3_c downto ctrl_rd_0_c) <= m_flag_i & link_reg_adr_c; -- link register
- ctrl_o(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_adc_c; -- add offset (without carry)
- if (word_mode_en_c = false) then -- byte addressing mode
- imm_o(9 downto 0) <= instr_int(8 downto 0) & '0'; -- offset = offset * 2 (byte offset)
- for i in 10 to data_width_c-1 loop
- imm_o(i) <= instr_int(8); -- sign extension
- end loop;
- else -- word addressing mode
- imm_o(8 downto 0) <= instr_int(8 downto 0); -- offset = offset (word offset)
- for i in 9 to data_width_c-1 loop
- imm_o(i) <= instr_int(8); -- sign extension
- end loop;
- end if;
-
-
- when "11" => -- class 3: sub classes
- -- ==============================================================================
- case (instr_int(13 downto 12)) is
-
- when "00" => -- class 3a: load immediate
- -- --------------------------------------------------------------------------------
- ctrl_o(ctrl_rd_wb_c) <= '1'; -- allow write back
- ctrl_o(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_orr_c; -- logical or
- ctrl_o(ctrl_ra_3_c downto ctrl_ra_0_c) <= m_flag_i & instr_int(9 downto 7); -- op a = source & destination
- ctrl_o(ctrl_rb_is_imm_c) <= '1'; -- b is an immediate
- if (instr_int(11) = '0') then -- load and expand low part
- ctrl_o(ctrl_clr_la_c) <= '1'; -- set low byte of a to 0
- imm_o(7 downto 0) <= instr_int(10) & instr_int(6 downto 0);
- if (ldil_sign_ext_c = true) then -- use sign extension
- for i in 8 to data_width_c-1 loop -- sign extension
- imm_o(i) <= instr_int(10);
- end loop;
- ctrl_o(ctrl_clr_ha_c) <= '1'; -- set high byte of a to 0
- end if;
- else -- load high part
- imm_o(15 downto 8) <= instr_int(10) & instr_int(6 downto 0);
- ctrl_o(ctrl_clr_ha_c) <= '1'; -- set high byte of a to 0
- end if;
-
-
- when "01" => -- class 3b: bit transfer
- -- --------------------------------------------------------------------------------
- ctrl_o(ctrl_rb_is_imm_c) <= '1'; -- b is an immediate
- case (instr_int(11 downto 10)) is
- when "00" => -- modifiy bit -> clear bit
- imm_o(to_integer(unsigned(instr_int(3 downto 0)))) <= '1';
- ctrl_o(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_bic_c; -- bit clear
- ctrl_o(ctrl_rd_wb_c) <= '1'; -- allow write back
- when "01" => -- modify bit -> set bit
- imm_o(to_integer(unsigned(instr_int(3 downto 0)))) <= '1';
- ctrl_o(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_orr_c; -- logical or
- ctrl_o(ctrl_rd_wb_c) <= '1'; -- allow write back
- when "10" => -- t-flag transfer, load from t
- imm_o(to_integer(unsigned(instr_int(3 downto 0)))) <= '1';
- ctrl_o(ctrl_rd_wb_c) <= '1'; -- allow write back
- if (t_flag_i = '0') then
- ctrl_o(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_bic_c; -- bit clear
- else
- ctrl_o(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_orr_c; -- logical or
- end if;
- when others => -- "11" -- t-flag transfer, store to t
- imm_o(3 downto 0) <= instr_int(3 downto 0);
- ctrl_o(ctrl_rb_is_imm_c) <= not instr_int(9); -- b is an immediate or reg
- ctrl_o(ctrl_tf_store_c) <= '1'; -- store to t-flag
- ctrl_o(ctrl_tf_inv_c) <= instr_int(7); -- invert bit to be transfered to t-flag
- ctrl_o(ctrl_get_par_c) <= instr_int(8); -- get parity bit of op_a
- end case;
-
-
- when "10" => -- class 3c: coprocessor access
- -- --------------------------------------------------------------------------------
- ctrl_o(ctrl_cp_acc_c) <= '1'; -- this is a cp access
- ctrl_o(ctrl_cp_trans_c) <= instr_int(11); -- data transfer/access
- if (instr_int(11) = '1') then -- data transfer
- ctrl_o(ctrl_cp_wr_c) <= instr_int(3); -- read / write
- ctrl_o(ctrl_rd_wb_c) <= not instr_int(3); -- allow write back
- end if;
- if (m_flag_i = user_mode_c) then -- access violation?
- if ((cp_ptc_i = '1') and (instr_int(10) = '0')) or (instr_int(10) = '1') then -- unauthorized acces?
- ctrl_o(ctrl_cmd_err_c) <= '1'; -- access violation/undefined instruction - cmd_err trap
- end if;
- end if;
-
-
- when others => -- class 3d: sub sub classes
- -- ==============================================================================
- case (instr_int(11 downto 10)) is
-
- when "00" => -- class 3c0: multiplication
- -- --------------------------------------------------------------------------------
- if (instr_int(3) = '1') then -- mul32
- if (build_mul_c = true) and (build_mul32_c = true) then -- unit present?
- ctrl_o(ctrl_ext_mul_c) <= '1'; -- use high result
- ctrl_o(ctrl_use_mul_c) <= '1'; -- use mul unit
- ctrl_o(ctrl_rd_wb_c) <= '1'; -- allow write back
- else -- not present
- ctrl_o(ctrl_cmd_err_c) <= '1'; -- invalid instruction - cmd_err trap
- end if;
- else -- mul16
- if (build_mul_c = true) then -- unit present?
- ctrl_o(ctrl_use_mul_c) <= '1'; -- use mul unit
- ctrl_o(ctrl_rd_wb_c) <= '1'; -- allow write back
- else -- not present
- ctrl_o(ctrl_cmd_err_c) <= '1'; -- invalid instruction - cmd_err trap
- end if;
- end if;
-
- if (instr_int(3) = '1') then -- mul32
- if (build_mul_c = true) and (build_mul32_c = true) then -- unit present?
- ctrl_o(ctrl_ext_mul_c) <= '1'; -- use high result
- ctrl_o(ctrl_use_mul_c) <= '1'; -- use mul unit
- ctrl_o(ctrl_rd_wb_c) <= '1'; -- allow write back
- else -- not present
- ctrl_o(ctrl_cmd_err_c) <= '1'; -- invalid instruction - cmd_err trap
- end if;
- else -- mul16
- if (build_mul_c = true) then -- unit present?
- ctrl_o(ctrl_use_mul_c) <= '1'; -- use mul unit
- ctrl_o(ctrl_rd_wb_c) <= '1'; -- allow write back
- else -- not present
- ctrl_o(ctrl_cmd_err_c) <= '1'; -- invalid instruction - cmd_err trap
- end if;
- end if;
-
-
- when "01" => -- class 3c1: special (sleep, reg-based branch)
- -- --------------------------------------------------------------------------------
- if (instr_int(9) = '0') then -- sleep mode
- if (m_flag_i = user_mode_c) then -- access violation?
- ctrl_o(ctrl_cmd_err_c) <= '1'; -- access violation - cmd_err trap
- else
- ctrl_o(ctrl_sleep_c) <= '1'; -- go to sleep
- end if;
- elsif (reg_branches_en_c = true) then -- register-based branches enabled
- ctrl_o(ctrl_cond_3_c downto ctrl_cond_0_c) <= instr_int(6 downto 3); -- branch condition
- ctrl_o(ctrl_rd_3_c downto ctrl_rd_0_c) <= m_flag_i & link_reg_adr_c; -- link register
- ctrl_o(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_adc_c; -- add offset (without carry)
- ctrl_o(ctrl_branch_c) <= '1'; -- this is a branch
- ctrl_o(ctrl_link_c) <= instr_int(7); -- link?
- ctrl_o(ctrl_rd_wb_c) <= instr_int(7); -- allow write back for linking
- ctrl_o(ctrl_ra_is_pc_c) <= '1'; -- operand a is the pc
- ctrl_o(ctrl_clr_la_c) <= instr_int(8); -- set low byte of a to 0
- ctrl_o(ctrl_clr_ha_c) <= instr_int(8); -- set high byte of a to 0
- else
- ctrl_o(ctrl_cmd_err_c) <= '1'; -- undefined instruction - cmd_err trap
- end if;
-
-
- when "10" => -- class 3c2: conditional move = if (cond=true) then rd <= rb
- -- --------------------------------------------------------------------------------
- if (cond_moves_en_c = true) then -- conditional moves enabled
- ctrl_o(ctrl_cond_3_c downto ctrl_cond_0_c) <= instr_int(6 downto 3); -- branch condition
- ctrl_o(ctrl_alu_fs_2_c downto ctrl_alu_fs_0_c) <= alu_orr_c; -- logical or
- ctrl_o(ctrl_rd_wb_c) <= '1'; -- allow write back
- ctrl_o(ctrl_clr_la_c) <= '1'; -- set low byte of a to 0
- ctrl_o(ctrl_clr_ha_c) <= '1'; -- set high byte of a to 0
- ctrl_o(ctrl_cond_wb_c) <= '1'; -- is conditional write back
- else
- ctrl_o(ctrl_cmd_err_c) <= '1'; -- undefined instruction - cmd_err trap
- end if;
-
-
- when others => -- class 3c3: system call with 10-bit tag
- -- --------------------------------------------------------------------------------
- ctrl_o(ctrl_syscall_c) <= '1'; -- is system call
-
- end case;
-
- end case;
-
-
- when others => -- undefined
- -- ==============================================================================
- null; -- wayne...
-
-
- end case;
-
- end process opcode_decoder;
-
-
-
-end op_dec_structure;
Index: doc/wbspec_b4.pdf
===================================================================
--- doc/wbspec_b4.pdf (revision 37)
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