URL
https://opencores.org/ocsvn/axi4_tlm_bfm/axi4_tlm_bfm/trunk
Subversion Repositories axi4_tlm_bfm
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- This comparison shows the changes necessary to convert path
/axi4_tlm_bfm/trunk/tester
- from Rev 20 to Rev 24
- ↔ Reverse comparison
Rev 20 → Rev 24
/questa/waves.do
File deleted
questa/waves.do
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: questa/simulate.sh
===================================================================
--- questa/simulate.sh (revision 20)
+++ questa/simulate.sh (nonexistent)
@@ -1,65 +0,0 @@
-#!/bin/bash
-#
-# Example bash script for Mentor Graphics QuestaSim/ModelSim simulation.
-#
-# Author(s):
-# - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
-#
-# Copyright (C) 2012-2013 Authors and OPENCORES.ORG
-#
-# This program is free software: you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation, either version 3 of the License, or
-# (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program. If not, see
questa/simulate.sh
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: tester.vhdl
===================================================================
--- tester.vhdl (nonexistent)
+++ tester.vhdl (revision 24)
@@ -0,0 +1,386 @@
+/*
+ This file is part of the AXI4 Transactor and Bus Functional Model
+ (axi4_tlm_bfm) project:
+ http://www.opencores.org/project,axi4_tlm_bfm
+
+ Description
+ Synthesisable use case for AXI4 on-chip messaging.
+
+ To Do:
+
+ Author(s):
+ - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
+
+ Copyright (C) 2012-2013 Authors and OPENCORES.ORG
+
+ This source file may be used and distributed without
+ restriction provided that this copyright statement is not
+ removed from the file and that any derivative work contains
+ the original copyright notice and the associated disclaimer.
+
+ This source file is free software; you can redistribute it
+ and/or modify it under the terms of the GNU Lesser General
+ Public License as published by the Free Software Foundation;
+ either version 2.1 of the License, or (at your option) any
+ later version.
+
+ This source is distributed in the hope that it will be
+ useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+ PURPOSE. See the GNU Lesser General Public License for more
+ details.
+
+ You should have received a copy of the GNU Lesser General
+ Public License along with this source; if not, download it
+ from http://www.opencores.org/lgpl.shtml.
+*/
+library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all;
+library tauhop; use tauhop.transactor.all, tauhop.axiTransactor.all; --TODO just use axiTransactor here as transactor should already be wrapped up.
+
+/* TODO remove once generic packages are supported. */
+--library tauhop; use tauhop.tlm.all, tauhop.axiTLM.all;
+
+/* synthesis translate_off */
+library osvvm; use osvvm.RandomPkg.all; use osvvm.CoveragePkg.all;
+/* synthesis translate_on */
+
+--library altera; use altera.stp;
+
+
+entity tester is port(
+ /* Comment-out for simulation. */
+ clk,reset:in std_ulogic;
+
+ /* AXI Master interface */
+ axiMaster_in:buffer t_axi4StreamTransactor_s2m;
+ axiMaster_out:in t_axi4StreamTransactor_m2s;
+
+ /* BFM signalling. */
+-- readRequest,writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
+-- readResponse,writeResponse:t_bfm;
+ readRequest,writeRequest:buffer t_bfm;
+ readResponse,writeResponse:in t_bfm;
+
+ irq_write:buffer std_ulogic; -- clock gating.
+
+ symbolsPerTransfer:buffer t_cnt;
+ outstandingTransactions:buffer t_cnt;
+
+ /* Debug ports. */
+-- dataIn:in t_msg;
+ selTxn:in unsigned(3 downto 0)
+);
+end entity tester;
+
+architecture rtl of tester is
+-- signal reset:std_ulogic:='0';
+ signal locked:std_ulogic;
+ signal porCnt:unsigned(3 downto 0);
+ signal trigger:boolean;
+
+ /* Global counters. */
+ constant maxSymbols:positive:=2048; --maximum number of symbols allowed to be transmitted in a frame. Each symbol's width equals tData's width.
+-- signal symbolsPerTransfer:t_cnt;
+-- signal outstandingTransactions:t_cnt;
+
+-- /* BFM signalling. */
+-- signal readRequest,writeRequest:t_bfm:=(address=>(others=>'X'),message=>(others=>'X'),trigger=>false);
+-- signal readResponse,writeResponse:t_bfm;
+
+ type txStates is (idle,transmitting);
+ signal txFSM,i_txFSM:txStates;
+
+ /* Tester signals. */
+ /* synthesis translate_off */
+-- signal clk,nReset:std_ulogic:='0';
+ attribute period:time; attribute period of clk:signal is 10 ps;
+ /* synthesis translate_on */
+
+ signal testerClk:std_ulogic;
+ signal dbg_axiTxFSM:axiBfmStatesTx;
+ signal anlysr_dataIn:std_logic_vector(127 downto 0);
+ signal anlysr_trigger:std_ulogic;
+
+-- signal axiMaster_in:t_axi4StreamTransactor_s2m;
+-- signal irq_write:std_ulogic; -- clock gating.
+
+ signal prbs:t_msg;
+
+begin
+ /* PLL to generate tester's clock. */
+/* f100MHz: entity altera.pll(syn) port map(
+ areset=>'0', --not nReset,
+ inclk0=>clk,
+ c0=>testerClk,
+ locked=>locked
+ );
+*/
+ /* Interrupt-request generator. */
+ trigger<=txFSM/=i_txFSM or writeResponse.trigger;
+ irq_write<=clk when not reset else '0';
+
+ /* SignalTap II embedded logic analyser. Included as part of BiST architecture. */
+ --anlysr_trigger<='1' when writeRequest.trigger else '0';
+ anlysr_trigger<='1' when reset else '0';
+
+ /* Disable this for synthesis as this is not currently synthesisable.
+ Pull the framerFSM statemachine signal from lower down the hierarchy to this level instead.
+ */
+ /* synthesis translate_off */
+ --framerFSM<=to_unsigned(<>,framerFSM'length);
+ /* synthesis translate_on */
+
+ anlysr_dataIn(7 downto 0)<=std_logic_vector(symbolsPerTransfer(7 downto 0));
+ anlysr_dataIn(15 downto 8)<=std_logic_vector(outstandingTransactions(7 downto 0));
+ --anlysr_dataIn(2 downto 0) <= <>;
+ anlysr_dataIn(17 downto 16)<=to_std_logic_vector(dbg_axiTxFSM);
+ anlysr_dataIn(18)<='1' when clk else '0';
+ anlysr_dataIn(19)<='1' when reset else '0';
+ anlysr_dataIn(20)<='1' when irq_write else '0';
+ anlysr_dataIn(21)<='1' when axiMaster_in.tReady else '0';
+ anlysr_dataIn(22)<='1' when axiMaster_out.tValid else '0';
+ anlysr_dataIn(54 downto 23)<=std_logic_vector(axiMaster_out.tData);
+ anlysr_dataIn(86 downto 55)<=std_logic_vector(prbs);
+ --anlysr_dataIn(90 downto 87)<=std_logic_vector(axiMaster_out.tStrb);
+ --anlysr_dataIn(94 downto 91)<=std_logic_vector(axiMaster_out.tKeep);
+ anlysr_dataIn(95)<='1' when axiMaster_out.tLast else '0';
+ anlysr_dataIn(96)<='1' when writeRequest.trigger else '0';
+ anlysr_dataIn(97)<='1' when writeResponse.trigger else '0';
+ anlysr_dataIn(99 downto 98)<=to_std_logic_vector(dbg_axiTxFSM);
+ anlysr_dataIn(101 downto 98)<=std_logic_vector(porCnt);
+-- anlysr_dataIn(102)<='1' when locked else '0';
+-- anlysr_dataIn(102)<=locked;
+
+ anlysr_dataIn(anlysr_dataIn'high downto 102)<=(others=>'0');
+
+
+ /* Simulate only if you have compiled Altera's simulation libraries. */
+/* i_bist_logicAnalyser: entity altera.stp(syn) port map(
+ acq_clk=>testerClk,
+ acq_data_in=>anlysr_dataIn,
+ acq_trigger_in=>"1",
+ trigger_in=>anlysr_trigger
+ );
+*/
+
+
+ /* Stimuli sequencer. TODO move to tester/stimuli.
+ This emulates the AXI4-Stream Slave.
+ */
+ /* Simulation-only stimuli sequencer. */
+ /* synthesis translate_off */
+ process is begin
+ report "Performing fast read..." severity note;
+
+ /* Fast read. */
+ while not axiMaster_out.tLast loop
+ /* Wait for tValid to assert. */
+ while not axiMaster_out.tValid loop
+ wait until falling_edge(clk);
+ end loop;
+
+ axiMaster_in.tReady<=true;
+
+ wait until falling_edge(clk);
+ axiMaster_in.tReady<=false;
+ end loop;
+
+ wait until falling_edge(clk);
+ report "Performing normal read..." severity note;
+
+ /* Normal read. */
+ while not axiMaster_out.tLast loop
+ /* Wait for tValid to assert. */
+ while not axiMaster_out.tValid loop
+ wait until falling_edge(clk);
+ end loop;
+
+ wait until falling_edge(clk);
+ wait until falling_edge(clk);
+ axiMaster_in.tReady<=true;
+
+ wait until falling_edge(clk);
+ axiMaster_in.tReady<=false;
+
+ wait until falling_edge(clk);
+ end loop;
+
+ report "Completed normal read." severity note;
+
+ for i in 0 to 10 loop
+ wait until falling_edge(clk);
+ end loop;
+
+ /* One-shot read. */
+ axiMaster_in.tReady<=true;
+
+ wait until falling_edge(clk);
+ axiMaster_in.tReady<=false;
+
+ report "Completed one-shot read." severity note;
+
+ wait;
+ end process;
+ /* synthesis translate_on */
+
+ /* Synthesisable stimuli sequencer. */
+/* process(clk) is begin
+ if falling_edge(clk) then
+ axiMaster_in.tReady<=false;
+ --if axiMaster_out.tValid and not axiMaster_out.tLast then
+ if not axiMaster_in.tReady and axiMaster_out.tValid and not axiMaster_out.tLast then
+ axiMaster_in.tReady<=true;
+ end if;
+ end if;
+ end process;
+*/
+
+ /* Data transmitter. */
+ i_prbs: entity tauhop.prbs31(rtl)
+ generic map(
+ isParallelLoad=>true,
+ tapVector=>(
+ /* Example polynomial from Wikipedia:
+ http://en.wikipedia.org/wiki/Computation_of_cyclic_redundancy_checks
+ */
+ 0|3|31=>true, 1|2|30 downto 4=>false
+ )
+ )
+ port map(
+ /* Comment-out for simulation. */
+ clk=>irq_write, reset=>reset,
+ en=>trigger,
+ seed=>32x"ace1", --9x"57",
+ prbs=>prbs
+ );
+
+ sequencer_ns: process(all) is begin
+ txFSM<=i_txFSM;
+ if reset then txFSM<=idle;
+ else
+ case i_txFSM is
+ when idle=>
+ if outstandingTransactions>0 then txFSM<=transmitting; end if;
+ when transmitting=>
+ if axiMaster_out.tLast then
+ txFSM<=idle;
+ end if;
+ when others=> null;
+ end case;
+ end if;
+ end process sequencer_ns;
+
+ sequencer_op: process(reset,irq_write) is
+ /* Local procedures to map BFM signals with the package procedure. */
+ procedure read(address:in t_addr) is begin
+ read(readRequest,address);
+ end procedure read;
+
+ procedure write(data:in t_msg) is begin
+ write(request=>writeRequest, address=>(others=>'-'), data=>data);
+ end procedure write;
+
+ variable isPktError:boolean;
+
+ /* Tester variables. */
+ /* Synthesis-only randomisation. */
+
+ /* Simulation-only randomisation. */
+ /* synthesis translate_off */
+ variable rv0:RandomPType;
+ /* synthesis translate_on */
+
+-- variable trigger:boolean;
+ begin
+-- if reset then
+ /* simulation only. */
+ /* synthesis translate_off */
+-- rv0.InitSeed(rv0'instance_name);
+ /* synthesis translate_on */
+ if falling_edge(irq_write) then
+ case txFSM is
+ when transmitting=>
+ if trigger then
+ /* Pseudorandom stimuli generation using OS-VVM. */
+ /* synthesis translate_off */
+ write(rv0.RandSigned(axiMaster_out.tData'length));
+ /* synthesis translate_on */
+
+ /* Pseudorandom stimuli generation using LFSR. */
+ /*
+ case selTxn is
+ when x"1"=> write(32x"12ab34cd");
+ when x"2"=> write(32x"12345678");
+ when x"3"=> write(32x"87654321");
+ when x"4"=> write(32x"abcd1234");
+ when others=> write(prbs);
+ end case;
+ */
+ end if;
+ when others=>null;
+ end case;
+ end if;
+ end process sequencer_op;
+
+ sequencer_regs: process(irq_write) is begin
+ if falling_edge(irq_write) then
+ i_txFSM<=txFSM;
+ end if;
+ end process sequencer_regs;
+
+ /* Transaction counter. */
+ process(reset,symbolsPerTransfer,irq_write) is begin
+ /* TODO close timing for asynchronous reset. */
+ if reset then outstandingTransactions<=symbolsPerTransfer;
+ elsif rising_edge(irq_write) then
+ if not axiMaster_out.tLast then
+ if outstandingTransactions<1 then
+ outstandingTransactions<=symbolsPerTransfer;
+ report "No more pending transactions." severity note;
+ elsif axiMaster_in.tReady then outstandingTransactions<=outstandingTransactions-1;
+ end if;
+ end if;
+
+ /* Use synchronous reset for outstandingTransactions to meet timing because it is a huge register set. */
+ if reset then outstandingTransactions<=symbolsPerTransfer; end if;
+ end if;
+ end process;
+
+ /* Reset symbolsPerTransfer to new value (prepare for new transfer) after current transfer has been completed. */
+ process(reset,irq_write) is
+ /* synthesis translate_off */
+ variable rv0:RandomPType;
+ /* synthesis translate_on */
+ begin
+ if reset then
+ /* synthesis translate_off */
+ rv0.InitSeed(rv0'instance_name);
+ symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
+ report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length)) severity note;
+ /* synthesis translate_on */
+
+ symbolsPerTransfer<=128x"fc";
+ elsif rising_edge(irq_write) then
+ if axiMaster_out.tLast then
+ /* synthesis only. */
+ /* Testcase 1: number of symbols per transfer becomes 0 after first stream transfer. */
+ --symbolsPerTransfer<=(others=>'0');
+
+ /* Testcase 2: number of symbols per transfer is randomised. */
+ --uniform(seed0,seed1,rand0);
+ --symbolsPerTransfer<=120x"0" & to_unsigned(integer(rand0 * 2.0**8),8); --symbolsPerTransfer'length
+ --report "symbols per transfer = " & ieee.numeric_std.to_hstring(to_unsigned(integer(rand0 * 2.0**8),8)); --axiMaster_out.tData'length));
+
+
+ /* synthesis translate_off */
+ symbolsPerTransfer<=120x"0" & rv0.RandUnsigned(8);
+ report "symbols per transfer = 0x" & ieee.numeric_std.to_hstring(rv0.RandUnsigned(axiMaster_out.tData'length)) severity note;
+ /* synthesis translate_on */
+
+ symbolsPerTransfer<=128x"0f"; --128x"ffffffff_ffffffff_ffffffff_ffffffff";
+ end if;
+ end if;
+ end process;
+
+-- outstandingTransactions<=128x"fc"; --symbolsPerTransfer;
+end architecture rtl;
tester.vhdl
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: stimuli/prbs-31.vhdl
===================================================================
--- stimuli/prbs-31.vhdl (nonexistent)
+++ stimuli/prbs-31.vhdl (revision 24)
@@ -0,0 +1,128 @@
+/*
+ This file is part of the Galois Linear Feedback Shift Register
+ (galois_lfsr) project:
+ http://www.opencores.org/project,galois_lfsr
+
+ Description
+ Synthesisable use case for Galois LFSR.
+ This example is a CRC generator that uses a Galois LFSR.
+
+ ToDo:
+
+ Author(s):
+ - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
+
+ Copyright (C) 2012-2013 Authors and OPENCORES.ORG
+
+ This source file may be used and distributed without
+ restriction provided that this copyright statement is not
+ removed from the file and that any derivative work contains
+ the original copyright notice and the associated disclaimer.
+
+ This source file is free software; you can redistribute it
+ and/or modify it under the terms of the GNU Lesser General
+ Public License as published by the Free Software Foundation;
+ either version 2.1 of the License, or (at your option) any
+ later version.
+
+ This source is distributed in the hope that it will be
+ useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+ PURPOSE. See the GNU Lesser General Public License for more
+ details.
+
+ You should have received a copy of the GNU Lesser General
+ Public License along with this source; if not, download it
+ from http://www.opencores.org/lgpl.shtml.
+*/
+library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all;
+/* Enable for synthesis; comment out for simulation.
+ For this design, we just need boolean_vector. This is already included in Questa/ModelSim,
+ but Quartus doesn't yet support this.
+*/
+library tauhop; use tauhop.types.all, tauhop.axiTransactor.all;
+
+entity prbs31 is
+ generic(
+ isParallelLoad:boolean:=false;
+ tapVector:boolean_vector:=(
+ /* Example polynomial from Wikipedia:
+ http://en.wikipedia.org/wiki/Computation_of_cyclic_redundancy_checks
+ */
+ --0|1|2|8=>true, 7 downto 3=>false
+ 0|3|31=>true, 1|2|30 downto 4=>false
+ )
+ );
+ port(
+ /* Comment-out for simulation. */
+ clk,reset:in std_ulogic;
+ en:in boolean;
+-- seed:in unsigned(tapVector'high downto 0);
+-- prbs:out unsigned(31 downto 0):=(others=>'0')
+ seed:in i_transactor.t_msg;
+ prbs:out i_transactor.t_msg
+ );
+end entity prbs31;
+
+architecture rtl of prbs31 is
+ signal n,c:natural;
+
+ /* Tester signals. */
+ signal d:std_ulogic;
+ /* synthesis translate_off */
+-- signal clk,reset:std_ulogic:='0';
+ /* synthesis translate_on */
+
+ signal loadEn:std_ulogic; -- clock gating.
+ signal load:boolean;
+-- signal loadEn,computeClk:std_ulogic; -- clock gating.
+ signal loaded,i_loaded:boolean;
+-- signal computed,i_computed:boolean;
+
+begin
+-- loadEn<=clk when reset='0' and not i_computed else '0';
+ loadEn<=clk when reset='0' and en else '0';
+
+ /* Galois LFSR instance. */
+ i_lfsr: entity tauhop.lfsr(rtl)
+ generic map(taps=>tapVector)
+ /*generic map(taps => (
+ 0|1|2|8=>true,
+ 7 downto 3=>false
+ ))*/
+ port map(nReset=>not reset, clk=>loadEn,
+-- load=>isParallelLoad,
+ load=>load,
+ seed=>seed,
+ d=>d,
+ q=>prbs(prbs'range)
+ );
+
+ /* Load message into LFSR. */
+ process(reset,loadEn) is begin
+ if reset then loaded<=false; n<=seed'length-1; d<='0';
+-- if reset then loaded<=false; n<=seed'length-1;
+ elsif rising_edge(loadEn) then
+ d<='0';
+
+ /* for parallel mode, LFSR automatically loads the seed in parallel. */
+ if isParallelLoad then loaded<=true;
+ else
+ if not loaded then d<=seed(n); end if;
+
+ if n>0 then n<=n-1;
+ else loaded<=true;
+ end if;
+ end if;
+ end if;
+ end process;
+
+ load<=(loaded xor i_loaded) and isParallelLoad and reset='0';
+
+ /* Register pipelines. */
+ process(clk) is begin
+ if rising_edge(clk) then
+ i_loaded<=loaded;
+ end if;
+ end process;
+end architecture rtl;
stimuli/prbs-31.vhdl
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: stimuli/prbs-15.vhdl
===================================================================
--- stimuli/prbs-15.vhdl (nonexistent)
+++ stimuli/prbs-15.vhdl (revision 24)
@@ -0,0 +1,117 @@
+/*
+ This file is part of the Galois Linear Feedback Shift Register
+ (galois_lfsr) project:
+ http://www.opencores.org/project,galois_lfsr
+
+ Description
+ Synthesisable use case for Galois LFSR.
+ This example is a CRC generator that uses a Galois LFSR.
+
+ ToDo:
+
+ Author(s):
+ - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
+
+ Copyright (C) 2012-2013 Authors and OPENCORES.ORG
+
+ This source file may be used and distributed without
+ restriction provided that this copyright statement is not
+ removed from the file and that any derivative work contains
+ the original copyright notice and the associated disclaimer.
+
+ This source file is free software; you can redistribute it
+ and/or modify it under the terms of the GNU Lesser General
+ Public License as published by the Free Software Foundation;
+ either version 2.1 of the License, or (at your option) any
+ later version.
+
+ This source is distributed in the hope that it will be
+ useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+ PURPOSE. See the GNU Lesser General Public License for more
+ details.
+
+ You should have received a copy of the GNU Lesser General
+ Public License along with this source; if not, download it
+ from http://www.opencores.org/lgpl.shtml.
+*/
+library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; use ieee.math_real.all;
+/* Enable for synthesis; comment out for simulation.
+ For this design, we just need boolean_vector. This is already included in Questa/ModelSim,
+ but Quartus doesn't yet support this.
+*/
+library tauhop; use tauhop.types.all;
+
+entity prbs15 is
+ generic(
+ parallelLoad:boolean:=false;
+ tapVector:boolean_vector:=(
+ /* Example polynomial from Wikipedia:
+ http://en.wikipedia.org/wiki/Computation_of_cyclic_redundancy_checks
+ */
+ --0|1|2|8=>true, 7 downto 3=>false
+ 0|1|15=>true, 14 downto 2=>false
+ )
+ );
+ port(
+ /* Comment-out for simulation. */
+ clk,reset:in std_ulogic;
+ seed:in unsigned(tapVector'high downto 0):=16x"ace1"; --9x"57";
+ prbs:out unsigned(15 downto 0):=(others=>'0')
+ );
+end entity prbs15;
+
+architecture rtl of prbs15 is
+ signal n,c:natural;
+
+ /* Tester signals. */
+ signal d:std_ulogic;
+ /* synthesis translate_off */
+-- signal clk,reset:std_ulogic:='0';
+ /* synthesis translate_on */
+
+ signal loadEn:std_ulogic; -- clock gating.
+-- signal loadEn,computeClk:std_ulogic; -- clock gating.
+ signal loaded:boolean;
+-- signal computed,i_computed:boolean;
+
+begin
+-- loadEn<=clk when reset='0' and not i_computed else '0';
+ loadEn<=clk when reset='0' else '0';
+
+ /* Galois LFSR instance. */
+ i_lfsr: entity work.lfsr(rtl)
+ generic map(taps=>tapVector)
+ /*generic map(taps => (
+ 0|1|2|8=>true,
+ 7 downto 3=>false
+ ))*/
+ port map(nReset=>not reset, clk=>loadEn,
+ load=>parallelLoad,
+ seed=>seed,
+ d=>d,
+ q=>prbs(prbs'range)
+ );
+
+ /* Load message into LFSR. */
+ process(reset,loadEn) is begin
+ if reset then loaded<=false; n<=seed'length-1; d<='0';
+-- if reset then loaded<=false; n<=seed'length-1;
+ elsif rising_edge(loadEn) then
+ d<='0';
+
+ /* for parallel mode, LFSR automatically loads the seed in parallel. */
+ if parallelLoad then d<='0'; loaded<=true;
+-- if parallelLoad then loaded<=true;
+ else
+ if not loaded then d<=seed(n); end if;
+
+ if n>0 then n<=n-1;
+ else loaded<=true;
+ end if;
+ end if;
+ end if;
+ end process;
+
+-- d<=seed(n) when rising_edge(loadEn);
+end architecture rtl;
stimuli/prbs-15.vhdl
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## -0,0 +1 ##
+*
\ No newline at end of property
Index: stimuli/galois-lfsr.vhdl
===================================================================
--- stimuli/galois-lfsr.vhdl (nonexistent)
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+/*
+ This file is part of the Galois-type linear-feedback shift register
+ (galois_lfsr) project:
+ http://www.opencores.org/project,galois_lfsr
+
+ Description
+ Synthesisable use case for Galois LFSR.
+ This example is a CRC generator that uses a Galois LFSR.
+ Example applications include:
+ * serial or parallel PRBS generation.
+ * CRC computation.
+ * digital scramblers/descramblers.
+
+ ToDo:
+
+ Author(s):
+ - Daniel C.K. Kho, daniel.kho@opencores.org | daniel.kho@tauhop.com
+
+ Copyright (C) 2012-2013 Authors and OPENCORES.ORG
+
+ This source file may be used and distributed without
+ restriction provided that this copyright statement is not
+ removed from the file and that any derivative work contains
+ the original copyright notice and the associated disclaimer.
+
+ This source file is free software; you can redistribute it
+ and/or modify it under the terms of the GNU Lesser General
+ Public License as published by the Free Software Foundation;
+ either version 2.1 of the License, or (at your option) any
+ later version.
+
+ This source is distributed in the hope that it will be
+ useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
+ PURPOSE. See the GNU Lesser General Public License for more
+ details.
+
+ You should have received a copy of the GNU Lesser General
+ Public License along with this source; if not, download it
+ from http://www.opencores.org/lgpl.shtml.
+*/
+library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
+/* Enable for synthesis; comment out for simulation.
+ For this design, we just need boolean_vector. This is already included in Questa/ModelSim,
+ but Quartus doesn't yet support this.
+*/
+library tauhop; use tauhop.types.all, tauhop.axiTransactor.all;
+
+entity lfsr is generic(
+ /*
+ * Tap vector: a TRUE means that position is tapped, otherwise that position is untapped.
+ */
+ taps:boolean_vector
+ );
+
+ port(nReset,clk:in std_ulogic:='0';
+ load:in boolean;
+-- seed:in unsigned(taps'high downto 0);
+ seed:in i_transactor.t_msg;
+
+ d:in std_ulogic;
+-- q:out unsigned(taps'high downto 0)
+ q:out i_transactor.t_msg
+ );
+end entity lfsr;
+
+architecture rtl of lfsr is
+-- signal i_d,i_q:unsigned(taps'high downto 0);
+-- signal x:unsigned(taps'high-1 downto 0);
+ signal i_d,i_q:i_transactor.t_msg;
+ signal x:i_transactor.t_msg;
+
+begin
+-- /* [begin]: Simulation testbench stimuli. Do not remove.
+-- TODO migrate to separate testbench when more testcases are developed.
+-- */
+-- /* synthesis translate_off */
+-- clk<=not clk after 1 ns;
+-- /* synthesis translate_on */
+-- /* [end]: simulation stimuli. */
+
+
+ /* Receives a vector of taps; generates LFSR structure with correct XOR positionings. */
+ tapGenr: for i in 0 to taps'high-1 generate
+ i_d(i+1)<=x(i) when taps(i) else i_q(i);
+ x(i)<=i_q(i) xor i_q(taps'high);
+ end generate;
+
+ process(nReset,load,seed,clk) is begin
+ if nReset='0' then i_q<=(others=>'0');
+ elsif load then i_q<=seed;
+ elsif rising_edge(clk) then
+ i_q<=i_d;
+ end if;
+ end process;
+
+ i_d(0)<=d;
+ q<=i_d;
+
+end architecture rtl;
stimuli/galois-lfsr.vhdl
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