OpenCores
URL https://opencores.org/ocsvn/axi_slave/axi_slave/trunk

Subversion Repositories axi_slave

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /axi_slave
    from Rev 1 to Rev 2
    ↔ Reverse comparison
  •

Rev 1 → Rev 2

/trunk/run/run.sh
0,0 → 1,9
#!/bin/bash
 
echo Starting RobustVerilog axi slave run
rm -rf out
mkdir out
 
../../../robust ../src/base/axi_slave.v -od out -I ../src/gen -list filelist.txt -listpath -header
 
echo Completed RobustVerilog axi slave run - results in run/out/
/trunk/src/gen/prgen_fifo.v
0,0 → 1,196
/////////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
/////////////////////////////////////////////////////////////////////
 
IFDEF STUB
OUTFILE prgen_fifo_stub.v
module prgen_fifo_stub(PORTS);
ELSE STUB
OUTFILE prgen_fifo.v
module prgen_fifo(PORTS);
ENDIF STUB
parameter WIDTH = 8;
parameter DEPTH_FULL = 8;
 
parameter SINGLE = DEPTH_FULL == 1;
parameter DEPTH = SINGLE ? 1 : DEPTH_FULL -1;
parameter DEPTH_BITS =
(DEPTH <= 2) ? 1 :
(DEPTH <= 4) ? 2 :
(DEPTH <= 8) ? 3 :
(DEPTH <= 16) ? 4 :
(DEPTH <= 32) ? 5 :
(DEPTH <= 64) ? 6 :
(DEPTH <= 128) ? 7 :
(DEPTH <= 256) ? 8 :
(DEPTH <= 512) ? 9 : 0; //0 is ilegal
 
parameter LAST_LINE = DEPTH-1;
 
input clk;
input reset;
 
input push;
input pop;
input [WIDTH-1:0] din;
output [WIDTH-1:0] dout;
IF STUB output [DEPTH_BITS:0] fullness;
output empty;
output full;
 
wire reg_push;
wire reg_pop;
wire fifo_push;
wire fifo_pop;
reg [DEPTH-1:0] full_mask_in;
reg [DEPTH-1:0] full_mask_out;
reg [DEPTH-1:0] full_mask;
reg [WIDTH-1:0] fifo [DEPTH-1:0];
wire fifo_empty;
wire next;
reg [WIDTH-1:0] dout;
reg dout_empty;
reg [DEPTH_BITS-1:0] ptr_in;
reg [DEPTH_BITS-1:0] ptr_out;
 
 
assign reg_push = push & fifo_empty & (dout_empty | pop);
assign reg_pop = pop & fifo_empty;
assign fifo_push = !SINGLE & push & (~reg_push);
assign fifo_pop = !SINGLE & pop & (~reg_pop);
always @(posedge clk or posedge reset)
if (reset)
begin
dout <= #FFD {WIDTH{1'b0}};
dout_empty <= #FFD 1'b1;
end
else if (reg_push)
begin
dout <= #FFD din;
dout_empty <= #FFD 1'b0;
end
else if (reg_pop)
begin
dout <= #FFD {WIDTH{1'b0}};
dout_empty <= #FFD 1'b1;
end
else if (fifo_pop)
begin
dout <= #FFD fifo[ptr_out];
dout_empty <= #FFD 1'b0;
end
always @(posedge clk or posedge reset)
if (reset)
ptr_in <= #FFD {DEPTH_BITS{1'b0}};
else if (fifo_push)
ptr_in <= #FFD ptr_in == LAST_LINE ? 0 : ptr_in + 1'b1;
 
always @(posedge clk or posedge reset)
if (reset)
ptr_out <= #FFD {DEPTH_BITS{1'b0}};
else if (fifo_pop)
ptr_out <= #FFD ptr_out == LAST_LINE ? 0 : ptr_out + 1'b1;
 
always @(posedge clk)
if (fifo_push)
fifo[ptr_in] <= #FFD din;
 
always @(/*AUTOSENSE*/fifo_push or ptr_in)
begin
full_mask_in = {DEPTH{1'b0}};
full_mask_in[ptr_in] = fifo_push;
end
always @(/*AUTOSENSE*/fifo_pop or ptr_out)
begin
full_mask_out = {DEPTH{1'b0}};
full_mask_out[ptr_out] = fifo_pop;
end
always @(posedge clk or posedge reset)
if (reset)
full_mask <= #FFD {DEPTH{1'b0}};
else if (fifo_push | fifo_pop)
full_mask <= #FFD (full_mask & (~full_mask_out)) | full_mask_in;
 
 
assign next = |full_mask;
assign fifo_empty = ~next;
assign empty = fifo_empty & dout_empty;
assign full = SINGLE ? !dout_empty : &full_mask;
 
 
IFDEF STUB
reg [DEPTH_BITS:0] fullness;
always @(posedge clk or posedge reset)
if (reset)
fullness <= #FFD {DEPTH_BITS+1{1'b0}};
else if (push | pop)
fullness <= #FFD fullness + push - pop;
wire overflow = full & fifo_push & (~fifo_pop);
wire underflow = empty & fifo_pop & (~fifo_push);
always @(posedge overflow)
begin
#1;
if (overflow)
begin
$display("-E-%m - overflow.\tTime: %0d ns", $time);
#1000;
$finish;
end
end
always @(posedge underflow)
begin
#1;
if (underflow)
begin
$display("-E-%m - underflow.\tTime: %0d ns", $time);
#1000;
$finish;
end
end
ENDIF STUB
endmodule
 
 
/trunk/src/gen/prgen_rand.v
0,0 → 1,87
/////////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
/////////////////////////////////////////////////////////////////////
 
function integer rand_chance;
input [31:0] chance_true;
 
begin
if (chance_true > 100)
begin
$display("RAND_CHANCE-E-: fatal error, rand_chance called with percent chance larger than 100.\tTime: %0d ns", $time);
$finish;
end
rand_chance = (rand(1,100) <= chance_true);
end
endfunction // rand_chance
 
 
function integer rand;
input [31:0] min;
input [31:0] max;
 
integer range;
begin
if (min > max)
begin
$display("RAND-E-: fatal error, rand was called with min larger than max.\tTime: %0d ns", $time);
$finish;
end
 
range = (max - min) + 1;
if (range == 0) range = -1;
rand = min + ($random % range);
end
endfunction // rand
 
 
function integer align;
input [31:0] num;
input [31:0] align_size;
integer align;
begin
align = num - (num % align_size);
end
endfunction
 
 
function integer rand_align;
input [31:0] min;
input [31:0] max;
input [31:0] align;
 
integer rand_align;
begin
rand_align = rand(min, max);
if (rand_align > align)
rand_align = align(rand_align, align);
end
endfunction
 
/trunk/src/base/axi_slave.v
0,0 → 1,82
/////////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
/////////////////////////////////////////////////////////////////////
 
OUTFILE PREFIX.v
 
INCLUDE def_axi_slave.txt
module PREFIX(PORTS);
parameter SLAVE_NUM = 0;
input clk;
input reset;
revport GROUP_STUB_AXI;
 
 
wire GROUP_STUB_MEM;
 
CREATE axi_slave_ram.v
PREFIX_ram PREFIX_ram(
.clk(clk),
.reset(reset),
.GROUP_STUB_AXI(GROUP_STUB_AXI),
.GROUP_STUB_MEM(GROUP_STUB_MEM),
STOMP ,
);
CREATE axi_slave_mem.v
PREFIX_mem PREFIX_mem(
.clk(clk),
.reset(reset),
.GROUP_STUB_MEM(GROUP_STUB_MEM),
STOMP ,
);
 
 
IFDEF TRACE
CREATE axi_slave_trace.v #(SLAVE_NUM)
PREFIX_trace PREFIX_trace(
.clk(clk),
.reset(reset),
.GROUP_STUB_MEM(GROUP_STUB_MEM),
STOMP ,
);
ENDIF TRACE
endmodule
 
 
/trunk/src/base/axi_slave_busy.v
0,0 → 1,187
/////////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
/////////////////////////////////////////////////////////////////////
 
OUTFILE PREFIX_busy.v
 
INCLUDE def_axi_slave.txt
module PREFIX_busy(PORTS);
`include "prgen_rand.v"
input clk;
input reset;
input ARREADY_pre;
input RVALID_pre;
input AWREADY_pre;
input WREADY_pre;
input BVALID_pre;
output ARREADY;
output RVALID;
output AWREADY;
output WREADY;
output BVALID;
 
output RBUSY;
output BBUSY;
 
 
reg stall_enable = 1;
integer burst_chance = 1;
integer burst_len = 10;
integer burst_val = 90;
integer ar_stall_chance = 10;
integer r_stall_chance = 10;
integer aw_stall_chance = 10;
integer w_stall_chance = 10;
integer b_stall_chance = 10;
 
integer burst_type;
reg burst_stall;
integer ar_stall_chance_valid;
integer r_stall_chance_valid;
integer aw_stall_chance_valid;
integer w_stall_chance_valid;
integer b_stall_chance_valid;
reg ARBUSY_pre = 0;
reg RBUSY_pre = 0;
reg AWBUSY_pre = 0;
reg WBUSY_pre = 0;
reg BBUSY_pre = 0;
reg ARBUSY;
reg RBUSY;
reg AWBUSY;
reg WBUSY;
reg BBUSY;
 
 
assign ARREADY = ARREADY_pre & (~ARBUSY);
assign RVALID = RVALID_pre; //in rd_buff
assign AWREADY = AWREADY_pre & (~AWBUSY);
assign WREADY = WREADY_pre & (~WBUSY);
assign BVALID = BVALID_pre; //in wresp
 
 
task set_stall;
reg stall;
begin
ar_stall_chance_valid = ar_stall_chance;
r_stall_chance_valid = r_stall_chance;
aw_stall_chance_valid = aw_stall_chance;
w_stall_chance_valid = w_stall_chance;
b_stall_chance_valid = b_stall_chance;
end
endtask
 
initial
begin
#FFD;
set_stall;
 
if (burst_chance > 0)
forever
begin
burst_stall = rand_chance(burst_chance);
if (burst_stall)
begin
#FFD;
burst_type = rand(1, 5);
case (burst_type)
1 : ar_stall_chance_valid = burst_val;
2 : r_stall_chance_valid = burst_val;
3 : aw_stall_chance_valid = burst_val;
4 : w_stall_chance_valid = burst_val;
5 : b_stall_chance_valid = burst_val;
endcase
repeat (burst_len) @(posedge clk);
set_stall;
end
else
begin
@(posedge clk);
end
end
end
always @(posedge clk)
begin
#FFD;
ARBUSY_pre = rand_chance(ar_stall_chance_valid);
RBUSY_pre = rand_chance(r_stall_chance_valid);
AWBUSY_pre = rand_chance(aw_stall_chance_valid);
WBUSY_pre = rand_chance(w_stall_chance_valid);
BBUSY_pre = rand_chance(b_stall_chance_valid);
end
always @(posedge clk or posedge reset)
if (reset)
begin
ARBUSY <= #FFD 1'b0;
RBUSY <= #FFD 1'b0;
AWBUSY <= #FFD 1'b0;
WBUSY <= #FFD 1'b0;
BBUSY <= #FFD 1'b0;
end
else if (stall_enable)
begin
ARBUSY <= #FFD ARBUSY_pre;
RBUSY <= #FFD RBUSY_pre;
AWBUSY <= #FFD AWBUSY_pre;
WBUSY <= #FFD WBUSY_pre;
BBUSY <= #FFD BBUSY_pre;
end
else
begin
ARBUSY <= #FFD 1'b0;
RBUSY <= #FFD 1'b0;
AWBUSY <= #FFD 1'b0;
WBUSY <= #FFD 1'b0;
BBUSY <= #FFD 1'b0;
end
endmodule
 
 
 
 
 
 
 
/trunk/src/base/axi_slave_addr_gen.v
0,0 → 1,70
/////////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
/////////////////////////////////////////////////////////////////////
 
OUTFILE PREFIX_addr_gen.v
 
INCLUDE def_axi_slave.txt
 
module PREFIX_addr_gen(PORTS);
input clk;
input reset;
 
input [ADDR_BITS-1:0] cmd_addr;
input [1:0] cmd_size;
 
input advance;
input restart;
 
output [ADDR_BITS-1:0] ADDR;
 
reg [ADDR_BITS-1:0] offset;
wire [3:0] size_bytes;
 
assign size_bytes =
cmd_size == 2'b00 ? 4'd1 :
cmd_size == 2'b01 ? 4'd2 :
cmd_size == 2'b10 ? 4'd4 :
cmd_size == 2'b11 ? 4'd8 : 4'd0;
always @(posedge clk or posedge reset)
if (reset)
offset <= #FFD {ADDR_BITS{1'b0}};
else if (restart)
offset <= #FFD {ADDR_BITS{1'b0}};
else if (advance)
offset <= #FFD offset + size_bytes;
 
assign ADDR = cmd_addr + offset;
 
 
endmodule
 
/trunk/src/base/axi_slave_wresp_fifo.v
0,0 → 1,156
/////////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
/////////////////////////////////////////////////////////////////////
 
OUTFILE PREFIX_wresp_fifo.v
 
INCLUDE def_axi_slave.txt
module PREFIX_wresp_fifo (PORTS);
parameter DEPTH = 8;
parameter DEPTH_BITS =
(DEPTH <= 2) ? 1 :
(DEPTH <= 4) ? 2 :
(DEPTH <= 8) ? 3 :
(DEPTH <= 16) ? 4 :
(DEPTH <= 32) ? 5 :
(DEPTH <= 64) ? 6 :
(DEPTH <= 128) ? 7 :
(DEPTH <= 256) ? 8 :
(DEPTH <= 512) ? 9 : 0; //0 is ilegal
input clk;
input reset;
 
input AWVALID;
input AWREADY;
input [ADDR_BITS-1:0] AWADDR;
input WVALID;
input WREADY;
input [ID_BITS-1:0] WID;
input WLAST;
 
output [ID_BITS-1:0] BID;
output [1:0] BRESP;
input BVALID;
input BREADY;
output empty;
output pending;
output timeout;
 
wire timeout_in;
wire timeout_out;
wire [1:0] resp_in;
reg [ADDR_BITS-1:0] SLVERR_addr = {ADDR_BITS{1'b1}};
reg [ADDR_BITS-1:0] DECERR_addr = {ADDR_BITS{1'b1}};
reg [ADDR_BITS-1:0] TIMEOUT_addr = {ADDR_BITS{1'b1}};
 
wire push;
wire push1;
wire pop;
wire empty;
wire full;
wire [DEPTH_BITS:0] fullness;
 
reg pending;
 
parameter RESP_SLVERR = 2'b10;
parameter RESP_DECERR = 2'b11;
assign resp_in =
push1 & (SLVERR_addr == AWADDR) ? RESP_SLVERR :
push1 & (DECERR_addr == AWADDR) ? RESP_DECERR : 2'b00;
 
assign timeout_in = push1 & (TIMEOUT_addr == AWADDR);
assign timeout = timeout_out & (TIMEOUT_addr != 0);
always @(posedge clk or posedge reset)
if (reset)
pending <= #1 1'b0;
else if (BVALID & BREADY)
pending <= #1 1'b0;
else if (BVALID & (~BREADY))
pending <= #1 1'b1;
 
assign push1 = AWVALID & AWREADY;
assign push = WVALID & WREADY & WLAST;
assign pop = BVALID & BREADY;
prgen_fifo_stub #(ID_BITS, DEPTH)
wresp_fifo(
.clk(clk),
.reset(reset),
.push(push),
.pop(pop),
.din({WID
}
),
.dout({BID
}
),
.fullness(fullness),
.empty(empty),
.full(full)
);
prgen_fifo_stub #(2+1, DEPTH*2)
wresp_fifo1(
.clk(clk),
.reset(reset),
.push(push1),
.pop(pop),
.din({resp_in,
timeout_in
}
),
.dout({BRESP,
timeout_out
}
),
.fullness(),
.empty(),
.full()
);
endmodule
 
 
/trunk/src/base/axi_slave_cmd_fifo.v
0,0 → 1,146
/////////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
/////////////////////////////////////////////////////////////////////
 
OUTFILE PREFIX_cmd_fifo.v
 
INCLUDE def_axi_slave.txt
module PREFIX_cmd_fifo (PORTS);
 
parameter DEPTH = 8;
parameter DEPTH_BITS =
(DEPTH <= 2) ? 1 :
(DEPTH <= 4) ? 2 :
(DEPTH <= 8) ? 3 :
(DEPTH <= 16) ? 4 :
(DEPTH <= 32) ? 5 :
(DEPTH <= 64) ? 6 :
(DEPTH <= 128) ? 7 :
(DEPTH <= 256) ? 8 :
(DEPTH <= 512) ? 9 : 0; //0 is ilegal
 
input clk;
input reset;
input [ADDR_BITS-1:0] AADDR;
input [ID_BITS-1:0] AID;
input [1:0] ASIZE;
input [LEN_BITS-1:0] ALEN;
input AVALID;
input AREADY;
 
input VALID;
input READY;
input LAST;
 
output [ADDR_BITS-1:0] cmd_addr;
output [ID_BITS-1:0] cmd_id;
output [1:0] cmd_size;
output [LEN_BITS-1:0] cmd_len;
output [1:0] cmd_resp;
output cmd_timeout;
output cmd_ready;
output cmd_empty;
output cmd_full;
 
 
wire push;
wire pop;
wire empty;
wire full;
wire [DEPTH_BITS:0] fullness;
 
 
wire [1:0] resp_in;
wire timeout_in;
wire timeout_out;
reg [ADDR_BITS-1:0] SLVERR_addr = {ADDR_BITS{1'b1}};
reg [ADDR_BITS-1:0] DECERR_addr = {ADDR_BITS{1'b1}};
reg [ADDR_BITS-1:0] TIMEOUT_addr = {ADDR_BITS{1'b1}};
 
 
parameter RESP_SLVERR = 2'b10;
parameter RESP_DECERR = 2'b11;
 
 
assign resp_in =
push & (SLVERR_addr == AADDR) ? RESP_SLVERR :
push & (DECERR_addr == AADDR) ? RESP_DECERR : 2'b00;
 
assign timeout_in = push & (TIMEOUT_addr == AADDR);
assign cmd_timeout = timeout_out & (TIMEOUT_addr != 0);
assign cmd_full = full | (DEPTH == fullness);
assign cmd_empty = empty;
assign cmd_ready = ~empty;
assign push = AVALID & AREADY;
assign pop = VALID & READY & LAST;
 
CREATE prgen_fifo.v DEFCMD(DEFINE STUB)
prgen_fifo_stub #(ADDR_BITS+ID_BITS+LEN_BITS+2+2+1, DEPTH)
cmd_fifo(
.clk(clk),
.reset(reset),
.push(push),
.pop(pop),
.din({AADDR,
AID,
ASIZE,
ALEN,
resp_in,
timeout_in
}
),
.dout({cmd_addr,
cmd_id,
cmd_size,
cmd_len,
cmd_resp,
timeout_out
}
),
.fullness(fullness),
.empty(empty),
.full(full)
);
endmodule
 
 
/trunk/src/base/axi_slave_rd_buff.v
0,0 → 1,116
/////////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
/////////////////////////////////////////////////////////////////////
 
OUTFILE PREFIX_rd_buff.v
 
INCLUDE def_axi_slave.txt
 
module PREFIX_rd_buff(PORTS);
 
input clk;
input reset;
 
output RD;
input [DATA_BITS-1:0] DOUT;
input [LEN_BITS-1:0] rcmd_len;
input [LEN_BITS-1:0] rcmd_len2;
input [1:0] rcmd_resp;
input rcmd_timeout;
input rcmd_ready;
 
output RVALID;
input RREADY;
output RLAST;
output [DATA_BITS-1:0] RDATA;
output [1:0] RRESP;
output RD_last;
 
input RBUSY;
 
reg [LEN_BITS:0] valid_counter;
reg [LEN_BITS-1:0] rd_counter;
wire cmd_pending;
reg RVALID;
reg [1:0] RRESP;
wire last_rd;
assign cmd_pending = RVALID & (~RREADY);
assign RDATA = DOUT;
 
assign RD = rcmd_ready & (~cmd_pending) & (~RBUSY) & (~rcmd_timeout);
 
assign RD_last = RD & (rd_counter == rcmd_len);
assign RLAST = RVALID & (valid_counter == rcmd_len2 + 1'b1);
 
 
always @(posedge clk or posedge reset)
if (reset)
RRESP <= #FFD 2'b00;
else if (RD)
RRESP <= #FFD rcmd_resp;
always @(posedge clk or posedge reset)
if (reset)
RVALID <= #FFD 1'b0;
else if (RD)
RVALID <= #FFD 1'b1;
else if (RVALID & RREADY)
RVALID <= #FFD 1'b0;
always @(posedge clk or posedge reset)
if (reset)
valid_counter <= #FFD {LEN_BITS+1{1'b0}};
else if (RVALID & RREADY & RLAST & RD)
valid_counter <= #FFD 'd1;
else if (RVALID & RREADY & RLAST)
valid_counter <= #FFD {LEN_BITS+1{1'b0}};
else if (RD)
valid_counter <= #FFD valid_counter + 1'b1;
 
always @(posedge clk or posedge reset)
if (reset)
rd_counter <= #FFD {LEN_BITS{1'b0}};
else if (RD_last)
rd_counter <= #FFD {LEN_BITS{1'b0}};
else if (RD)
rd_counter <= #FFD rd_counter + 1'b1;
 
endmodule
 
/trunk/src/base/def_axi_slave.txt
0,0 → 1,46
<##//////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////##>
 
INCLUDE def_axi_slave_static.txt
 
SWAP.GLOBAL #FFD #1 ##Flip-Flop simulation delay
 
SWAP PREFIX axi_slave ##prefix for all module and file names
SWAP ID_BITS 4 ##AXI ID bits
SWAP ADDR_BITS 24 ##AXI address bits
SWAP DATA_BITS 64 ##AXI data bits
SWAP LEN_BITS 4 ##AXI LEN bits
SWAP SIZE_BITS 2 ##AXI SIZE bits
 
SWAP WCMD_DEPTH 8 ##AXI write command depth
SWAP RCMD_DEPTH 8 ##AXI write command depth
 
##DEFINE TRACE ##print memory trace to file
/trunk/src/base/axi_slave_mem.v
0,0 → 1,64
/////////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
/////////////////////////////////////////////////////////////////////
 
OUTFILE PREFIX_mem.v
 
INCLUDE def_axi_slave.txt
 
ITER BX EXPR(DATA_BITS/8)
module PREFIX_mem (PORTS);
 
parameter MEM_WORDS = EXPR((2^ADDR_BITS)/(DATA_BITS/8));
parameter ADDR_LSB = LOG2(EXPR(DATA_BITS/8));
input clk;
input reset;
revport GROUP_STUB_MEM;
reg [DATA_BITS-1:0] Mem [MEM_WORDS-1:0];
reg [DATA_BITS-1:0] DOUT;
wire [DATA_BITS-1:0] BitSEL;
wire [ADDR_BITS-1:ADDR_LSB] ADDR_WR_word = ADDR_WR[ADDR_BITS-1:ADDR_LSB];
wire [ADDR_BITS-1:ADDR_LSB] ADDR_RD_word = ADDR_RD[ADDR_BITS-1:ADDR_LSB];
 
assign BitSEL = {CONCAT({8{BSEL[BX]}} ,)};
always @(posedge clk)
if (WR)
Mem[ADDR_WR_word] <= #FFD (Mem[ADDR_WR_word] & ~BitSEL) | (DIN & BitSEL);
always @(posedge clk or posedge reset)
if (reset)
DOUT <= #FFD {DATA_BITS{1'b0}};
else if (RD)
DOUT <= #FFD Mem[ADDR_RD_word];
 
endmodule
/trunk/src/base/axi_slave_trace.v
0,0 → 1,81
/////////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
/////////////////////////////////////////////////////////////////////
 
OUTFILE PREFIX_trace.v
 
INCLUDE def_axi_slave.txt
module PREFIX_trace(PORTS);
parameter SLAVE_NUM = 0;
parameter FILE_NAME = "PREFIX.trc";
input clk;
input reset;
 
input GROUP_STUB_MEM;
 
reg RD_d;
reg [ADDR_BITS-1:0] ADDR_RD_d;
 
wire [31:0] ADDR_WR_disp = ADDR_WR;
wire [31:0] ADDR_RD_disp = ADDR_RD_d;
integer file_ptr;
initial
file_ptr = $fopen(FILE_NAME, "w");
 
always @(posedge clk or posedge reset)
if (reset)
begin
ADDR_RD_d <= #FFD 'd0;
RD_d <= #FFD 'd0;
end
else
begin
ADDR_RD_d <= #FFD ADDR_RD;
RD_d <= #FFD RD;
end
always @(posedge clk)
if (WR)
$fwrite(file_ptr, "%16d: %0s WR: Addr: 0x%8h, Data: 0x%8h, Bsel: 0x%2h\n", $time, FILE_NAME, ADDR_WR_disp, DIN, BSEL);
always @(posedge clk)
if (RD_d)
$fwrite(file_ptr, "%16d: %0s RD: Addr: 0x%8h, Data: 0x%8h\n", $time, FILE_NAME, ADDR_RD_disp, DOUT);
 
endmodule
 
/trunk/src/base/axi_slave_ram.v
0,0 → 1,263
/////////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
/////////////////////////////////////////////////////////////////////
 
OUTFILE PREFIX_ram.v
 
INCLUDE def_axi_slave.txt
module PREFIX_ram(PORTS);
 
input clk;
input reset;
revport GROUP_STUB_AXI;
 
port GROUP_STUB_MEM;
//busy
wire ARREADY_pre;
wire RVALID_pre;
wire AWREADY_pre;
wire WREADY_pre;
wire BVALID_pre;
wire RBUSY;
wire BBUSY;
//wcmd fifo
wire [ADDR_BITS-1:0] wcmd_addr;
wire [ID_BITS-1:0] wcmd_id;
wire [1:0] wcmd_size;
wire [LEN_BITS-1:0] wcmd_len;
wire [1:0] wcmd_resp;
wire wcmd_timeout;
wire wcmd_ready;
wire wcmd_empty;
wire wcmd_full;
//rcmd fifo
wire [ADDR_BITS-1:0] rcmd_addr;
wire [ID_BITS-1:0] rcmd_id;
wire [1:0] rcmd_size;
wire [LEN_BITS-1:0] rcmd_len;
wire [1:0] rcmd_resp;
wire rcmd_timeout;
wire rcmd_ready;
wire rcmd_full;
 
wire [ID_BITS-1:0] rcmd_id2;
wire [LEN_BITS-1:0] rcmd_len2;
 
wire wresp_empty;
wire wresp_pending;
wire wresp_timeout;
reg [ADDR_BITS-1:0] TIMEOUT_AR_addr = {ADDR_BITS{1'b1}};
reg [ADDR_BITS-1:0] TIMEOUT_AW_addr = {ADDR_BITS{1'b1}};
wire AR_stall = ARVALID & (TIMEOUT_AR_addr == ARADDR);
wire AW_stall = AWVALID & (TIMEOUT_AW_addr == AWADDR);
wire RD_last;
 
assign RID = rcmd_id2;
 
 
assign ARREADY_pre = (~rcmd_full) & (~AR_stall);
assign AWREADY_pre = (~wcmd_full) & (~AW_stall);
assign BVALID_pre = (~wresp_timeout) & (wresp_pending ? (~wresp_empty) : (~wresp_empty) & (~BBUSY));
 
CREATE axi_slave_busy.v
PREFIX_busy
PREFIX_busy (
.clk(clk),
.reset(reset),
.ARREADY_pre(ARREADY_pre),
.RVALID_pre(RVALID_pre),
.AWREADY_pre(AWREADY_pre),
.WREADY_pre(WREADY_pre),
.BVALID_pre(BVALID_pre),
.ARREADY(ARREADY),
.RVALID(RVALID),
.AWREADY(AWREADY),
.WREADY(WREADY),
.BVALID(BVALID),
.RBUSY(RBUSY),
.BBUSY(BBUSY)
);
 
CREATE axi_slave_cmd_fifo.v
PREFIX_cmd_fifo #(WCMD_DEPTH)
PREFIX_wcmd_fifo (
.clk(clk),
.reset(reset),
.AADDR(AWADDR),
.AID(AWID),
.ASIZE(AWSIZE),
.ALEN(AWLEN),
.AVALID(AWVALID),
.AREADY(AWREADY),
.VALID(WVALID),
.READY(WREADY),
.LAST(WLAST),
.cmd_addr(wcmd_addr),
.cmd_id(wcmd_id), //not used
.cmd_size(wcmd_size),
.cmd_len(wcmd_len), //not used
.cmd_resp(),
.cmd_timeout(wcmd_timeout),
.cmd_ready(wcmd_ready),
.cmd_empty(wcmd_empty),
.cmd_full(wcmd_full)
);
 
PREFIX_cmd_fifo #(RCMD_DEPTH)
PREFIX_rcmd_fifo (
.clk(clk),
.reset(reset),
.AADDR(ARADDR),
.AID(ARID),
.ASIZE(ARSIZE),
.ALEN(ARLEN),
.AVALID(ARVALID),
.AREADY(ARREADY),
.VALID(RD_last),
.READY(1'b1),
.LAST(1'b1),
.cmd_addr(rcmd_addr),
.cmd_id(rcmd_id),
.cmd_size(rcmd_size),
.cmd_len(rcmd_len),
.cmd_resp(rcmd_resp),
.cmd_timeout(rcmd_timeout),
.cmd_ready(rcmd_ready),
.cmd_empty(),
.cmd_full()
);
PREFIX_cmd_fifo #(RCMD_DEPTH)
PREFIX_rcmd_fifo2 (
.clk(clk),
.reset(reset),
.AADDR(ARADDR),
.AID(ARID),
.ASIZE(ARSIZE),
.ALEN(ARLEN),
.AVALID(ARVALID),
.AREADY(ARREADY),
.VALID(RVALID),
.READY(RREADY),
.LAST(RLAST),
.cmd_addr(),
.cmd_id(rcmd_id2),
.cmd_size(),
.cmd_len(rcmd_len2),
.cmd_resp(),
.cmd_timeout(),
.cmd_ready(),
.cmd_empty(),
.cmd_full(rcmd_full)
);
CREATE axi_slave_wresp_fifo.v
PREFIX_wresp_fifo #(WCMD_DEPTH)
PREFIX_wresp_fifo (
.clk(clk),
.reset(reset),
.AWVALID(AWVALID),
.AWREADY(AWREADY),
.AWADDR(AWADDR),
.WVALID(WVALID),
.WREADY(WREADY),
.WLAST(WLAST),
.WID(WID),
.BID(BID),
.BRESP(BRESP),
.BVALID(BVALID),
.BREADY(BREADY),
.empty(wresp_empty),
.pending(wresp_pending),
.timeout(wresp_timeout)
);
CREATE axi_slave_addr_gen.v
PREFIX_addr_gen
PREFIX_addr_gen_wr (
.clk(clk),
.reset(reset),
.cmd_addr(wcmd_addr),
.cmd_size(wcmd_size),
.advance(WVALID & WREADY & (~WLAST)),
.restart(WVALID & WREADY & WLAST),
.ADDR(ADDR_WR)
);
 
 
PREFIX_addr_gen
PREFIX_addr_gen_rd (
.clk(clk),
.reset(reset),
.cmd_addr(rcmd_addr),
.cmd_size(rcmd_size),
.advance(RD),
.restart(RD_last),
.ADDR(ADDR_RD)
);
CREATE axi_slave_rd_buff.v
PREFIX_rd_buff #(DATA_BITS, ID_BITS)
PREFIX_rd_buff(
.clk(clk),
.reset(reset),
.RD(RD),
.DOUT(DOUT),
.rcmd_len(rcmd_len),
.rcmd_len2(rcmd_len2),
.rcmd_resp(rcmd_resp),
.rcmd_timeout(rcmd_timeout),
.rcmd_ready(rcmd_ready),
.RVALID(RVALID_pre),
.RREADY(RREADY),
.RLAST(RLAST),
.RDATA(RDATA),
.RD_last(RD_last),
.RRESP(RRESP),
.RBUSY(RBUSY)
);
 
//wr_buff
assign WREADY_pre = (~wcmd_timeout) & (~wcmd_empty);
assign WR = WVALID & WREADY & (~wcmd_empty);
assign DIN = WDATA;
assign BSEL = WSTRB;
endmodule
 
 
/trunk/src/base/def_axi_slave_static.txt
0,0 → 1,89
<##//////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
//// eyal@provartec.com ////
//// ////
//// Downloaded from: http://www.opencores.org ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2010 Provartec LTD ////
//// www.provartec.com ////
//// info@provartec.com ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation.////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more////
//// details. http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////##>
 
VERIFY (DATA_BITS <= 64) else stub supports 32 or 64 bits data bus
VERIFY (SIZE_BITS <= 3) else stub supports 32 or 64 bits data bus
VERIFY (ADDR_BITS<=24) else Memory size should not be too big to prevent maloc fail
 
GROUP STUB_AXI_A is {
ID ID_BITS output
ADDR ADDR_BITS output
LEN LEN_BITS output
SIZE SIZE_BITS output
BURST 2 output
CACHE 4 output
PROT 3 output
LOCK 2 output
VALID 1 output
READY 1 input
}
 
GROUP STUB_AXI_W is {
ID ID_BITS output
DATA DATA_BITS output
STRB DATA_BITS/8 output
LAST 1 output
VALID 1 output
READY 1 input
}
 
GROUP STUB_AXI_B is {
ID ID_BITS input
RESP 2 input
VALID 1 input
READY 1 output
}
 
GROUP STUB_AXI_R is {
ID ID_BITS input
DATA DATA_BITS input
RESP 2 input
LAST 1 input
VALID 1 input
READY 1 output
}
 
GROUP STUB_AXI joins {
GROUP STUB_AXI_A prefix_AW
GROUP STUB_AXI_W prefix_W
GROUP STUB_AXI_B prefix_B
GROUP STUB_AXI_A prefix_AR
GROUP STUB_AXI_R prefix_R
}
 
GROUP STUB_MEM is {
WR 1 output
RD 1 output
ADDR_WR ADDR_BITS output
ADDR_RD ADDR_BITS output
DIN DATA_BITS output
BSEL DATA_BITS/8 output
DOUT DATA_BITS input
}
/trunk/README.txt
0,0 → 1,20
 
------------------------------ Remark ----------------------------------------
This code is a generic code written in RobustVerilog. In order to convert it to Verilog a RobustVerilog parser is required.
It is possible to download a free RobustVerilog parser from www.provartec.com/edatools.
 
We will be very happy to receive any kind of feedback regarding our tools and cores.
We will also be willing to support any company intending to integrate our cores into their project.
For any questions / remarks / suggestions / bugs please contact info@provartec.com.
------------------------------------------------------------------------------
 
RobustVerilog generic AXI slave stub
 
In order to create the Verilog design use the run.sh script in the run directory (notice that the run scripts calls the robust binary (RobustVerilog parser)).
 
The RobustVerilog top source file is axi_slave.v, it calls the top definition file named def_axi_slave.txt.
 
The default definition file def_axi_master.txt generates an AXI slave with a 64 bit data bus and both read and write command depth of 8.
 
Changing the stub parameters should be made only in def_axi_master.txt in the src/base directory (command depth, address bits, data width etc.).
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.