URL
https://opencores.org/ocsvn/bit_gpio/bit_gpio/trunk
Subversion Repositories bit_gpio
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/bit_gpio
- from Rev 1 to Rev 2
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Rev 1 → Rev 2
/trunk/sopc/hdl/gpio.v
0,0 → 1,88
// -*- Mode: Verilog -*- |
// Filename : gpio.v |
// Description : a bitwise gpio |
// Author : Thomas Chou |
|
// this is a bitwise gpio to be used with i2c,spi,sdio,1 wire etc. |
// it is unlike Altera's pio, each access is bit by bit. |
// it is designed to work with generic gpio interface of Linux |
// so that it will run faster and use less LEs |
// you may turn on FAST_OUTPUT_REGISTER for the port pins to reduce LEs usage further |
// interrupt is not supported |
// port pin[i] can be addressed with base+(i*4) |
// writedata[1] : output enable |
// writedata[0] : output data |
// readdata[0] : input data from pin |
// paramters |
// GPIO_WIDTH for total number of io pins (bidir + input_only), |
// GPIO_BIDIR for number of bidir pins. |
// GPIO_ADDR the address width |
// WIDTH <= 2^ADDR |
|
module gpio ( |
/*AUTOARG*/ |
// Outputs |
readdata, |
// Inouts |
bidir_port, |
// Inputs |
input_port, address, clk, reset_n, write_n, writedata |
); |
|
parameter BIDIR_WIDTH = 8; |
parameter INPUT_WIDTH = 4; |
parameter ADDR_WIDTH = 3; |
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inout [ BIDIR_WIDTH - 1: 0] bidir_port; |
input [ INPUT_WIDTH - 1: 0 ] input_port; |
output [ 1: 0] readdata; |
input [ ADDR_WIDTH - 1: 0] address; |
input clk; |
input reset_n; |
input write_n; |
input [ 1: 0] writedata; |
|
wire [ (BIDIR_WIDTH + INPUT_WIDTH) - 1: 0] data_in; |
reg [ BIDIR_WIDTH - 1: 0] bidir_port; |
reg [ 1: 0] readdata; |
reg [ BIDIR_WIDTH - 1: 0] data_mode; |
reg [ BIDIR_WIDTH - 1: 0] data_outz; |
reg [ BIDIR_WIDTH - 1: 0] data_mode_v; |
reg [ BIDIR_WIDTH - 1: 0] data_outz_v; |
integer N; |
|
assign data_in = { input_port,bidir_port }; |
|
always @(data_mode or data_outz) |
for (N = 0; N <= (BIDIR_WIDTH - 1) ; N = N+1) |
bidir_port[N] = data_mode[N]? ~data_outz[N] : 1'bz; |
|
always @(/*AS*/address or data_in) |
readdata = { 1'b0, data_in[address] }; |
|
always @(/*AS*/BIDIR_WIDTH or address or data_outz or write_n |
or writedata) |
for (N = 0; N <= (BIDIR_WIDTH - 1) ; N = N+1) |
data_outz_v[N] = (~write_n & (address == N)) ? ~writedata[0] : data_outz[N]; |
|
always @(/*AS*/BIDIR_WIDTH or address or data_mode or write_n |
or writedata) |
for (N = 0; N <= (BIDIR_WIDTH - 1) ; N = N+1) |
data_mode_v[N] = (~write_n & (address == N)) ? writedata[1] : data_mode[N]; |
|
always @(posedge clk or negedge reset_n) |
begin |
if (reset_n == 0) |
begin |
data_outz <= 0; |
data_mode <=0; |
end |
else |
begin |
data_outz <= data_outz_v; |
data_mode <= data_mode_v; |
end |
end // always @ (posedge clk or negedge reset_n) |
|
endmodule |
|
/trunk/sopc/gpio_hw.tcl
0,0 → 1,120
# TCL File Generated by Component Editor 9.0 |
# Thu Apr 23 11:35:45 CST 2009 |
# DO NOT MODIFY |
|
|
# +----------------------------------- |
# | |
# | gpio "gpio" v2.0 |
# | Thomas Chou 2009.04.23.11:35:45 |
# | generic gpio |
# | |
# | /home/thomas/new2/gpio/t1proj/gpio.v |
# | |
# | ./gpio.v syn, sim |
# | |
# +----------------------------------- |
|
|
# +----------------------------------- |
# | module gpio |
# | |
set_module_property DESCRIPTION "generic gpio" |
set_module_property NAME gpio |
set_module_property VERSION 2.0 |
set_module_property INTERNAL false |
set_module_property GROUP "Peripherals/Microcontroller Peripherals" |
set_module_property AUTHOR "Thomas Chou" |
set_module_property DISPLAY_NAME gpio |
set_module_property TOP_LEVEL_HDL_FILE hdl/gpio.v |
set_module_property TOP_LEVEL_HDL_MODULE gpio |
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true |
set_module_property EDITABLE true |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | files |
# | |
add_file hdl/gpio.v {SYNTHESIS SIMULATION} |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | parameters |
# | |
add_parameter BIDIR_WIDTH INTEGER 8 |
set_parameter_property BIDIR_WIDTH DISPLAY_NAME BIDIR_WIDTH |
set_parameter_property BIDIR_WIDTH UNITS None |
set_parameter_property BIDIR_WIDTH DISPLAY_HINT "Total IO width" |
set_parameter_property BIDIR_WIDTH AFFECTS_GENERATION true |
set_parameter_property BIDIR_WIDTH IS_HDL_PARAMETER true |
add_parameter INPUT_WIDTH INTEGER 4 |
set_parameter_property INPUT_WIDTH DISPLAY_NAME INPUT_WIDTH |
set_parameter_property INPUT_WIDTH UNITS None |
set_parameter_property INPUT_WIDTH DISPLAY_HINT "Bidir IO width" |
set_parameter_property INPUT_WIDTH AFFECTS_GENERATION true |
set_parameter_property INPUT_WIDTH IS_HDL_PARAMETER true |
add_parameter ADDR_WIDTH INTEGER 4 |
set_parameter_property ADDR_WIDTH DISPLAY_NAME ADDR_WIDTH |
set_parameter_property ADDR_WIDTH UNITS None |
set_parameter_property ADDR_WIDTH DISPLAY_HINT "Address width" |
set_parameter_property ADDR_WIDTH AFFECTS_GENERATION true |
set_parameter_property ADDR_WIDTH IS_HDL_PARAMETER true |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | connection point avalon_slave_0 |
# | |
add_interface avalon_slave_0 avalon end |
set_interface_property avalon_slave_0 addressAlignment NATIVE |
set_interface_property avalon_slave_0 bridgesToMaster "" |
set_interface_property avalon_slave_0 burstOnBurstBoundariesOnly false |
set_interface_property avalon_slave_0 holdTime 0 |
set_interface_property avalon_slave_0 isMemoryDevice false |
set_interface_property avalon_slave_0 isNonVolatileStorage false |
set_interface_property avalon_slave_0 linewrapBursts false |
set_interface_property avalon_slave_0 maximumPendingReadTransactions 0 |
set_interface_property avalon_slave_0 printableDevice false |
set_interface_property avalon_slave_0 readLatency 0 |
set_interface_property avalon_slave_0 readWaitTime 1 |
set_interface_property avalon_slave_0 setupTime 0 |
set_interface_property avalon_slave_0 timingUnits Cycles |
set_interface_property avalon_slave_0 writeWaitTime 0 |
|
set_interface_property avalon_slave_0 ASSOCIATED_CLOCK clock_reset |
set_interface_property avalon_slave_0 ENABLED true |
|
add_interface_port avalon_slave_0 readdata readdata Output 2 |
add_interface_port avalon_slave_0 address address Input -1 |
add_interface_port avalon_slave_0 write_n write_n Input 1 |
add_interface_port avalon_slave_0 writedata writedata Input 2 |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | connection point clock_reset |
# | |
add_interface clock_reset clock end |
set_interface_property clock_reset ptfSchematicName "" |
|
set_interface_property clock_reset ENABLED true |
|
add_interface_port clock_reset clk clk Input 1 |
add_interface_port clock_reset reset_n reset_n Input 1 |
# | |
# +----------------------------------- |
|
# +----------------------------------- |
# | connection point conduit_end |
# | |
add_interface conduit_end conduit end |
|
set_interface_property conduit_end ASSOCIATED_CLOCK clock_reset |
set_interface_property conduit_end ENABLED true |
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add_interface_port conduit_end bidir_port export Bidir -1 |
add_interface_port conduit_end input_port export Input -1 |
# | |
# +----------------------------------- |