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URL https://opencores.org/ocsvn/bustap-jtag/bustap-jtag/trunk

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Rev 2 → Rev 5

/up_monitor.vhd File deleted
/up_monitor.v
1,86 → 1,99
//**************************************************************
// Module : up_monitor.v
// Platform : Windows xp sp2
// Simulator : Modelsim 6.5b
// Synthesizer : QuartusII 10.1 sp1
// Place and Route : QuartusII 10.1 sp1
// Targets device : Cyclone III
// Author : Bibo Yang (ash_riple@hotmail.com)
// Organization : www.opencores.org
// Revision : 2.0
// Date : 2012/03/12
// Description : Top level glue logic to group together
// the JTAG input and output modules.
//**************************************************************
 
module up_monitor (up_clk,up_wbe,up_csn,up_addr,up_data_io);
`timescale 1ns/1ns
 
input up_clk,up_wbe,up_csn;
input [15:2] up_addr;
input [31:0] up_data_io;
module up_monitor (
input clk,
input wr_en,rd_en,
input [15:2] addr_in,
input [31:0] data_in
);
 
reg up_csn_d1, up_csn_d2, up_csn_d3, up_csn_d4;
wire up_csn_neg_pulse;
wire [47:0] up_bus_content;
reg wr_en_d1,rd_en_d1;
reg [15:2] addr_in_d1;
reg [31:0] data_in_d1;
 
wire [49:0] trig_condition;
wire trig_en = trig_condition[49];
wire trig_set = trig_condition[48];
wire [15:0] trig_addr = trig_condition[47:32];
wire [31:0] trig_data = trig_condition[31:0];
reg trig_condition_ok;
wire [31:0] addr_mask0,addr_mask1,addr_mask2,addr_mask3,addr_mask4,addr_mask5,addr_mask6,addr_mask7,
addr_mask8,addr_mask9,addr_mask10,addr_mask11,addr_mask12,addr_mask13,addr_mask14,addr_mask15;
reg addr_mask_ok;
 
wire [31:0] addr_mask0,addr_mask1,addr_mask2,addr_mask3,addr_mask4,addr_mask5,addr_mask6,addr_mask7,
addr_mask8,addr_mask9,addr_mask10,addr_mask11,addr_mask12,addr_mask13,addr_mask14,addr_mask15;
reg addr_mask_ok;
wire [49:0] trig_cond;
wire trig_en = trig_cond[49];
wire trig_set = trig_cond[48];
wire [15:0] trig_addr = trig_cond[47:32];
wire [31:0] trig_data = trig_cond[31:0];
reg trig_cond_ok;
 
always @(posedge up_clk)
wire [47:0] capture_in;
wire capture_wr;
 
// bus input pipeline, allowing back-to-back/continuous bus access
always @(posedge clk)
begin
up_csn_d1 <= up_csn || up_wbe;
up_csn_d2 <= up_csn_d1;
up_csn_d3 <= up_csn_d2;
up_csn_d4 <= up_csn_d3;
wr_en_d1 <= wr_en;
rd_en_d1 <= rd_en;
addr_in_d1 <= addr_in;
data_in_d1 <= data_in;
end
 
always @(posedge up_clk)
// address range based capture enable
always @(posedge clk)
begin
if (( (up_addr[15:2]<=addr_mask0[31:18] && up_addr[15:2]>=addr_mask0[15:2]) ||
(up_addr[15:2]<=addr_mask1[31:18] && up_addr[15:2]>=addr_mask1[15:2]) ||
(up_addr[15:2]<=addr_mask2[31:18] && up_addr[15:2]>=addr_mask2[15:2]) ||
(up_addr[15:2]<=addr_mask3[31:18] && up_addr[15:2]>=addr_mask3[15:2]) ||
(up_addr[15:2]<=addr_mask4[31:18] && up_addr[15:2]>=addr_mask4[15:2]) ||
(up_addr[15:2]<=addr_mask5[31:18] && up_addr[15:2]>=addr_mask5[15:2]) ||
(up_addr[15:2]<=addr_mask6[31:18] && up_addr[15:2]>=addr_mask6[15:2]) ||
(up_addr[15:2]<=addr_mask7[31:18] && up_addr[15:2]>=addr_mask7[15:2])
) //inclusive address set
&&
( (up_addr[15:2]>addr_mask8 [31:18] || up_addr[15:2]<addr_mask8 [15:2]) &&
(up_addr[15:2]>addr_mask9 [31:18] || up_addr[15:2]<addr_mask9 [15:2]) &&
(up_addr[15:2]>addr_mask10[31:18] || up_addr[15:2]<addr_mask10[15:2]) &&
(up_addr[15:2]>addr_mask11[31:18] || up_addr[15:2]<addr_mask11[15:2]) &&
(up_addr[15:2]>addr_mask12[31:18] || up_addr[15:2]<addr_mask12[15:2]) &&
(up_addr[15:2]>addr_mask13[31:18] || up_addr[15:2]<addr_mask13[15:2]) &&
(up_addr[15:2]>addr_mask14[31:18] || up_addr[15:2]<addr_mask14[15:2]) &&
(up_addr[15:2]>addr_mask15[31:18] || up_addr[15:2]<addr_mask15[15:2])
) //exclusive address set
if (((addr_in[15:2]<=addr_mask0[31:18] && addr_in[15:2]>=addr_mask0[15:2]) ||
(addr_in[15:2]<=addr_mask1[31:18] && addr_in[15:2]>=addr_mask1[15:2]) ||
(addr_in[15:2]<=addr_mask2[31:18] && addr_in[15:2]>=addr_mask2[15:2]) ||
(addr_in[15:2]<=addr_mask3[31:18] && addr_in[15:2]>=addr_mask3[15:2]) ||
(addr_in[15:2]<=addr_mask4[31:18] && addr_in[15:2]>=addr_mask4[15:2]) ||
(addr_in[15:2]<=addr_mask5[31:18] && addr_in[15:2]>=addr_mask5[15:2]) ||
(addr_in[15:2]<=addr_mask6[31:18] && addr_in[15:2]>=addr_mask6[15:2]) ||
(addr_in[15:2]<=addr_mask7[31:18] && addr_in[15:2]>=addr_mask7[15:2])
) //inclusive address range set: addr_mask 0 - 7
&&
((addr_in[15:2]>addr_mask8 [31:18] || addr_in[15:2]<addr_mask8 [15:2]) &&
(addr_in[15:2]>addr_mask9 [31:18] || addr_in[15:2]<addr_mask9 [15:2]) &&
(addr_in[15:2]>addr_mask10[31:18] || addr_in[15:2]<addr_mask10[15:2]) &&
(addr_in[15:2]>addr_mask11[31:18] || addr_in[15:2]<addr_mask11[15:2]) &&
(addr_in[15:2]>addr_mask12[31:18] || addr_in[15:2]<addr_mask12[15:2]) &&
(addr_in[15:2]>addr_mask13[31:18] || addr_in[15:2]<addr_mask13[15:2]) &&
(addr_in[15:2]>addr_mask14[31:18] || addr_in[15:2]<addr_mask14[15:2]) &&
(addr_in[15:2]>addr_mask15[31:18] || addr_in[15:2]<addr_mask15[15:2])
) //exclusive address range set: addr_mask 8 - 15
)
addr_mask_ok <= 1;
else
addr_mask_ok <= 0;
addr_mask_ok <= wr_en;
else
addr_mask_ok <= 0;
end
 
always @(posedge up_clk)
// address-data based capture trigger
always @(posedge clk)
begin
if (trig_en==0)
trig_condition_ok <= 1;
else if (trig_set==0)
trig_condition_ok <= 0;
else if (up_csn_d1==0 && up_csn_d2==1)
if (trig_addr[15:2]==up_addr[15:2] && trig_data==up_data_io)
trig_condition_ok <= 1;
if (trig_en==0) // trigger not enabled, trigger gate forced open
trig_cond_ok <= 1;
else if (trig_set==0) // trigger enabled and trigger stopped, trigger gate forced close
trig_cond_ok <= 0;
else // trigger enabled and trigger started, trigger gate conditional open
if (trig_addr[15:2]==addr_in[15:2] && trig_data==data_in)
trig_cond_ok <= wr_en;// trigger gate kept open until trigger stoped
end
 
assign up_csn_neg_pulse = !up_csn_d3 && up_csn_d4 && addr_mask_ok && trig_condition_ok;
assign up_bus_content = {up_addr[15:2],2'b0,up_data_io[31:0]};
// generate capture wr-in
assign capture_in = {addr_in_d1[15:2],2'b0,data_in_d1[31:0]};
assign capture_wr = wr_en_d1 && addr_mask_ok && trig_cond_ok;
 
virtual_jtag_adda_fifo u_virtual_jtag_adda_fifo (
.clk(up_clk),
.wr_en(up_csn_neg_pulse),
.data_in(up_bus_content)
);
defparam
u_virtual_jtag_adda_fifo.data_width = 48,
u_virtual_jtag_adda_fifo.fifo_depth = 512,
u_virtual_jtag_adda_fifo.addr_width = 9,
u_virtual_jtag_adda_fifo.al_full_val = 511,
u_virtual_jtag_adda_fifo.al_empt_val = 0;
 
// instantiate capture mask, as input
virtual_jtag_addr_mask u_virtual_jtag_addr_mask (
.mask_out0(addr_mask0),
.mask_out1(addr_mask1),
104,10 → 117,24
u_virtual_jtag_addr_mask.mask_index = 4,
u_virtual_jtag_addr_mask.mask_num = 16;
 
// instantiate capture trigger, as input
virtual_jtag_adda_trig u_virtual_jtag_adda_trig (
.trig_out(trig_condition)
.trig_out(trig_cond)
);
defparam
u_virtual_jtag_adda_trig.trig_width = 50;
 
// instantiate capture fifo, as output
virtual_jtag_adda_fifo u_virtual_jtag_adda_fifo (
.clk(clk),
.wr_en(capture_wr),
.data_in(capture_in)
);
defparam
u_virtual_jtag_adda_fifo.data_width = 48,
u_virtual_jtag_adda_fifo.fifo_depth = 512,
u_virtual_jtag_adda_fifo.addr_width = 9,
u_virtual_jtag_adda_fifo.al_full_val = 511,
u_virtual_jtag_adda_fifo.al_empt_val = 0;
 
endmodule
/up_monitor_wrapper.v
0,0 → 1,57
//**************************************************************
// Module : up_monitor_wrapper.v
// Platform : Windows xp sp2
// Simulator : Modelsim 6.5b
// Synthesizer : QuartusII 10.1 sp1
// Place and Route : QuartusII 10.1 sp1
// Targets device : Cyclone III
// Author : Bibo Yang (ash_riple@hotmail.com)
// Organization : www.opencores.org
// Revision : 2.0
// Date : 2012/03/12
// Description : Common CPU interface to pipelined access
// interface converter.
//**************************************************************
 
`timescale 1ns/1ns
 
module up_monitor_wrapper (up_clk,up_wbe,up_csn,up_addr,up_data_io);
 
// common CPU bus interface
input up_clk;
input up_wbe,up_csn;
input [15:2] up_addr;
input [31:0] up_data_io;
 
// prepare for generating wr_en pulse
reg up_wr_d1, up_wr_d2, up_wr_d3;
always @(posedge up_clk) begin
up_wr_d1 <= !up_wbe & !up_csn;
up_wr_d2 <= up_wr_d1;
up_wr_d3 <= up_wr_d2;
end
 
// prepare for generating rd_en pulse
reg up_rd_d1, up_rd_d2, up_rd_d3;
always @(posedge up_clk) begin
up_rd_d1 <= up_wbe & !up_csn;
up_rd_d2 <= up_rd_d1;
up_rd_d3 <= up_rd_d2;
end
 
// map to pipelined access interface
wire clk = up_clk;
wire wr_en = up_wr_d2 & !up_wr_d3;
wire rd_en = up_rd_d2 & !up_rd_d3;
wire [15:2] addr_in = up_addr;
wire [31:0] data_in = up_data_io;
 
up_monitor inst (
.clk(clk),
.wr_en(wr_en),
.rd_en(rd_en),
.addr_in(addr_in),
.data_in(data_in)
);
 
endmodule
/altera/virtual_jtag_addr_mask.v
1,9 → 1,26
module virtual_jtag_addr_mask(mask_out0,mask_out1,mask_out2,mask_out3,
mask_out4,mask_out5,mask_out6,mask_out7,
mask_out8,mask_out9,mask_out10,mask_out11,
mask_out12,mask_out13,mask_out14,mask_out15
);
//**************************************************************
// Module : virtual_jtag_addr_mask.v
// Platform : Windows xp sp2
// Simulator : Modelsim 6.5b
// Synthesizer : QuartusII 10.1 sp1
// Place and Route : QuartusII 10.1 sp1
// Targets device : Cyclone III
// Author : Bibo Yang (ash_riple@hotmail.com)
// Organization : www.opencores.org
// Revision : 2.0
// Date : 2012/03/12
// Description : addr mask input from debug host via
// Virtual JTAG.
//**************************************************************
 
`timescale 1ns/1ns
 
module virtual_jtag_addr_mask(mask_out0 ,mask_out1 ,mask_out2 ,mask_out3 ,
mask_out4 ,mask_out5 ,mask_out6 ,mask_out7 ,
mask_out8 ,mask_out9 ,mask_out10,mask_out11,
mask_out12,mask_out13,mask_out14,mask_out15
);
 
parameter addr_width = 32,
mask_index = 4, //2**mask_index=mask_num
mask_num = 16;
/altera/virtual_jtag_adda_fifo.v
1,3 → 1,20
//**************************************************************
// Module : virtual_jtag_adda_fifo.v
// Platform : Windows xp sp2
// Simulator : Modelsim 6.5b
// Synthesizer : QuartusII 10.1 sp1
// Place and Route : QuartusII 10.1 sp1
// Targets device : Cyclone III
// Author : Bibo Yang (ash_riple@hotmail.com)
// Organization : www.opencores.org
// Revision : 2.0
// Date : 2012/03/12
// Description : addr/data capture output to debug host
// via Virtual JTAG.
//**************************************************************
 
`timescale 1ns/1ns
 
module virtual_jtag_adda_fifo(clk,wr_en,data_in);
 
parameter data_width = 32,
/altera/virtual_jtag_adda_trig.v
1,3 → 1,20
//**************************************************************
// Module : virtual_jtag_adda_trig.v
// Platform : Windows xp sp2
// Simulator : Modelsim 6.5b
// Synthesizer : QuartusII 10.1 sp1
// Place and Route : QuartusII 10.1 sp1
// Targets device : Cyclone III
// Author : Bibo Yang (ash_riple@hotmail.com)
// Organization : www.opencores.org
// Revision : 2.0
// Date : 2012/03/12
// Description : addr/data trigger input from debug host
// via Virtual JTAG.
//**************************************************************
 
`timescale 1ns/1ns
 
module virtual_jtag_adda_trig(trig_out);
 
parameter trig_width = 32;

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