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Rev 5 → Rev 6

/up_monitor.v
7,8 → 7,8
// Targets device : Cyclone III
// Author : Bibo Yang (ash_riple@hotmail.com)
// Organization : www.opencores.org
// Revision : 2.0
// Date : 2012/03/12
// Revision : 2.1
// Date : 2012/03/15
// Description : Top level glue logic to group together
// the JTAG input and output modules.
//**************************************************************
22,24 → 22,43
input [31:0] data_in
);
 
reg wr_en_d1,rd_en_d1;
reg [15:2] addr_in_d1;
reg [31:0] data_in_d1;
/////////////////////////////////////////////////
// Registers and wires announcment
/////////////////////////////////////////////////
 
wire [31:0] addr_mask0,addr_mask1,addr_mask2,addr_mask3,addr_mask4,addr_mask5,addr_mask6,addr_mask7,
addr_mask8,addr_mask9,addr_mask10,addr_mask11,addr_mask12,addr_mask13,addr_mask14,addr_mask15;
// for CPU bus signal buffer
reg wr_en_d1,rd_en_d1;
reg [15:2] addr_in_d1;
reg [31:0] data_in_d1;
// for capture address mask
wire [35:0] addr_mask0,addr_mask1,addr_mask2 ,addr_mask3 ,addr_mask4 ,addr_mask5 ,addr_mask6 ,addr_mask7 , // inclusive
addr_mask8,addr_mask9,addr_mask10,addr_mask11,addr_mask12,addr_mask13,addr_mask14,addr_mask15; // exclusive
wire [15:0] addr_mask_en = {addr_mask15[32],addr_mask14[32],addr_mask13[32],addr_mask12[32],
addr_mask11[32],addr_mask10[32],addr_mask9 [32],addr_mask8 [32],
addr_mask7 [32],addr_mask6 [32],addr_mask5 [32],addr_mask4 [32],
addr_mask3 [32],addr_mask2 [32],addr_mask1 [32],addr_mask0 [32]};
wire addr_wren = addr_mask15[35];
wire addr_rden = addr_mask15[34];
reg addr_mask_ok;
 
wire [49:0] trig_cond;
// for capture address+data trigger
wire [55:0] trig_cond;
wire trig_aden = trig_cond[55];
wire trig_daen = trig_cond[54];
wire trig_wren = trig_cond[51];
wire trig_rden = trig_cond[50];
wire trig_en = trig_cond[49];
wire trig_set = trig_cond[48];
wire [15:0] trig_addr = trig_cond[47:32];
wire [31:0] trig_data = trig_cond[31:0];
reg trig_cond_ok;
 
wire [47:0] capture_in;
reg trig_cond_ok,trig_cond_ok_d1;
// for capture storage
wire [49:0] capture_in;
wire capture_wr;
 
/////////////////////////////////////////////////
// Capture logic main
/////////////////////////////////////////////////
 
// bus input pipeline, allowing back-to-back/continuous bus access
always @(posedge clk)
begin
52,49 → 71,77
// address range based capture enable
always @(posedge clk)
begin
if (((addr_in[15:2]<=addr_mask0[31:18] && addr_in[15:2]>=addr_mask0[15:2]) ||
(addr_in[15:2]<=addr_mask1[31:18] && addr_in[15:2]>=addr_mask1[15:2]) ||
(addr_in[15:2]<=addr_mask2[31:18] && addr_in[15:2]>=addr_mask2[15:2]) ||
(addr_in[15:2]<=addr_mask3[31:18] && addr_in[15:2]>=addr_mask3[15:2]) ||
(addr_in[15:2]<=addr_mask4[31:18] && addr_in[15:2]>=addr_mask4[15:2]) ||
(addr_in[15:2]<=addr_mask5[31:18] && addr_in[15:2]>=addr_mask5[15:2]) ||
(addr_in[15:2]<=addr_mask6[31:18] && addr_in[15:2]>=addr_mask6[15:2]) ||
(addr_in[15:2]<=addr_mask7[31:18] && addr_in[15:2]>=addr_mask7[15:2])
) //inclusive address range set: addr_mask 0 - 7
if (((addr_in[15:2]<=addr_mask0[31:18] && addr_in[15:2]>=addr_mask0[15:2] && addr_mask_en[ 0]) ||
(addr_in[15:2]<=addr_mask1[31:18] && addr_in[15:2]>=addr_mask1[15:2] && addr_mask_en[ 1]) ||
(addr_in[15:2]<=addr_mask2[31:18] && addr_in[15:2]>=addr_mask2[15:2] && addr_mask_en[ 2]) ||
(addr_in[15:2]<=addr_mask3[31:18] && addr_in[15:2]>=addr_mask3[15:2] && addr_mask_en[ 3]) ||
(addr_in[15:2]<=addr_mask4[31:18] && addr_in[15:2]>=addr_mask4[15:2] && addr_mask_en[ 4]) ||
(addr_in[15:2]<=addr_mask5[31:18] && addr_in[15:2]>=addr_mask5[15:2] && addr_mask_en[ 5]) ||
(addr_in[15:2]<=addr_mask6[31:18] && addr_in[15:2]>=addr_mask6[15:2] && addr_mask_en[ 6]) ||
(addr_in[15:2]<=addr_mask7[31:18] && addr_in[15:2]>=addr_mask7[15:2] && addr_mask_en[ 7])
) //inclusive address range set with individual enable: addr_mask 0 - 7
&&
((addr_in[15:2]>addr_mask8 [31:18] || addr_in[15:2]<addr_mask8 [15:2]) &&
(addr_in[15:2]>addr_mask9 [31:18] || addr_in[15:2]<addr_mask9 [15:2]) &&
(addr_in[15:2]>addr_mask10[31:18] || addr_in[15:2]<addr_mask10[15:2]) &&
(addr_in[15:2]>addr_mask11[31:18] || addr_in[15:2]<addr_mask11[15:2]) &&
(addr_in[15:2]>addr_mask12[31:18] || addr_in[15:2]<addr_mask12[15:2]) &&
(addr_in[15:2]>addr_mask13[31:18] || addr_in[15:2]<addr_mask13[15:2]) &&
(addr_in[15:2]>addr_mask14[31:18] || addr_in[15:2]<addr_mask14[15:2]) &&
(addr_in[15:2]>addr_mask15[31:18] || addr_in[15:2]<addr_mask15[15:2])
) //exclusive address range set: addr_mask 8 - 15
((addr_in[15:2]>addr_mask8 [31:18] || addr_in[15:2]<addr_mask8 [15:2] || !addr_mask_en[ 8]) &&
(addr_in[15:2]>addr_mask9 [31:18] || addr_in[15:2]<addr_mask9 [15:2] || !addr_mask_en[ 9]) &&
(addr_in[15:2]>addr_mask10[31:18] || addr_in[15:2]<addr_mask10[15:2] || !addr_mask_en[10]) &&
(addr_in[15:2]>addr_mask11[31:18] || addr_in[15:2]<addr_mask11[15:2] || !addr_mask_en[11]) &&
(addr_in[15:2]>addr_mask12[31:18] || addr_in[15:2]<addr_mask12[15:2] || !addr_mask_en[12]) &&
(addr_in[15:2]>addr_mask13[31:18] || addr_in[15:2]<addr_mask13[15:2] || !addr_mask_en[13]) &&
(addr_in[15:2]>addr_mask14[31:18] || addr_in[15:2]<addr_mask14[15:2] || !addr_mask_en[14]) &&
(addr_in[15:2]>addr_mask15[31:18] || addr_in[15:2]<addr_mask15[15:2] || !addr_mask_en[15])
) //exclusive address range set with individual enable: addr_mask 8 - 15
)
addr_mask_ok <= wr_en;
addr_mask_ok <= (addr_rden && rd_en) || (addr_wren && wr_en);
else
addr_mask_ok <= 0;
end
 
// address-data based capture trigger
// address+data based capture trigger
always @(posedge clk)
begin
if (trig_en==0) // trigger not enabled, trigger gate forced open
trig_cond_ok <= 1;
else if (trig_set==0) // trigger enabled and trigger stopped, trigger gate forced close
trig_cond_ok <= 0;
else // trigger enabled and trigger started, trigger gate conditional open
if (trig_addr[15:2]==addr_in[15:2] && trig_data==data_in)
trig_cond_ok <= wr_en;// trigger gate kept open until trigger stoped
if (trig_en==0) begin // trigger not enabled, trigger gate forced open
trig_cond_ok <= 1;
trig_cond_ok_d1 <= 1;
end
else if (trig_set==0) begin // trigger enabled and trigger stopped, trigger gate forced close
trig_cond_ok <= 0;
trig_cond_ok_d1 <= 0;
end
else begin // trigger enabled and trigger started, trigger gate conditional open
if ((trig_aden? trig_addr[15:2]==addr_in[15:2]: 1) && (trig_daen? trig_data==data_in: 1) &&
(trig_wren? wr_en : 1) && (trig_rden? rd_en : 1) &&
(rd_en || wr_en))
trig_cond_ok <= 1;
trig_cond_ok_d1 <= trig_cond_ok;
end
// trigger gate kept open until trigger stoped
end
wire trig_cond_ok_pulse = trig_cond_ok & !trig_cond_ok_d1;
 
// generate capture wr-in
assign capture_in = {addr_in_d1[15:2],2'b0,data_in_d1[31:0]};
assign capture_wr = wr_en_d1 && addr_mask_ok && trig_cond_ok;
assign capture_in = {trig_cond_ok_pulse,wr_en_d1,addr_in_d1[15:2],2'b00,data_in_d1[31:0]};
assign capture_wr = trig_cond_ok_pulse | (addr_mask_ok & trig_cond_ok);
 
// instantiate capture mask, as input
/////////////////////////////////////////////////
// Instantiate vendor specific JTAG functions
/////////////////////////////////////////////////
 
// index 0, instantiate capture fifo, as output
virtual_jtag_adda_fifo u_virtual_jtag_adda_fifo (
.clk(clk),
.wr_en(capture_wr),
.data_in(capture_in)
);
defparam
u_virtual_jtag_adda_fifo.data_width = 50,
u_virtual_jtag_adda_fifo.fifo_depth = 512,
u_virtual_jtag_adda_fifo.addr_width = 9,
u_virtual_jtag_adda_fifo.al_full_val = 511,
u_virtual_jtag_adda_fifo.al_empt_val = 0;
 
// index 1, instantiate capture mask, as input
virtual_jtag_addr_mask u_virtual_jtag_addr_mask (
// inclusive
.mask_out0(addr_mask0),
.mask_out1(addr_mask1),
.mask_out2(addr_mask2),
103,6 → 150,7
.mask_out5(addr_mask5),
.mask_out6(addr_mask6),
.mask_out7(addr_mask7),
// exclusive
.mask_out8(addr_mask8),
.mask_out9(addr_mask9),
.mask_out10(addr_mask10),
113,28 → 161,15
.mask_out15(addr_mask15)
);
defparam
u_virtual_jtag_addr_mask.addr_width = 32,
u_virtual_jtag_addr_mask.mask_index = 4,
u_virtual_jtag_addr_mask.mask_num = 16;
u_virtual_jtag_addr_mask.mask_enabl = 4,
u_virtual_jtag_addr_mask.addr_width = 32;
 
// instantiate capture trigger, as input
// index 2, instantiate capture trigger, as input
virtual_jtag_adda_trig u_virtual_jtag_adda_trig (
.trig_out(trig_cond)
);
defparam
u_virtual_jtag_adda_trig.trig_width = 50;
u_virtual_jtag_adda_trig.trig_width = 56;
 
// instantiate capture fifo, as output
virtual_jtag_adda_fifo u_virtual_jtag_adda_fifo (
.clk(clk),
.wr_en(capture_wr),
.data_in(capture_in)
);
defparam
u_virtual_jtag_adda_fifo.data_width = 48,
u_virtual_jtag_adda_fifo.fifo_depth = 512,
u_virtual_jtag_adda_fifo.addr_width = 9,
u_virtual_jtag_adda_fifo.al_full_val = 511,
u_virtual_jtag_adda_fifo.al_empt_val = 0;
 
endmodule
/up_monitor_wrapper.v
7,10 → 7,11
// Targets device : Cyclone III
// Author : Bibo Yang (ash_riple@hotmail.com)
// Organization : www.opencores.org
// Revision : 2.0
// Date : 2012/03/12
// Revision : 2.1
// Date : 2012/03/15
// Description : Common CPU interface to pipelined access
// interface converter.
// @Note: Implementation dependent.
//**************************************************************
 
`timescale 1ns/1ns
19,32 → 20,50
 
// common CPU bus interface
input up_clk;
input up_wbe,up_csn;
input up_wbe,up_csn; // negative logic
input [15:2] up_addr;
input [31:0] up_data_io;
 
// prepare for generating wr_en pulse
reg up_wr_d1, up_wr_d2, up_wr_d3;
// filter out glitches on the line with extra 4 clocks
reg up_wbe_d1, up_wbe_d2, up_wbe_d3, up_wbe_d4;
reg up_csn_d1, up_csn_d2, up_csn_d3, up_csn_d4;
always @(posedge up_clk) begin
up_wr_d1 <= !up_wbe & !up_csn;
up_wr_d2 <= up_wr_d1;
up_wr_d3 <= up_wr_d2;
up_wbe_d1 <= up_wbe;
up_wbe_d2 <= up_wbe_d1;
up_wbe_d3 <= up_wbe_d2;
up_wbe_d4 <= up_wbe_d3;
up_csn_d1 <= up_csn;
up_csn_d2 <= up_csn_d1;
up_csn_d3 <= up_csn_d2;
up_csn_d4 <= up_csn_d3;
end
 
// prepare for generating rd_en pulse
reg up_rd_d1, up_rd_d2, up_rd_d3;
reg wr_en_filtered, wr_en_filtered_d1;
always @(posedge up_clk) begin
up_rd_d1 <= up_wbe & !up_csn;
up_rd_d2 <= up_rd_d1;
up_rd_d3 <= up_rd_d2;
// negative logic changed to positive logic, with filter
wr_en_filtered <= (!up_wbe_d2 & !up_wbe_d3 & !up_wbe_d4) & (!up_csn_d2 & !up_csn_d3 & !up_csn_d4);
wr_en_filtered_d1 <= wr_en_filtered;
end
reg rd_en_filtered, rd_en_filtered_d1;
always @(posedge up_clk) begin
// negative logic changed to positive logic, with filter
rd_en_filtered <= (up_wbe_d2 & up_wbe_d3 & up_wbe_d4) & (!up_csn_d2 & !up_csn_d3 & !up_csn_d4);
rd_en_filtered_d1 <= rd_en_filtered;
end
 
// latch the data at rising edge of up_csn(negative logic)
reg [15:2] up_addr_latch;
reg [31:0] up_data_latch;
always @(posedge up_csn) begin
up_addr_latch <= up_addr;
up_data_latch <= up_data_io;
end
 
// map to pipelined access interface
wire clk = up_clk;
wire wr_en = up_wr_d2 & !up_wr_d3;
wire rd_en = up_rd_d2 & !up_rd_d3;
wire [15:2] addr_in = up_addr;
wire [31:0] data_in = up_data_io;
wire wr_en = !wr_en_filtered & wr_en_filtered_d1; // falling edge of write_enable(positive logic)
wire rd_en = !rd_en_filtered & rd_en_filtered_d1; // falling edge of read_enable(positive logic)
wire [15:2] addr_in = up_addr_latch;
wire [31:0] data_in = up_data_latch;
 
up_monitor inst (
.clk(clk),
/altera/virtual_jtag_addr_mask.v
7,8 → 7,8
// Targets device : Cyclone III
// Author : Bibo Yang (ash_riple@hotmail.com)
// Organization : www.opencores.org
// Revision : 2.0
// Date : 2012/03/12
// Revision : 2.1
// Date : 2012/03/15
// Description : addr mask input from debug host via
// Virtual JTAG.
//**************************************************************
21,54 → 21,54
mask_out12,mask_out13,mask_out14,mask_out15
);
 
parameter addr_width = 32,
mask_index = 4, //2**mask_index=mask_num
mask_num = 16;
parameter mask_index = 4, //2**mask_index=mask_num
mask_enabl = 4,
addr_width = 32;
 
output [addr_width-1:0] mask_out0;
output [addr_width-1:0] mask_out1;
output [addr_width-1:0] mask_out2;
output [addr_width-1:0] mask_out3;
output [addr_width-1:0] mask_out4;
output [addr_width-1:0] mask_out5;
output [addr_width-1:0] mask_out6;
output [addr_width-1:0] mask_out7;
output [addr_width-1:0] mask_out8;
output [addr_width-1:0] mask_out9;
output [addr_width-1:0] mask_out10;
output [addr_width-1:0] mask_out11;
output [addr_width-1:0] mask_out12;
output [addr_width-1:0] mask_out13;
output [addr_width-1:0] mask_out14;
output [addr_width-1:0] mask_out15;
output [mask_enabl+addr_width-1:0] mask_out0;
output [mask_enabl+addr_width-1:0] mask_out1;
output [mask_enabl+addr_width-1:0] mask_out2;
output [mask_enabl+addr_width-1:0] mask_out3;
output [mask_enabl+addr_width-1:0] mask_out4;
output [mask_enabl+addr_width-1:0] mask_out5;
output [mask_enabl+addr_width-1:0] mask_out6;
output [mask_enabl+addr_width-1:0] mask_out7;
output [mask_enabl+addr_width-1:0] mask_out8;
output [mask_enabl+addr_width-1:0] mask_out9;
output [mask_enabl+addr_width-1:0] mask_out10;
output [mask_enabl+addr_width-1:0] mask_out11;
output [mask_enabl+addr_width-1:0] mask_out12;
output [mask_enabl+addr_width-1:0] mask_out13;
output [mask_enabl+addr_width-1:0] mask_out14;
output [mask_enabl+addr_width-1:0] mask_out15;
 
reg [addr_width-1:0] mask_out0;
reg [addr_width-1:0] mask_out1;
reg [addr_width-1:0] mask_out2;
reg [addr_width-1:0] mask_out3;
reg [addr_width-1:0] mask_out4;
reg [addr_width-1:0] mask_out5;
reg [addr_width-1:0] mask_out6;
reg [addr_width-1:0] mask_out7;
reg [addr_width-1:0] mask_out8;
reg [addr_width-1:0] mask_out9;
reg [addr_width-1:0] mask_out10;
reg [addr_width-1:0] mask_out11;
reg [addr_width-1:0] mask_out12;
reg [addr_width-1:0] mask_out13;
reg [addr_width-1:0] mask_out14;
reg [addr_width-1:0] mask_out15;
reg [mask_enabl+addr_width-1:0] mask_out0;
reg [mask_enabl+addr_width-1:0] mask_out1;
reg [mask_enabl+addr_width-1:0] mask_out2;
reg [mask_enabl+addr_width-1:0] mask_out3;
reg [mask_enabl+addr_width-1:0] mask_out4;
reg [mask_enabl+addr_width-1:0] mask_out5;
reg [mask_enabl+addr_width-1:0] mask_out6;
reg [mask_enabl+addr_width-1:0] mask_out7;
reg [mask_enabl+addr_width-1:0] mask_out8;
reg [mask_enabl+addr_width-1:0] mask_out9;
reg [mask_enabl+addr_width-1:0] mask_out10;
reg [mask_enabl+addr_width-1:0] mask_out11;
reg [mask_enabl+addr_width-1:0] mask_out12;
reg [mask_enabl+addr_width-1:0] mask_out13;
reg [mask_enabl+addr_width-1:0] mask_out14;
reg [mask_enabl+addr_width-1:0] mask_out15;
 
wire tdi, tck, cdr, cir, e1dr, e2dr, pdr, sdr, udr, uir;
reg tdo;
reg [mask_index+addr_width-1:0] mask_instr_reg;
reg [mask_index+mask_enabl+addr_width-1:0] mask_instr_reg;
reg bypass_reg;
 
wire [1:0] ir_in;
wire mask_instr = ~ir_in[1] & ir_in[0]; // 1
 
wire [mask_index-1:0] mask_id = mask_instr_reg[(mask_index+addr_width-1):addr_width];
wire [addr_width-1:0] mask_is = mask_instr_reg[(addr_width-1):0];
wire [mask_index-1 :0] mask_id = mask_instr_reg[(mask_index+mask_enabl+addr_width-1):(mask_enabl+addr_width)];
wire [mask_enabl+addr_width-1:0] mask_is = mask_instr_reg[ (mask_enabl+addr_width-1):0];
 
always @(posedge tck)
begin
114,7 → 114,7
if ( mask_instr && cdr )
mask_instr_reg <= mask_instr_reg;
else if ( mask_instr && sdr )
mask_instr_reg <= {tdi, mask_instr_reg[mask_index+addr_width-1:1]};
mask_instr_reg <= {tdi, mask_instr_reg[mask_index+mask_enabl+addr_width-1:1]};
 
/* Bypass register */
always @ (posedge tck)
/altera/virtual_jtag_adda_fifo.v
7,8 → 7,8
// Targets device : Cyclone III
// Author : Bibo Yang (ash_riple@hotmail.com)
// Organization : www.opencores.org
// Revision : 2.0
// Date : 2012/03/12
// Revision : 2.1
// Date : 2012/03/15
// Description : addr/data capture output to debug host
// via Virtual JTAG.
//**************************************************************
/altera/virtual_jtag_adda_trig.v
7,8 → 7,8
// Targets device : Cyclone III
// Author : Bibo Yang (ash_riple@hotmail.com)
// Organization : www.opencores.org
// Revision : 2.0
// Date : 2012/03/12
// Revision : 2.1
// Date : 2012/03/15
// Description : addr/data trigger input from debug host
// via Virtual JTAG.
//**************************************************************

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