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Rev 15 → Rev 16

/tags/v2p2/rtl/up_monitor.v
0,0 → 1,219
//**************************************************************
// Module : up_monitor.v
// Platform : Windows xp sp2
// Simulator : Modelsim 6.5b
// Synthesizer : QuartusII 10.1 sp1
// Place and Route : QuartusII 10.1 sp1
// Targets device : Cyclone III
// Author : Bibo Yang (ash_riple@hotmail.com)
// Organization : www.opencores.org
// Revision : 2.2
// Date : 2012/03/28
// Description : Top level glue logic to group together
// the JTAG input and output modules.
//**************************************************************
 
`timescale 1ns/1ns
 
module up_monitor (
input clk,
input wr_en,rd_en,
input [15:2] addr_in,
input [31:0] data_in
);
 
/////////////////////////////////////////////////
// Registers and wires announcment
/////////////////////////////////////////////////
 
// for CPU bus signal buffer
reg wr_en_d1,rd_en_d1;
reg [15:2] addr_in_d1;
reg [31:0] data_in_d1;
// for capture address mask
wire [35:0] addr_mask0,addr_mask1,addr_mask2 ,addr_mask3 ,addr_mask4 ,addr_mask5 ,addr_mask6 ,addr_mask7 , // inclusive
addr_mask8,addr_mask9,addr_mask10,addr_mask11,addr_mask12,addr_mask13,addr_mask14,addr_mask15; // exclusive
wire [15:0] addr_mask_en = {addr_mask15[32],addr_mask14[32],addr_mask13[32],addr_mask12[32],
addr_mask11[32],addr_mask10[32],addr_mask9 [32],addr_mask8 [32],
addr_mask7 [32],addr_mask6 [32],addr_mask5 [32],addr_mask4 [32],
addr_mask3 [32],addr_mask2 [32],addr_mask1 [32],addr_mask0 [32]};
wire addr_wren = addr_mask15[35];
wire addr_rden = addr_mask15[34];
reg addr_mask_ok;
// for capture address+data trigger
wire [55:0] trig_cond;
wire trig_aden = trig_cond[55];
wire trig_daen = trig_cond[54];
wire trig_wren = trig_cond[51];
wire trig_rden = trig_cond[50];
wire trig_en = trig_cond[49];
wire trig_set = trig_cond[48];
wire [15:0] trig_addr = trig_cond[47:32];
wire [31:0] trig_data = trig_cond[31:0];
reg trig_cond_ok,trig_cond_ok_d1;
// for capture storage
wire [81:0] capture_in;
wire capture_wr;
// for pretrigger capture
wire [9:0] pretrig_num;
reg [9:0] pretrig_cnt;
wire pretrig_full;
wire pretrig_wr;
reg pretrig_wr_d1,pretrig_rd;
// for inter capture timer
reg [31:0] inter_cap_cnt;
 
/////////////////////////////////////////////////
// Capture logic main
/////////////////////////////////////////////////
 
// bus input pipeline, allowing back-to-back/continuous bus access
always @(posedge clk)
begin
wr_en_d1 <= wr_en;
rd_en_d1 <= rd_en;
addr_in_d1 <= addr_in;
data_in_d1 <= data_in;
end
 
// address range based capture enable
always @(posedge clk)
begin
if (((addr_in[15:2]<=addr_mask0[31:18] && addr_in[15:2]>=addr_mask0[15:2] && addr_mask_en[ 0]) ||
(addr_in[15:2]<=addr_mask1[31:18] && addr_in[15:2]>=addr_mask1[15:2] && addr_mask_en[ 1]) ||
(addr_in[15:2]<=addr_mask2[31:18] && addr_in[15:2]>=addr_mask2[15:2] && addr_mask_en[ 2]) ||
(addr_in[15:2]<=addr_mask3[31:18] && addr_in[15:2]>=addr_mask3[15:2] && addr_mask_en[ 3]) ||
(addr_in[15:2]<=addr_mask4[31:18] && addr_in[15:2]>=addr_mask4[15:2] && addr_mask_en[ 4]) ||
(addr_in[15:2]<=addr_mask5[31:18] && addr_in[15:2]>=addr_mask5[15:2] && addr_mask_en[ 5]) ||
(addr_in[15:2]<=addr_mask6[31:18] && addr_in[15:2]>=addr_mask6[15:2] && addr_mask_en[ 6]) ||
(addr_in[15:2]<=addr_mask7[31:18] && addr_in[15:2]>=addr_mask7[15:2] && addr_mask_en[ 7])
) //inclusive address range set with individual enable: addr_mask 0 - 7
&&
((addr_in[15:2]>addr_mask8 [31:18] || addr_in[15:2]<addr_mask8 [15:2] || !addr_mask_en[ 8]) &&
(addr_in[15:2]>addr_mask9 [31:18] || addr_in[15:2]<addr_mask9 [15:2] || !addr_mask_en[ 9]) &&
(addr_in[15:2]>addr_mask10[31:18] || addr_in[15:2]<addr_mask10[15:2] || !addr_mask_en[10]) &&
(addr_in[15:2]>addr_mask11[31:18] || addr_in[15:2]<addr_mask11[15:2] || !addr_mask_en[11]) &&
(addr_in[15:2]>addr_mask12[31:18] || addr_in[15:2]<addr_mask12[15:2] || !addr_mask_en[12]) &&
(addr_in[15:2]>addr_mask13[31:18] || addr_in[15:2]<addr_mask13[15:2] || !addr_mask_en[13]) &&
(addr_in[15:2]>addr_mask14[31:18] || addr_in[15:2]<addr_mask14[15:2] || !addr_mask_en[14]) &&
(addr_in[15:2]>addr_mask15[31:18] || addr_in[15:2]<addr_mask15[15:2] || !addr_mask_en[15])
) //exclusive address range set with individual enable: addr_mask 8 - 15
)
addr_mask_ok <= (addr_rden && rd_en) || (addr_wren && wr_en);
else
addr_mask_ok <= 0;
end
 
// address+data based capture trigger
always @(posedge clk)
begin
if (trig_en==0) begin // trigger not enabled, trigger gate forced open
trig_cond_ok <= 1;
trig_cond_ok_d1 <= 1;
end
else if (trig_set==0) begin // trigger enabled and trigger stopped, trigger gate forced close
trig_cond_ok <= 0;
trig_cond_ok_d1 <= 0;
end
else begin // trigger enabled and trigger started, trigger gate conditional open
if ((trig_aden? trig_addr[15:2]==addr_in[15:2]: 1) && (trig_daen? trig_data==data_in: 1) &&
(trig_wren? wr_en : 1) && (trig_rden? rd_en : 1) &&
(rd_en || wr_en))
trig_cond_ok <= 1;
trig_cond_ok_d1 <= trig_cond_ok;
end
// trigger gate kept open until trigger stoped
end
wire trig_cond_ok_pulse = trig_cond_ok & !trig_cond_ok_d1;
 
// generate capture wr_in
assign capture_in = {trig_cond_ok_pulse,wr_en_d1,inter_cap_cnt,addr_in_d1[15:2],2'b00,data_in_d1[31:0]};
assign capture_wr = trig_cond_ok_pulse || (addr_mask_ok && trig_cond_ok);
 
// generate pre-trigger wr_in
assign pretrig_full = (pretrig_cnt >= pretrig_num) || trig_cond_ok;
assign pretrig_wr = (!trig_en || (trig_en && !trig_set))? 1'b0 : (trig_cond_ok? 1'b0 : addr_mask_ok);
always @(posedge clk)
begin
if (!trig_en || (trig_en && !trig_set)) begin
pretrig_cnt <= 10'd0;
pretrig_wr_d1<= 1'b0;
pretrig_rd <= 1'b0;
end
else if (!pretrig_full) begin
pretrig_cnt <= pretrig_cnt + addr_mask_ok;
pretrig_wr_d1<= 1'b0;
pretrig_rd <= 1'b0;
end
else if (pretrig_full) begin
pretrig_cnt <= pretrig_cnt;
pretrig_wr_d1<= pretrig_wr;
pretrig_rd <= pretrig_wr_d1;
end
end
 
// generate interval counter
always @(posedge clk)
begin
if (capture_wr || pretrig_wr)
inter_cap_cnt <= 32'd0;
else if (inter_cap_cnt[31])
inter_cap_cnt <= 32'd3000000000;
else
inter_cap_cnt <= inter_cap_cnt + 32'd1;
end
 
/////////////////////////////////////////////////
// Instantiate vendor specific JTAG functions
/////////////////////////////////////////////////
 
// index 0, instantiate capture fifo, as output
virtual_jtag_adda_fifo u_virtual_jtag_adda_fifo (
.clk(clk),
.wr_in(capture_wr || pretrig_wr),
.data_in(capture_in),
.rd_in(pretrig_rd)
);
defparam
u_virtual_jtag_adda_fifo.data_width = 82,
u_virtual_jtag_adda_fifo.fifo_depth = 512,
u_virtual_jtag_adda_fifo.addr_width = 9,
u_virtual_jtag_adda_fifo.al_full_val = 511,
u_virtual_jtag_adda_fifo.al_empt_val = 0;
 
// index 1, instantiate capture mask, as input
virtual_jtag_addr_mask u_virtual_jtag_addr_mask (
// inclusive
.mask_out0(addr_mask0),
.mask_out1(addr_mask1),
.mask_out2(addr_mask2),
.mask_out3(addr_mask3),
.mask_out4(addr_mask4),
.mask_out5(addr_mask5),
.mask_out6(addr_mask6),
.mask_out7(addr_mask7),
// exclusive
.mask_out8(addr_mask8),
.mask_out9(addr_mask9),
.mask_out10(addr_mask10),
.mask_out11(addr_mask11),
.mask_out12(addr_mask12),
.mask_out13(addr_mask13),
.mask_out14(addr_mask14),
.mask_out15(addr_mask15)
);
defparam
u_virtual_jtag_addr_mask.mask_index = 4,
u_virtual_jtag_addr_mask.mask_enabl = 4,
u_virtual_jtag_addr_mask.addr_width = 32;
 
// index 2, instantiate capture trigger, as input
virtual_jtag_adda_trig u_virtual_jtag_adda_trig (
.trig_out(trig_cond),
.pnum_out(pretrig_num)
);
defparam
u_virtual_jtag_adda_trig.trig_width = 56,
u_virtual_jtag_adda_trig.pnum_width = 10;
 
endmodule
/tags/v2p2/rtl/up_monitor_wrapper.v
0,0 → 1,76
//**************************************************************
// Module : up_monitor_wrapper.v
// Platform : Windows xp sp2
// Simulator : Modelsim 6.5b
// Synthesizer : QuartusII 10.1 sp1
// Place and Route : QuartusII 10.1 sp1
// Targets device : Cyclone III
// Author : Bibo Yang (ash_riple@hotmail.com)
// Organization : www.opencores.org
// Revision : 2.2
// Date : 2012/03/28
// Description : Common CPU interface to pipelined access
// interface converter.
// @Note: Implementation dependent.
//**************************************************************
 
`timescale 1ns/1ns
 
module up_monitor_wrapper (up_clk,up_wbe,up_csn,up_addr,up_data_io);
 
// common CPU bus interface
input up_clk;
input up_wbe,up_csn; // negative logic
input [15:2] up_addr;
input [31:0] up_data_io;
 
// filter out glitches on the line with extra 4 clocks
reg up_wbe_d1, up_wbe_d2, up_wbe_d3, up_wbe_d4;
reg up_csn_d1, up_csn_d2, up_csn_d3, up_csn_d4;
always @(posedge up_clk) begin
up_wbe_d1 <= up_wbe;
up_wbe_d2 <= up_wbe_d1;
up_wbe_d3 <= up_wbe_d2;
up_wbe_d4 <= up_wbe_d3;
up_csn_d1 <= up_csn;
up_csn_d2 <= up_csn_d1;
up_csn_d3 <= up_csn_d2;
up_csn_d4 <= up_csn_d3;
end
reg wr_en_filtered, wr_en_filtered_d1;
always @(posedge up_clk) begin
// negative logic changed to positive logic, with filter
wr_en_filtered <= (!up_wbe_d2 & !up_wbe_d3 & !up_wbe_d4) & (!up_csn_d2 & !up_csn_d3 & !up_csn_d4);
wr_en_filtered_d1 <= wr_en_filtered;
end
reg rd_en_filtered, rd_en_filtered_d1;
always @(posedge up_clk) begin
// negative logic changed to positive logic, with filter
rd_en_filtered <= (up_wbe_d2 & up_wbe_d3 & up_wbe_d4) & (!up_csn_d2 & !up_csn_d3 & !up_csn_d4);
rd_en_filtered_d1 <= rd_en_filtered;
end
 
// latch the data at rising edge of up_csn(negative logic)
reg [15:2] up_addr_latch;
reg [31:0] up_data_latch;
always @(posedge up_csn) begin
up_addr_latch <= up_addr;
up_data_latch <= up_data_io;
end
 
// map to pipelined access interface
wire clk = up_clk;
wire wr_en = !wr_en_filtered & wr_en_filtered_d1; // falling edge of write_enable(positive logic)
wire rd_en = !rd_en_filtered & rd_en_filtered_d1; // falling edge of read_enable(positive logic)
wire [15:2] addr_in = up_addr_latch;
wire [31:0] data_in = up_data_latch;
 
up_monitor inst (
.clk(clk),
.wr_en(wr_en),
.rd_en(rd_en),
.addr_in(addr_in),
.data_in(data_in)
);
 
endmodule
/tags/v2p2/rtl/altera/virtual_jtag_addr_mask.v
0,0 → 1,178
//**************************************************************
// Module : virtual_jtag_addr_mask.v
// Platform : Windows xp sp2
// Simulator : Modelsim 6.5b
// Synthesizer : QuartusII 10.1 sp1
// Place and Route : QuartusII 10.1 sp1
// Targets device : Cyclone III
// Author : Bibo Yang (ash_riple@hotmail.com)
// Organization : www.opencores.org
// Revision : 2.2
// Date : 2012/03/28
// Description : addr mask input from debug host via
// Virtual JTAG.
//**************************************************************
 
`include "jtag_sim_define.h"
`timescale 1ns/1ns
 
module virtual_jtag_addr_mask(mask_out0 ,mask_out1 ,mask_out2 ,mask_out3 ,
mask_out4 ,mask_out5 ,mask_out6 ,mask_out7 ,
mask_out8 ,mask_out9 ,mask_out10,mask_out11,
mask_out12,mask_out13,mask_out14,mask_out15
);
 
parameter mask_index = 4, //2**mask_index=mask_num
mask_enabl = 4,
addr_width = 32;
 
output [mask_enabl+addr_width-1:0] mask_out0;
output [mask_enabl+addr_width-1:0] mask_out1;
output [mask_enabl+addr_width-1:0] mask_out2;
output [mask_enabl+addr_width-1:0] mask_out3;
output [mask_enabl+addr_width-1:0] mask_out4;
output [mask_enabl+addr_width-1:0] mask_out5;
output [mask_enabl+addr_width-1:0] mask_out6;
output [mask_enabl+addr_width-1:0] mask_out7;
output [mask_enabl+addr_width-1:0] mask_out8;
output [mask_enabl+addr_width-1:0] mask_out9;
output [mask_enabl+addr_width-1:0] mask_out10;
output [mask_enabl+addr_width-1:0] mask_out11;
output [mask_enabl+addr_width-1:0] mask_out12;
output [mask_enabl+addr_width-1:0] mask_out13;
output [mask_enabl+addr_width-1:0] mask_out14;
output [mask_enabl+addr_width-1:0] mask_out15;
 
reg [mask_enabl+addr_width-1:0] mask_out0;
reg [mask_enabl+addr_width-1:0] mask_out1;
reg [mask_enabl+addr_width-1:0] mask_out2;
reg [mask_enabl+addr_width-1:0] mask_out3;
reg [mask_enabl+addr_width-1:0] mask_out4;
reg [mask_enabl+addr_width-1:0] mask_out5;
reg [mask_enabl+addr_width-1:0] mask_out6;
reg [mask_enabl+addr_width-1:0] mask_out7;
reg [mask_enabl+addr_width-1:0] mask_out8;
reg [mask_enabl+addr_width-1:0] mask_out9;
reg [mask_enabl+addr_width-1:0] mask_out10;
reg [mask_enabl+addr_width-1:0] mask_out11;
reg [mask_enabl+addr_width-1:0] mask_out12;
reg [mask_enabl+addr_width-1:0] mask_out13;
reg [mask_enabl+addr_width-1:0] mask_out14;
reg [mask_enabl+addr_width-1:0] mask_out15;
 
wire tdi, tck, cdr, cir, e1dr, e2dr, pdr, sdr, udr, uir;
reg tdo;
reg [mask_index+mask_enabl+addr_width-1:0] mask_instr_reg;
reg bypass_reg;
 
wire [1:0] ir_in;
wire mask_instr = ~ir_in[1] & ir_in[0]; // 1
 
wire [mask_index-1 :0] mask_id = mask_instr_reg[(mask_index+mask_enabl+addr_width-1):(mask_enabl+addr_width)];
wire [mask_enabl+addr_width-1:0] mask_is = mask_instr_reg[ (mask_enabl+addr_width-1):0];
 
always @(posedge tck)
begin
if (mask_instr && e1dr)
case (mask_id)
4'd0 :
mask_out0 <= mask_is;
4'd1 :
mask_out1 <= mask_is;
4'd2 :
mask_out2 <= mask_is;
4'd3 :
mask_out3 <= mask_is;
4'd4 :
mask_out4 <= mask_is;
4'd5 :
mask_out5 <= mask_is;
4'd6 :
mask_out6 <= mask_is;
4'd7 :
mask_out7 <= mask_is;
4'd8 :
mask_out8 <= mask_is;
4'd9 :
mask_out9 <= mask_is;
4'd10 :
mask_out10 <= mask_is;
4'd11 :
mask_out11 <= mask_is;
4'd12 :
mask_out12 <= mask_is;
4'd13 :
mask_out13 <= mask_is;
4'd14 :
mask_out14 <= mask_is;
4'd15 :
mask_out15 <= mask_is;
endcase
end
 
/* mask_instr Instruction Handler */
always @ (posedge tck)
if ( mask_instr && cdr )
mask_instr_reg <= mask_instr_reg;
else if ( mask_instr && sdr )
mask_instr_reg <= {tdi, mask_instr_reg[mask_index+mask_enabl+addr_width-1:1]};
 
/* Bypass register */
always @ (posedge tck)
bypass_reg = tdi;
 
/* Node TDO Output */
always @ ( mask_instr, mask_instr_reg, bypass_reg )
begin
if (mask_instr)
tdo <= mask_instr_reg[0];
else
tdo <= bypass_reg;// Used to maintain the continuity of the scan chain.
end
 
sld_virtual_jtag sld_virtual_jtag_component (
.ir_in (ir_in),
.ir_out (2'b0),
.tdo (tdo),
.tdi (tdi),
.tms (),
.tck (tck),
.virtual_state_cir (cir),
.virtual_state_pdr (pdr),
.virtual_state_uir (uir),
.virtual_state_sdr (sdr),
.virtual_state_cdr (cdr),
.virtual_state_udr (udr),
.virtual_state_e1dr (e1dr),
.virtual_state_e2dr (e2dr),
.jtag_state_rti (),
.jtag_state_e1dr (),
.jtag_state_e2dr (),
.jtag_state_pir (),
.jtag_state_tlr (),
.jtag_state_sir (),
.jtag_state_cir (),
.jtag_state_uir (),
.jtag_state_pdr (),
.jtag_state_sdrs (),
.jtag_state_sdr (),
.jtag_state_cdr (),
.jtag_state_udr (),
.jtag_state_sirs (),
.jtag_state_e1ir (),
.jtag_state_e2ir ());
defparam
sld_virtual_jtag_component.sld_auto_instance_index = "NO",
sld_virtual_jtag_component.sld_instance_index = 1,
sld_virtual_jtag_component.sld_ir_width = 2,
`ifdef USE_SIM_STIMULUS
sld_virtual_jtag_component.sld_sim_action = `ADDR_SLD_SIM_ACTION,
sld_virtual_jtag_component.sld_sim_n_scan = `ADDR_SLD_SIM_N_SCAN,
sld_virtual_jtag_component.sld_sim_total_length = `ADDR_SLD_SIM_T_LENG;
`else
sld_virtual_jtag_component.sld_sim_action = "((1,1,1,2))",
sld_virtual_jtag_component.sld_sim_n_scan = 1,
sld_virtual_jtag_component.sld_sim_total_length = 2;
`endif
endmodule
/tags/v2p2/rtl/altera/virtual_jtag_adda_fifo.v
0,0 → 1,180
//**************************************************************
// Module : virtual_jtag_adda_fifo.v
// Platform : Windows xp sp2
// Simulator : Modelsim 6.5b
// Synthesizer : QuartusII 10.1 sp1
// Place and Route : QuartusII 10.1 sp1
// Targets device : Cyclone III
// Author : Bibo Yang (ash_riple@hotmail.com)
// Organization : www.opencores.org
// Revision : 2.2
// Date : 2012/03/28
// Description : addr/data capture output to debug host
// via Virtual JTAG.
//**************************************************************
 
`include "jtag_sim_define.h"
`timescale 1ns/1ns
 
module virtual_jtag_adda_fifo(clk,wr_in,data_in,rd_in);
 
parameter data_width = 32,
fifo_depth = 256,
addr_width = 8,
al_full_val = 255,
al_empt_val = 0;
 
input clk;
input wr_in, rd_in;
input [data_width-1:0] data_in;
 
wire tdi, tck, cdr, cir, e1dr, e2dr, pdr, sdr, udr, uir;
reg tdo;
reg [addr_width-1:0] usedw_instr_reg;
reg reset_instr_reg;
reg [data_width-1:0] read_instr_reg;
reg bypass_reg;
 
wire [1:0] ir_in;
wire usedw_instr = ~ir_in[1] & ir_in[0]; // 1
wire reset_instr = ir_in[1] & ~ir_in[0]; // 2
wire read_instr = ir_in[1] & ir_in[0]; // 3
 
wire reset = reset_instr && e1dr;
 
wire [addr_width-1:0] usedw;
wire [data_width-1:0] data_out;
wire full;
wire al_full;
 
reg read_instr_d1;
reg read_instr_d2;
reg read_instr_d3;
wire rd_en = rd_in | (read_instr_d2 & !read_instr_d3);
wire wr_en = wr_in;
always @(posedge clk or posedge reset)
begin
if (reset)
begin
read_instr_d1 <= 1'b0;
read_instr_d2 <= 1'b0;
read_instr_d3 <= 1'b0;
end
else
begin
read_instr_d1 <= read_instr;
read_instr_d2 <= read_instr_d1;
read_instr_d3 <= read_instr_d2;
end
end
 
scfifo jtag_fifo (
.aclr (reset),
.clock (clk),
.wrreq (wr_en & !al_full),
.data (data_in),
.rdreq (rd_en),
.q (data_out),
.full (full),
.almost_full (al_full),
.empty (),
.almost_empty (),
.usedw (usedw),
.sclr ());
defparam
jtag_fifo.lpm_width = data_width,
jtag_fifo.lpm_numwords = fifo_depth,
jtag_fifo.lpm_widthu = addr_width,
jtag_fifo.intended_device_family = "Cyclone III",
jtag_fifo.almost_full_value = al_full_val,
jtag_fifo.almost_empty_value = al_empt_val,
jtag_fifo.lpm_type = "scfifo",
jtag_fifo.lpm_showahead = "OFF",
jtag_fifo.overflow_checking = "ON",
jtag_fifo.underflow_checking = "ON",
jtag_fifo.use_eab = "ON",
jtag_fifo.add_ram_output_register = "ON";
 
/* usedw_instr Instruction Handler */
always @ (posedge tck)
if ( usedw_instr && cdr )
usedw_instr_reg <= usedw;
else if ( usedw_instr && sdr )
usedw_instr_reg <= {tdi, usedw_instr_reg[addr_width-1:1]};
 
/* reset_instr Instruction Handler */
always @ (posedge tck)
if ( reset_instr && sdr )
reset_instr_reg <= tdi;//{tdi, reset_instr_reg[data_width-1:1]};
 
/* read_instr Instruction Handler */
always @ (posedge tck)
if ( read_instr && cdr )
read_instr_reg <= data_out;
else if ( read_instr && sdr )
read_instr_reg <= {tdi, read_instr_reg[data_width-1:1]};
 
/* Bypass register */
always @ (posedge tck)
bypass_reg = tdi;
 
/* Node TDO Output */
always @ ( usedw_instr, reset_instr, read_instr, usedw_instr_reg[0], reset_instr_reg/*[0]*/, read_instr_reg[0], bypass_reg )
begin
if (usedw_instr)
tdo <= usedw_instr_reg[0];
else if (reset_instr)
tdo <= reset_instr_reg/*[0]*/;
else if (read_instr)
tdo <= read_instr_reg[0];
else
tdo <= bypass_reg; // Used to maintain the continuity of the scan chain.
end
 
sld_virtual_jtag sld_virtual_jtag_component (
.ir_in (ir_in),
.ir_out (2'b0),
.tdo (tdo),
.tdi (tdi),
.tms (),
.tck (tck),
.virtual_state_cir (cir),
.virtual_state_pdr (pdr),
.virtual_state_uir (uir),
.virtual_state_sdr (sdr),
.virtual_state_cdr (cdr),
.virtual_state_udr (udr),
.virtual_state_e1dr (e1dr),
.virtual_state_e2dr (e2dr),
.jtag_state_rti (),
.jtag_state_e1dr (),
.jtag_state_e2dr (),
.jtag_state_pir (),
.jtag_state_tlr (),
.jtag_state_sir (),
.jtag_state_cir (),
.jtag_state_uir (),
.jtag_state_pdr (),
.jtag_state_sdrs (),
.jtag_state_sdr (),
.jtag_state_cdr (),
.jtag_state_udr (),
.jtag_state_sirs (),
.jtag_state_e1ir (),
.jtag_state_e2ir ());
defparam
sld_virtual_jtag_component.sld_auto_instance_index = "NO",
sld_virtual_jtag_component.sld_instance_index = 0,
sld_virtual_jtag_component.sld_ir_width = 2,
`ifdef USE_SIM_STIMULUS
sld_virtual_jtag_component.sld_sim_action = `FIFO_SLD_SIM_ACTION,
sld_virtual_jtag_component.sld_sim_n_scan = `FIFO_SLD_SIM_N_SCAN,
sld_virtual_jtag_component.sld_sim_total_length = `FIFO_SLD_SIM_T_LENG;
`else
sld_virtual_jtag_component.sld_sim_action = "((1,1,1,2))",
sld_virtual_jtag_component.sld_sim_n_scan = 1,
sld_virtual_jtag_component.sld_sim_total_length = 2;
`endif
endmodule
/tags/v2p2/rtl/altera/virtual_jtag_adda_trig.v
0,0 → 1,126
//**************************************************************
// Module : virtual_jtag_adda_trig.v
// Platform : Windows xp sp2
// Simulator : Modelsim 6.5b
// Synthesizer : QuartusII 10.1 sp1
// Place and Route : QuartusII 10.1 sp1
// Targets device : Cyclone III
// Author : Bibo Yang (ash_riple@hotmail.com)
// Organization : www.opencores.org
// Revision : 2.2
// Date : 2012/03/28
// Description : addr/data trigger input from debug host
// via Virtual JTAG.
//**************************************************************
 
`include "jtag_sim_define.h"
`timescale 1ns/1ns
 
module virtual_jtag_adda_trig(trig_out, pnum_out);
 
parameter trig_width = 32;
parameter pnum_width = 10;
 
output [trig_width-1:0] trig_out;
output [pnum_width-1:0] pnum_out;
 
reg [trig_width-1:0] trig_out;
reg [pnum_width-1:0] pnum_out;
 
wire tdi, tck, cdr, cir, e1dr, e2dr, pdr, sdr, udr, uir;
reg tdo;
reg [trig_width-1:0] trig_instr_reg;
reg [pnum_width-1:0] pnum_instr_reg;
reg bypass_reg;
 
wire [1:0] ir_in;
wire trig_instr = ~ir_in[1] & ir_in[0]; // 1
wire pnum_instr = ir_in[1] & ~ir_in[0]; // 2
 
always @(posedge tck)
begin
if (trig_instr && e1dr)
trig_out <= trig_instr_reg;
end
 
always @(posedge tck)
begin
if (pnum_instr && e1dr)
pnum_out <= pnum_instr_reg;
end
 
/* trig_instr Instruction Handler */
always @ (posedge tck)
if ( trig_instr && cdr )
trig_instr_reg <= trig_instr_reg;
else if ( trig_instr && sdr )
trig_instr_reg <= {tdi, trig_instr_reg[trig_width-1:1]};
 
/* pnum_instr Instruction Handler */
always @ (posedge tck)
if ( pnum_instr && cdr )
pnum_instr_reg <= pnum_instr_reg;
else if ( pnum_instr && sdr )
pnum_instr_reg <= {tdi, pnum_instr_reg[pnum_width-1:1]};
 
/* Bypass register */
always @ (posedge tck)
bypass_reg <= tdi;
 
/* Node TDO Output */
always @ ( trig_instr, trig_instr_reg, pnum_instr, pnum_instr_reg, bypass_reg )
begin
if (trig_instr)
tdo <= trig_instr_reg[0];
else if (pnum_instr)
tdo <= pnum_instr_reg[0];
else
tdo <= bypass_reg;// Used to maintain the continuity of the scan chain.
end
 
sld_virtual_jtag sld_virtual_jtag_component (
.ir_in (ir_in),
.ir_out (2'b0),
.tdo (tdo),
.tdi (tdi),
.tms (),
.tck (tck),
.virtual_state_cir (cir),
.virtual_state_pdr (pdr),
.virtual_state_uir (uir),
.virtual_state_sdr (sdr),
.virtual_state_cdr (cdr),
.virtual_state_udr (udr),
.virtual_state_e1dr (e1dr),
.virtual_state_e2dr (e2dr),
.jtag_state_rti (),
.jtag_state_e1dr (),
.jtag_state_e2dr (),
.jtag_state_pir (),
.jtag_state_tlr (),
.jtag_state_sir (),
.jtag_state_cir (),
.jtag_state_uir (),
.jtag_state_pdr (),
.jtag_state_sdrs (),
.jtag_state_sdr (),
.jtag_state_cdr (),
.jtag_state_udr (),
.jtag_state_sirs (),
.jtag_state_e1ir (),
.jtag_state_e2ir ());
defparam
sld_virtual_jtag_component.sld_auto_instance_index = "NO",
sld_virtual_jtag_component.sld_instance_index = 2,
sld_virtual_jtag_component.sld_ir_width = 2,
`ifdef USE_SIM_STIMULUS
sld_virtual_jtag_component.sld_sim_action = `TRIG_SLD_SIM_ACTION,
sld_virtual_jtag_component.sld_sim_n_scan = `TRIG_SLD_SIM_N_SCAN,
sld_virtual_jtag_component.sld_sim_total_length = `TRIG_SLD_SIM_T_LENG;
`else
sld_virtual_jtag_component.sld_sim_action = "((1,1,1,2))",
sld_virtual_jtag_component.sld_sim_n_scan = 1,
sld_virtual_jtag_component.sld_sim_total_length = 2;
`endif
endmodule
/tags/v2p2/rtl/altera/jtag_sim_define.h
0,0 → 1,16
`define USE_SIM_STIMULUS
 
`define FIFO_SLD_SIM_ACTION "((1,1,1,2))"
`define FIFO_SLD_SIM_N_SCAN 1
`define FIFO_SLD_SIM_T_LENG 2
 
`define ADDR_SLD_SIM_ACTION "((1,1,1,2))"
`define ADDR_SLD_SIM_N_SCAN 1
`define ADDR_SLD_SIM_T_LENG 2
 
`define TRIG_SLD_SIM_ACTION "((1,1,1,2))"
`define TRIG_SLD_SIM_N_SCAN 1
`define TRIG_SLD_SIM_T_LENG 2
 
 
 
/tags/v2p2/cmd/altera/virtual_jtag_console.tcl
0,0 → 1,444
##**************************************************************
## Module : virtual_jtag_console.tcl
## Platform : Windows xp sp2
## Author : Bibo Yang (ash_riple@hotmail.com)
## Organization : www.opencores.org
## Revision : 2.2
## Date : 2012/03/28
## Description : Tcl/Tk GUI for the up_monitor
##**************************************************************
 
proc reset_fifo {{jtag_index_0 0}} {
device_lock -timeout 5
device_virtual_ir_shift -instance_index $jtag_index_0 -ir_value 2 -no_captured_ir_value
device_virtual_dr_shift -instance_index $jtag_index_0 -length 32 -dr_value 00000000 -value_in_hex -no_captured_dr_value
device_unlock
return 0
}
 
proc query_usedw {{jtag_index_0 0}} {
global fifoUsedw
device_lock -timeout 5
device_virtual_ir_shift -instance_index $jtag_index_0 -ir_value 1 -no_captured_ir_value
set usedw [device_virtual_dr_shift -instance_index $jtag_index_0 -length 9 -value_in_hex]
device_unlock
set tmp 0x
append tmp $usedw
set usedw [format "%i" $tmp]
set fifoUsedw $usedw
return $usedw
}
 
proc read_fifo {{jtag_index_0 0}} {
device_lock -timeout 5
device_virtual_ir_shift -instance_index $jtag_index_0 -ir_value 1 -no_captured_ir_value
device_virtual_ir_shift -instance_index $jtag_index_0 -ir_value 3 -no_captured_ir_value
set fifo_data [device_virtual_dr_shift -instance_index $jtag_index_0 -length 82 -value_in_hex]
device_unlock
return $fifo_data
}
 
proc config_addr {{jtag_index_1 1} {mask 0100000000} {mask_id 1}} {
global log
set mask_leng [string length $mask]
if {$mask_leng!=10} {
$log insert end "\nError: Wrong address mask length @$mask_id: [expr $mask_leng-2]. Expects: 8.\n"
 
} else {
device_lock -timeout 5
device_virtual_ir_shift -instance_index $jtag_index_1 -ir_value 1 -no_captured_ir_value
set addr_mask [device_virtual_dr_shift -instance_index $jtag_index_1 -dr_value $mask -length 40 -value_in_hex]
device_unlock
return $addr_mask
}
}
 
proc config_trig {{jtag_index_2 2} {trig 00000000000000} {pnum 000}} {
global log
set trig_leng [string length $trig]
if {$trig_leng!=14} {
$log insert end "\nError: Wrong trigger condition length: [expr $trig_leng-2]. Expects: 4+8.\n"
} else {
device_lock -timeout 5
device_virtual_ir_shift -instance_index $jtag_index_2 -ir_value 1 -no_captured_ir_value
set addr_trig [device_virtual_dr_shift -instance_index $jtag_index_2 -dr_value $trig -length 56 -value_in_hex]
device_unlock
}
if {[format "%d" 0x$pnum]>=511} {
$log insert end "\nError: Wrong trigger pre-capture value: [format "%d" 0x$pnum]. Expects: 0~510.\n"
} else {
device_lock -timeout 5
device_virtual_ir_shift -instance_index $jtag_index_2 -ir_value 2 -no_captured_ir_value
set pnum_trig [device_virtual_dr_shift -instance_index $jtag_index_2 -dr_value $pnum -length 10 -value_in_hex]
device_unlock
}
return $addr_trig
}
 
proc open_jtag_device {{test_cable "USB-Blaster [USB-0]"} {test_device "@2: EP2SGX90 (0x020E30DD)"}} {
open_device -hardware_name $test_cable -device_name $test_device
# Retrieve device id code.
device_lock -timeout 5
device_ir_shift -ir_value 6 -no_captured_ir_value
set idcode "0x[device_dr_shift -length 32 -value_in_hex]"
device_unlock
return $idcode
}
 
proc close_jtag_device {} {
close_device
}
 
proc scan_chain {} {
global log
$log insert end "JTAG Chain Scanning report:\n"
$log insert end "****************************************\n"
set blaster_cables [get_hardware_names]
set cable_num 0
foreach blaster_cable $blaster_cables {
incr cable_num
$log insert end "@$cable_num: $blaster_cable\n"
}
$log insert end "\n****************************************\n"
global device_list
set device_list ""
foreach blaster_cable $blaster_cables {
$log insert end "$blaster_cable:\n"
lappend device_list $blaster_cable
if [catch {get_device_names -hardware_name $blaster_cable} error_msg] {
$log insert end $error_msg
lappend device_list $error_msg
} else {
foreach test_device [get_device_names -hardware_name $blaster_cable] {
$log insert end "$test_device\n"
}
lappend device_list [get_device_names -hardware_name $blaster_cable]
}
}
}
 
proc select_device {{cableNum 1} {deviceNum 1}} {
global log
global device_list
$log insert end "\n****************************************\n"
set test_cable [lindex $device_list [expr 2*$cableNum-2]]
$log insert end "Selected Cable : $test_cable\n"
set test_device [lindex [lindex $device_list [expr 2*$cableNum-1]] [expr $deviceNum-1]]
$log insert end "Selected Device: $test_device\n"
set jtagIdCode [open_jtag_device $test_cable $test_device]
$log insert end "Device ID code : $jtagIdCode\n"
reset_fifo 0
query_usedw 0
}
 
proc updateAddrConfig {} {
global address_span1
global address_span2
global address_span3
global address_span4
global address_span5
global address_span6
global address_span7
global address_span8
global address_span9
global address_span10
global address_span11
global address_span12
global address_span13
global address_span14
global address_span15
global address_span16
global address_span_en1
global address_span_en2
global address_span_en3
global address_span_en4
global address_span_en5
global address_span_en6
global address_span_en7
global address_span_en8
global address_span_en9
global address_span_en10
global address_span_en11
global address_span_en12
global address_span_en13
global address_span_en14
global address_span_en15
global address_span_en16
global addr_wren
global addr_rden
for {set i 1} {$i<=16} {incr i} {
set mask [format "%1X" [expr $i-1]]
append mask [format "%1X" [expr $addr_wren*8+$addr_rden*4+[set address_span_en$i]]]
append mask [set address_span$i]
config_addr 1 $mask $i
}
}
 
proc initAddrConfig {} {
global log
global address_span1
global address_span2
global address_span3
global address_span4
global address_span5
global address_span6
global address_span7
global address_span8
global address_span9
global address_span10
global address_span11
global address_span12
global address_span13
global address_span14
global address_span15
global address_span16
for {set i 1} {$i<=8} {incr i} {
if {[set address_span$i]==""} {
set address_span$i ffff0000
}
}
for {set i 9} {$i<=16} {incr i} {
if {[set address_span$i]==""} {
set address_span$i 00000000
}
}
}
 
proc initTrigConfig {} {
global triggerAddr
global triggerData
global triggerPnum
if {[set triggerAddr]==""} {
set triggerAddr ffff
}
if {[set triggerData]==""} {
set triggerData a5a5a5a5
}
if {[set triggerPnum]==""} {
set triggerPnum 0
}
}
 
proc updateTrigger {{trigCmd 0}} {
global triggerAddr
global triggerData
global triggerPnum
global trig_wren
global trig_rden
global trig_aden
global trig_daen
set triggerValue [format "%1X" [expr $trig_aden*8+$trig_daen*4+0]]
append triggerValue [format "%1X" [expr $trig_wren*8+$trig_rden*4+$trigCmd]]
append triggerValue $triggerAddr
append triggerValue $triggerData
config_trig 2 $triggerValue [format "%03X" $triggerPnum]
}
 
proc startTrigger {} {
global trig_wren
global trig_rden
global trig_aden
global trig_daen
set trigEnable [expr $trig_wren+$trig_rden+$trig_aden+$trig_daen]
if {$trigEnable>0} {
updateTrigger 2
reset_fifo 0
query_usedw 0
updateTrigger 3
} else {
updateTrigger 0
}
}
 
proc reset_fifo_ptr {} {
reset_fifo 0
query_usedw 0
}
 
proc query_fifo_usedw {} {
query_usedw 0
}
 
proc read_fifo_content {} {
global log
global fifoUsedw
$log insert end "\n****************************************\n"
for {set i 0} {$i<$fifoUsedw} {incr i} {
set fifoContent [read_fifo 0]
set ok_trig [expr [format "%d" 0x[string index $fifoContent 0]]/2]
set wr_cptr [expr [format "%d" 0x[string index $fifoContent 0]]%2]
set tm_cptr [format "%d" 0x[string range $fifoContent 1 8]]
set ad_cptr [string range $fifoContent 9 12]
set da_cptr [string range $fifoContent 13 20]
if $ok_trig {
$log insert end "@@@@@@@@@@@@@@@@@@@@\n"
}
if $wr_cptr {
$log insert end "wr $ad_cptr $da_cptr @$tm_cptr\n"
} else {
$log insert end "rd $ad_cptr $da_cptr @$tm_cptr\n"
}
}
query_usedw 0
}
 
proc clear_log {} {
global log
$log delete insert end
}
 
proc quit {} {
global exit_console
destroy .console
set exit_console 1
}
 
# set the QuartusII special Tk command
init_tk
set exit_console 0
 
# set the main window
toplevel .console
wm title .console "www.OpenCores.org: uP Transaction Monitor"
pack propagate .console true
 
# set the www.OpenCores.org logo
frame .console.fig -bg white
pack .console.fig -expand true -fill both
image create photo logo -format gif -file "../common/OpenCores.gif"
label .console.fig.logo -image logo -bg white
pack .console.fig.logo
 
# set the JTAG utility
frame .console.jtag -relief groove -borderwidth 5
pack .console.jtag
button .console.jtag.scan -text {Scan JTAG Chain} -command {scan_chain}
button .console.jtag.select -text {Select JTAG Device :} -command {select_device $cableNum $deviceNum}
button .console.jtag.deselect -text {DeSelect JTAG Device} -command {close_jtag_device}
label .console.jtag.cable -text {Cable @}
label .console.jtag.devic -text {Device @}
entry .console.jtag.cable_num -textvariable cableNum -width 5
entry .console.jtag.devic_num -textvariable deviceNum -width 5
pack .console.jtag.scan .console.jtag.select \
.console.jtag.cable .console.jtag.cable_num \
.console.jtag.devic .console.jtag.devic_num \
.console.jtag.deselect \
-side left -ipadx 0
 
# set the inclusive address entries
frame .console.f1 -relief groove -borderwidth 5
pack .console.f1
label .console.f1.incl_addr -text {Inclusive Addr:}
entry .console.f1.address_span1 -textvariable address_span1 -width 8
entry .console.f1.address_span2 -textvariable address_span2 -width 8
entry .console.f1.address_span3 -textvariable address_span3 -width 8
entry .console.f1.address_span4 -textvariable address_span4 -width 8
entry .console.f1.address_span5 -textvariable address_span5 -width 8
entry .console.f1.address_span6 -textvariable address_span6 -width 8
entry .console.f1.address_span7 -textvariable address_span7 -width 8
entry .console.f1.address_span8 -textvariable address_span8 -width 8
checkbutton .console.f1.address_span_en1 -variable address_span_en1
checkbutton .console.f1.address_span_en2 -variable address_span_en2
checkbutton .console.f1.address_span_en3 -variable address_span_en3
checkbutton .console.f1.address_span_en4 -variable address_span_en4
checkbutton .console.f1.address_span_en5 -variable address_span_en5
checkbutton .console.f1.address_span_en6 -variable address_span_en6
checkbutton .console.f1.address_span_en7 -variable address_span_en7
checkbutton .console.f1.address_span_en8 -variable address_span_en8
pack .console.f1.incl_addr \
.console.f1.address_span_en1 .console.f1.address_span1 \
.console.f1.address_span_en2 .console.f1.address_span2 \
.console.f1.address_span_en3 .console.f1.address_span3 \
.console.f1.address_span_en4 .console.f1.address_span4 \
.console.f1.address_span_en5 .console.f1.address_span5 \
.console.f1.address_span_en6 .console.f1.address_span6 \
.console.f1.address_span_en7 .console.f1.address_span7 \
.console.f1.address_span_en8 .console.f1.address_span8 \
-side left -ipadx 0
 
# set the exclusive address entries
frame .console.f2 -relief groove -borderwidth 5
pack .console.f2
label .console.f2.excl_addr -text {Exclusive Addr:}
entry .console.f2.address_span9 -textvariable address_span9 -width 8
entry .console.f2.address_span10 -textvariable address_span10 -width 8
entry .console.f2.address_span11 -textvariable address_span11 -width 8
entry .console.f2.address_span12 -textvariable address_span12 -width 8
entry .console.f2.address_span13 -textvariable address_span13 -width 8
entry .console.f2.address_span14 -textvariable address_span14 -width 8
entry .console.f2.address_span15 -textvariable address_span15 -width 8
entry .console.f2.address_span16 -textvariable address_span16 -width 8
checkbutton .console.f2.address_span_en9 -variable address_span_en9
checkbutton .console.f2.address_span_en10 -variable address_span_en10
checkbutton .console.f2.address_span_en11 -variable address_span_en11
checkbutton .console.f2.address_span_en12 -variable address_span_en12
checkbutton .console.f2.address_span_en13 -variable address_span_en13
checkbutton .console.f2.address_span_en14 -variable address_span_en14
checkbutton .console.f2.address_span_en15 -variable address_span_en15
checkbutton .console.f2.address_span_en16 -variable address_span_en16
pack .console.f2.excl_addr \
.console.f2.address_span_en9 .console.f2.address_span9 \
.console.f2.address_span_en10 .console.f2.address_span10 \
.console.f2.address_span_en11 .console.f2.address_span11 \
.console.f2.address_span_en12 .console.f2.address_span12 \
.console.f2.address_span_en13 .console.f2.address_span13 \
.console.f2.address_span_en14 .console.f2.address_span14 \
.console.f2.address_span_en15 .console.f2.address_span15 \
.console.f2.address_span_en16 .console.f2.address_span16 \
-side left -ipadx 0
initAddrConfig
 
# set the address configuration buttons
frame .console.addr_cnfg -relief groove -borderwidth 5
pack .console.addr_cnfg
checkbutton .console.addr_cnfg.wren -text {WR} -variable addr_wren
checkbutton .console.addr_cnfg.rden -text {RD} -variable addr_rden
button .console.addr_cnfg.config -text {Apply Address Filter} -command {updateAddrConfig}
pack .console.addr_cnfg.wren .console.addr_cnfg.rden .console.addr_cnfg.config \
-side left -ipadx 0
 
# set the transaction trigger controls
frame .console.trig -relief groove -borderwidth 5
pack .console.trig
button .console.trig.starttrig -text {Apply Trigger Condition} -command {startTrigger}
entry .console.trig.trigvalue_addr -textvar triggerAddr -width 4
entry .console.trig.trigvalue_data -textvar triggerData -width 8
checkbutton .console.trig.trigaddr -text {@Addr:} -variable trig_aden
checkbutton .console.trig.trigdata -text {@Data:} -variable trig_daen
checkbutton .console.trig.wren -text {@WR} -variable trig_wren
checkbutton .console.trig.rden -text {@RD} -variable trig_rden
label .console.trig.pnum -text {Pre-Capture:}
entry .console.trig.trigvalue_pnum -textvar triggerPnum -width 4
pack .console.trig.pnum .console.trig.trigvalue_pnum \
.console.trig.wren .console.trig.rden \
.console.trig.trigaddr .console.trig.trigvalue_addr \
.console.trig.trigdata .console.trig.trigvalue_data \
.console.trig.starttrig \
-side left -ipadx 0
initTrigConfig
 
# set the control buttons
frame .console.fifo -relief groove -borderwidth 5
pack .console.fifo
button .console.fifo.reset -text {Reset FIFO} -command {reset_fifo_ptr}
button .console.fifo.loop -text {Query Used Word} -command {query_fifo_usedw}
label .console.fifo.usedw -textvariable fifoUsedw -relief sunken -width 4
button .console.fifo.read -text {Read FIFO} -command {read_fifo_content}
button .console.fifo.clear -text {Clear Log} -command {clear_log}
button .console.fifo.quit -text {Quit} -command {quit}
pack .console.fifo.reset .console.fifo.loop .console.fifo.usedw .console.fifo.read .console.fifo.clear .console.fifo.quit \
-side left -ipadx 0
 
# set the log window
frame .console.log -relief groove -borderwidth 5
set log [text .console.log.text -width 80 -height 25 \
-borderwidth 2 -relief sunken -setgrid true \
-yscrollcommand {.console.log.scroll set}]
scrollbar .console.log.scroll -command {.console.log.text yview}
pack .console.log.scroll -side right -fill y
pack .console.log.text -side left -fill both -expand true
pack .console.log -side top -fill both -expand true
 
# make the program wait for exit signal
vwait exit_console
 
/tags/v2p2/cmd/altera/virtual_jtag_console.bat
0,0 → 1,2
quartus_stp -t virtual_jtag_console.tcl
pause
/tags/v2p2/cmd/common/OpenCores.gif Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/tags/v2p2/cmd/common/OpenCores.gif
tags/v2p2/cmd/common/OpenCores.gif Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/v2p2/sim/up_monitor_tb.v =================================================================== --- tags/v2p2/sim/up_monitor_tb.v (nonexistent) +++ tags/v2p2/sim/up_monitor_tb.v (revision 16) @@ -0,0 +1,70 @@ +//************************************************************** +// Module : up_monitor_tb.v +// Platform : Windows xp sp2 +// Simulator : Modelsim 6.5b +// Synthesizer : +// Place and Route : +// Targets device : +// Author : Bibo Yang (ash_riple@hotmail.com) +// Organization : www.opencores.org +// Revision : 2.2 +// Date : 2012/03/28 +// Description : up_monitor testbench at both pin level +// and transaction level +//************************************************************** + +`timescale 1ns/1ns + +module up_monitor_tb (); + +reg cpu_start; +reg up_clk; +wire up_wbe, up_csn; +wire [15:2] up_addr; +wire [31:0] up_data_io; +initial begin + up_clk = 1'b0; + forever #5 up_clk = !up_clk; +end + +// pin level DUT +up_monitor_wrapper MON_LO ( + .up_clk(up_clk), + .up_wbe(), // negative logic + .up_csn(), // negative logic + .up_addr(), + .up_data_io() +); + +up_bfm_sv CPU ( + .up_clk(up_clk), + .up_wbe(up_wbe), // negative logic + .up_csn(up_csn), // negative logic + .up_addr(up_addr), + .up_data_io(up_data_io) +); + +reg_bfm_sv REG ( + .up_clk(up_clk), + .up_wbe(up_wbe), // negative logic + .up_csn(up_csn), // negative logic + .up_addr({up_addr,2'b00}), + .up_data_io(up_data_io) +); + +jtag_bfm_sv JTAG ( +); + +assign MON_LO.up_wbe = up_wbe; +assign MON_LO.up_csn = up_csn; +assign MON_LO.up_addr = up_addr; +assign MON_LO.up_data_io = up_data_io; + +initial begin + up_monitor_tb.CPU.up_start = 0; + @(posedge up_monitor_tb.JTAG.jtag_sim_done); + up_monitor_tb.CPU.up_start = 1; + #100000000 $stop; +end + +endmodule Index: tags/v2p2/sim/altera/virtual_jtag_stimulus.tcl =================================================================== --- tags/v2p2/sim/altera/virtual_jtag_stimulus.tcl (nonexistent) +++ tags/v2p2/sim/altera/virtual_jtag_stimulus.tcl (revision 16) @@ -0,0 +1,576 @@ +##************************************************************** +## Module : virtual_jtag_console.tcl +## Platform : Windows xp sp2 +## Author : Bibo Yang (ash_riple@hotmail.com) +## Organization : www.opencores.org +## Revision : 2.2 +## Date : 2012/03/28 +## Description : Tcl/Tk GUI for the simulation stimulus +##************************************************************** + +proc reset_fifo {{jtag_index_0 0}} { + #device_lock -timeout 5 + #device_virtual_ir_shift -instance_index $jtag_index_0 -ir_value 2 -no_captured_ir_value + #device_virtual_dr_shift -instance_index $jtag_index_0 -length 32 -dr_value 00000000 -value_in_hex -no_captured_dr_value + #device_unlock + global sim_started + if {$sim_started==0} { + global fifo_sim_act + global fifo_sim_num + global fifo_sim_len + append fifo_sim_act (0,1,2,[format "%X" 2]), + set fifo_sim_num [expr $fifo_sim_num+1] + set fifo_sim_len [expr $fifo_sim_len+2] + append fifo_sim_act (0,2,0,[format "%X" 32]), + set fifo_sim_num [expr $fifo_sim_num+1] + set fifo_sim_len [expr $fifo_sim_len+32] + } else { + force -freeze /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/reset 1 -cancel 10ns + run 20ns + } + return 0 +} + +proc query_usedw {{jtag_index_0 0}} { + #global fifoUsedw + #device_lock -timeout 5 + #device_virtual_ir_shift -instance_index $jtag_index_0 -ir_value 1 -no_captured_ir_value + #set usedw [device_virtual_dr_shift -instance_index $jtag_index_0 -length 9 -value_in_hex] + #device_unlock + # set tmp 0x + # append tmp $usedw + # set usedw [format "%i" $tmp] + #set fifoUsedw $usedw + global sim_started + if {$sim_started==0} { + global fifo_sim_act + global fifo_sim_num + global fifo_sim_len + append fifo_sim_act (0,1,1,[format "%X" 2]), + set fifo_sim_num [expr $fifo_sim_num+1] + set fifo_sim_len [expr $fifo_sim_len+2] + append fifo_sim_act (0,2,0,[format "%X" 9]), + set fifo_sim_num [expr $fifo_sim_num+1] + set fifo_sim_len [expr $fifo_sim_len+9] + } else { + global fifoUsedw + set usedw [format "%i" 0x[examine /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/usedw]] + set fifoUsedw $usedw + } + return 0 +} + +proc read_fifo {{jtag_index_0 0}} { + #device_lock -timeout 5 + #device_virtual_ir_shift -instance_index $jtag_index_0 -ir_value 1 -no_captured_ir_value + #device_virtual_ir_shift -instance_index $jtag_index_0 -ir_value 3 -no_captured_ir_value + #set fifo_data [device_virtual_dr_shift -instance_index $jtag_index_0 -length 82 -value_in_hex] + #device_unlock + global sim_started + if {$sim_started==0} { + global fifo_sim_act + global fifo_sim_num + global fifo_sim_len + append fifo_sim_act (0,1,1,[format "%X" 2]), + set fifo_sim_num [expr $fifo_sim_num+1] + set fifo_sim_len [expr $fifo_sim_len+2] + append fifo_sim_act (0,1,3,[format "%X" 2]), + set fifo_sim_num [expr $fifo_sim_num+1] + set fifo_sim_len [expr $fifo_sim_len+2] + append fifo_sim_act (0,2,0,[format "%X" 82]), + set fifo_sim_num [expr $fifo_sim_num+1] + set fifo_sim_len [expr $fifo_sim_len+82] + return 000000000000000000000 + } else { + force -freeze /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/rd_en 1 -cancel 10ns + run 20ns + #after 10 + set fifo_data [examine /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/data_out] + return $fifo_data + } +} + +proc config_addr {{jtag_index_1 1} {mask 0100000000} {mask_id 1}} { + global log + set mask_leng [string length $mask] + if {$mask_leng!=10} { + $log insert end "\nError: Wrong address mask length @$mask_id: [expr $mask_leng-2]. Expects: 8.\n" + + } else { + #device_lock -timeout 5 + #device_virtual_ir_shift -instance_index $jtag_index_1 -ir_value 1 -no_captured_ir_value + #set addr_mask [device_virtual_dr_shift -instance_index $jtag_index_1 -dr_value $mask -length 40 -value_in_hex] + #device_unlock + global addr_sim_act + global addr_sim_num + global addr_sim_len + append addr_sim_act (0,1,1,[format "%X" 2]), + set addr_sim_num [expr $addr_sim_num+1] + set addr_sim_len [expr $addr_sim_len+2] + append addr_sim_act (0,2,$mask,[format "%X" 40]), + set addr_sim_num [expr $addr_sim_num+1] + set addr_sim_len [expr $addr_sim_len+40] + return 0 + } +} + +proc config_trig {{jtag_index_2 2} {trig 00000000000000} {pnum 000}} { + global log + set trig_leng [string length $trig] + if {$trig_leng!=14} { + $log insert end "\nError: Wrong trigger condition length: [expr $trig_leng-2]. Expects: 4+8.\n" + } else { + #device_lock -timeout 5 + #device_virtual_ir_shift -instance_index $jtag_index_2 -ir_value 1 -no_captured_ir_value + #set addr_trig [device_virtual_dr_shift -instance_index $jtag_index_2 -dr_value $trig -length 56 -value_in_hex] + #device_virtual_ir_shift -instance_index $jtag_index_2 -ir_value 2 -no_captured_ir_value + #set addr_trig [device_virtual_dr_shift -instance_index $jtag_index_2 -dr_value $pnum -length 10 -value_in_hex] + #device_unlock + global trig_sim_act + global trig_sim_num + global trig_sim_len + append trig_sim_act (0,1,1,[format "%X" 2]), + set trig_sim_num [expr $trig_sim_num+1] + set trig_sim_len [expr $trig_sim_len+2] + append trig_sim_act (0,2,$trig,[format "%X" 56]), + set trig_sim_num [expr $trig_sim_num+1] + set trig_sim_len [expr $trig_sim_len+56] + append trig_sim_act (0,1,2,[format "%X" 2]), + set trig_sim_num [expr $trig_sim_num+1] + set trig_sim_len [expr $trig_sim_len+2] + append trig_sim_act (0,2,$pnum,[format "%X" 10]), + set trig_sim_num [expr $trig_sim_num+1] + set trig_sim_len [expr $trig_sim_len+10] + return 0 + } +} + +proc open_jtag_device {{test_cable "USB-Blaster [USB-0]"} {test_device "@2: EP2SGX90 (0x020E30DD)"}} { + open_device -hardware_name $test_cable -device_name $test_device + # Retrieve device id code. + device_lock -timeout 5 + device_ir_shift -ir_value 6 -no_captured_ir_value + set idcode "0x[device_dr_shift -length 32 -value_in_hex]" + device_unlock + return $idcode +} + +proc close_jtag_device {} { + close_device +} + +proc scan_chain {} { + global log + $log insert end "JTAG Chain Scanning report:\n" + $log insert end "****************************************\n" + set blaster_cables [get_hardware_names] + set cable_num 0 + foreach blaster_cable $blaster_cables { + incr cable_num + $log insert end "@$cable_num: $blaster_cable\n" + } + $log insert end "\n****************************************\n" + global device_list + set device_list "" + foreach blaster_cable $blaster_cables { + $log insert end "$blaster_cable:\n" + lappend device_list $blaster_cable + if [catch {get_device_names -hardware_name $blaster_cable} error_msg] { + $log insert end $error_msg + lappend device_list $error_msg + } else { + foreach test_device [get_device_names -hardware_name $blaster_cable] { + $log insert end "$test_device\n" + } + lappend device_list [get_device_names -hardware_name $blaster_cable] + } + } +} + +proc select_device {{cableNum 1} {deviceNum 1}} { + global log + global device_list + $log insert end "\n****************************************\n" + set test_cable [lindex $device_list [expr 2*$cableNum-2]] + $log insert end "Selected Cable : $test_cable\n" + set test_device [lindex [lindex $device_list [expr 2*$cableNum-1]] [expr $deviceNum-1]] + $log insert end "Selected Device: $test_device\n" + set jtagIdCode [open_jtag_device $test_cable $test_device] + $log insert end "Device ID code : $jtagIdCode\n" + reset_fifo 0 + query_usedw 0 +} + +proc updateAddrConfig {} { + global address_span1 + global address_span2 + global address_span3 + global address_span4 + global address_span5 + global address_span6 + global address_span7 + global address_span8 + global address_span9 + global address_span10 + global address_span11 + global address_span12 + global address_span13 + global address_span14 + global address_span15 + global address_span16 + global address_span_en1 + global address_span_en2 + global address_span_en3 + global address_span_en4 + global address_span_en5 + global address_span_en6 + global address_span_en7 + global address_span_en8 + global address_span_en9 + global address_span_en10 + global address_span_en11 + global address_span_en12 + global address_span_en13 + global address_span_en14 + global address_span_en15 + global address_span_en16 + global addr_wren + global addr_rden + for {set i 1} {$i<=16} {incr i} { + set mask [format "%1X" [expr $i-1]] + append mask [format "%1X" [expr $addr_wren*8+$addr_rden*4+[set address_span_en$i]]] + append mask [set address_span$i] + config_addr 1 $mask $i + } +} + +proc initAddrConfig {} { + global log + global address_span1 + global address_span2 + global address_span3 + global address_span4 + global address_span5 + global address_span6 + global address_span7 + global address_span8 + global address_span9 + global address_span10 + global address_span11 + global address_span12 + global address_span13 + global address_span14 + global address_span15 + global address_span16 + for {set i 1} {$i<=8} {incr i} { + if {[set address_span$i]==""} { + set address_span$i ffff0000 + } + } + for {set i 9} {$i<=16} {incr i} { + if {[set address_span$i]==""} { + set address_span$i 00000000 + } + } +} + +proc initTrigConfig {} { + global triggerAddr + global triggerData + global triggerPnum + if {[set triggerAddr]==""} { + set triggerAddr ffff + } + if {[set triggerData]==""} { + set triggerData a5a5a5a5 + } + if {[set triggerPnum]==""} { + set triggerPnum 0 + } +} + +proc updateTrigger {{trigCmd 0}} { + global triggerAddr + global triggerData + global triggerPnum + global trig_wren + global trig_rden + global trig_aden + global trig_daen + set triggerValue [format "%1X" [expr $trig_aden*8+$trig_daen*4+0]] + append triggerValue [format "%1X" [expr $trig_wren*8+$trig_rden*4+$trigCmd]] + append triggerValue $triggerAddr + append triggerValue $triggerData + config_trig 2 $triggerValue [format "%03X" $triggerPnum] +} + +proc startTrigger {} { + global trig_wren + global trig_rden + global trig_aden + global trig_daen + set trigEnable [expr $trig_wren+$trig_rden+$trig_aden+$trig_daen] + if {$trigEnable>0} { + updateTrigger 2 + reset_fifo 0 + query_usedw 0 + updateTrigger 3 + } else { + updateTrigger 0 + } +} + +proc reset_fifo_ptr {} { + reset_fifo 0 + query_usedw 0 +} + +proc query_fifo_usedw {} { + query_usedw 0 +} + +proc read_fifo_content {} { + global log + global fifoUsedw + $log insert end "\n****************************************\n" + for {set i 0} {$i<$fifoUsedw} {incr i} { + set fifoContent [read_fifo 0] + set ok_trig [expr [format "%d" 0x[string index $fifoContent 0]]/2] + set wr_cptr [expr [format "%d" 0x[string index $fifoContent 0]]%2] + set tm_cptr [format "%d" 0x[string range $fifoContent 1 8]] + set ad_cptr [string range $fifoContent 9 12] + set da_cptr [string range $fifoContent 13 20] + if $ok_trig { + $log insert end "@@@@@@@@@@@@@@@@@@@@\n" + } + if $wr_cptr { + $log insert end "wr $ad_cptr $da_cptr @$tm_cptr\n" + } else { + $log insert end "rd $ad_cptr $da_cptr @$tm_cptr\n" + } + } + query_usedw 0 +} + +proc reset_stimulus {} { + global fifo_sim_act + global fifo_sim_num + global fifo_sim_len + global addr_sim_act + global addr_sim_num + global addr_sim_len + global trig_sim_act + global trig_sim_num + global trig_sim_len + set fifo_sim_act \"( + set fifo_sim_num 0 + set fifo_sim_len 0 + set addr_sim_act \"( + set addr_sim_num 0 + set addr_sim_len 0 + set trig_sim_act \"( + set trig_sim_num 0 + set trig_sim_len 0 +} + +proc generate_stimulus {} { + global log + global fifo_sim_act + global fifo_sim_num + global fifo_sim_len + global addr_sim_act + global addr_sim_num + global addr_sim_len + global trig_sim_act + global trig_sim_num + global trig_sim_len + append fifo_sim_act (1,1,1,2))\" + set fifo_sim_num [expr $fifo_sim_num+1] + set fifo_sim_len [expr $fifo_sim_len+2] + append addr_sim_act (1,1,1,2))\" + set addr_sim_num [expr $addr_sim_num+1] + set addr_sim_len [expr $addr_sim_len+2] + append trig_sim_act (1,1,1,2))\" + set trig_sim_num [expr $trig_sim_num+1] + set trig_sim_len [expr $trig_sim_len+2] + $log delete 1.0 end + $log insert end "`define USE_SIM_STIMULUS\n\n" + $log insert end "`define FIFO_SLD_SIM_ACTION $fifo_sim_act\n" + $log insert end "`define FIFO_SLD_SIM_N_SCAN $fifo_sim_num\n" + $log insert end "`define FIFO_SLD_SIM_T_LENG $fifo_sim_len\n\n" + $log insert end "`define ADDR_SLD_SIM_ACTION $addr_sim_act\n" + $log insert end "`define ADDR_SLD_SIM_N_SCAN $addr_sim_num\n" + $log insert end "`define ADDR_SLD_SIM_T_LENG $addr_sim_len\n\n" + $log insert end "`define TRIG_SLD_SIM_ACTION $trig_sim_act\n" + $log insert end "`define TRIG_SLD_SIM_N_SCAN $trig_sim_num\n" + $log insert end "`define TRIG_SLD_SIM_T_LENG $trig_sim_len\n\n" + + set fileId [open ../../rtl/altera/jtag_sim_define.h w] + puts $fileId [$log get 1.0 end] + close $fileId +} + +proc quit_console {} { + global exit_console + destroy .console + set exit_console 1 +} + +proc back_sim {} { + global exit_console + #destroy .console + set exit_console 1 +} + +proc start_sim {} { + do sim.do +} + +proc pause_sim {} { + vsim_break +} + +# initialize +set exit_console 0 +reset_stimulus +destroy .console + +# set the main window +toplevel .console +wm title .console "www.OpenCores.org: uP Transaction Monitor: Simulation Console" +pack propagate .console true + +# set the www.OpenCores.org logo +frame .console.fig -bg white +pack .console.fig -expand true -fill both +image create photo logo -format gif -file "../../cmd/common/OpenCores.gif" +label .console.fig.logo -image logo -bg white +pack .console.fig.logo + +# set the inclusive address entries +frame .console.f1 -relief groove -borderwidth 5 +pack .console.f1 +label .console.f1.incl_addr -text {Inclusive Addr:} +entry .console.f1.address_span1 -textvariable address_span1 -width 8 +entry .console.f1.address_span2 -textvariable address_span2 -width 8 +entry .console.f1.address_span3 -textvariable address_span3 -width 8 +entry .console.f1.address_span4 -textvariable address_span4 -width 8 +entry .console.f1.address_span5 -textvariable address_span5 -width 8 +entry .console.f1.address_span6 -textvariable address_span6 -width 8 +entry .console.f1.address_span7 -textvariable address_span7 -width 8 +entry .console.f1.address_span8 -textvariable address_span8 -width 8 +checkbutton .console.f1.address_span_en1 -variable address_span_en1 +checkbutton .console.f1.address_span_en2 -variable address_span_en2 +checkbutton .console.f1.address_span_en3 -variable address_span_en3 +checkbutton .console.f1.address_span_en4 -variable address_span_en4 +checkbutton .console.f1.address_span_en5 -variable address_span_en5 +checkbutton .console.f1.address_span_en6 -variable address_span_en6 +checkbutton .console.f1.address_span_en7 -variable address_span_en7 +checkbutton .console.f1.address_span_en8 -variable address_span_en8 +pack .console.f1.incl_addr \ + .console.f1.address_span_en1 .console.f1.address_span1 \ + .console.f1.address_span_en2 .console.f1.address_span2 \ + .console.f1.address_span_en3 .console.f1.address_span3 \ + .console.f1.address_span_en4 .console.f1.address_span4 \ + .console.f1.address_span_en5 .console.f1.address_span5 \ + .console.f1.address_span_en6 .console.f1.address_span6 \ + .console.f1.address_span_en7 .console.f1.address_span7 \ + .console.f1.address_span_en8 .console.f1.address_span8 \ + -side left -ipadx 0 + +# set the exclusive address entries +frame .console.f2 -relief groove -borderwidth 5 +pack .console.f2 +label .console.f2.excl_addr -text {Exclusive Addr:} +entry .console.f2.address_span9 -textvariable address_span9 -width 8 +entry .console.f2.address_span10 -textvariable address_span10 -width 8 +entry .console.f2.address_span11 -textvariable address_span11 -width 8 +entry .console.f2.address_span12 -textvariable address_span12 -width 8 +entry .console.f2.address_span13 -textvariable address_span13 -width 8 +entry .console.f2.address_span14 -textvariable address_span14 -width 8 +entry .console.f2.address_span15 -textvariable address_span15 -width 8 +entry .console.f2.address_span16 -textvariable address_span16 -width 8 +checkbutton .console.f2.address_span_en9 -variable address_span_en9 +checkbutton .console.f2.address_span_en10 -variable address_span_en10 +checkbutton .console.f2.address_span_en11 -variable address_span_en11 +checkbutton .console.f2.address_span_en12 -variable address_span_en12 +checkbutton .console.f2.address_span_en13 -variable address_span_en13 +checkbutton .console.f2.address_span_en14 -variable address_span_en14 +checkbutton .console.f2.address_span_en15 -variable address_span_en15 +checkbutton .console.f2.address_span_en16 -variable address_span_en16 +pack .console.f2.excl_addr \ + .console.f2.address_span_en9 .console.f2.address_span9 \ + .console.f2.address_span_en10 .console.f2.address_span10 \ + .console.f2.address_span_en11 .console.f2.address_span11 \ + .console.f2.address_span_en12 .console.f2.address_span12 \ + .console.f2.address_span_en13 .console.f2.address_span13 \ + .console.f2.address_span_en14 .console.f2.address_span14 \ + .console.f2.address_span_en15 .console.f2.address_span15 \ + .console.f2.address_span_en16 .console.f2.address_span16 \ + -side left -ipadx 0 +initAddrConfig + +# set the address configuration buttons +frame .console.addr_cnfg -relief groove -borderwidth 5 +pack .console.addr_cnfg +checkbutton .console.addr_cnfg.wren -text {WR} -variable addr_wren +checkbutton .console.addr_cnfg.rden -text {RD} -variable addr_rden +button .console.addr_cnfg.config -text {Apply Address Filter} -command {updateAddrConfig} +pack .console.addr_cnfg.wren .console.addr_cnfg.rden .console.addr_cnfg.config \ + -side left -ipadx 0 + +# set the transaction trigger controls +frame .console.trig -relief groove -borderwidth 5 +pack .console.trig +button .console.trig.starttrig -text {Apply Trigger Condition} -command {startTrigger} +entry .console.trig.trigvalue_addr -textvar triggerAddr -width 4 +entry .console.trig.trigvalue_data -textvar triggerData -width 8 +checkbutton .console.trig.trigaddr -text {@Addr:} -variable trig_aden +checkbutton .console.trig.trigdata -text {@Data:} -variable trig_daen +checkbutton .console.trig.wren -text {@WR} -variable trig_wren +checkbutton .console.trig.rden -text {@RD} -variable trig_rden +label .console.trig.pnum -text {Pre-Capture:} +entry .console.trig.trigvalue_pnum -textvar triggerPnum -width 4 +pack .console.trig.pnum .console.trig.trigvalue_pnum \ + .console.trig.wren .console.trig.rden \ + .console.trig.trigaddr .console.trig.trigvalue_addr \ + .console.trig.trigdata .console.trig.trigvalue_data \ + .console.trig.starttrig \ + -side left -ipadx 0 +initTrigConfig + +# set the control buttons +frame .console.fifo -relief groove -borderwidth 5 +pack .console.fifo +button .console.fifo.reset -text {Reset FIFO} -command {reset_fifo_ptr} +button .console.fifo.loop -text {Query Used Word} -command {query_fifo_usedw} +label .console.fifo.usedw -textvariable fifoUsedw -relief sunken -width 4 +button .console.fifo.read -text {Read FIFO} -command {read_fifo_content} +pack .console.fifo.reset .console.fifo.loop .console.fifo.usedw .console.fifo.read \ + -side left -ipadx 0 + +# set the control buttons +frame .console.sim -relief groove -borderwidth 5 +pack .console.sim +button .console.sim.reset -text {Reset Stimulus} -command {reset_stimulus} +button .console.sim.generate -text {Generate Stimulus} -command {generate_stimulus} +button .console.sim.start -text {Start Simulation} -command {start_sim} +button .console.sim.pause -text {Pause Simulation} -command {pause_sim} +button .console.sim.back -text {Back to Simulation} -command {back_sim} +button .console.sim.quit -text {Quit} -command {quit_console} +pack .console.sim.reset .console.sim.generate .console.sim.back .console.sim.quit \ + -side left -ipadx 0 + +# set the log window +frame .console.log -relief groove -borderwidth 5 +set log [text .console.log.text -width 80 -height 25 \ + -borderwidth 2 -relief sunken -setgrid true \ + -yscrollcommand {.console.log.scroll set}] +scrollbar .console.log.scroll -command {.console.log.text yview} +pack .console.log.scroll -side right -fill y +pack .console.log.text -side left -fill both -expand true +pack .console.log -side top -fill both -expand true + +# make the program wait for exit signal +vwait exit_console + Index: tags/v2p2/sim/altera/jtag_bfm_sv.v =================================================================== --- tags/v2p2/sim/altera/jtag_bfm_sv.v (nonexistent) +++ tags/v2p2/sim/altera/jtag_bfm_sv.v (revision 16) @@ -0,0 +1,33 @@ +//************************************************************** +// Module : jtag_bfm_sv.v +// Platform : Windows xp sp2 +// Simulator : Modelsim 6.5b +// Synthesizer : +// Place and Route : +// Targets device : +// Author : Bibo Yang (ash_riple@hotmail.com) +// Organization : www.opencores.org +// Revision : 2.2 +// Date : 2012/03/28 +// Description : JTAG Stimulus monitor +//************************************************************** + +`timescale 1ns/1ns +`include "jtag_sim_define.h" + +module jtag_bfm_sv ( +); + +reg jtag_sim_done; +initial begin + jtag_sim_done = 0; + fork + @(posedge up_monitor_tb.MON_LO.inst.u_virtual_jtag_adda_fifo.sld_virtual_jtag_component.user_input.vj_sim_done); + @(posedge up_monitor_tb.MON_LO.inst.u_virtual_jtag_addr_mask.sld_virtual_jtag_component.user_input.vj_sim_done); + @(posedge up_monitor_tb.MON_LO.inst.u_virtual_jtag_adda_trig.sld_virtual_jtag_component.user_input.vj_sim_done); + join + $display("All JTAG stimulus excercised"); + jtag_sim_done = 1; +end + +endmodule Index: tags/v2p2/sim/altera/sim.sh =================================================================== --- tags/v2p2/sim/altera/sim.sh (nonexistent) +++ tags/v2p2/sim/altera/sim.sh (revision 16) @@ -0,0 +1,50 @@ +quit -sim +vlib work +vdel -lib work -all +vlib work + +set sim_started 0 + +# compile vendor independent files +vlog -work work ../../rtl/up_monitor.v +initreg+0 +vlog -work work ../../rtl/up_monitor_wrapper.v +initreg+0 + +# compile altera virtual jtag files +source virtual_jtag_stimulus.tcl +vlog -work work ../../rtl/altera/virtual_jtag_adda_fifo.v +incdir+../../rtl/altera +vlog -work work ../../rtl/altera/virtual_jtag_adda_trig.v +incdir+../../rtl/altera +vlog -work work ../../rtl/altera/virtual_jtag_addr_mask.v +incdir+../../rtl/altera +vlog -work work altera_mf.v + +# compile testbench files +vlog -work work -sv ../up_monitor_tb.v + +# compile register bfm files +vlog -work work -sv ../reg_bfm_sv.v + +# compile cpu bfm files +# Sytemverilog DPI steps to combine sv and c +# step 1: generate dpiheader.h +vlog -work work -sv -dpiheader ../dpiheader.h ../up_bfm_sv.v +## step 2: generate up_bfm_sv.obj +#vsim -dpiexportobj up_bfm_sv up_bfm_sv +# step 3: generate up_bfm_c.o +gcc -c -I $::env(MODEL_TECH)/../include ../up_bfm_c.c +# step 4: generate up_bfm_c.dll +gcc -shared -Bsymbolic -o up_bfm_c.so up_bfm_c.o + +# compile jtag bfms files +vlog -work work -sv jtag_bfm_sv.v +incdir+../../rtl/altera + +vsim -novopt \ + -sv_lib up_bfm_c \ + -t ps \ + up_monitor_tb + +set sim_started 1 + +log -r */* +radix -hexadecimal +do wave.do + +run 10000ns Index: tags/v2p2/sim/altera/wave.do =================================================================== --- tags/v2p2/sim/altera/wave.do (nonexistent) +++ tags/v2p2/sim/altera/wave.do (revision 16) @@ -0,0 +1,73 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate -divider {CPU BFM} +add wave -noupdate -format Logic /up_monitor_tb/CPU/up_clk +add wave -noupdate -format Logic /up_monitor_tb/CPU/up_csn +add wave -noupdate -format Logic /up_monitor_tb/CPU/up_wbe +add wave -noupdate -format Literal /up_monitor_tb/CPU/up_addr +add wave -noupdate -format Literal /up_monitor_tb/CPU/up_data_io +add wave -noupdate -divider {REG BFM} +add wave -noupdate -format Logic /up_monitor_tb/REG/up_clk +add wave -noupdate -format Logic /up_monitor_tb/REG/up_csn +add wave -noupdate -format Logic /up_monitor_tb/REG/up_wbe +add wave -noupdate -format Literal /up_monitor_tb/REG/up_addr +add wave -noupdate -format Literal /up_monitor_tb/REG/up_data_io +add wave -noupdate -divider MON_LO +add wave -noupdate -format Logic /up_monitor_tb/MON_LO/up_wbe +add wave -noupdate -format Logic /up_monitor_tb/MON_LO/up_csn +add wave -noupdate -format Literal /up_monitor_tb/MON_LO/up_addr +add wave -noupdate -format Literal /up_monitor_tb/MON_LO/up_data_io +add wave -noupdate -format Logic /up_monitor_tb/MON_LO/up_clk +add wave -noupdate -divider pin-to-transaction +add wave -noupdate -format Logic /up_monitor_tb/MON_LO/wr_en +add wave -noupdate -format Logic /up_monitor_tb/MON_LO/rd_en +add wave -noupdate -format Literal /up_monitor_tb/MON_LO/addr_in +add wave -noupdate -format Literal /up_monitor_tb/MON_LO/data_in +add wave -noupdate -divider {New Divider} +add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/wr_en_d1 +add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/rd_en_d1 +add wave -noupdate -format Literal /up_monitor_tb/MON_LO/inst/addr_in_d1 +add wave -noupdate -format Literal /up_monitor_tb/MON_LO/inst/data_in_d1 +add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/addr_mask_ok +add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/trig_cond_ok_d1 +add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/capture_wr +add wave -noupdate -format Literal /up_monitor_tb/MON_LO/inst/capture_in +add wave -noupdate -divider {New Divider} +add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/clk +add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/wr_en +add wave -noupdate -format Literal /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/data_in +add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/reset +add wave -noupdate -format Literal /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/usedw +add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/rd_en +add wave -noupdate -format Literal /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/data_out +add wave -noupdate -divider {New Divider} +add wave -noupdate -format Literal /up_monitor_tb/MON_LO/inst/pretrig_num +add wave -noupdate -format Literal /up_monitor_tb/MON_LO/inst/pretrig_cnt +add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/pretrig_full +add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/pretrig_wr +add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/pretrig_rd +add wave -noupdate -divider {New Divider} +add wave -noupdate -format Literal -radix unsigned /up_monitor_tb/MON_LO/inst/inter_cap_cnt +add wave -noupdate -divider {New Divider} +add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_fifo/sld_virtual_jtag_component/user_input/vj_sim_done +add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/u_virtual_jtag_adda_trig/sld_virtual_jtag_component/user_input/vj_sim_done +add wave -noupdate -format Logic /up_monitor_tb/MON_LO/inst/u_virtual_jtag_addr_mask/sld_virtual_jtag_component/user_input/vj_sim_done +add wave -noupdate -divider {New Divider} +add wave -noupdate -divider {New Divider} +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {8603967 ps} 0} +configure wave -namecolwidth 147 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits ps +update +WaveRestoreZoom {0 ps} {10500 ns} Index: tags/v2p2/sim/altera/sim.do =================================================================== --- tags/v2p2/sim/altera/sim.do (nonexistent) +++ tags/v2p2/sim/altera/sim.do (revision 16) @@ -0,0 +1,51 @@ +quit -sim +vlib work +vdel -lib work -all +vlib work + +set sim_started 0 + +# compile vendor independent files +vlog -work work ../../rtl/up_monitor.v +initreg+0 +vlog -work work ../../rtl/up_monitor_wrapper.v +initreg+0 + +# compile altera virtual jtag files +source virtual_jtag_stimulus.tcl +vlog -work work ../../rtl/altera/virtual_jtag_adda_fifo.v +incdir+../../rtl/altera +vlog -work work ../../rtl/altera/virtual_jtag_adda_trig.v +incdir+../../rtl/altera +vlog -work work ../../rtl/altera/virtual_jtag_addr_mask.v +incdir+../../rtl/altera +vlog -work work altera_mf.v + +# compile testbench files +vlog -work work -sv ../up_monitor_tb.v + +# compile register bfm files +vlog -work work -sv ../reg_bfm_sv.v + +# compile cpu bfm files +# Sytemverilog DPI steps to combine sv and c +# step 1: generate dpiheader.h +vlog -work work -sv -dpiheader ../dpiheader.h ../up_bfm_sv.v +# step 2: generate up_bfm_sv.obj +vsim -dpiexportobj up_bfm_sv up_bfm_sv +# step 3: generate up_bfm_c.o +gcc -c -I $::env(MODEL_TECH)/../include ../up_bfm_c.c +# step 4: generate up_bfm_c.dll +gcc -shared -Bsymbolic -o up_bfm_c.dll up_bfm_c.o \ + up_bfm_sv.obj -L $::env(MODEL_TECH) -lmtipli + +# compile jtag bfms files +vlog -work work -sv jtag_bfm_sv.v +incdir+../../rtl/altera + +vsim -novopt \ + -sv_lib up_bfm_c \ + -t ps \ + up_monitor_tb + +set sim_started 1 + +log -r */* +radix -hexadecimal +do wave.do + +run 10000ns Index: tags/v2p2/sim/altera/sim.bat =================================================================== --- tags/v2p2/sim/altera/sim.bat (nonexistent) +++ tags/v2p2/sim/altera/sim.bat (revision 16) @@ -0,0 +1,7 @@ +title %CD% + +SET LM_LICENSE_FILE=C:\lmlicense\licensefile.dat +SET MODEL_TECH=C:\modeltech_6.5b\win32 +SET PATH=C:\Modeltech_6.5b\win32;C:\modeltech_6.5b\gcc-4.2.1-mingw32\bin + +vsim -do sim.do \ No newline at end of file Index: tags/v2p2/sim/altera/altera_mf.v =================================================================== --- tags/v2p2/sim/altera/altera_mf.v (nonexistent) +++ tags/v2p2/sim/altera/altera_mf.v (revision 16) @@ -0,0 +1,2979 @@ +// Copyright (C) 1991-2011 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. +// Quartus II 10.1 Build 197 11/29/2010 + + +// VIRTUAL JTAG MODULE CONSTANTS + +// the default bit length for time and value +`define DEFAULT_BIT_LENGTH 32 + +// the bit length for type +`define TYPE_BIT_LENGTH 4 + +// the bit length for delay time +`define TIME_BIT_LENGTH 64 + +// the number of selection bits + width of hub instructions(3) +`define NUM_SELECTION_BITS 4 + +// the states for the parser state machine +`define STARTSTATE 3'b000 +`define LENGTHSTATE 3'b001 +`define VALUESTATE 3'b011 +`define TYPESTATE 3'b111 +`define TIMESTATE 3'b101 + +`define V_DR_SCAN_TYPE 4'b0010 +`define V_IR_SCAN_TYPE 4'b0001 + +// specify time scale, allowing JTAG to run at 1GHz against actual 10MHz +`define CLK_PERIOD 1000 + +`define DELAY_RESOLUTION 100 + +// the states for the tap controller state machine +`define TLR_ST 5'b00000 +`define RTI_ST 5'b00001 +`define DRS_ST 5'b00011 +`define CDR_ST 5'b00111 +`define SDR_ST 5'b01111 +`define E1DR_ST 5'b01011 +`define PDR_ST 5'b01101 +`define E2DR_ST 5'b01000 +`define UDR_ST 5'b01001 +`define IRS_ST 5'b01100 +`define CIR_ST 5'b01010 +`define SIR_ST 5'b00101 +`define E1IR_ST 5'b00100 +`define PIR_ST 5'b00010 +`define E2IR_ST 5'b00110 +`define UIR_ST 5'b01110 +`define INIT_ST 5'b10000 + +// usr1 instruction for tap controller +`define JTAG_USR1_INSTR 10'b0000001110 + + +//START_MODULE_NAME------------------------------------------------------------ +// Module Name : signal_gen +// +// Description : Simulates customizable actions on a JTAG input +// +// Limitation : Zero is not a valid length and causes simulation to halt with +// an error message. +// Values with more bits than specified length will be truncated. +// Length for IR scans are ignored. They however should be factored in when +// calculating SLD_NODE_TOTAl_LENGTH. +// +// Results expected : +// +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module signal_gen (tck,tms,tdi,jtag_usr1,tdo); + + + // GLOBAL PARAMETER DECLARATION + parameter sld_node_ir_width = 1; + parameter sld_node_n_scan = 0; + parameter sld_node_total_length = 0; + parameter sld_node_sim_action = "()"; + + // INPUT PORTS + input jtag_usr1; + input tdo; + + // OUTPUT PORTS + output tck; + output tms; + output tdi; + + // CONSTANT DECLARATIONS +`define DECODED_SCANS_LENGTH (sld_node_total_length + ((sld_node_n_scan * `DEFAULT_BIT_LENGTH) * 2) + (sld_node_n_scan * `TYPE_BIT_LENGTH) - 1) +`define DEFAULT_SCAN_LENGTH (sld_node_n_scan * `DEFAULT_BIT_LENGTH) +`define TYPE_SCAN_LENGTH (sld_node_n_scan * `TYPE_BIT_LENGTH) - 1 + + // INTEGER DECLARATION + integer char_idx; // character_loop index + integer value_idx; // decoding value index + integer value_idx_old; // previous decoding value index + integer value_idx_cur; // reading/outputing value index + integer length_idx; // decoding length index + integer length_idx_old; // previous decoding length index + integer length_idx_cur; // reading/outputing length index + integer last_length_idx;// decoding previous length index + integer type_idx; // decoding type index + integer type_idx_old; // previous decoding type index + integer type_idx_cur; // reading/outputing type index + integer time_idx; // decoding time index + integer time_idx_old; // previous decoding time index + integer time_idx_cur; // reading/outputing time index + + // REGISTERS + reg [ `DEFAULT_SCAN_LENGTH - 1 : 0 ] scan_length; + // register for the 32-bit length values + reg [ sld_node_total_length - 1 : 0 ] scan_values; + // register for values + reg [ `TYPE_SCAN_LENGTH : 0 ] scan_type; + // register for 4-bit type + reg [ `DEFAULT_SCAN_LENGTH - 1 : 0 ] scan_time; + // register to hold time values + reg [15 : 0] two_character; + // two ascii characters. Used in decoding + reg [2 : 0] c_state; + // the current state register + reg [3 : 0] hex_value; + // temporary value to hold hex value of ascii character + reg [31 : 0] last_length; + // register to hold the previous length value read + reg tms_reg; + // register to hold tms value before its clocked + reg tdi_reg; + // register to hold tdi vale before its clocked + + // OUTPUT REGISTERS + reg tms; + reg tck; + reg tdi; + + // input registers + + // LOCAL TIME DECLARATION + + // FUNCTION DECLARATION + + // hexToBits - takes in a hexadecimal character and + // returns the 4-bit value of the character. + // Returns 0 if character is not a hexadeciaml character + function [3 : 0] hexToBits; + input [7 : 0] character; + begin + case ( character ) + "0" : hexToBits = 4'b0000; + "1" : hexToBits = 4'b0001; + "2" : hexToBits = 4'b0010; + "3" : hexToBits = 4'b0011; + "4" : hexToBits = 4'b0100; + "5" : hexToBits = 4'b0101; + "6" : hexToBits = 4'b0110; + "7" : hexToBits = 4'b0111; + "8" : hexToBits = 4'b1000; + "9" : hexToBits = 4'b1001; + "A" : hexToBits = 4'b1010; + "a" : hexToBits = 4'b1010; + "B" : hexToBits = 4'b1011; + "b" : hexToBits = 4'b1011; + "C" : hexToBits = 4'b1100; + "c" : hexToBits = 4'b1100; + "D" : hexToBits = 4'b1101; + "d" : hexToBits = 4'b1101; + "E" : hexToBits = 4'b1110; + "e" : hexToBits = 4'b1110; + "F" : hexToBits = 4'b1111; + "f" : hexToBits = 4'b1111; + default : + begin + hexToBits = 4'b0000; + $display("%s is not a hexadecimal value",character); + end + endcase + end + endfunction + + // TASK DECLARATIONS + + // clocks tck + task clock_tck; + input in_tms; + input in_tdi; + begin : clock_tck_tsk + #(`CLK_PERIOD/2) tck <= ~tck; + tms <= in_tms; + tdi <= in_tdi; + #(`CLK_PERIOD/2) tck <= ~tck; + end // clock_tck_tsk + endtask // clock_tck + + // move tap controller from dr/ir shift state to ir/dr update state + task goto_update_state; + begin : goto_update_state_tsk + // get into e1(i/d)r state + tms_reg = 1'b1; + clock_tck(tms_reg,tdi_reg); + // get into u(i/d)r state + tms_reg = 1'b1; + clock_tck(tms_reg,tdi_reg); + end // goto_update_state_tsk + endtask // goto_update_state + + // resets the jtag TAP controller by holding tms high + // for 6 tck cycles + task reset_jtag; + integer idx; + begin + for (idx = 0; idx < 6; idx= idx + 1) + begin + tms_reg = 1'b1; + clock_tck(tms_reg,tdi_reg); + end + // get into rti state + tms_reg = 1'b0; + clock_tck(tms_reg,tdi_reg); + jtag_ir_usr1; + end + endtask // reset_jtag + + // sends a jtag_usr0 intsruction + task jtag_ir_usr0; + integer i; + begin : jtag_ir_usr0_tsk + // get into drs state + tms_reg = 1'b1; + clock_tck(tms_reg,tdi_reg); + // get into irs state + tms_reg = 1'b1; + clock_tck(tms_reg,tdi_reg); + // get into cir state + tms_reg = 1'b0; + clock_tck(tms_reg,tdi_reg); + // get into sir state + tms_reg = 1'b0; + clock_tck(tms_reg,tdi_reg); + // shift in data i.e usr0 instruction + // usr1 = 0x0E = 0b00 0000 1100 + for ( i = 0; i < 2; i = i + 1) + begin :ir_usr0_loop1 + tdi_reg = 1'b0; + tms_reg = 1'b0; + clock_tck(tms_reg,tdi_reg); + end // ir_usr0_loop1 + for ( i = 0; i < 2; i = i + 1) + begin :ir_usr0_loop2 + tdi_reg = 1'b1; + tms_reg = 1'b0; + clock_tck(tms_reg,tdi_reg); + end // ir_usr0_loop2 + // done with 1100 + for ( i = 0; i < 6; i = i + 1) + begin :ir_usr0_loop3 + tdi_reg = 1'b0; + tms_reg = 1'b0; + clock_tck(tms_reg,tdi_reg); + end // ir_usr0_loop3 + // done with 00 0000 + // get into e1ir state + tms_reg = 1'b1; + clock_tck(tms_reg,tdi_reg); + // get into uir state + tms_reg = 1'b1; + clock_tck(tms_reg,tdi_reg); + end // jtag_ir_usr0_tsk + endtask // jtag_ir_usr0 + + // sends a jtag_usr1 intsruction + task jtag_ir_usr1; + integer i; + begin : jtag_ir_usr1_tsk + // get into drs state + tms_reg = 1'b1; + clock_tck(tms_reg,tdi_reg); + // get into irs state + tms_reg = 1'b1; + clock_tck(tms_reg,tdi_reg); + // get into cir state + tms_reg = 1'b0; + clock_tck(tms_reg,tdi_reg); + // get into sir state + tms_reg = 1'b0; + clock_tck(tms_reg,tdi_reg); + // shift in data i.e usr1 instruction + // usr1 = 0x0E = 0b00 0000 1110 + tdi_reg = 1'b0; + tms_reg = 1'b0; + clock_tck(tms_reg,tdi_reg); + for ( i = 0; i < 3; i = i + 1) + begin :ir_usr1_loop1 + tdi_reg = 1'b1; + tms_reg = 1'b0; + clock_tck(tms_reg,tdi_reg); + end // ir_usr1_loop1 + // done with 1110 + for ( i = 0; i < 5; i = i + 1) + begin :ir_usr1_loop2 + tdi_reg = 1'b0; + tms_reg = 1'b0; + clock_tck(tms_reg,tdi_reg); + end // ir_sur1_loop2 + tdi_reg = 1'b0; + tms_reg = 1'b1; + clock_tck(tms_reg,tdi_reg); + // done with 00 0000 + // now in e1ir state + // get into uir state + tms_reg = 1'b1; + clock_tck(tms_reg,tdi_reg); + end // jtag_ir_usr1_tsk + endtask // jtag_ir_usr1 + + // sends a force_ir_capture instruction to the node + task send_force_ir_capture; + integer i; + begin : send_force_ir_capture_tsk + goto_dr_shift_state; + // start shifting in the instruction + tdi_reg = 1'b1; + tms_reg = 1'b0; + clock_tck(tms_reg,tdi_reg); + tdi_reg = 1'b1; + tms_reg = 1'b0; + clock_tck(tms_reg,tdi_reg); + tdi_reg = 1'b0; + tms_reg = 1'b0; + clock_tck(tms_reg,tdi_reg); + // done with 011 + tdi_reg = 1'b0; + tms_reg = 1'b0; + clock_tck(tms_reg,tdi_reg); + // done with select bit + // fill up with zeros up to ir_width + for ( i = 0; i < sld_node_ir_width - 4; i = i + 1 ) + begin + tdi_reg = 1'b0; + tms_reg = 1'b0; + clock_tck(tms_reg,tdi_reg); + end + goto_update_state; + end // send_force_ir_capture_tsk + endtask // send_forse_ir_capture + + // puts the JTAG tap controller in DR shift state + task goto_dr_shift_state; + begin : goto_dr_shift_state_tsk + // get into drs state + tms_reg = 1'b1; + clock_tck(tms_reg,tdi_reg); + // get into cdr state + tms_reg = 1'b0; + clock_tck(tms_reg,tdi_reg); + // get into sdr state + tms_reg = 1'b0; + clock_tck(tms_reg,tdi_reg); + end // goto_dr_shift_state_tsk + endtask // goto_dr_shift_state + + // performs a virtual_ir_scan + task v_ir_scan; + input [`DEFAULT_BIT_LENGTH - 1 : 0] length; + integer i; + begin : v_ir_scan_tsk + // if we are not in usr1 then go to usr1 state + if (jtag_usr1 == 1'b0) + begin + jtag_ir_usr1; + end + // send force_ir_capture + send_force_ir_capture; + // shift in the ir value + goto_dr_shift_state; + value_idx_cur = value_idx_cur - length; + for ( i = 0; i < length; i = i + 1) + begin + tms_reg = 1'b0; + tdi_reg = scan_values[value_idx_cur + i]; + clock_tck(tms_reg,tdi_reg); + end + // pad with zeros if necessary + for(i = length; i < sld_node_ir_width; i = i + 1) + begin : zero_padding + tdi_reg = 1'b0; + tms_reg = 1'b0; + clock_tck(tms_reg,tdi_reg); + end //zero_padding + tdi_reg = 1'b1; + goto_update_state; + end // v_ir_scan_tsk + endtask // v_ir_scan + + // performs a virtual dr scan + task v_dr_scan; + input [`DEFAULT_BIT_LENGTH - 1 : 0] length; + integer i; + begin : v_dr_scan_tsk + // if we are in usr1 then go to usr0 state + if (jtag_usr1 == 1'b1) + begin + jtag_ir_usr0; + end + // shift in the dr value + goto_dr_shift_state; + value_idx_cur = value_idx_cur - length; + for ( i = 0; i < length - 1; i = i + 1) + begin + tms_reg = 1'b0; + tdi_reg = scan_values[value_idx_cur + i]; + clock_tck(tms_reg,tdi_reg); + end + // last bit is clocked together with state transition + tdi_reg = scan_values[value_idx_cur + i]; + goto_update_state; + end // v_dr_scan_tsk + endtask // v_dr_scan + + reg vj_sim_done; + initial + begin : sim_model + vj_sim_done = 0; + // initialize output registers + tck = 1'b1; + tms = 1'b0; + tdi = 1'b0; + // initialize variables + tms_reg = 1'b0; + tdi_reg = 1'b0; + two_character = 'b0; + last_length_idx = 0; + value_idx = 0; + value_idx_old = 0; + length_idx = 0; + length_idx_old = 0; + type_idx = 0; + type_idx_old = 0; + time_idx = 0; + time_idx_old = 0; + scan_length = 'b0; + scan_values = 'b0; + scan_type = 'b0; + scan_time = 'b0; + last_length = 'b0; + hex_value = 'b0; + c_state = `STARTSTATE; + // initialize current indices + value_idx_cur = sld_node_total_length; + type_idx_cur = `TYPE_SCAN_LENGTH; + time_idx_cur = `DEFAULT_SCAN_LENGTH; + length_idx_cur = `DEFAULT_SCAN_LENGTH; + for(char_idx = 0;two_character != "((";char_idx = char_idx + 8) + begin : character_loop + // convert two characters to equivalent 16-bit value + two_character[0] = sld_node_sim_action[char_idx]; + two_character[1] = sld_node_sim_action[char_idx+1]; + two_character[2] = sld_node_sim_action[char_idx+2]; + two_character[3] = sld_node_sim_action[char_idx+3]; + two_character[4] = sld_node_sim_action[char_idx+4]; + two_character[5] = sld_node_sim_action[char_idx+5]; + two_character[6] = sld_node_sim_action[char_idx+6]; + two_character[7] = sld_node_sim_action[char_idx+7]; + two_character[8] = sld_node_sim_action[char_idx+8]; + two_character[9] = sld_node_sim_action[char_idx+9]; + two_character[10] = sld_node_sim_action[char_idx+10]; + two_character[11] = sld_node_sim_action[char_idx+11]; + two_character[12] = sld_node_sim_action[char_idx+12]; + two_character[13] = sld_node_sim_action[char_idx+13]; + two_character[14] = sld_node_sim_action[char_idx+14]; + two_character[15] = sld_node_sim_action[char_idx+15]; + // use state machine to decode + case (c_state) + `STARTSTATE : + begin + if (two_character[15 : 8] != ")") + begin + c_state = `LENGTHSTATE; + end + end + `LENGTHSTATE : + begin + if (two_character[7 : 0] == ",") + begin + length_idx = length_idx_old + 32; + length_idx_old = length_idx; + c_state = `VALUESTATE; + end + else + begin + hex_value = hexToBits(two_character[7:0]); + scan_length [ length_idx] = hex_value[0]; + scan_length [ length_idx + 1] = hex_value[1]; + scan_length [ length_idx + 2] = hex_value[2]; + scan_length [ length_idx + 3] = hex_value[3]; + last_length [ last_length_idx] = hex_value[0]; + last_length [ last_length_idx + 1] = hex_value[1]; + last_length [ last_length_idx + 2] = hex_value[2]; + last_length [ last_length_idx + 3] = hex_value[3]; + length_idx = length_idx + 4; + last_length_idx = last_length_idx + 4; + end + end + `VALUESTATE : + begin + if (two_character[7 : 0] == ",") + begin + value_idx = value_idx_old + last_length; + value_idx_old = value_idx; + last_length = 'b0; // reset the last length value + last_length_idx = 0; // reset index for length + c_state = `TYPESTATE; + end + else + begin + hex_value = hexToBits(two_character[7:0]); + scan_values [ value_idx] = hex_value[0]; + scan_values [ value_idx + 1] = hex_value[1]; + scan_values [ value_idx + 2] = hex_value[2]; + scan_values [ value_idx + 3] = hex_value[3]; + value_idx = value_idx + 4; + end + end + `TYPESTATE : + begin + if (two_character[7 : 0] == ",") + begin + type_idx = type_idx + 4; + c_state = `TIMESTATE; + end + else + begin + hex_value = hexToBits(two_character[7:0]); + scan_type [ type_idx] = hex_value[0]; + scan_type [ type_idx + 1] = hex_value[1]; + scan_type [ type_idx + 2] = hex_value[2]; + scan_type [ type_idx + 3] = hex_value[3]; + end + end + `TIMESTATE : + begin + if (two_character[7 : 0] == "(") + begin + time_idx = time_idx_old + 32; + time_idx_old = time_idx; + c_state = `STARTSTATE; + end + else + begin + hex_value = hexToBits(two_character[7:0]); + scan_time [ time_idx] = hex_value[0]; + scan_time [ time_idx + 1] = hex_value[1]; + scan_time [ time_idx + 2] = hex_value[2]; + scan_time [ time_idx + 3] = hex_value[3]; + time_idx = time_idx + 4; + end + end + default : + c_state = `STARTSTATE; + endcase + end // block: character_loop + # (`CLK_PERIOD/2); + begin : execute + integer write_scan_idx; + integer tempLength_idx; + reg [`TYPE_BIT_LENGTH - 1 : 0] tempType; + reg [`DEFAULT_BIT_LENGTH - 1 : 0 ] tempLength; + reg [`DEFAULT_BIT_LENGTH - 1 : 0 ] tempTime; + reg [`TIME_BIT_LENGTH - 1 : 0 ] delayTime; + reset_jtag; + for (write_scan_idx = 0; write_scan_idx < sld_node_n_scan; write_scan_idx = write_scan_idx + 1) + begin : all_scans_loop + tempType[3] = scan_type[type_idx_cur]; + tempType[2] = scan_type[type_idx_cur - 1]; + tempType[1] = scan_type[type_idx_cur - 2]; + tempType[0] = scan_type[type_idx_cur - 3]; + time_idx_cur = time_idx_cur - `DEFAULT_BIT_LENGTH; + length_idx_cur = length_idx_cur - `DEFAULT_BIT_LENGTH; + for (tempLength_idx = 0; tempLength_idx < `DEFAULT_BIT_LENGTH; tempLength_idx = tempLength_idx + 1) + begin : get_scan_time + tempTime[tempLength_idx] = scan_time[time_idx_cur + tempLength_idx]; + end // get_scan_time + delayTime =(`DELAY_RESOLUTION * `CLK_PERIOD * tempTime); + # delayTime; + if (tempType == `V_IR_SCAN_TYPE) + begin + for (tempLength_idx = 0; tempLength_idx < `DEFAULT_BIT_LENGTH; tempLength_idx = tempLength_idx + 1) + begin : ir_get_length + tempLength[tempLength_idx] = scan_length[length_idx_cur + tempLength_idx]; + end // ir_get_length + v_ir_scan(tempLength); + end + else + begin + if (tempType == `V_DR_SCAN_TYPE) + begin + for (tempLength_idx = 0; tempLength_idx < `DEFAULT_BIT_LENGTH; tempLength_idx = tempLength_idx + 1) + begin : dr_get_length + tempLength[tempLength_idx] = scan_length[length_idx_cur + tempLength_idx]; + end // dr_get_length + v_dr_scan(tempLength); + end + else + begin + $display("Invalid scan type"); + end + end + type_idx_cur = type_idx_cur - 4; + end // all_scans_loop + //get into tlr state + for (tempLength_idx = 0; tempLength_idx < 6; tempLength_idx= tempLength_idx + 1) + begin + tms_reg = 1'b1; + clock_tck(tms_reg,tdi_reg); + end + end //execute + vj_sim_done = 1; + end // block: sim_model +endmodule // signal_gen + +// END OF MODULE + + + +//START_MODULE_NAME------------------------------------------------------------ +// Module Name : jtag_tap_controller +// +// Description : Behavioral model of JTAG tap controller with state signals +// +// Limitation : Can only decode USER1 and USER0 instructions +// +// Results expected : +// +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module jtag_tap_controller (tck,tms,tdi,jtag_tdo,tdo,jtag_tck,jtag_tms,jtag_tdi, + jtag_state_tlr,jtag_state_rti,jtag_state_drs,jtag_state_cdr, + jtag_state_sdr,jtag_state_e1dr,jtag_state_pdr,jtag_state_e2dr, + jtag_state_udr,jtag_state_irs,jtag_state_cir,jtag_state_sir, + jtag_state_e1ir,jtag_state_pir,jtag_state_e2ir,jtag_state_uir, + jtag_usr1); + + + // GLOBAL PARAMETER DECLARATION + parameter ir_register_width = 16; + + // INPUT PORTS + input tck; // tck signal from signal_gen + input tms; // tms signal from signal_gen + input tdi; // tdi signal from signal_gen + input jtag_tdo; // tdo signal from hub + + // OUTPUT PORTS + output tdo; // tdo signal to signal_gen + output jtag_tck; // tck signal from jtag + output jtag_tms; // tms signal from jtag + output jtag_tdi; // tdi signal from jtag + output jtag_state_tlr; // tlr state + output jtag_state_rti; // rti state + output jtag_state_drs; // select dr scan state + output jtag_state_cdr; // capture dr state + output jtag_state_sdr; // shift dr state + output jtag_state_e1dr; // exit1 dr state + output jtag_state_pdr; // pause dr state + output jtag_state_e2dr; // exit2 dr state + output jtag_state_udr; // update dr state + output jtag_state_irs; // select ir scan state + output jtag_state_cir; // capture ir state + output jtag_state_sir; // shift ir state + output jtag_state_e1ir; // exit1 ir state + output jtag_state_pir; // pause ir state + output jtag_state_e2ir; // exit2 ir state + output jtag_state_uir; // update ir state + output jtag_usr1; // jtag has usr1 instruction + + // INTERNAL REGISTERS + + reg tdo_reg; + // temporary tdo output register + reg tdo_rom_reg; + // temporary register used to generate 0101... during SIR_ST + reg jtag_usr1_reg; + // temporary jtag_usr1 register + reg jtag_reset_i; + // internal reset + reg [ 4 : 0 ] cState; + // register for current state + reg [ 4 : 0 ] nState; + // register for the next state signal + reg [ ir_register_width - 1 : 0] ir_srl; + // the ir shift register + reg [ ir_register_width - 1 : 0] ir_srl_hold; + // the ir shift register + + // INTERNAL WIRES + wire [ 4 : 0 ] cState_tmp; + wire [ ir_register_width - 1 : 0] ir_srl_tmp; + + + // OUTPUT REGISTERS + reg jtag_state_tlr; // tlr state + reg jtag_state_rti; // rti state + reg jtag_state_drs; // select dr scan state + reg jtag_state_cdr; // capture dr state + reg jtag_state_sdr; // shift dr state + reg jtag_state_e1dr; // exit1 dr state + reg jtag_state_pdr; // pause dr state + reg jtag_state_e2dr; // exit2 dr state + reg jtag_state_udr; // update dr state + reg jtag_state_irs; // select ir scan state + reg jtag_state_cir; // capture ir state + reg jtag_state_sir; // shift ir state + reg jtag_state_e1ir; // exit1 ir state + reg jtag_state_pir; // pause ir state + reg jtag_state_e2ir; // exit2 ir state + reg jtag_state_uir; // update ir state + + + // INITIAL STATEMENTS + initial + begin + // initialize state registers + cState = `INIT_ST; + nState = `TLR_ST; + end + + // State Register block + always @ (posedge tck or posedge jtag_reset_i) + begin : stateReg + if (jtag_reset_i) + begin + cState <= `TLR_ST; + ir_srl <= 'b0; + tdo_reg <= 1'b0; + tdo_rom_reg <= 1'b0; + jtag_usr1_reg <= 1'b0; + end + else + begin + // in capture ir, set-up tdo_rom_reg + // to generate 010101... + if(cState_tmp == `CIR_ST) + begin + tdo_rom_reg <= 1'b0; + end + else + begin + // write to shift register else pipe + if (cState_tmp == `SIR_ST) + begin + tdo_rom_reg <= ~tdo_rom_reg; + tdo_reg <= tdo_rom_reg; + ir_srl <= ir_srl_tmp >> 1; + ir_srl[ir_register_width - 1] <= tdi; + end + else + begin + tdo_reg <= jtag_tdo; + end + end + // check if in usr1 state + if (cState_tmp == `UIR_ST) + begin + if (ir_srl_hold == `JTAG_USR1_INSTR) + begin + jtag_usr1_reg <= 1'b1; + end + else + begin + jtag_usr1_reg <= 1'b0; + end + end + cState <= nState; + end + end // stateReg + + // hold register + always @ (negedge tck or posedge jtag_reset_i) + begin : holdReg + if (jtag_reset_i) + begin + ir_srl_hold <= 'b0; + end + else + begin + if (cState == `E1IR_ST) + begin + ir_srl_hold <= ir_srl; + end + end + end // holdReg + + // next state logic + always @(cState or tms) + begin : stateTrans + nState = cState; + case (cState) + `TLR_ST : + begin + if (tms == 1'b0) + begin + nState = `RTI_ST; + jtag_reset_i = 1'b0; + end + else + begin + jtag_reset_i = 1'b1; + end + end + `RTI_ST : + begin + if (tms) + begin + nState = `DRS_ST; + end + end + `DRS_ST : + begin + if (tms) + begin + nState = `IRS_ST; + end + else + begin + nState = `CDR_ST; + end + end + `CDR_ST : + begin + if (tms) + begin + nState = `E1DR_ST; + end + else + begin + nState = `SDR_ST; + end + end + `SDR_ST : + begin + if (tms) + begin + nState = `E1DR_ST; + end + end + `E1DR_ST : + begin + if (tms) + begin + nState = `UDR_ST; + end + else + begin + nState = `PDR_ST; + end + end + `PDR_ST : + begin + if (tms) + begin + nState = `E2DR_ST; + end + end + `E2DR_ST : + begin + if (tms) + begin + nState = `UDR_ST; + end + else + begin + nState = `SDR_ST; + end + end + `UDR_ST : + begin + if (tms) + begin + nState = `DRS_ST; + end + else + begin + nState = `RTI_ST; + end + end + `IRS_ST : + begin + if (tms) + begin + nState = `TLR_ST; + end + else + begin + nState = `CIR_ST; + end + end + `CIR_ST : + begin + if (tms) + begin + nState = `E1IR_ST; + end + else + begin + nState = `SIR_ST; + end + end + `SIR_ST : + begin + if (tms) + begin + nState = `E1IR_ST; + end + end + `E1IR_ST : + begin + if (tms) + begin + nState = `UIR_ST; + end + else + begin + nState = `PIR_ST; + end + end + `PIR_ST : + begin + if (tms) + begin + nState = `E2IR_ST; + end + end + `E2IR_ST : + begin + if (tms) + begin + nState = `UIR_ST; + end + else + begin + nState = `SIR_ST; + end + end + `UIR_ST : + begin + if (tms) + begin + nState = `DRS_ST; + end + else + begin + nState = `RTI_ST; + end + end + `INIT_ST : + begin + nState = `TLR_ST; + end + default : + begin + $display("Tap Controller State machine error"); + $display ("Time: %0t Instance: %m", $time); + nState = `TLR_ST; + end + endcase + end // stateTrans + + // Output logic + always @ (cState) + begin : output_logic + jtag_state_tlr <= 1'b0; + jtag_state_rti <= 1'b0; + jtag_state_drs <= 1'b0; + jtag_state_cdr <= 1'b0; + jtag_state_sdr <= 1'b0; + jtag_state_e1dr <= 1'b0; + jtag_state_pdr <= 1'b0; + jtag_state_e2dr <= 1'b0; + jtag_state_udr <= 1'b0; + jtag_state_irs <= 1'b0; + jtag_state_cir <= 1'b0; + jtag_state_sir <= 1'b0; + jtag_state_e1ir <= 1'b0; + jtag_state_pir <= 1'b0; + jtag_state_e2ir <= 1'b0; + jtag_state_uir <= 1'b0; + case (cState) + `TLR_ST : + begin + jtag_state_tlr <= 1'b1; + end + `RTI_ST : + begin + jtag_state_rti <= 1'b1; + end + `DRS_ST : + begin + jtag_state_drs <= 1'b1; + end + `CDR_ST : + begin + jtag_state_cdr <= 1'b1; + end + `SDR_ST : + begin + jtag_state_sdr <= 1'b1; + end + `E1DR_ST : + begin + jtag_state_e1dr <= 1'b1; + end + `PDR_ST : + begin + jtag_state_pdr <= 1'b1; + end + `E2DR_ST : + begin + jtag_state_e2dr <= 1'b1; + end + `UDR_ST : + begin + jtag_state_udr <= 1'b1; + end + `IRS_ST : + begin + jtag_state_irs <= 1'b1; + end + `CIR_ST : + begin + jtag_state_cir <= 1'b1; + end + `SIR_ST : + begin + jtag_state_sir <= 1'b1; + end + `E1IR_ST : + begin + jtag_state_e1ir <= 1'b1; + end + `PIR_ST : + begin + jtag_state_pir <= 1'b1; + end + `E2IR_ST : + begin + jtag_state_e2ir <= 1'b1; + end + `UIR_ST : + begin + jtag_state_uir <= 1'b1; + end + default : + begin + $display("Tap Controller State machine output error"); + $display ("Time: %0t Instance: %m", $time); + end + endcase + end // output_logic + // temporary values + assign ir_srl_tmp = ir_srl; + assign cState_tmp = cState; + + // Pipe through signals + assign tdo = tdo_reg; + assign jtag_tck = tck; + assign jtag_tdi = tdi; + assign jtag_tms = tms; + assign jtag_usr1 = jtag_usr1_reg; + +endmodule +// END OF MODULE + + + +//START_MODULE_NAME------------------------------------------------------------ +// Module Name : dummy_hub +// +// Description : Acts as node and mux between the tap controller and +// user design. Generates hub signals +// +// Limitation : Assumes only one node. Ignores user input on tdo and ir_out. +// +// Results expected : +// +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION + +module dummy_hub (jtag_tck,jtag_tdi,jtag_tms,jtag_usr1,jtag_state_tlr,jtag_state_rti, + jtag_state_drs,jtag_state_cdr,jtag_state_sdr,jtag_state_e1dr, + jtag_state_pdr,jtag_state_e2dr,jtag_state_udr,jtag_state_irs, + jtag_state_cir,jtag_state_sir,jtag_state_e1ir,jtag_state_pir, + jtag_state_e2ir,jtag_state_uir,dummy_tdo,virtual_ir_out, + jtag_tdo,dummy_tck,dummy_tdi,dummy_tms,dummy_state_tlr, + dummy_state_rti,dummy_state_drs,dummy_state_cdr,dummy_state_sdr, + dummy_state_e1dr,dummy_state_pdr,dummy_state_e2dr,dummy_state_udr, + dummy_state_irs,dummy_state_cir,dummy_state_sir,dummy_state_e1ir, + dummy_state_pir,dummy_state_e2ir,dummy_state_uir,virtual_state_cdr, + virtual_state_sdr,virtual_state_e1dr,virtual_state_pdr,virtual_state_e2dr, + virtual_state_udr,virtual_state_cir,virtual_state_uir,virtual_ir_in); + + + // GLOBAL PARAMETER DECLARATION + parameter sld_node_ir_width = 16; + + // INPUT PORTS + + input jtag_tck; // tck signal from tap controller + input jtag_tdi; // tdi signal from tap controller + input jtag_tms; // tms signal from tap controller + input jtag_usr1; // usr1 signal from tap controller + input jtag_state_tlr; // tlr state signal from tap controller + input jtag_state_rti; // rti state signal from tap controller + input jtag_state_drs; // drs state signal from tap controller + input jtag_state_cdr; // cdr state signal from tap controller + input jtag_state_sdr; // sdr state signal from tap controller + input jtag_state_e1dr;// e1dr state signal from tap controller + input jtag_state_pdr; // pdr state signal from tap controller + input jtag_state_e2dr;// esdr state signal from tap controller + input jtag_state_udr; // udr state signal from tap controller + input jtag_state_irs; // irs state signal from tap controller + input jtag_state_cir; // cir state signals from tap controller + input jtag_state_sir; // sir state signal from tap controller + input jtag_state_e1ir;// e1ir state signal from tap controller + input jtag_state_pir; // pir state signals from tap controller + input jtag_state_e2ir;// e2ir state signal from tap controller + input jtag_state_uir; // uir state signal from tap controller + input dummy_tdo; // tdo signal from world + input [sld_node_ir_width - 1 : 0] virtual_ir_out; // captures parallel input from + + // OUTPUT PORTS + output jtag_tdo; // tdo signal to tap controller + output dummy_tck; // tck signal to world + output dummy_tdi; // tdi signal to world + output dummy_tms; // tms signal to world + output dummy_state_tlr; // tlr state signal to world + output dummy_state_rti; // rti state signal to world + output dummy_state_drs; // drs state signal to world + output dummy_state_cdr; // cdr state signal to world + output dummy_state_sdr; // sdr state signal to world + output dummy_state_e1dr; // e1dr state signal to the world + output dummy_state_pdr; // pdr state signal to world + output dummy_state_e2dr; // e2dr state signal to world + output dummy_state_udr; // udr state signal to world + output dummy_state_irs; // irs state signal to world + output dummy_state_cir; // cir state signal to world + output dummy_state_sir; // sir state signal to world + output dummy_state_e1ir; // e1ir state signal to world + output dummy_state_pir; // pir state signal to world + output dummy_state_e2ir; // e2ir state signal to world + output dummy_state_uir; // uir state signal to world + output virtual_state_cdr; // virtual cdr state signal + output virtual_state_sdr; // virtual sdr state signal + output virtual_state_e1dr; // virtual e1dr state signal + output virtual_state_pdr; // virtula pdr state signal + output virtual_state_e2dr; // virtual e2dr state signal + output virtual_state_udr; // virtual udr state signal + output virtual_state_cir; // virtual cir state signal + output virtual_state_uir; // virtual uir state signal + output [sld_node_ir_width - 1 : 0] virtual_ir_in; // parallel output to user design + + +`define SLD_NODE_IR_WIDTH_I sld_node_ir_width + `NUM_SELECTION_BITS // internal ir width + + // INTERNAL REGISTERS + reg capture_ir; // signals force_ir_capture instruction + reg jtag_tdo_reg; // register for jtag_tdo + reg dummy_tdi_reg; // register for dummy_tdi + reg dummy_tck_reg; // register for dummy_tck. + reg [`SLD_NODE_IR_WIDTH_I - 1 : 0] ir_srl; // ir shift register + wire [`SLD_NODE_IR_WIDTH_I - 1 : 0] ir_srl_tmp; // ir shift register + reg [`SLD_NODE_IR_WIDTH_I - 1 : 0] ir_srl_hold; //hold register for ir shift register + + // OUTPUT REGISTERS + reg [sld_node_ir_width - 1 : 0] virtual_ir_in; + + // INITIAL STATEMENTS + always @ (posedge jtag_tck or posedge jtag_state_tlr) + begin : simulation_logic + if (jtag_state_tlr) // asynchronous active high reset + begin : active_hi_async_reset + ir_srl <= 'b0; + jtag_tdo_reg <= 1'b0; + dummy_tdi_reg <= 1'b0; + end // active_hi_async_reset + else + begin : rising_edge_jtag_tck + // logic for shifting in data and piping data through + // logic for muxing inputs to outputs and otherwise + if (jtag_usr1 && jtag_state_sdr) + begin : shift_in_out_usr1 + jtag_tdo_reg <= ir_srl_tmp[0]; + ir_srl <= ir_srl_tmp >> 1; + ir_srl[`SLD_NODE_IR_WIDTH_I - 1] <= jtag_tdi; + end // shift_in_out_usr1 + else + begin + if (capture_ir && jtag_state_cdr) + begin : capture_virtual_ir_out + ir_srl[`SLD_NODE_IR_WIDTH_I - 2 : `NUM_SELECTION_BITS - 1] <= virtual_ir_out; + end // capture_virtual_ir_out + else + begin + if (capture_ir && jtag_state_sdr) + begin : shift_in_out_usr0 + jtag_tdo_reg <= ir_srl_tmp[0]; + ir_srl <= ir_srl_tmp >> 1; + ir_srl[`SLD_NODE_IR_WIDTH_I - 1] <= jtag_tdi; + end // shift_in_out_usr0 + else + begin + if (jtag_state_sdr) + begin : pipe_through + dummy_tdi_reg <= jtag_tdi; + jtag_tdo_reg <= dummy_tdo; + end // pipe_through + end + end + end + end // rising_edge_jtag_tck + end // simulation_logic + + // always block for writing to capture_ir + // stops nlint from complaining. + always @ (posedge jtag_tck or posedge jtag_state_tlr) + begin : capture_ir_logic + if (jtag_state_tlr) // asynchronous active high reset + begin : active_hi_async_reset + capture_ir <= 1'b0; + end // active_hi_async_reset + else + begin : rising_edge_jtag_tck + // should check for 011 instruction + // but we know that it is the only instruction ever sent to the + // hub. So all we have to do is check the selection bit and udr + // and usr1 state + // logic for capture_ir signal + if (jtag_state_udr && (ir_srl[`SLD_NODE_IR_WIDTH_I - 1] == 1'b0)) + begin + capture_ir <= jtag_usr1; + end + else + begin + if (jtag_state_e1dr) + begin + capture_ir <= 1'b0; + end + end + end // rising_edge_jtag_tck + end // capture_ir_logic + + // outputs - rising edge of clock + always @ (posedge jtag_tck or posedge jtag_state_tlr) + begin : parallel_ir_out + if (jtag_state_tlr) + begin : active_hi_async_reset + virtual_ir_in <= 'b0; + end + else + begin : rising_edge_jtag_tck + virtual_ir_in <= ir_srl_hold[`SLD_NODE_IR_WIDTH_I - 2 : `NUM_SELECTION_BITS - 1]; + end + end + + // outputs - falling edge of clock, separated for clarity + always @ (negedge jtag_tck or posedge jtag_state_tlr) + begin : shift_reg_hold + if (jtag_state_tlr) + begin : active_hi_async_reset + ir_srl_hold <= 'b0; + end + else + begin + if (ir_srl[`SLD_NODE_IR_WIDTH_I - 1] && jtag_state_e1dr) + begin + ir_srl_hold <= ir_srl; + end + end + end // shift_reg_hold + + // generate tck in sync with tdi + always @ (posedge jtag_tck or negedge jtag_tck) + begin : gen_tck + dummy_tck_reg <= jtag_tck; + end // gen_tck + // temporary signals + assign ir_srl_tmp = ir_srl; + + // Pipe through signals + assign dummy_state_tlr = jtag_state_tlr; + assign dummy_state_rti = jtag_state_rti; + assign dummy_state_drs = jtag_state_drs; + assign dummy_state_cdr = jtag_state_cdr; + assign dummy_state_sdr = jtag_state_sdr; + assign dummy_state_e1dr = jtag_state_e1dr; + assign dummy_state_pdr = jtag_state_pdr; + assign dummy_state_e2dr = jtag_state_e2dr; + assign dummy_state_udr = jtag_state_udr; + assign dummy_state_irs = jtag_state_irs; + assign dummy_state_cir = jtag_state_cir; + assign dummy_state_sir = jtag_state_sir; + assign dummy_state_e1ir = jtag_state_e1ir; + assign dummy_state_pir = jtag_state_pir; + assign dummy_state_e2ir = jtag_state_e2ir; + assign dummy_state_uir = jtag_state_uir; + assign dummy_tms = jtag_tms; + + + // Virtual signals + assign virtual_state_uir = jtag_usr1 && jtag_state_udr && ir_srl_hold[`SLD_NODE_IR_WIDTH_I - 1]; + assign virtual_state_cir = jtag_usr1 && jtag_state_cdr && ir_srl_hold[`SLD_NODE_IR_WIDTH_I - 1]; + assign virtual_state_udr = (! jtag_usr1) && jtag_state_udr && ir_srl_hold[`SLD_NODE_IR_WIDTH_I - 1]; + assign virtual_state_e2dr = (! jtag_usr1) && jtag_state_e2dr && ir_srl_hold[`SLD_NODE_IR_WIDTH_I - 1]; + assign virtual_state_pdr = (! jtag_usr1) && jtag_state_pdr && ir_srl_hold[`SLD_NODE_IR_WIDTH_I - 1]; + assign virtual_state_e1dr = (! jtag_usr1) && jtag_state_e1dr && ir_srl_hold[`SLD_NODE_IR_WIDTH_I - 1]; + assign virtual_state_sdr = (! jtag_usr1) && jtag_state_sdr && ir_srl_hold[`SLD_NODE_IR_WIDTH_I - 1]; + assign virtual_state_cdr = (! jtag_usr1) && jtag_state_cdr && ir_srl_hold[`SLD_NODE_IR_WIDTH_I - 1]; + + // registered output + assign jtag_tdo = jtag_tdo_reg; + assign dummy_tdi = dummy_tdi_reg; + assign dummy_tck = dummy_tck_reg; + +endmodule +// END OF MODULE + + +//START_MODULE_NAME------------------------------------------------------------ +// Module Name : sld_virtual_jtag +// +// Description : Simulation model for SLD_VIRTUAL_JTAG megafunction +// +// Limitation : None +// +// Results expected : +// +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps +`define IR_REGISTER_WIDTH 10; + + +// MODULE DECLARATION +module sld_virtual_jtag (tdo,ir_out,tck,tdi,ir_in,virtual_state_cdr,virtual_state_sdr, + virtual_state_e1dr,virtual_state_pdr,virtual_state_e2dr, + virtual_state_udr,virtual_state_cir,virtual_state_uir, + jtag_state_tlr,jtag_state_rti,jtag_state_sdrs,jtag_state_cdr, + jtag_state_sdr,jtag_state_e1dr,jtag_state_pdr,jtag_state_e2dr, + jtag_state_udr,jtag_state_sirs,jtag_state_cir,jtag_state_sir, + jtag_state_e1ir,jtag_state_pir,jtag_state_e2ir,jtag_state_uir, + tms); + + + // GLOBAL PARAMETER DECLARATION + parameter lpm_type = "SLD_VIRTUAL_JTAG"; // required by coding standard + parameter lpm_hint = "SLD_VIRTUAL_JTAG"; // required by coding standard + parameter sld_auto_instance_index = "NO"; //Yes if auto index is desired and no otherwise + parameter sld_instance_index = 0; // index to be used if SLD_AUTO_INDEX is no + parameter sld_ir_width = 1; //the width of the IR register + parameter sld_sim_n_scan = 0; // the number of scans in the simulatiom parameters + parameter sld_sim_total_length = 0; // The total bit width of all scan values + parameter sld_sim_action = ""; // the actions to be simulated + + // local parameter declaration + defparam user_input.sld_node_ir_width = sld_ir_width; + defparam user_input.sld_node_n_scan = sld_sim_n_scan; + defparam user_input.sld_node_total_length = sld_sim_total_length; + defparam user_input.sld_node_sim_action = sld_sim_action; + defparam jtag.ir_register_width = 10 ; // compilation fails if defined constant is used + defparam hub.sld_node_ir_width = sld_ir_width; + + + // INPUT PORTS DECLARATION + input tdo; // tdo signal into megafunction + input [sld_ir_width - 1 : 0] ir_out;// parallel ir data into megafunction + + // OUTPUT PORTS DECLARATION + output tck; // tck signal from megafunction + output tdi; // tdi signal from megafunction + output virtual_state_cdr; // cdr state signal of megafunction + output virtual_state_sdr; // sdr state signal of megafunction + output virtual_state_e1dr;// e1dr state signal of megafunction + output virtual_state_pdr; // pdr state signal of megafunction + output virtual_state_e2dr;// e2dr state signal of megafunction + output virtual_state_udr; // udr state signal of megafunction + output virtual_state_cir; // cir state signal of megafunction + output virtual_state_uir; // uir state signal of megafunction + output jtag_state_tlr; // Test, Logic, Reset state + output jtag_state_rti; // Run, Test, Idle state + output jtag_state_sdrs; // Select DR scan state + output jtag_state_cdr; // capture DR state + output jtag_state_sdr; // Shift DR state + output jtag_state_e1dr; // exit 1 dr state + output jtag_state_pdr; // pause dr state + output jtag_state_e2dr; // exit 2 dr state + output jtag_state_udr; // update dr state + output jtag_state_sirs; // Select IR scan state + output jtag_state_cir; // capture IR state + output jtag_state_sir; // shift IR state + output jtag_state_e1ir; // exit 1 IR state + output jtag_state_pir; // pause IR state + output jtag_state_e2ir; // exit 2 IR state + output jtag_state_uir; // update IR state + output tms; // tms signal + output [sld_ir_width - 1 : 0] ir_in; // paraller ir data from megafunction + + // connecting wires + wire tck_i; + wire tms_i; + wire tdi_i; + wire jtag_usr1_i; + wire tdo_i; + wire jtag_tdo_i; + wire jtag_tck_i; + wire jtag_tms_i; + wire jtag_tdi_i; + wire jtag_state_tlr_i; + wire jtag_state_rti_i; + wire jtag_state_drs_i; + wire jtag_state_cdr_i; + wire jtag_state_sdr_i; + wire jtag_state_e1dr_i; + wire jtag_state_pdr_i; + wire jtag_state_e2dr_i; + wire jtag_state_udr_i; + wire jtag_state_irs_i; + wire jtag_state_cir_i; + wire jtag_state_sir_i; + wire jtag_state_e1ir_i; + wire jtag_state_pir_i; + wire jtag_state_e2ir_i; + wire jtag_state_uir_i; + + + // COMPONENT INSTANTIATIONS + // generates input to jtag controller + signal_gen user_input (tck_i,tms_i,tdi_i,jtag_usr1_i,tdo_i); + + // the JTAG TAP controller + jtag_tap_controller jtag (tck_i,tms_i,tdi_i,jtag_tdo_i, + tdo_i,jtag_tck_i,jtag_tms_i,jtag_tdi_i, + jtag_state_tlr_i,jtag_state_rti_i, + jtag_state_drs_i,jtag_state_cdr_i, + jtag_state_sdr_i,jtag_state_e1dr_i, + jtag_state_pdr_i,jtag_state_e2dr_i, + jtag_state_udr_i,jtag_state_irs_i, + jtag_state_cir_i,jtag_state_sir_i, + jtag_state_e1ir_i,jtag_state_pir_i, + jtag_state_e2ir_i,jtag_state_uir_i, + jtag_usr1_i); + + // the HUB + dummy_hub hub (jtag_tck_i,jtag_tdi_i,jtag_tms_i,jtag_usr1_i, + jtag_state_tlr_i,jtag_state_rti_i,jtag_state_drs_i, + jtag_state_cdr_i,jtag_state_sdr_i,jtag_state_e1dr_i, + jtag_state_pdr_i,jtag_state_e2dr_i,jtag_state_udr_i, + jtag_state_irs_i,jtag_state_cir_i,jtag_state_sir_i, + jtag_state_e1ir_i,jtag_state_pir_i,jtag_state_e2ir_i, + jtag_state_uir_i,tdo,ir_out,jtag_tdo_i,tck,tdi,tms, + jtag_state_tlr,jtag_state_rti,jtag_state_sdrs,jtag_state_cdr, + jtag_state_sdr,jtag_state_e1dr,jtag_state_pdr,jtag_state_e2dr, + jtag_state_udr,jtag_state_sirs,jtag_state_cir,jtag_state_sir, + jtag_state_e1ir,jtag_state_pir,jtag_state_e2ir,jtag_state_uir, + virtual_state_cdr,virtual_state_sdr,virtual_state_e1dr, + virtual_state_pdr,virtual_state_e2dr,virtual_state_udr, + virtual_state_cir,virtual_state_uir,ir_in); + +endmodule +// END OF MODULE + + + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : scfifo +// +// Description : Single Clock FIFO +// +// Limitation : +// +// Results expected: +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module scfifo ( data, + clock, + wrreq, + rdreq, + aclr, + sclr, + q, + usedw, + full, + empty, + almost_full, + almost_empty); + +// GLOBAL PARAMETER DECLARATION + parameter lpm_width = 1; + parameter lpm_widthu = 1; + parameter lpm_numwords = 2; + parameter lpm_showahead = "OFF"; + parameter lpm_type = "scfifo"; + parameter lpm_hint = "USE_EAB=ON"; + parameter intended_device_family = "Stratix"; + parameter underflow_checking = "ON"; + parameter overflow_checking = "ON"; + parameter allow_rwcycle_when_full = "OFF"; + parameter use_eab = "ON"; + parameter add_ram_output_register = "OFF"; + parameter almost_full_value = 0; + parameter almost_empty_value = 0; + parameter maximum_depth = 0; + +// LOCAL_PARAMETERS_BEGIN + + parameter showahead_area = ((lpm_showahead == "ON") && (add_ram_output_register == "OFF")); + parameter showahead_speed = ((lpm_showahead == "ON") && (add_ram_output_register == "ON")); + parameter legacy_speed = ((lpm_showahead == "OFF") && (add_ram_output_register == "ON")); + +// LOCAL_PARAMETERS_END + +// INPUT PORT DECLARATION + input [lpm_width-1:0] data; + input clock; + input wrreq; + input rdreq; + input aclr; + input sclr; + +// OUTPUT PORT DECLARATION + output [lpm_width-1:0] q; + output [lpm_widthu-1:0] usedw; + output full; + output empty; + output almost_full; + output almost_empty; + +// INTERNAL REGISTERS DECLARATION + reg [lpm_width-1:0] mem_data [(1< (1 << lpm_widthu))) + begin + $display ("Error! LPM_NUMWORDS must equal to the ceiling of log2(LPM_WIDTHU)."); + $display ("Time: %0t Instance: %m", $time); + end + if (dev.IS_VALID_FAMILY(intended_device_family) == 0) + begin + $display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family); + $display ("Time: %0t Instance: %m", $time); + end + if((add_ram_output_register != "ON") && (add_ram_output_register != "OFF")) + begin + $display ("Error! add_ram_output_register must be ON or OFF."); + $display ("Time: %0t Instance: %m", $time); + end + for (i = 0; i < (1< 0) + almost_full_flag <= 1'b0; + if (almost_empty_value > 0) + almost_empty_flag <= 1'b1; + + write_id <= 0; + + if ((use_eab == "ON") && (stratix_family) && ((showahead_speed) || (showahead_area) || (legacy_speed))) + begin + write_latency1 <= 1'bx; + write_latency2 <= 1'bx; + data_shown <= {lpm_width{1'b0}}; + if (add_ram_output_register == "ON") + tmp_q <= {lpm_width{1'b0}}; + else + tmp_q <= {lpm_width{1'bX}}; + end + end + else + begin + if (sclr) + begin + if (add_ram_output_register == "ON") + tmp_q <= {lpm_width{1'b0}}; + else + tmp_q <= {lpm_width{1'bX}}; + + read_id <= 0; + count_id <= 0; + full_flag <= 1'b0; + empty_flag <= 1'b1; + empty_latency1 <= 1'b1; + empty_latency2 <= 1'b1; + set_q_to_x <= 1'b0; + set_q_to_x_by_empty <= 1'b0; + wrt_count <= 0; + + if (almost_full_value > 0) + almost_full_flag <= 1'b0; + if (almost_empty_value > 0) + almost_empty_flag <= 1'b1; + + if (!stratix_family) + begin + if (valid_wreq) + begin + write_flag <= 1'b1; + end + else + write_id <= 0; + end + else + begin + write_id <= 0; + end + + if ((use_eab == "ON") && (stratix_family) && ((showahead_speed) || (showahead_area) || (legacy_speed))) + begin + write_latency1 <= 1'bx; + write_latency2 <= 1'bx; + data_shown <= {lpm_width{1'b0}}; + if (add_ram_output_register == "ON") + tmp_q <= {lpm_width{1'b0}}; + else + tmp_q <= {lpm_width{1'bX}}; + end + end + else + begin + //READ operation + if (valid_rreq) + begin + if (!(set_q_to_x || set_q_to_x_by_empty)) + begin + if (!valid_wreq) + wrt_count <= wrt_count - 1; + + if (!valid_wreq) + begin + full_flag <= 1'b0; + + if (count_id <= 0) + count_id <= {lpm_widthu{1'b1}}; + else + count_id <= count_id - 1; + end + + if ((use_eab == "ON") && stratix_family && (showahead_speed || showahead_area || legacy_speed)) + begin + if ((wrt_count == 1 && valid_rreq && !valid_wreq) || ((wrt_count == 1 ) && valid_wreq && valid_rreq)) + begin + empty_flag <= 1'b1; + end + else + begin + if (showahead_speed) + begin + if (data_shown[write_latency2] == 1'b0) + begin + empty_flag <= 1'b1; + end + end + else if (showahead_area || legacy_speed) + begin + if (data_shown[write_latency1] == 1'b0) + begin + empty_flag <= 1'b1; + end + end + end + end + else + begin + if (!valid_wreq) + begin + if ((count_id == 1) && !(full_flag)) + empty_flag <= 1'b1; + end + end + + if (empty_flag) + begin + if (underflow_checking == "ON") + begin + if ((use_eab == "OFF") || (!stratix_family)) + tmp_q <= {lpm_width{1'b0}}; + end + else + begin + set_q_to_x_by_empty <= 1'b1; + $display ("Warning : Underflow occurred! Fifo output is unknown until the next reset is asserted."); + $display ("Time: %0t Instance: %m", $time); + end + end + else if (read_id >= ((1<= ((1<= (1 << lpm_widthu) - 1) + count_id <= 0; + else + count_id <= count_id + 1; + end + else + begin + if (allow_rwcycle_when_full == "OFF") + full_flag <= 1'b0; + end + + if (!(stratix_family) || (stratix_family && !(showahead_speed || showahead_area || legacy_speed))) + begin + if (!valid_rreq) + if ((count_id == lpm_numwords - 1) && (empty_flag == 1'b0)) + full_flag <= 1'b1; + end + else + begin + if (!valid_rreq) + if (count_id == lpm_numwords - 1) + full_flag <= 1'b1; + end + + if (lpm_showahead == "ON") + begin + if ((use_eab == "ON") && stratix_family && (showahead_speed || showahead_area)) + begin + write_latency1 <= write_id; + data_shown[write_id] <= 1'b1; + data_ready[write_id] <= 1'bx; + end + else + begin + if ((use_eab == "OFF") && stratix_family && (count_id == 0) && (!full_flag)) + begin + tmp_q <= data; + end + else + begin + if ((!empty_flag) && (!valid_rreq)) + begin + tmp_q <= mem_data[read_id]; + end + end + end + end + else + begin + if ((use_eab == "ON") && stratix_family && legacy_speed) + begin + write_latency1 <= write_id; + data_shown[write_id] <= 1'b1; + data_ready[write_id] <= 1'bx; + end + end + end + end + end + + if (almost_full_value == 0) + almost_full_flag <= 1'b1; + else if (lpm_numwords > almost_full_value) + begin + if (almost_full_flag) + begin + if ((count_id == almost_full_value) && !wrreq && rdreq) + almost_full_flag <= 1'b0; + end + else + begin + if ((almost_full_value == 1) && (count_id == 0) && wrreq) + almost_full_flag <= 1'b1; + else if ((almost_full_value > 1) && (count_id == almost_full_value - 1) + && wrreq && !rdreq) + almost_full_flag <= 1'b1; + end + end + + if (almost_empty_value == 0) + almost_empty_flag <= 1'b0; + else if (lpm_numwords > almost_empty_value) + begin + if (almost_empty_flag) + begin + if ((almost_empty_value == 1) && (count_id == 0) && wrreq) + almost_empty_flag <= 1'b0; + else if ((almost_empty_value > 1) && (count_id == almost_empty_value - 1) + && wrreq && !rdreq) + almost_empty_flag <= 1'b0; + end + else + begin + if ((count_id == almost_empty_value) && !wrreq && rdreq) + almost_empty_flag <= 1'b1; + end + end + end + + if ((use_eab == "ON") && stratix_family) + begin + if (showahead_speed) + begin + write_latency2 <= write_latency1; + write_latency3 <= write_latency2; + if (write_latency3 !== write_latency2) + data_ready[write_latency2] <= 1'b1; + + empty_latency2 <= empty_latency1; + + if (data_shown[write_latency2]==1'b1) + begin + if ((read_id == write_latency2) || aclr || sclr) + begin + if (!(aclr === 1'b1) && !(sclr === 1'b1)) + begin + if (write_latency2 !== 1'bx) + begin + tmp_q <= mem_data[write_latency2]; + data_shown[write_latency2] <= 1'b0; + data_ready[write_latency2] <= 1'b0; + + if (!valid_rreq) + empty_flag <= empty_latency2; + end + end + end + end + end + else if (showahead_area) + begin + write_latency2 <= write_latency1; + if (write_latency2 !== write_latency1) + data_ready[write_latency1] <= 1'b1; + + if (data_shown[write_latency1]==1'b1) + begin + if ((read_id == write_latency1) || aclr || sclr) + begin + if (!(aclr === 1'b1) && !(sclr === 1'b1)) + begin + if (write_latency1 !== 1'bx) + begin + tmp_q <= mem_data[write_latency1]; + data_shown[write_latency1] <= 1'b0; + data_ready[write_latency1] <= 1'b0; + + if (!valid_rreq) + begin + empty_flag <= empty_latency1; + end + end + end + end + end + end + else + begin + if (legacy_speed) + begin + write_latency2 <= write_latency1; + if (write_latency2 !== write_latency1) + data_ready[write_latency1] <= 1'b1; + + empty_flag <= empty_latency1; + + if ((wrt_count == 1 && !valid_wreq && valid_rreq) || aclr || sclr) + begin + empty_flag <= 1'b1; + empty_latency1 <= 1'b1; + end + else + begin + if ((wrt_count == 1) && valid_wreq && valid_rreq) + begin + empty_flag <= 1'b1; + end + end + end + end + end + end + end + + always @(negedge clock) + begin + if (write_flag) + begin + write_flag <= 1'b0; + + if (sclr || aclr || (write_id >= ((1 << lpm_widthu) - 1))) + write_id <= 0; + else + write_id <= write_id + 1; + end + + if (!(stratix_family)) + begin + if (!empty) + begin + if ((lpm_showahead == "ON") && ($time > 0)) + tmp_q <= mem_data[read_id]; + end + end + end + + always @(full_flag) + begin + if (lpm_numwords == almost_full_value) + if (full_flag) + almost_full_flag = 1'b1; + else + almost_full_flag = 1'b0; + + if (lpm_numwords == almost_empty_value) + if (full_flag) + almost_empty_flag = 1'b0; + else + almost_empty_flag = 1'b1; + end + +// CONTINOUS ASSIGNMENT + assign q = (set_q_to_x || set_q_to_x_by_empty)? {lpm_width{1'bX}} : tmp_q; + assign full = (set_q_to_x || set_q_to_x_by_empty)? 1'bX : full_flag; + assign empty = (set_q_to_x || set_q_to_x_by_empty)? 1'bX : empty_flag; + assign usedw = (set_q_to_x || set_q_to_x_by_empty)? {lpm_widthu{1'bX}} : count_id; + assign almost_full = (set_q_to_x || set_q_to_x_by_empty)? 1'bX : almost_full_flag; + assign almost_empty = (set_q_to_x || set_q_to_x_by_empty)? 1'bX : almost_empty_flag; + +endmodule // scfifo +// END OF MODULE + + + +//START_MODULE_NAME------------------------------------------------------------ +// +// Module Name : ALTERA_DEVICE_FAMILIES +// +// Description : Common Altera device families comparison +// +// Limitation : +// +// Results expected: +// +//END_MODULE_NAME-------------------------------------------------------------- + +// BEGINNING OF MODULE +`timescale 1 ps / 1 ps + +// MODULE DECLARATION +module ALTERA_DEVICE_FAMILIES; + +function IS_FAMILY_STRATIX; + input[8*20:1] device; + reg is_stratix; +begin + if ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager")) + is_stratix = 1; + else + is_stratix = 0; + + IS_FAMILY_STRATIX = is_stratix; +end +endfunction //IS_FAMILY_STRATIX + +function IS_FAMILY_STRATIXGX; + input[8*20:1] device; + reg is_stratixgx; +begin + if ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora")) + is_stratixgx = 1; + else + is_stratixgx = 0; + + IS_FAMILY_STRATIXGX = is_stratixgx; +end +endfunction //IS_FAMILY_STRATIXGX + +function IS_FAMILY_CYCLONE; + input[8*20:1] device; + reg is_cyclone; +begin + if ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado")) + is_cyclone = 1; + else + is_cyclone = 0; + + IS_FAMILY_CYCLONE = is_cyclone; +end +endfunction //IS_FAMILY_CYCLONE + +function IS_FAMILY_MAXII; + input[8*20:1] device; + reg is_maxii; +begin + if ((device == "MAX II") || (device == "max ii") || (device == "MAXII") || (device == "maxii") || (device == "Tsunami") || (device == "TSUNAMI") || (device == "tsunami")) + is_maxii = 1; + else + is_maxii = 0; + + IS_FAMILY_MAXII = is_maxii; +end +endfunction //IS_FAMILY_MAXII + +function IS_FAMILY_STRATIXII; + input[8*20:1] device; + reg is_stratixii; +begin + if ((device == "Stratix II") || (device == "STRATIX II") || (device == "stratix ii") || (device == "StratixII") || (device == "STRATIXII") || (device == "stratixii") || (device == "Armstrong") || (device == "ARMSTRONG") || (device == "armstrong")) + is_stratixii = 1; + else + is_stratixii = 0; + + IS_FAMILY_STRATIXII = is_stratixii; +end +endfunction //IS_FAMILY_STRATIXII + +function IS_FAMILY_STRATIXIIGX; + input[8*20:1] device; + reg is_stratixiigx; +begin + if ((device == "Stratix II GX") || (device == "STRATIX II GX") || (device == "stratix ii gx") || (device == "StratixIIGX") || (device == "STRATIXIIGX") || (device == "stratixiigx")) + is_stratixiigx = 1; + else + is_stratixiigx = 0; + + IS_FAMILY_STRATIXIIGX = is_stratixiigx; +end +endfunction //IS_FAMILY_STRATIXIIGX + +function IS_FAMILY_ARRIAGX; + input[8*20:1] device; + reg is_arriagx; +begin + if ((device == "Arria GX") || (device == "ARRIA GX") || (device == "arria gx") || (device == "ArriaGX") || (device == "ARRIAGX") || (device == "arriagx") || (device == "Stratix II GX Lite") || (device == "STRATIX II GX LITE") || (device == "stratix ii gx lite") || (device == "StratixIIGXLite") || (device == "STRATIXIIGXLITE") || (device == "stratixiigxlite")) + is_arriagx = 1; + else + is_arriagx = 0; + + IS_FAMILY_ARRIAGX = is_arriagx; +end +endfunction //IS_FAMILY_ARRIAGX + +function IS_FAMILY_CYCLONEII; + input[8*20:1] device; + reg is_cycloneii; +begin + if ((device == "Cyclone II") || (device == "CYCLONE II") || (device == "cyclone ii") || (device == "Cycloneii") || (device == "CYCLONEII") || (device == "cycloneii") || (device == "Magellan") || (device == "MAGELLAN") || (device == "magellan")) + is_cycloneii = 1; + else + is_cycloneii = 0; + + IS_FAMILY_CYCLONEII = is_cycloneii; +end +endfunction //IS_FAMILY_CYCLONEII + +function IS_FAMILY_HARDCOPYII; + input[8*20:1] device; + reg is_hardcopyii; +begin + if ((device == "HardCopy II") || (device == "HARDCOPY II") || (device == "hardcopy ii") || (device == "HardCopyII") || (device == "HARDCOPYII") || (device == "hardcopyii") || (device == "Fusion") || (device == "FUSION") || (device == "fusion")) + is_hardcopyii = 1; + else + is_hardcopyii = 0; + + IS_FAMILY_HARDCOPYII = is_hardcopyii; +end +endfunction //IS_FAMILY_HARDCOPYII + +function IS_FAMILY_STRATIXIII; + input[8*20:1] device; + reg is_stratixiii; +begin + if ((device == "Stratix III") || (device == "STRATIX III") || (device == "stratix iii") || (device == "StratixIII") || (device == "STRATIXIII") || (device == "stratixiii") || (device == "Titan") || (device == "TITAN") || (device == "titan") || (device == "SIII") || (device == "siii")) + is_stratixiii = 1; + else + is_stratixiii = 0; + + IS_FAMILY_STRATIXIII = is_stratixiii; +end +endfunction //IS_FAMILY_STRATIXIII + +function IS_FAMILY_CYCLONEIII; + input[8*20:1] device; + reg is_cycloneiii; +begin + if ((device == "Cyclone III") || (device == "CYCLONE III") || (device == "cyclone iii") || (device == "CycloneIII") || (device == "CYCLONEIII") || (device == "cycloneiii") || (device == "Barracuda") || (device == "BARRACUDA") || (device == "barracuda") || (device == "Cuda") || (device == "CUDA") || (device == "cuda") || (device == "CIII") || (device == "ciii")) + is_cycloneiii = 1; + else + is_cycloneiii = 0; + + IS_FAMILY_CYCLONEIII = is_cycloneiii; +end +endfunction //IS_FAMILY_CYCLONEIII + +function IS_FAMILY_STRATIXIV; + input[8*20:1] device; + reg is_stratixiv; +begin + if ((device == "Stratix IV") || (device == "STRATIX IV") || (device == "stratix iv") || (device == "TGX") || (device == "tgx") || (device == "StratixIV") || (device == "STRATIXIV") || (device == "stratixiv") || (device == "Stratix IV (GT)") || (device == "STRATIX IV (GT)") || (device == "stratix iv (gt)") || (device == "Stratix IV (GX)") || (device == "STRATIX IV (GX)") || (device == "stratix iv (gx)") || (device == "Stratix IV (E)") || (device == "STRATIX IV (E)") || (device == "stratix iv (e)") || (device == "StratixIV(GT)") || (device == "STRATIXIV(GT)") || (device == "stratixiv(gt)") || (device == "StratixIV(GX)") || (device == "STRATIXIV(GX)") || (device == "stratixiv(gx)") || (device == "StratixIV(E)") || (device == "STRATIXIV(E)") || (device == "stratixiv(e)") || (device == "StratixIIIGX") || (device == "STRATIXIIIGX") || (device == "stratixiiigx") || (device == "Stratix IV (GT/GX/E)") || (device == "STRATIX IV (GT/GX/E)") || (device == "stratix iv (gt/gx/e)") || (device == "Stratix IV (GT/E/GX)") || (device == "STRATIX IV (GT/E/GX)") || (device == "stratix iv (gt/e/gx)") || (device == "Stratix IV (E/GT/GX)") || (device == "STRATIX IV (E/GT/GX)") || (device == "stratix iv (e/gt/gx)") || (device == "Stratix IV (E/GX/GT)") || (device == "STRATIX IV (E/GX/GT)") || (device == "stratix iv (e/gx/gt)") || (device == "StratixIV(GT/GX/E)") || (device == "STRATIXIV(GT/GX/E)") || (device == "stratixiv(gt/gx/e)") || (device == "StratixIV(GT/E/GX)") || (device == "STRATIXIV(GT/E/GX)") || (device == "stratixiv(gt/e/gx)") || (device == "StratixIV(E/GX/GT)") || (device == "STRATIXIV(E/GX/GT)") || (device == "stratixiv(e/gx/gt)") || (device == "StratixIV(E/GT/GX)") || (device == "STRATIXIV(E/GT/GX)") || (device == "stratixiv(e/gt/gx)") || (device == "Stratix IV (GX/E)") || (device == "STRATIX IV (GX/E)") || (device == "stratix iv (gx/e)") || (device == "StratixIV(GX/E)") || (device == "STRATIXIV(GX/E)") || (device == "stratixiv(gx/e)")) + is_stratixiv = 1; + else + is_stratixiv = 0; + + IS_FAMILY_STRATIXIV = is_stratixiv; +end +endfunction //IS_FAMILY_STRATIXIV + +function IS_FAMILY_ARRIAIIGX; + input[8*20:1] device; + reg is_arriaiigx; +begin + if ((device == "Arria II GX") || (device == "ARRIA II GX") || (device == "arria ii gx") || (device == "ArriaIIGX") || (device == "ARRIAIIGX") || (device == "arriaiigx") || (device == "Arria IIGX") || (device == "ARRIA IIGX") || (device == "arria iigx") || (device == "ArriaII GX") || (device == "ARRIAII GX") || (device == "arriaii gx") || (device == "Arria II") || (device == "ARRIA II") || (device == "arria ii") || (device == "ArriaII") || (device == "ARRIAII") || (device == "arriaii") || (device == "Arria II (GX/E)") || (device == "ARRIA II (GX/E)") || (device == "arria ii (gx/e)") || (device == "ArriaII(GX/E)") || (device == "ARRIAII(GX/E)") || (device == "arriaii(gx/e)") || (device == "PIRANHA") || (device == "piranha")) + is_arriaiigx = 1; + else + is_arriaiigx = 0; + + IS_FAMILY_ARRIAIIGX = is_arriaiigx; +end +endfunction //IS_FAMILY_ARRIAIIGX + +function IS_FAMILY_HARDCOPYIII; + input[8*20:1] device; + reg is_hardcopyiii; +begin + if ((device == "HardCopy III") || (device == "HARDCOPY III") || (device == "hardcopy iii") || (device == "HardCopyIII") || (device == "HARDCOPYIII") || (device == "hardcopyiii") || (device == "HCX") || (device == "hcx")) + is_hardcopyiii = 1; + else + is_hardcopyiii = 0; + + IS_FAMILY_HARDCOPYIII = is_hardcopyiii; +end +endfunction //IS_FAMILY_HARDCOPYIII + +function IS_FAMILY_HARDCOPYIV; + input[8*20:1] device; + reg is_hardcopyiv; +begin + if ((device == "HardCopy IV") || (device == "HARDCOPY IV") || (device == "hardcopy iv") || (device == "HardCopyIV") || (device == "HARDCOPYIV") || (device == "hardcopyiv") || (device == "HardCopy IV (GX)") || (device == "HARDCOPY IV (GX)") || (device == "hardcopy iv (gx)") || (device == "HardCopy IV (E)") || (device == "HARDCOPY IV (E)") || (device == "hardcopy iv (e)") || (device == "HardCopyIV(GX)") || (device == "HARDCOPYIV(GX)") || (device == "hardcopyiv(gx)") || (device == "HardCopyIV(E)") || (device == "HARDCOPYIV(E)") || (device == "hardcopyiv(e)") || (device == "HCXIV") || (device == "hcxiv") || (device == "HardCopy IV (GX/E)") || (device == "HARDCOPY IV (GX/E)") || (device == "hardcopy iv (gx/e)") || (device == "HardCopy IV (E/GX)") || (device == "HARDCOPY IV (E/GX)") || (device == "hardcopy iv (e/gx)") || (device == "HardCopyIV(GX/E)") || (device == "HARDCOPYIV(GX/E)") || (device == "hardcopyiv(gx/e)") || (device == "HardCopyIV(E/GX)") || (device == "HARDCOPYIV(E/GX)") || (device == "hardcopyiv(e/gx)")) + is_hardcopyiv = 1; + else + is_hardcopyiv = 0; + + IS_FAMILY_HARDCOPYIV = is_hardcopyiv; +end +endfunction //IS_FAMILY_HARDCOPYIV + +function IS_FAMILY_CYCLONEIIILS; + input[8*20:1] device; + reg is_cycloneiiils; +begin + if ((device == "Cyclone III LS") || (device == "CYCLONE III LS") || (device == "cyclone iii ls") || (device == "CycloneIIILS") || (device == "CYCLONEIIILS") || (device == "cycloneiiils") || (device == "Cyclone III LPS") || (device == "CYCLONE III LPS") || (device == "cyclone iii lps") || (device == "Cyclone LPS") || (device == "CYCLONE LPS") || (device == "cyclone lps") || (device == "CycloneLPS") || (device == "CYCLONELPS") || (device == "cyclonelps") || (device == "Tarpon") || (device == "TARPON") || (device == "tarpon") || (device == "Cyclone IIIE") || (device == "CYCLONE IIIE") || (device == "cyclone iiie")) + is_cycloneiiils = 1; + else + is_cycloneiiils = 0; + + IS_FAMILY_CYCLONEIIILS = is_cycloneiiils; +end +endfunction //IS_FAMILY_CYCLONEIIILS + +function IS_FAMILY_CYCLONEIVGX; + input[8*20:1] device; + reg is_cycloneivgx; +begin + if ((device == "Cyclone IV GX") || (device == "CYCLONE IV GX") || (device == "cyclone iv gx") || (device == "Cyclone IVGX") || (device == "CYCLONE IVGX") || (device == "cyclone ivgx") || (device == "CycloneIV GX") || (device == "CYCLONEIV GX") || (device == "cycloneiv gx") || (device == "CycloneIVGX") || (device == "CYCLONEIVGX") || (device == "cycloneivgx") || (device == "Cyclone IV") || (device == "CYCLONE IV") || (device == "cyclone iv") || (device == "CycloneIV") || (device == "CYCLONEIV") || (device == "cycloneiv") || (device == "Cyclone IV (GX)") || (device == "CYCLONE IV (GX)") || (device == "cyclone iv (gx)") || (device == "CycloneIV(GX)") || (device == "CYCLONEIV(GX)") || (device == "cycloneiv(gx)") || (device == "Cyclone III GX") || (device == "CYCLONE III GX") || (device == "cyclone iii gx") || (device == "CycloneIII GX") || (device == "CYCLONEIII GX") || (device == "cycloneiii gx") || (device == "Cyclone IIIGX") || (device == "CYCLONE IIIGX") || (device == "cyclone iiigx") || (device == "CycloneIIIGX") || (device == "CYCLONEIIIGX") || (device == "cycloneiiigx") || (device == "Cyclone III GL") || (device == "CYCLONE III GL") || (device == "cyclone iii gl") || (device == "CycloneIII GL") || (device == "CYCLONEIII GL") || (device == "cycloneiii gl") || (device == "Cyclone IIIGL") || (device == "CYCLONE IIIGL") || (device == "cyclone iiigl") || (device == "CycloneIIIGL") || (device == "CYCLONEIIIGL") || (device == "cycloneiiigl") || (device == "Stingray") || (device == "STINGRAY") || (device == "stingray")) + is_cycloneivgx = 1; + else + is_cycloneivgx = 0; + + IS_FAMILY_CYCLONEIVGX = is_cycloneivgx; +end +endfunction //IS_FAMILY_CYCLONEIVGX + +function IS_FAMILY_CYCLONEIVE; + input[8*20:1] device; + reg is_cycloneive; +begin + if ((device == "Cyclone IV E") || (device == "CYCLONE IV E") || (device == "cyclone iv e") || (device == "CycloneIV E") || (device == "CYCLONEIV E") || (device == "cycloneiv e") || (device == "Cyclone IVE") || (device == "CYCLONE IVE") || (device == "cyclone ive") || (device == "CycloneIVE") || (device == "CYCLONEIVE") || (device == "cycloneive")) + is_cycloneive = 1; + else + is_cycloneive = 0; + + IS_FAMILY_CYCLONEIVE = is_cycloneive; +end +endfunction //IS_FAMILY_CYCLONEIVE + +function IS_FAMILY_STRATIXV; + input[8*20:1] device; + reg is_stratixv; +begin + if ((device == "Stratix V") || (device == "STRATIX V") || (device == "stratix v") || (device == "StratixV") || (device == "STRATIXV") || (device == "stratixv") || (device == "Stratix V (GS)") || (device == "STRATIX V (GS)") || (device == "stratix v (gs)") || (device == "StratixV(GS)") || (device == "STRATIXV(GS)") || (device == "stratixv(gs)") || (device == "Stratix V (GX)") || (device == "STRATIX V (GX)") || (device == "stratix v (gx)") || (device == "StratixV(GX)") || (device == "STRATIXV(GX)") || (device == "stratixv(gx)") || (device == "Stratix V (GS/GX)") || (device == "STRATIX V (GS/GX)") || (device == "stratix v (gs/gx)") || (device == "StratixV(GS/GX)") || (device == "STRATIXV(GS/GX)") || (device == "stratixv(gs/gx)") || (device == "Stratix V (GX/GS)") || (device == "STRATIX V (GX/GS)") || (device == "stratix v (gx/gs)") || (device == "StratixV(GX/GS)") || (device == "STRATIXV(GX/GS)") || (device == "stratixv(gx/gs)")) + is_stratixv = 1; + else + is_stratixv = 0; + + IS_FAMILY_STRATIXV = is_stratixv; +end +endfunction //IS_FAMILY_STRATIXV + +function IS_FAMILY_ARRIAIIGZ; + input[8*20:1] device; + reg is_arriaiigz; +begin + if ((device == "Arria II GZ") || (device == "ARRIA II GZ") || (device == "arria ii gz") || (device == "ArriaII GZ") || (device == "ARRIAII GZ") || (device == "arriaii gz") || (device == "Arria IIGZ") || (device == "ARRIA IIGZ") || (device == "arria iigz") || (device == "ArriaIIGZ") || (device == "ARRIAIIGZ") || (device == "arriaiigz")) + is_arriaiigz = 1; + else + is_arriaiigz = 0; + + IS_FAMILY_ARRIAIIGZ = is_arriaiigz; +end +endfunction //IS_FAMILY_ARRIAIIGZ + +function IS_FAMILY_MAXV; + input[8*20:1] device; + reg is_maxv; +begin + if ((device == "MAX V") || (device == "max v") || (device == "MAXV") || (device == "maxv") || (device == "Jade") || (device == "JADE") || (device == "jade")) + is_maxv = 1; + else + is_maxv = 0; + + IS_FAMILY_MAXV = is_maxv; +end +endfunction //IS_FAMILY_MAXV + +function FEATURE_FAMILY_STRATIXGX; + input[8*20:1] device; + reg var_family_stratixgx; +begin + if (IS_FAMILY_STRATIXGX(device) ) + var_family_stratixgx = 1; + else + var_family_stratixgx = 0; + + FEATURE_FAMILY_STRATIXGX = var_family_stratixgx; +end +endfunction //FEATURE_FAMILY_STRATIXGX + +function FEATURE_FAMILY_CYCLONE; + input[8*20:1] device; + reg var_family_cyclone; +begin + if (IS_FAMILY_CYCLONE(device) ) + var_family_cyclone = 1; + else + var_family_cyclone = 0; + + FEATURE_FAMILY_CYCLONE = var_family_cyclone; +end +endfunction //FEATURE_FAMILY_CYCLONE + +function FEATURE_FAMILY_STRATIXIIGX; + input[8*20:1] device; + reg var_family_stratixiigx; +begin + if (IS_FAMILY_STRATIXIIGX(device) || IS_FAMILY_ARRIAGX(device) ) + var_family_stratixiigx = 1; + else + var_family_stratixiigx = 0; + + FEATURE_FAMILY_STRATIXIIGX = var_family_stratixiigx; +end +endfunction //FEATURE_FAMILY_STRATIXIIGX + +function FEATURE_FAMILY_STRATIXIII; + input[8*20:1] device; + reg var_family_stratixiii; +begin + if (IS_FAMILY_STRATIXIII(device) || FEATURE_FAMILY_STRATIXIV(device) || IS_FAMILY_HARDCOPYIII(device) ) + var_family_stratixiii = 1; + else + var_family_stratixiii = 0; + + FEATURE_FAMILY_STRATIXIII = var_family_stratixiii; +end +endfunction //FEATURE_FAMILY_STRATIXIII + +function FEATURE_FAMILY_STRATIXV; + input[8*20:1] device; + reg var_family_stratixv; +begin + if (IS_FAMILY_STRATIXV(device) ) + var_family_stratixv = 1; + else + var_family_stratixv = 0; + + FEATURE_FAMILY_STRATIXV = var_family_stratixv; +end +endfunction //FEATURE_FAMILY_STRATIXV + +function FEATURE_FAMILY_STRATIXII; + input[8*20:1] device; + reg var_family_stratixii; +begin + if (IS_FAMILY_STRATIXII(device) || IS_FAMILY_HARDCOPYII(device) || FEATURE_FAMILY_STRATIXIIGX(device) || FEATURE_FAMILY_STRATIXIII(device) ) + var_family_stratixii = 1; + else + var_family_stratixii = 0; + + FEATURE_FAMILY_STRATIXII = var_family_stratixii; +end +endfunction //FEATURE_FAMILY_STRATIXII + +function FEATURE_FAMILY_CYCLONEIVGX; + input[8*20:1] device; + reg var_family_cycloneivgx; +begin + if (IS_FAMILY_CYCLONEIVGX(device) || IS_FAMILY_CYCLONEIVGX(device) ) + var_family_cycloneivgx = 1; + else + var_family_cycloneivgx = 0; + + FEATURE_FAMILY_CYCLONEIVGX = var_family_cycloneivgx; +end +endfunction //FEATURE_FAMILY_CYCLONEIVGX + +function FEATURE_FAMILY_CYCLONEIVE; + input[8*20:1] device; + reg var_family_cycloneive; +begin + if (IS_FAMILY_CYCLONEIVE(device) ) + var_family_cycloneive = 1; + else + var_family_cycloneive = 0; + + FEATURE_FAMILY_CYCLONEIVE = var_family_cycloneive; +end +endfunction //FEATURE_FAMILY_CYCLONEIVE + +function FEATURE_FAMILY_CYCLONEIII; + input[8*20:1] device; + reg var_family_cycloneiii; +begin + if (IS_FAMILY_CYCLONEIII(device) || IS_FAMILY_CYCLONEIIILS(device) || FEATURE_FAMILY_CYCLONEIVGX(device) || FEATURE_FAMILY_CYCLONEIVE(device) ) + var_family_cycloneiii = 1; + else + var_family_cycloneiii = 0; + + FEATURE_FAMILY_CYCLONEIII = var_family_cycloneiii; +end +endfunction //FEATURE_FAMILY_CYCLONEIII + +function FEATURE_FAMILY_STRATIX_HC; + input[8*20:1] device; + reg var_family_stratix_hc; +begin + if ((device == "StratixHC") ) + var_family_stratix_hc = 1; + else + var_family_stratix_hc = 0; + + FEATURE_FAMILY_STRATIX_HC = var_family_stratix_hc; +end +endfunction //FEATURE_FAMILY_STRATIX_HC + +function FEATURE_FAMILY_STRATIX; + input[8*20:1] device; + reg var_family_stratix; +begin + if (IS_FAMILY_STRATIX(device) || FEATURE_FAMILY_STRATIX_HC(device) || FEATURE_FAMILY_STRATIXGX(device) || FEATURE_FAMILY_CYCLONE(device) || FEATURE_FAMILY_STRATIXII(device) || FEATURE_FAMILY_MAXII(device) || FEATURE_FAMILY_CYCLONEII(device) ) + var_family_stratix = 1; + else + var_family_stratix = 0; + + FEATURE_FAMILY_STRATIX = var_family_stratix; +end +endfunction //FEATURE_FAMILY_STRATIX + +function FEATURE_FAMILY_MAXII; + input[8*20:1] device; + reg var_family_maxii; +begin + if (IS_FAMILY_MAXII(device) || FEATURE_FAMILY_MAXV(device) ) + var_family_maxii = 1; + else + var_family_maxii = 0; + + FEATURE_FAMILY_MAXII = var_family_maxii; +end +endfunction //FEATURE_FAMILY_MAXII + +function FEATURE_FAMILY_MAXV; + input[8*20:1] device; + reg var_family_maxv; +begin + if (IS_FAMILY_MAXV(device) ) + var_family_maxv = 1; + else + var_family_maxv = 0; + + FEATURE_FAMILY_MAXV = var_family_maxv; +end +endfunction //FEATURE_FAMILY_MAXV + +function FEATURE_FAMILY_CYCLONEII; + input[8*20:1] device; + reg var_family_cycloneii; +begin + if (IS_FAMILY_CYCLONEII(device) || FEATURE_FAMILY_CYCLONEIII(device) ) + var_family_cycloneii = 1; + else + var_family_cycloneii = 0; + + FEATURE_FAMILY_CYCLONEII = var_family_cycloneii; +end +endfunction //FEATURE_FAMILY_CYCLONEII + +function FEATURE_FAMILY_STRATIXIV; + input[8*20:1] device; + reg var_family_stratixiv; +begin + if (IS_FAMILY_STRATIXIV(device) || IS_FAMILY_ARRIAIIGX(device) || IS_FAMILY_HARDCOPYIV(device) || FEATURE_FAMILY_STRATIXV(device) || FEATURE_FAMILY_ARRIAIIGZ(device) ) + var_family_stratixiv = 1; + else + var_family_stratixiv = 0; + + FEATURE_FAMILY_STRATIXIV = var_family_stratixiv; +end +endfunction //FEATURE_FAMILY_STRATIXIV + +function FEATURE_FAMILY_ARRIAIIGZ; + input[8*20:1] device; + reg var_family_arriaiigz; +begin + if (IS_FAMILY_ARRIAIIGZ(device) ) + var_family_arriaiigz = 1; + else + var_family_arriaiigz = 0; + + FEATURE_FAMILY_ARRIAIIGZ = var_family_arriaiigz; +end +endfunction //FEATURE_FAMILY_ARRIAIIGZ + +function FEATURE_FAMILY_ARRIAIIGX; + input[8*20:1] device; + reg var_family_arriaiigx; +begin + if (IS_FAMILY_ARRIAIIGX(device) ) + var_family_arriaiigx = 1; + else + var_family_arriaiigx = 0; + + FEATURE_FAMILY_ARRIAIIGX = var_family_arriaiigx; +end +endfunction //FEATURE_FAMILY_ARRIAIIGX + +function FEATURE_FAMILY_BASE_STRATIXII; + input[8*20:1] device; + reg var_family_base_stratixii; +begin + if (IS_FAMILY_STRATIXII(device) || IS_FAMILY_HARDCOPYII(device) || FEATURE_FAMILY_STRATIXIIGX(device) ) + var_family_base_stratixii = 1; + else + var_family_base_stratixii = 0; + + FEATURE_FAMILY_BASE_STRATIXII = var_family_base_stratixii; +end +endfunction //FEATURE_FAMILY_BASE_STRATIXII + +function FEATURE_FAMILY_BASE_STRATIX; + input[8*20:1] device; + reg var_family_base_stratix; +begin + if (IS_FAMILY_STRATIX(device) || IS_FAMILY_STRATIXGX(device) ) + var_family_base_stratix = 1; + else + var_family_base_stratix = 0; + + FEATURE_FAMILY_BASE_STRATIX = var_family_base_stratix; +end +endfunction //FEATURE_FAMILY_BASE_STRATIX + +function FEATURE_FAMILY_BASE_CYCLONEII; + input[8*20:1] device; + reg var_family_base_cycloneii; +begin + if (IS_FAMILY_CYCLONEII(device) ) + var_family_base_cycloneii = 1; + else + var_family_base_cycloneii = 0; + + FEATURE_FAMILY_BASE_CYCLONEII = var_family_base_cycloneii; +end +endfunction //FEATURE_FAMILY_BASE_CYCLONEII + +function FEATURE_FAMILY_BASE_CYCLONE; + input[8*20:1] device; + reg var_family_base_cyclone; +begin + if (IS_FAMILY_CYCLONE(device) ) + var_family_base_cyclone = 1; + else + var_family_base_cyclone = 0; + + FEATURE_FAMILY_BASE_CYCLONE = var_family_base_cyclone; +end +endfunction //FEATURE_FAMILY_BASE_CYCLONE + +function FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM; + input[8*20:1] device; + reg var_family_has_stratixii_style_ram; +begin + if (FEATURE_FAMILY_STRATIXII(device) || FEATURE_FAMILY_CYCLONEII(device) ) + var_family_has_stratixii_style_ram = 1; + else + var_family_has_stratixii_style_ram = 0; + + FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM = var_family_has_stratixii_style_ram; +end +endfunction //FEATURE_FAMILY_HAS_STRATIXII_STYLE_RAM + +function FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM; + input[8*20:1] device; + reg var_family_has_stratixiii_style_ram; +begin + if (FEATURE_FAMILY_STRATIXIII(device) || FEATURE_FAMILY_CYCLONEIII(device) ) + var_family_has_stratixiii_style_ram = 1; + else + var_family_has_stratixiii_style_ram = 0; + + FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM = var_family_has_stratixiii_style_ram; +end +endfunction //FEATURE_FAMILY_HAS_STRATIXIII_STYLE_RAM + +function FEATURE_FAMILY_HAS_STRATIX_STYLE_PLL; + input[8*20:1] device; + reg var_family_has_stratix_style_pll; +begin + if (FEATURE_FAMILY_CYCLONE(device) || FEATURE_FAMILY_STRATIX_HC(device) || IS_FAMILY_STRATIX(device) || FEATURE_FAMILY_STRATIXGX(device) ) + var_family_has_stratix_style_pll = 1; + else + var_family_has_stratix_style_pll = 0; + + FEATURE_FAMILY_HAS_STRATIX_STYLE_PLL = var_family_has_stratix_style_pll; +end +endfunction //FEATURE_FAMILY_HAS_STRATIX_STYLE_PLL + +function FEATURE_FAMILY_HAS_STRATIXII_STYLE_PLL; + input[8*20:1] device; + reg var_family_has_stratixii_style_pll; +begin + if (FEATURE_FAMILY_STRATIXII(device) && ! FEATURE_FAMILY_STRATIXIII(device) || FEATURE_FAMILY_CYCLONEII(device) && ! FEATURE_FAMILY_CYCLONEIII(device) ) + var_family_has_stratixii_style_pll = 1; + else + var_family_has_stratixii_style_pll = 0; + + FEATURE_FAMILY_HAS_STRATIXII_STYLE_PLL = var_family_has_stratixii_style_pll; +end +endfunction //FEATURE_FAMILY_HAS_STRATIXII_STYLE_PLL + +function FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO; + input[8*20:1] device; + reg var_family_has_inverted_output_ddio; +begin + if (FEATURE_FAMILY_CYCLONEII(device) ) + var_family_has_inverted_output_ddio = 1; + else + var_family_has_inverted_output_ddio = 0; + + FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO = var_family_has_inverted_output_ddio; +end +endfunction //FEATURE_FAMILY_HAS_INVERTED_OUTPUT_DDIO + +function IS_VALID_FAMILY; + input[8*20:1] device; + reg is_valid; +begin + if (((device == "MAX7000B") || (device == "max7000b") || (device == "MAX 7000B") || (device == "max 7000b")) + || ((device == "MAX7000AE") || (device == "max7000ae") || (device == "MAX 7000AE") || (device == "max 7000ae")) + || ((device == "MAX3000A") || (device == "max3000a") || (device == "MAX 3000A") || (device == "max 3000a")) + || ((device == "MAX7000S") || (device == "max7000s") || (device == "MAX 7000S") || (device == "max 7000s")) + || ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager")) + || ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora")) + || ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado")) + || ((device == "MAX II") || (device == "max ii") || (device == "MAXII") || (device == "maxii") || (device == "Tsunami") || (device == "TSUNAMI") || (device == "tsunami")) + || ((device == "Stratix II") || (device == "STRATIX II") || (device == "stratix ii") || (device == "StratixII") || (device == "STRATIXII") || (device == "stratixii") || (device == "Armstrong") || (device == "ARMSTRONG") || (device == "armstrong")) + || ((device == "Stratix II GX") || (device == "STRATIX II GX") || (device == "stratix ii gx") || (device == "StratixIIGX") || (device == "STRATIXIIGX") || (device == "stratixiigx")) + || ((device == "Arria GX") || (device == "ARRIA GX") || (device == "arria gx") || (device == "ArriaGX") || (device == "ARRIAGX") || (device == "arriagx") || (device == "Stratix II GX Lite") || (device == "STRATIX II GX LITE") || (device == "stratix ii gx lite") || (device == "StratixIIGXLite") || (device == "STRATIXIIGXLITE") || (device == "stratixiigxlite")) + || ((device == "Cyclone II") || (device == "CYCLONE II") || (device == "cyclone ii") || (device == "Cycloneii") || (device == "CYCLONEII") || (device == "cycloneii") || (device == "Magellan") || (device == "MAGELLAN") || (device == "magellan")) + || ((device == "HardCopy II") || (device == "HARDCOPY II") || (device == "hardcopy ii") || (device == "HardCopyII") || (device == "HARDCOPYII") || (device == "hardcopyii") || (device == "Fusion") || (device == "FUSION") || (device == "fusion")) + || ((device == "Stratix III") || (device == "STRATIX III") || (device == "stratix iii") || (device == "StratixIII") || (device == "STRATIXIII") || (device == "stratixiii") || (device == "Titan") || (device == "TITAN") || (device == "titan") || (device == "SIII") || (device == "siii")) + || ((device == "Cyclone III") || (device == "CYCLONE III") || (device == "cyclone iii") || (device == "CycloneIII") || (device == "CYCLONEIII") || (device == "cycloneiii") || (device == "Barracuda") || (device == "BARRACUDA") || (device == "barracuda") || (device == "Cuda") || (device == "CUDA") || (device == "cuda") || (device == "CIII") || (device == "ciii")) + || ((device == "BS") || (device == "bs")) + || ((device == "Stratix IV") || (device == "STRATIX IV") || (device == "stratix iv") || (device == "TGX") || (device == "tgx") || (device == "StratixIV") || (device == "STRATIXIV") || (device == "stratixiv") || (device == "Stratix IV (GT)") || (device == "STRATIX IV (GT)") || (device == "stratix iv (gt)") || (device == "Stratix IV (GX)") || (device == "STRATIX IV (GX)") || (device == "stratix iv (gx)") || (device == "Stratix IV (E)") || (device == "STRATIX IV (E)") || (device == "stratix iv (e)") || (device == "StratixIV(GT)") || (device == "STRATIXIV(GT)") || (device == "stratixiv(gt)") || (device == "StratixIV(GX)") || (device == "STRATIXIV(GX)") || (device == "stratixiv(gx)") || (device == "StratixIV(E)") || (device == "STRATIXIV(E)") || (device == "stratixiv(e)") || (device == "StratixIIIGX") || (device == "STRATIXIIIGX") || (device == "stratixiiigx") || (device == "Stratix IV (GT/GX/E)") || (device == "STRATIX IV (GT/GX/E)") || (device == "stratix iv (gt/gx/e)") || (device == "Stratix IV (GT/E/GX)") || (device == "STRATIX IV (GT/E/GX)") || (device == "stratix iv (gt/e/gx)") || (device == "Stratix IV (E/GT/GX)") || (device == "STRATIX IV (E/GT/GX)") || (device == "stratix iv (e/gt/gx)") || (device == "Stratix IV (E/GX/GT)") || (device == "STRATIX IV (E/GX/GT)") || (device == "stratix iv (e/gx/gt)") || (device == "StratixIV(GT/GX/E)") || (device == "STRATIXIV(GT/GX/E)") || (device == "stratixiv(gt/gx/e)") || (device == "StratixIV(GT/E/GX)") || (device == "STRATIXIV(GT/E/GX)") || (device == "stratixiv(gt/e/gx)") || (device == "StratixIV(E/GX/GT)") || (device == "STRATIXIV(E/GX/GT)") || (device == "stratixiv(e/gx/gt)") || (device == "StratixIV(E/GT/GX)") || (device == "STRATIXIV(E/GT/GX)") || (device == "stratixiv(e/gt/gx)") || (device == "Stratix IV (GX/E)") || (device == "STRATIX IV (GX/E)") || (device == "stratix iv (gx/e)") || (device == "StratixIV(GX/E)") || (device == "STRATIXIV(GX/E)") || (device == "stratixiv(gx/e)")) + || ((device == "tgx_commercial_v1_1") || (device == "TGX_COMMERCIAL_V1_1")) + || ((device == "Arria II GX") || (device == "ARRIA II GX") || (device == "arria ii gx") || (device == "ArriaIIGX") || (device == "ARRIAIIGX") || (device == "arriaiigx") || (device == "Arria IIGX") || (device == "ARRIA IIGX") || (device == "arria iigx") || (device == "ArriaII GX") || (device == "ARRIAII GX") || (device == "arriaii gx") || (device == "Arria II") || (device == "ARRIA II") || (device == "arria ii") || (device == "ArriaII") || (device == "ARRIAII") || (device == "arriaii") || (device == "Arria II (GX/E)") || (device == "ARRIA II (GX/E)") || (device == "arria ii (gx/e)") || (device == "ArriaII(GX/E)") || (device == "ARRIAII(GX/E)") || (device == "arriaii(gx/e)") || (device == "PIRANHA") || (device == "piranha")) + || ((device == "HardCopy III") || (device == "HARDCOPY III") || (device == "hardcopy iii") || (device == "HardCopyIII") || (device == "HARDCOPYIII") || (device == "hardcopyiii") || (device == "HCX") || (device == "hcx")) + || ((device == "HardCopy IV") || (device == "HARDCOPY IV") || (device == "hardcopy iv") || (device == "HardCopyIV") || (device == "HARDCOPYIV") || (device == "hardcopyiv") || (device == "HardCopy IV (GX)") || (device == "HARDCOPY IV (GX)") || (device == "hardcopy iv (gx)") || (device == "HardCopy IV (E)") || (device == "HARDCOPY IV (E)") || (device == "hardcopy iv (e)") || (device == "HardCopyIV(GX)") || (device == "HARDCOPYIV(GX)") || (device == "hardcopyiv(gx)") || (device == "HardCopyIV(E)") || (device == "HARDCOPYIV(E)") || (device == "hardcopyiv(e)") || (device == "HCXIV") || (device == "hcxiv") || (device == "HardCopy IV (GX/E)") || (device == "HARDCOPY IV (GX/E)") || (device == "hardcopy iv (gx/e)") || (device == "HardCopy IV (E/GX)") || (device == "HARDCOPY IV (E/GX)") || (device == "hardcopy iv (e/gx)") || (device == "HardCopyIV(GX/E)") || (device == "HARDCOPYIV(GX/E)") || (device == "hardcopyiv(gx/e)") || (device == "HardCopyIV(E/GX)") || (device == "HARDCOPYIV(E/GX)") || (device == "hardcopyiv(e/gx)")) + || ((device == "Cyclone III LS") || (device == "CYCLONE III LS") || (device == "cyclone iii ls") || (device == "CycloneIIILS") || (device == "CYCLONEIIILS") || (device == "cycloneiiils") || (device == "Cyclone III LPS") || (device == "CYCLONE III LPS") || (device == "cyclone iii lps") || (device == "Cyclone LPS") || (device == "CYCLONE LPS") || (device == "cyclone lps") || (device == "CycloneLPS") || (device == "CYCLONELPS") || (device == "cyclonelps") || (device == "Tarpon") || (device == "TARPON") || (device == "tarpon") || (device == "Cyclone IIIE") || (device == "CYCLONE IIIE") || (device == "cyclone iiie")) + || ((device == "Cyclone IV GX") || (device == "CYCLONE IV GX") || (device == "cyclone iv gx") || (device == "Cyclone IVGX") || (device == "CYCLONE IVGX") || (device == "cyclone ivgx") || (device == "CycloneIV GX") || (device == "CYCLONEIV GX") || (device == "cycloneiv gx") || (device == "CycloneIVGX") || (device == "CYCLONEIVGX") || (device == "cycloneivgx") || (device == "Cyclone IV") || (device == "CYCLONE IV") || (device == "cyclone iv") || (device == "CycloneIV") || (device == "CYCLONEIV") || (device == "cycloneiv") || (device == "Cyclone IV (GX)") || (device == "CYCLONE IV (GX)") || (device == "cyclone iv (gx)") || (device == "CycloneIV(GX)") || (device == "CYCLONEIV(GX)") || (device == "cycloneiv(gx)") || (device == "Cyclone III GX") || (device == "CYCLONE III GX") || (device == "cyclone iii gx") || (device == "CycloneIII GX") || (device == "CYCLONEIII GX") || (device == "cycloneiii gx") || (device == "Cyclone IIIGX") || (device == "CYCLONE IIIGX") || (device == "cyclone iiigx") || (device == "CycloneIIIGX") || (device == "CYCLONEIIIGX") || (device == "cycloneiiigx") || (device == "Cyclone III GL") || (device == "CYCLONE III GL") || (device == "cyclone iii gl") || (device == "CycloneIII GL") || (device == "CYCLONEIII GL") || (device == "cycloneiii gl") || (device == "Cyclone IIIGL") || (device == "CYCLONE IIIGL") || (device == "cyclone iiigl") || (device == "CycloneIIIGL") || (device == "CYCLONEIIIGL") || (device == "cycloneiiigl") || (device == "Stingray") || (device == "STINGRAY") || (device == "stingray")) + || ((device == "Cyclone IV E") || (device == "CYCLONE IV E") || (device == "cyclone iv e") || (device == "CycloneIV E") || (device == "CYCLONEIV E") || (device == "cycloneiv e") || (device == "Cyclone IVE") || (device == "CYCLONE IVE") || (device == "cyclone ive") || (device == "CycloneIVE") || (device == "CYCLONEIVE") || (device == "cycloneive")) + || ((device == "Stratix V") || (device == "STRATIX V") || (device == "stratix v") || (device == "StratixV") || (device == "STRATIXV") || (device == "stratixv") || (device == "Stratix V (GS)") || (device == "STRATIX V (GS)") || (device == "stratix v (gs)") || (device == "StratixV(GS)") || (device == "STRATIXV(GS)") || (device == "stratixv(gs)") || (device == "Stratix V (GX)") || (device == "STRATIX V (GX)") || (device == "stratix v (gx)") || (device == "StratixV(GX)") || (device == "STRATIXV(GX)") || (device == "stratixv(gx)") || (device == "Stratix V (GS/GX)") || (device == "STRATIX V (GS/GX)") || (device == "stratix v (gs/gx)") || (device == "StratixV(GS/GX)") || (device == "STRATIXV(GS/GX)") || (device == "stratixv(gs/gx)") || (device == "Stratix V (GX/GS)") || (device == "STRATIX V (GX/GS)") || (device == "stratix v (gx/gs)") || (device == "StratixV(GX/GS)") || (device == "STRATIXV(GX/GS)") || (device == "stratixv(gx/gs)")) + || ((device == "Arria II GZ") || (device == "ARRIA II GZ") || (device == "arria ii gz") || (device == "ArriaII GZ") || (device == "ARRIAII GZ") || (device == "arriaii gz") || (device == "Arria IIGZ") || (device == "ARRIA IIGZ") || (device == "arria iigz") || (device == "ArriaIIGZ") || (device == "ARRIAIIGZ") || (device == "arriaiigz")) + || ((device == "arriaiigz_commercial_v1_1") || (device == "ARRIAIIGZ_COMMERCIAL_V1_1")) + || ((device == "MAX V") || (device == "max v") || (device == "MAXV") || (device == "maxv") || (device == "Jade") || (device == "JADE") || (device == "jade")) + || ((device == "ArriaV") || (device == "ARRIAV") || (device == "arriav") || (device == "Arria V") || (device == "ARRIA V") || (device == "arria v"))) + is_valid = 1; + else + is_valid = 0; + + IS_VALID_FAMILY = is_valid; +end +endfunction // IS_VALID_FAMILY + + +endmodule // ALTERA_DEVICE_FAMILIES + Index: tags/v2p2/sim/reg_bfm_sv.v =================================================================== --- tags/v2p2/sim/reg_bfm_sv.v (nonexistent) +++ tags/v2p2/sim/reg_bfm_sv.v (revision 16) @@ -0,0 +1,38 @@ +//************************************************************** +// Module : reg_bfm_sv.v +// Platform : Windows xp sp2 +// Simulator : Modelsim 6.5b +// Synthesizer : +// Place and Route : +// Targets device : +// Author : Bibo Yang (ash_riple@hotmail.com) +// Organization : www.opencores.org +// Revision : 2.2 +// Date : 2012/03/28 +// Description : Register BFM +//************************************************************** + +`timescale 1ns/1ns + +module reg_bfm_sv ( + input up_clk, + input up_wbe,up_csn, // negative logic + input [15:0] up_addr, + inout [31:0] up_data_io +); + +wire [31:0] up_data_i; +reg [31:0] up_data_o; + +assign #10 up_data_io = (up_wbe&&!up_csn)? up_data_o : 32'bzzzzzzzz; +assign up_data_i = up_data_io; + +reg [31:0] RAM [0:3]; +always @(posedge up_clk) begin + if (!up_wbe && !up_csn) + RAM[up_addr[3:2]] <= up_data_i; + + up_data_o <= RAM[up_addr[3:2]]; +end + +endmodule Index: tags/v2p2/sim/up_bfm_sv.v =================================================================== --- tags/v2p2/sim/up_bfm_sv.v (nonexistent) +++ tags/v2p2/sim/up_bfm_sv.v (revision 16) @@ -0,0 +1,86 @@ +`timescale 1ns/1ns + +module up_bfm_sv +( + input up_clk, + output up_wbe, + output up_csn, + output [15:2] up_addr, + inout [31:0] up_data_io +); + +import "DPI-C" context task up_bfm_c +( + input real fw_delay +); + +reg [15:0] up_addr_o; +reg [31:0] up_data_o; +wire [31:0] up_data_i; +reg up_wbe_o; +reg up_csn_o; + +export "DPI-C" task cpu_wr; +task cpu_wr(input int addr, input int data); + integer i; + //$display("wr %08x %08x", addr, data); + for (i=0; i<2; i=i+1) @(posedge up_clk); + up_addr_o = addr; + up_data_o = data; + up_wbe_o = 1'b0; + up_csn_o = 1'b0; + for (i=0; i<20; i=i+1) @(posedge up_clk); + up_csn_o = 1'b1; + for (i=0; i<1; i=i+1) @(posedge up_clk); + up_addr_o = addr; + up_data_o = data; + up_wbe_o = 1'b1; + up_csn_o = 1'b1; + for (i=0; i<2; i=i+1) @(posedge up_clk); +endtask + +export "DPI-C" task cpu_rd; +task cpu_rd(input int addr, output int data); + integer i; + for (i=0; i<2; i=i+1) @(posedge up_clk); + up_addr_o = addr; + up_wbe_o = 1'b1; + up_csn_o = 1'b0; + for (i=0; i<20; i=i+1) @(posedge up_clk); + data = up_data_i; + for (i=0; i<1; i=i+1) @(posedge up_clk); + up_addr_o = addr; + up_wbe_o = 1'b1; + up_csn_o = 1'b1; + for (i=0; i<2; i=i+1) @(posedge up_clk); + //$display("rd %08x %08x", addr, data); +endtask + +export "DPI-C" task cpu_hd; +task cpu_hd(input int t); + integer i; + //$display("#%d",t); + for (i=0; i<=t; i=i+1) @(posedge up_clk); +endtask + +assign up_wbe = up_wbe_o; +assign up_csn = up_csn_o; +assign up_addr = up_addr_o[15:2]; +assign up_data_io = !up_wbe_o? up_data_o : 32'bzzzzzzzz; +assign up_data_i = up_data_io; + + + +// start cpu bfm C model +reg up_start; +initial begin + up_wbe_o = 1'b1; + up_csn_o = 1'b1; + up_addr_o = 'd0; + up_data_o = 'd0; + + @(posedge up_start); + #100 up_bfm_c(5); +end + +endmodule Index: tags/v2p2/sim/up_bfm_c.c =================================================================== --- tags/v2p2/sim/up_bfm_c.c (nonexistent) +++ tags/v2p2/sim/up_bfm_c.c (revision 16) @@ -0,0 +1,28 @@ +#include + +#include "svdpi.h" +#include "dpiheader.h" +int up_bfm_c(double fw_delay) +{ + int cpu_addr_i; + int cpu_data_i; + int cpu_data_o; + + int t; + for (t=0; t<=4000; t=t+4) + { + + cpu_addr_i = 0x0000c0a0+t; + cpu_data_i = t+0; + cpu_wr(cpu_addr_i, cpu_data_i); + + cpu_hd(50); + + cpu_addr_i = 0x0000c0a0+t; + cpu_rd(cpu_addr_i, &cpu_data_o); + + cpu_hd(100); + } + + return(0); /* Return success (required by tasks) */ +} Index: tags/v2p2/doc/references/United States Patent US6931524.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: tags/v2p2/doc/references/United States Patent US6931524.pdf =================================================================== --- tags/v2p2/doc/references/United States Patent US6931524.pdf (nonexistent) +++ tags/v2p2/doc/references/United States Patent US6931524.pdf (revision 16)
tags/v2p2/doc/references/United States Patent US6931524.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/v2p2/doc/references/A Hardware and Software Monitor for High-Level System-on-Chip Verification.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: tags/v2p2/doc/references/A Hardware and Software Monitor for High-Level System-on-Chip Verification.pdf =================================================================== --- tags/v2p2/doc/references/A Hardware and Software Monitor for High-Level System-on-Chip Verification.pdf (nonexistent) +++ tags/v2p2/doc/references/A Hardware and Software Monitor for High-Level System-on-Chip Verification.pdf (revision 16)
tags/v2p2/doc/references/A Hardware and Software Monitor for High-Level System-on-Chip Verification.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/v2p2/doc/Revision History.txt =================================================================== --- tags/v2p2/doc/Revision History.txt (nonexistent) +++ tags/v2p2/doc/Revision History.txt (revision 16) @@ -0,0 +1,7 @@ + +1.0 Code base as published on EDN. + +2.0 Code base for 2.x development. Added pipelined bus access capture support. + +2.1 Added new features: 1. Multiple address filter selection; 2. Read access capture support; 3. Full trigger condition support; 4. Updated GUI; 5. Updated wrapper example with glitch filter and stable address/data capture. + Index: tags/v2p2/doc/Debug a microcontroller-to-FPGA interface from the FPGA side.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: tags/v2p2/doc/Debug a microcontroller-to-FPGA interface from the FPGA side.pdf =================================================================== --- tags/v2p2/doc/Debug a microcontroller-to-FPGA interface from the FPGA side.pdf (nonexistent) +++ tags/v2p2/doc/Debug a microcontroller-to-FPGA interface from the FPGA side.pdf (revision 16)
tags/v2p2/doc/Debug a microcontroller-to-FPGA interface from the FPGA side.pdf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: tags/v2p2/par/altera/up_monitor.qsf =================================================================== --- tags/v2p2/par/altera/up_monitor.qsf (nonexistent) +++ tags/v2p2/par/altera/up_monitor.qsf (revision 16) @@ -0,0 +1,45 @@ +# Copyright (C) 1991-2006 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + +# The default values for assignments are stored in the file +# up_monitor_assignment_defaults.qdf +# If this file doesn't exist, and for assignments not listed, see file +# assignment_defaults.qdf + +# Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. + + +set_global_assignment -name DEVICE Auto +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name TOP_LEVEL_ENTITY up_monitor_wrapper +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:33:38 JUNE 01, 2009" +set_global_assignment -name LAST_QUARTUS_VERSION "10.1 SP1" +set_global_assignment -name ENABLE_ADVANCED_IO_TIMING OFF +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output + +set_global_assignment -name VERILOG_FILE ../../rtl/up_monitor_wrapper.v +set_global_assignment -name VERILOG_FILE ../../rtl/up_monitor.v +set_global_assignment -name VERILOG_FILE ../../rtl/altera/virtual_jtag_addr_mask.v +set_global_assignment -name VERILOG_FILE ../../rtl/altera/virtual_jtag_adda_fifo.v +set_global_assignment -name VERILOG_FILE ../../rtl/altera/virtual_jtag_adda_trig.v + +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top + +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top Index: tags/v2p2/par/altera/up_monitor.qpf =================================================================== --- tags/v2p2/par/altera/up_monitor.qpf (nonexistent) +++ tags/v2p2/par/altera/up_monitor.qpf (revision 16) @@ -0,0 +1,23 @@ +# Copyright (C) 1991-2006 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + + +QUARTUS_VERSION = "6.1" +DATE = "18:33:38 June 01, 2009" + + +# Revisions + +PROJECT_REVISION = "up_monitor"

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