URL
https://opencores.org/ocsvn/bw_tiff_compression/bw_tiff_compression/trunk
Subversion Repositories bw_tiff_compression
Compare Revisions
- This comparison shows the changes necessary to convert path
/bw_tiff_compression
- from Rev 10 to Rev 11
- ↔ Reverse comparison
Rev 10 → Rev 11
/trunk/prj/bw_tiff_compression.xise
294,8 → 294,8
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/TB_capture_manager/uut" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.capture_manager" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/TB_capture_manager" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.TB_capture_manager" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
311,7 → 311,7
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.capture_manager" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.TB_capture_manager" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> |
/trunk/var_width_RAM.vhd
185,14 → 185,6
end process rd_addr_cnt_process; |
|
--Multiplexer 1(input to RAM 1) |
-- wr1 <= wr1_i when (mux_sel + to_unsigned(0,2)) = to_unsigned(0,2) |
-- else wr2_i when (mux_sel + to_unsigned(0,2)) = to_unsigned(1,2) |
-- else wr3_i when (mux_sel + to_unsigned(0,2)) = to_unsigned(2,2) |
-- else wr4_i when (mux_sel + to_unsigned(0,2)) = to_unsigned(3,2); |
-- d1_in <= d1_i when (mux_sel + to_unsigned(0,2)) = to_unsigned(0,2) |
-- else d2_i when (mux_sel + to_unsigned(0,2)) = to_unsigned(1,2) |
-- else d3_i when (mux_sel + to_unsigned(0,2)) = to_unsigned(2,2) |
-- else d4_i when (mux_sel + to_unsigned(0,2)) = to_unsigned(3,2); |
mux1_process : process(clk_i) |
begin |
if clk_i'event and clk_i = '0' then |
213,14 → 205,6
end process mux1_process; |
|
--Multiplexer 2(input to RAM 2) |
-- wr2 <= wr1_i when (mux_sel + to_unsigned(1,2)) = to_unsigned(0,2) |
-- else wr2_i when (mux_sel + to_unsigned(1,2)) = to_unsigned(1,2) |
-- else wr3_i when (mux_sel + to_unsigned(1,2)) = to_unsigned(2,2) |
-- else wr4_i when (mux_sel + to_unsigned(1,2)) = to_unsigned(3,2); |
-- d2_in <= d1_i when (mux_sel + to_unsigned(1,2)) = to_unsigned(0,2) |
-- else d2_i when (mux_sel + to_unsigned(1,2)) = to_unsigned(1,2) |
-- else d3_i when (mux_sel + to_unsigned(1,2)) = to_unsigned(2,2) |
-- else d4_i when (mux_sel + to_unsigned(1,2)) = to_unsigned(3,2); |
mux2_process : process(clk_i) |
begin |
if clk_i'event and clk_i = '0' then |
241,14 → 225,6
end process mux2_process; |
|
--Multiplexer 3(input to RAM 3) |
-- wr3 <= wr1_i when (mux_sel + to_unsigned(2,2)) = to_unsigned(0,2) |
-- else wr2_i when (mux_sel + to_unsigned(2,2)) = to_unsigned(1,2) |
-- else wr3_i when (mux_sel + to_unsigned(2,2)) = to_unsigned(2,2) |
-- else wr4_i when (mux_sel + to_unsigned(2,2)) = to_unsigned(3,2); |
-- d3_in <= d1_i when (mux_sel + to_unsigned(2,2)) = to_unsigned(0,2) |
-- else d2_i when (mux_sel + to_unsigned(2,2)) = to_unsigned(1,2) |
-- else d3_i when (mux_sel + to_unsigned(2,2)) = to_unsigned(2,2) |
-- else d4_i when (mux_sel + to_unsigned(2,2)) = to_unsigned(3,2); |
mux3_process : process(clk_i) |
begin |
if clk_i'event and clk_i = '0' then |
269,14 → 245,6
end process mux3_process; |
|
--Multiplexer 4(input to RAM 4) |
-- wr4 <= wr1_i when (mux_sel + to_unsigned(3,2)) = to_unsigned(0,2) |
-- else wr2_i when (mux_sel + to_unsigned(3,2)) = to_unsigned(1,2) |
-- else wr3_i when (mux_sel + to_unsigned(3,2)) = to_unsigned(2,2) |
-- else wr4_i when (mux_sel + to_unsigned(3,2)) = to_unsigned(3,2); |
-- d4_in <= d1_i when (mux_sel + to_unsigned(3,2)) = to_unsigned(0,2) |
-- else d2_i when (mux_sel + to_unsigned(3,2)) = to_unsigned(1,2) |
-- else d3_i when (mux_sel + to_unsigned(3,2)) = to_unsigned(2,2) |
-- else d4_i when (mux_sel + to_unsigned(3,2)) = to_unsigned(3,2); |
mux4_process : process(clk_i) |
begin |
if clk_i'event and clk_i = '0' then |
trunk/user_manual
Property changes :
Added: svn:ignore
## -0,0 +1,15 ##
+*.tex
+*.sty
+*.bib
+images
+*.backup
+*.toc
+*.aux
+*.bbl
+*.blg
+*.idx
+*.ilg
+*.ind
+*.backup
+*.out
+*.log