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/trunk/urng/MT_GET.vhd
0,0 → 1,411
--/////////////////////////MT_GET BLOCK///////////////////////////////
--Purpose: to produce functionality equivalent to following C code:
--
--
--Created by: Minzhen Ren
--Last Modified by: Minzhen Ren
--Last Modified Date: Auguest 30, 2010
--Lately Updates:
--/////////////////////////////////////////////////////////////////
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity MT_GET is
generic(
DATA_WIDTH : Natural := 32
);
port(
signal CLK : in std_logic;
signal RESET : in std_logic;
signal SEED_IN : in std_logic_vector( DATA_WIDTH-1 downto 0 );
signal PAUSE : in std_logic;
signal DONE_INIT : out std_logic;
signal OUT_SIG : out std_logic;
signal OUTPUT : out std_logic_vector( DATA_WIDTH-1 downto 0 )
);
end MT_GET;
 
architecture BEHAVE of MT_GET is
--contant
signal M_CONST : std_logic_vector( 9 downto 0 );
signal N_CONST : std_logic_vector( 9 downto 0 );
signal MN_DIFF : std_logic_vector( 9 downto 0 );
signal M_MINUS : std_logic_vector( 9 downto 0 );
signal N_MINUS : std_logic_vector( 9 downto 0 );
--MT_SET interface
signal SEED : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal WRITE_DATA : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal IDLE_SIG : std_logic;
--Memory interface
signal ADDR_MAX : std_logic_vector( 8 downto 0 );
signal WR_ENABLE0 : std_logic;
signal WR_ADDR0 : std_logic_vector( 8 downto 0 );
signal WR_ADDR0_Q : std_logic_vector( 8 downto 0 );
signal WR_ADDR0_QQ : std_logic_vector( 8 downto 0 );
signal WR_ADDR0_QQQ : std_logic_vector( 8 downto 0 );
signal WR_ADDR0_QQQQ : std_logic_vector( 8 downto 0 );
signal RD_ENABLE0 : std_logic;
signal RD_ADDR0 : std_logic_vector( 8 downto 0 );
signal MEM0_IN : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal MEM0_OUT : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal WR_ENABLE1 : std_logic;
signal WR_ADDR1 : std_logic_vector( 8 downto 0 );
signal RD_ENABLE1 : std_logic;
signal RD_ADDR1 : std_logic_vector( 8 downto 0 );
signal MEM1_IN : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal MEM1_OUT : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal DATA_MT_GEN : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal ADDR_SHF_IN : std_logic_vector( 9 downto 0 );
signal ADDR_SHF_OUT : std_logic_vector( 9 downto 0 );
signal OPRAND1 : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal OPRAND2 : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal OPRAND3 : std_logic_vector( DATA_WIDTH-1 downto 0 );
--Counter
signal KK : std_logic_vector( 9 downto 0 );
signal INNER_STATE : std_logic_vector( 2 downto 0 );
signal KK_MAX : std_logic_vector( 9 downto 0 );
--Control signal
signal MEM_SEL : std_logic;
--State Machine
type STATE_TYPE is (INITIAL, MEM_INIT, MT_GEN, PAUSE_STATE);
signal CS : STATE_TYPE;
signal NS : STATE_TYPE;
component MT_SET is
generic(
DATA_WIDTH : Natural := 32
);
port(
signal CLK : in std_logic;
signal RESET : in std_logic;
signal IDLE_SIG : in std_logic;
signal S_IN : in std_logic_vector( DATA_WIDTH-1 downto 0 );
signal S_OUT : out std_logic_vector( DATA_WIDTH-1 downto 0 )
);
end component;
component dp_mem is
generic (
Addr_Wdth : Natural := 9;
Bit_Wdth : Natural := 32
);
port (Clock : in Std_Logic;
Write_Enable : in Std_Logic;
Write_Address : in Std_Logic_Vector(Addr_Wdth-1 downto 0);
Read_Enable : in Std_Logic;
Read_Address : in Std_Logic_Vector(Addr_Wdth-1 downto 0);
Data_In : in Std_Logic_Vector(Bit_Wdth-1 downto 0);
Data_Out : out Std_Logic_Vector(Bit_Wdth-1 downto 0));
end component;
component MT_PATH is
generic(
DATA_WIDTH : Natural := 32
);
port(
signal OPRAND1 : in std_logic_vector( DATA_WIDTH-1 downto 0 );
signal OPRAND2 : in std_logic_vector( DATA_WIDTH-1 downto 0 );
signal OPRAND3 : in std_logic_vector( DATA_WIDTH-1 downto 0 );
signal CLK : in std_logic;
signal RESET : in std_logic;
signal OUTPUT : out std_logic_vector( DATA_WIDTH-1 downto 0 )
);
end component;
component MT_SHIFTING is
generic(
DATA_WIDTH : Natural := 32
);
port(
signal INPUT : in std_logic_vector( DATA_WIDTH-1 downto 0 );
signal OUTPUT : out std_logic_vector( DATA_WIDTH-1 downto 0 )
);
end component;
begin
MT_BLK : MT_SET
port map(
S_IN => SEED,
S_OUT => WRITE_DATA,
CLK => CLK,
RESET => RESET,
IDLE_SIG => IDLE_SIG
);
MEM0 : dp_mem
port map(
Clock => CLK,
Write_Enable => WR_ENABLE0,
Write_Address => WR_ADDR0,
Read_Enable => RD_ENABLE0,
Read_Address => RD_ADDR0,
Data_In => MEM0_IN,
Data_Out => MEM0_OUT
);
MEM1 : dp_mem
port map(
Clock => CLK,
Write_Enable => WR_ENABLE1,
Write_Address => WR_ADDR1,
Read_Enable => RD_ENABLE1,
Read_Address => RD_ADDR1,
Data_In => MEM1_IN,
Data_Out => MEM1_OUT
);
CURRENT_STATE : process(CLK, RESET)
begin
if RESET = '1' then
CS <= INITIAL;
elsif CLK='1' and CLK'event then
CS <= NS;
end if;
end process;
NEXT_STATE : process(CS, KK, N_MINUS, INNER_STATE, PAUSE)
begin
if CS = INITIAL then
NS <= MEM_INIT;
elsif CS = MEM_INIT then
if KK = N_MINUS and INNER_STATE(2) = '1' then
NS <= MT_GEN;
else
NS <= CS;
end if;
elsif CS <= MT_GEN then
if PAUSE = '1' then
NS <= PAUSE_STATE;
else
NS <= MT_GEN;
end if;
elsif CS <= PAUSE_STATE then
if PAUSE = '0' then
NS <= MT_GEN;
else
NS <= PAUSE_STATE;
end if;
else
NS <= INITIAL;
end if;
end process;
COUNTER_PROC : process(CLK, RESET)
begin
if RESET = '1' then
KK <= (others => '0');
elsif CLK'event and CLK='1' then
if CS = INITIAL then
KK <= (others => '0');
elsif CS = MEM_INIT then
if INNER_STATE(2) = '1' and KK /= N_MINUS then
KK <= KK + 1;
elsif INNER_STATE(2) = '1' and KK = N_MINUS then
KK <= (others => '0');
else
KK <= KK;
end if;
elsif CS = MT_GEN then
if INNER_STATE = "011" and KK /= N_MINUS then
KK <= KK + 1;
elsif INNER_STATE = "011" and KK = N_MINUS then
KK <= (others => '0');
end if;
elsif CS = PAUSE_STATE then
KK <= KK;
else
KK <= (others => '0');
end if;
end if;
end process;
INNER_STATE_COUNTER : process(CLK, RESET)
begin
if RESET = '1' then
INNER_STATE <= (others => '0');
elsif CLK'event and CLK='1' then
if CS = INITIAL then
INNER_STATE <= (others => '0');
elsif CS = MEM_INIT then
if INNER_STATE(2) = '0' then
INNER_STATE <= INNER_STATE + '1';
else
INNER_STATE <= "001";
end if;
elsif CS = MT_GEN then
if INNER_STATE < "011" then
INNER_STATE <= INNER_STATE + '1';
else
INNER_STATE <= "001";
end if;
elsif CS = PAUSE_STATE then
INNER_STATE <= "001";
else
INNER_STATE <= (others => '0');
end if;
end if;
end process;
IDLE_SIG <= '0' when CS = MEM_INIT and RESET = '0' else '1';
--constants
N_CONST <= "1001110000"; --624
M_CONST <= "0110001101"; --397
MN_DIFF <= "0011100011"; --227
N_MINUS <= "1001101111"; --623
M_MINUS <= "0110001100"; --396
--N_MM <= "1001101101"; --621
SEED <= "00000000000000000001000100000101" when SEED_IN = 0 else SEED_IN; --default seed
KK_MAX <= "1001101111"; --623
ADDR_MAX <= "100110111"; --311
--memory control
MEM_SEL <= '0' when KK(0) = '0' and CS = MEM_INIT else
'1' when KK(0) = '1' and CS = MEM_INIT else
'0' when ((to_integer(unsigned(KK))) mod 2) = 0 and RESET = '0' and CS = MT_GEN else
'1' when RESET = '0' and CS = MT_GEN else
'0';
WR_ENABLE0 <= '1' when (CS = MEM_INIT and MEM_SEL = '0') or (CS = MT_GEN and INNER_STATE = "011" and MEM_SEL = '0')
else '0';
WR_ENABLE1 <= '1' when (CS = MEM_INIT and MEM_SEL = '1') or (CS = MT_GEN and INNER_STATE = "011" and MEM_SEL = '1')
else '0';
RD_ENABLE0 <= '1' when (NS = MT_GEN)
else '0';
RD_ENABLE1 <= '1' when (NS = MT_GEN)
else '0';
MEM0_IN <= WRITE_DATA when MEM_SEL = '0' and CS = MEM_INIT
else DATA_MT_GEN when MEM_SEL = '0' and CS = MT_GEN and INNER_STATE = "011"
else ( others => '0' );
MEM1_IN <= WRITE_DATA when MEM_SEL = '1' and (CS = MEM_INIT or (CS = MT_GEN and INNER_STATE = "001"))
else DATA_MT_GEN when MEM_SEL = '1' and CS = MT_GEN and INNER_STATE = "011"
else ( others => '0' );
MEM0_WR_PROC : process(CLK, RESET)
begin
if RESET = '1' then
WR_ADDR0 <= (others => '0');
elsif CLK = '1' and CLK'event then
if CS = MEM_INIT then
if INNER_STATE(2) = '1' and MEM_SEL = '0' and WR_ADDR0 /= ADDR_MAX then
WR_ADDR0 <= WR_ADDR0 + 1;
elsif INNER_STATE(2) = '1' and MEM_SEL = '0' and WR_ADDR0 = ADDR_MAX then
WR_ADDR0 <= (others => '0');
else
WR_ADDR0 <= WR_ADDR0;
end if;
elsif CS = MT_GEN then
if WR_ADDR0 /= ADDR_MAX and INNER_STATE = "011" and MEM_SEL = '0' then
WR_ADDR0 <= WR_ADDR0 + 1;
elsif WR_ADDR0 = ADDR_MAX and MEM_SEL = '0' and INNER_STATE = "011" then
WR_ADDR0 <= (others => '0');
else
WR_ADDR0 <= WR_ADDR0;
end if;
elsif CS = PAUSE_STATE then
WR_ADDR0 <= WR_ADDR0;
else
WR_ADDR0 <= (others => '0');
end if;
end if;
end process;
MEM0_WR_DELAY : process (CLK, RESET)
begin
if RESET = '1' then
WR_ADDR0_Q <= (others => '0');
WR_ADDR0_QQ <= (others => '0');
WR_ADDR0_QQQ <= (others => '0');
WR_ADDR0_QQQQ <= (others => '0');
elsif CLK='1' and CLK'event then
WR_ADDR0_Q <= WR_ADDR0;
WR_ADDR0_QQ <= WR_ADDR0_Q;
WR_ADDR0_QQQ <= WR_ADDR0_QQ;
WR_ADDR0_QQQQ <= WR_ADDR0_QQQ;
end if;
end process;
WR_ADDR1 <= WR_ADDR0_QQQQ when CS = MEM_INIT else
WR_ADDR0_QQQ when CS = MT_GEN;
ADDR_SHF_IN <= KK + M_CONST when KK < MN_DIFF and CS = MT_GEN else
KK - MN_DIFF when (KK >= MN_DIFF and KK < N_MINUS) and CS = MT_GEN else
M_MINUS when KK = N_MINUS and CS = MT_GEN
else (others => '0');
ADDR_SHF_OUT <= '0' & ADDR_SHF_IN(9 downto 1);
MEM0_RD_PROC : process(CS, INNER_STATE, MEM_SEL, ADDR_SHF_OUT, WR_ADDR0)
begin
if CS = MT_GEN then
if INNER_STATE = "001" then
RD_ADDR0 <= WR_ADDR0;
elsif INNER_STATE = "010" and MEM_SEL = '1' then
RD_ADDR0 <= ADDR_SHF_OUT( 8 downto 0 );
else
RD_ADDR0<= WR_ADDR0;
end if;
else
RD_ADDR0 <= (others => '0');
end if;
end process;
MEM1_RD_PROC : process(CS, INNER_STATE, MEM_SEL, ADDR_SHF_OUT, WR_ADDR1)
begin
if CS = MT_GEN then
if INNER_STATE = "001" then
RD_ADDR1 <= WR_ADDR1;
elsif INNER_STATE = "010" and MEM_SEL = '0' then
RD_ADDR1 <= ADDR_SHF_OUT( 8 downto 0 );
else
RD_ADDR1 <= WR_ADDR1;
end if;
else
RD_ADDR1 <= (others => '0');
end if;
end process;
OPRAND1 <= MEM0_OUT when MEM_SEL = '0' and CS = MT_GEN and INNER_STATE = "010"
else MEM1_OUT when MEM_SEL = '1' and CS = MT_GEN and INNER_STATE = "010"
else (others =>'0');
OPRAND2 <= MEM0_OUT when MEM_SEL = '1' and CS = MT_GEN and INNER_STATE = "010"
else MEM1_OUT when MEM_SEL = '0' and CS = MT_GEN and INNER_STATE = "010"
else (others=>'0');
OPRAND3 <= MEM0_OUT when MEM_SEL = '1' and CS = MT_GEN and INNER_STATE = "011"
else MEM1_OUT when MEM_SEL = '0' and CS = MT_GEN and INNER_STATE = "011"
else (others =>'0');
MT_DATAPATH : MT_PATH
port map(
OPRAND1 => OPRAND1,
OPRAND2 => OPRAND2,
OPRAND3 => OPRAND3,
CLK => CLK,
RESET => RESET,
OUTPUT => DATA_MT_GEN
);
MT_RN_GEN : MT_SHIFTING
port map(
INPUT => DATA_MT_GEN,
OUTPUT => OUTPUT
);
DONE_INIT <= '0' when NS = MEM_INIT else '1';
OUT_SIG <= '1' when CS = MT_GEN and (INNER_STATE = "010" or INNER_STATE = "011") else '0';
end BEHAVE;
/trunk/urng/MAGIC.vhd
0,0 → 1,39
--/////////////////////////MAGIC BLOCK///////////////////////////////
--Purpose: to produce the equivalent funtionality of following C code
-- #define MAGIC(y) (((y)&0x1) ? 0x9908b0dfUL : 0)
--Created by: Minzhen Ren
--Last Modified by: Minzhen Ren
--Last Modified Date: Auguest 28, 2010
--Lately Updates:
--/////////////////////////////////////////////////////////////////
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity MAGIC is
generic(
DATA_WIDTH : Natural := 32
);
port(
Y_IN : in std_logic_vector( DATA_WIDTH-1 downto 0 );
Y_OUT : out std_logic_vector( DATA_WIDTH-1 downto 0 )
);
end MAGIC;
 
architecture BEHAVE of MAGIC is
begin
WHOLE : process(Y_IN)
begin
if (Y_IN(0) and '1') = '1' then
Y_OUT <= "10011001000010001011000011011111"; -- 0x9908b0dfUL
else
Y_OUT <= ( others => '0' );
end if;
end process;
end BEHAVE;
/trunk/urng/DP_MEM.vhd
0,0 → 1,39
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;
use IEEE.Std_Logic_Unsigned.all;
 
entity dp_mem is
generic (
Addr_Wdth : Natural := 9;
Bit_Wdth : Natural := 32
);
-- DO NOT USE more than 14 address bits
-- Using more than 11 address bits may be inefficient for some data widths.
port (Clock : in Std_Logic;
Write_Enable : in Std_Logic;
Write_Address : in Std_Logic_Vector(Addr_Wdth-1 downto 0);
Read_Enable : in Std_Logic;
Read_Address : in Std_Logic_Vector(Addr_Wdth-1 downto 0);
Data_In : in Std_Logic_Vector(Bit_Wdth-1 downto 0);
Data_Out : out Std_Logic_Vector(Bit_Wdth-1 downto 0)
);
end dp_mem;
 
architecture rtl of dp_mem is
Type T_Mem is array (0 to 311) of Std_Logic_Vector(Bit_Wdth-1 downto 0);
signal Mem_Contents : T_Mem;
begin -- rtl
S_Write_Mem : process(Clock)
begin
-- Do not use write first
if Clock'event and Clock = '1' then
if Read_Enable = '1' then
Data_Out <= Mem_Contents(conv_integer(Read_Address));
end if;
if Write_Enable = '1' then
Mem_Contents(conv_integer(Write_Address)) <= Data_In;
end if;
end if;
end process;
end rtl;
/trunk/urng/MT_GET_TB.vhd
0,0 → 1,145
--/////////////////////////MT_GET TEST BENCH///////////////////////////////
--Purpose: test bench for MT_GET module
--Created by: Minzhen Ren
--Last Modified by: Minzhen Ren
--Last Modified Date: September 01, 2010
--Lately Updates: File was created
--////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.math_real.all;
library STD;
use STD.textio.all;
entity MT_GET_TB is
end MT_GET_TB;
 
architecture TB of MT_GET_TB is
 
--interface signals
signal CLK : std_logic;
signal RESET : std_logic;
signal PAUSE : std_logic;
signal OUT_SIG : std_logic;
signal SEED : std_logic_vector( 31 downto 0 );
signal RND_NUM_BIN : std_logic_vector( 31 downto 0 );
signal RND_NUM_INT : integer;
signal NUMS : integer;
--half of a period defined
signal HALF_PERIOD : time := 10 ns;
--FILE I/O
file INFILE : TEXT open READ_MODE is "commands.stim";
file OUTFILE : TEXT open WRITE_MODE is "rnd_num.out";
--components
component MT_GET is
generic(
DATA_WIDTH : Natural := 32
);
port(
signal CLK : in std_logic;
signal RESET : in std_logic;
signal SEED_IN : in std_logic_vector( DATA_WIDTH-1 downto 0 );
signal PAUSE : in std_logic;
signal OUT_SIG : out std_logic;
signal OUTPUT : out std_logic_vector( DATA_WIDTH-1 downto 0 )
);
end component;
function Slv_To_String(SLV: std_logic_vector(31 downto 0)) return string is
variable RET: string(32 downto 1);
variable ONEBIT : character;
begin
for I in SLV'range loop
case SLV(I) is
when '1' => RET(I+1) := '1';
when '0' => RET(I+1) := '0';
when others => null;
end case;
end loop;
return(RET);
end function Slv_To_String;
begin
-- PAUSE <= '0';
PAUSE_PROCESS : process
begin
PAUSE <= '0';
wait for 50230 ns;
PAUSE <= '1' ;
wait for 80 ns;
PAUSE <= '0';
wait for 1 ms;
end process;
RND_NUM_INT <= to_integer(signed(RND_NUM_BIN));
CLK_PROC : process
begin
CLK <= '0';
wait for HALF_PERIOD;
CLK <= '1';
wait for HALF_PERIOD;
end process;
MT_GET_BLK : MT_GET
port map(
CLK => CLK,
RESET => RESET,
SEED_IN => SEED,
PAUSE => PAUSE,
OUT_SIG => OUT_SIG,
OUTPUT => RND_NUM_BIN
);
TB_FLOW : process
variable FILE_LINE_IN : line; --INFILE LINE
variable FILE_LINE_OUT : line;
variable TEMPINT : integer;
variable CMD : string(5 downto 1);
begin
if (not(ENDFILE(INFILE))) then
READLINE(INFILE, FILE_LINE_IN);
READ(FILE_LINE_IN, CMD);
if ( CMD = "NUMS " ) then
-- Read the number of outputs
READ(FILE_LINE_IN, TEMPINT);
NUMS <= TEMPINT;
wait until RISING_EDGE(OUT_SIG);
for j in 1 to NUMS loop
wait for HALF_PERIOD;
wait for HALF_PERIOD;
wait for HALF_PERIOD;
write(FILE_LINE_OUT, RND_NUM_INT);
writeline(OUTFILE, FILE_LINE_OUT);
wait until FALLING_EDGE(OUT_SIG);
wait until RISING_EDGE(OUT_SIG);
end loop;
elsif ( CMD = "RESET" ) then
RESET <= '1';
wait until FALLING_EDGE(CLK);
wait until FALLING_EDGE(CLK);
RESET <= '0';
elsif ( CMD = "SEED " ) then
READ(FILE_LINE_IN, TEMPINT);
SEED <= std_logic_vector(to_unsigned(TEMPINT, 32));
else
report("Command not recognized");
end if;
else
assert FALSE report("Simulation Completed") severity FAILURE;
end if;
end process;
-- END_PROCESS : process
-- begin
-- wait for 60000 ns;
-- assert FALSE report("Simulation Completed") severity FAILURE;
-- end process;
end TB;
/trunk/urng/LCG.vhd
0,0 → 1,68
--/////////////////////////LCG BLOCK///////////////////////////////
--Purpose: to produce functionality equivalent to following C code:
-- #define LCG(x) ((69069 * x) + 1) & 0xffffffffUL
--
--Created by: Minzhen Ren
--Last Modified by: Minzhen Ren
--Last Modified Date: November 2, 2010
--Lately Updates: Pipelined
--/////////////////////////////////////////////////////////////////
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity LCG is
generic(
DATA_WIDTH : Natural := 32
);
port(
CLK : in std_logic;
RESET : in std_logic;
X_IN : in std_logic_vector( DATA_WIDTH-1 downto 0 );
X_OUT : out std_logic_vector( DATA_WIDTH-1 downto 0 )
);
end LCG;
 
architecture BEHAV of LCG is
signal MASK : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal MULTIPLICAND : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal OP_Q : std_logic_vector( 2*DATA_WIDTH-1 downto 0 );
signal OP_D : std_logic_vector( 2*DATA_WIDTH-1 downto 0 );
signal OP_TEMP : std_logic_vector( 2*DATA_WIDTH-1 downto 0 );
component REG is
generic( BIT_WIDTH : Natural := 64); -- Default is 8 bits
port(
CLK : in std_logic;
RESET : in std_logic; -- high asserted
DATA_IN : in std_logic_vector( BIT_WIDTH-1 downto 0 );
DATA_OUT : out std_logic_vector( BIT_WIDTH-1 downto 0 )
);
end component;
begin
MASK <= ( others => '1' ); --0xffffffffUL
MULTIPLICAND <= "00000000000000010000110111001101"; --69069
OP_D <= X_IN * MULTIPLICAND; -- + 1;
OP_REG : REG
generic map(
BIT_WIDTH => 64
)
port map(
CLK => CLK,
RESET => RESET,
DATA_IN => OP_D,
DATA_OUT => OP_Q
);
OP_TEMP <= OP_Q + 1;
X_OUT <= MASK and OP_TEMP( DATA_WIDTH-1 downto 0);
end BEHAV;
/trunk/urng/MT_SET.vhd
0,0 → 1,204
--/////////////////////////MT BLOCK///////////////////////////////
--Purpose: to produce functionality equivalent to following C code
-- excluding a momry module
-- void mt_set (void *vstate, unsigned long int s)
-- {
-- mt_state_t *state = (mt_state_t *) vstate;
-- int i;
-- if (s == 0)
-- s = 4357; /* the default seed is 4357 */
-- #define LCG(x) ((69069 * x) + 1) &0xffffffffUL
-- for (i = 0; i < N; i++)
-- {
-- state->mt[i] = s & 0xffff0000UL;
-- s = LCG(s);
-- state->mt[i] |= (s &0xffff0000UL) >> 16;
-- s = LCG(s);
-- }
-- state->mti = i;
-- }
--Created by: Minzhen Ren
--Last Modified by: Minzhen Ren
--Last Modified Date: Auguest 28, 2010
--Lately Updates:
--/////////////////////////////////////////////////////////////////
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity MT_SET is
generic(
DATA_WIDTH : Natural := 32
);
port(
signal CLK : in std_logic;
signal RESET : in std_logic;
signal IDLE_SIG : in std_logic;
signal S_IN : in std_logic_vector( DATA_WIDTH-1 downto 0 );
signal S_OUT : out std_logic_vector( DATA_WIDTH-1 downto 0 )
);
end MT_SET;
 
architecture BEHAV of MT_SET is
--state machine
type STATE_TYPE is (INITIAL, RUNNING, IDLE);
signal CS : STATE_TYPE;
signal NS : STATE_TYPE;
signal INNER_STATE : std_logic_vector(2 downto 0);
signal MASK : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal S_D : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal S_Q : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal IDLE_IN : std_logic;
signal S_LCG1 : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal S_LCG1_Q : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal S_LCG2 : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal S_OP1_D : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal S_OP1_Q : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal S_OP2 : std_logic_vector( DATA_WIDTH-1 downto 0 );
component REG is
generic(
BIT_WIDTH : Natural := 32
);
port(
CLK : in std_logic;
RESET : in std_logic; -- high asserted
DATA_IN : in std_logic_vector( BIT_WIDTH-1 downto 0 );
DATA_OUT : out std_logic_vector( BIT_WIDTH-1 downto 0 )
);
end component;
component LCG is
generic(
DATA_WIDTH : Natural := 32
);
port(
CLK : in std_logic;
RESET : in std_logic;
X_IN : in std_logic_vector( DATA_WIDTH-1 downto 0 );
X_OUT : out std_logic_vector( DATA_WIDTH-1 downto 0 )
);
end component;
 
begin
MASK <= "11111111111111110000000000000000"; --0xffffffffUL
IDLE_IN <= IDLE_SIG;
CURRENT_STATE : process(CLK, RESET)
begin
if RESET = '1' then
CS <=INITIAL;
elsif CLK='1' and CLK'event then
CS <= NS;
end if;
end process;
NEXT_STATE : process(CS, IDLE_IN)
begin
if CS = INITIAL then
NS <= RUNNING;
elsif CS = RUNNING then
if IDLE_IN = '1' then
NS <= IDLE;
else
NS <= CS;
end if;
elsif CS = IDLE then
if IDLE_IN = '0' then
NS <= RUNNING;
else
NS <= CS;
end if;
else
NS <= CS;
end if;
 
end process;
INNER_STATE_PROCESS : process(RESET, CLK)
begin
if RESET = '1' then
INNER_STATE <= (others => '0');
elsif CLK'event and CLK='1' then
if INNER_STATE(2) = '0' then
INNER_STATE <= INNER_STATE + 1;
else
INNER_STATE <= "001";
end if;
end if;
end process;
--input mux
S_D <= S_IN when CS = INITIAL else
S_Q when CS = IDLE else
S_LCG2 when INNER_STATE(2) = '1' else
S_Q;
S_IN_REG : REG
port map(
CLK => CLK,
RESET => RESET,
DATA_IN => S_D,
DATA_OUT => S_Q
);
S_OP1_D <= S_Q and MASK;
S_OP1_REG : REG
port map(
CLK => CLK,
RESET => RESET,
DATA_IN => S_OP1_D,
DATA_OUT => S_OP1_Q
);
LCG1 : LCG
port map(
CLK => CLK,
RESET => RESET,
X_IN => S_Q,
X_OUT => S_LCG1
);
S_OP2 <= S_LCG1 and MASK;
S_OUT <= S_OP1_Q or ("0000000000000000" & S_OP2(31 downto 16));
S_LCG1_REG : REG
port map(
CLK => CLK,
RESET => RESET,
DATA_IN => S_LCG1,
DATA_OUT => S_LCG1_Q
);
LCG2 : LCG
port map(
CLK => CLK,
RESET => RESET,
X_IN => S_LCG1_Q,
X_OUT => S_LCG2
);
-- S_OUT_REG1 : REG
-- port map(
-- CLK => CLK,
-- RESET => RESET,
-- DATA_IN => S_OUT_D,
-- DATA_OUT => S_OUT_DD
-- );
-- S_OUT_REG2 : REG
-- port map(
-- CLK => CLK,
-- RESET => RESET,
-- DATA_IN => S_OUT_DD,
-- DATA_OUT => S_OUT
-- );
end BEHAV;
/trunk/urng/MT_SHIFTING.vhd
0,0 → 1,59
--/////////////////////////MT_SHIFTING BLOCK///////////////////////////////
--Purpose: to produce functionality equivalent to following C code:
-- k = mt[state->mti];
-- k ^= (k >> 11);
-- k ^= (k << 7) & 0x9d2c5680UL;
-- k ^= (k << 15) & 0xefc60000UL;
-- k ^= (k >> 18);
--
--Created by: Minzhen Ren
--Last Modified by: Minzhen Ren
--Last Modified Date: Auguest 30, 2010
--Lately Updates:
--/////////////////////////////////////////////////////////////////
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity MT_SHIFTING is
generic(
DATA_WIDTH : Natural := 32
);
port(
signal INPUT : in std_logic_vector( DATA_WIDTH-1 downto 0 );
signal OUTPUT : out std_logic_vector( DATA_WIDTH-1 downto 0 )
);
end MT_SHIFTING;
 
architecture BEHAVE of MT_SHIFTING is
--constant
signal MASK1 : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal MASK2 : std_logic_vector( DATA_WIDTH-1 downto 0 );
--internal signals
signal SIGNAL_S1 : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal SIGNAL_I1 : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal SIGNAL_S2 : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal SIGNAL_I2 : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal SIGNAL_S3 : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal SIGNAL_I3 : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal SIGNAL_S4 : std_logic_vector( DATA_WIDTH-1 downto 0 );
begin
--constant
MASK1 <= "10011101001011000101011010000000"; -- Ox9d2c5680UL
MASK2 <= "11101111110001100000000000000000"; -- Oxefc60000UL
SIGNAL_S1 <= "00000000000" & INPUT(DATA_WIDTH-1 downto 11);
SIGNAL_I1 <= INPUT xor SIGNAL_S1;
SIGNAL_S2 <= SIGNAL_I1(DATA_WIDTH-8 downto 0) & "0000000";
SIGNAL_I2 <= SIGNAL_I1 xor (SIGNAL_S2 and MASK1);
SIGNAL_S3 <= SIGNAL_I2(DATA_WIDTH-16 downto 0) & "000000000000000";
SIGNAL_I3 <= SIGNAL_I2 xor (SIGNAL_S3 and MASK2);
SIGNAL_S4 <= "000000000000000000" & SIGNAL_I3(DATA_WIDTH-1 downto 18);
OUTPUT <= SIGNAL_I3 xor SIGNAL_S4;
end BEHAVE;
/trunk/urng/commands.stim
0,0 → 1,3
SEED 1234
RESET
NUMS 10
/trunk/urng/MT_PATH.vhd
0,0 → 1,89
--/////////////////////////MT_PATH BLOCK///////////////////////////////
--Purpose: to produce functionality equivalent to following C code:
--
--
--Created by: Minzhen Ren
--Last Modified by: Minzhen Ren
--Last Modified Date: Auguest 29, 2010
--Lately Updates:
--////////////////////////////////////////////////////////////////////
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity MT_PATH is
generic(
DATA_WIDTH : Natural := 32
);
port(
signal OPRAND1 : in std_logic_vector( DATA_WIDTH-1 downto 0 );
signal OPRAND2 : in std_logic_vector( DATA_WIDTH-1 downto 0 );
signal OPRAND3 : in std_logic_vector( DATA_WIDTH-1 downto 0 );
signal CLK : in std_logic;
signal RESET : in std_logic;
signal OUTPUT : out std_logic_vector( DATA_WIDTH-1 downto 0 )
);
end MT_PATH;
 
architecture BEHAVE of MT_PATH is
--constant
signal UPPER_MASK : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal LOWER_MASK : std_logic_vector( DATA_WIDTH-1 downto 0 );
--Y calculation
signal Y_OP1 : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal Y_OP2 : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal Y_D : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal Y_Q : std_logic_vector( DATA_WIDTH-1 downto 0 );
signal Y_MAGIC : std_logic_vector( DATA_WIDTH-1 downto 0 );
component REG is
generic( BIT_WIDTH : Natural := 32); -- Default is 8 bits
port( CLK : in std_logic;
RESET : in std_logic; -- high asserted
DATA_IN : in std_logic_vector( BIT_WIDTH-1 downto 0 );
DATA_OUT : out std_logic_vector( BIT_WIDTH-1 downto 0 )
);
end component;
component MAGIC is
generic(
DATA_WIDTH : Natural := 32
);
port(
Y_IN : in std_logic_vector( DATA_WIDTH-1 downto 0 );
Y_OUT : out std_logic_vector( DATA_WIDTH-1 downto 0 )
);
end component;
begin
--constant
UPPER_MASK <= "10000000000000000000000000000000"; --0x80000000UL
LOWER_MASK <= "01111111111111111111111111111111"; --0x7fffffffUL
Y_OP1 <= OPRAND1 and UPPER_MASK;
Y_OP2 <= OPRAND2 and LOWER_MASK;
Y_D <= Y_OP1 or Y_OP2;
Y_REG : REG
port map(
CLK => CLK,
RESET => RESET,
DATA_IN => Y_D,
DATA_OUT => Y_Q
);
MAGIC_Y : MAGIC
port map(
Y_IN => Y_Q,
Y_OUT => Y_MAGIC
);
OUTPUT <= (OPRAND3 xor ('0' & Y_Q(DATA_WIDTH-1 downto 1))) xor Y_MAGIC;
end BEHAVE;
/trunk/urng/REG.vhd
0,0 → 1,34
--/////////////////////////REG///////////////////////////////
--Purpose: 37-bit register
--Created by: Minzhen Ren
--Last Modified by: Minzhen Ren
--Last Modified Date: October 6, 2010
--Lately Updates: 37-bit register for CORDIC log algorithm
--/////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;
use IEEE.Std_Logic_Unsigned.all;
entity REG is
generic( BIT_WIDTH : Natural := 37); -- Default is 37 bits
port( CLK : in std_logic;
RESET : in std_logic; -- high asserted
DATA_IN : in std_logic_vector( BIT_WIDTH-1 downto 0 );
DATA_OUT : out std_logic_vector( BIT_WIDTH-1 downto 0 )
);
end REG;
architecture BEHAVIOR of REG is
begin
reg_proc : process(CLK, RESET)
begin
if RESET = '1' then
DATA_OUT <= (others => '0');
elsif (CLK'event) and (CLK = '1') then
DATA_OUT <= DATA_IN;
end if;
end process;
end BEHAVIOR;

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