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URL https://opencores.org/ocsvn/connect-6/connect-6/trunk

Subversion Repositories connect-6

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  • This comparison shows the changes necessary to convert path 
    /connect-6/trunk
    from Rev 5 to Rev 6
    ↔ Reverse comparison
  •

Rev 5 → Rev 6

/BUILD_SCC/scc_scripts/run_imp_line.tcl
42,7 → 42,7
schedule
csim -schedule -cexec_args "-port /dev/ttyS0 -player L"
synthesize
csim -synthesize -dump_memory_access_trace -sim_after_synth_phase 5
#csim -synthesize -dump_memory_access_trace -sim_after_synth_phase 5
create_rtl_package
 
#set_implementation_params -simulator modelsim
/BUILD_SCC/scc_scripts/run_imp_threat.tcl
46,7 → 46,7
#csim -synthesize -dump_memory_access_trace
#csim -synthesize with -dump_memory_access_trace -sim_after_synth_phase 5
create_rtl_package
csim -synthesize
#csim -synthesize
 
#set_implementation_params -simulator modelsim
#vlogsim -offline -dotasks 1-30
/BUILD_SCC/scc_scripts/run_imp_connect.tcl
42,7 → 42,7
schedule
csim -schedule -cexec_args "-port /dev/ttyS0 -player L"
synthesize
csim -synthesize -dump_memory_access_trace -sim_after_synth_phase 5
#csim -synthesize -dump_memory_access_trace -sim_after_synth_phase 5
create_rtl_package
 
#set_implementation_params -simulator modelsim
/BUILD_SCC/scc_scripts/run_imp_threat_flat.tcl
0,0 → 1,52
set SYNTH_SRC "synth_src"
set_project_params -directory ./
set_project_params -results myboard.txt
set_project_params -sources "${SYNTH_SRC}/connect6.cpp ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/main.cpp ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/util.cpp"
set_project_params -headers "${SYNTH_SRC}/connect6.h ${SYNTH_SRC}/connect6_synth.h ${SYNTH_SRC}/shared.h ${SYNTH_SRC}/threats.h ${SYNTH_SRC}/util.h"
 
if [file exists imp_threat_flat] { delete_implementation imp_threat_flat }
create_implementation imp_threat_flat
 
set_implementation_params -systemc_source no
set_implementation_params -memory_return_path_external_delay 0%
set_implementation_params -memory_forward_path_external_delay 0%
set_implementation_params -instream_forward_path_external_delay 0%
#set_implementation_params -import_tcab "imp_line"
#imp_line"
set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID"
set_implementation_params -outstream_return_path_external_delay 0%
set_implementation_params -appfiles "${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp"
set_implementation_params -proc ai_threats
set_implementation_params -memory_forward_boundary_register infer
set_implementation_params -techlib altera-cyclone3
set_implementation_params -memory_return_boundary_register infer
set_implementation_params -cexec_args "-port /dev/ttyS0 -player L"
set_implementation_params -host_memory_access never
set_implementation_params -device ep3c25-ea144-7
set_implementation_params -force_independent_stalldomain_tcab yes
set_implementation_params -init_data_registers yes
set_implementation_params -outstream_forward_path_external_delay 0%
set_implementation_params -build_tcab yes
set_implementation_params -reset_data_registers yes
set_implementation_params -instream_return_path_external_delay 0%
set_implementation_params -clock_freq 100
set_implementation_params -allow_latency_violation no
#set_implementation_params -user_supplied_fpga_memory_read_write_ports separate
#set_implementation_params -internal_blockram_memory_read_write_ports separate
 
 
 
csim -golden -cexec_args "-port /dev/ttyS0 -player L"
preprocess
csim -preprocess -cexec_args "-port /dev/ttyS0 -player L"
schedule
csim -schedule -cexec_args "-port /dev/ttyS0 -player L"
synthesize
#csim -synthesize -dump_memory_access_trace
#csim -synthesize with -dump_memory_access_trace -sim_after_synth_phase 5
create_rtl_package
#csim -synthesize
 
#set_implementation_params -simulator modelsim
#vlogsim -offline -dotasks 1-30
/BUILD_SCC/Makefile
40,30 → 40,36
fpga: synth altera_synth test
cp cp ./rtl_package/synth/altera_fpga/run/DE2.sof ../DEMO
 
synth: all imp_connect
imp_window:
synth: imp_connect.tag
imp_window.tag:
#sed -s 's/\\TCAB_NAME/threat_window/g' main.cpp.base >main.cpp
cp ${SYNTH_SRC}/main.cpp.base ${SYNTH_SRC}/main.cpp
${SCC} ${SCC_SCRIPTS}/run_imp_window.tcl
imp_line: imp_window
echo "Done" > imp_window.tag
imp_line.tag: imp_window.tag
#sed -s 's/\\TCAB_NAME/threat_line/g' main.cpp.base >main.cpp
cp ${SYNTH_SRC}/main.cpp.base ${SYNTH_SRC}/main.cpp
${SCC} ${SCC_SCRIPTS}/run_imp_line.tcl
imp_marks:
echo "Done" > imp_line.tag
imp_marks.tag:
#sed -s 's/\\TCAB_NAME/ai_mraks/g' main.cpp.base >main.cpp
cp ${SYNTH_SRC}/main.cpp.base ${SYNTH_SRC}/main.cpp
${SCC} ${SCC_SCRIPTS}/run_imp_marks.tcl
imp_threat: imp_line imp_marks
echo "Done" > imp_marks.tag
imp_threat.tag: imp_line.tag imp_marks.tag
#sed -s 's/\\TCAB_NAME/ai_threats/g' main.cpp.base >main.cpp
cp ${SYNTH_SRC}/main.cpp.base ${SYNTH_SRC}/main.cpp
${SCC} ${SCC_SCRIPTS}/run_imp_threat.tcl
imp_adjacent:
echo "Done" > imp_threat.tag
imp_adjacent.tag:
cp ${SYNTH_SRC}/main.cpp.base ${SYNTH_SRC}/main.cpp
#sed -s 's/\\TCAB_NAME/ai_adjacent/g' main.cpp.base >main.cpp
${SCC} ${SCC_SCRIPTS}/run_imp_adjacent.tcl
imp_connect: imp_threat imp_adjacent
echo "Done" > imp_adjacent.tag
imp_connect.tag: imp_threat.tag imp_adjacent.tag
sed -s 's/\\TCAB_NAME/connect6ai_synth/g' ${SYNTH_SRC}/main.cpp.base >${SYNTH_SRC}/main.cpp
${SCC} ${SCC_SCRIPTS}/run_imp_connect.tcl
echo "Done" > imp_connect.tag
 
altera_synth:
cp -r ./imp_connect/rtl_package/ ./
94,4 → 100,4
rm -rf ./rtl_package/
ultraclean: altera_clean
rm -rf imp_line imp_marks imp_threat imp_choose imp_adjacent imp_connect imp_window Logs
rm -rf *.tag imp_line imp_marks imp_threat imp_choose imp_adjacent imp_connect imp_window Logs

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