OpenCores
URL https://opencores.org/ocsvn/connect-6/connect-6/trunk

Subversion Repositories connect-6

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  • This comparison shows the changes necessary to convert path
    /connect-6/trunk
    from Rev 6 to Rev 7
    Reverse comparison

Rev 6 → Rev 7

/BUILD_SCC/scc_scripts/run_imp_line.tcl
1,49 → 1,47
set SYNTH_SRC "synth_src"
set_project_params -directory ./
set_project_params -results myboard.txt
set_project_params -sources "${SYNTH_SRC}/connect6.cpp ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/main.cpp ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/util.cpp"
set_project_params -headers "${SYNTH_SRC}/connect6.h ${SYNTH_SRC}/connect6_synth.h ${SYNTH_SRC}/shared.h ${SYNTH_SRC}/threats.h ${SYNTH_SRC}/util.h"
set_project_params -sources "synth_src/connect6.cpp synth_src/connect6_synth.cpp synth_src/main.cpp synth_src/q.cpp synth_src/state.cpp synth_src/threats.cpp synth_src/util.cpp"
set_project_params -headers "synth_src/connect6.h synth_src/connect6_synth.h synth_src/q.hpp synth_src/shared.h synth_src/threats.h synth_src/util.h"
set_project_params -cache_result_files no
set_project_params -cache_data_files yes
 
if [file exists imp_line] { delete_implementation imp_line }
create_implementation imp_line
 
set_implementation_params -systemc_source no
#set_implementation_params -memory_return_path_external_delay 0%
#set_implementation_params -memory_forward_path_external_delay 0%
#set_implementation_params -instream_forward_path_external_delay 0%
set_implementation_params -import_tcab "imp_window"
set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID"
#set_implementation_params -outstream_return_path_external_delay 0%
set_implementation_params -appfiles "${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp"
set_implementation_params -memory_return_path_external_delay 0%
set_implementation_params -memory_forward_path_external_delay 0%
set_implementation_params -instream_forward_path_external_delay 0%
set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g"
set_implementation_params -outstream_return_path_external_delay 0%
set_implementation_params -appfiles "synth_src/state.cpp synth_src/threats.cpp"
set_implementation_params -proc threat_line
#set_implementation_params -memory_forward_boundary_register infer
set_implementation_params -memory_forward_boundary_register infer
set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive"
set_implementation_params -task_ii 441
set_implementation_params -techlib altera-cyclone3
#set_implementation_params -memory_return_boundary_register infer
set_implementation_params -cexec_args "-port /dev/ttyS0 -player L"
set_implementation_params -host_memory_access never,,,
set_implementation_params -device ep3c25-ea144-7
#set_implementation_params -force_independent_stalldomain_tcab yes
set_implementation_params -init_data_registers yes
#set_implementation_params -outstream_forward_path_external_delay 0%
set_implementation_params -memory_return_boundary_register infer
set_implementation_params -cexec_args "-port /dev/ttyS0 -player L"
set_implementation_params -host_memory_access never
set_implementation_params -outstream_forward_path_external_delay 0%
set_implementation_params -build_tcab yes
set_implementation_params -reset_data_registers yes
#set_implementation_params -instream_return_path_external_delay 0%
set_implementation_params -task_overlap 0
set_implementation_params -instream_return_path_external_delay 0%
set_implementation_params -simulator modelsim
set_implementation_params -clock_freq 100
#set_implementation_params -allow_latency_violation no
#set_implementation_params -user_supplied_fpga_memory_read_write_ports separate
#set_implementation_params -internal_blockram_memory_read_write_ports separate
 
 
setvar preprocess_auxopts "-L"
 
csim -golden -cexec_args "-port /dev/ttyS0 -player L"
csim -golden -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
preprocess
csim -preprocess -cexec_args "-port /dev/ttyS0 -player L"
csim -preprocess -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
schedule
csim -schedule -cexec_args "-port /dev/ttyS0 -player L"
csim -schedule -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
synthesize
#csim -synthesize -dump_memory_access_trace -sim_after_synth_phase 5
create_rtl_package
create_rtl_package -force
 
#set_implementation_params -simulator modelsim
#vlogsim -offline -dotasks 1-30
/BUILD_SCC/scc_scripts/run_imp_threat.tcl
1,52 → 1,51
set SYNTH_SRC "synth_src"
set_project_params -directory ./
set_project_params -results myboard.txt
set_project_params -sources "${SYNTH_SRC}/connect6.cpp ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/main.cpp ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/util.cpp"
set_project_params -headers "${SYNTH_SRC}/connect6.h ${SYNTH_SRC}/connect6_synth.h ${SYNTH_SRC}/shared.h ${SYNTH_SRC}/threats.h ${SYNTH_SRC}/util.h"
set_project_params -sources "synth_src/connect6.cpp synth_src/connect6_synth.cpp synth_src/main.cpp synth_src/q.cpp synth_src/state.cpp synth_src/threats.cpp synth_src/util.cpp"
set_project_params -headers "synth_src/connect6.h synth_src/connect6_synth.h synth_src/q.hpp synth_src/shared.h synth_src/threats.h synth_src/util.h"
set_project_params -cache_result_files no
set_project_params -cache_data_files yes
 
if [file exists imp_threat] { delete_implementation imp_threat }
create_implementation imp_threat
 
set_implementation_params -systemc_source no
#set_implementation_params -instream_boundary_register infer
set_implementation_params -memory_return_path_external_delay 0%
set_implementation_params -memory_forward_path_external_delay 0%
set_implementation_params -instream_forward_path_external_delay 0%
set_implementation_params -import_tcab "imp_line"
#imp_line"
set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID"
set_implementation_params -outstream_return_path_external_delay 0%
set_implementation_params -appfiles "${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp"
#set_implementation_params -instream_forward_path_external_delay 0%
set_implementation_params -import_tcab "imp_line "
set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g"
#set_implementation_params -outstream_return_path_external_delay 0%
set_implementation_params -appfiles "synth_src/state.cpp synth_src/threats.cpp"
set_implementation_params -proc ai_threats
set_implementation_params -memory_forward_boundary_register infer
set_implementation_params -techlib altera-cyclone3
set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive"
set_implementation_params -memory_return_boundary_register infer
set_implementation_params -cexec_args "-port /dev/ttyS0 -player L"
set_implementation_params -host_memory_access never
set_implementation_params -techlib altera-cyclone3
set_implementation_params -device ep3c25-ea144-7
set_implementation_params -force_independent_stalldomain_tcab yes
#set_implementation_params -always_enabled_ppa yes
set_implementation_params -init_data_registers yes
set_implementation_params -outstream_forward_path_external_delay 0%
#set_implementation_params -outstream_forward_path_external_delay 0%
#set_implementation_params -outstream_boundary_register infer
set_implementation_params -build_tcab yes
set_implementation_params -reset_data_registers yes
set_implementation_params -instream_return_path_external_delay 0%
set_implementation_params -task_overlap 0
#set_implementation_params -instream_return_path_external_delay 0%
set_implementation_params -simulator modelsim
set_implementation_params -clock_freq 100
set_implementation_params -allow_latency_violation no
#set_implementation_params -user_supplied_fpga_memory_read_write_ports separate
#set_implementation_params -internal_blockram_memory_read_write_ports separate
 
 
setvar schedule_auxopts "-j"
 
csim -golden -cexec_args "-port /dev/ttyS0 -player L"
csim -golden -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
preprocess
csim -preprocess -cexec_args "-port /dev/ttyS0 -player L"
csim -preprocess -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
schedule
csim -schedule -cexec_args "-port /dev/ttyS0 -player L"
csim -schedule -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
synthesize
#csim -synthesize -dump_memory_access_trace
#csim -synthesize with -dump_memory_access_trace -sim_after_synth_phase 5
create_rtl_package
#csim -synthesize
 
#set_implementation_params -simulator modelsim
#vlogsim -offline -dotasks 1-30
create_rtl_package -force
#vlogsim -online -detailed_perf_report
/BUILD_SCC/scc_scripts/run_imp_window.tcl
1,8 → 1,8
set SYNTH_SRC "synth_src"
set_project_params -directory ./
set_project_params -results myboard.txt
set_project_params -sources "${SYNTH_SRC}/connect6.cpp ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/main.cpp ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/util.cpp"
set_project_params -headers "${SYNTH_SRC}/connect6.h ${SYNTH_SRC}/connect6_synth.h ${SYNTH_SRC}/shared.h ${SYNTH_SRC}/threats.h ${SYNTH_SRC}/util.h"
set_project_params -sources "${SYNTH_SRC}/connect6.cpp ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/main.cpp ${SYNTH_SRC}/q.cpp ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/threat_line.cpp ${SYNTH_SRC}/util.cpp"
set_project_params -headers "${SYNTH_SRC}/connect6.h ${SYNTH_SRC}/connect6_synth.h ${SYNTH_SRC}/q.hpp ${SYNTH_SRC}/shared.h ${SYNTH_SRC}/threats.h ${SYNTH_SRC}/util.h"
 
if [file exists imp_window] { delete_implementation imp_window }
create_implementation imp_window
13,9 → 13,11
#set_implementation_params -instream_forward_path_external_delay 0%
set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID"
#set_implementation_params -outstream_return_path_external_delay 0%
set_implementation_params -appfiles "${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp"
set_implementation_params -appfiles "${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threat_line.cpp"
set_implementation_params -proc threat_window
#set_implementation_params -task_ii 9
#set_implementation_params -memory_forward_boundary_register infer
set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive"
set_implementation_params -techlib altera-cyclone3
#set_implementation_params -memory_return_boundary_register infer
set_implementation_params -cexec_args "-port /dev/ttyS0 -player L"
28,6 → 30,7
set_implementation_params -reset_data_registers yes
#set_implementation_params -instream_return_path_external_delay 0%
set_implementation_params -clock_freq 100
set_implementation_params -task_overlap infer
#set_implementation_params -allow_latency_violation no
#set_implementation_params -user_supplied_fpga_memory_read_write_ports separate
#set_implementation_params -internal_blockram_memory_read_write_ports separate
/BUILD_SCC/scc_scripts/run_imp_sort.tcl
0,0 → 1,48
set_project_params -directory ./
set_project_params -results myboard.txt
set_project_params -sources "synth_src/connect6.cpp synth_src/connect6_synth.cpp synth_src/main.cpp synth_src/q.cpp synth_src/state.cpp synth_src/threats.cpp synth_src/util.cpp"
set_project_params -headers "synth_src/connect6.h synth_src/connect6_synth.h synth_src/q.hpp synth_src/shared.h synth_src/threats.h synth_src/util.h"
set_project_params -cache_result_files no
set_project_params -cache_data_files yes
 
if [file exists imp_sort] { delete_implementation imp_sort }
create_implementation imp_sort
 
set_implementation_params -systemc_source no
set_implementation_params -instream_boundary_register infer
set_implementation_params -memory_return_path_external_delay 0%
set_implementation_params -memory_forward_path_external_delay 0%
set_implementation_params -instream_forward_path_external_delay 0%
set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID -g -g -g -g -g"
set_implementation_params -outstream_return_path_external_delay 0%
set_implementation_params -appfile synth_src/threats.cpp
set_implementation_params -proc streamsort
set_implementation_params -memory_forward_boundary_register infer
set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive"
set_implementation_params -techlib altera-cyclone4gx
set_implementation_params -device ep4cgx110c-fc23-7
set_implementation_params -memory_return_boundary_register infer
set_implementation_params -cexec_args "-port /dev/ttyS0 -player L"
set_implementation_params -host_memory_access never
set_implementation_params -init_data_registers yes
set_implementation_params -outstream_forward_path_external_delay 0%
set_implementation_params -outstream_boundary_register infer
set_implementation_params -build_tcab yes
set_implementation_params -reset_data_registers yes
set_implementation_params -task_overlap infer
set_implementation_params -instream_return_path_external_delay 0%
set_implementation_params -simulator modelsim
set_implementation_params -clock_freq 100
 
 
 
set_loop_params -ii 1
csim -golden -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
preprocess
csim -preprocess -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
schedule
csim -schedule -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
synthesize
create_rtl_package -force
 
/BUILD_SCC/scc_scripts/run_imp_adjacent.tcl
1,8 → 1,8
set SYNTH_SRC "synth_src"
set_project_params -directory ./
set_project_params -results myboard.txt
set_project_params -sources "${SYNTH_SRC}/connect6.cpp ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/main.cpp ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/util.cpp"
set_project_params -headers "${SYNTH_SRC}/connect6.h ${SYNTH_SRC}/connect6_synth.h ${SYNTH_SRC}/shared.h ${SYNTH_SRC}/threats.h ${SYNTH_SRC}/util.h"
set_project_params -sources "${SYNTH_SRC}/connect6.cpp ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/main.cpp ${SYNTH_SRC}/q.cpp ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/util.cpp"
set_project_params -headers "${SYNTH_SRC}/connect6.h ${SYNTH_SRC}/connect6_synth.h ${SYNTH_SRC}/q.hpp ${SYNTH_SRC}/shared.h ${SYNTH_SRC}/threats.h ${SYNTH_SRC}/util.h"
 
if [file exists imp_adjacent] { delete_implementation imp_adjacent }
create_implementation imp_adjacent
16,11 → 16,12
set_implementation_params -appfiles " ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp"
set_implementation_params -proc ai_adjacent
set_implementation_params -memory_forward_boundary_register infer
set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive"
set_implementation_params -memory_return_boundary_register infer
set_implementation_params -techlib altera-cyclone3
set_implementation_params -memory_return_boundary_register infer
set_implementation_params -device ep3c25-ea144-7
set_implementation_params -cexec_args "-port /dev/ttyS0 -player L"
set_implementation_params -host_memory_access never,,,
set_implementation_params -device ep3c25-ea144-7
set_implementation_params -init_data_registers yes
set_implementation_params -outstream_forward_path_external_delay 0%
set_implementation_params -build_tcab yes
/BUILD_SCC/scc_scripts/run_imp_connect.tcl
1,8 → 1,8
set SYNTH_SRC "synth_src"
set_project_params -directory ./
set_project_params -results myboard.txt
set_project_params -sources "${SYNTH_SRC}/connect6.cpp ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/main.cpp ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/util.cpp"
set_project_params -headers "${SYNTH_SRC}/connect6.h ${SYNTH_SRC}/connect6_synth.h ${SYNTH_SRC}/shared.h ${SYNTH_SRC}/threats.h ${SYNTH_SRC}/util.h"
set_project_params -sources "${SYNTH_SRC}/connect6.cpp ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/main.cpp ${SYNTH_SRC}/q.cpp ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/util.cpp"
set_project_params -headers "${SYNTH_SRC}/connect6.h ${SYNTH_SRC}/connect6_synth.h ${SYNTH_SRC}/q.hpp ${SYNTH_SRC}/shared.h ${SYNTH_SRC}/threats.h ${SYNTH_SRC}/util.h"
 
if [file exists imp_connect] { delete_implementation imp_connect }
create_implementation imp_connect
17,11 → 17,12
set_implementation_params -appfiles "${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/connect6_synth.cpp"
set_implementation_params -proc connect6ai_synth
set_implementation_params -memory_forward_boundary_register infer
set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive"
set_implementation_params -techlib altera-cyclone3
set_implementation_params -device ep3c25-ea144-7
set_implementation_params -memory_return_boundary_register infer
set_implementation_params -cexec_args "-port /dev/ttyS0 -player L"
set_implementation_params -host_memory_access never,,,
set_implementation_params -device ep3c25-ea144-7
set_implementation_params -init_data_registers yes
set_implementation_params -outstream_forward_path_external_delay 0%
set_implementation_params -build_tcab yes
36,6 → 37,8
 
 
setvar schedule_auxopts "-j"
 
csim -golden -cexec_args "-port /dev/ttyS0 -player L"
preprocess
csim -preprocess -cexec_args "-port /dev/ttyS0 -player L"
44,6 → 47,6
synthesize
#csim -synthesize -dump_memory_access_trace -sim_after_synth_phase 5
create_rtl_package
 
#vlogsim -online -detailed_perf_report
#set_implementation_params -simulator modelsim
#vlogsim -offline -dotasks 1-30
/BUILD_SCC/scc_scripts/run_imp_marks.tcl
1,8 → 1,9
set SYNTH_SRC "synth_src"
set_project_params -directory ./
set_project_params -results myboard.txt
set_project_params -sources "${SYNTH_SRC}/connect6.cpp ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/main.cpp ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/util.cpp"
set_project_params -headers "${SYNTH_SRC}/connect6.h ${SYNTH_SRC}/connect6_synth.h ${SYNTH_SRC}/shared.h ${SYNTH_SRC}/threats.h ${SYNTH_SRC}/util.h"
set_project_params -sources "synth_src/connect6.cpp synth_src/connect6_synth.cpp synth_src/main.cpp synth_src/q.cpp synth_src/state.cpp synth_src/threats.cpp synth_src/util.cpp"
set_project_params -headers "synth_src/connect6.h synth_src/connect6_synth.h synth_src/q.hpp synth_src/shared.h synth_src/threats.h synth_src/util.h"
set_project_params -cache_result_files no
set_project_params -cache_data_files yes
 
if [file exists imp_marks] { delete_implementation imp_marks }
create_implementation imp_marks
11,37 → 12,35
set_implementation_params -memory_return_path_external_delay 0%
set_implementation_params -memory_forward_path_external_delay 0%
set_implementation_params -instream_forward_path_external_delay 0%
set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID"
set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID -g -g -g -g"
set_implementation_params -outstream_return_path_external_delay 0%
set_implementation_params -appfiles "${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp"
set_implementation_params -appfiles "synth_src/state.cpp synth_src/threats.cpp"
set_implementation_params -proc ai_marks
set_implementation_params -memory_forward_boundary_register infer
set_implementation_params -techlib altera-cyclone3
set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive"
set_implementation_params -techlib altera-cyclone4gx
set_implementation_params -device ep4cgx110c-fc23-7
set_implementation_params -memory_return_boundary_register infer
set_implementation_params -cexec_args "-port /dev/ttyS0 -player L"
set_implementation_params -host_memory_access never,,,
set_implementation_params -device ep3c25-ea144-7
set_implementation_params -force_independent_stalldomain_tcab yes
set_implementation_params -host_memory_access never
set_implementation_params -init_data_registers yes
set_implementation_params -outstream_forward_path_external_delay 0%
set_implementation_params -build_tcab yes
set_implementation_params -reset_data_registers yes
set_implementation_params -init_data_registers yes
set_implementation_params -task_overlap 0
set_implementation_params -instream_return_path_external_delay 0%
set_implementation_params -simulator modelsim
set_implementation_params -clock_freq 100
#set_implementation_params -user_supplied_fpga_memory_read_write_ports separate
#set_implementation_params -internal_blockram_memory_read_write_ports separate
 
 
 
set_loop_params -ii 3
csim -golden -cexec_args "-port /dev/ttyS0 -player L"
csim -golden -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
preprocess
csim -preprocess -cexec_args "-port /dev/ttyS0 -player L"
csim -preprocess -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
schedule
csim -schedule -cexec_args "-port /dev/ttyS0 -player L"
csim -schedule -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
synthesize
#csim -synthesize -dump_memory_access_trace
create_rtl_package
 
#set_implementation_params -simulator modelsim
#vlogsim -offline -dotasks 1-30
/BUILD_SCC/scc_scripts/run_imp_threat_flat.tcl
1,8 → 1,8
set SYNTH_SRC "synth_src"
set_project_params -directory ./
set_project_params -results myboard.txt
set_project_params -sources "${SYNTH_SRC}/connect6.cpp ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/main.cpp ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/util.cpp"
set_project_params -headers "${SYNTH_SRC}/connect6.h ${SYNTH_SRC}/connect6_synth.h ${SYNTH_SRC}/shared.h ${SYNTH_SRC}/threats.h ${SYNTH_SRC}/util.h"
set_project_params -sources "${SYNTH_SRC}/connect6.cpp ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/main.cpp ${SYNTH_SRC}/q.cpp ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/util.cpp"
set_project_params -headers "${SYNTH_SRC}/connect6.h ${SYNTH_SRC}/connect6_synth.h ${SYNTH_SRC}/q.hpp ${SYNTH_SRC}/shared.h ${SYNTH_SRC}/threats.h ${SYNTH_SRC}/util.h"
 
if [file exists imp_threat_flat] { delete_implementation imp_threat_flat }
create_implementation imp_threat_flat
18,6 → 18,7
set_implementation_params -appfiles "${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp"
set_implementation_params -proc ai_threats
set_implementation_params -memory_forward_boundary_register infer
set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive"
set_implementation_params -techlib altera-cyclone3
set_implementation_params -memory_return_boundary_register infer
set_implementation_params -cexec_args "-port /dev/ttyS0 -player L"
/BUILD_SCC/scc_scripts/run_imp_choose.tcl
1,8 → 1,8
set SYNTH_SRC "synth_src"
set_project_params -directory ./
set_project_params -results myboard.txt
set_project_params -sources "${SYNTH_SRC}/connect6.cpp ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/main.cpp ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/util.cpp"
set_project_params -headers "${SYNTH_SRC}/connect6.h ${SYNTH_SRC}/connect6_synth.h ${SYNTH_SRC}/shared.h ${SYNTH_SRC}/threats.h ${SYNTH_SRC}/util.h"
set_project_params -sources "${SYNTH_SRC}/connect6.cpp ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/main.cpp ${SYNTH_SRC}/q.cpp ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/util.cpp"
set_project_params -headers "${SYNTH_SRC}/connect6.h ${SYNTH_SRC}/connect6_synth.h ${SYNTH_SRC}/q.hpp ${SYNTH_SRC}/shared.h ${SYNTH_SRC}/threats.h ${SYNTH_SRC}/util.h"
 
if [file exists imp_choose] { delete_implementation imp_choose }
create_implementation imp_choose
16,6 → 16,7
set_implementation_params -appfiles "${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/connect6_synth.cpp"
set_implementation_params -proc aimoves_choose
set_implementation_params -memory_forward_boundary_register infer
set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive"
set_implementation_params -techlib altera-cyclone3
set_implementation_params -memory_return_boundary_register infer
set_implementation_params -cexec_args "-port /dev/ttyS0 -player L"
/BUILD_SCC/DE2/async_receiver_altera.v
3,8 → 3,8
output RxD_data_ready; // onc clock pulse when RxD_data is valid
output [7:0] RxD_data;
 
parameter ClkFrequency = 50000000; // 50MHz
//parameter ClkFrequency = 27000000; // 27MHz
//parameter ClkFrequency = 50000000; // 50MHz
parameter ClkFrequency = 27000000; // 27MHz
parameter Baud = 115200;
 
// We also detect if a gap occurs in the received stream of characters
/BUILD_SCC/DE2/async_transmitter_altera.v
3,8 → 3,8
input [7:0] TxD_data;
output TxD, TxD_busy;
 
parameter ClkFrequency = 50000000; // 50MHz
//parameter ClkFrequency = 27000000; // 27MHz
//parameter ClkFrequency = 50000000; // 50MHz
parameter ClkFrequency = 27000000; // 27MHz
parameter Baud = 115200;
 
// Baud generator
/BUILD_SCC/DE2/DE2.v
72,7 → 72,7
 
wire mTXD_Done_not;
RS232_Controller u1_bis( .iDATA(mTXD_DATA),.iTxD_Start(mTXD_Start),.oTxD_Busy(mTXD_Done_not),
.oDATA(mRXD_DATA),.oRxD_Ready(mRXD_Ready),.iCLK(OSC_50),.RST_n(KEY[0]),
.oDATA(mRXD_DATA),.oRxD_Ready(mRXD_Ready),.iCLK(OSC_27),.RST_n(KEY[0]),
.oTxD(UART_TXD),.iRxD(UART_RXD));
assign mTXD_Done = !mTXD_Done_not;
assign LED_RED[9] = mTXD_Done_not;
88,7 → 88,7
.iRXD_DATA(mRXD_DATA),.iRXD_Ready(mRXD_Ready),
.oTXD_DATA(mTXD_DATA),.oTXD_Start(mTXD_Start),.iTXD_Done(mTXD_Done),
// Control
.iCLK(OSC_50),.iRST_n(KEY[0]), .oAI_RSTn(mAI_RSTn),
.iCLK(OSC_27),.iRST_n(KEY[0]), .oAI_RSTn(mAI_RSTn),
//AI
.oAI_DATA(DATA_to_AI),
.iAI_DATA(DATA_from_AI),
103,7 → 103,7
.oAI_Done(mAI_Done),
// Control
.iCLK(OSC_50),.iRST_n(mAI_RSTn) );
.iCLK(OSC_27),.iRST_n(mAI_RSTn) );
wire [63:0] CMD_Tmp;
 
//assign mSEG7_DIG = { CMD_Tmp[31:28],CMD_Tmp[27:24],CMD_Tmp[23:20],CMD_Tmp[19:16],
/BUILD_SCC/synth_src/state.cpp
27,9 → 27,15
//#include <stdio.h>
//#include <string.h>
//#include <math.h>
#include "./shared.h"
//#include <iostream>
#include "shared.h"
//#include "q.hpp"
//#include "connectk.h"
 
#ifdef PICO_SYNTH
//#include "pico.h"
#endif
//#include "./q.hpp"
using namespace std;
/*
* Allocation chain
*/
46,6 → 52,7
* K & R. Not a great generator, but fast, and good enough for my needs. */
 
 
//int ready=0;
void my_srandom(int seed,unsigned int *current_random)
{
*current_random = (unsigned int)seed;
175,7 → 182,8
} else
moves->data[i].weight += move->weight;
}
 
//FIFO(moves_fifo,AIMove);
//#pragma fifo_length moves_fifo 361
void aimoves_append(AIMoves *moves, const AIMove *move)
{
int i;
182,6 → 190,7
 
if (move->x >= board_size || move->y >= board_size)
return;
#pragma num_iterations(0,150,361)
for (i = 0; i < moves->len; i++) {
AIMove *aim = moves->data + i;
 
196,6 → 205,7
return;
}
moves->data[moves->len++] = *move;
//if(!moves_fifo.full()) moves_fifo.push(*move);
}
 
int aimoves_compare(const void *a, const void *b)
203,24 → 213,49
return ((AIMove*)b)->weight - ((AIMove*)a)->weight;
}
 
int aimoves_choose(AIMoves *moves, AIMove *move)
int aimoves_choose(AIMoves *moves, AIMove *move,unsigned int *index)
{
//#pragma read_write_ports moves.data combined 3
//#pragma internal_blockram moves
//#pragma no_memory_analysis moves
int i = 0, top = 0;
 
int i = 0;
int top;
AIMoves moves1;
#pragma bitsize i 4
if (!moves || !moves->len)
return 0;
aimoves_sort(moves);
for (top = 0; top < moves->len &&
moves->data[top].weight == moves->data[0].weight; top++);
if (top)
//i = my_irand(top,current_random);//g_random_int_range(0, top);
i=0;
*move = moves->data[i];
return 1;
// if (!moves || !moves->len)
// return 0;
// //aimoves_sort(moves);
// for (top = 0; top < moves->len &&
// moves->data[top].weight == moves->data[0].weight; top++);
// if (top)
// //i = my_irand(top,current_random);//g_random_int_range(0, top);
// i=0;
//
// *move = moves->data[i];
// return 1;
/*---------------------------------------
Rewritten for Hardware
---------------------------------------*/
//for (top = 0; top < moves->len; top++){
// if(top==0) {
// if (!moves)
// return 0;
// }
// if(moves->data[index[top]].weight != moves->data[index[0]].weight){
// *move = moves->data[index[i]];
// return 1;
// }
// if(top==moves->len-1) {
// *move = moves->data[index[i]];
// return 1;
// }
//}
// return 0;
if(!moves|| !moves->len) return 0;
else {*move=moves->data[index[i]];return 1;}
 
 
}
//
//void aimoves_crop(AIMoves *moves, unsigned int n)
389,6 → 424,9
for(j=0;j<(n-(i+1));j++)
if(list[j].weight < list[j+1].weight)
swap(&list[j],&list[j+1]);
//cout<<"BUBBLESORT"<<":"<<n<<endl;
//for(i=0;i<n;i++) cout<<list[i].weight<<",";
//cout<<endl;
}
//taken from http://cprogramminglanguage.net/c-bubble-sort-source-code.aspx
void aimoves_sort(AIMoves *moves)
395,6 → 433,7
{
//qsort(moves->data, moves->len, sizeof (AIMove), aimoves_compare);
bublesort(moves->data,moves->len);
//streamsort(moves->data,moves->len);
}
 
/BUILD_SCC/synth_src/connect6_synth.cpp
13,7 → 13,9
//#include "connect6.h"
//#include<stdio.h>
#include "./shared.h"
//#include "pico.h"
//#ifdef PICO_SYSC_SIM
#include "pico.h"
//#endif
 
// Subtract this many points for moves at the edges.
#define EDGEPENALTY 5
108,8 → 110,12
// aimoves_choose(moves, move);
// }
//}
int id;
int connect6ai_synth(int firstmove,char movein[8], char colour, char moveout[8]){
//int id= PICO_initialize_PPA(ai_threats);
//#ifdef PICO_SYSC_SIM
//id= PICO_initialize_PPA(ai_threats);
//PICO_set_task_overlap(id, 2);
//#endif
#pragma bitsize firstmove 17
char moveoutm[8];
#pragma internal_blockram moveoutm
119,6 → 125,7
//#pragma read_write_ports board.data combined 2
//#pragma preserve_array myboard.data
#pragma internal_blockram myboard
//#pragma multi_buffer myboard 2
//#pragma no_memory_analysis myboard
static unsigned int current_random = 10;
AIMove move,move_threat,move_adj;
163,6 → 170,8
int i;
#pragma bitsize i 6
 
//#pragma num_iterations(1,2,2)
//#pragma unroll
for(i=myboard.moves_left;i>0;i--){
//aimoves_free(&moves);
move.x=-1;
244,7 → 253,10
// /// Convert the int coordinates to corresponding ASCII chars
//move_to_ascii(move.x+1,move.y+1,&moveout[4]);
//}
//#ifdef PICO_SYSC_SIM
//PICO_sync_task(id, 1);
//PICO_finalize_PPA(id);
//#endif
return 0;
}
 
/BUILD_SCC/synth_src/main.cpp
23,8 → 23,8
#include "util.h"
#include "connect6.h"
#include "connect6_synth.h"
//#include "pico.h"
//#include "shared.h"
#include "pico.h"
#include "shared.h"
 
// The AI has as much time as it wants, but moves after 1 second. Default is to wait 2 seconds
#define AI_WAIT_TIME 0.1
33,7 → 33,7
#define MOVE_TIME_LIMIT 0.1
 
using namespace std;
 
extern "C" int main(int argc, char **argv);
// commandline option: -port <serialport>
int main(int argc, char **argv){
//for verification two runs and a reference board
53,7 → 53,7
// Get software AI's colour
char AI_colour = select_AI_colour(argc,argv);
char FPGA_colour;
//int id = PICO_initialize_PPA(connect6ai_synth);
int id = PICO_initialize_PPA(connect6ai_synth);
// Take care of the first few moves (including sending the colour)
if (AI_colour == 'D'){
FPGA_colour = 'L';
219,6 → 219,7
connect6ai(board,AI_colour,move);
movecount++;
cout<<"AI MOVE: "<<move[0]<<move[1]<<move[2]<<move[3]<<endl;
//if(movecount >=20) return 0 ; //reducing length of simulation
winning_colour = check_for_win(board);
if (winning_colour == AI_colour){
cout<<"AI has won! " << movecount << " moves " << "Exiting."<<endl;
269,7 → 270,7
print_board_file(board);
}
 
//PICO_finalize_PPA(id);
PICO_finalize_PPA(id);
 
return 0;
 
/BUILD_SCC/synth_src/threats.cpp
23,21 → 23,116
//#include "config.h"
//#include <math.h>
//#include <glib->h>
//#include <iostream>
#include "./shared.h"
//#include "./q.hpp"
#include "pico.h"
//#include <stdio.h>
 
/* Bits per threat level */
#define BITS_PER_THREAT 6
 
//FIFO(x,int);
//#pragma fifo_length x 24
//#pragma no_inter_loop_stream_analysis pico_stream_input_x
//#pragma no_inter_loop_stream_analysis pico_stream_output_x
//#pragma no_inter_task_stream_analysis pico_stream_input_x
//#pragma no_inter_task_stream_analysis pico_stream_output_x
/*--------------------------------------------------------------------*/
#ifdef PICO_SYNTH
#define Q_ASSERT(_cond, _msg)
//#include <iostream>
//#include "pico.h"
//#include "q.hpp"
//#include "./shared.h"
using namespace std;
#else
/* not synthesizable */
#include <iostream>
#include <sstream>
#include <string>
#include <assert.h>
 
typedef struct {
int threat[2];
PIECE turn[2];
} Line;
typedef struct{
int data[MAX_CONNECT_K + 1][2];
}threat_count_array;
static void debug_assert (bool cond, char * msg) {
if (!cond) {
printf("assert failed: %s\n", msg);
assert(0);
}
}
 
#define Q_ASSERT(_cond, _msg) debug_assert(_cond, _msg)
#endif
#define max_size 361
#define ptr_bw 32
//FIFO(queue,AIMove);
//#pragma no_inter_loop_stream_analysis pico_stream_input_queue
//#pragma no_inter_loop_stream_analysis pico_stream_output_queue
//#pragma no_inter_task_stream_analysis pico_stream_input_queue
//#pragma no_inter_task_stream_analysis pico_stream_output_queue
 
//FIFO(queue,AIMove);
//FIFO_INTERFACE(queue,AIMove);
//#pragma fifo_length pico_stream_input_queue 800
//#pragma fifo_length pico_stream_output_queue 800
//#pragma read_write_port queue separate
//#pragma bandwidth pico_stream_input_queue 1
//#pragma bandwidth pico_stream_output_queue 1
//////template <class tp=AIMove, int max_size=128, int ptr_bw=32>
////
//// /* pop front of queue, returning the front data */
//// /* q is corrupted if pop when empty */
//// AIMove q::pop (){
//// /* assert that before pop, queue is not empty (underflow check) */
//// Q_ASSERT((!wrapped && (head < tail)) || (wrapped && (head >= tail)),
//// "queue underflowed");
//// AIMove d = pico_stream_input_queue();
//// //cout <<"pop: "<<head<<":"<<tail<<":"<<wrapped<<endl;
//// if (head == max_size-1) {
//// head = 0;
//// wrapped = false;
//// } else {
//// head = head + 1;
//// }
//// return d;
//// }
////
//// /* push data into back of queue */
//// /* q is corrupted if push when full */
//// void q::push (AIMove d){
//// pico_stream_output_queue(d);
//// if (tail == max_size-1) {
//// tail = 0;
//// wrapped = true;
//// } else {
//// tail = tail + 1;
//// }
//// /* assert that after push, queue is not empty (overflow check) */
//// Q_ASSERT((!wrapped && (head < tail)) || (wrapped && (head >= tail)),
//// "Queue overflowed") ;
//// //cout <<"push: "<<head<<":"<<tail<<":"<<wrapped<<endl;
//// }
////
//// /* return current size of the queue */
//// int q::size (){
//// if (wrapped) {
//// return (max_size - head) + (tail - 0);
//// } else {
//// return tail - head;
//// }
//// }
/////*--------------------------------------------------------------------*/
////void test(int ready){
//// int i;
//// //for (i=0;i<10;i++) if(ready>1) pico_stream_input_x();
//// //for (i=0;i<10;i++) {if(!moves_fifo1.empty()) moves_fifo1.pop(); }
//// AIMove m;
//// while(1) {
//// if(ready>1) m=pico_stream_input_queue();
//// if(m.weight==-1) break;
//// }
////}
////q moves_fifo1;
 
static AIWEIGHT threat_bits(int threat, PIECE type, Board *b)
/* Bit pack the threat value */
{
97,7 → 192,8
return 0;
 
/* Push forward the maximum and find the window type */
#pragma unroll
//#pragma unroll
//#pragma num_iterations(1,3,6)
for (maximum = 1; maximum < connect_k; maximum++) {
p = piece_at(b, x + dx * maximum, y + dy * maximum);
if (p == PIECE_ERROR)
113,7 → 209,8
maximum--;
 
/* Try to push the entire window back */
#pragma unroll
//#pragma unroll
//#pragma num_iterations(1,3,6)
for (minimum = -1; minimum > -connect_k; minimum--) {
p = piece_at(b, x + dx * minimum, y + dy * minimum);
if (p == PIECE_ERROR || piece_empty(p))
135,6 → 232,8
/* Push back minimum if we haven't formed a complete window, this window
can't be a double */
if (maximum - minimum < connect_k - 1) {
//#pragma unroll
//#pragma num_iterations(1,3,6)
for (minimum--; minimum > maximum - connect_k; minimum--) {
p = piece_at(b, x + dx * minimum, y + dy * minimum);
if (p == PIECE_ERROR)
157,7 → 256,7
return 0;
}
 
/*static*/ AIWEIGHT threat_line(int x, int y, int dx, int dy,Board *b,Board *bwrite,AIMoves *moves,int k)
/*static*/ AIWEIGHT threat_line(int x, int y, int dx, int dy,Board *b,Board *bwrite,int k,int loop_bound)
{
//#pragma read_write_ports threat_counts.data combined 2
165,8 → 264,6
//#pragma no_memory_analysis threat_counts
//#pragma read_write_ports b.data combined 2
#pragma internal_blockram b
#pragma internal_blockram bwrite
//#pragma read_write_ports b.data separate 1 readonly 2 writeonly
//#pragma no_memory_analysis b
/* This is the line of threats currently being processed */
245,10 → 342,16
return weight;
}
 
FIFO(queue,AIMove);
//FIFO_INTERFACE(queue,AIMove);
#pragma fifo_length pico_stream_input_queue 800
#pragma fifo_length pico_stream_output_queue 800
#pragma bandwidth pico_stream_input_queue 1
#pragma bandwidth pico_stream_output_queue 1
/*AIMoves*/int ai_threats(Board *board,AIMove *move)
{
//#pragma read_write_ports board.data combined 2
#pragma internal_blockram board
//#pragma internal_blockram board
//#pragma no_memory_analysis board
 
//#pragma internal_blockram move
258,13 → 361,15
/*static*/ Board b;//={0,0,0,0,0,0,0,0,0,0,0,{{0}}} ;//= NULL;
//#pragma read_write_ports b.data combined 2
#pragma internal_blockram b
//#pragma multi_buffer b 2
//#pragma read_write_ports b.data separate 1 readonly 2 writeonly
//#pragma no_memory_analysis b
/*static*/ Board bwrite;//={0,0,0,0,0,0,0,0,0,0,0,{{0}}} ;//= NULL;
//#pragma read_write_ports b.data combined 2
#pragma internal_blockram bwrite
//#pragma multi_buffer bwrite 2
//#pragma no_memory_analysis b
/*static*/ AIMoves moves;//={{0,0,0,{{0,0,0}}}};
/*static*/ AIMoves moves;//={0,0,0,{{0,0,0}}};
//#pragma read_write_ports moves.data combined 3
#pragma internal_blockram moves
//#pragma no_memory_analysis moves
306,6 → 411,8
/*---------------------------------------------------------------------------*/
//rewritten for hardware
/*---------------------------------------------------------------------------*/
//int id= PICO_initialize_PPA(threat_line);
//PICO_set_task_overlap(id, 2);
int j;
int arg1,arg2,arg3,arg4,loop_bound,loop_begin;
int k=0;
408,16 → 515,37
}
 
 
u_sum += threat_line(arg1, arg2, arg3, arg4,&b,&bwrite,&moves,k);
u_sum += threat_line(arg1, arg2, arg3, arg4,&b,&bwrite,k,loop_bound);
}
}
//PICO_sync_task(id, 1);
//PICO_finalize_PPA(id);
/*---------------------------------------------------------------------------*/
//board_copy(&b,&b_marks);
unsigned int index[max_size]={0};
#pragma bitsize index 9
#pragma internal_fast index
AIMoves moves1;
#pragma internal_blockram moves1
/*moves = */ ai_marks(&bwrite, PIECE_THREAT(1),&moves);
moves.utility = u_sum;
if (!aimoves_choose(&moves, move))
//test(ready);
streamsort(&moves1,&index[0]);
//moves1.utility = u_sum;
//moves.utility = u_sum;
/*----------------------------
rewritten for hardware
----------------------------*/
//if (!aimoves_choose(&moves1, move))
// return 0;
//else return 1;
int ret_val;
ret_val=aimoves_choose(&moves1, move,&index[0]);
if (!ret_val)
return 0;
else return 1;
/*----------------------------
end rewritten for hardware
----------------------------*/
//board_free(b);
//return moves;
//return 0;
516,15 → 644,110
//AIMoves moves[361];
AIMove move;
PIECE p;
//moves_fifo.resoet();
AIMove m;
#pragma num_iterations(19,19,19)
for (move.y = 0; move.y < board_size; move.y++)
for (move.x = 0; move.x < board_size; move.x++)
#pragma num_iterations(19,19,19)
for (move.x = 0; move.x < board_size; move.x++){
if ((p = piece_at(b, move.x, move.y)) >= minimum) {
move.weight = p - PIECE_THREAT0;
aimoves_set(moves, &move);
}
pico_stream_output_queue(move);
//cout<<"push"<<move.weight<<endl;
//ready=ready+1;
//cout<<"READY"<<*ready<<endl;
}else {
m.weight =-100;
pico_stream_output_queue(m);
//cout<<"push"<<m.weight<<endl;
}
//if((move.y == board_size-1) && (move.x == board_size-1)){
// m.weight=-1;m.x=-1;m.y=-1;
// /*if((ready))*/ {pico_stream_output_queue(m);/*cout<<"push_finish"<<m.weight<<endl;*/}
//
//}
}
//moves_fifo.active=0;
//return moves;
int i;
//for (i=0;i<10;i++) {*ready=i;pico_stream_output_x(i); }
//for (i=0;i<10;i++) {if(!moves_fifo1.full()) moves_fifo1.push(m); }
//for (i=0;i<10;i++) {
// *ready=i;pico_stream_output_queue(m);
// if(i==9){
// m.weight=-1;
// pico_stream_output_queue(m);
// }
//
// }
}
 
void streamsort(AIMoves *moves,unsigned int *index){
/* Insertion sort for streaming*/
AIMove val;
AIMove data[361]={{-1},{-1},{-1}};
//unsigned int index[361];
#pragma bitsize index 9
#pragma internal_fast index
int i,j,k;
unsigned int len=0;
moves->data[0].weight=-100;
// while(1) {
// if(!moves_fifo.empty()){
// val=moves_fifo.pop();
// for(i=0;i<len;i++){
// if (list[i].weight < val.weight){
// for(j=len-1;j>i-1;j--){
// list[j+1]=list[j];
// }
// break;
// }
// }
// list[i]=val;
// len++;
// }
// else break;
// //if(!moves_fifo.active && moves_fifo.empty()) break;
// }
//while(1) {
//int count=0;
#pragma num_iterations(1,150,1362)
for(k=0;k<1362;k++){
//count++;
//cout<<count<<endl;
if (k>1000){
//if(ready>5){
val=pico_stream_input_queue();
//cout<<"popped"<<","<<val.weight<<" "<<val.x<<" "<<val.y<<endl;
if(val.weight==-1) {moves->len=len;break;}
else if(val.weight==-100) continue;
#pragma num_iterations(0,150,361)
for(i=0;i<len;i++){
if (moves->data[index[i]].weight < val.weight){
for(j=len-1;j>i-1;j--){
//moves->data[j+1]=moves->data[j];
index[j+1]=index[j];
}
break;
}
}
index[i]=len;
moves->data[len]=val;
len++;
//cout<<"STREAMSORT"<<":";
//}
/*else*/ //{moves->len=len;break;}
}
}
moves->len=len;
//cout<<"STREAMSORT"<<":"<<moves->len<<endl;
//for(i=0;i<len;i++) cout<<moves->data[i].weight<<",";
//cout<<endl;
//for(i=0;i<len;i++) cout<<moves->data[index[i]].weight<<",";
//cout<<endl;
}
static gboolean is_adjacent( Board *b, BCOORD x, BCOORD y, int dist)
{
int dx, dy, count;
551,10 → 774,14
 
move.weight = AIW_NONE;
//moves = aimoves_new();
for (move.y = 0; move.y < board_size; move.y++)
for (move.x = 0; move.x < board_size; move.x++)
#pragma num_iterations(1,9,19)
for (move.y = 0; move.y < board_size; move.y++){
#pragma num_iterations(1,9,19)
for (move.x = 0; move.x < board_size; move.x++){
if (is_adjacent(b, move.x, move.y, dist))
aimoves_append(moves, &move);
}
}
//aimoves_shuffle(moves,current_random);
//return moves;
}
572,12 → 799,13
//#pragma internal_blockram moves
//#pragma no_memory_analysis moves
//AIMove move;
unsigned int index[1]={0};
//AIMoves *moves;
moves.len=0;
/* Get all open tiles adjacent to any piece */
/*moves =*/ enum_adjacent(b, 1,&moves,current_random);
if (moves.len){
aimoves_choose(&moves, move);
aimoves_choose(&moves, move,&index[0]);
return ;//moves;
}
/BUILD_SCC/synth_src/shared.h
1,4 → 1,5
 
#ifndef SHARED_H
#define SHARED_H
/*
 
connectk -- a program to play the connect-k family of games
23,7 → 24,7
//#ifndef TRUE
#define TRUE 1
#define FALSE 0
#define NULL ((void*)0)
//#define NULL ((void*)0)
//#endif
//#ifndef __G_TYPES_H__
typedef unsigned int gboolean;
30,6 → 31,7
#pragma bitsize gboolean 1
typedef int gsize;
//#endif
#include "pico.h"
 
 
/*
304,6 → 306,22
} AIMoves;
/* An array type for holding move lists */
 
 
typedef struct {
int threat[2];
PIECE turn[2];
} Line;
typedef struct{
int data[MAX_CONNECT_K + 1][2];
}threat_count_array;
 
 
 
 
 
 
 
 
AllocChain *aimoves_alloc(AllocChain *data);
#define aimoves_new() ((AIMoves*)achain_new(&aimoves_root, aimoves_alloc))
//#define aimoves_free(m) achain_free((AllocChain*)(m))
325,7 → 343,7
///////////* Add an AIMove to an AIMoves array; existing moves weights will be
////////// overwritten */
//////////
int aimoves_choose(AIMoves *moves, AIMove *move);
int aimoves_choose(AIMoves *moves, AIMove *move, unsigned int *index);
/* Will choose one of the best moves from a GArray of AIMove structures at
random. Returns non-zero if a move was chosen or zero if a move could not
be chosen for some reason. */
400,6 → 418,7
/*AIMoves **/ void enum_adjacent(Board *b, int dist,AIMoves *moves,unsigned int current_random);
/* Enumerate empty tiles at most dist away from some other piece on the board */
 
void streamsort(AIMoves *moves,unsigned int *index);
/*AIMoves **/void ai_marks(Board *b, PIECE min,AIMoves *moves);
/* Fills a moves list with tiles marked at least PIECE_THREAT(min) */
 
448,7 → 467,14
void my_srandom(int seed,unsigned int *current_random);
int my_irand(int imax,unsigned int current_random);
//void backup_move(Board *board, AIMoves *moves,AIMove *move);
AIWEIGHT threat_line(int x, int y, int dx, int dy,Board *b,Board *bwrite,AIMoves *moves,int k);
int threat_window(int x, int y, int dx, int dy,
PIECE *ptype, int *pdouble,Board *b);
//AIWEIGHT threat_line(int x, int y, int dx, int dy,Board *b,Board *bwrite,int k,int loop_bound);
//int threat_window(int x, int y, int dx, int dy,
// PIECE *ptype, int *pdouble,Board *b);
int connect6ai_synth(int firstmove,char movein[8], char colour, char moveout[8]);
//extern "C" AIMove pico_stream_input_queue();
//extern "C" void pico_stream_output_queue(AIMove);
//extern "C" AIMove pico_ips_fifo_read_queue();
//extern "C" void pico_ips_fifo_write_queue(AIMove);
//extern int id;
//extern int ready;
#endif
/BUILD_SCC/synth_src/main.cpp.base
23,8 → 23,8
#include "util.h"
#include "connect6.h"
#include "connect6_synth.h"
//#include "pico.h"
//#include "shared.h"
#include "pico.h"
#include "shared.h"
 
// The AI has as much time as it wants, but moves after 1 second. Default is to wait 2 seconds
#define AI_WAIT_TIME 0.1
33,7 → 33,7
#define MOVE_TIME_LIMIT 0.1
 
using namespace std;
 
extern "C" int main(int argc, char **argv);
// commandline option: -port <serialport>
int main(int argc, char **argv){
//for verification two runs and a reference board
53,7 → 53,7
// Get software AI's colour
char AI_colour = select_AI_colour(argc,argv);
char FPGA_colour;
//int id = PICO_initialize_PPA(\TCAB_NAME);
int id = PICO_initialize_PPA(connect6ai_synth);
// Take care of the first few moves (including sending the colour)
if (AI_colour == 'D'){
FPGA_colour = 'L';
219,6 → 219,7
connect6ai(board,AI_colour,move);
movecount++;
cout<<"AI MOVE: "<<move[0]<<move[1]<<move[2]<<move[3]<<endl;
if(movecount >=20) return 0 ; //reducing length of simulation
winning_colour = check_for_win(board);
if (winning_colour == AI_colour){
cout<<"AI has won! " << movecount << " moves " << "Exiting."<<endl;
269,7 → 270,7
print_board_file(board);
}
 
//PICO_finalize_PPA(id);
PICO_finalize_PPA(id);
 
return 0;
 
/BUILD_SCC/synth_src/util.cpp
27,22 → 27,22
 
 
char select_AI_colour (int argc, char **argv){
char ai_colour;
char ai_colour='L';
int i;
//cout<<"Please enter referee AI's colour. L or D"<<endl;
//cin >> ai_colour;
for(i=0;i<argc; i++){
if((strcmp(argv[i],"-player")==0) && (i< (argc+1)) ){
ai_colour= *argv[i+1];
}
}
// cout<<"Please enter referee AI's colour. L or D"<<endl;
// cin >> ai_colour;
// for(i=0;i<argc; i++){
// if((strncmp(argv[i],"-player",7)==0) && (i< (argc+1)) ){
// ai_colour= *argv[i+1];
// }
// }
 
while (ai_colour != 'L' && ai_colour != 'D'){
cout<<"Invalid colour. Single character L or D"<<endl;
cin >> ai_colour;
}
// while (ai_colour != 'L' && ai_colour != 'D'){
// cout<<"Invalid colour. Single character L or D"<<endl;
// cin >> ai_colour;
// }
 
cout<<"AI is playing as "<<ai_colour<<endl;
// cout<<"AI is playing as "<<ai_colour<<endl;
return ai_colour;
}
 
54,7 → 54,7
bool cmd_line_port_set = false;
 
for(i=0;i<argc; i++){
if((strcmp(argv[i],"-port")==0) && (i< (argc+1)) ){
if((strncmp(argv[i],"-port",5)==0) && (i< (argc+1)) ){
com_port = argv[i+1];
cmd_line_port_set = true;
}
/BUILD_SCC/Makefile
1,5 → 1,5
GCC=g++
 
GCC=g++ -g -DPICO_SYNTH -I/opt/synopsys/scc/synphonycc-fpga-vE-2010.12-SP1/pico/simu/include -I./synth_src
GCC_LINK= g++ -L/opt/synopsys/scc/synphonycc-fpga-vE-2010.12-SP1/pico/simu/src/SimCode/ -lpdextn -lnosimdump -lsimerror -L/opt/synopsys/scc/synphonycc-fpga-vE-2010.12-SP1/pico/edgcpfe/lib/ -lpthread -lm -lstdc++ -lC
SCC=schroot -c centos5-i386 ~/bin/synphonycc_fpga
SCC_SCRIPTS=./scc_scripts
SYNTH_SRC=./synth_src
6,13 → 6,14
 
 
 
GCC_LINK=g++ /opt/synopsys/scc/synphonycc-fpga-vE-2010.12-SP1/pico/simu/src/SimCode/golden.o -L/opt/synopsys/scc/synphonycc-fpga-vE-2010.12-SP1/pico/simu/src/SimCode/ -lpdextn -lnosimdump -lsimerror -L/opt/synopsys/scc/synphonycc-fpga-vE-2010.12-SP1/pico/edgcpfe/lib/ -lpthread -lm -lstdc++ -lC
 
 
all: fpt_connect6 test_golden
 
fpt_connect6: ${SYNTH_SRC}/main.cpp util.o connect6.o connect6_synth.o state.o threats.o
${GCC} -o connect6 ${SYNTH_SRC}/main.cpp util.o connect6.o connect6_synth.o state.o threats.o -lpthread -lm -g -pg
 
fpt_connect6: main.o util.o connect6.o connect6_synth.o state.o threats.o q.o
${GCC_LINK} -o connect6 main.o q.o util.o connect6.o connect6_synth.o state.o threats.o -lpthread -lm -g -pg
main.o:${SYNTH_SRC}/main.cpp
${GCC} -c -g -pg ${SYNTH_SRC}/main.cpp
connect6_synth.o: ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/connect6_synth.h
${GCC} -c -g -pg ${SYNTH_SRC}/connect6_synth.cpp
connect6.o: ${SYNTH_SRC}/connect6.cpp ${SYNTH_SRC}/connect6.h
25,6 → 26,8
threats.o:${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/shared.h
${GCC} -c -g -pg ${SYNTH_SRC}/threats.cpp
q.o:${SYNTH_SRC}/q.cpp ${SYNTH_SRC}/shared.h
${GCC} -c -g -pg ${SYNTH_SRC}/q.cpp
 
 
test_golden:
46,27 → 49,32
cp ${SYNTH_SRC}/main.cpp.base ${SYNTH_SRC}/main.cpp
${SCC} ${SCC_SCRIPTS}/run_imp_window.tcl
echo "Done" > imp_window.tag
imp_line.tag: imp_window.tag
#sed -s 's/\\TCAB_NAME/threat_line/g' main.cpp.base >main.cpp
cp ${SYNTH_SRC}/main.cpp.base ${SYNTH_SRC}/main.cpp
imp_line.tag:
sed -s 's/\\TCAB_NAME/threat_line/g' ${SYNTH_SRC}/main.cpp.base >${SYNTH_SRC}/main.cpp
#cp ${SYNTH_SRC}/main.cpp.base ${SYNTH_SRC}/main.cpp
${SCC} ${SCC_SCRIPTS}/run_imp_line.tcl
echo "Done" > imp_line.tag
imp_marks.tag:
#sed -s 's/\\TCAB_NAME/ai_mraks/g' main.cpp.base >main.cpp
cp ${SYNTH_SRC}/main.cpp.base ${SYNTH_SRC}/main.cpp
sed -s 's/\\TCAB_NAME/ai_marks/g' ${SYNTH_SRC}/main.cpp.base >${SYNTH_SRC}/main.cpp
#cp ${SYNTH_SRC}/main.cpp.base ${SYNTH_SRC}/main.cpp
${SCC} ${SCC_SCRIPTS}/run_imp_marks.tcl
echo "Done" > imp_marks.tag
imp_threat.tag: imp_line.tag imp_marks.tag
#sed -s 's/\\TCAB_NAME/ai_threats/g' main.cpp.base >main.cpp
cp ${SYNTH_SRC}/main.cpp.base ${SYNTH_SRC}/main.cpp
imp_sort.tag:
sed -s 's/\\TCAB_NAME/streamsort/g' ${SYNTH_SRC}/main.cpp.base >${SYNTH_SRC}/main.cpp
#cp ${SYNTH_SRC}/main.cpp.base ${SYNTH_SRC}/main.cpp
${SCC} ${SCC_SCRIPTS}/run_imp_sort.tcl
echo "Done" > imp_sort.tag
imp_threat.tag: imp_line.tag
sed -s 's/\\TCAB_NAME/ai_threats/g' ${SYNTH_SRC}/main.cpp.base >${SYNTH_SRC}/main.cpp
#cp ${SYNTH_SRC}/main.cpp.base ${SYNTH_SRC}/main.cpp
${SCC} ${SCC_SCRIPTS}/run_imp_threat.tcl
echo "Done" > imp_threat.tag
imp_adjacent.tag:
cp ${SYNTH_SRC}/main.cpp.base ${SYNTH_SRC}/main.cpp
#sed -s 's/\\TCAB_NAME/ai_adjacent/g' main.cpp.base >main.cpp
#cp ${SYNTH_SRC}/main.cpp.base ${SYNTH_SRC}/main.cpp
sed -s 's/\\TCAB_NAME/ai_adjacent/g' ${SYNTH_SRC}/main.cpp.base >${SYNTH_SRC}/main.cpp
${SCC} ${SCC_SCRIPTS}/run_imp_adjacent.tcl
echo "Done" > imp_adjacent.tag
imp_connect.tag: imp_threat.tag imp_adjacent.tag
imp_connect.tag: imp_threat.tag imp_adjacent.tag
sed -s 's/\\TCAB_NAME/connect6ai_synth/g' ${SYNTH_SRC}/main.cpp.base >${SYNTH_SRC}/main.cpp
${SCC} ${SCC_SCRIPTS}/run_imp_connect.tcl
echo "Done" > imp_connect.tag

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