URL
https://opencores.org/ocsvn/connect-6/connect-6/trunk
Subversion Repositories connect-6
Compare Revisions
- This comparison shows the changes necessary to convert path
/connect-6
- from Rev 16 to Rev 17
- ↔ Reverse comparison
Rev 16 → Rev 17
/trunk/XILINX/BUILD_SCC_SRCH/scc_scripts/run_imp_search.tcl
0,0 → 1,54
set SYNTH_SRC "synth_src" |
set_project_params -directory ./ |
set_project_params -results myboard.txt |
set_project_params -sources "${SYNTH_SRC}/connect6.cpp ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/main.cpp ${SYNTH_SRC}/q.cpp ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/util.cpp ${SYNTH_SRC}/search_bfs.cpp" |
set_project_params -headers "${SYNTH_SRC}/connect6.h ${SYNTH_SRC}/connect6_synth.h ${SYNTH_SRC}/q.hpp ${SYNTH_SRC}/shared.h ${SYNTH_SRC}/threats.h ${SYNTH_SRC}/util.h" |
|
if [file exists imp_search] { delete_implementation imp_search } |
create_implementation imp_search |
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set_implementation_params -systemc_source no |
set_implementation_params -memory_return_path_external_delay 0% |
set_implementation_params -memory_forward_path_external_delay 0% |
set_implementation_params -instream_forward_path_external_delay 0% |
set_implementation_params -import_tcab "imp_threat" |
set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID" |
set_implementation_params -outstream_return_path_external_delay 0% |
set_implementation_params -appfiles "${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/search_bfs.cpp " |
set_implementation_params -proc df_search |
set_implementation_params -memory_forward_boundary_register infer |
set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" |
set_implementation_params -techlib xilinx-spartan6 |
set_implementation_params -device xc6slx45t-fgg484-3 |
#set_implementation_params -techlib altera-cyclone3 |
#set_implementation_params -device ep3c25-ea144-7 |
set_implementation_params -memory_return_boundary_register infer |
set_implementation_params -cexec_args "-port /dev/ttyS0 -player L" |
set_implementation_params -host_memory_access never,,, |
set_implementation_params -init_data_registers yes |
set_implementation_params -outstream_forward_path_external_delay 0% |
set_implementation_params -build_tcab yes |
set_implementation_params -reset_data_registers yes |
set_implementation_params -instream_return_path_external_delay 0% |
set_implementation_params -clock_freq 50 |
set_implementation_params -allow_latency_violation no |
set_implementation_params -tcab_deployment conditional_outputs:yes |
#setvar preprocess_auxopts "-Xmax_loops_for_jamming=15" |
#set_implementation_params -user_supplied_fpga_memory_read_write_ports separate |
#set_implementation_params -internal_blockram_memory_read_write_ports separate |
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set_loop_params -ii 25 |
|
setvar schedule_auxopts "-j" |
|
csim -golden -cexec_args "-port /dev/ttyS0 -player L" |
preprocess |
csim -preprocess -cexec_args "-port /dev/ttyS0 -player L" |
schedule |
csim -schedule -cexec_args "-port /dev/ttyS0 -player L" |
synthesize |
#csim -synthesize -dump_memory_access_trace -sim_after_synth_phase 5 |
create_rtl_package |
#vlogsim -online -detailed_perf_report |
#set_implementation_params -simulator modelsim |
#vlogsim -offline -dotasks 1-30 |
/trunk/XILINX/BUILD_SCC_SRCH/scc_scripts/run_imp_line.tcl
0,0 → 1,52
set SYNTH_SRC "synth_src" |
set_project_params -directory ./ |
set_project_params -results myboard.txt |
set_project_params -sources "${SYNTH_SRC}/connect6.cpp ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/main.cpp ${SYNTH_SRC}/q.cpp ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/util.cpp ${SYNTH_SRC}/search_bfs.cpp" |
set_project_params -headers "${SYNTH_SRC}/connect6.h ${SYNTH_SRC}/connect6_synth.h ${SYNTH_SRC}/q.hpp ${SYNTH_SRC}/shared.h ${SYNTH_SRC}/threats.h ${SYNTH_SRC}/util.h" |
set_project_params -cache_result_files no |
set_project_params -cache_data_files yes |
|
if [file exists imp_line] { delete_implementation imp_line } |
create_implementation imp_line |
|
set_implementation_params -systemc_source no |
set_implementation_params -memory_return_path_external_delay 0% |
set_implementation_params -memory_forward_path_external_delay 0% |
set_implementation_params -instream_forward_path_external_delay 0% |
set_implementation_params -import_tcab "imp_window" |
set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g" |
set_implementation_params -outstream_return_path_external_delay 0% |
set_implementation_params -appfiles "synth_src/state.cpp synth_src/threats.cpp" |
set_implementation_params -proc threat_line |
set_implementation_params -memory_forward_boundary_register infer |
set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" |
#set_implementation_params -task_ii 441 |
set_loop_params -ii 1 |
#set_implementation_params -techlib altera-cyclone3 |
#set_implementation_params -device ep3c25-ea144-7 |
set_implementation_params -techlib xilinx-spartan6 |
set_implementation_params -device xc6slx45t-fgg484-3 |
set_implementation_params -init_data_registers yes |
set_implementation_params -memory_return_boundary_register infer |
set_implementation_params -cexec_args "-port /dev/ttyS0 -player L" |
set_implementation_params -host_memory_access never |
set_implementation_params -outstream_forward_path_external_delay 0% |
set_implementation_params -build_tcab yes |
set_implementation_params -reset_data_registers yes |
set_implementation_params -task_overlap 0 |
set_implementation_params -instream_return_path_external_delay 0% |
set_implementation_params -simulator modelsim |
set_implementation_params -clock_freq 50 |
|
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setvar preprocess_auxopts "-L" |
|
|
csim -golden -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L" |
preprocess |
csim -preprocess -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L" |
schedule |
csim -schedule -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L" |
synthesize |
create_rtl_package -force |
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/trunk/XILINX/BUILD_SCC_SRCH/scc_scripts/run_imp_threat.tcl
0,0 → 1,55
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set SYNTH_SRC "synth_src" |
set_project_params -directory ./ |
set_project_params -results myboard.txt |
set_project_params -sources "${SYNTH_SRC}/connect6.cpp ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/main.cpp ${SYNTH_SRC}/q.cpp ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/util.cpp ${SYNTH_SRC}/search_bfs.cpp" |
set_project_params -headers "${SYNTH_SRC}/connect6.h ${SYNTH_SRC}/connect6_synth.h ${SYNTH_SRC}/q.hpp ${SYNTH_SRC}/shared.h ${SYNTH_SRC}/threats.h ${SYNTH_SRC}/util.h" |
set_project_params -cache_result_files no |
set_project_params -cache_data_files yes |
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if [file exists imp_threat] { delete_implementation imp_threat } |
create_implementation imp_threat |
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set_implementation_params -systemc_source no |
#set_implementation_params -instream_boundary_register infer |
set_implementation_params -memory_return_path_external_delay 0% |
set_implementation_params -memory_forward_path_external_delay 0% |
#set_implementation_params -instream_forward_path_external_delay 0% |
set_implementation_params -import_tcab "imp_line" |
set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g" |
#set_implementation_params -outstream_return_path_external_delay 0% |
set_implementation_params -appfiles "synth_src/state.cpp synth_src/threats.cpp" |
set_implementation_params -proc ai_threats |
set_implementation_params -memory_forward_boundary_register infer |
set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" |
set_implementation_params -memory_return_boundary_register infer |
set_implementation_params -cexec_args "-port /dev/ttyS0 -player L" |
set_implementation_params -host_memory_access never |
#set_implementation_params -techlib altera-cyclone3 |
#set_implementation_params -device ep3c25-ea144-7 |
set_implementation_params -techlib xilinx-spartan6 |
set_implementation_params -device xc6slx45t-fgg484-3 |
#set_implementation_params -always_enabled_ppa yes |
set_implementation_params -init_data_registers yes |
#set_implementation_params -outstream_forward_path_external_delay 0% |
#set_implementation_params -outstream_boundary_register infer |
set_implementation_params -build_tcab yes |
set_implementation_params -reset_data_registers yes |
set_implementation_params -task_overlap 0 |
#set_implementation_params -instream_return_path_external_delay 0% |
set_implementation_params -simulator modelsim |
set_implementation_params -clock_freq 50 |
set_implementation_params -allow_latency_violation no |
|
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setvar schedule_auxopts "-j" |
|
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csim -golden -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L" |
preprocess |
csim -preprocess -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L" |
schedule |
csim -schedule -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L" |
synthesize |
create_rtl_package -force |
#vlogsim -online -detailed_perf_report |
/trunk/XILINX/BUILD_SCC_SRCH/scc_scripts/run_imp_window.tcl
0,0 → 1,52
|
set SYNTH_SRC "synth_src" |
set_project_params -directory ./ |
set_project_params -results myboard.txt |
set_project_params -sources "${SYNTH_SRC}/connect6.cpp ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/main.cpp ${SYNTH_SRC}/q.cpp ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/util.cpp ${SYNTH_SRC}/search_bfs.cpp" |
set_project_params -headers "${SYNTH_SRC}/connect6.h ${SYNTH_SRC}/connect6_synth.h ${SYNTH_SRC}/q.hpp ${SYNTH_SRC}/shared.h ${SYNTH_SRC}/threats.h ${SYNTH_SRC}/util.h" |
set_project_params -cache_result_files no |
set_project_params -cache_data_files yes |
|
if [file exists imp_window] { delete_implementation imp_window } |
create_implementation imp_window |
|
set_implementation_params -systemc_source no |
set_implementation_params -memory_return_path_external_delay 0% |
set_implementation_params -memory_forward_path_external_delay 0% |
set_implementation_params -instream_forward_path_external_delay 0% |
set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID" |
set_implementation_params -outstream_return_path_external_delay 0% |
set_implementation_params -appfiles "synth_src/state.cpp synth_src/threats.cpp" |
set_implementation_params -proc threat_window |
set_implementation_params -memory_forward_boundary_register infer |
set_implementation_params -architectural_pipelinability "1" |
set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" |
#set_implementation_params -techlib altera-cyclone3 |
#set_implementation_params -device ep3c25-ea144-7 |
set_implementation_params -techlib xilinx-spartan6 |
set_implementation_params -device xc6slx45t-fgg484-3 |
set_implementation_params -memory_return_boundary_register infer |
set_implementation_params -cexec_args "-port /dev/ttyS0 -player L" |
set_implementation_params -host_memory_access never |
set_implementation_params -init_data_registers yes |
set_implementation_params -outstream_forward_path_external_delay 0% |
set_implementation_params -build_tcab yes |
set_implementation_params -reset_data_registers yes |
set_implementation_params -task_overlap infer |
set_implementation_params -instream_return_path_external_delay 0% |
set_implementation_params -simulator modelsim |
set_implementation_params -clock_freq 50 |
|
|
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#set_loop_params -ii 1 |
|
csim -golden -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L" |
preprocess |
csim -preprocess -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L" |
schedule |
csim -schedule -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L" |
synthesize |
create_rtl_package |
#vlogsim -online -ccompiler_args "-g" -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -sccompiler_args "-DDONT_VERIFY_PPAID" -cexec_args "-port /dev/ttyS0 -player L" -simulator modelsim -vcompiler_args -vexec_args |
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/trunk/XILINX/BUILD_SCC_SRCH/scc_scripts/run_imp_sort.tcl
0,0 → 1,50
set_project_params -directory ./ |
set_project_params -results myboard.txt |
set_project_params -sources "synth_src/connect6.cpp synth_src/connect6_synth.cpp synth_src/main.cpp synth_src/q.cpp synth_src/state.cpp synth_src/threats.cpp synth_src/util.cpp synth_src/search_bfs.cpp" |
set_project_params -headers "synth_src/connect6.h synth_src/connect6_synth.h synth_src/q.hpp synth_src/shared.h synth_src/threats.h synth_src/util.h" |
set_project_params -cache_result_files no |
set_project_params -cache_data_files yes |
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if [file exists imp_sort] { delete_implementation imp_sort } |
create_implementation imp_sort |
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set_implementation_params -systemc_source no |
set_implementation_params -instream_boundary_register infer |
set_implementation_params -memory_return_path_external_delay 0% |
set_implementation_params -memory_forward_path_external_delay 0% |
set_implementation_params -instream_forward_path_external_delay 0% |
set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID -g -g -g -g -g" |
set_implementation_params -outstream_return_path_external_delay 0% |
set_implementation_params -appfile synth_src/state.cpp |
set_implementation_params -proc aimoves_sort_bis |
set_implementation_params -memory_forward_boundary_register infer |
set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" |
#set_implementation_params -techlib altera-cyclone4gx |
#set_implementation_params -device ep4cgx110c-fc23-7 |
set_implementation_params -techlib xilinx-spartan6 |
set_implementation_params -device xc6slx45-csg324-2 |
set_implementation_params -memory_return_boundary_register infer |
set_implementation_params -cexec_args "-port /dev/ttyS0 -player L" |
set_implementation_params -host_memory_access never |
set_implementation_params -init_data_registers yes |
set_implementation_params -outstream_forward_path_external_delay 0% |
set_implementation_params -outstream_boundary_register infer |
set_implementation_params -build_tcab yes |
set_implementation_params -reset_data_registers yes |
set_implementation_params -task_overlap infer |
set_implementation_params -instream_return_path_external_delay 0% |
set_implementation_params -simulator modelsim |
set_implementation_params -clock_freq 100 |
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set_loop_params -ii 1 |
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csim -golden -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L" |
preprocess |
csim -preprocess -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L" |
schedule |
csim -schedule -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L" |
synthesize |
create_rtl_package -force |
|
/trunk/XILINX/BUILD_SCC_SRCH/scc_scripts/run_imp_connect.tcl
0,0 → 1,54
set SYNTH_SRC "synth_src" |
set_project_params -directory ./ |
set_project_params -results myboard.txt |
set_project_params -sources "${SYNTH_SRC}/connect6.cpp ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/main.cpp ${SYNTH_SRC}/q.cpp ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/util.cpp ${SYNTH_SRC}/search_bfs.cpp" |
set_project_params -headers "${SYNTH_SRC}/connect6.h ${SYNTH_SRC}/connect6_synth.h ${SYNTH_SRC}/q.hpp ${SYNTH_SRC}/shared.h ${SYNTH_SRC}/threats.h ${SYNTH_SRC}/util.h" |
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if [file exists imp_connect] { delete_implementation imp_connect } |
create_implementation imp_connect |
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set_implementation_params -systemc_source no |
set_implementation_params -memory_return_path_external_delay 0% |
set_implementation_params -memory_forward_path_external_delay 0% |
set_implementation_params -instream_forward_path_external_delay 0% |
set_implementation_params -import_tcab "imp_search imp_adjacent" |
set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID" |
set_implementation_params -outstream_return_path_external_delay 0% |
set_implementation_params -appfiles "${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/search_bfs.cpp" |
set_implementation_params -proc connect6ai_synth |
set_implementation_params -memory_forward_boundary_register infer |
set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" |
#set_implementation_params -techlib altera-cyclone3 |
#set_implementation_params -device ep3c25-ea144-7 |
set_implementation_params -techlib xilinx-spartan6 |
set_implementation_params -device xc6slx45t-fgg484-3 |
set_implementation_params -memory_return_boundary_register infer |
set_implementation_params -cexec_args "-port /dev/ttyS0 -player L" |
set_implementation_params -host_memory_access never,,, |
set_implementation_params -init_data_registers yes |
set_implementation_params -outstream_forward_path_external_delay 0% |
set_implementation_params -build_tcab yes |
set_implementation_params -reset_data_registers yes |
set_implementation_params -instream_return_path_external_delay 0% |
set_implementation_params -clock_freq 50 |
set_implementation_params -allow_latency_violation no |
set_implementation_params -tcab_deployment conditional_outputs:yes |
#setvar preprocess_auxopts "-Xmax_loops_for_jamming=15" |
#set_implementation_params -user_supplied_fpga_memory_read_write_ports separate |
#set_implementation_params -internal_blockram_memory_read_write_ports separate |
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setvar schedule_auxopts "-j" |
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csim -golden -cexec_args "-port /dev/ttyS0 -player L" |
preprocess |
csim -preprocess -cexec_args "-port /dev/ttyS0 -player L" |
schedule |
csim -schedule -cexec_args "-port /dev/ttyS0 -player L" |
synthesize |
#csim -synthesize -dump_memory_access_trace -sim_after_synth_phase 5 |
create_rtl_package |
#vlogsim -online -detailed_perf_report |
#set_implementation_params -simulator modelsim |
#vlogsim -offline -dotasks 1-30 |
/trunk/XILINX/BUILD_SCC_SRCH/scc_scripts/run_imp_adjacent.tcl
0,0 → 1,49
set SYNTH_SRC "synth_src" |
set_project_params -directory ./ |
set_project_params -results myboard.txt |
set_project_params -sources "${SYNTH_SRC}/connect6.cpp ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/main.cpp ${SYNTH_SRC}/q.cpp ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/util.cpp ${SYNTH_SRC}/search_bfs.cpp" |
set_project_params -headers "${SYNTH_SRC}/connect6.h ${SYNTH_SRC}/connect6_synth.h ${SYNTH_SRC}/q.hpp ${SYNTH_SRC}/shared.h ${SYNTH_SRC}/threats.h ${SYNTH_SRC}/util.h" |
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if [file exists imp_adjacent] { delete_implementation imp_adjacent } |
create_implementation imp_adjacent |
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set_implementation_params -systemc_source no |
set_implementation_params -memory_return_path_external_delay 0% |
set_implementation_params -memory_forward_path_external_delay 0% |
set_implementation_params -instream_forward_path_external_delay 0% |
set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID" |
set_implementation_params -outstream_return_path_external_delay 0% |
set_implementation_params -appfiles " ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp" |
set_implementation_params -proc ai_adjacent |
set_implementation_params -memory_forward_boundary_register infer |
set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" |
set_implementation_params -memory_return_boundary_register infer |
set_implementation_params -techlib xilinx-spartan6 |
set_implementation_params -device xc6slx45t-fgg484-3 |
#set_implementation_params -techlib altera-cyclone3 |
#set_implementation_params -device ep3c25-ea144-7 |
set_implementation_params -cexec_args "-port /dev/ttyS0 -player L" |
set_implementation_params -host_memory_access never,,, |
set_implementation_params -init_data_registers yes |
set_implementation_params -outstream_forward_path_external_delay 0% |
set_implementation_params -build_tcab yes |
set_implementation_params -reset_data_registers yes |
set_implementation_params -instream_return_path_external_delay 0% |
set_implementation_params -clock_freq 50 |
set_implementation_params -allow_latency_violation no |
#set_implementation_params -user_supplied_fpga_memory_read_write_ports separate |
#set_implementation_params -internal_blockram_memory_read_write_ports separate |
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|
|
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csim -golden -cexec_args "-port /dev/ttyS0 -player L" |
preprocess |
csim -preprocess -cexec_args "-port /dev/ttyS0 -player L" |
schedule |
csim -schedule -cexec_args "-port /dev/ttyS0 -player L" |
synthesize |
#csim -synthesize -dump_memory_access_trace |
create_rtl_package |
#set_implementation_params -simulator modelsim |
#vlogsim -offline -dotasks 1-30 |
/trunk/XILINX/BUILD_SCC_SRCH/scc_scripts/run_imp_threat_flat.tcl
0,0 → 1,53
set SYNTH_SRC "synth_src" |
set_project_params -directory ./ |
set_project_params -results myboard.txt |
set_project_params -sources "${SYNTH_SRC}/connect6.cpp ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/main.cpp ${SYNTH_SRC}/q.cpp ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/util.cpp" |
set_project_params -headers "${SYNTH_SRC}/connect6.h ${SYNTH_SRC}/connect6_synth.h ${SYNTH_SRC}/q.hpp ${SYNTH_SRC}/shared.h ${SYNTH_SRC}/threats.h ${SYNTH_SRC}/util.h" |
|
if [file exists imp_threat_flat] { delete_implementation imp_threat_flat } |
create_implementation imp_threat_flat |
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set_implementation_params -systemc_source no |
set_implementation_params -memory_return_path_external_delay 0% |
set_implementation_params -memory_forward_path_external_delay 0% |
set_implementation_params -instream_forward_path_external_delay 0% |
#set_implementation_params -import_tcab "imp_line" |
#imp_line" |
set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID" |
set_implementation_params -outstream_return_path_external_delay 0% |
set_implementation_params -appfiles "${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp" |
set_implementation_params -proc ai_threats |
set_implementation_params -memory_forward_boundary_register infer |
set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" |
set_implementation_params -techlib altera-cyclone3 |
set_implementation_params -memory_return_boundary_register infer |
set_implementation_params -cexec_args "-port /dev/ttyS0 -player L" |
set_implementation_params -host_memory_access never |
set_implementation_params -device ep3c25-ea144-7 |
set_implementation_params -force_independent_stalldomain_tcab yes |
set_implementation_params -init_data_registers yes |
set_implementation_params -outstream_forward_path_external_delay 0% |
set_implementation_params -build_tcab yes |
set_implementation_params -reset_data_registers yes |
set_implementation_params -instream_return_path_external_delay 0% |
set_implementation_params -clock_freq 100 |
set_implementation_params -allow_latency_violation no |
#set_implementation_params -user_supplied_fpga_memory_read_write_ports separate |
#set_implementation_params -internal_blockram_memory_read_write_ports separate |
|
|
|
|
csim -golden -cexec_args "-port /dev/ttyS0 -player L" |
preprocess |
csim -preprocess -cexec_args "-port /dev/ttyS0 -player L" |
schedule |
csim -schedule -cexec_args "-port /dev/ttyS0 -player L" |
synthesize |
#csim -synthesize -dump_memory_access_trace |
#csim -synthesize with -dump_memory_access_trace -sim_after_synth_phase 5 |
create_rtl_package |
#csim -synthesize |
|
#set_implementation_params -simulator modelsim |
#vlogsim -offline -dotasks 1-30 |
/trunk/XILINX/BUILD_SCC_SRCH/scc_scripts/run_imp_marks.tcl
0,0 → 1,48
set_project_params -directory ./ |
set_project_params -results myboard.txt |
set_project_params -sources "synth_src/connect6.cpp synth_src/connect6_synth.cpp synth_src/main.cpp synth_src/q.cpp synth_src/state.cpp synth_src/threats.cpp synth_src/util.cpp" |
set_project_params -headers "synth_src/connect6.h synth_src/connect6_synth.h synth_src/q.hpp synth_src/shared.h synth_src/threats.h synth_src/util.h" |
set_project_params -cache_result_files no |
set_project_params -cache_data_files yes |
|
if [file exists imp_marks] { delete_implementation imp_marks } |
create_implementation imp_marks |
|
set_implementation_params -systemc_source no |
set_implementation_params -memory_return_path_external_delay 0% |
set_implementation_params -memory_forward_path_external_delay 0% |
set_implementation_params -instream_forward_path_external_delay 0% |
set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID -g -g -g -g" |
set_implementation_params -outstream_return_path_external_delay 0% |
set_implementation_params -appfiles "synth_src/state.cpp synth_src/threats.cpp" |
set_implementation_params -proc ai_marks |
set_implementation_params -memory_forward_boundary_register infer |
set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" |
#set_implementation_params -techlib altera-cyclone4gx |
#set_implementation_params -device ep4cgx110c-fc23-7 |
set_implementation_params -techlib xilinx-spartan6 |
set_implementation_params -device xc6slx45-csg324-2 |
set_implementation_params -memory_return_boundary_register infer |
set_implementation_params -cexec_args "-port /dev/ttyS0 -player L" |
set_implementation_params -host_memory_access never |
set_implementation_params -init_data_registers yes |
set_implementation_params -outstream_forward_path_external_delay 0% |
set_implementation_params -build_tcab yes |
set_implementation_params -reset_data_registers yes |
set_implementation_params -task_overlap 0 |
set_implementation_params -instream_return_path_external_delay 0% |
set_implementation_params -simulator modelsim |
set_implementation_params -clock_freq 100 |
|
|
|
set_loop_params -ii 3 |
|
csim -golden -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L" |
preprocess |
csim -preprocess -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L" |
schedule |
csim -schedule -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L" |
synthesize |
create_rtl_package |
|
/trunk/XILINX/BUILD_SCC_SRCH/scc_scripts/run_imp_choose.tcl
0,0 → 1,49
set SYNTH_SRC "synth_src" |
set_project_params -directory ./ |
set_project_params -results myboard.txt |
set_project_params -sources "${SYNTH_SRC}/connect6.cpp ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/main.cpp ${SYNTH_SRC}/q.cpp ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/util.cpp ${SYNTH_SRC}/search_bfs.cpp" |
set_project_params -headers "${SYNTH_SRC}/connect6.h ${SYNTH_SRC}/connect6_synth.h ${SYNTH_SRC}/q.hpp ${SYNTH_SRC}/shared.h ${SYNTH_SRC}/threats.h ${SYNTH_SRC}/util.h" |
|
if [file exists imp_choose] { delete_implementation imp_choose } |
create_implementation imp_choose |
|
set_implementation_params -systemc_source no |
set_implementation_params -memory_return_path_external_delay 0% |
set_implementation_params -memory_forward_path_external_delay 0% |
set_implementation_params -instream_forward_path_external_delay 0% |
set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID" |
set_implementation_params -outstream_return_path_external_delay 0% |
set_implementation_params -appfiles "${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/connect6_synth.cpp" |
set_implementation_params -proc aimoves_choose |
set_implementation_params -memory_forward_boundary_register infer |
set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" |
set_implementation_params -techlib altera-cyclone3 |
set_implementation_params -memory_return_boundary_register infer |
set_implementation_params -cexec_args "-port /dev/ttyS0 -player L" |
set_implementation_params -host_memory_access never,,, |
set_implementation_params -device ep3c25-ea144-7 |
set_implementation_params -init_data_registers yes |
set_implementation_params -outstream_forward_path_external_delay 0% |
set_implementation_params -build_tcab yes |
set_implementation_params -reset_data_registers yes |
set_implementation_params -instream_return_path_external_delay 0% |
set_implementation_params -clock_freq 100 |
set_implementation_params -allow_latency_violation no |
#set_implementation_params -memory_size "moves.data:moves_size" |
#set_implementation_params -user_supplied_fpga_memory_read_write_ports separate |
#set_implementation_params -internal_blockram_memory_read_write_ports separate |
|
|
|
|
csim -golden -cexec_args "-port /dev/ttyS0 -player L" |
preprocess |
csim -preprocess -cexec_args "-port /dev/ttyS0 -player L" |
schedule |
csim -schedule -cexec_args "-port /dev/ttyS0 -player L" |
synthesize |
#csim -synthesize -dump_memory_access_trace |
create_rtl_package |
|
#set_implementation_params -simulator modelsim |
#vlogsim -offline -dotasks 1-30 |
/trunk/XILINX/BUILD_SCC_SRCH/scc_scripts/run_imp_board_copy.tcl
0,0 → 1,47
set_project_params -directory ./ |
set_project_params -results myboard.txt |
set_project_params -sources "synth_src/connect6.cpp synth_src/connect6_synth.cpp synth_src/main.cpp synth_src/q.cpp synth_src/state.cpp synth_src/threats.cpp synth_src/util.cpp" |
set_project_params -headers "synth_src/connect6.h synth_src/connect6_synth.h synth_src/q.hpp synth_src/shared.h synth_src/threats.h synth_src/util.h" |
set_project_params -cache_result_files no |
set_project_params -cache_data_files yes |
|
if [file exists imp_line] { delete_implementation imp_line } |
create_implementation imp_board |
|
set_implementation_params -systemc_source no |
set_implementation_params -memory_return_path_external_delay 0% |
set_implementation_params -memory_forward_path_external_delay 0% |
set_implementation_params -instream_forward_path_external_delay 0% |
set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g" |
set_implementation_params -outstream_return_path_external_delay 0% |
set_implementation_params -appfiles "synth_src/state.cpp" |
set_implementation_params -proc board_copy |
set_implementation_params -memory_forward_boundary_register infer |
set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" |
set_implementation_params -task_ii 441 |
set_implementation_params -techlib altera-cyclone3 |
set_implementation_params -device ep3c25-ea144-7 |
set_implementation_params -init_data_registers yes |
set_implementation_params -memory_return_boundary_register infer |
set_implementation_params -cexec_args "-port /dev/ttyS0 -player L" |
set_implementation_params -host_memory_access never |
set_implementation_params -outstream_forward_path_external_delay 0% |
set_implementation_params -build_tcab yes |
set_implementation_params -reset_data_registers yes |
set_implementation_params -task_overlap 0 |
set_implementation_params -instream_return_path_external_delay 0% |
set_implementation_params -simulator modelsim |
set_implementation_params -clock_freq 50 |
|
|
setvar preprocess_auxopts "-L" |
|
|
csim -golden -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L" |
preprocess |
csim -preprocess -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L" |
schedule |
csim -schedule -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L" |
synthesize |
create_rtl_package -force |
|
/trunk/XILINX/BUILD_SCC_SRCH/.picoferc
0,0 → 1,17
bgcap 0 |
c_compiler gcc |
cache_data_files yes |
cache_result_files no |
cpp_compiler g++ |
editor xterm -e vi %FILE% & |
filter ERROR WARNING INTERNAL_ERROR NOTE |
headers synth_src/connect6.h synth_src/connect6_synth.h synth_src/q.hpp synth_src/shared.h synth_src/threats.h synth_src/util.h |
logdir Logs |
maxhist 0 |
outputmode verbose |
read_only_files 0 |
results myboard.txt |
sc_compiler g++ |
source_directory ./ |
sources synth_src/connect6.cpp synth_src/connect6_synth.cpp synth_src/main.cpp synth_src/q.cpp synth_src/state.cpp synth_src/threats.cpp synth_src/util.cpp synth_src/search_bfs.cpp |
transcript 0 |
/trunk/XILINX/BUILD_SCC_SRCH/SP6/constraints.sdc
0,0 → 1,5
# clocks |
|
create_clock -period 30.0 -name clk [get_ports OSC_27] |
# input/output delays |
|
/trunk/XILINX/BUILD_SCC_SRCH/SP6/SP6.xise
0,0 → 1,830
<?xml version="1.0" encoding="UTF-8" standalone="no" ?> |
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> |
|
<header> |
<!-- ISE source project file created by Project Navigator. --> |
<!-- --> |
<!-- This file contains project source information including a list of --> |
<!-- project source files, project and process properties. This file, --> |
<!-- along with the project source files, is sufficient to open and --> |
<!-- implement in ISE Project Navigator. --> |
<!-- --> |
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
</header> |
|
<version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/> |
|
<files> |
<file xil_pn:name="../../../../../../SP6/AI.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="95"/> |
</file> |
<file xil_pn:name="../../../../../../SP6/CMD_Decode_simple.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="94"/> |
</file> |
<file xil_pn:name="../../../../../../SP6/DE2.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="96"/> |
</file> |
<file xil_pn:name="../../../../../../SP6/LCD_Controller_safe.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="../../../../../../SP6/LCD_TEST_SAFE.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="../../../../../../SP6/RS232_Command.h" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="../../../../../../SP6/RS232_Controller.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="93"/> |
</file> |
<file xil_pn:name="../../../../../../SP6/Reset_Delay.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="../../../../../../SP6/SEG7_LUT.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="87"/> |
</file> |
<file xil_pn:name="../../../../../../SP6/SEG7_LUT_8.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="92"/> |
</file> |
<file xil_pn:name="../../../../../../SP6/async_receiver_altera.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="90"/> |
</file> |
<file xil_pn:name="../../../../../../SP6/async_transmitter_altera.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="89"/> |
</file> |
<file xil_pn:name="../../../../../../SP6/bram_based_stream_buffer.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="88"/> |
</file> |
<file xil_pn:name="../../../../../../SP6/safe_test.vhd" xil_pn:type="FILE_VHDL"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
</file> |
<file xil_pn:name="../../../../macrocells/RA1SH.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="75"/> |
</file> |
<file xil_pn:name="../../../../macrocells/RA2SH.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="74"/> |
</file> |
<file xil_pn:name="../../../../macrocells/SRAM_4.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="85"/> |
</file> |
<file xil_pn:name="../../../../macrocells/addsubw.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="44"/> |
</file> |
<file xil_pn:name="../../../../macrocells/addw.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="43"/> |
</file> |
<file xil_pn:name="../../../../macrocells/andw.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="42"/> |
</file> |
<file xil_pn:name="../../../../macrocells/brf.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="41"/> |
</file> |
<file xil_pn:name="../../../../macrocells/cmpp_eq_1_4.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="40"/> |
</file> |
<file xil_pn:name="../../../../macrocells/cmpp_eq_2_4.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="69"/> |
</file> |
<file xil_pn:name="../../../../macrocells/cmpp_ineq_13_40.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="39"/> |
</file> |
<file xil_pn:name="../../../../macrocells/cmpp_ineq_21_40.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="38"/> |
</file> |
<file xil_pn:name="../../../../macrocells/cmpp_ineq_29_40.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="37"/> |
</file> |
<file xil_pn:name="../../../../macrocells/cmpp_ineq_37_40.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="68"/> |
</file> |
<file xil_pn:name="../../../../macrocells/cmpp_neq_1_4.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="36"/> |
</file> |
<file xil_pn:name="../../../../macrocells/cmpp_neq_2_4.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="82"/> |
</file> |
<file xil_pn:name="../../../../macrocells/cmpr_eq.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="35"/> |
</file> |
<file xil_pn:name="../../../../macrocells/cmpr_ineq_3.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="34"/> |
</file> |
<file xil_pn:name="../../../../macrocells/cmpr_ineq_4.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="33"/> |
</file> |
<file xil_pn:name="../../../../macrocells/cmpr_ineq_5.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="32"/> |
</file> |
<file xil_pn:name="../../../../macrocells/cmpr_ineq_7.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="67"/> |
</file> |
<file xil_pn:name="../../../../macrocells/cmpr_ineq_8.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="66"/> |
</file> |
<file xil_pn:name="../../../../macrocells/cmpr_ineq_9.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="31"/> |
</file> |
<file xil_pn:name="../../../../macrocells/cmpr_neq.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="30"/> |
</file> |
<file xil_pn:name="../../../../macrocells/combine12_wn.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="76"/> |
</file> |
<file xil_pn:name="../../../../macrocells/combine26_wn.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="56"/> |
</file> |
<file xil_pn:name="../../../../macrocells/combine2_wn.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="55"/> |
</file> |
<file xil_pn:name="../../../../macrocells/combine32_wn.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="54"/> |
</file> |
<file xil_pn:name="../../../../macrocells/combine3_wn.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="65"/> |
</file> |
<file xil_pn:name="../../../../macrocells/counter.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="29"/> |
</file> |
<file xil_pn:name="../../../../macrocells/decode.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="28"/> |
</file> |
<file xil_pn:name="../../../../macrocells/delayn.v" xil_pn:type="FILE_VERILOG"> |
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/> |
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> |
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<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/> |
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/> |
<property xil_pn:name="Device" xil_pn:value="xc6slx45t" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/> |
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/> |
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/> |
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/> |
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/> |
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/> |
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/> |
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/> |
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/> |
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/> |
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/> |
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/> |
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/> |
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/> |
<property xil_pn:name="ICAP Select" xil_pn:value="Top" xil_pn:valueState="default"/> |
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Implementation Top" xil_pn:value="Module|DE2" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top File" xil_pn:value="../../../../../../SP6/DE2.v" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/DE2" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/> |
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/> |
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/> |
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/> |
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/> |
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/> |
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/> |
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/> |
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/> |
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/> |
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/> |
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/> |
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/> |
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/> |
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/> |
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/> |
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/> |
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Output File Name" xil_pn:value="DE2" xil_pn:valueState="default"/> |
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Package" xil_pn:value="fgg484" xil_pn:valueState="default"/> |
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/> |
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/> |
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/> |
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="DE2_map.v" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="DE2_timesim.v" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="DE2_synthesis.v" xil_pn:valueState="default"/> |
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="DE2_translate.v" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> |
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/> |
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/> |
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/> |
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/> |
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/> |
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/> |
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/> |
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> |
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/> |
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/> |
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> |
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> |
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> |
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> |
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> |
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/> |
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/> |
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> |
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> |
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/> |
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> |
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/> |
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> |
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> |
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/> |
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> |
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/> |
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/> |
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/> |
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/> |
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/> |
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/> |
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> |
<!-- --> |
<!-- The following properties are for internal use only. These should not be modified.--> |
<!-- --> |
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_DesignName" xil_pn:value="DE2" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> |
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-05-06T16:07:07" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="92490F4AB7F9CE5927D505926FB25CA0" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> |
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> |
</properties> |
|
<bindings/> |
|
<libraries/> |
|
<autoManagedFiles> |
<!-- The following files are identified by `include statements in verilog --> |
<!-- source files and are automatically managed by Project Navigator. --> |
<!-- --> |
<!-- Do not hand-edit this section, as it will be overwritten when the --> |
<!-- project is analyzed based on files automatically identified as --> |
<!-- include files. --> |
</autoManagedFiles> |
|
</project> |
/trunk/XILINX/BUILD_SCC_SRCH/SP6/RS232_Controller.v
0,0 → 1,18
module RS232_Controller(oDATA,iDATA,oTxD,oTxD_Busy,iTxD_Start, |
iRxD,oRxD_Ready,oRxD_ERROR,oRxD_idle,iCLK,RST_n); |
input [7:0] iDATA; |
input iTxD_Start,iRxD,iCLK,RST_n; |
output [7:0] oDATA; |
output oTxD,oTxD_Busy,oRxD_Ready,oRxD_ERROR,oRxD_idle; |
|
async_receiver u0 ( /*.RST_n(RST_n),*/.clk(iCLK), .RxD(iRxD), |
.RxD_data_ready(oRxD_Ready),/*.RxD_data_error(oRxD_ERROR),*/ |
.RxD_data(oDATA),.RxD_idle(oRxD_idle)); |
//serie u0 ( .n_reset(RST_n),.clk(iCLK), .rx_in(iRxD), |
// .d_rdy(oRxD_Ready),.d_err(oRxD_ERROR), |
// .rx_data(oDATA)); |
async_transmitter u1 ( /*.RST_n(RST_n),*/.clk(iCLK), .TxD_start(iTxD_Start), |
.TxD_data(iDATA), .TxD(oTxD), |
.TxD_busy(oTxD_Busy)); |
|
endmodule |
trunk/XILINX/BUILD_SCC_SRCH/SP6/RS232_Controller.v
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC_SRCH/SP6/CMD_Decode_simple.v
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/SP6/CMD_Decode_simple.v (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/SP6/CMD_Decode_simple.v (revision 17)
@@ -0,0 +1,314 @@
+
+module CMD_Decode( // USB JTAG
+ iRXD_DATA,oTXD_DATA,iRXD_Ready,iTXD_Done,oTXD_Start,
+ // AI
+ oAI_DATA,iAI_DATA,oAI_Start,iAI_Done,oCOLOR,
+ // Control
+ iCLK,iRST_n,oAI_RSTn,
+ //Debug
+ d_cmd
+ );
+// USB JTAG
+input [7:0] iRXD_DATA;
+input iRXD_Ready,iTXD_Done;
+output [7:0] oTXD_DATA;
+output oTXD_Start;
+// AI
+input [63:0] iAI_DATA;
+output [63:0] oAI_DATA;
+output reg oAI_Start;
+input iAI_Done;
+output [7:0] oCOLOR;
+// Control
+input iCLK,iRST_n;
+output oAI_RSTn;
+//output oAI_RSTn =AI_RSTn; //doesn't work in synplify
+//Debug
+output [16:0] d_cmd ;
+// Internal Register
+reg [63:0] CMD_Tmp;
+reg [71:0] AI_RESULT;
+reg [71:0] AI_RESULT_next;
+reg [2:0] mAI_ST /* synthesis syn_encoding = "safe,onehot" */;
+reg [2:0] mAI_ST_next;
+
+reg [63:0] AI_INPUT;
+reg [63:0] AI_INPUT_next;
+reg [16:0] AI_INPUT_MOVE;
+reg [16:0] AI_INPUT_MOVE_next;
+// USB JTAG TXD Output
+reg oSR_TXD_Start;
+reg [7:0] oSR_TXD_DATA;
+
+//
+reg AI_RSTn;
+assign oAI_RSTn =AI_RSTn; // this one works in synplify. see line 24
+reg [16:0] move_count_me,move_count_you; //maximum no. of moves= 361
+reg [16:0] move_count_me_next; //maximum no. of moves= 361
+wire [16:0] move_count=(move_count_me+move_count_you) >> 2;
+
+reg [7:0] CMD;
+
+reg TXD_Start;
+reg TXD_Start_next;
+reg rst_count;
+assign oTXD_Start =TXD_Start;
+assign d_cmd=AI_INPUT_MOVE;
+assign oCOLOR = CMD;
+
+/////////////////////////////////////////////////////////
+/////// Shift Register For Command Temp /////////////
+always@(posedge iCLK or negedge iRST_n)
+begin
+ if(!iRST_n)
+ begin
+ CMD_Tmp<=0;
+ CMD<=0;
+ move_count_you<=0;
+ AI_RSTn<=1'b0;
+ end
+ else
+ begin
+ CMD_Tmp<=CMD_Tmp;
+ CMD<=CMD;
+ move_count_you<=move_count_you;
+ AI_RSTn<=AI_RSTn;
+ if(iRXD_Ready)
+ begin
+ CMD_Tmp<={CMD_Tmp[55:0],iRXD_DATA};
+
+
+ if(iRXD_DATA !=8'h44 && iRXD_DATA!=8'h4C)
+ begin
+
+ move_count_you<=move_count_you+1;//4 ascii chars == 1 move
+ AI_RSTn<=1'b1;
+ end
+ else
+ begin
+
+ CMD<=iRXD_DATA;
+ move_count_you<=0;
+ AI_RSTn<=1'b0;
+
+ end
+ end
+ else
+
+ AI_RSTn<=1'b1;
+ end
+end
+/////////////////////////////////////////////////////////
+/////////////////////////////////////////////////////////
+//////////////// AI Control /////////////////////
+reg [3:0] wait_count;
+reg [3:0] wait_count_next;
+reg [3:0] NO_OF_MOVES;
+reg [3:0] NO_OF_MOVES_next;
+parameter state0=3'b000,state1=3'b001,state2=3'b010,state3=3'b011,state4=3'b100,state5=3'b101,state6=3'b110;
+
+always@(posedge iCLK or negedge AI_RSTn)
+
+begin
+ if(!AI_RSTn)
+ begin
+ mAI_ST<= state0;
+ wait_count <=0;
+ move_count_me<=0;
+ AI_RESULT<=0;
+ TXD_Start<=1'b0;
+ NO_OF_MOVES<=0;
+ AI_INPUT<=0;
+ AI_INPUT_MOVE<=0;
+
+ end
+ else
+ begin
+ mAI_ST<=mAI_ST_next;
+ wait_count <=wait_count_next;
+ move_count_me<=move_count_me_next;
+ AI_RESULT<=AI_RESULT_next;
+ TXD_Start<=TXD_Start_next;
+ NO_OF_MOVES<=NO_OF_MOVES_next;
+ AI_INPUT<=AI_INPUT_next;
+ AI_INPUT_MOVE<=AI_INPUT_MOVE_next;
+
+ end
+end
+
+
+always@*//(mAI_ST,move_count,iTXD_Done,TXD_Start,iAI_Done,iAI_DATA)
+begin
+ mAI_ST_next<=mAI_ST;
+ wait_count_next<=wait_count;
+ move_count_me_next<=move_count_me;
+ AI_RESULT_next<=AI_RESULT;
+ TXD_Start_next<=TXD_Start;
+ NO_OF_MOVES_next<=NO_OF_MOVES;
+ AI_INPUT_next <=AI_INPUT;
+ AI_INPUT_MOVE_next<=AI_INPUT_MOVE;
+ case(mAI_ST)
+
+
+ state0: begin
+ if( (CMD == 8'h44) && (move_count ==0))
+ begin
+ mAI_ST_next <= state1;
+ AI_INPUT_next<=CMD_Tmp;
+ AI_INPUT_MOVE_next<=move_count;
+ end
+ else if ( (CMD == 8'h4C) && (move_count ==1))
+ begin
+ mAI_ST_next <= state4;
+ AI_INPUT_next<=CMD_Tmp;
+ AI_INPUT_MOVE_next<=move_count;
+ end
+
+ else
+ mAI_ST_next <= state0;
+
+
+
+ end
+ state1: begin
+ mAI_ST_next <= state2;
+ end
+ state2: begin
+ if(iAI_Done == 1'b1)
+ begin
+ mAI_ST_next <= state3;
+ NO_OF_MOVES_next<=4;
+ AI_RESULT_next[63:0]<=iAI_DATA;
+ //AI_RESULT_next[63:0]<=CMD_Tmp;loop back
+
+ end
+ else begin
+ mAI_ST_next <= state2;
+ end
+
+
+ end
+ state3: begin
+
+ if(iTXD_Done == 1'b1 && TXD_Start ==1'b0)
+ begin
+ if(wait_count==NO_OF_MOVES) begin
+ mAI_ST_next <= state4;
+ wait_count_next<=0;
+ TXD_Start_next <=1'b0;
+ end
+ else begin
+ mAI_ST_next <= state3;
+ TXD_Start_next <=1'b1;
+ wait_count_next<=wait_count+1;
+ AI_RESULT_next<={AI_RESULT[63:0],8'h0};
+ move_count_me_next<=move_count_me+1;
+ end
+ end
+ else begin
+ TXD_Start_next <=1'b0;
+ end
+
+ end
+ state4: begin
+ //move_count % 4 == 0 means dark's turn, (move_count % 4 == 1 ) means light's turn
+ if((((move_count % 4) == 3 ) && (CMD ==8'h44))|| (((move_count % 4) == 1 ) && (CMD ==8'h4C)))
+ begin
+ //if(((move_count ==1|| move_count ==5|| move_count ==9) && (CMD ==8'h4C)))
+ mAI_ST_next <= state5;
+ AI_INPUT_next<=CMD_Tmp;
+ AI_INPUT_MOVE_next<=move_count;
+ end
+ else
+ mAI_ST_next <= state4;
+
+ end
+ state5: begin
+ mAI_ST_next <= state6;
+ AI_INPUT_next<=CMD_Tmp;
+ end
+ state6: begin
+ if(iAI_Done == 1'b1) begin
+ mAI_ST_next <= state3;
+ AI_RESULT_next[63:0]<=iAI_DATA;
+ //AI_RESULT_next[63:0]<=CMD_Tmp; loop back
+ NO_OF_MOVES_next<=8 ;
+ end
+
+ else begin
+ mAI_ST_next <= state6;
+ AI_RESULT_next<=0;
+ NO_OF_MOVES_next<=NO_OF_MOVES;
+ end
+
+ end
+ default:mAI_ST_next <= mAI_ST;
+ endcase
+
+
+end
+
+assign oTXD_DATA = AI_RESULT[71:64];
+
+assign oAI_DATA = AI_INPUT;
+
+always@(mAI_ST)
+begin
+ case(mAI_ST)
+
+
+ state0: begin
+
+ oAI_Start <=1'b0;
+ //oAI_DATA<=0;
+
+
+ end
+ state1: begin
+ oAI_Start <=1'b1;
+ //oAI_DATA<=CMD_Tmp[63:0];
+
+
+ //end
+ end
+ state2: begin
+
+ oAI_Start <=1'b0;
+ //oAI_DATA<=0;
+ //end
+ end
+ state3: begin
+ oAI_Start <=1'b0;
+ //oAI_DATA<=0;
+
+ //end
+ end
+ state4: begin
+ oAI_Start <=1'b0;
+ //oAI_DATA<=CMD_Tmp[63:0];
+
+
+ end
+ state5: begin
+ oAI_Start <=1'b1;
+ //oAI_DATA<=CMD_Tmp[63:0];
+
+
+ //end
+ end
+ state6: begin
+ oAI_Start <=1'b0;
+ //oAI_DATA<=CMD_Tmp[63:0];
+
+
+ //end
+ end
+ default:begin
+ oAI_Start <=1'b0;
+ //oAI_DATA<=CMD_Tmp[63:0];
+ end
+ endcase
+
+
+end
+endmodule
Index: trunk/XILINX/BUILD_SCC_SRCH/SP6/SEG7_LUT_8.v
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/SP6/SEG7_LUT_8.v (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/SP6/SEG7_LUT_8.v (revision 17)
@@ -0,0 +1,14 @@
+module SEG7_LUT_8 ( oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7,iDIG );
+input [31:0] iDIG;
+output [6:0] oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7;
+
+SEG7_LUT u0 ( oSEG0,iDIG[3:0] );
+SEG7_LUT u1 ( oSEG1,iDIG[7:4] );
+SEG7_LUT u2 ( oSEG2,iDIG[11:8] );
+SEG7_LUT u3 ( oSEG3,iDIG[15:12] );
+SEG7_LUT u4 ( oSEG4,iDIG[19:16] );
+SEG7_LUT u5 ( oSEG5,iDIG[23:20] );
+SEG7_LUT u6 ( oSEG6,iDIG[27:24] );
+SEG7_LUT u7 ( oSEG7,iDIG[31:28] );
+
+endmodule
\ No newline at end of file
trunk/XILINX/BUILD_SCC_SRCH/SP6/SEG7_LUT_8.v
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC_SRCH/SP6/SP6.ucf
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/SP6/SP6.ucf (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/SP6/SP6.ucf (revision 17)
@@ -0,0 +1,48 @@
+#
+# Constraints generated by Synplify Pro map500rc, Build 036R
+#
+
+# Period Constraints
+NET "SYSCLK_P" TNM_NET = "SYSCLK_P";
+TIMESPEC "TS_SYSCLK_P" = PERIOD "SYSCLK_P" 5 ns HIGH 50 %;
+
+#Begin clock constraints
+NET "clocks/clk20_bufg_in" TNM_NET = "clocks_clk20_bufg_in";
+TIMESPEC "TS_clocks_clk20_bufg_in" = PERIOD "clocks_clk20_bufg_in" 50.000 ns HIGH 50.00%;
+#NET "clocks/clkfbout_clkfbin_125" TNM_NET = "clocks_clkfbout_clkfbin_125";
+#TIMESPEC "TS_clocks_clkfbout_clkfbin_125" = PERIOD "clocks_clkfbout_clkfbin_125" 50.000 ns HIGH 50.00%;
+#NET "clocks/osc_clk_ibufg" TNM_NET = "clocks_osc_clk_ibufg";
+#TIMESPEC "TS_clocks_osc_clk_ibufg" = PERIOD "clocks_osc_clk_ibufg" 50.000 ns HIGH 50.00%;
+#End clock constraints
+
+# Unconstrained Outputs
+
+NET "HEX0[*]" TIG; # port HEX0[6:0]
+NET "HEX1[*]" TIG; # port HEX1[6:0]
+NET "HEX2[*]" TIG; # port HEX2[6:0]
+NET "HEX3[*]" TIG; # port HEX3[6:0]
+NET "HEX4[*]" TIG; # port HEX4[6:0]
+NET "HEX5[*]" TIG; # port HEX5[6:0]
+NET "HEX6[*]" TIG; # port HEX6[6:0]
+NET "HEX7[*]" TIG; # port HEX7[6:0]
+#NET "LED_GREEN[*]" TIG; # port LED_GREEN[8:0]
+#NET "LED_RED[*]" TIG; # port LED_RED[17:0]
+#NET "UART_TXD" TIG;
+NET "TD_RESET" TIG;
+
+
+# Location Constraints
+#PIN "clocks/clk20_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;
+
+## Clock inputs
+NET "SYSCLK_P" LOC = "K21" |IOSTANDARD=LVDS_25;
+NET "SYSCLK_N" LOC = "K22" |IOSTANDARD=LVDS_25;
+
+NET "LED_RED[9]" LOC = "D17"; ## 2 on DS3 LED
+NET "LED_RED[10]" LOC = "AB4"; ## 2 on DS4 LED
+NET "LED_RED[11]" LOC = "D21"; ## 2 on DS5 LED
+NET "LED_RED[12]" LOC = "W15"; ## 2 on DS6 LED
+NET "KEY[0]" LOC = "F3"; ## 2 on SW4 pushbutton (active-high)
+NET "UART_TXD" LOC = "B21"; ##
+NET "UART_RXD" LOC = "H17"; ##
+# End of generated constraints
Index: trunk/XILINX/BUILD_SCC_SRCH/SP6/quartus.tcl
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/SP6/quartus.tcl (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/SP6/quartus.tcl (revision 17)
@@ -0,0 +1,554 @@
+
+#set project_name connect6ai_synth_tcab
+#set top_level connect6ai_synth_tcab
+set project_name DE2
+set top_level DE2
+set family "CycloneII"
+set device EP2C35F672C6
+set sdc_constraints ../constraints.sdc
+
+# create new project
+project_new ${project_name}
+
+# project settings
+
+set_global_assignment -name TOP_LEVEL_ENTITY ${top_level}
+set_global_assignment -name family ${family}
+set_global_assignment -name device ${device}
+set_global_assignment -name SDC_FILE ${sdc_constraints}
+set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS OFF
+#set_global_assignment -name AUTO_RESOURCE_SHARING ON
+
+create_base_clock -fmax 50MHz clk -target OSC_50
+#verilog files
+set mcsfiles [glob -directory ../../../macrocells -nocomplain -tails -types f -- {*\.v}]
+foreach mcs ${mcsfiles} {
+ if [ regexp -- {assertions} ${mcs} ] {
+ continue
+}
+ set_global_assignment -name VERILOG_FILE "../../../macrocells/${mcs}"
+}
+
+set rtlfiles [glob -directory ../../../rtl -nocomplain -tails -types f -- {*\.v}]
+foreach rtl ${rtlfiles} {
+ if [ regexp -- {assertions} ${rtl} ] {
+ continue
+ }
+ set_global_assignment -name VERILOG_FILE "../../../rtl/${rtl}"
+}
+#set_global_assignment -name VERILOG_FILE ../../../../rtl_package/simu_stubs/vsim/bram_based_stream_buffer.v
+#DE2 files
+set de2files [glob -directory ../../../../DE2/ -nocomplain -tails -types f -- {*\.v}]
+foreach mcs ${de2files} {
+ if [ regexp -- {assertions} ${mcs} ] {
+ continue
+}
+ set_global_assignment -name VERILOG_FILE "../../../../DE2/${mcs}"
+}
+set de2files [glob -directory ../../../../DE2/ -nocomplain -tails -types f -- {*\.vhd}]
+foreach mcs ${de2files} {
+ if [ regexp -- {assertions} ${mcs} ] {
+ continue
+}
+ set_global_assignment -name VHDL_FILE "../../../../DE2/${mcs}"
+}
+set_global_assignment -name VHDL_FILE "../../../../DE2/pll/pll.vhd"
+set_global_assignment -name MISC_FILE "../../../../DE2/pll/pll_inst.vhd"
+set_global_assignment -name MISC_FILE "../../../../DE2/pll/pll.cmp"
+set_global_assignment -name MISC_FILE "../../../../DE2/pll/pll.ppf"
+set_global_assignment -name MISC_FILE "../../../../DE2/pll/pll_syn.v"
+
+# run the flow
+#execute_flow -compile
+
+#load_package flow
+#execute_module -tool map
+#set name_ids [get_names -filter * -node_type pin]
+#foreach_in_collection name_id $name_ids {
+# set pin_name [get_name_info -info full_path $name_id]
+# post_message "Making VIRTUAL_PIN assignment to $pin_name"
+# set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
+#}
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_N25 -to DPDT_SW[0]
+set_location_assignment PIN_N26 -to DPDT_SW[1]
+set_location_assignment PIN_P25 -to DPDT_SW[2]
+set_location_assignment PIN_AE14 -to DPDT_SW[3]
+set_location_assignment PIN_AF14 -to DPDT_SW[4]
+set_location_assignment PIN_AD13 -to DPDT_SW[5]
+set_location_assignment PIN_AC13 -to DPDT_SW[6]
+set_location_assignment PIN_C13 -to DPDT_SW[7]
+set_location_assignment PIN_B13 -to DPDT_SW[8]
+set_location_assignment PIN_A13 -to DPDT_SW[9]
+set_location_assignment PIN_N1 -to DPDT_SW[10]
+set_location_assignment PIN_P1 -to DPDT_SW[11]
+set_location_assignment PIN_P2 -to DPDT_SW[12]
+set_location_assignment PIN_T7 -to DPDT_SW[13]
+set_location_assignment PIN_U3 -to DPDT_SW[14]
+set_location_assignment PIN_U4 -to DPDT_SW[15]
+set_location_assignment PIN_V1 -to DPDT_SW[16]
+set_location_assignment PIN_V2 -to DPDT_SW[17]
+set_location_assignment PIN_T6 -to DRAM_ADDR[0]
+set_location_assignment PIN_V4 -to DRAM_ADDR[1]
+set_location_assignment PIN_V3 -to DRAM_ADDR[2]
+set_location_assignment PIN_W2 -to DRAM_ADDR[3]
+set_location_assignment PIN_W1 -to DRAM_ADDR[4]
+set_location_assignment PIN_U6 -to DRAM_ADDR[5]
+set_location_assignment PIN_U7 -to DRAM_ADDR[6]
+set_location_assignment PIN_U5 -to DRAM_ADDR[7]
+set_location_assignment PIN_W4 -to DRAM_ADDR[8]
+set_location_assignment PIN_W3 -to DRAM_ADDR[9]
+set_location_assignment PIN_Y1 -to DRAM_ADDR[10]
+set_location_assignment PIN_V5 -to DRAM_ADDR[11]
+set_location_assignment PIN_AE2 -to DRAM_BA_0
+set_location_assignment PIN_AE3 -to DRAM_BA_1
+set_location_assignment PIN_AB3 -to DRAM_CAS_N
+set_location_assignment PIN_AA6 -to DRAM_CKE
+set_location_assignment PIN_AA7 -to DRAM_CLK
+set_location_assignment PIN_AC3 -to DRAM_CS_N
+set_location_assignment PIN_V6 -to DRAM_DQ[0]
+set_location_assignment PIN_AA2 -to DRAM_DQ[1]
+set_location_assignment PIN_AA1 -to DRAM_DQ[2]
+set_location_assignment PIN_Y3 -to DRAM_DQ[3]
+set_location_assignment PIN_Y4 -to DRAM_DQ[4]
+set_location_assignment PIN_R8 -to DRAM_DQ[5]
+set_location_assignment PIN_T8 -to DRAM_DQ[6]
+set_location_assignment PIN_V7 -to DRAM_DQ[7]
+set_location_assignment PIN_W6 -to DRAM_DQ[8]
+set_location_assignment PIN_AB2 -to DRAM_DQ[9]
+set_location_assignment PIN_AB1 -to DRAM_DQ[10]
+set_location_assignment PIN_AA4 -to DRAM_DQ[11]
+set_location_assignment PIN_AA3 -to DRAM_DQ[12]
+set_location_assignment PIN_AC2 -to DRAM_DQ[13]
+set_location_assignment PIN_AC1 -to DRAM_DQ[14]
+set_location_assignment PIN_AA5 -to DRAM_DQ[15]
+set_location_assignment PIN_AD2 -to DRAM_LDQM
+set_location_assignment PIN_Y5 -to DRAM_UDQM
+set_location_assignment PIN_AB4 -to DRAM_RAS_N
+set_location_assignment PIN_AD3 -to DRAM_WE_N
+set_location_assignment PIN_AC18 -to FL_ADDR[0]
+set_location_assignment PIN_AB18 -to FL_ADDR[1]
+set_location_assignment PIN_AE19 -to FL_ADDR[2]
+set_location_assignment PIN_AF19 -to FL_ADDR[3]
+set_location_assignment PIN_AE18 -to FL_ADDR[4]
+set_location_assignment PIN_AF18 -to FL_ADDR[5]
+set_location_assignment PIN_Y16 -to FL_ADDR[6]
+set_location_assignment PIN_AA16 -to FL_ADDR[7]
+set_location_assignment PIN_AD17 -to FL_ADDR[8]
+set_location_assignment PIN_AC17 -to FL_ADDR[9]
+set_location_assignment PIN_AE17 -to FL_ADDR[10]
+set_location_assignment PIN_AF17 -to FL_ADDR[11]
+set_location_assignment PIN_W16 -to FL_ADDR[12]
+set_location_assignment PIN_W15 -to FL_ADDR[13]
+set_location_assignment PIN_AC16 -to FL_ADDR[14]
+set_location_assignment PIN_AD16 -to FL_ADDR[15]
+set_location_assignment PIN_AE16 -to FL_ADDR[16]
+set_location_assignment PIN_AC15 -to FL_ADDR[17]
+set_location_assignment PIN_AB15 -to FL_ADDR[18]
+set_location_assignment PIN_AA15 -to FL_ADDR[19]
+set_location_assignment PIN_V17 -to FL_CE_N
+set_location_assignment PIN_W17 -to FL_OE_N
+set_location_assignment PIN_AD19 -to FL_DQ[0]
+set_location_assignment PIN_AC19 -to FL_DQ[1]
+set_location_assignment PIN_AF20 -to FL_DQ[2]
+set_location_assignment PIN_AE20 -to FL_DQ[3]
+set_location_assignment PIN_AB20 -to FL_DQ[4]
+set_location_assignment PIN_AC20 -to FL_DQ[5]
+set_location_assignment PIN_AF21 -to FL_DQ[6]
+set_location_assignment PIN_AE21 -to FL_DQ[7]
+set_location_assignment PIN_AA18 -to FL_RST_N
+set_location_assignment PIN_AA17 -to FL_WE_N
+set_location_assignment PIN_AF10 -to HEX0[0]
+set_location_assignment PIN_AB12 -to HEX0[1]
+set_location_assignment PIN_AC12 -to HEX0[2]
+set_location_assignment PIN_AD11 -to HEX0[3]
+set_location_assignment PIN_AE11 -to HEX0[4]
+set_location_assignment PIN_V14 -to HEX0[5]
+set_location_assignment PIN_V13 -to HEX0[6]
+set_location_assignment PIN_V20 -to HEX1[0]
+set_location_assignment PIN_V21 -to HEX1[1]
+set_location_assignment PIN_W21 -to HEX1[2]
+set_location_assignment PIN_Y22 -to HEX1[3]
+set_location_assignment PIN_AA24 -to HEX1[4]
+set_location_assignment PIN_AA23 -to HEX1[5]
+set_location_assignment PIN_AB24 -to HEX1[6]
+set_location_assignment PIN_AB23 -to HEX2[0]
+set_location_assignment PIN_V22 -to HEX2[1]
+set_location_assignment PIN_AC25 -to HEX2[2]
+set_location_assignment PIN_AC26 -to HEX2[3]
+set_location_assignment PIN_AB26 -to HEX2[4]
+set_location_assignment PIN_AB25 -to HEX2[5]
+set_location_assignment PIN_Y24 -to HEX2[6]
+set_location_assignment PIN_Y23 -to HEX3[0]
+set_location_assignment PIN_AA25 -to HEX3[1]
+set_location_assignment PIN_AA26 -to HEX3[2]
+set_location_assignment PIN_Y26 -to HEX3[3]
+set_location_assignment PIN_Y25 -to HEX3[4]
+set_location_assignment PIN_U22 -to HEX3[5]
+set_location_assignment PIN_W24 -to HEX3[6]
+set_location_assignment PIN_U9 -to HEX4[0]
+set_location_assignment PIN_U1 -to HEX4[1]
+set_location_assignment PIN_U2 -to HEX4[2]
+set_location_assignment PIN_T4 -to HEX4[3]
+set_location_assignment PIN_R7 -to HEX4[4]
+set_location_assignment PIN_R6 -to HEX4[5]
+set_location_assignment PIN_T3 -to HEX4[6]
+set_location_assignment PIN_T2 -to HEX5[0]
+set_location_assignment PIN_P6 -to HEX5[1]
+set_location_assignment PIN_P7 -to HEX5[2]
+set_location_assignment PIN_T9 -to HEX5[3]
+set_location_assignment PIN_R5 -to HEX5[4]
+set_location_assignment PIN_R4 -to HEX5[5]
+set_location_assignment PIN_R3 -to HEX5[6]
+set_location_assignment PIN_R2 -to HEX6[0]
+set_location_assignment PIN_P4 -to HEX6[1]
+set_location_assignment PIN_P3 -to HEX6[2]
+set_location_assignment PIN_M2 -to HEX6[3]
+set_location_assignment PIN_M3 -to HEX6[4]
+set_location_assignment PIN_M5 -to HEX6[5]
+set_location_assignment PIN_M4 -to HEX6[6]
+set_location_assignment PIN_L3 -to HEX7[0]
+set_location_assignment PIN_L2 -to HEX7[1]
+set_location_assignment PIN_L9 -to HEX7[2]
+set_location_assignment PIN_L6 -to HEX7[3]
+set_location_assignment PIN_L7 -to HEX7[4]
+set_location_assignment PIN_P9 -to HEX7[5]
+set_location_assignment PIN_N9 -to HEX7[6]
+set_location_assignment PIN_G26 -to KEY[0]
+set_location_assignment PIN_N23 -to KEY[1]
+set_location_assignment PIN_P23 -to KEY[2]
+set_location_assignment PIN_W26 -to KEY[3]
+set_location_assignment PIN_AE23 -to LED_RED[0]
+set_location_assignment PIN_AF23 -to LED_RED[1]
+set_location_assignment PIN_AB21 -to LED_RED[2]
+set_location_assignment PIN_AC22 -to LED_RED[3]
+set_location_assignment PIN_AD22 -to LED_RED[4]
+set_location_assignment PIN_AD23 -to LED_RED[5]
+set_location_assignment PIN_AD21 -to LED_RED[6]
+set_location_assignment PIN_AC21 -to LED_RED[7]
+set_location_assignment PIN_AA14 -to LED_RED[8]
+set_location_assignment PIN_Y13 -to LED_RED[9]
+set_location_assignment PIN_AA13 -to LED_RED[10]
+set_location_assignment PIN_AC14 -to LED_RED[11]
+set_location_assignment PIN_AD15 -to LED_RED[12]
+set_location_assignment PIN_AE15 -to LED_RED[13]
+set_location_assignment PIN_AF13 -to LED_RED[14]
+set_location_assignment PIN_AE13 -to LED_RED[15]
+set_location_assignment PIN_AE12 -to LED_RED[16]
+set_location_assignment PIN_AD12 -to LED_RED[17]
+set_location_assignment PIN_AE22 -to LED_GREEN[0]
+set_location_assignment PIN_AF22 -to LED_GREEN[1]
+set_location_assignment PIN_W19 -to LED_GREEN[2]
+set_location_assignment PIN_V18 -to LED_GREEN[3]
+set_location_assignment PIN_U18 -to LED_GREEN[4]
+set_location_assignment PIN_U17 -to LED_GREEN[5]
+set_location_assignment PIN_AA20 -to LED_GREEN[6]
+set_location_assignment PIN_Y18 -to LED_GREEN[7]
+set_location_assignment PIN_Y12 -to LED_GREEN[8]
+set_location_assignment PIN_D13 -to OSC_27
+set_location_assignment PIN_N2 -to OSC_50
+set_location_assignment PIN_P26 -to EXT_CLOCK
+set_location_assignment PIN_D26 -to PS2_CLK
+set_location_assignment PIN_C24 -to PS2_DAT
+set_location_assignment PIN_C25 -to UART_RXD
+set_location_assignment PIN_B25 -to UART_TXD
+set_location_assignment PIN_K4 -to LCD_RW
+set_location_assignment PIN_K3 -to LCD_EN
+set_location_assignment PIN_K1 -to LCD_RS
+set_location_assignment PIN_J1 -to LCD_DATA[0]
+set_location_assignment PIN_J2 -to LCD_DATA[1]
+set_location_assignment PIN_H1 -to LCD_DATA[2]
+set_location_assignment PIN_H2 -to LCD_DATA[3]
+set_location_assignment PIN_J4 -to LCD_DATA[4]
+set_location_assignment PIN_J3 -to LCD_DATA[5]
+set_location_assignment PIN_H4 -to LCD_DATA[6]
+set_location_assignment PIN_H3 -to LCD_DATA[7]
+set_location_assignment PIN_L4 -to LCD_ON
+set_location_assignment PIN_K2 -to LCD_BLON
+set_location_assignment PIN_AE4 -to SRAM_ADDR[0]
+set_location_assignment PIN_AF4 -to SRAM_ADDR[1]
+set_location_assignment PIN_AC5 -to SRAM_ADDR[2]
+set_location_assignment PIN_AC6 -to SRAM_ADDR[3]
+set_location_assignment PIN_AD4 -to SRAM_ADDR[4]
+set_location_assignment PIN_AD5 -to SRAM_ADDR[5]
+set_location_assignment PIN_AE5 -to SRAM_ADDR[6]
+set_location_assignment PIN_AF5 -to SRAM_ADDR[7]
+set_location_assignment PIN_AD6 -to SRAM_ADDR[8]
+set_location_assignment PIN_AD7 -to SRAM_ADDR[9]
+set_location_assignment PIN_V10 -to SRAM_ADDR[10]
+set_location_assignment PIN_V9 -to SRAM_ADDR[11]
+set_location_assignment PIN_AC7 -to SRAM_ADDR[12]
+set_location_assignment PIN_W8 -to SRAM_ADDR[13]
+set_location_assignment PIN_W10 -to SRAM_ADDR[14]
+set_location_assignment PIN_Y10 -to SRAM_ADDR[15]
+set_location_assignment PIN_AB8 -to SRAM_ADDR[16]
+set_location_assignment PIN_AC8 -to SRAM_ADDR[17]
+set_location_assignment PIN_AD8 -to SRAM_DQ[0]
+set_location_assignment PIN_AE6 -to SRAM_DQ[1]
+set_location_assignment PIN_AF6 -to SRAM_DQ[2]
+set_location_assignment PIN_AA9 -to SRAM_DQ[3]
+set_location_assignment PIN_AA10 -to SRAM_DQ[4]
+set_location_assignment PIN_AB10 -to SRAM_DQ[5]
+set_location_assignment PIN_AA11 -to SRAM_DQ[6]
+set_location_assignment PIN_Y11 -to SRAM_DQ[7]
+set_location_assignment PIN_AE7 -to SRAM_DQ[8]
+set_location_assignment PIN_AF7 -to SRAM_DQ[9]
+set_location_assignment PIN_AE8 -to SRAM_DQ[10]
+set_location_assignment PIN_AF8 -to SRAM_DQ[11]
+set_location_assignment PIN_W11 -to SRAM_DQ[12]
+set_location_assignment PIN_W12 -to SRAM_DQ[13]
+set_location_assignment PIN_AC9 -to SRAM_DQ[14]
+set_location_assignment PIN_AC10 -to SRAM_DQ[15]
+set_location_assignment PIN_AE10 -to SRAM_WE_N
+set_location_assignment PIN_AD10 -to SRAM_OE_N
+set_location_assignment PIN_AF9 -to SRAM_UB_N
+set_location_assignment PIN_AE9 -to SRAM_LB_N
+set_location_assignment PIN_AC11 -to SRAM_CE_N
+set_location_assignment PIN_K7 -to OTG_ADDR[0]
+set_location_assignment PIN_F2 -to OTG_ADDR[1]
+set_location_assignment PIN_F1 -to OTG_CS_N
+set_location_assignment PIN_G2 -to OTG_RD_N
+set_location_assignment PIN_G1 -to OTG_WR_N
+set_location_assignment PIN_G5 -to OTG_RST_N
+set_location_assignment PIN_F4 -to OTG_DATA[0]
+set_location_assignment PIN_D2 -to OTG_DATA[1]
+set_location_assignment PIN_D1 -to OTG_DATA[2]
+set_location_assignment PIN_F7 -to OTG_DATA[3]
+set_location_assignment PIN_J5 -to OTG_DATA[4]
+set_location_assignment PIN_J8 -to OTG_DATA[5]
+set_location_assignment PIN_J7 -to OTG_DATA[6]
+set_location_assignment PIN_H6 -to OTG_DATA[7]
+set_location_assignment PIN_E2 -to OTG_DATA[8]
+set_location_assignment PIN_E1 -to OTG_DATA[9]
+set_location_assignment PIN_K6 -to OTG_DATA[10]
+set_location_assignment PIN_K5 -to OTG_DATA[11]
+set_location_assignment PIN_G4 -to OTG_DATA[12]
+set_location_assignment PIN_G3 -to OTG_DATA[13]
+set_location_assignment PIN_J6 -to OTG_DATA[14]
+set_location_assignment PIN_K8 -to OTG_DATA[15]
+set_location_assignment PIN_B3 -to OTG_INT0
+set_location_assignment PIN_C3 -to OTG_INT1
+set_location_assignment PIN_C2 -to OTG_DACK0_N
+set_location_assignment PIN_B2 -to OTG_DACK1_N
+set_location_assignment PIN_F6 -to OTG_DREQ0
+set_location_assignment PIN_E5 -to OTG_DREQ1
+set_location_assignment PIN_F3 -to OTG_FSPEED
+set_location_assignment PIN_G6 -to OTG_LSPEED
+set_location_assignment PIN_B14 -to TDI
+set_location_assignment PIN_A14 -to TCS
+set_location_assignment PIN_D14 -to TCK
+set_location_assignment PIN_F14 -to TDO
+set_location_assignment PIN_C4 -to TD_RESET
+set_location_assignment PIN_C8 -to VGA_R[0]
+set_location_assignment PIN_F10 -to VGA_R[1]
+set_location_assignment PIN_G10 -to VGA_R[2]
+set_location_assignment PIN_D9 -to VGA_R[3]
+set_location_assignment PIN_C9 -to VGA_R[4]
+set_location_assignment PIN_A8 -to VGA_R[5]
+set_location_assignment PIN_H11 -to VGA_R[6]
+set_location_assignment PIN_H12 -to VGA_R[7]
+set_location_assignment PIN_F11 -to VGA_R[8]
+set_location_assignment PIN_E10 -to VGA_R[9]
+set_location_assignment PIN_B9 -to VGA_G[0]
+set_location_assignment PIN_A9 -to VGA_G[1]
+set_location_assignment PIN_C10 -to VGA_G[2]
+set_location_assignment PIN_D10 -to VGA_G[3]
+set_location_assignment PIN_B10 -to VGA_G[4]
+set_location_assignment PIN_A10 -to VGA_G[5]
+set_location_assignment PIN_G11 -to VGA_G[6]
+set_location_assignment PIN_D11 -to VGA_G[7]
+set_location_assignment PIN_E12 -to VGA_G[8]
+set_location_assignment PIN_D12 -to VGA_G[9]
+set_location_assignment PIN_J13 -to VGA_B[0]
+set_location_assignment PIN_J14 -to VGA_B[1]
+set_location_assignment PIN_F12 -to VGA_B[2]
+set_location_assignment PIN_G12 -to VGA_B[3]
+set_location_assignment PIN_J10 -to VGA_B[4]
+set_location_assignment PIN_J11 -to VGA_B[5]
+set_location_assignment PIN_C11 -to VGA_B[6]
+set_location_assignment PIN_B11 -to VGA_B[7]
+set_location_assignment PIN_C12 -to VGA_B[8]
+set_location_assignment PIN_B12 -to VGA_B[9]
+set_location_assignment PIN_B8 -to VGA_CLK
+set_location_assignment PIN_D6 -to VGA_BLANK
+set_location_assignment PIN_A7 -to VGA_HS
+set_location_assignment PIN_D8 -to VGA_VS
+set_location_assignment PIN_B7 -to VGA_SYNC
+set_location_assignment PIN_A6 -to I2C_SCLK
+set_location_assignment PIN_B6 -to I2C_SDAT
+set_location_assignment PIN_J9 -to TD_DATA[0]
+set_location_assignment PIN_E8 -to TD_DATA[1]
+set_location_assignment PIN_H8 -to TD_DATA[2]
+set_location_assignment PIN_H10 -to TD_DATA[3]
+set_location_assignment PIN_G9 -to TD_DATA[4]
+set_location_assignment PIN_F9 -to TD_DATA[5]
+set_location_assignment PIN_D7 -to TD_DATA[6]
+set_location_assignment PIN_C7 -to TD_DATA[7]
+set_location_assignment PIN_D5 -to TD_HS
+set_location_assignment PIN_K9 -to TD_VS
+set_location_assignment PIN_C5 -to AUD_ADCLRCK
+set_location_assignment PIN_B5 -to AUD_ADCDAT
+set_location_assignment PIN_C6 -to AUD_DACLRCK
+set_location_assignment PIN_A4 -to AUD_DACDAT
+set_location_assignment PIN_A5 -to AUD_XCK
+set_location_assignment PIN_B4 -to AUD_BCLK
+set_location_assignment PIN_D17 -to ENET_DATA[0]
+set_location_assignment PIN_C17 -to ENET_DATA[1]
+set_location_assignment PIN_B18 -to ENET_DATA[2]
+set_location_assignment PIN_A18 -to ENET_DATA[3]
+set_location_assignment PIN_B17 -to ENET_DATA[4]
+set_location_assignment PIN_A17 -to ENET_DATA[5]
+set_location_assignment PIN_B16 -to ENET_DATA[6]
+set_location_assignment PIN_B15 -to ENET_DATA[7]
+set_location_assignment PIN_B20 -to ENET_DATA[8]
+set_location_assignment PIN_A20 -to ENET_DATA[9]
+set_location_assignment PIN_C19 -to ENET_DATA[10]
+set_location_assignment PIN_D19 -to ENET_DATA[11]
+set_location_assignment PIN_B19 -to ENET_DATA[12]
+set_location_assignment PIN_A19 -to ENET_DATA[13]
+set_location_assignment PIN_E18 -to ENET_DATA[14]
+set_location_assignment PIN_D18 -to ENET_DATA[15]
+set_location_assignment PIN_B24 -to ENET_CLK
+set_location_assignment PIN_A21 -to ENET_CMD
+set_location_assignment PIN_A23 -to ENET_CS_N
+set_location_assignment PIN_B21 -to ENET_INT
+set_location_assignment PIN_A22 -to ENET_RD_N
+set_location_assignment PIN_B22 -to ENET_WR_N
+set_location_assignment PIN_B23 -to ENET_RST_N
+set_location_assignment PIN_AE24 -to IRDA_TXD
+set_location_assignment PIN_AE25 -to IRDA_RXD
+set_location_assignment PIN_AD24 -to SD_DAT
+set_location_assignment PIN_AC23 -to SD_DAT3
+set_location_assignment PIN_Y21 -to SD_CMD
+set_location_assignment PIN_AD25 -to SD_CLK
+#set_location_assignment PIN_D25 -to GPIO_0[0]
+#set_location_assignment PIN_J22 -to GPIO_0[1]
+#set_location_assignment PIN_E26 -to GPIO_0[2]
+#set_location_assignment PIN_E25 -to GPIO_0[3]
+#set_location_assignment PIN_F24 -to GPIO_0[4]
+#set_location_assignment PIN_F23 -to GPIO_0[5]
+#set_location_assignment PIN_J21 -to GPIO_0[6]
+set_location_assignment PIN_J21 -to UART_RXD_JP1_7
+#set_location_assignment PIN_J20 -to GPIO_0[7]
+#set_location_assignment PIN_F25 -to GPIO_0[8]
+#set_location_assignment PIN_F26 -to GPIO_0[9]
+set_location_assignment PIN_N18 -to GPIO_0_10
+#set_location_assignment PIN_P18 -to GPIO_0[11]
+#set_location_assignment PIN_G23 -to GPIO_0[12]
+#set_location_assignment PIN_G24 -to GPIO_0[13]
+#set_location_assignment PIN_K22 -to GPIO_0[14]
+#set_location_assignment PIN_G25 -to GPIO_0[15]
+#set_location_assignment PIN_H23 -to GPIO_0[16]
+#set_location_assignment PIN_H24 -to GPIO_0[17]
+#set_location_assignment PIN_J23 -to GPIO_0[18]
+#set_location_assignment PIN_J24 -to GPIO_0[19]
+#set_location_assignment PIN_H25 -to GPIO_0[20]
+set_location_assignment PIN_H25 -to I_OR7_JP1_35_bis
+#set_location_assignment PIN_H26 -to GPIO_0[21]
+#set_location_assignment PIN_H19 -to GPIO_0[22]
+set_location_assignment PIN_H19 -to I_OR8_JP1_36_bis
+#set_location_assignment PIN_K18 -to GPIO_0_[23]
+#set_location_assignment PIN_K19 -to GPIO_0[24]
+set_location_assignment PIN_K19 -to UART_TXD_JP1_27
+#set_location_assignment PIN_K21 -to GPIO_0[25]
+#set_location_assignment PIN_K23 -to GPIO_0[26]
+#set_location_assignment PIN_K24 -to GPIO_0[27]
+#set_location_assignment PIN_L21 -to GPIO_0[28]
+#set_location_assignment PIN_L20 -to GPIO_0[29]
+#set_location_assignment PIN_J25 -to GPIO_0[30]
+set_location_assignment PIN_J25 -to I_OR7_JP1_35
+#set_location_assignment PIN_J26 -to GPIO_0[31]
+set_location_assignment PIN_J26 -to I_OR8_JP1_36
+#set_location_assignment PIN_L23 -to GPIO_0[32]
+set_location_assignment PIN_L23 -to CONFIG_MODE_JP1_37
+#set_location_assignment PIN_L24 -to GPIO_0[33]
+set_location_assignment PIN_L24 -to I_OT2_JP1_38
+#set_location_assignment PIN_L25 -to GPIO_0[34]
+#set_location_assignment PIN_L19 -to GPIO_0[35]
+set_location_assignment PIN_L25 -to INIT_JP1_39
+#set_location_assignment PIN_K25 -to GPIO_1[0]
+set_location_assignment PIN_K25 -to I_OT7_JP2_41
+#set_location_assignment PIN_K26 -to GPIO_1[1]
+set_location_assignment PIN_K26 -to I_OT6_JP2_42
+#set_location_assignment PIN_M22 -to GPIO_1[2]
+set_location_assignment PIN_M22 -to I_OT4_JP2_43
+#set_location_assignment PIN_M23 -to GPIO_1[3]
+set_location_assignment PIN_M23 -to I_OT3_JP2_44
+#set_location_assignment PIN_M19 -to GPIO_1[4]
+set_location_assignment PIN_M19 -to I_OT1_JP2_45
+#set_location_assignment PIN_M20 -to GPIO_1[5]
+set_location_assignment PIN_M20 -to I_OT0_JP2_46
+#set_location_assignment PIN_N20 -to GPIO_1[6]
+set_location_assignment PIN_N20 -to CONFIG_OUT0_JP2_47
+#set_location_assignment PIN_M21 -to GPIO_1[7]
+set_location_assignment PIN_M21 -to I_OL6_JP2_48
+#set_location_assignment PIN_M24 -to GPIO_1[8]
+set_location_assignment PIN_M24 -to CONFIG_OUT1_JP2_49
+#set_location_assignment PIN_M25 -to GPIO_1[9]
+set_location_assignment PIN_M25 -to I_OL3_JP2_50
+#set_location_assignment PIN_N24 -to GPIO_1_10
+set_location_assignment PIN_N24 -to I_OL7_JP2_53
+#set_location_assignment PIN_P24 -to GPIO_1[11]
+set_location_assignment PIN_P24 -to I_OL0_JP2_54
+#set_location_assignment PIN_R25 -to GPIO_1[12]
+set_location_assignment PIN_R25 -to I_OL4_JP2_55
+#set_location_assignment PIN_R24 -to GPIO_1[13]
+set_location_assignment PIN_R24 -to I_OL8_JP2_56
+#set_location_assignment PIN_R20 -to GPIO_1[14]
+set_location_assignment PIN_R20 -to I_OL1_JP2_57
+#set_location_assignment PIN_T22 -to GPIO_1[15]
+set_location_assignment PIN_T22 -to I_OT8_JP2_58
+#set_location_assignment PIN_T23 -to GPIO_1_16
+set_location_assignment PIN_T23 -to I_OL2_JP2_59
+#set_location_assignment PIN_T24 -to GPIO_1[17]
+set_location_assignment PIN_T24 -to I_OB2_JP2_60
+#set_location_assignment PIN_T25 -to GPIO_1[18]
+set_location_assignment PIN_T25 -to I_OL5_JP2_61
+#set_location_assignment PIN_T18 -to GPIO_1[19]
+set_location_assignment PIN_T18 -to I_OB5_JP2_62
+#set_location_assignment PIN_T21 -to GPIO_1[20]
+set_location_assignment PIN_T21 -to I_OT5_JP2_63
+#set_location_assignment PIN_T20 -to GPIO_1[21]
+set_location_assignment PIN_T20 -to I_OR2_JP2_64
+#set_location_assignment PIN_U26 -to GPIO_1[22]
+set_location_assignment PIN_U26 -to I_OB8_JP2_65
+#set_location_assignment PIN_U25 -to GPIO_1[23]
+set_location_assignment PIN_U25 -to CONFIG_ACK_IN_JP2_66
+#set_location_assignment PIN_U23 -to GPIO_1[24]
+set_location_assignment PIN_U23 -to I_OR5_JP2_67
+#set_location_assignment PIN_U24 -to GPIO_1[25]
+set_location_assignment PIN_U24 -to I_OB0_JP2_68
+#set_location_assignment PIN_R19 -to GPIO_1[26]
+set_location_assignment PIN_R19 -to I_OB1_JP2_71
+#set_location_assignment PIN_T19 -to GPIO_1[27]
+set_location_assignment PIN_T19 -to I_OB3_JP2_72
+#set_location_assignment PIN_U20 -to GPIO_1[28]
+set_location_assignment PIN_U20 -to I_OB4_JP2_73
+#set_location_assignment PIN_U21 -to GPIO_1[29]
+set_location_assignment PIN_U21 -to I_OB6_JP2_74
+#set_location_assignment PIN_V26 -to GPIO_1[30]
+set_location_assignment PIN_V26 -to I_OB7_JP2_75
+#set_location_assignment PIN_V25 -to GPIO_1[31]
+set_location_assignment PIN_V25 -to I_OR0_JP2_76
+#set_location_assignment PIN_V24 -to GPIO_1[32]
+set_location_assignment PIN_V24 -to I_OR1_JP2_77
+#set_location_assignment PIN_V23 -to GPIO_1[33]
+set_location_assignment PIN_V23 -to I_OR3_JP2_78
+#set_location_assignment PIN_W25 -to GPIO_1[34]
+set_location_assignment PIN_W25 -to I_OR4_JP2_79
+#set_location_assignment PIN_W23 -to GPIO_1[35]
+set_location_assignment PIN_W23 -to I_OR6_JP2_80
+
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
+
+
+export_assignments
+
+# close the project
+project_close
+
Index: trunk/XILINX/BUILD_SCC_SRCH/SP6/do_synth
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/SP6/do_synth (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/SP6/do_synth (revision 17)
@@ -0,0 +1,49 @@
+
+#!/bin/sh
+
+run_logic_synthesis_only=0 ;
+while getopts ":s i" options; do
+ case $options in
+ i ) run_logic_synthesis_only=0;;
+ s ) run_logic_synthesis_only=1;;
+ ? ) echo $usage
+ exit 1;;
+ esac
+done
+
+################################
+# set up the verilog filelists:
+################################
+
+export date_of_run=`date +%Y.%m.%d_%H.%M.%S`
+mkdir run_$date_of_run
+rm -f run
+ln -s run_$date_of_run run
+
+cd run
+
+if [ $run_logic_synthesis_only -eq 1 ]; then
+ touch .LOGIC_SYNTHESIS_ONLY
+fi
+
+quartus_sh -t ../quartus.tcl
+if [[ $? != 0 ]]; then exit 1; fi
+
+quartus_map DE2
+if [[ $? != 0 ]]; then exit 1; fi
+
+if [ $run_logic_synthesis_only -eq 1 ]; then
+ quartus_fit --early_timing_estimate=realistic DE2
+ if [[ $? != 0 ]]; then exit 1; fi
+else
+ quartus_fit DE2
+ if [[ $? != 0 ]]; then exit 1; fi
+fi
+
+quartus_sta --do_report_timing DE2
+if [[ $? != 0 ]]; then exit 1; fi
+quartus_asm DE2
+quartus_pgm -c USB-Blaster -m jtag -o "p;DE2.sof"
+cd -
+exit 0
+
trunk/XILINX/BUILD_SCC_SRCH/SP6/do_synth
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC_SRCH/SP6/bram_based_stream_buffer.v
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/SP6/bram_based_stream_buffer.v (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/SP6/bram_based_stream_buffer.v (revision 17)
@@ -0,0 +1,244 @@
+// Copyright (c) 2011 Synopsys, Inc. All rights reserved.
+//
+//
+// $Revision: 1.8 $
+
+
+`timescale 1ns / 1ps
+
+`ifdef PICO_CLOCK_EDGE
+`else
+ `define PICO_CLOCK_EDGE posedge
+`endif
+`ifdef PICO_CLOCK_SENSITIVITY
+`else
+ `define PICO_CLOCK_SENSITIVITY clk
+`endif
+`ifdef PICO_RESET_SENSITIVITY
+`else
+ `define PICO_RESET_SENSITIVITY
+`endif
+`ifdef PICO_RESET_SENSITIVITY2
+`else
+ `define PICO_RESET_SENSITIVITY2 reset
+`endif
+
+`timescale 1 ns / 10 ps
+
+module bram_based_stream_buffer (clk, indata, outdata, store_ready, load_ready, reset, flush, load_req, store_req );
+
+ parameter width = 48;
+ parameter depth = 800;
+ parameter awidth = clogb2(depth);
+
+input clk, load_ready, store_ready, reset, flush;
+wire clk, load_ready, store_ready, reset, flush;
+
+input [width-1:0] indata;
+wire [width-1:0] indata;
+
+output load_req, store_req;
+wire load_req, store_req;
+
+output [width-1:0] outdata;
+wire [width-1:0] outdata;
+
+
+function integer clogb2(input integer depth);
+ begin
+ for (clogb2=0; depth>0; clogb2=clogb2+1)
+ depth= depth>>1;
+ end
+ endfunction
+
+ // 0in assert -var (depth >= 1)
+ // coverage off
+ // pragma coverage off
+ // VCS coverage off
+ // synopsys translate_off
+ initial begin
+ if ( depth < 1 ) begin
+ $display ("ERROR::::");
+ $display ("mc_log: ERROR: bram_based_stream_buffer of depth %0d in %m. This is unsupported.Stopping simulation",depth);
+ $display ("END ERROR");
+ $finish;
+ end
+ end
+ // synopsys translate_on
+ // VCS coverage on
+ // pragma coverage on
+ // coverage on
+
+reg [awidth-1:0] read_addr_ff, next_read_addr_ff, write_addr_ff;
+reg [awidth-1:0] count_ff ;
+reg full_ff, not_empty_ff, onefull_ff, init_ff;
+
+reg [width-1:0] bypass_reg_ff;
+reg bypass_reg_valid_ff;
+
+wire [width-1:0] bram_outdata;
+wire addq_only, shiftq_only, shiftq_addq, mem_is_empty;
+
+wire addq = load_ready;
+wire shiftq = store_ready;
+
+wire full_mem = full_ff;
+assign mem_is_empty = ~not_empty_ff;
+
+assign addq_only = (addq & !full_ff & (!shiftq |(shiftq & mem_is_empty)));
+assign shiftq_only = (shiftq & !mem_is_empty & (!addq | (addq & full_mem)) );
+assign shiftq_addq = (shiftq & addq & not_empty_ff & !full_mem);
+
+wire rreq, wreq;
+
+assign rreq = not_empty_ff;
+assign wreq = addq & !full_mem;
+assign load_req = !full_mem;
+assign store_req = !mem_is_empty;
+
+always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY ) begin
+ if (`PICO_RESET_SENSITIVITY2) begin
+ not_empty_ff <= 1'b0;
+ full_ff <= 1'b0;
+ init_ff <= 1'b0;
+ end
+ else if (flush) begin
+ not_empty_ff <= 1'b0;
+ full_ff <= 1'b0;
+ init_ff <= 1'b0;
+ end
+ else begin
+ init_ff <= 1'b1;
+ if (addq & mem_is_empty) begin
+ not_empty_ff <= 1'b1;
+ end
+ else if (shiftq & !addq & onefull_ff) begin
+ not_empty_ff <= 1'b0;
+ end
+
+ if (addq_only & (count_ff == depth-1)) full_ff <= 1'b1;
+ else if (shiftq_only) full_ff <= 1'b0;
+
+ end
+end
+
+always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY ) begin
+ if (`PICO_RESET_SENSITIVITY2) begin
+ onefull_ff <= 1'b0;
+ end
+ else if (flush) begin
+ onefull_ff <= 1'b0;
+ end
+ else begin
+ if (addq_only) begin
+ if (mem_is_empty) begin
+ onefull_ff <= 1'b1;
+ end
+ else begin
+ onefull_ff <= 1'b0;
+ end
+ end
+ else if (shiftq_only) begin
+ if (onefull_ff) begin
+ onefull_ff <= 1'b0;
+ end
+ else if (count_ff == 2'b10) begin
+ onefull_ff <= 1'b1;
+ end
+ end
+ end
+end
+
+always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY ) begin
+ if (`PICO_RESET_SENSITIVITY2) begin
+ read_addr_ff <= {awidth{1'b0}};
+ next_read_addr_ff <= {awidth{1'b0}};
+ end
+ else if (flush) begin
+ read_addr_ff <= {awidth{1'b0}};
+ next_read_addr_ff <= {awidth{1'b0}};
+ end
+ else begin
+
+ if ( (shiftq & not_empty_ff) | ~init_ff ) begin
+ read_addr_ff <= next_read_addr_ff;
+ if (next_read_addr_ff == depth-1) begin
+ next_read_addr_ff <= {awidth{1'b0}};
+ end
+ else begin
+ next_read_addr_ff <= next_read_addr_ff + 1'b1;
+ end
+ end
+ end
+end
+
+always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY ) begin
+ if (`PICO_RESET_SENSITIVITY2) begin
+ write_addr_ff <= {awidth{1'b0}};
+ end
+ else if (flush) begin
+ write_addr_ff <= {awidth{1'b0}};
+ end
+ else begin
+ if (wreq) begin
+ if (write_addr_ff == depth-1)
+ write_addr_ff <= {awidth{1'b0}};
+ else
+ write_addr_ff <= write_addr_ff + 1'b1;
+ end
+ end
+end
+
+always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY ) begin
+ if (`PICO_RESET_SENSITIVITY2) begin
+ count_ff <= {awidth{1'b0}};
+ end
+ else if (flush) begin
+ count_ff <= {awidth{1'b0}};
+ end
+ else begin
+ if (addq_only) begin
+ count_ff <= count_ff + 1'b1;
+ end
+ else if (shiftq_only) begin
+ count_ff <= count_ff - 1'b1;
+ end
+ end
+end
+
+ always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY) begin
+ if (`PICO_RESET_SENSITIVITY2)
+ begin
+ bypass_reg_valid_ff <= 1'b0;
+ bypass_reg_ff <= {(width){1'b0}};
+ end
+ else if (flush)
+ begin
+ bypass_reg_valid_ff <= 1'b0;
+ end
+ else
+ begin
+ bypass_reg_valid_ff <= addq & ( mem_is_empty | (shiftq & onefull_ff) );
+ bypass_reg_ff <= indata;
+ end
+ end
+ assign outdata = bypass_reg_valid_ff ? bypass_reg_ff[width-1:0] : bram_outdata[width-1:0];
+
+ wire [awidth-1:0] speculative_read_addr = (shiftq & not_empty_ff) ? next_read_addr_ff : read_addr_ff;
+
+ RA2SH #(.dwidth(width), .depth(depth), .awidth(awidth) ) fifo_storage(
+ .QA(),
+ .CLKA(clk),
+ .CENA(~wreq),
+ .WENA(1'b0),
+ .AA(write_addr_ff[awidth-1:0]),
+ .DA(indata[width-1:0]),
+ .QB(bram_outdata[width-1:0]),
+ .CLKB(clk),
+ .CENB(~rreq),
+ .WENB(1'b1),
+ .AB(speculative_read_addr),
+ .DB({width{1'b0}}));
+
+
+endmodule
Index: trunk/XILINX/BUILD_SCC_SRCH/SP6/SP6.tcl
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/SP6/SP6.tcl (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/SP6/SP6.tcl (revision 17)
@@ -0,0 +1,639 @@
+#
+# Project automation script for DE2
+#
+# Created for ISE version 13.4
+#
+# This file contains several Tcl procedures (procs) that you can use to automate
+# your project by running from xtclsh or the Project Navigator Tcl console.
+# If you load this file (using the Tcl command: source DE2.tcl), then you can
+# run any of the procs included here.
+#
+# This script is generated assuming your project has HDL sources.
+# Several of the defined procs won't apply to an EDIF or NGC based project.
+# If that is the case, simply remove them from this script.
+#
+# You may also edit any of these procs to customize them. See comments in each
+# proc for more instructions.
+#
+# This file contains the following procedures:
+#
+# Top Level procs (meant to be called directly by the user):
+# run_process: you can use this top-level procedure to run any processes
+# that you choose to by adding and removing comments, or by
+# adding new entries.
+# rebuild_project: you can alternatively use this top-level procedure
+# to recreate your entire project, and the run selected processes.
+#
+# Lower Level (helper) procs (called under in various cases by the top level procs):
+# show_help: print some basic information describing how this script works
+# add_source_files: adds the listed source files to your project.
+# set_project_props: sets the project properties that were in effect when this
+# script was generated.
+# create_libraries: creates and adds file to VHDL libraries that were defined when
+# this script was generated.
+# set_process_props: set the process properties as they were set for your project
+# when this script was generated.
+#
+
+set myProject "DE2"
+set myScript "DE2.tcl"
+
+#
+# Main (top-level) routines
+#
+# run_process
+# This procedure is used to run processes on an existing project. You may comment or
+# uncomment lines to control which processes are run. This routine is set up to run
+# the Implement Design and Generate Programming File processes by default. This proc
+# also sets process properties as specified in the "set_process_props" proc. Only
+# those properties which have values different from their current settings in the project
+# file will be modified in the project.
+#
+proc run_process {} {
+
+ global myScript
+ global myProject
+
+ ## put out a 'heartbeat' - so we know something's happening.
+ puts "\n$myScript: running ($myProject)...\n"
+
+ if { ! [ open_project ] } {
+ return false
+ }
+
+ set_process_props
+ #
+ # Remove the comment characters (#'s) to enable the following commands
+ # process run "Synthesize"
+ # process run "Translate"
+ # process run "Map"
+ # process run "Place & Route"
+ #
+ set task "Implement Design"
+ if { ! [run_task $task] } {
+ puts "$myScript: $task run failed, check run output for details."
+ project close
+ return
+ }
+
+ set task "Generate Programming File"
+ if { ! [run_task $task] } {
+ puts "$myScript: $task run failed, check run output for details."
+ project close
+ return
+ }
+
+ puts "Run completed (successfully)."
+ project close
+
+}
+
+#
+# rebuild_project
+#
+# This procedure renames the project file (if it exists) and recreates the project.
+# It then sets project properties and adds project sources as specified by the
+# set_project_props and add_source_files support procs. It recreates VHDL Libraries
+# as they existed at the time this script was generated.
+#
+# It then calls run_process to set process properties and run selected processes.
+#
+proc rebuild_project {} {
+
+ global myScript
+ global myProject
+
+ project close
+ ## put out a 'heartbeat' - so we know something's happening.
+ puts "\n$myScript: Rebuilding ($myProject)...\n"
+
+ set proj_exts [ list ise xise gise ]
+ foreach ext $proj_exts {
+ set proj_name "${myProject}.$ext"
+ if { [ file exists $proj_name ] } {
+ file delete $proj_name
+ }
+ }
+
+ project new $myProject
+ set_project_props
+ add_source_files
+ create_libraries
+ puts "$myScript: project rebuild completed."
+
+ run_process
+
+}
+
+#
+# Support Routines
+#
+
+#
+proc run_task { task } {
+
+ # helper proc for run_process
+
+ puts "Running '$task'"
+ set result [ process run "$task" ]
+ #
+ # check process status (and result)
+ set status [ process get $task status ]
+ if { ( ( $status != "up_to_date" ) && \
+ ( $status != "warnings" ) ) || \
+ ! $result } {
+ return false
+ }
+ return true
+}
+
+#
+# show_help: print information to help users understand the options available when
+# running this script.
+#
+proc show_help {} {
+
+ global myScript
+
+ puts ""
+ puts "usage: xtclsh $myScript "
+ puts " or you can run xtclsh and then enter 'source $myScript'."
+ puts ""
+ puts "options:"
+ puts " run_process - set properties and run processes."
+ puts " rebuild_project - rebuild the project from scratch and run processes."
+ puts " set_project_props - set project properties (device, speed, etc.)"
+ puts " add_source_files - add source files"
+ puts " create_libraries - create vhdl libraries"
+ puts " set_process_props - set process property values"
+ puts " show_help - print this message"
+ puts ""
+}
+
+proc open_project {} {
+
+ global myScript
+ global myProject
+
+ if { ! [ file exists ${myProject}.xise ] } {
+ ## project file isn't there, rebuild it.
+ puts "Project $myProject not found. Use project_rebuild to recreate it."
+ return false
+ }
+
+ project open $myProject
+
+ return true
+
+}
+#
+# set_project_props
+#
+# This procedure sets the project properties as they were set in the project
+# at the time this script was generated.
+#
+proc set_project_props {} {
+
+ global myScript
+
+ if { ! [ open_project ] } {
+ return false
+ }
+
+ puts "$myScript: Setting project properties..."
+
+ project set family "Spartan6"
+ project set device "xc6slx45t"
+ project set package "fgg484"
+ project set speed "-3"
+ project set top_level_module_type "HDL"
+ project set synthesis_tool "XST (VHDL/Verilog)"
+ project set simulator "ISim (VHDL/Verilog)"
+ project set "Preferred Language" "Verilog"
+ project set "Enable Message Filtering" "false"
+
+}
+
+
+#
+# add_source_files
+#
+# This procedure add the source files that were known to the project at the
+# time this script was generated.
+#
+proc add_source_files {} {
+
+ global myScript
+
+ if { ! [ open_project ] } {
+ return false
+ }
+
+ puts "$myScript: Adding sources to project..."
+
+ xfile add "../../../../../../SP6/AI.vhd"
+ xfile add "../../../../../../SP6/CMD_Decode_simple.v"
+ xfile add "../../../../../../SP6/DE2.v"
+ xfile add "../../../../../../SP6/LCD_Controller_safe.v"
+ xfile add "../../../../../../SP6/LCD_TEST_SAFE.v"
+ xfile add "../../../../../../SP6/RS232_Command.h"
+ xfile add "../../../../../../SP6/RS232_Controller.v"
+ xfile add "../../../../../../SP6/Reset_Delay.v"
+ xfile add "../../../../../../SP6/SEG7_LUT.v"
+ xfile add "../../../../../../SP6/SEG7_LUT_8.v"
+ xfile add "../../../../../../SP6/async_receiver_altera.v"
+ xfile add "../../../../../../SP6/async_transmitter_altera.v"
+ xfile add "../../../../../../SP6/bram_based_stream_buffer.v"
+ xfile add "../../../../../../SP6/safe_test.vhd"
+ xfile add "../../../../macrocells/RA1SH.v"
+ xfile add "../../../../macrocells/RA2SH.v"
+ xfile add "../../../../macrocells/SRAM_4.v"
+ xfile add "../../../../macrocells/addsubw.v"
+ xfile add "../../../../macrocells/addw.v"
+ xfile add "../../../../macrocells/andw.v"
+ xfile add "../../../../macrocells/brf.v"
+ xfile add "../../../../macrocells/cmpp_eq_1_4.v"
+ xfile add "../../../../macrocells/cmpp_eq_2_4.v"
+ xfile add "../../../../macrocells/cmpp_ineq_13_40.v"
+ xfile add "../../../../macrocells/cmpp_ineq_21_40.v"
+ xfile add "../../../../macrocells/cmpp_ineq_29_40.v"
+ xfile add "../../../../macrocells/cmpp_ineq_37_40.v"
+ xfile add "../../../../macrocells/cmpp_neq_1_4.v"
+ xfile add "../../../../macrocells/cmpp_neq_2_4.v"
+ xfile add "../../../../macrocells/cmpr_eq.v"
+ xfile add "../../../../macrocells/cmpr_ineq_3.v"
+ xfile add "../../../../macrocells/cmpr_ineq_4.v"
+ xfile add "../../../../macrocells/cmpr_ineq_5.v"
+ xfile add "../../../../macrocells/cmpr_ineq_7.v"
+ xfile add "../../../../macrocells/cmpr_ineq_8.v"
+ xfile add "../../../../macrocells/cmpr_ineq_9.v"
+ xfile add "../../../../macrocells/cmpr_neq.v"
+ xfile add "../../../../macrocells/combine12_wn.v"
+ xfile add "../../../../macrocells/combine26_wn.v"
+ xfile add "../../../../macrocells/combine2_wn.v"
+ xfile add "../../../../macrocells/combine32_wn.v"
+ xfile add "../../../../macrocells/combine3_wn.v"
+ xfile add "../../../../macrocells/counter.v"
+ xfile add "../../../../macrocells/decode.v"
+ xfile add "../../../../macrocells/delayn.v"
+ xfile add "../../../../macrocells/equal.v"
+ xfile add "../../../../macrocells/fifo.v"
+ xfile add "../../../../macrocells/ldlm_lx.v"
+ xfile add "../../../../macrocells/ldlmff_raw_lx.v"
+ xfile add "../../../../macrocells/ldstlm_lx.v"
+ xfile add "../../../../macrocells/ldstlmff_lx.v"
+ xfile add "../../../../macrocells/ldstr_sx.v"
+ xfile add "../../../../macrocells/lshiftw.v"
+ xfile add "../../../../macrocells/minmaxw_0.v"
+ xfile add "../../../../macrocells/minmaxw_1.v"
+ xfile add "../../../../macrocells/mpyw_1_stage.v"
+ xfile add "../../../../macrocells/mpyw_multi_stage.v"
+ xfile add "../../../../macrocells/orw.v"
+ xfile add "../../../../macrocells/rsflipflop_noinit.v"
+ xfile add "../../../../macrocells/select_11_1_wn.v"
+ xfile add "../../../../macrocells/select_12_1_wn.v"
+ xfile add "../../../../macrocells/select_17_1_wn.v"
+ xfile add "../../../../macrocells/select_1_1_wn.v"
+ xfile add "../../../../macrocells/select_2_1_wn.v"
+ xfile add "../../../../macrocells/select_3_1_wn.v"
+ xfile add "../../../../macrocells/select_4_1_wn.v"
+ xfile add "../../../../macrocells/select_5_1_wn.v"
+ xfile add "../../../../macrocells/select_6_1_wn.v"
+ xfile add "../../../../macrocells/select_7_1_wn.v"
+ xfile add "../../../../macrocells/select_8_1_wn.v"
+ xfile add "../../../../macrocells/select_9_1_wn.v"
+ xfile add "../../../../macrocells/sext.v"
+ xfile add "../../../../macrocells/shlkw.v"
+ xfile add "../../../../macrocells/shrkw.v"
+ xfile add "../../../../macrocells/sramff_raw_1.v"
+ xfile add "../../../../macrocells/sramff_raw_2.v"
+ xfile add "../../../../macrocells/sramff_raw_4.v"
+ xfile add "../../../../macrocells/sregn_noinit.v"
+ xfile add "../../../../macrocells/staller.v"
+ xfile add "../../../../macrocells/stlm_lx.v"
+ xfile add "../../../../macrocells/stlmff_raw_lx.v"
+ xfile add "../../../../macrocells/ststr_sx.v"
+ xfile add "../../../../macrocells/xorw.v"
+ xfile add "../../../../rtl/ai_adjacent_pa_0.v"
+ xfile add "../../../../rtl/ai_adjacent_paw_0.v"
+ xfile add "../../../../rtl/ai_adjacent_pe_0.v"
+ xfile add "../../../../rtl/ai_adjacent_tcab.v"
+ xfile add "../../../../rtl/ai_adjacent_tcab_assertions.v"
+ xfile add "../../../../rtl/ai_threats_pa_0.v"
+ xfile add "../../../../rtl/ai_threats_paw_0.v"
+ xfile add "../../../../rtl/ai_threats_pe_0.v"
+ xfile add "../../../../rtl/ai_threats_tcab.v"
+ xfile add "../../../../rtl/ai_threats_tcab_assertions.v"
+ xfile add "../../../../rtl/ai_threats_wide_ldstream0_0.v"
+ xfile add "../../../../rtl/ai_threats_wide_ststream0_0.v"
+ xfile add "../../../../rtl/connect6ai_synth_pa_0.v"
+ xfile add "../../../../rtl/connect6ai_synth_paw_0.v"
+ xfile add "../../../../rtl/connect6ai_synth_pe_0.v"
+ xfile add "../../../../rtl/connect6ai_synth_tcab.v"
+ xfile add "../../../../rtl/connect6ai_synth_tcab_assertions.v"
+ xfile add "../../../../rtl/threat_line_pa_0.v"
+ xfile add "../../../../rtl/threat_line_paw_0.v"
+ xfile add "../../../../rtl/threat_line_pe_0.v"
+ xfile add "../../../../rtl/threat_line_tcab.v"
+ xfile add "../../../../rtl/threat_line_tcab_assertions.v"
+ xfile add "../../../../rtl/threat_window_pa_0.v"
+ xfile add "../../../../rtl/threat_window_paw_0.v"
+ xfile add "../../../../rtl/threat_window_pe_0.v"
+ xfile add "../../../../rtl/threat_window_tcab.v"
+ xfile add "../../../../rtl/threat_window_tcab_assertions.v"
+
+ # Set the Top Module as well...
+ project set top "DE2"
+
+ puts "$myScript: project sources reloaded."
+
+} ; # end add_source_files
+
+#
+# create_libraries
+#
+# This procedure defines VHDL libraries and associates files with those libraries.
+# It is expected to be used when recreating the project. Any libraries defined
+# when this script was generated are recreated by this procedure.
+#
+proc create_libraries {} {
+
+ global myScript
+
+ if { ! [ open_project ] } {
+ return false
+ }
+
+ puts "$myScript: Creating libraries..."
+
+
+ # must close the project or library definitions aren't saved.
+ project save
+
+} ; # end create_libraries
+
+#
+# set_process_props
+#
+# This procedure sets properties as requested during script generation (either
+# all of the properties, or only those modified from their defaults).
+#
+proc set_process_props {} {
+
+ global myScript
+
+ if { ! [ open_project ] } {
+ return false
+ }
+
+ puts "$myScript: setting process properties..."
+
+ #project set "Compiled Library Directory" "\$XILINX//"
+ ##project set "Global Optimization" "Off" -process "Map"
+ #project set "Pack I/O Registers/Latches into IOBs" "Off" -process "Map"
+ #project set "Place And Route Mode" "Route Only" -process "Place & Route"
+ #project set "Regenerate Core" "Under Current Project Setting" -process "Regenerate Core"
+ #project set "Filter Files From Compile Order" "true"
+ #project set "Last Applied Goal" "Balanced"
+ #project set "Last Applied Strategy" "Xilinx Default (unlocked)"
+ #project set "Last Unlock Status" "false"
+ #project set "Manual Compile Order" "false"
+ #project set "Placer Effort Level" "High" -process "Map"
+ #project set "Extra Cost Tables" "0" -process "Map"
+ #project set "LUT Combining" "Off" -process "Map"
+ #project set "Combinatorial Logic Optimization" "false" -process "Map"
+ #project set "Starting Placer Cost Table (1-100)" "1" -process "Map"
+ #project set "Power Reduction" "Off" -process "Map"
+ #project set "Report Fastest Path(s) in Each Constraint" "true" -process "Generate Post-Place & Route Static Timing"
+ #project set "Generate Datasheet Section" "true" -process "Generate Post-Place & Route Static Timing"
+ #project set "Generate Timegroups Section" "false" -process "Generate Post-Place & Route Static Timing"
+ #project set "Report Fastest Path(s) in Each Constraint" "true" -process "Generate Post-Map Static Timing"
+ #project set "Generate Datasheet Section" "true" -process "Generate Post-Map Static Timing"
+ #project set "Generate Timegroups Section" "false" -process "Generate Post-Map Static Timing"
+ #project set "Project Description" ""
+ #project set "Property Specification in Project File" "Store all values"
+ #project set "Reduce Control Sets" "Auto" -process "Synthesize - XST"
+ #project set "Shift Register Minimum Size" "2" -process "Synthesize - XST"
+ #project set "Case Implementation Style" "None" -process "Synthesize - XST"
+ #project set "RAM Extraction" "true" -process "Synthesize - XST"
+ #project set "ROM Extraction" "true" -process "Synthesize - XST"
+ #project set "FSM Encoding Algorithm" "Auto" -process "Synthesize - XST"
+ #project set "Optimization Goal" "Speed" -process "Synthesize - XST"
+ #project set "Optimization Effort" "Normal" -process "Synthesize - XST"
+ #project set "Resource Sharing" "true" -process "Synthesize - XST"
+ #project set "Shift Register Extraction" "true" -process "Synthesize - XST"
+ #project set "User Browsed Strategy Files" "/opt/Xilinx/13.4/ISE_DS/ISE/data/default.xds"
+ #project set "VHDL Source Analysis Standard" "VHDL-93"
+ ##project set "Analysis Effort Level" "Standard" -process "Analyze Power Distribution (XPower Analyzer)"
+ ##project set "Analysis Effort Level" "Standard" -process "Generate Text Power Report"
+ #project set "Input TCL Command Script" "" -process "Generate Text Power Report"
+ #project set "Load Physical Constraints File" "Default" -process "Analyze Power Distribution (XPower Analyzer)"
+ #project set "Load Physical Constraints File" "Default" -process "Generate Text Power Report"
+ #project set "Load Simulation File" "Default" -process "Analyze Power Distribution (XPower Analyzer)"
+ #project set "Load Simulation File" "Default" -process "Generate Text Power Report"
+ #project set "Load Setting File" "" -process "Analyze Power Distribution (XPower Analyzer)"
+ #project set "Load Setting File" "" -process "Generate Text Power Report"
+ #project set "Setting Output File" "" -process "Generate Text Power Report"
+ #project set "Produce Verbose Report" "false" -process "Generate Text Power Report"
+ #project set "Other XPWR Command Line Options" "" -process "Generate Text Power Report"
+ ##project set "Essential Bits" "false" -process "Generate Programming File"
+ #project set "Other Bitgen Command Line Options" "" -process "Generate Programming File"
+ #project set "Maximum Signal Name Length" "20" -process "Generate IBIS Model"
+ #project set "Show All Models" "false" -process "Generate IBIS Model"
+ ##project set "VCCAUX Voltage Level" "2.5V" -process "Generate IBIS Model"
+ #project set "Disable Detailed Package Model Insertion" "false" -process "Generate IBIS Model"
+ #project set "Launch SDK after Export" "true" -process "Export Hardware Design To SDK with Bitstream"
+ #project set "Launch SDK after Export" "true" -process "Export Hardware Design To SDK without Bitstream"
+ #project set "Target UCF File Name" "" -process "Back-annotate Pin Locations"
+ #project set "Ignore User Timing Constraints" "false" -process "Map"
+ #project set "Register Ordering" "4" -process "Map"
+ #project set "Use RLOC Constraints" "Yes" -process "Map"
+ #project set "Other Map Command Line Options" "" -process "Map"
+ #project set "Use LOC Constraints" "true" -process "Translate"
+ #project set "Other Ngdbuild Command Line Options" "" -process "Translate"
+ #project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "Floorplan Area/IO/Logic (PlanAhead)"
+ #project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "I/O Pin Planning (PlanAhead) - Pre-Synthesis"
+ #project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "I/O Pin Planning (PlanAhead) - Post-Synthesis"
+ #project set "Ignore User Timing Constraints" "false" -process "Place & Route"
+ #project set "Other Place & Route Command Line Options" "" -process "Place & Route"
+ #project set "Use DSP Block" "Auto" -process "Synthesize - XST"
+ #project set "UserID Code (8 Digit Hexadecimal)" "0xFFFFFFFF" -process "Generate Programming File"
+ #project set "Configuration Pin Done" "Pull Up" -process "Generate Programming File"
+ ##project set "Enable External Master Clock" "false" -process "Generate Programming File"
+ #project set "Create ASCII Configuration File" "false" -process "Generate Programming File"
+ #project set "Create Bit File" "true" -process "Generate Programming File"
+ #project set "Enable BitStream Compression" "false" -process "Generate Programming File"
+ #project set "Run Design Rules Checker (DRC)" "true" -process "Generate Programming File"
+ #project set "Enable Cyclic Redundancy Checking (CRC)" "true" -process "Generate Programming File"
+ #project set "Create IEEE 1532 Configuration File" "false" -process "Generate Programming File"
+ #project set "Create ReadBack Data Files" "false" -process "Generate Programming File"
+ #project set "Configuration Pin Program" "Pull Up" -process "Generate Programming File"
+ #project set "Place MultiBoot Settings into Bitstream" "false" -process "Generate Programming File"
+ #project set "Configuration Rate" "2" -process "Generate Programming File"
+ #project set "Set SPI Configuration Bus Width" "1" -process "Generate Programming File"
+ #project set "JTAG Pin TCK" "Pull Up" -process "Generate Programming File"
+ #project set "JTAG Pin TDI" "Pull Up" -process "Generate Programming File"
+ #project set "JTAG Pin TDO" "Pull Up" -process "Generate Programming File"
+ #project set "JTAG Pin TMS" "Pull Up" -process "Generate Programming File"
+ #project set "Unused IOB Pins" "Pull Down" -process "Generate Programming File"
+ #project set "Watchdog Timer Value" "0xFFFF" -process "Generate Programming File"
+ #project set "Security" "Enable Readback and Reconfiguration" -process "Generate Programming File"
+ #project set "FPGA Start-Up Clock" "CCLK" -process "Generate Programming File"
+ #project set "Done (Output Events)" "Default (4)" -process "Generate Programming File"
+ #project set "Drive Done Pin High" "false" -process "Generate Programming File"
+ #project set "Enable Outputs (Output Events)" "Default (5)" -process "Generate Programming File"
+ #project set "Wait for DCM and PLL Lock (Output Events)" "Default (NoWait)" -process "Generate Programming File"
+ #project set "Release Write Enable (Output Events)" "Default (6)" -process "Generate Programming File"
+ #project set "Enable Internal Done Pipe" "false" -process "Generate Programming File"
+ #project set "Drive Awake Pin During Suspend/Wake Sequence" "false" -process "Generate Programming File"
+ #project set "Enable Suspend/Wake Global Set/Reset" "false" -process "Generate Programming File"
+ #project set "Enable Multi-Pin Wake-Up Suspend Mode" "false" -process "Generate Programming File"
+ #project set "GTS Cycle During Suspend/Wakeup Sequence" "4" -process "Generate Programming File"
+ #project set "GWE Cycle During Suspend/Wakeup Sequence" "5" -process "Generate Programming File"
+ #project set "Wakeup Clock" "Startup Clock" -process "Generate Programming File"
+ #project set "Allow Logic Optimization Across Hierarchy" "false" -process "Map"
+ #project set "Maximum Compression" "false" -process "Map"
+ #project set "Generate Detailed MAP Report" "false" -process "Map"
+ #project set "Map Slice Logic into Unused Block RAMs" "false" -process "Map"
+ #project set "Perform Timing-Driven Packing and Placement" "false"
+ #project set "Trim Unconnected Signals" "true" -process "Map"
+ #project set "Create I/O Pads from Ports" "false" -process "Translate"
+ #project set "Macro Search Path" "" -process "Translate"
+ #project set "Netlist Translation Type" "Timestamp" -process "Translate"
+ #project set "User Rules File for Netlister Launcher" "" -process "Translate"
+ #project set "Allow Unexpanded Blocks" "false" -process "Translate"
+ #project set "Allow Unmatched LOC Constraints" "false" -process "Translate"
+ #project set "Allow Unmatched Timing Group Constraints" "false" -process "Translate"
+ #project set "Perform Advanced Analysis" "false" -process "Generate Post-Place & Route Static Timing"
+ #project set "Report Paths by Endpoint" "3" -process "Generate Post-Place & Route Static Timing"
+ #project set "Report Type" "Verbose Report" -process "Generate Post-Place & Route Static Timing"
+ #project set "Number of Paths in Error/Verbose Report" "3" -process "Generate Post-Place & Route Static Timing"
+ #project set "Stamp Timing Model Filename" "" -process "Generate Post-Place & Route Static Timing"
+ #project set "Report Unconstrained Paths" "" -process "Generate Post-Place & Route Static Timing"
+ #project set "Perform Advanced Analysis" "false" -process "Generate Post-Map Static Timing"
+ #project set "Report Paths by Endpoint" "3" -process "Generate Post-Map Static Timing"
+ #project set "Report Type" "Verbose Report" -process "Generate Post-Map Static Timing"
+ #project set "Number of Paths in Error/Verbose Report" "3" -process "Generate Post-Map Static Timing"
+ #project set "Report Unconstrained Paths" "" -process "Generate Post-Map Static Timing"
+ #project set "Number of Clock Buffers" "16" -process "Synthesize - XST"
+ #project set "Add I/O Buffers" "true" -process "Synthesize - XST"
+ #project set "Global Optimization Goal" "AllClockNets" -process "Synthesize - XST"
+ #project set "Keep Hierarchy" "No" -process "Synthesize - XST"
+ #project set "Max Fanout" "100000" -process "Synthesize - XST"
+ #project set "Register Balancing" "No" -process "Synthesize - XST"
+ #project set "Register Duplication" "true" -process "Synthesize - XST"
+ #project set "Library for Verilog Sources" "" -process "Synthesize - XST"
+ #project set "Export Results to XPower Estimator" "" -process "Generate Text Power Report"
+ #project set "Asynchronous To Synchronous" "false" -process "Synthesize - XST"
+ #project set "Automatic BRAM Packing" "false" -process "Synthesize - XST"
+ #project set "BRAM Utilization Ratio" "100" -process "Synthesize - XST"
+ #project set "Bus Delimiter" "<>" -process "Synthesize - XST"
+ #project set "Case" "Maintain" -process "Synthesize - XST"
+ #project set "Cores Search Directories" "" -process "Synthesize - XST"
+ #project set "Cross Clock Analysis" "false" -process "Synthesize - XST"
+ #project set "DSP Utilization Ratio" "100" -process "Synthesize - XST"
+ #project set "Equivalent Register Removal" "true" -process "Synthesize - XST"
+ #project set "FSM Style" "LUT" -process "Synthesize - XST"
+ #project set "Generate RTL Schematic" "Yes" -process "Synthesize - XST"
+ #project set "Generics, Parameters" "" -process "Synthesize - XST"
+ #project set "Hierarchy Separator" "/" -process "Synthesize - XST"
+ #project set "HDL INI File" "" -process "Synthesize - XST"
+ #project set "LUT Combining" "Auto" -process "Synthesize - XST"
+ #project set "Library Search Order" "" -process "Synthesize - XST"
+ #project set "Netlist Hierarchy" "As Optimized" -process "Synthesize - XST"
+ #project set "Optimize Instantiated Primitives" "false" -process "Synthesize - XST"
+ #project set "Pack I/O Registers into IOBs" "Auto" -process "Synthesize - XST"
+ #project set "Power Reduction" "false" -process "Synthesize - XST"
+ #project set "Read Cores" "true" -process "Synthesize - XST"
+ #project set "Use Clock Enable" "Auto" -process "Synthesize - XST"
+ #project set "Use Synchronous Reset" "Auto" -process "Synthesize - XST"
+ #project set "Use Synchronous Set" "Auto" -process "Synthesize - XST"
+ #project set "Use Synthesis Constraints File" "true" -process "Synthesize - XST"
+ #project set "Verilog Include Directories" "" -process "Synthesize - XST"
+ #project set "Verilog Macros" "" -process "Synthesize - XST"
+ #project set "Work Directory" "/tmp/BUILD_SCC/imp_connect/rtl_package/synth/synplify_fpga/run_2012.05.04_15.04.58/DE2/xst" -process "Synthesize - XST"
+ #project set "Write Timing Constraints" "false" -process "Synthesize - XST"
+ #project set "Other XST Command Line Options" "" -process "Synthesize - XST"
+ #project set "Timing Mode" "Performance Evaluation" -process "Map"
+ #project set "Generate Asynchronous Delay Report" "false" -process "Place & Route"
+ #project set "Generate Clock Region Report" "false" -process "Place & Route"
+ #project set "Generate Post-Place & Route Power Report" "false" -process "Place & Route"
+ #project set "Generate Post-Place & Route Simulation Model" "false" -process "Place & Route"
+ #project set "Power Reduction" "false" -process "Place & Route"
+ #project set "Place & Route Effort Level (Overall)" "High" -process "Place & Route"
+ #project set "Auto Implementation Compile Order" "true"
+ #project set "Equivalent Register Removal" "true" -process "Map"
+ #project set "Placer Extra Effort" "None" -process "Map"
+ #project set "Power Activity File" "" -process "Map"
+ #project set "Register Duplication" "Off" -process "Map"
+ #project set "Generate Constraints Interaction Report" "false" -process "Generate Post-Map Static Timing"
+ #project set "Synthesis Constraints File" "" -process "Synthesize - XST"
+ #project set "RAM Style" "Auto" -process "Synthesize - XST"
+ #project set "Maximum Number of Lines in Report" "1000" -process "Generate Text Power Report"
+ #project set "MultiBoot: Insert IPROG CMD in the Bitfile" "Enable" -process "Generate Programming File"
+ #project set "Output File Name" "ai_adjacent_tcab" -process "Generate IBIS Model"
+ #project set "Timing Mode" "Performance Evaluation" -process "Place & Route"
+ #project set "Create Binary Configuration File" "false" -process "Generate Programming File"
+ #project set "Enable Debugging of Serial Mode BitStream" "false" -process "Generate Programming File"
+ #project set "Create Logic Allocation File" "false" -process "Generate Programming File"
+ #project set "Create Mask File" "false" -process "Generate Programming File"
+ #project set "Retry Configuration if CRC Error Occurs" "false" -process "Generate Programming File"
+ #project set "MultiBoot: Starting Address for Next Configuration" "0x00000000" -process "Generate Programming File"
+ #project set "MultiBoot: Starting Address for Golden Configuration" "0x00000000" -process "Generate Programming File"
+ #project set "MultiBoot: Use New Mode for Next Configuration" "true" -process "Generate Programming File"
+ #project set "MultiBoot: User-Defined Register for Failsafe Scheme" "0x0000" -process "Generate Programming File"
+ #project set "Setup External Master Clock Division" "1" -process "Generate Programming File"
+ #project set "Allow SelectMAP Pins to Persist" "false" -process "Generate Programming File"
+ #project set "Mask Pins for Multi-Pin Wake-Up Suspend Mode" "0x00" -process "Generate Programming File"
+ #project set "Enable Multi-Threading" "Off" -process "Map"
+ #project set "Generate Constraints Interaction Report" "false" -process "Generate Post-Place & Route Static Timing"
+ #project set "Move First Flip-Flop Stage" "true" -process "Synthesize - XST"
+ #project set "Move Last Flip-Flop Stage" "true" -process "Synthesize - XST"
+ #project set "ROM Style" "Auto" -process "Synthesize - XST"
+ #project set "Safe Implementation" "No" -process "Synthesize - XST"
+ #project set "Power Activity File" "" -process "Place & Route"
+ #project set "Extra Effort (Highest PAR level only)" "None" -process "Place & Route"
+ #project set "MultiBoot: Next Configuration Mode" "001" -process "Generate Programming File"
+ #project set "Encrypt Bitstream" "false" -process "Generate Programming File"
+ #project set "Enable Multi-Threading" "Off" -process "Place & Route"
+ #project set "AES Initial Vector" "" -process "Generate Programming File"
+ #project set "Encrypt Key Select" "BBRAM" -process "Generate Programming File"
+ #project set "AES Key (Hex String)" "" -process "Generate Programming File"
+ #project set "Input Encryption Key File" "" -process "Generate Programming File"
+ #project set "Functional Model Target Language" "Verilog" -process "View HDL Source"
+ #project set "Change Device Speed To" "-3" -process "Generate Post-Place & Route Static Timing"
+ #project set "Change Device Speed To" "-3" -process "Generate Post-Map Static Timing"
+
+ puts "$myScript: project property values set."
+
+} ; # end set_process_props
+
+proc main {} {
+
+ if { [llength $::argv] == 0 } {
+ show_help
+ return true
+ }
+
+ foreach option $::argv {
+ switch $option {
+ "show_help" { show_help }
+ "run_process" { run_process }
+ "rebuild_project" { rebuild_project }
+ "set_project_props" { set_project_props }
+ "add_source_files" { add_source_files }
+ "create_libraries" { create_libraries }
+ "set_process_props" { set_process_props }
+ default { puts "unrecognized option: $option"; show_help }
+ }
+ }
+}
+
+if { $tcl_interactive } {
+ show_help
+} else {
+ if {[catch {main} result]} {
+ puts "$myScript failed: $result."
+ }
+}
+
Index: trunk/XILINX/BUILD_SCC_SRCH/SP6/async_receiver_altera.v
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/SP6/async_receiver_altera.v (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/SP6/async_receiver_altera.v (revision 17)
@@ -0,0 +1,92 @@
+module async_receiver(clk, RxD, RxD_data_ready, RxD_data, RxD_endofpacket, RxD_idle);
+input clk, RxD;
+output RxD_data_ready; // onc clock pulse when RxD_data is valid
+output [7:0] RxD_data;
+
+//parameter ClkFrequency = 62500000; // 50MHz
+parameter ClkFrequency = 20000000; // 50MHz
+//parameter ClkFrequency = 27000000; // 27MHz
+parameter Baud = 115200;
+
+// We also detect if a gap occurs in the received stream of characters
+// That can be useful if multiple characters are sent in burst
+// so that multiple characters can be treated as a "packet"
+output RxD_endofpacket; // one clock pulse, when no more data is received (RxD_idle is going high)
+output RxD_idle; // no data is being received
+
+// Baud generator (we use 8 times oversampling)
+parameter Baud8 = Baud*8;
+parameter Baud8GeneratorAccWidth = 16;
+parameter Baud8GeneratorInc = ((Baud8<<(Baud8GeneratorAccWidth-7))+(ClkFrequency>>8))/(ClkFrequency>>7);
+reg [Baud8GeneratorAccWidth:0] Baud8GeneratorAcc;
+always @(posedge clk) Baud8GeneratorAcc <= Baud8GeneratorAcc[Baud8GeneratorAccWidth-1:0] + Baud8GeneratorInc;
+wire Baud8Tick = Baud8GeneratorAcc[Baud8GeneratorAccWidth];
+
+////////////////////////////
+reg [1:0] RxD_sync_inv;
+always @(posedge clk) if(Baud8Tick) RxD_sync_inv <= {RxD_sync_inv[0], ~RxD};
+// we invert RxD, so that the idle becomes "0", to prevent a phantom character to be received at startup
+
+reg [1:0] RxD_cnt_inv;
+reg RxD_bit_inv;
+
+always @(posedge clk)
+if(Baud8Tick)
+begin
+ if( RxD_sync_inv[1] && RxD_cnt_inv!=2'b11) RxD_cnt_inv <= RxD_cnt_inv + 1;
+ else
+ if(~RxD_sync_inv[1] && RxD_cnt_inv!=2'b00) RxD_cnt_inv <= RxD_cnt_inv - 1;
+
+ if(RxD_cnt_inv==2'b00) RxD_bit_inv <= 0;
+ else
+ if(RxD_cnt_inv==2'b11) RxD_bit_inv <= 1;
+end
+
+reg [3:0] state;
+reg [3:0] bit_spacing;
+
+// "next_bit" controls when the data sampling occurs
+// depending on how noisy the RxD is, different values might work better
+// with a clean connection, values from 8 to 11 work
+wire next_bit = (bit_spacing==10);
+
+always @(posedge clk)
+if(state==0)
+ bit_spacing <= 0;
+else
+if(Baud8Tick)
+ bit_spacing <= {bit_spacing[2:0] + 1} | {bit_spacing[3], 3'b000};
+
+always @(posedge clk)
+if(Baud8Tick)
+case(state)
+ 4'b0000: if(RxD_bit_inv) state <= 4'b1000; // start bit found?
+ 4'b1000: if(next_bit) state <= 4'b1001; // bit 0
+ 4'b1001: if(next_bit) state <= 4'b1010; // bit 1
+ 4'b1010: if(next_bit) state <= 4'b1011; // bit 2
+ 4'b1011: if(next_bit) state <= 4'b1100; // bit 3
+ 4'b1100: if(next_bit) state <= 4'b1101; // bit 4
+ 4'b1101: if(next_bit) state <= 4'b1110; // bit 5
+ 4'b1110: if(next_bit) state <= 4'b1111; // bit 6
+ 4'b1111: if(next_bit) state <= 4'b0001; // bit 7
+ 4'b0001: if(next_bit) state <= 4'b0000; // stop bit
+ default: state <= 4'b0000;
+endcase
+
+reg [7:0] RxD_data;
+always @(posedge clk)
+if(Baud8Tick && next_bit && state[3]) RxD_data <= {~RxD_bit_inv, RxD_data[7:1]};
+
+reg RxD_data_ready, RxD_data_error;
+always @(posedge clk)
+begin
+ RxD_data_ready <= (Baud8Tick && next_bit && state==4'b0001 && ~RxD_bit_inv); // ready only if the stop bit is received
+ RxD_data_error <= (Baud8Tick && next_bit && state==4'b0001 && RxD_bit_inv); // error if the stop bit is not received
+end
+
+reg [4:0] gap_count;
+always @(posedge clk) if (state!=0) gap_count<=0; else if(Baud8Tick & ~gap_count[4]) gap_count <= gap_count + 1;
+assign RxD_idle = gap_count[4];
+reg RxD_endofpacket; always @(posedge clk) RxD_endofpacket <= Baud8Tick & (gap_count==15);
+
+endmodule
trunk/XILINX/BUILD_SCC_SRCH/SP6/async_receiver_altera.v
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC_SRCH/SP6/SEG7_LUT.v
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/SP6/SEG7_LUT.v (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/SP6/SEG7_LUT.v (revision 17)
@@ -0,0 +1,28 @@
+module SEG7_LUT ( oSEG,iDIG );
+input [3:0] iDIG;
+output [6:0] oSEG;
+reg [6:0] oSEG;
+
+always @(iDIG)
+begin
+ case(iDIG)
+ 4'h1: oSEG = 7'b1111001; // ---t----
+ 4'h2: oSEG = 7'b0100100; // | |
+ 4'h3: oSEG = 7'b0110000; // lt rt
+ 4'h4: oSEG = 7'b0011001; // | |
+ 4'h5: oSEG = 7'b0010010; // ---m----
+ 4'h6: oSEG = 7'b0000010; // | |
+ 4'h7: oSEG = 7'b1111000; // lb rb
+ 4'h8: oSEG = 7'b0000000; // | |
+ 4'h9: oSEG = 7'b0011000; // ---b----
+ 4'ha: oSEG = 7'b0001000;
+ 4'hb: oSEG = 7'b0000011;
+ 4'hc: oSEG = 7'b1000110;
+ 4'hd: oSEG = 7'b0100001;
+ 4'he: oSEG = 7'b0000110;
+ 4'hf: oSEG = 7'b0001110;
+ 4'h0: oSEG = 7'b1000000;
+ endcase
+end
+
+endmodule
trunk/XILINX/BUILD_SCC_SRCH/SP6/SEG7_LUT.v
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC_SRCH/SP6/safe_test.vhd
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/SP6/safe_test.vhd (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/SP6/safe_test.vhd (revision 17)
@@ -0,0 +1,384 @@
+library ieee;
+use ieee.std_logic_1164.all;
+--use ieee.numeric_bit.all;
+use ieee.std_logic_arith.all;
+
+
+
+entity safe_test is
+generic(INPUT_LENGTH:integer:=6;OUTPUT_LENGTH:integer:=6);
+ port(
+ clk:in std_ulogic;
+ rst:in std_ulogic;
+ --Config Signals
+ init_out:out std_ulogic;
+ config_mode_out:out std_ulogic;
+ config_out0:out std_ulogic;
+ config_out1:out std_ulogic;
+ config_ack_in:in std_ulogic;
+ --DE2 Control SIgnals
+ msg_out:out std_ulogic_vector(2 downto 0);
+ Ack_count_out:out std_logic_vector(31 downto 0);
+ cmd:in std_ulogic_vector(4 downto 0);
+ --SRAM
+ SRAM_DATA_OUT: OUT std_logic_vector(15 downto 0);
+ SRAM_DATA: in std_logic_vector(15 downto 0);
+ SRAM_ADDR: out std_logic_vector(23 downto 0);
+ SRAM_WEN: out std_logic;
+ SRAM_OEN: out std_logic;
+ --SDRAM
+ SDRAM_DATA: out std_logic_vector(15 downto 0);
+ SDRAM_ADDR: out std_logic_vector(23 downto 0);
+ SDRAM_WEN: out std_logic;
+ SDRAM_OEN: out std_logic;
+ --Result Vectors
+ INPUT_ASYNC_0: in std_ulogic_vector(INPUT_LENGTH-1 downto 0);
+ INPUT_ASYNC_1: in std_ulogic_vector(INPUT_LENGTH-1 downto 0);
+ INPUT_ASYNC_ACKOUT: out std_ulogic_vector(INPUT_LENGTH-1 downto 0);
+ --Test Vectors
+ OUTPUT_ASYNC_0: out std_ulogic_vector(OUTPUT_LENGTH-1 downto 0);
+ OUTPUT_ASYNC_1: out std_ulogic_vector(OUTPUT_LENGTH-1 downto 0);
+ OUTPUT_ASYNC_ACKIN: in std_ulogic_vector(OUTPUT_LENGTH-1 downto 0);
+
+ --Trigger for oscilloscope
+ trigger: out std_ulogic
+
+ );
+end entity safe_test;
+
+
+architecture machine_a_etat of safe_test is
+component S_TO_AS_CONFIG is
+generic (BEGIN_ADDR:integer:=0;END_ADDR:integer:=0;LENGTH:integer:=16);
+ port(
+ clk:in std_ulogic;
+ rst:in std_ulogic;
+
+ SRAM_DATA_OUT: out std_logic_vector(15 downto 0);
+ SRAM_DATA: in std_logic_vector(15 downto 0);
+ SRAM_ADDR: out std_logic_vector(23 downto 0);
+ SRAM_WEN: out std_logic;
+ SRAM_OEN: out std_logic;
+
+ AS_OUT0: out std_ulogic;
+ AS_OUT1: out std_ulogic;
+ ACK_IN: in std_ulogic;
+
+ config_enable: in std_ulogic; -- Command from the state_machine up there
+ ACK_COUNT_OUT: out std_logic_vector(31 downto 0)
+ );
+end component S_TO_AS_CONFIG;
+
+component AS_TO_S_VECTOR is
+generic (BEGIN_ADDR:integer:=0;END_ADDR:integer:=0;LENGTH:integer:=16);
+ port(
+ clk:in std_ulogic;
+ rst:in std_ulogic;
+
+ SRAM_DATA: out std_logic_vector(15 downto 0);
+ SRAM_ADDR: out std_logic_vector(23 downto 0);
+ SRAM_WEN: out std_logic;
+ SRAM_OEN: out std_logic;
+
+ I_ASYNC_0: in std_ulogic_vector(LENGTH-1 downto 0);
+ I_ASYNC_1: in std_ulogic_vector(LENGTH-1 downto 0);
+ I_ASYNC_ACK_OUT: out std_ulogic_vector(LENGTH-1 downto 0);
+
+ vector_enable: in std_ulogic; -- Command from the state_machine up there
+ ACK_COUNT_OUT: out std_logic_vector(31 downto 0)
+ );
+end component AS_TO_S_VECTOR;
+
+component S_TO_AS_VECTOR is
+generic (BEGIN_ADDR:integer:=0;END_ADDR:integer:=0;LENGTH:integer:=16);
+ port(
+ clk:in std_ulogic;
+ rst:in std_ulogic;
+ trigger:out std_ulogic;
+
+ SRAM_DATA: in std_logic_vector(15 downto 0);
+ SRAM_ADDR: out std_logic_vector(23 downto 0);
+ SRAM_WEN: out std_logic;
+ SRAM_OEN: out std_logic;
+
+ O_ASYNC_0: out std_ulogic_vector(LENGTH-1 downto 0);
+ O_ASYNC_1: out std_ulogic_vector(LENGTH-1 downto 0);
+ O_ASYNC_ACK_IN: in std_ulogic_vector(LENGTH-1 downto 0);
+
+ vector_enable: in std_ulogic; -- Command from the state_machine up there
+ ACK_COUNT_OUT: out std_logic_vector(31 downto 0)
+ );
+end component S_TO_AS_VECTOR;
+
+--type STATE_TYPE is(IDLE,INIT,CONFIG,RUNNING);
+--signal state,next_state:STATE_TYPE;
+signal msg_out_int:std_ulogic_vector(2 downto 0);
+signal count:integer range 0 to integer'high;
+signal count_in,count_out:std_logic_vector(31 downto 0);
+signal config_enable,run_enable,safe_rst:std_ulogic;
+signal SRAM_DATA_TEST,SRAM_DATA_CONFIG:std_logic_vector(15 downto 0);
+signal SRAM_ADDR_TEST,SRAM_ADDR_CONFIG:std_logic_vector(23 downto 0);
+signal SRAM_WEN_CONFIG,SRAM_WEN_TEST,SRAM_OEN_CONFIG,SRAM_OEN_TEST:std_logic;
+signal trig_count:integer range 0 to integer'high;
+begin
+ msg_out<=msg_out_int;
+ TRANSLATE: S_TO_AS_CONFIG
+ generic map(BEGIN_ADDR=>0,END_ADDR=>293,LENGTH=>1)
+ port map(
+ clk=>clk,
+ rst=>rst,
+
+ SRAM_DATA_OUT=>SRAM_DATA_OUT,
+ SRAM_DATA=>SRAM_DATA,
+ SRAM_ADDR=>SRAM_ADDR_CONFIG,
+ SRAM_WEN=>SRAM_WEN_CONFIG,
+ SRAM_OEN=>SRAM_OEN_CONFIG,
+
+ AS_OUT0=>config_out0,
+ AS_OUT1=>config_out1,
+ ACK_IN=>config_ack_in,
+
+ config_enable=>config_enable,
+ ACK_COUNT_OUT=>Ack_count_out);
+
+
+ TRANSLATE_S_TO_AS:S_TO_AS_VECTOR
+ generic map(BEGIN_ADDR=>4096,END_ADDR=>4159,LENGTH=>OUTPUT_LENGTH)
+ port map(
+ clk=>clk,
+ rst=>safe_rst,
+ trigger=>trigger,
+
+ SRAM_DATA=>SRAM_DATA,
+ SRAM_ADDR=>SRAM_ADDR_TEST,
+ SRAM_WEN=>SRAM_WEN_TEST,
+ SRAM_OEN=>SRAM_OEN_TEST,
+
+ O_ASYNC_0=>OUTPUT_ASYNC_0,
+ O_ASYNC_1=>OUTPUT_ASYNC_1,
+ O_ASYNC_ACK_IN=>OUTPUT_ASYNC_ACKIN,
+
+ vector_enable=>run_enable,
+ ACK_COUNT_OUT=>count_out
+ );
+ TRANSLATE_AS_TO_S:AS_TO_S_VECTOR
+ generic map(BEGIN_ADDR=>0,END_ADDR=>63,LENGTH=>INPUT_LENGTH)
+ port map(
+ clk=>clk,
+ rst=>safe_rst,
+
+ SRAM_DATA=>SDRAM_DATA,
+ SRAM_ADDR=>SDRAM_ADDR,
+ SRAM_WEN=>SDRAM_WEN,
+ SRAM_OEN=>SDRAM_OEN,
+
+ I_ASYNC_0=>INPUT_ASYNC_0,
+ I_ASYNC_1=>INPUT_ASYNC_1,
+ I_ASYNC_ACK_OUT=>INPUT_ASYNC_ACKOUT,
+
+ vector_enable=>run_enable,
+ ACK_COUNT_OUT=>count_in
+ );
+ p1:process(cmd,SRAM_ADDR_CONFIG,SRAM_WEN_CONFIG,SRAM_OEN_CONFIG,SRAM_ADDR_TEST,SRAM_WEN_TEST,SRAM_OEN_TEST)
+ begin
+-- if(rst='0') then
+-- --state<=IDLE;
+-- msg_out_int<="111";
+-- init_out<='0';
+-- config_mode_out<='0';
+-- config_enable<='0';
+-- I_OL7_JP2_53<='0';
+-- elsif rising_edge(clk) then
+ -- state<=next_state;
+ case cmd is
+ when "00000"=>--IDLE
+ msg_out_int<="111";
+ init_out<='0';
+ config_mode_out<='0';
+ config_enable<='0';
+ run_enable<='0';
+ SRAM_ADDR<=SRAM_ADDR_CONFIG;
+ SRAM_WEN<=SRAM_WEN_CONFIG;
+ SRAM_OEN<=SRAM_OEN_CONFIG;
+ safe_rst<='0';
+
+ when "00001"=>--CONNECTED
+ msg_out_int<="000";
+ init_out<='0';
+ config_mode_out<='0';
+ config_enable<='0';
+ run_enable<='0';
+ SRAM_ADDR<=SRAM_ADDR_CONFIG;
+ SRAM_WEN<=SRAM_WEN_CONFIG;
+ SRAM_OEN<=SRAM_OEN_CONFIG;
+ safe_rst<='0';
+
+ when "00011"=>--INIT
+ msg_out_int<="001";
+ init_out<='0';
+ config_mode_out<='0';
+ config_enable<='0';
+ run_enable<='0';
+ SRAM_ADDR<=SRAM_ADDR_CONFIG;
+ SRAM_WEN<=SRAM_WEN_CONFIG;
+ SRAM_OEN<=SRAM_OEN_CONFIG;
+ safe_rst<='0';
+
+ when "00101"=>--CONFIG
+ msg_out_int<="010";
+ init_out<='1';
+ config_mode_out<='0';
+ config_enable<='1';
+ run_enable<='0';
+ SRAM_ADDR<=SRAM_ADDR_CONFIG;
+ SRAM_WEN<=SRAM_WEN_CONFIG;
+ SRAM_OEN<=SRAM_OEN_CONFIG;
+ safe_rst<='0';
+
+ when "10001"=>--SAFE_RESET,Only I/Os there is no reset for safe!!
+ msg_out_int<="011";
+ init_out<='1';
+ config_mode_out<='1';
+ config_enable<='1';
+ run_enable<='0';
+ SRAM_ADDR<=SRAM_ADDR_TEST;
+ SRAM_WEN<=SRAM_WEN_TEST;
+ SRAM_OEN<=SRAM_OEN_TEST;
+ safe_rst<='0';
+ when "01001"=>--RUNNING
+ msg_out_int<="011";
+ init_out<='1';
+ config_mode_out<='1';
+ config_enable<='1';
+ run_enable<='1';
+ SRAM_ADDR<=SRAM_ADDR_TEST;
+ SRAM_WEN<=SRAM_WEN_TEST;
+ SRAM_OEN<=SRAM_OEN_TEST;
+ safe_rst<='1';
+
+ when others=>
+ msg_out_int<= "111";
+ init_out<='1';
+ config_mode_out<='0';
+ config_enable<='0';
+ run_enable<='0';
+ SRAM_ADDR<=SRAM_ADDR_CONFIG;
+ SRAM_WEN<=SRAM_WEN_CONFIG;
+ SRAM_OEN<=SRAM_OEN_CONFIG;
+ safe_rst<='0';
+ end case;
+-- end if;
+ end process;
+
+-- p2:process(state,init_config,config_mode)
+-- begin
+-- case state is
+--
+-- when IDLE=>
+-- if(init_config='0') then
+-- next_state<=INIT;
+-- else
+-- next_state<=IDLE;
+-- end if;
+---- when CONNECT=>
+----
+---- if(init_config='0') then
+---- next_state<= INIT;
+---- else
+---- next_state<= CONNECT;
+---- end if;
+--
+-- when INIT=>
+-- if(config_mode='1') then
+-- next_state<=CONFIG;
+-- else
+-- next_state<=INIT;
+-- end if;
+--
+-- when CONFIG=>
+-- -- if(init_config='0') then
+-- -- next_state<=INIT;
+-- if(config_mode='0') then
+-- next_state<=RUNNING;
+-- elsif(config_mode='1') then
+-- next_state<=CONFIG;
+-- end if;
+--
+-- when RUNNING=>
+-- --if(init_config='0') then
+-- -- next_state<=INIT;
+-- if(config_mode='1') then
+-- next_state<=CONFIG;
+-- elsif(config_mode='0') then
+-- next_state<=RUNNING;
+-- end if;
+--
+-- when others=>
+-- next_state<=state;
+-- end case;
+-- end process;
+
+-- p3:process(state)
+-- begin
+-- case state is
+-- when IDLE=>
+-- msg_out_int<="111";
+-- init_out<='0';
+-- config_mode_out<='0';
+-- config_enable<='0';
+-- I_OL7_JP2_53<='0';
+--
+-- when CONNECT=>
+-- msg_out_int<="000";
+-- init_out<='0';
+-- config_mode_out<='0';
+-- config_enable<='0';
+-- I_OL7_JP2_53<='0';
+--
+-- when INIT=>
+-- msg_out_int<="001";
+-- init_out<='0';
+-- config_mode_out<='0';
+-- config_enable<='0';
+-- I_OL7_JP2_53<='0';
+--
+-- when CONFIG=>
+-- msg_out_int<="010";
+-- init_out<='1';
+-- config_mode_out<='0';
+-- config_enable<='1';
+-- I_OL7_JP2_53<='0';
+--
+-- when RUNNING=>
+-- msg_out_int<="011";
+-- init_out<='1';
+-- config_mode_out<='1';
+-- config_enable<='0';
+-- I_OL7_JP2_53<='1';
+--
+-- when others=>
+-- msg_out_int<= "111";
+-- init_out<='1';
+-- config_mode_out<='0';
+-- config_enable<='0';
+-- I_OL7_JP2_53<='0';
+-- end case;
+-- end process;
+-- --Main State Machine------------------------------------
+--p_trigger:process(clk,rst)
+-- begin
+-- if(rst='0') then
+-- trig_count<=0;
+-- trigger<='0';
+-- elsif rising_edge(clk) then
+-- trig_count<=trig_count+1;
+-- if(trig_count=1024) then
+-- trigger<='1';
+-- elsif(trig_count=2048) then
+-- trig_count<=0;
+-- trigger<='0';
+-- end if;
+-- end if;
+-- end process;
+--trigger<=clk;
+end architecture machine_a_etat;
Index: trunk/XILINX/BUILD_SCC_SRCH/SP6/SP6.do_synth
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/SP6/SP6.do_synth (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/SP6/SP6.do_synth (revision 17)
@@ -0,0 +1,53 @@
+#!/bin/sh
+
+run_logic_synthesis_only=0;
+while getopts ":s i" options; do
+ case $options in
+ i ) run_logic_synthesis_only=0;;
+ s ) run_logic_synthesis_only=1;;
+ ? ) echo $usage
+ exit 1;;
+ esac
+done
+
+export date_of_run=`date +%Y.%m.%d_%H.%M.%S`
+
+mkdir run_$date_of_run
+rm -f run
+ln -s run_$date_of_run run
+
+mkdir run/synthesis
+
+if [ $run_logic_synthesis_only -eq 1 ] ; then
+ touch run/synthesis/.LOGIC_SYNTHESIS_ONLY
+fi
+
+synplify_premier_dp -batch synplify.tcl
+if [[ $? != 0 ]]; then exit 1; fi
+
+if [ $run_logic_synthesis_only -ne 1 ] ; then
+
+ mkdir run/implementation
+ cd run/implementation
+ ngdbuild -uc ../../SP6.ucf -sd ../../../../coregen/ip_rtl/ -dd _ngo -nt timestamp -p xc6slx45t-fgg484-3 ../synthesis/DE2.edf DE2.ngd
+ if [[ $? != 0 ]]; then exit 1; fi
+ map -u -timing -p xc6slx45t-fgg484-3 -ol high -pr b -detail -o DE2_map.ncd DE2.ngd DE2.pcf
+ if [[ $? != 0 ]]; then exit 1; fi
+ par -ol high -w -nopad DE2_map.ncd DE2.ncd DE2.pcf
+ if [[ $? != 0 ]]; then exit 1; fi
+ trce -v 20 -u 64 -o DE2.twr DE2.ncd DE2.pcf
+ if [[ $? != 0 ]]; then exit 1; fi
+ bitgen -intstyle xflow -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:Yes -g DriveDone:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 DE2.ncd -g INIT_9K:yes
+ #if [[ $? != 0 ]]; then exit 1; fi
+ #setMode -bs
+ #setCable -port auto
+ #Identify -inferir
+ #identifyMPM
+ #assignFile -p 2 -file"/tmp/BUILD_SCC/imp_connect/rtl_package/synth/synplify_fpga/run/implementation/DE2.bit"
+ #Program -p 2
+
+ if [[ $? != 0 ]]; then exit 1; fi
+ cd -
+
+fi
+exit 0
trunk/XILINX/BUILD_SCC_SRCH/SP6/SP6.do_synth
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC_SRCH/SP6/RS232_Command.h
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/SP6/RS232_Command.h (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/SP6/RS232_Command.h (revision 17)
@@ -0,0 +1,27 @@
+////////////////// Command Action /////////////////////
+parameter SETUP = 8'h61;
+parameter ERASE = 8'h72;
+parameter WRITE = 8'h83;
+parameter READ = 8'h94;
+parameter LCD_DAT = 8'h83;
+parameter LCD_CMD = 8'h94;
+////////////////// Command Target /////////////////////
+parameter LED = 8'hF0;
+parameter SEG7 = 8'hE1;
+parameter PS2 = 8'hD2;
+parameter FLASH = 8'hC3;
+parameter SDRAM = 8'hB4;
+parameter SRAM = 8'hA5;
+parameter LCD = 8'h96;
+parameter VGA = 8'h87;
+parameter SDRSEL = 8'h1F;
+parameter FLSEL = 8'h2E;
+parameter EXTIO = 8'h3D;
+parameter SET_REG = 8'h4C;
+parameter SRSEL = 8'h5B;
+parameter SAFE = 8'h6A;
+////////////////// Command Mode /////////////////////
+parameter OUTSEL = 8'h33;
+parameter NORMAL = 8'hAA;
+parameter DISPLAY = 8'hCC;
+parameter BURST = 8'hFF;
trunk/XILINX/BUILD_SCC_SRCH/SP6/RS232_Command.h
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC_SRCH/SP6/DE2.qpf
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/SP6/DE2.qpf (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/SP6/DE2.qpf (revision 17)
@@ -0,0 +1,23 @@
+# Copyright (C) 1991-2005 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+
+
+QUARTUS_VERSION = "5.0"
+DATE = "11:08:53 August 22, 2005"
+
+
+# Revisions
+
+PROJECT_REVISION = "DE2"
trunk/XILINX/BUILD_SCC_SRCH/SP6/DE2.qpf
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC_SRCH/SP6/DE2_USB_API.pin
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/SP6/DE2_USB_API.pin (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/SP6/DE2_USB_API.pin (revision 17)
@@ -0,0 +1,742 @@
+ -- Copyright (C) 1991-2010 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions
+ -- and other software and tools, and its AMPP partner logic
+ -- functions, and any output files from any of the foregoing
+ -- (including device programming or simulation files), and any
+ -- associated documentation or information are expressly subject
+ -- to the terms and conditions of the Altera Program License
+ -- Subscription Agreement, Altera MegaCore Function License
+ -- Agreement, or other applicable license agreement, including,
+ -- without limitation, that your use is for the sole purpose of
+ -- programming logic devices manufactured by Altera and sold by
+ -- Altera or its authorized distributors. Please refer to the
+ -- applicable agreement for further details.
+ --
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC : No Connect. This pin has no internal connection to the device.
+ -- DNU : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
+ -- VCCIO : Dedicated power pin, which MUST be connected to VCC
+ -- of its bank.
+ -- Bank 1: 3.3V
+ -- Bank 2: 3.3V
+ -- Bank 3: 3.3V
+ -- Bank 4: 3.3V
+ -- Bank 5: 3.3V
+ -- Bank 6: 3.3V
+ -- Bank 7: 3.3V
+ -- Bank 8: 3.3V
+ -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ -- It can also be used to report unused dedicated pins. The connection
+ -- on the board for unused dedicated pins depends on whether this will
+ -- be used in a future design. One example is device migration. When
+ -- using device migration, refer to the device pin-tables. If it is a
+ -- GND pin in the pin table or if it will not be used in a future design
+ -- for another purpose the it MUST be connected to GND. If it is an unused
+ -- dedicated pin, then it can be connected to a valid signal on the board
+ -- (low, high, or toggling) if that signal is required for a different
+ -- revision of the design.
+ -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
+ -- This pin should be connected to GND. It may also be connected to a
+ -- valid signal on the board (low, high, or toggling) if that signal
+ -- is required for a different revision of the design.
+ -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
+ -- or leave it unconnected.
+ -- RESERVED : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II Version 10.0 Build 218 06/27/2010 SJ Full Version
+CHIP "DE2_USB_API" ASSIGNED TO AN: EP2C35F672C6
+
+Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND : A2 : gnd : : : :
+VCCIO3 : A3 : power : : 3.3V : 3 :
+RESERVED_INPUT : A4 : : : : 3 :
+RESERVED_INPUT : A5 : : : : 3 :
+RESERVED_INPUT : A6 : : : : 3 :
+RESERVED_INPUT : A7 : : : : 3 :
+RESERVED_INPUT : A8 : : : : 3 :
+RESERVED_INPUT : A9 : : : : 3 :
+RESERVED_INPUT : A10 : : : : 3 :
+VCCIO3 : A11 : power : : 3.3V : 3 :
+GND : A12 : gnd : : : :
+DPDT_SW[9] : A13 : input : 3.3-V LVTTL : : 4 : Y
+RESERVED_INPUT : A14 : : : : 4 :
+GND : A15 : gnd : : : :
+VCCIO4 : A16 : power : : 3.3V : 4 :
+RESERVED_INPUT : A17 : : : : 4 :
+RESERVED_INPUT : A18 : : : : 4 :
+RESERVED_INPUT : A19 : : : : 4 :
+RESERVED_INPUT : A20 : : : : 4 :
+RESERVED_INPUT : A21 : : : : 4 :
+RESERVED_INPUT : A22 : : : : 4 :
+RESERVED_INPUT : A23 : : : : 4 :
+VCCIO4 : A24 : power : : 3.3V : 4 :
+GND : A25 : gnd : : : :
+RESERVED_INPUT : AA1 : : : : 1 :
+RESERVED_INPUT : AA2 : : : : 1 :
+RESERVED_INPUT : AA3 : : : : 1 :
+RESERVED_INPUT : AA4 : : : : 1 :
+RESERVED_INPUT : AA5 : : : : 1 :
+RESERVED_INPUT : AA6 : : : : 1 :
+RESERVED_INPUT : AA7 : : : : 1 :
+VCCA_PLL1 : AA8 : power : : 1.2V : :
+RESERVED_INPUT : AA9 : : : : 8 :
+RESERVED_INPUT : AA10 : : : : 8 :
+RESERVED_INPUT : AA11 : : : : 8 :
+RESERVED_INPUT : AA12 : : : : 8 :
+LED_RED[10] : AA13 : output : 3.3-V LVTTL : : 7 : Y
+LED_RED[8] : AA14 : output : 3.3-V LVTTL : : 7 : Y
+RESERVED_INPUT : AA15 : : : : 7 :
+RESERVED_INPUT : AA16 : : : : 7 :
+RESERVED_INPUT : AA17 : : : : 7 :
+RESERVED_INPUT : AA18 : : : : 7 :
+VCCA_PLL4 : AA19 : power : : 1.2V : :
+LED_GREEN[6] : AA20 : output : 3.3-V LVTTL : : 7 : Y
+GND_PLL4 : AA21 : gnd : : : :
+VCCIO6 : AA22 : power : : 3.3V : 6 :
+HEX1[5] : AA23 : output : 3.3-V LVTTL : : 6 : Y
+HEX1[4] : AA24 : output : 3.3-V LVTTL : : 6 : Y
+HEX3[1] : AA25 : output : 3.3-V LVTTL : : 6 : Y
+HEX3[2] : AA26 : output : 3.3-V LVTTL : : 6 : Y
+RESERVED_INPUT : AB1 : : : : 1 :
+RESERVED_INPUT : AB2 : : : : 1 :
+RESERVED_INPUT : AB3 : : : : 1 :
+RESERVED_INPUT : AB4 : : : : 1 :
+VCCIO1 : AB5 : power : : 3.3V : 1 :
+VCCIO8 : AB6 : power : : 3.3V : 8 :
+GND : AB7 : gnd : : : :
+RESERVED_INPUT : AB8 : : : : 8 :
+VCCIO8 : AB9 : power : : 3.3V : 8 :
+RESERVED_INPUT : AB10 : : : : 8 :
+GND : AB11 : gnd : : : :
+HEX0[1] : AB12 : output : 3.3-V LVTTL : : 8 : Y
+VCCIO8 : AB13 : power : : 3.3V : 8 :
+VCCIO7 : AB14 : power : : 3.3V : 7 :
+RESERVED_INPUT : AB15 : : : : 7 :
+GND : AB16 : gnd : : : :
+VCCIO7 : AB17 : power : : 3.3V : 7 :
+RESERVED_INPUT : AB18 : : : : 7 :
+GND : AB19 : gnd : : : :
+RESERVED_INPUT : AB20 : : : : 7 :
+LED_RED[2] : AB21 : output : 3.3-V LVTTL : : 7 : Y
+VCCIO7 : AB22 : power : : 3.3V : 7 :
+HEX2[0] : AB23 : output : 3.3-V LVTTL : : 6 : Y
+HEX1[6] : AB24 : output : 3.3-V LVTTL : : 6 : Y
+HEX2[5] : AB25 : output : 3.3-V LVTTL : : 6 : Y
+HEX2[4] : AB26 : output : 3.3-V LVTTL : : 6 : Y
+RESERVED_INPUT : AC1 : : : : 1 :
+RESERVED_INPUT : AC2 : : : : 1 :
+RESERVED_INPUT : AC3 : : : : 1 :
+GND : AC4 : gnd : : : :
+RESERVED_INPUT : AC5 : : : : 8 :
+RESERVED_INPUT : AC6 : : : : 8 :
+RESERVED_INPUT : AC7 : : : : 8 :
+RESERVED_INPUT : AC8 : : : : 8 :
+RESERVED_INPUT : AC9 : : : : 8 :
+RESERVED_INPUT : AC10 : : : : 8 :
+RESERVED_INPUT : AC11 : : : : 8 :
+HEX0[2] : AC12 : output : 3.3-V LVTTL : : 8 : Y
+DPDT_SW[6] : AC13 : input : 3.3-V LVTTL : : 8 : Y
+LED_RED[11] : AC14 : output : 3.3-V LVTTL : : 7 : Y
+RESERVED_INPUT : AC15 : : : : 7 :
+RESERVED_INPUT : AC16 : : : : 7 :
+RESERVED_INPUT : AC17 : : : : 7 :
+RESERVED_INPUT : AC18 : : : : 7 :
+RESERVED_INPUT : AC19 : : : : 7 :
+RESERVED_INPUT : AC20 : : : : 7 :
+LED_RED[7] : AC21 : output : 3.3-V LVTTL : : 7 : Y
+LED_RED[3] : AC22 : output : 3.3-V LVTTL : : 7 : Y
+RESERVED_INPUT : AC23 : : : : 6 :
+NC : AC24 : : : : :
+HEX2[2] : AC25 : output : 3.3-V LVTTL : : 6 : Y
+HEX2[3] : AC26 : output : 3.3-V LVTTL : : 6 : Y
+VCCIO1 : AD1 : power : : 3.3V : 1 :
+RESERVED_INPUT : AD2 : : : : 1 :
+RESERVED_INPUT : AD3 : : : : 1 :
+RESERVED_INPUT : AD4 : : : : 8 :
+RESERVED_INPUT : AD5 : : : : 8 :
+RESERVED_INPUT : AD6 : : : : 8 :
+RESERVED_INPUT : AD7 : : : : 8 :
+RESERVED_INPUT : AD8 : : : : 8 :
+GND : AD9 : gnd : : : :
+RESERVED_INPUT : AD10 : : : : 8 :
+HEX0[3] : AD11 : output : 3.3-V LVTTL : : 8 : Y
+LED_RED[17] : AD12 : output : 3.3-V LVTTL : : 8 : Y
+DPDT_SW[5] : AD13 : input : 3.3-V LVTTL : : 8 : Y
+GND : AD14 : gnd : : : :
+LED_RED[12] : AD15 : output : 3.3-V LVTTL : : 7 : Y
+RESERVED_INPUT : AD16 : : : : 7 :
+RESERVED_INPUT : AD17 : : : : 7 :
+GND : AD18 : gnd : : : :
+RESERVED_INPUT : AD19 : : : : 7 :
+VCCIO7 : AD20 : power : : 3.3V : 7 :
+LED_RED[6] : AD21 : output : 3.3-V LVTTL : : 7 : Y
+LED_RED[4] : AD22 : output : 3.3-V LVTTL : : 7 : Y
+LED_RED[5] : AD23 : output : 3.3-V LVTTL : : 7 : Y
+RESERVED_INPUT : AD24 : : : : 6 :
+RESERVED_INPUT : AD25 : : : : 6 :
+VCCIO6 : AD26 : power : : 3.3V : 6 :
+GND : AE1 : gnd : : : :
+RESERVED_INPUT : AE2 : : : : 1 :
+RESERVED_INPUT : AE3 : : : : 1 :
+RESERVED_INPUT : AE4 : : : : 8 :
+RESERVED_INPUT : AE5 : : : : 8 :
+RESERVED_INPUT : AE6 : : : : 8 :
+RESERVED_INPUT : AE7 : : : : 8 :
+RESERVED_INPUT : AE8 : : : : 8 :
+RESERVED_INPUT : AE9 : : : : 8 :
+RESERVED_INPUT : AE10 : : : : 8 :
+HEX0[4] : AE11 : output : 3.3-V LVTTL : : 8 : Y
+LED_RED[16] : AE12 : output : 3.3-V LVTTL : : 8 : Y
+LED_RED[15] : AE13 : output : 3.3-V LVTTL : : 8 : Y
+DPDT_SW[3] : AE14 : input : 3.3-V LVTTL : : 7 : Y
+LED_RED[13] : AE15 : output : 3.3-V LVTTL : : 7 : Y
+RESERVED_INPUT : AE16 : : : : 7 :
+RESERVED_INPUT : AE17 : : : : 7 :
+RESERVED_INPUT : AE18 : : : : 7 :
+RESERVED_INPUT : AE19 : : : : 7 :
+RESERVED_INPUT : AE20 : : : : 7 :
+RESERVED_INPUT : AE21 : : : : 7 :
+LED_GREEN[0] : AE22 : output : 3.3-V LVTTL : : 7 : Y
+LED_RED[0] : AE23 : output : 3.3-V LVTTL : : 7 : Y
+RESERVED_INPUT : AE24 : : : : 6 :
+RESERVED_INPUT : AE25 : : : : 6 :
+GND : AE26 : gnd : : : :
+GND : AF2 : gnd : : : :
+VCCIO8 : AF3 : power : : 3.3V : 8 :
+RESERVED_INPUT : AF4 : : : : 8 :
+RESERVED_INPUT : AF5 : : : : 8 :
+RESERVED_INPUT : AF6 : : : : 8 :
+RESERVED_INPUT : AF7 : : : : 8 :
+RESERVED_INPUT : AF8 : : : : 8 :
+RESERVED_INPUT : AF9 : : : : 8 :
+HEX0[0] : AF10 : output : 3.3-V LVTTL : : 8 : Y
+VCCIO8 : AF11 : power : : 3.3V : 8 :
+GND : AF12 : gnd : : : :
+LED_RED[14] : AF13 : output : 3.3-V LVTTL : : 8 : Y
+DPDT_SW[4] : AF14 : input : 3.3-V LVTTL : : 7 : Y
+GND : AF15 : gnd : : : :
+VCCIO7 : AF16 : power : : 3.3V : 7 :
+RESERVED_INPUT : AF17 : : : : 7 :
+RESERVED_INPUT : AF18 : : : : 7 :
+RESERVED_INPUT : AF19 : : : : 7 :
+RESERVED_INPUT : AF20 : : : : 7 :
+RESERVED_INPUT : AF21 : : : : 7 :
+LED_GREEN[1] : AF22 : output : 3.3-V LVTTL : : 7 : Y
+LED_RED[1] : AF23 : output : 3.3-V LVTTL : : 7 : Y
+VCCIO7 : AF24 : power : : 3.3V : 7 :
+GND : AF25 : gnd : : : :
+GND : B1 : gnd : : : :
+RESERVED_INPUT : B2 : : : : 2 :
+RESERVED_INPUT : B3 : : : : 2 :
+RESERVED_INPUT : B4 : : : : 3 :
+RESERVED_INPUT : B5 : : : : 3 :
+RESERVED_INPUT : B6 : : : : 3 :
+RESERVED_INPUT : B7 : : : : 3 :
+RESERVED_INPUT : B8 : : : : 3 :
+RESERVED_INPUT : B9 : : : : 3 :
+RESERVED_INPUT : B10 : : : : 3 :
+RESERVED_INPUT : B11 : : : : 3 :
+RESERVED_INPUT : B12 : : : : 3 :
+DPDT_SW[8] : B13 : input : 3.3-V LVTTL : : 4 : Y
+RESERVED_INPUT : B14 : : : : 4 :
+RESERVED_INPUT : B15 : : : : 4 :
+RESERVED_INPUT : B16 : : : : 4 :
+RESERVED_INPUT : B17 : : : : 4 :
+RESERVED_INPUT : B18 : : : : 4 :
+RESERVED_INPUT : B19 : : : : 4 :
+RESERVED_INPUT : B20 : : : : 4 :
+RESERVED_INPUT : B21 : : : : 4 :
+RESERVED_INPUT : B22 : : : : 4 :
+RESERVED_INPUT : B23 : : : : 4 :
+RESERVED_INPUT : B24 : : : : 5 :
+UART_TXD : B25 : output : 3.3-V LVTTL : : 5 : Y
+GND : B26 : gnd : : : :
+VCCIO2 : C1 : power : : 3.3V : 2 :
+RESERVED_INPUT : C2 : : : : 2 :
+RESERVED_INPUT : C3 : : : : 2 :
+RESERVED_INPUT : C4 : : : : 3 :
+RESERVED_INPUT : C5 : : : : 3 :
+RESERVED_INPUT : C6 : : : : 3 :
+RESERVED_INPUT : C7 : : : : 3 :
+RESERVED_INPUT : C8 : : : : 3 :
+RESERVED_INPUT : C9 : : : : 3 :
+RESERVED_INPUT : C10 : : : : 3 :
+RESERVED_INPUT : C11 : : : : 3 :
+RESERVED_INPUT : C12 : : : : 3 :
+DPDT_SW[7] : C13 : input : 3.3-V LVTTL : : 3 : Y
+GND : C14 : gnd : : : :
+RESERVED_INPUT : C15 : : : : 4 :
+RESERVED_INPUT : C16 : : : : 4 :
+RESERVED_INPUT : C17 : : : : 4 :
+GND : C18 : gnd : : : :
+RESERVED_INPUT : C19 : : : : 4 :
+VCCIO4 : C20 : power : : 3.3V : 4 :
+RESERVED_INPUT : C21 : : : : 4 :
+RESERVED_INPUT : C22 : : : : 4 :
+RESERVED_INPUT : C23 : : : : 4 :
+RESERVED_INPUT : C24 : : : : 5 :
+UART_RXD : C25 : input : 3.3-V LVTTL : : 5 : Y
+VCCIO5 : C26 : power : : 3.3V : 5 :
+RESERVED_INPUT : D1 : : : : 2 :
+RESERVED_INPUT : D2 : : : : 2 :
+~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : input : 3.3-V LVTTL : : 2 : N
+GND : D4 : gnd : : : :
+RESERVED_INPUT : D5 : : : : 3 :
+RESERVED_INPUT : D6 : : : : 3 :
+RESERVED_INPUT : D7 : : : : 3 :
+RESERVED_INPUT : D8 : : : : 3 :
+RESERVED_INPUT : D9 : : : : 3 :
+RESERVED_INPUT : D10 : : : : 3 :
+RESERVED_INPUT : D11 : : : : 3 :
+RESERVED_INPUT : D12 : : : : 3 :
+OSC_27 : D13 : input : 3.3-V LVTTL : : 3 : Y
+RESERVED_INPUT : D14 : : : : 4 :
+RESERVED_INPUT : D15 : : : : 4 :
+RESERVED_INPUT : D16 : : : : 4 :
+RESERVED_INPUT : D17 : : : : 4 :
+RESERVED_INPUT : D18 : : : : 4 :
+RESERVED_INPUT : D19 : : : : 4 :
+RESERVED_INPUT : D20 : : : : 4 :
+RESERVED_INPUT : D21 : : : : 4 :
+VCCIO4 : D22 : power : : 3.3V : 4 :
+RESERVED_INPUT : D23 : : : : 5 :
+GND : D24 : gnd : : : :
+RESERVED_INPUT : D25 : : : : 5 :
+RESERVED_INPUT : D26 : : : : 5 :
+RESERVED_INPUT : E1 : : : : 2 :
+RESERVED_INPUT : E2 : : : : 2 :
+~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : input : 3.3-V LVTTL : : 2 : N
+GND_PLL3 : E4 : gnd : : : :
+RESERVED_INPUT : E5 : : : : 2 :
+VCCIO3 : E6 : power : : 3.3V : 3 :
+GND : E7 : gnd : : : :
+RESERVED_INPUT : E8 : : : : 3 :
+VCCIO3 : E9 : power : : 3.3V : 3 :
+RESERVED_INPUT : E10 : : : : 3 :
+GND : E11 : gnd : : : :
+RESERVED_INPUT : E12 : : : : 3 :
+VCCIO3 : E13 : power : : 3.3V : 3 :
+VCCIO4 : E14 : power : : 3.3V : 4 :
+RESERVED_INPUT : E15 : : : : 4 :
+GND : E16 : gnd : : : :
+VCCIO4 : E17 : power : : 3.3V : 4 :
+RESERVED_INPUT : E18 : : : : 4 :
+GND : E19 : gnd : : : :
+RESERVED_INPUT : E20 : : : : 4 :
+GND_PLL2 : E21 : gnd : : : :
+RESERVED_INPUT : E22 : : : : 5 :
+RESERVED_INPUT : E23 : : : : 5 :
+RESERVED_INPUT : E24 : : : : 5 :
+RESERVED_INPUT : E25 : : : : 5 :
+RESERVED_INPUT : E26 : : : : 5 :
+RESERVED_INPUT : F1 : : : : 2 :
+RESERVED_INPUT : F2 : : : : 2 :
+RESERVED_INPUT : F3 : : : : 2 :
+RESERVED_INPUT : F4 : : : : 2 :
+VCCIO2 : F5 : power : : 3.3V : 2 :
+RESERVED_INPUT : F6 : : : : 2 :
+RESERVED_INPUT : F7 : : : : 2 :
+GNDA_PLL3 : F8 : gnd : : : :
+RESERVED_INPUT : F9 : : : : 3 :
+RESERVED_INPUT : F10 : : : : 3 :
+RESERVED_INPUT : F11 : : : : 3 :
+RESERVED_INPUT : F12 : : : : 3 :
+RESERVED_INPUT : F13 : : : : 4 :
+RESERVED_INPUT : F14 : : : : 4 :
+RESERVED_INPUT : F15 : : : : 4 :
+RESERVED_INPUT : F16 : : : : 4 :
+RESERVED_INPUT : F17 : : : : 4 :
+RESERVED_INPUT : F18 : : : : 4 :
+GNDA_PLL2 : F19 : gnd : : : :
+RESERVED_INPUT : F20 : : : : 5 :
+RESERVED_INPUT : F21 : : : : 5 :
+VCCIO5 : F22 : power : : 3.3V : 5 :
+RESERVED_INPUT : F23 : : : : 5 :
+RESERVED_INPUT : F24 : : : : 5 :
+RESERVED_INPUT : F25 : : : : 5 :
+RESERVED_INPUT : F26 : : : : 5 :
+RESERVED_INPUT : G1 : : : : 2 :
+RESERVED_INPUT : G2 : : : : 2 :
+RESERVED_INPUT : G3 : : : : 2 :
+RESERVED_INPUT : G4 : : : : 2 :
+RESERVED_INPUT : G5 : : : : 2 :
+RESERVED_INPUT : G6 : : : : 2 :
+GND_PLL3 : G7 : gnd : : : :
+VCCA_PLL3 : G8 : power : : 1.2V : :
+RESERVED_INPUT : G9 : : : : 3 :
+RESERVED_INPUT : G10 : : : : 3 :
+RESERVED_INPUT : G11 : : : : 3 :
+RESERVED_INPUT : G12 : : : : 3 :
+RESERVED_INPUT : G13 : : : : 4 :
+RESERVED_INPUT : G14 : : : : 4 :
+RESERVED_INPUT : G15 : : : : 4 :
+RESERVED_INPUT : G16 : : : : 4 :
+RESERVED_INPUT : G17 : : : : 4 :
+RESERVED_INPUT : G18 : : : : 4 :
+VCCA_PLL2 : G19 : power : : 1.2V : :
+GND_PLL2 : G20 : gnd : : : :
+RESERVED_INPUT : G21 : : : : 5 :
+RESERVED_INPUT : G22 : : : : 5 :
+RESERVED_INPUT : G23 : : : : 5 :
+RESERVED_INPUT : G24 : : : : 5 :
+RESERVED_INPUT : G25 : : : : 5 :
+KEY[0] : G26 : input : 3.3-V LVTTL : : 5 : Y
+RESERVED_INPUT : H1 : : : : 2 :
+RESERVED_INPUT : H2 : : : : 2 :
+RESERVED_INPUT : H3 : : : : 2 :
+RESERVED_INPUT : H4 : : : : 2 :
+GND : H5 : gnd : : : :
+RESERVED_INPUT : H6 : : : : 2 :
+VCCD_PLL3 : H7 : power : : 1.2V : :
+RESERVED_INPUT : H8 : : : : 3 :
+VCCIO3 : H9 : power : : 3.3V : 3 :
+RESERVED_INPUT : H10 : : : : 3 :
+RESERVED_INPUT : H11 : : : : 3 :
+RESERVED_INPUT : H12 : : : : 3 :
+GND : H13 : gnd : : : :
+GND : H14 : gnd : : : :
+RESERVED_INPUT : H15 : : : : 4 :
+RESERVED_INPUT : H16 : : : : 4 :
+RESERVED_INPUT : H17 : : : : 4 :
+VCCIO4 : H18 : power : : 3.3V : 4 :
+RESERVED_INPUT : H19 : : : : 5 :
+VCCD_PLL2 : H20 : power : : 1.2V : :
+RESERVED_INPUT : H21 : : : : 5 :
+GND : H22 : gnd : : : :
+RESERVED_INPUT : H23 : : : : 5 :
+RESERVED_INPUT : H24 : : : : 5 :
+RESERVED_INPUT : H25 : : : : 5 :
+RESERVED_INPUT : H26 : : : : 5 :
+RESERVED_INPUT : J1 : : : : 2 :
+RESERVED_INPUT : J2 : : : : 2 :
+RESERVED_INPUT : J3 : : : : 2 :
+RESERVED_INPUT : J4 : : : : 2 :
+RESERVED_INPUT : J5 : : : : 2 :
+RESERVED_INPUT : J6 : : : : 2 :
+RESERVED_INPUT : J7 : : : : 2 :
+RESERVED_INPUT : J8 : : : : 2 :
+RESERVED_INPUT : J9 : : : : 3 :
+RESERVED_INPUT : J10 : : : : 3 :
+RESERVED_INPUT : J11 : : : : 3 :
+VCCIO3 : J12 : power : : 3.3V : 3 :
+RESERVED_INPUT : J13 : : : : 3 :
+RESERVED_INPUT : J14 : : : : 3 :
+VCCIO4 : J15 : power : : 3.3V : 4 :
+RESERVED_INPUT : J16 : : : : 4 :
+RESERVED_INPUT : J17 : : : : 4 :
+RESERVED_INPUT : J18 : : : : 4 :
+VCCIO5 : J19 : power : : 3.3V : 5 :
+RESERVED_INPUT : J20 : : : : 5 :
+RESERVED_INPUT : J21 : : : : 5 :
+RESERVED_INPUT : J22 : : : : 5 :
+RESERVED_INPUT : J23 : : : : 5 :
+RESERVED_INPUT : J24 : : : : 5 :
+RESERVED_INPUT : J25 : : : : 5 :
+RESERVED_INPUT : J26 : : : : 5 :
+RESERVED_INPUT : K1 : : : : 2 :
+RESERVED_INPUT : K2 : : : : 2 :
+RESERVED_INPUT : K3 : : : : 2 :
+RESERVED_INPUT : K4 : : : : 2 :
+RESERVED_INPUT : K5 : : : : 2 :
+RESERVED_INPUT : K6 : : : : 2 :
+RESERVED_INPUT : K7 : : : : 2 :
+RESERVED_INPUT : K8 : : : : 2 :
+RESERVED_INPUT : K9 : : : : 3 :
+VCCINT : K10 : power : : 1.2V : :
+VCCINT : K11 : power : : 1.2V : :
+VCCINT : K12 : power : : 1.2V : :
+VCCINT : K13 : power : : 1.2V : :
+VCCINT : K14 : power : : 1.2V : :
+VCCINT : K15 : power : : 1.2V : :
+RESERVED_INPUT : K16 : : : : 4 :
+RESERVED_INPUT : K17 : : : : 4 :
+RESERVED_INPUT : K18 : : : : 5 :
+RESERVED_INPUT : K19 : : : : 5 :
+GND : K20 : gnd : : : :
+RESERVED_INPUT : K21 : : : : 5 :
+RESERVED_INPUT : K22 : : : : 5 :
+RESERVED_INPUT : K23 : : : : 5 :
+RESERVED_INPUT : K24 : : : : 5 :
+RESERVED_INPUT : K25 : : : : 5 :
+RESERVED_INPUT : K26 : : : : 5 :
+VCCIO2 : L1 : power : : 3.3V : 2 :
+HEX7[1] : L2 : output : 3.3-V LVTTL : : 2 : Y
+HEX7[0] : L3 : output : 3.3-V LVTTL : : 2 : Y
+RESERVED_INPUT : L4 : : : : 2 :
+GND : L5 : gnd : : : :
+HEX7[3] : L6 : output : 3.3-V LVTTL : : 2 : Y
+HEX7[4] : L7 : output : 3.3-V LVTTL : : 2 : Y
+TMS : L8 : input : : : 2 :
+HEX7[2] : L9 : output : 3.3-V LVTTL : : 2 : Y
+RESERVED_INPUT : L10 : : : : 2 :
+VCCINT : L11 : power : : 1.2V : :
+GND : L12 : gnd : : : :
+GND : L13 : gnd : : : :
+GND : L14 : gnd : : : :
+GND : L15 : gnd : : : :
+VCCINT : L16 : power : : 1.2V : :
+VCCINT : L17 : power : : 1.2V : :
+VCCINT : L18 : power : : 1.2V : :
+RESERVED_INPUT : L19 : : : : 5 :
+RESERVED_INPUT : L20 : : : : 5 :
+RESERVED_INPUT : L21 : : : : 5 :
+GND : L22 : gnd : : : :
+RESERVED_INPUT : L23 : : : : 5 :
+RESERVED_INPUT : L24 : : : : 5 :
+RESERVED_INPUT : L25 : : : : 5 :
+VCCIO5 : L26 : power : : 3.3V : 5 :
+GND : M1 : gnd : : : :
+HEX6[3] : M2 : output : 3.3-V LVTTL : : 2 : Y
+HEX6[4] : M3 : output : 3.3-V LVTTL : : 2 : Y
+HEX6[6] : M4 : output : 3.3-V LVTTL : : 2 : Y
+HEX6[5] : M5 : output : 3.3-V LVTTL : : 2 : Y
+TCK : M6 : input : : : 2 :
+TDO : M7 : output : : : 2 :
+TDI : M8 : input : : : 2 :
+VCCIO2 : M9 : power : : 3.3V : 2 :
+VCCINT : M10 : power : : 1.2V : :
+VCCINT : M11 : power : : 1.2V : :
+GND : M12 : gnd : : : :
+GND : M13 : gnd : : : :
+GND : M14 : gnd : : : :
+GND : M15 : gnd : : : :
+VCCINT : M16 : power : : 1.2V : :
+VCCINT : M17 : power : : 1.2V : :
+VCCIO5 : M18 : power : : 3.3V : 5 :
+RESERVED_INPUT : M19 : : : : 5 :
+RESERVED_INPUT : M20 : : : : 5 :
+RESERVED_INPUT : M21 : : : : 5 :
+RESERVED_INPUT : M22 : : : : 5 :
+RESERVED_INPUT : M23 : : : : 5 :
+RESERVED_INPUT : M24 : : : : 5 :
+RESERVED_INPUT : M25 : : : : 5 :
+GND : M26 : gnd : : : :
+DPDT_SW[10] : N1 : input : 3.3-V LVTTL : : 2 : Y
+OSC_50 : N2 : input : 3.3-V LVTTL : : 2 : Y
+DATA0 : N3 : input : : : 2 :
+nCE : N4 : : : : 2 :
+VCCIO2 : N5 : power : : 3.3V : 2 :
+DCLK : N6 : : : : 2 :
+nCONFIG : N7 : : : : 2 :
+GND : N8 : gnd : : : :
+HEX7[6] : N9 : output : 3.3-V LVTTL : : 2 : Y
+VCCINT : N10 : power : : 1.2V : :
+GND : N11 : gnd : : : :
+GND : N12 : gnd : : : :
+GND : N13 : gnd : : : :
+GND : N14 : gnd : : : :
+GND : N15 : gnd : : : :
+GND : N16 : gnd : : : :
+VCCINT : N17 : power : : 1.2V : :
+RESERVED_INPUT : N18 : : : : 5 :
+GND : N19 : gnd : : : :
+RESERVED_INPUT : N20 : : : : 5 :
+NC : N21 : : : : :
+VCCIO5 : N22 : power : : 3.3V : 5 :
+KEY[1] : N23 : input : 3.3-V LVTTL : : 5 : Y
+RESERVED_INPUT : N24 : : : : 5 :
+DPDT_SW[0] : N25 : input : 3.3-V LVTTL : : 5 : Y
+DPDT_SW[1] : N26 : input : 3.3-V LVTTL : : 5 : Y
+DPDT_SW[11] : P1 : input : 3.3-V LVTTL : : 1 : Y
+DPDT_SW[12] : P2 : input : 3.3-V LVTTL : : 1 : Y
+HEX6[2] : P3 : output : 3.3-V LVTTL : : 1 : Y
+HEX6[1] : P4 : output : 3.3-V LVTTL : : 1 : Y
+VCCIO1 : P5 : power : : 3.3V : 1 :
+HEX5[1] : P6 : output : 3.3-V LVTTL : : 1 : Y
+HEX5[2] : P7 : output : 3.3-V LVTTL : : 1 : Y
+GND : P8 : gnd : : : :
+HEX7[5] : P9 : output : 3.3-V LVTTL : : 2 : Y
+VCCINT : P10 : power : : 1.2V : :
+GND : P11 : gnd : : : :
+GND : P12 : gnd : : : :
+GND : P13 : gnd : : : :
+GND : P14 : gnd : : : :
+GND : P15 : gnd : : : :
+GND : P16 : gnd : : : :
+RESERVED_INPUT : P17 : : : : 6 :
+RESERVED_INPUT : P18 : : : : 5 :
+GND : P19 : gnd : : : :
+MSEL0 : P20 : : : : 6 :
+MSEL1 : P21 : : : : 6 :
+VCCIO6 : P22 : power : : 3.3V : 6 :
+KEY[2] : P23 : input : 3.3-V LVTTL : : 6 : Y
+RESERVED_INPUT : P24 : : : : 6 :
+DPDT_SW[2] : P25 : input : 3.3-V LVTTL : : 6 : Y
+EXT_CLOCK : P26 : input : 3.3-V LVTTL : : 6 : Y
+GND : R1 : gnd : : : :
+HEX6[0] : R2 : output : 3.3-V LVTTL : : 1 : Y
+HEX5[6] : R3 : output : 3.3-V LVTTL : : 1 : Y
+HEX5[5] : R4 : output : 3.3-V LVTTL : : 1 : Y
+HEX5[4] : R5 : output : 3.3-V LVTTL : : 1 : Y
+HEX4[5] : R6 : output : 3.3-V LVTTL : : 1 : Y
+HEX4[4] : R7 : output : 3.3-V LVTTL : : 1 : Y
+RESERVED_INPUT : R8 : : : : 1 :
+VCCIO1 : R9 : power : : 3.3V : 1 :
+VCCINT : R10 : power : : 1.2V : :
+VCCINT : R11 : power : : 1.2V : :
+GND : R12 : gnd : : : :
+GND : R13 : gnd : : : :
+GND : R14 : gnd : : : :
+GND : R15 : gnd : : : :
+VCCINT : R16 : power : : 1.2V : :
+RESERVED_INPUT : R17 : : : : 6 :
+VCCIO6 : R18 : power : : 3.3V : 6 :
+RESERVED_INPUT : R19 : : : : 6 :
+RESERVED_INPUT : R20 : : : : 6 :
+GND : R21 : gnd : : : :
+nSTATUS : R22 : : : : 6 :
+CONF_DONE : R23 : : : : 6 :
+RESERVED_INPUT : R24 : : : : 6 :
+RESERVED_INPUT : R25 : : : : 6 :
+GND : R26 : gnd : : : :
+VCCIO1 : T1 : power : : 3.3V : 1 :
+HEX5[0] : T2 : output : 3.3-V LVTTL : : 1 : Y
+HEX4[6] : T3 : output : 3.3-V LVTTL : : 1 : Y
+HEX4[3] : T4 : output : 3.3-V LVTTL : : 1 : Y
+GND : T5 : gnd : : : :
+RESERVED_INPUT : T6 : : : : 1 :
+DPDT_SW[13] : T7 : input : 3.3-V LVTTL : : 1 : Y
+RESERVED_INPUT : T8 : : : : 1 :
+HEX5[3] : T9 : output : 3.3-V LVTTL : : 1 : Y
+RESERVED_INPUT : T10 : : : : 1 :
+VCCINT : T11 : power : : 1.2V : :
+GND : T12 : gnd : : : :
+GND : T13 : gnd : : : :
+GND : T14 : gnd : : : :
+GND : T15 : gnd : : : :
+VCCINT : T16 : power : : 1.2V : :
+RESERVED_INPUT : T17 : : : : 6 :
+RESERVED_INPUT : T18 : : : : 6 :
+RESERVED_INPUT : T19 : : : : 6 :
+RESERVED_INPUT : T20 : : : : 6 :
+RESERVED_INPUT : T21 : : : : 6 :
+RESERVED_INPUT : T22 : : : : 6 :
+RESERVED_INPUT : T23 : : : : 6 :
+RESERVED_INPUT : T24 : : : : 6 :
+RESERVED_INPUT : T25 : : : : 6 :
+VCCIO6 : T26 : power : : 3.3V : 6 :
+HEX4[1] : U1 : output : 3.3-V LVTTL : : 1 : Y
+HEX4[2] : U2 : output : 3.3-V LVTTL : : 1 : Y
+DPDT_SW[14] : U3 : input : 3.3-V LVTTL : : 1 : Y
+DPDT_SW[15] : U4 : input : 3.3-V LVTTL : : 1 : Y
+RESERVED_INPUT : U5 : : : : 1 :
+RESERVED_INPUT : U6 : : : : 1 :
+RESERVED_INPUT : U7 : : : : 1 :
+GND : U8 : gnd : : : :
+HEX4[0] : U9 : output : 3.3-V LVTTL : : 1 : Y
+RESERVED_INPUT : U10 : : : : 1 :
+VCCINT : U11 : power : : 1.2V : :
+RESERVED_INPUT : U12 : : : : 8 :
+VCCINT : U13 : power : : 1.2V : :
+VCCINT : U14 : power : : 1.2V : :
+VCCINT : U15 : power : : 1.2V : :
+VCCINT : U16 : power : : 1.2V : :
+LED_GREEN[5] : U17 : output : 3.3-V LVTTL : : 7 : Y
+LED_GREEN[4] : U18 : output : 3.3-V LVTTL : : 7 : Y
+GND : U19 : gnd : : : :
+RESERVED_INPUT : U20 : : : : 6 :
+RESERVED_INPUT : U21 : : : : 6 :
+HEX3[5] : U22 : output : 3.3-V LVTTL : : 6 : Y
+RESERVED_INPUT : U23 : : : : 6 :
+RESERVED_INPUT : U24 : : : : 6 :
+RESERVED_INPUT : U25 : : : : 6 :
+RESERVED_INPUT : U26 : : : : 6 :
+DPDT_SW[16] : V1 : input : 3.3-V LVTTL : : 1 : Y
+DPDT_SW[17] : V2 : input : 3.3-V LVTTL : : 1 : Y
+RESERVED_INPUT : V3 : : : : 1 :
+RESERVED_INPUT : V4 : : : : 1 :
+RESERVED_INPUT : V5 : : : : 1 :
+RESERVED_INPUT : V6 : : : : 1 :
+RESERVED_INPUT : V7 : : : : 1 :
+VCCIO1 : V8 : power : : 3.3V : 1 :
+RESERVED_INPUT : V9 : : : : 8 :
+RESERVED_INPUT : V10 : : : : 8 :
+RESERVED_INPUT : V11 : : : : 8 :
+VCCIO8 : V12 : power : : 3.3V : 8 :
+HEX0[6] : V13 : output : 3.3-V LVTTL : : 8 : Y
+HEX0[5] : V14 : output : 3.3-V LVTTL : : 8 : Y
+VCCIO7 : V15 : power : : 3.3V : 7 :
+VCCINT : V16 : power : : 1.2V : :
+RESERVED_INPUT : V17 : : : : 7 :
+LED_GREEN[3] : V18 : output : 3.3-V LVTTL : : 7 : Y
+VCCIO6 : V19 : power : : 3.3V : 6 :
+HEX1[0] : V20 : output : 3.3-V LVTTL : : 6 : Y
+HEX1[1] : V21 : output : 3.3-V LVTTL : : 6 : Y
+HEX2[1] : V22 : output : 3.3-V LVTTL : : 6 : Y
+RESERVED_INPUT : V23 : : : : 6 :
+RESERVED_INPUT : V24 : : : : 6 :
+RESERVED_INPUT : V25 : : : : 6 :
+RESERVED_INPUT : V26 : : : : 6 :
+RESERVED_INPUT : W1 : : : : 1 :
+RESERVED_INPUT : W2 : : : : 1 :
+RESERVED_INPUT : W3 : : : : 1 :
+RESERVED_INPUT : W4 : : : : 1 :
+GND : W5 : gnd : : : :
+RESERVED_INPUT : W6 : : : : 1 :
+GND_PLL1 : W7 : gnd : : : :
+RESERVED_INPUT : W8 : : : : 8 :
+VCCIO8 : W9 : power : : 3.3V : 8 :
+RESERVED_INPUT : W10 : : : : 8 :
+RESERVED_INPUT : W11 : : : : 8 :
+RESERVED_INPUT : W12 : : : : 8 :
+GND : W13 : gnd : : : :
+GND : W14 : gnd : : : :
+RESERVED_INPUT : W15 : : : : 7 :
+RESERVED_INPUT : W16 : : : : 7 :
+RESERVED_INPUT : W17 : : : : 7 :
+VCCIO7 : W18 : power : : 3.3V : 7 :
+LED_GREEN[2] : W19 : output : 3.3-V LVTTL : : 7 : Y
+GND_PLL4 : W20 : gnd : : : :
+HEX1[2] : W21 : output : 3.3-V LVTTL : : 6 : Y
+GND : W22 : gnd : : : :
+RESERVED_INPUT : W23 : : : : 6 :
+HEX3[6] : W24 : output : 3.3-V LVTTL : : 6 : Y
+RESERVED_INPUT : W25 : : : : 6 :
+KEY[3] : W26 : input : 3.3-V LVTTL : : 6 : Y
+RESERVED_INPUT : Y1 : : : : 1 :
+NC : Y2 : : : : :
+RESERVED_INPUT : Y3 : : : : 1 :
+RESERVED_INPUT : Y4 : : : : 1 :
+RESERVED_INPUT : Y5 : : : : 1 :
+GND_PLL1 : Y6 : gnd : : : :
+VCCD_PLL1 : Y7 : power : : 1.2V : :
+GNDA_PLL1 : Y8 : gnd : : : :
+GND : Y9 : gnd : : : :
+RESERVED_INPUT : Y10 : : : : 8 :
+RESERVED_INPUT : Y11 : : : : 8 :
+LED_GREEN[8] : Y12 : output : 3.3-V LVTTL : : 8 : Y
+LED_RED[9] : Y13 : output : 3.3-V LVTTL : : 7 : Y
+RESERVED_INPUT : Y14 : : : : 7 :
+RESERVED_INPUT : Y15 : : : : 7 :
+RESERVED_INPUT : Y16 : : : : 7 :
+GND : Y17 : gnd : : : :
+LED_GREEN[7] : Y18 : output : 3.3-V LVTTL : : 7 : Y
+GNDA_PLL4 : Y19 : gnd : : : :
+VCCD_PLL4 : Y20 : power : : 1.2V : :
+RESERVED_INPUT : Y21 : : : : 6 :
+HEX1[3] : Y22 : output : 3.3-V LVTTL : : 6 : Y
+HEX3[0] : Y23 : output : 3.3-V LVTTL : : 6 : Y
+HEX2[6] : Y24 : output : 3.3-V LVTTL : : 6 : Y
+HEX3[4] : Y25 : output : 3.3-V LVTTL : : 6 : Y
+HEX3[3] : Y26 : output : 3.3-V LVTTL : : 6 : Y
Index: trunk/XILINX/BUILD_SCC_SRCH/SP6/DE2.qsf
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/SP6/DE2.qsf (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/SP6/DE2.qsf (revision 17)
@@ -0,0 +1,546 @@
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name LAST_QUARTUS_VERSION 10.0
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_N25 -to DPDT_SW[0]
+set_location_assignment PIN_N26 -to DPDT_SW[1]
+set_location_assignment PIN_P25 -to DPDT_SW[2]
+set_location_assignment PIN_AE14 -to DPDT_SW[3]
+set_location_assignment PIN_AF14 -to DPDT_SW[4]
+set_location_assignment PIN_AD13 -to DPDT_SW[5]
+set_location_assignment PIN_AC13 -to DPDT_SW[6]
+set_location_assignment PIN_C13 -to DPDT_SW[7]
+set_location_assignment PIN_B13 -to DPDT_SW[8]
+set_location_assignment PIN_A13 -to DPDT_SW[9]
+set_location_assignment PIN_N1 -to DPDT_SW[10]
+set_location_assignment PIN_P1 -to DPDT_SW[11]
+set_location_assignment PIN_P2 -to DPDT_SW[12]
+set_location_assignment PIN_T7 -to DPDT_SW[13]
+set_location_assignment PIN_U3 -to DPDT_SW[14]
+set_location_assignment PIN_U4 -to DPDT_SW[15]
+set_location_assignment PIN_V1 -to DPDT_SW[16]
+set_location_assignment PIN_V2 -to DPDT_SW[17]
+set_location_assignment PIN_T6 -to DRAM_ADDR[0]
+set_location_assignment PIN_V4 -to DRAM_ADDR[1]
+set_location_assignment PIN_V3 -to DRAM_ADDR[2]
+set_location_assignment PIN_W2 -to DRAM_ADDR[3]
+set_location_assignment PIN_W1 -to DRAM_ADDR[4]
+set_location_assignment PIN_U6 -to DRAM_ADDR[5]
+set_location_assignment PIN_U7 -to DRAM_ADDR[6]
+set_location_assignment PIN_U5 -to DRAM_ADDR[7]
+set_location_assignment PIN_W4 -to DRAM_ADDR[8]
+set_location_assignment PIN_W3 -to DRAM_ADDR[9]
+set_location_assignment PIN_Y1 -to DRAM_ADDR[10]
+set_location_assignment PIN_V5 -to DRAM_ADDR[11]
+set_location_assignment PIN_AE2 -to DRAM_BA_0
+set_location_assignment PIN_AE3 -to DRAM_BA_1
+set_location_assignment PIN_AB3 -to DRAM_CAS_N
+set_location_assignment PIN_AA6 -to DRAM_CKE
+set_location_assignment PIN_AA7 -to DRAM_CLK
+set_location_assignment PIN_AC3 -to DRAM_CS_N
+set_location_assignment PIN_V6 -to DRAM_DQ[0]
+set_location_assignment PIN_AA2 -to DRAM_DQ[1]
+set_location_assignment PIN_AA1 -to DRAM_DQ[2]
+set_location_assignment PIN_Y3 -to DRAM_DQ[3]
+set_location_assignment PIN_Y4 -to DRAM_DQ[4]
+set_location_assignment PIN_R8 -to DRAM_DQ[5]
+set_location_assignment PIN_T8 -to DRAM_DQ[6]
+set_location_assignment PIN_V7 -to DRAM_DQ[7]
+set_location_assignment PIN_W6 -to DRAM_DQ[8]
+set_location_assignment PIN_AB2 -to DRAM_DQ[9]
+set_location_assignment PIN_AB1 -to DRAM_DQ[10]
+set_location_assignment PIN_AA4 -to DRAM_DQ[11]
+set_location_assignment PIN_AA3 -to DRAM_DQ[12]
+set_location_assignment PIN_AC2 -to DRAM_DQ[13]
+set_location_assignment PIN_AC1 -to DRAM_DQ[14]
+set_location_assignment PIN_AA5 -to DRAM_DQ[15]
+set_location_assignment PIN_AD2 -to DRAM_LDQM
+set_location_assignment PIN_Y5 -to DRAM_UDQM
+set_location_assignment PIN_AB4 -to DRAM_RAS_N
+set_location_assignment PIN_AD3 -to DRAM_WE_N
+set_location_assignment PIN_AC18 -to FL_ADDR[0]
+set_location_assignment PIN_AB18 -to FL_ADDR[1]
+set_location_assignment PIN_AE19 -to FL_ADDR[2]
+set_location_assignment PIN_AF19 -to FL_ADDR[3]
+set_location_assignment PIN_AE18 -to FL_ADDR[4]
+set_location_assignment PIN_AF18 -to FL_ADDR[5]
+set_location_assignment PIN_Y16 -to FL_ADDR[6]
+set_location_assignment PIN_AA16 -to FL_ADDR[7]
+set_location_assignment PIN_AD17 -to FL_ADDR[8]
+set_location_assignment PIN_AC17 -to FL_ADDR[9]
+set_location_assignment PIN_AE17 -to FL_ADDR[10]
+set_location_assignment PIN_AF17 -to FL_ADDR[11]
+set_location_assignment PIN_W16 -to FL_ADDR[12]
+set_location_assignment PIN_W15 -to FL_ADDR[13]
+set_location_assignment PIN_AC16 -to FL_ADDR[14]
+set_location_assignment PIN_AD16 -to FL_ADDR[15]
+set_location_assignment PIN_AE16 -to FL_ADDR[16]
+set_location_assignment PIN_AC15 -to FL_ADDR[17]
+set_location_assignment PIN_AB15 -to FL_ADDR[18]
+set_location_assignment PIN_AA15 -to FL_ADDR[19]
+set_location_assignment PIN_V17 -to FL_CE_N
+set_location_assignment PIN_W17 -to FL_OE_N
+set_location_assignment PIN_AD19 -to FL_DQ[0]
+set_location_assignment PIN_AC19 -to FL_DQ[1]
+set_location_assignment PIN_AF20 -to FL_DQ[2]
+set_location_assignment PIN_AE20 -to FL_DQ[3]
+set_location_assignment PIN_AB20 -to FL_DQ[4]
+set_location_assignment PIN_AC20 -to FL_DQ[5]
+set_location_assignment PIN_AF21 -to FL_DQ[6]
+set_location_assignment PIN_AE21 -to FL_DQ[7]
+set_location_assignment PIN_AA18 -to FL_RST_N
+set_location_assignment PIN_AA17 -to FL_WE_N
+set_location_assignment PIN_AF10 -to HEX0[0]
+set_location_assignment PIN_AB12 -to HEX0[1]
+set_location_assignment PIN_AC12 -to HEX0[2]
+set_location_assignment PIN_AD11 -to HEX0[3]
+set_location_assignment PIN_AE11 -to HEX0[4]
+set_location_assignment PIN_V14 -to HEX0[5]
+set_location_assignment PIN_V13 -to HEX0[6]
+set_location_assignment PIN_V20 -to HEX1[0]
+set_location_assignment PIN_V21 -to HEX1[1]
+set_location_assignment PIN_W21 -to HEX1[2]
+set_location_assignment PIN_Y22 -to HEX1[3]
+set_location_assignment PIN_AA24 -to HEX1[4]
+set_location_assignment PIN_AA23 -to HEX1[5]
+set_location_assignment PIN_AB24 -to HEX1[6]
+set_location_assignment PIN_AB23 -to HEX2[0]
+set_location_assignment PIN_V22 -to HEX2[1]
+set_location_assignment PIN_AC25 -to HEX2[2]
+set_location_assignment PIN_AC26 -to HEX2[3]
+set_location_assignment PIN_AB26 -to HEX2[4]
+set_location_assignment PIN_AB25 -to HEX2[5]
+set_location_assignment PIN_Y24 -to HEX2[6]
+set_location_assignment PIN_Y23 -to HEX3[0]
+set_location_assignment PIN_AA25 -to HEX3[1]
+set_location_assignment PIN_AA26 -to HEX3[2]
+set_location_assignment PIN_Y26 -to HEX3[3]
+set_location_assignment PIN_Y25 -to HEX3[4]
+set_location_assignment PIN_U22 -to HEX3[5]
+set_location_assignment PIN_W24 -to HEX3[6]
+set_location_assignment PIN_U9 -to HEX4[0]
+set_location_assignment PIN_U1 -to HEX4[1]
+set_location_assignment PIN_U2 -to HEX4[2]
+set_location_assignment PIN_T4 -to HEX4[3]
+set_location_assignment PIN_R7 -to HEX4[4]
+set_location_assignment PIN_R6 -to HEX4[5]
+set_location_assignment PIN_T3 -to HEX4[6]
+set_location_assignment PIN_T2 -to HEX5[0]
+set_location_assignment PIN_P6 -to HEX5[1]
+set_location_assignment PIN_P7 -to HEX5[2]
+set_location_assignment PIN_T9 -to HEX5[3]
+set_location_assignment PIN_R5 -to HEX5[4]
+set_location_assignment PIN_R4 -to HEX5[5]
+set_location_assignment PIN_R3 -to HEX5[6]
+set_location_assignment PIN_R2 -to HEX6[0]
+set_location_assignment PIN_P4 -to HEX6[1]
+set_location_assignment PIN_P3 -to HEX6[2]
+set_location_assignment PIN_M2 -to HEX6[3]
+set_location_assignment PIN_M3 -to HEX6[4]
+set_location_assignment PIN_M5 -to HEX6[5]
+set_location_assignment PIN_M4 -to HEX6[6]
+set_location_assignment PIN_L3 -to HEX7[0]
+set_location_assignment PIN_L2 -to HEX7[1]
+set_location_assignment PIN_L9 -to HEX7[2]
+set_location_assignment PIN_L6 -to HEX7[3]
+set_location_assignment PIN_L7 -to HEX7[4]
+set_location_assignment PIN_P9 -to HEX7[5]
+set_location_assignment PIN_N9 -to HEX7[6]
+set_location_assignment PIN_G26 -to KEY[0]
+set_location_assignment PIN_N23 -to KEY[1]
+set_location_assignment PIN_P23 -to KEY[2]
+set_location_assignment PIN_W26 -to KEY[3]
+set_location_assignment PIN_AE23 -to LED_RED[0]
+set_location_assignment PIN_AF23 -to LED_RED[1]
+set_location_assignment PIN_AB21 -to LED_RED[2]
+set_location_assignment PIN_AC22 -to LED_RED[3]
+set_location_assignment PIN_AD22 -to LED_RED[4]
+set_location_assignment PIN_AD23 -to LED_RED[5]
+set_location_assignment PIN_AD21 -to LED_RED[6]
+set_location_assignment PIN_AC21 -to LED_RED[7]
+set_location_assignment PIN_AA14 -to LED_RED[8]
+set_location_assignment PIN_Y13 -to LED_RED[9]
+set_location_assignment PIN_AA13 -to LED_RED[10]
+set_location_assignment PIN_AC14 -to LED_RED[11]
+set_location_assignment PIN_AD15 -to LED_RED[12]
+set_location_assignment PIN_AE15 -to LED_RED[13]
+set_location_assignment PIN_AF13 -to LED_RED[14]
+set_location_assignment PIN_AE13 -to LED_RED[15]
+set_location_assignment PIN_AE12 -to LED_RED[16]
+set_location_assignment PIN_AD12 -to LED_RED[17]
+set_location_assignment PIN_AE22 -to LED_GREEN[0]
+set_location_assignment PIN_AF22 -to LED_GREEN[1]
+set_location_assignment PIN_W19 -to LED_GREEN[2]
+set_location_assignment PIN_V18 -to LED_GREEN[3]
+set_location_assignment PIN_U18 -to LED_GREEN[4]
+set_location_assignment PIN_U17 -to LED_GREEN[5]
+set_location_assignment PIN_AA20 -to LED_GREEN[6]
+set_location_assignment PIN_Y18 -to LED_GREEN[7]
+set_location_assignment PIN_Y12 -to LED_GREEN[8]
+set_location_assignment PIN_D13 -to OSC_27
+set_location_assignment PIN_N2 -to OSC_50
+set_location_assignment PIN_P26 -to EXT_CLOCK
+set_location_assignment PIN_D26 -to PS2_CLK
+set_location_assignment PIN_C24 -to PS2_DAT
+set_location_assignment PIN_C25 -to UART_RXD
+set_location_assignment PIN_B25 -to UART_TXD
+set_location_assignment PIN_K4 -to LCD_RW
+set_location_assignment PIN_K3 -to LCD_EN
+set_location_assignment PIN_K1 -to LCD_RS
+set_location_assignment PIN_J1 -to LCD_DATA[0]
+set_location_assignment PIN_J2 -to LCD_DATA[1]
+set_location_assignment PIN_H1 -to LCD_DATA[2]
+set_location_assignment PIN_H2 -to LCD_DATA[3]
+set_location_assignment PIN_J4 -to LCD_DATA[4]
+set_location_assignment PIN_J3 -to LCD_DATA[5]
+set_location_assignment PIN_H4 -to LCD_DATA[6]
+set_location_assignment PIN_H3 -to LCD_DATA[7]
+set_location_assignment PIN_L4 -to LCD_ON
+set_location_assignment PIN_K2 -to LCD_BLON
+set_location_assignment PIN_AE4 -to SRAM_ADDR[0]
+set_location_assignment PIN_AF4 -to SRAM_ADDR[1]
+set_location_assignment PIN_AC5 -to SRAM_ADDR[2]
+set_location_assignment PIN_AC6 -to SRAM_ADDR[3]
+set_location_assignment PIN_AD4 -to SRAM_ADDR[4]
+set_location_assignment PIN_AD5 -to SRAM_ADDR[5]
+set_location_assignment PIN_AE5 -to SRAM_ADDR[6]
+set_location_assignment PIN_AF5 -to SRAM_ADDR[7]
+set_location_assignment PIN_AD6 -to SRAM_ADDR[8]
+set_location_assignment PIN_AD7 -to SRAM_ADDR[9]
+set_location_assignment PIN_V10 -to SRAM_ADDR[10]
+set_location_assignment PIN_V9 -to SRAM_ADDR[11]
+set_location_assignment PIN_AC7 -to SRAM_ADDR[12]
+set_location_assignment PIN_W8 -to SRAM_ADDR[13]
+set_location_assignment PIN_W10 -to SRAM_ADDR[14]
+set_location_assignment PIN_Y10 -to SRAM_ADDR[15]
+set_location_assignment PIN_AB8 -to SRAM_ADDR[16]
+set_location_assignment PIN_AC8 -to SRAM_ADDR[17]
+set_location_assignment PIN_AD8 -to SRAM_DQ[0]
+set_location_assignment PIN_AE6 -to SRAM_DQ[1]
+set_location_assignment PIN_AF6 -to SRAM_DQ[2]
+set_location_assignment PIN_AA9 -to SRAM_DQ[3]
+set_location_assignment PIN_AA10 -to SRAM_DQ[4]
+set_location_assignment PIN_AB10 -to SRAM_DQ[5]
+set_location_assignment PIN_AA11 -to SRAM_DQ[6]
+set_location_assignment PIN_Y11 -to SRAM_DQ[7]
+set_location_assignment PIN_AE7 -to SRAM_DQ[8]
+set_location_assignment PIN_AF7 -to SRAM_DQ[9]
+set_location_assignment PIN_AE8 -to SRAM_DQ[10]
+set_location_assignment PIN_AF8 -to SRAM_DQ[11]
+set_location_assignment PIN_W11 -to SRAM_DQ[12]
+set_location_assignment PIN_W12 -to SRAM_DQ[13]
+set_location_assignment PIN_AC9 -to SRAM_DQ[14]
+set_location_assignment PIN_AC10 -to SRAM_DQ[15]
+set_location_assignment PIN_AE10 -to SRAM_WE_N
+set_location_assignment PIN_AD10 -to SRAM_OE_N
+set_location_assignment PIN_AF9 -to SRAM_UB_N
+set_location_assignment PIN_AE9 -to SRAM_LB_N
+set_location_assignment PIN_AC11 -to SRAM_CE_N
+set_location_assignment PIN_K7 -to OTG_ADDR[0]
+set_location_assignment PIN_F2 -to OTG_ADDR[1]
+set_location_assignment PIN_F1 -to OTG_CS_N
+set_location_assignment PIN_G2 -to OTG_RD_N
+set_location_assignment PIN_G1 -to OTG_WR_N
+set_location_assignment PIN_G5 -to OTG_RST_N
+set_location_assignment PIN_F4 -to OTG_DATA[0]
+set_location_assignment PIN_D2 -to OTG_DATA[1]
+set_location_assignment PIN_D1 -to OTG_DATA[2]
+set_location_assignment PIN_F7 -to OTG_DATA[3]
+set_location_assignment PIN_J5 -to OTG_DATA[4]
+set_location_assignment PIN_J8 -to OTG_DATA[5]
+set_location_assignment PIN_J7 -to OTG_DATA[6]
+set_location_assignment PIN_H6 -to OTG_DATA[7]
+set_location_assignment PIN_E2 -to OTG_DATA[8]
+set_location_assignment PIN_E1 -to OTG_DATA[9]
+set_location_assignment PIN_K6 -to OTG_DATA[10]
+set_location_assignment PIN_K5 -to OTG_DATA[11]
+set_location_assignment PIN_G4 -to OTG_DATA[12]
+set_location_assignment PIN_G3 -to OTG_DATA[13]
+set_location_assignment PIN_J6 -to OTG_DATA[14]
+set_location_assignment PIN_K8 -to OTG_DATA[15]
+set_location_assignment PIN_B3 -to OTG_INT0
+set_location_assignment PIN_C3 -to OTG_INT1
+set_location_assignment PIN_C2 -to OTG_DACK0_N
+set_location_assignment PIN_B2 -to OTG_DACK1_N
+set_location_assignment PIN_F6 -to OTG_DREQ0
+set_location_assignment PIN_E5 -to OTG_DREQ1
+set_location_assignment PIN_F3 -to OTG_FSPEED
+set_location_assignment PIN_G6 -to OTG_LSPEED
+set_location_assignment PIN_B14 -to TDI
+set_location_assignment PIN_A14 -to TCS
+set_location_assignment PIN_D14 -to TCK
+set_location_assignment PIN_F14 -to TDO
+set_location_assignment PIN_C4 -to TD_RESET
+set_location_assignment PIN_C8 -to VGA_R[0]
+set_location_assignment PIN_F10 -to VGA_R[1]
+set_location_assignment PIN_G10 -to VGA_R[2]
+set_location_assignment PIN_D9 -to VGA_R[3]
+set_location_assignment PIN_C9 -to VGA_R[4]
+set_location_assignment PIN_A8 -to VGA_R[5]
+set_location_assignment PIN_H11 -to VGA_R[6]
+set_location_assignment PIN_H12 -to VGA_R[7]
+set_location_assignment PIN_F11 -to VGA_R[8]
+set_location_assignment PIN_E10 -to VGA_R[9]
+set_location_assignment PIN_B9 -to VGA_G[0]
+set_location_assignment PIN_A9 -to VGA_G[1]
+set_location_assignment PIN_C10 -to VGA_G[2]
+set_location_assignment PIN_D10 -to VGA_G[3]
+set_location_assignment PIN_B10 -to VGA_G[4]
+set_location_assignment PIN_A10 -to VGA_G[5]
+set_location_assignment PIN_G11 -to VGA_G[6]
+set_location_assignment PIN_D11 -to VGA_G[7]
+set_location_assignment PIN_E12 -to VGA_G[8]
+set_location_assignment PIN_D12 -to VGA_G[9]
+set_location_assignment PIN_J13 -to VGA_B[0]
+set_location_assignment PIN_J14 -to VGA_B[1]
+set_location_assignment PIN_F12 -to VGA_B[2]
+set_location_assignment PIN_G12 -to VGA_B[3]
+set_location_assignment PIN_J10 -to VGA_B[4]
+set_location_assignment PIN_J11 -to VGA_B[5]
+set_location_assignment PIN_C11 -to VGA_B[6]
+set_location_assignment PIN_B11 -to VGA_B[7]
+set_location_assignment PIN_C12 -to VGA_B[8]
+set_location_assignment PIN_B12 -to VGA_B[9]
+set_location_assignment PIN_B8 -to VGA_CLK
+set_location_assignment PIN_D6 -to VGA_BLANK
+set_location_assignment PIN_A7 -to VGA_HS
+set_location_assignment PIN_D8 -to VGA_VS
+set_location_assignment PIN_B7 -to VGA_SYNC
+set_location_assignment PIN_A6 -to I2C_SCLK
+set_location_assignment PIN_B6 -to I2C_SDAT
+set_location_assignment PIN_J9 -to TD_DATA[0]
+set_location_assignment PIN_E8 -to TD_DATA[1]
+set_location_assignment PIN_H8 -to TD_DATA[2]
+set_location_assignment PIN_H10 -to TD_DATA[3]
+set_location_assignment PIN_G9 -to TD_DATA[4]
+set_location_assignment PIN_F9 -to TD_DATA[5]
+set_location_assignment PIN_D7 -to TD_DATA[6]
+set_location_assignment PIN_C7 -to TD_DATA[7]
+set_location_assignment PIN_D5 -to TD_HS
+set_location_assignment PIN_K9 -to TD_VS
+set_location_assignment PIN_C5 -to AUD_ADCLRCK
+set_location_assignment PIN_B5 -to AUD_ADCDAT
+set_location_assignment PIN_C6 -to AUD_DACLRCK
+set_location_assignment PIN_A4 -to AUD_DACDAT
+set_location_assignment PIN_A5 -to AUD_XCK
+set_location_assignment PIN_B4 -to AUD_BCLK
+set_location_assignment PIN_D17 -to ENET_DATA[0]
+set_location_assignment PIN_C17 -to ENET_DATA[1]
+set_location_assignment PIN_B18 -to ENET_DATA[2]
+set_location_assignment PIN_A18 -to ENET_DATA[3]
+set_location_assignment PIN_B17 -to ENET_DATA[4]
+set_location_assignment PIN_A17 -to ENET_DATA[5]
+set_location_assignment PIN_B16 -to ENET_DATA[6]
+set_location_assignment PIN_B15 -to ENET_DATA[7]
+set_location_assignment PIN_B20 -to ENET_DATA[8]
+set_location_assignment PIN_A20 -to ENET_DATA[9]
+set_location_assignment PIN_C19 -to ENET_DATA[10]
+set_location_assignment PIN_D19 -to ENET_DATA[11]
+set_location_assignment PIN_B19 -to ENET_DATA[12]
+set_location_assignment PIN_A19 -to ENET_DATA[13]
+set_location_assignment PIN_E18 -to ENET_DATA[14]
+set_location_assignment PIN_D18 -to ENET_DATA[15]
+set_location_assignment PIN_B24 -to ENET_CLK
+set_location_assignment PIN_A21 -to ENET_CMD
+set_location_assignment PIN_A23 -to ENET_CS_N
+set_location_assignment PIN_B21 -to ENET_INT
+set_location_assignment PIN_A22 -to ENET_RD_N
+set_location_assignment PIN_B22 -to ENET_WR_N
+set_location_assignment PIN_B23 -to ENET_RST_N
+set_location_assignment PIN_AE24 -to IRDA_TXD
+set_location_assignment PIN_AE25 -to IRDA_RXD
+set_location_assignment PIN_AD24 -to SD_DAT
+set_location_assignment PIN_AC23 -to SD_DAT3
+set_location_assignment PIN_Y21 -to SD_CMD
+set_location_assignment PIN_AD25 -to SD_CLK
+#set_location_assignment PIN_D25 -to GPIO_0[0]
+#set_location_assignment PIN_J22 -to GPIO_0[1]
+#set_location_assignment PIN_E26 -to GPIO_0[2]
+#set_location_assignment PIN_E25 -to GPIO_0[3]
+#set_location_assignment PIN_F24 -to GPIO_0[4]
+#set_location_assignment PIN_F23 -to GPIO_0[5]
+#set_location_assignment PIN_J21 -to GPIO_0[6]
+set_location_assignment PIN_J21 -to UART_RXD_JP1_7
+#set_location_assignment PIN_J20 -to GPIO_0[7]
+#set_location_assignment PIN_F25 -to GPIO_0[8]
+#set_location_assignment PIN_F26 -to GPIO_0[9]
+set_location_assignment PIN_N18 -to GPIO_0_10
+#set_location_assignment PIN_P18 -to GPIO_0[11]
+#set_location_assignment PIN_G23 -to GPIO_0[12]
+#set_location_assignment PIN_G24 -to GPIO_0[13]
+#set_location_assignment PIN_K22 -to GPIO_0[14]
+#set_location_assignment PIN_G25 -to GPIO_0[15]
+#set_location_assignment PIN_H23 -to GPIO_0[16]
+#set_location_assignment PIN_H24 -to GPIO_0[17]
+#set_location_assignment PIN_J23 -to GPIO_0[18]
+#set_location_assignment PIN_J24 -to GPIO_0[19]
+#set_location_assignment PIN_H25 -to GPIO_0[20]
+set_location_assignment PIN_H25 -to I_OR7_JP1_35_bis
+#set_location_assignment PIN_H26 -to GPIO_0[21]
+#set_location_assignment PIN_H19 -to GPIO_0[22]
+set_location_assignment PIN_H19 -to I_OR8_JP1_36_bis
+#set_location_assignment PIN_K18 -to GPIO_0_[23]
+#set_location_assignment PIN_K19 -to GPIO_0[24]
+set_location_assignment PIN_K19 -to UART_TXD_JP1_27
+#set_location_assignment PIN_K21 -to GPIO_0[25]
+#set_location_assignment PIN_K23 -to GPIO_0[26]
+#set_location_assignment PIN_K24 -to GPIO_0[27]
+#set_location_assignment PIN_L21 -to GPIO_0[28]
+#set_location_assignment PIN_L20 -to GPIO_0[29]
+#set_location_assignment PIN_J25 -to GPIO_0[30]
+set_location_assignment PIN_J25 -to I_OR7_JP1_35
+#set_location_assignment PIN_J26 -to GPIO_0[31]
+set_location_assignment PIN_J26 -to I_OR8_JP1_36
+#set_location_assignment PIN_L23 -to GPIO_0[32]
+set_location_assignment PIN_L23 -to CONFIG_MODE_JP1_37
+#set_location_assignment PIN_L24 -to GPIO_0[33]
+set_location_assignment PIN_L24 -to I_OT2_JP1_38
+#set_location_assignment PIN_L25 -to GPIO_0[34]
+#set_location_assignment PIN_L19 -to GPIO_0[35]
+set_location_assignment PIN_L25 -to INIT_JP1_39
+#set_location_assignment PIN_K25 -to GPIO_1[0]
+set_location_assignment PIN_K25 -to I_OT7_JP2_41
+#set_location_assignment PIN_K26 -to GPIO_1[1]
+set_location_assignment PIN_K26 -to I_OT6_JP2_42
+#set_location_assignment PIN_M22 -to GPIO_1[2]
+set_location_assignment PIN_M22 -to I_OT4_JP2_43
+#set_location_assignment PIN_M23 -to GPIO_1[3]
+set_location_assignment PIN_M23 -to I_OT3_JP2_44
+#set_location_assignment PIN_M19 -to GPIO_1[4]
+set_location_assignment PIN_M19 -to I_OT1_JP2_45
+#set_location_assignment PIN_M20 -to GPIO_1[5]
+set_location_assignment PIN_M20 -to I_OT0_JP2_46
+#set_location_assignment PIN_N20 -to GPIO_1[6]
+set_location_assignment PIN_N20 -to CONFIG_OUT0_JP2_47
+#set_location_assignment PIN_M21 -to GPIO_1[7]
+set_location_assignment PIN_M21 -to I_OL6_JP2_48
+#set_location_assignment PIN_M24 -to GPIO_1[8]
+set_location_assignment PIN_M24 -to CONFIG_OUT1_JP2_49
+#set_location_assignment PIN_M25 -to GPIO_1[9]
+set_location_assignment PIN_M25 -to I_OL3_JP2_50
+#set_location_assignment PIN_N24 -to GPIO_1_10
+set_location_assignment PIN_N24 -to I_OL7_JP2_53
+#set_location_assignment PIN_P24 -to GPIO_1[11]
+set_location_assignment PIN_P24 -to I_OL0_JP2_54
+#set_location_assignment PIN_R25 -to GPIO_1[12]
+set_location_assignment PIN_R25 -to I_OL4_JP2_55
+#set_location_assignment PIN_R24 -to GPIO_1[13]
+set_location_assignment PIN_R24 -to I_OL8_JP2_56
+#set_location_assignment PIN_R20 -to GPIO_1[14]
+set_location_assignment PIN_R20 -to I_OL1_JP2_57
+#set_location_assignment PIN_T22 -to GPIO_1[15]
+set_location_assignment PIN_T22 -to I_OT8_JP2_58
+#set_location_assignment PIN_T23 -to GPIO_1_16
+set_location_assignment PIN_T23 -to I_OL2_JP2_59
+#set_location_assignment PIN_T24 -to GPIO_1[17]
+set_location_assignment PIN_T24 -to I_OB2_JP2_60
+#set_location_assignment PIN_T25 -to GPIO_1[18]
+set_location_assignment PIN_T25 -to I_OL5_JP2_61
+#set_location_assignment PIN_T18 -to GPIO_1[19]
+set_location_assignment PIN_T18 -to I_OB5_JP2_62
+#set_location_assignment PIN_T21 -to GPIO_1[20]
+set_location_assignment PIN_T21 -to I_OT5_JP2_63
+#set_location_assignment PIN_T20 -to GPIO_1[21]
+set_location_assignment PIN_T20 -to I_OR2_JP2_64
+#set_location_assignment PIN_U26 -to GPIO_1[22]
+set_location_assignment PIN_U26 -to I_OB8_JP2_65
+#set_location_assignment PIN_U25 -to GPIO_1[23]
+set_location_assignment PIN_U25 -to CONFIG_ACK_IN_JP2_66
+#set_location_assignment PIN_U23 -to GPIO_1[24]
+set_location_assignment PIN_U23 -to I_OR5_JP2_67
+#set_location_assignment PIN_U24 -to GPIO_1[25]
+set_location_assignment PIN_U24 -to I_OB0_JP2_68
+#set_location_assignment PIN_R19 -to GPIO_1[26]
+set_location_assignment PIN_R19 -to I_OB1_JP2_71
+#set_location_assignment PIN_T19 -to GPIO_1[27]
+set_location_assignment PIN_T19 -to I_OB3_JP2_72
+#set_location_assignment PIN_U20 -to GPIO_1[28]
+set_location_assignment PIN_U20 -to I_OB4_JP2_73
+#set_location_assignment PIN_U21 -to GPIO_1[29]
+set_location_assignment PIN_U21 -to I_OB6_JP2_74
+#set_location_assignment PIN_V26 -to GPIO_1[30]
+set_location_assignment PIN_V26 -to I_OB7_JP2_75
+#set_location_assignment PIN_V25 -to GPIO_1[31]
+set_location_assignment PIN_V25 -to I_OR0_JP2_76
+#set_location_assignment PIN_V24 -to GPIO_1[32]
+set_location_assignment PIN_V24 -to I_OR1_JP2_77
+#set_location_assignment PIN_V23 -to GPIO_1[33]
+set_location_assignment PIN_V23 -to I_OR3_JP2_78
+#set_location_assignment PIN_W25 -to GPIO_1[34]
+set_location_assignment PIN_W25 -to I_OR4_JP2_79
+#set_location_assignment PIN_W23 -to GPIO_1[35]
+set_location_assignment PIN_W23 -to I_OR6_JP2_80
+
+# Timing Assignments
+# ==================
+#set_global_assignment -name REPORT_IO_PATHS_SEPARATELY ON
+#set_global_assignment -name FLOW_ENABLE_TIMING_CONSTRAINT_CHECK ON
+#set_global_assignment -name DO_COMBINED_ANALYSIS OFF
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone II"
+set_global_assignment -name TOP_LEVEL_ENTITY DE2
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP2C35F672C6
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_instance_assignment -name IO_STANDARD LVTTL -to TD_DATA[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to TD_DATA[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to TD_DATA[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to TD_DATA[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to TD_DATA[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to TD_DATA[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to TD_DATA[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to TD_DATA[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to TD_HS
+set_instance_assignment -name IO_STANDARD LVTTL -to TD_VS
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to ENET_DATA[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to SD_DAT3
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+
+# Timing Analysis Assignments
+# ===========================
+set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS ON
+set_global_assignment -name ENABLE_CLOCK_LATENCY ON
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
+set_global_assignment -name FMAX_REQUIREMENT "50 MHz" -section_id OSC_50
+set_instance_assignment -name CLOCK_SETTINGS OSC_50 -to OSC_50
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+
+set_global_assignment -name FMAX_REQUIREMENT "50 MHz"
+set_global_assignment -name FLOW_ENABLE_TIMING_CONSTRAINT_CHECK OFF
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+
+set_global_assignment -name VERILOG_FILE CMD_Decode_simple.v
+set_global_assignment -name VHDL_FILE AI.vhd
+set_global_assignment -name SOURCE_FILE RS232_Command.h
+set_global_assignment -name VERILOG_FILE async_receiver_altera.v
+set_global_assignment -name VERILOG_FILE async_transmitter_altera.v
+set_global_assignment -name VERILOG_FILE DE2.v
+set_global_assignment -name VERILOG_FILE LCD_TEST_SAFE.v
+set_global_assignment -name VERILOG_FILE RS232_Controller.v
+set_global_assignment -name VERILOG_FILE SEG7_LUT.v
+set_global_assignment -name VERILOG_FILE SEG7_LUT_8.v
+
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
trunk/XILINX/BUILD_SCC_SRCH/SP6/DE2.qsf
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC_SRCH/SP6/LCD_TEST_SAFE.v
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/SP6/LCD_TEST_SAFE.v (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/SP6/LCD_TEST_SAFE.v (revision 17)
@@ -0,0 +1,335 @@
+module LCD_TEST ( // Host Side
+ iCLK,iRST_N,msg_in,
+ // LCD Side
+ LCD_DATA,LCD_RW,LCD_EN,LCD_RS );
+// Host Side
+input iCLK,iRST_N;
+input [2:0] msg_in;
+// LCD Side
+output [7:0] LCD_DATA;
+output LCD_RW,LCD_EN,LCD_RS;
+// Internal Wires/Registers
+reg [5:0] LUT_INDEX;
+reg[5:0] LUT_INDEX_NEXT;
+reg [8:0] LUT_DATA;
+reg [5:0] mLCD_ST,mLCD_nxt_ST;
+reg [17:0] mDLY;
+reg [17:0] mDLY_NEXT;
+reg mLCD_Start;
+reg mLCD_Start_NEXT;
+reg [7:0] mLCD_DATA;
+reg mLCD_RS;
+reg [2:0] msg_in_int;
+wire mLCD_Done;
+
+parameter LCD_INTIAL = 0;
+parameter LCD_LINE1 = 5;
+parameter LCD_CH_LINE = LCD_LINE1+16;
+parameter LCD_LINE2 = LCD_LINE1+16+1;
+parameter LUT_SIZE = LCD_LINE1+32+1;
+
+always@(posedge iCLK or negedge iRST_N)
+begin
+ if(!iRST_N)
+ begin
+ mLCD_ST<=4;
+ mLCD_DATA <= 0;
+ mLCD_RS <= 0;
+ msg_in_int <= 0;
+ end
+ else
+ begin
+ mLCD_ST<=mLCD_nxt_ST;
+ LUT_INDEX<=LUT_INDEX_NEXT;
+ mDLY<=mDLY_NEXT;
+ mLCD_Start<=mLCD_Start_NEXT;
+ msg_in_int<=msg_in;
+ mLCD_DATA <= LUT_DATA[7:0];
+ mLCD_RS <= LUT_DATA[8];
+ end
+end
+
+
+//always@(mLCD_ST or msg_in or msg_in_int or LUT_INDEX or LUT_DATA or msg_in_int)
+always@(*)
+ begin
+ case(mLCD_ST)
+ 0: begin
+ mLCD_Start_NEXT <= 1;
+ mDLY_NEXT <= mDLY;
+ if(msg_in_int!=msg_in)
+ begin
+ LUT_INDEX_NEXT<=0;
+ end
+ else begin
+ LUT_INDEX_NEXT<=LUT_INDEX;
+ end
+
+ if( LUT_INDEX>5))/(ClkFrequency>>4);
+reg [BaudGeneratorAccWidth:0] BaudGeneratorAcc;
+wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth];
+wire TxD_busy;
+always @(posedge clk) if(TxD_busy) BaudGeneratorAcc <= BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc;
+
+// Transmitter state machine
+reg [3:0] state;
+assign TxD_busy = (state!=0);
+
+always @(posedge clk)
+case(state)
+ 4'b0000: if(TxD_start) state <= 4'b0100;
+ 4'b0100: if(BaudTick) state <= 4'b1000; // start
+ 4'b1000: if(BaudTick) state <= 4'b1001; // bit 0
+ 4'b1001: if(BaudTick) state <= 4'b1010; // bit 1
+ 4'b1010: if(BaudTick) state <= 4'b1011; // bit 2
+ 4'b1011: if(BaudTick) state <= 4'b1100; // bit 3
+ 4'b1100: if(BaudTick) state <= 4'b1101; // bit 4
+ 4'b1101: if(BaudTick) state <= 4'b1110; // bit 5
+ 4'b1110: if(BaudTick) state <= 4'b1111; // bit 6
+ 4'b1111: if(BaudTick) state <= 4'b0001; // bit 7
+ 4'b0001: if(BaudTick) state <= 4'b0010; // stop1
+ 4'b0010: if(BaudTick) state <= 4'b0000; // stop2
+ default: if(BaudTick) state <= 4'b0000;
+endcase
+
+// Output mux
+reg muxbit;
+always @(state[2:0] or TxD_data)
+case(state[2:0])
+ 0: muxbit <= TxD_data[0];
+ 1: muxbit <= TxD_data[1];
+ 2: muxbit <= TxD_data[2];
+ 3: muxbit <= TxD_data[3];
+ 4: muxbit <= TxD_data[4];
+ 5: muxbit <= TxD_data[5];
+ 6: muxbit <= TxD_data[6];
+ 7: muxbit <= TxD_data[7];
+endcase
+
+// Put together the start, data and stop bits
+reg TxD;
+always @(posedge clk) TxD <= (state<4) | (state[3] & muxbit); // register the output to make it glitch free
+
+endmodule
trunk/XILINX/BUILD_SCC_SRCH/SP6/async_transmitter_altera.v
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC_SRCH/SP6/SP6.synplify.tcl
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/SP6/SP6.synplify.tcl (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/SP6/SP6.synplify.tcl (revision 17)
@@ -0,0 +1,99 @@
+
+set project_name DE2
+set top_level DE2
+set sdc_constraints constraints.sdc
+
+# create a new project
+project -new ${project_name}
+
+# add coregen related files, if present
+if {[file exists coregen.tcl]} {
+ source coregen.tcl
+}
+
+# add verilog files
+# top level design must be last
+
+set mcsfiles [glob -directory ../../macrocells -nocomplain -tails -types f -- {*.v}]
+foreach mcs ${mcsfiles} {
+ if [ regexp -- {assertions} ${mcs} ] {
+ continue
+ }
+ add_file -verilog "../../macrocells/${mcs}"
+}
+
+set rtlfiles [glob -directory ../../rtl -nocomplain -tails -types f -- {*.v}]
+foreach rtl ${rtlfiles} {
+ if [ regexp -- {assertions} ${rtl} ] {
+ continue
+ }
+ add_file -verilog "../../rtl/${rtl}"
+}
+#set_global_assignment -name VERILOG_FILE ../../../../rtl_package/simu_stubs/vsim/bram_based_stream_buffer.v
+set sp6files [glob -directory ../../../../SP6/ -nocomplain -tails -types f -- {*\.vhd}]
+foreach mcs ${sp6files} {
+ if [ regexp -- {assertions} ${mcs} ] {
+ continue
+}
+ add_file -vhdl "../../../../SP6/${mcs}"
+}
+#DE2 files
+set sp6files [glob -directory ../../../../SP6/ -nocomplain -tails -types f -- {*\.v}]
+foreach mcs ${sp6files} {
+ if [ regexp -- {assertions} ${mcs} ] {
+ continue
+}
+ add_file -verilog "../../../../SP6/${mcs}"
+}
+
+# setting options and constraints
+
+set_option -top_module ${top_level}
+add_file "${sdc_constraints}"
+set_option -technology spartan6
+set_option -part xc6slx45t
+set_option -package fgg484
+set_option -speed_grade -3
+
+#compilation/mapping options
+set_option -default_enum_encoding onehot
+set_option -symbolic_fsm_compiler 1
+set_option -resource_sharing 1
+set_option -use_fsm_explorer 0
+
+#map options
+set_option -frequency 20
+set_option -run_prop_extract 1
+
+#Not setting the fanout limit.
+#Synplify to pick up appropriate fanout
+#set_option -fanout_limit 10000
+
+set_option -disable_io_insertion 0
+set_option -pipe 1
+set_option -update_models_cp 0
+set_option -verification_mode 0
+set_option -modular 0
+set_option -retiming 0
+set_option -no_sequential_opt 0
+set_option -fixgatedclocks 0
+
+#simulation options
+set_option -write_verilog 1
+set_option -write_vhdl 0
+#VIF options
+set_option -write_vif 1
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+project -result_file run/synthesis/${top_level}.edf
+
+#implementation attributes
+set_option -vlog_std v2001
+set_option -synthesis_onoff_pragma 0
+set_option -project_relative_includes 1
+
+# compile the design
+project -run
+project -save
Index: trunk/XILINX/BUILD_SCC_SRCH/SP6/SP605_BRD_clocks.v
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/SP6/SP605_BRD_clocks.v (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/SP6/SP605_BRD_clocks.v (revision 17)
@@ -0,0 +1,218 @@
+`timescale 100 ps / 10 ps
+//-------------------------------------
+// SP601_BRD_CLOCKS.v
+//-------------------------------------
+// History of Changes:
+// 5-5-2009 Initial creation
+// 6-15-2009 Added PLL to generate MCB clocks, also used PLL to generate some others.
+//-------------------------------------
+// This module contains all of the clock related stuff
+//-------------------------------------
+//
+module SP605_BRD_CLOCKS(
+
+// Differential sys clock
+input wire SYSCLK_P,SYSCLK_N,
+
+output wire CLK20, // 20 Mhz
+output wire CLK200, // 200 Mhz
+output wire PROC_CLK, // Processing Clock (200 Mhz?)
+output wire CLK125, // 125 Mhz
+
+// Master Clock for memory controller block
+output wire MCBCLK_2X_0, // CLKOUT0 from PLL @ 667 MHz
+output wire MCBCLK_2X_180, // CLKOUT1 from PLL @ 667 MHz, 180 degree phase
+output wire MCBCLK_PLL_LOCK, CLK_PLL_LOCK,// from PLL
+output wire CALIB_CLK, // GCLK. MIN = 50MHz, MAX = 100MHz.
+
+// 125 Mhz clocks (from PHY RXCLK)
+input wire PHY_RXCLK,
+output wire CLK125_RX, // 125 Mhz
+output wire CLK125_RX_BUFIO,
+input wire RST // system reset - resets PLLs, DCM's
+
+);
+
+parameter [7:0] PROC_CLK_FREQ = 8'd100;
+
+/* System Clock */
+// IBUFG the raw clock input
+wire osc_clk_ibufg;
+IBUFGDS #(
+ .DIFF_TERM("FALSE"), // Differential Termination (Virtex-4/5, Spartan-3E/3A)
+ .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for
+ // the buffer, "0"-"16" (Spartan-3E/3A only)
+ .IOSTANDARD("LVDS_25") // Specify the input I/O standard
+) inibufg (
+ .O(osc_clk_ibufg), // Clock buffer output
+ .I(SYSCLK_P), // Diff_p clock buffer input (connect directly to top-level port)
+ .IB(SYSCLK_N) // Diff_n clock buffer input (connect directly to top-level port)
+);
+
+ wire clk20_bufg_in, calib_clk_bufg_in, clk200_bufg_in, proc_clk_bufg_in; // raw PLL outputs
+ BUFG clk20_bufg (.I(clk20_bufg_in), .O(CLK20) );
+ BUFG calib_clk_bufg (.I(calib_clk_bufg_in), .O(CALIB_CLK) );
+ BUFG clk200_bufg (.I(clk200_bufg_in), .O(CLK200) );
+ BUFG proc_clk_bufg (.I(proc_clk_bufg_in), .O(PROC_CLK) );
+
+
+ wire clkfbout_clkfbin; // Clock from PLLFBOUT to PLLFBIN
+ wire clkfbout_clkfbin_125; // Clock from PLLFBOUT to PLLFBIN
+
+ PLL_ADV #
+ (
+ .BANDWIDTH ("OPTIMIZED"),
+ .CLKIN1_PERIOD (5), // 200 MHz = 5ns
+ .CLKIN2_PERIOD (1),
+ .DIVCLK_DIVIDE (3),
+ .CLKFBOUT_MULT (10), // 200 MHz x 10 / 3 = 667 Mhz
+ .CLKFBOUT_PHASE (0.0),
+ .CLKOUT0_DIVIDE (1), // 667 Mhz /1 = 667 Mhz
+ .CLKOUT1_DIVIDE (1), // 667 Mhz /1 = 667 Mhz
+ .CLKOUT2_DIVIDE (),
+ .CLKOUT3_DIVIDE (),
+ .CLKOUT4_DIVIDE (),
+ .CLKOUT5_DIVIDE (),
+ .CLKOUT0_PHASE (0.000),
+ .CLKOUT1_PHASE (180.000),
+ .CLKOUT2_PHASE (0.000),
+ .CLKOUT3_PHASE (0.000),
+ .CLKOUT4_PHASE (0.000),
+ .CLKOUT5_PHASE (0.000),
+ .CLKOUT0_DUTY_CYCLE (0.500),
+ .CLKOUT1_DUTY_CYCLE (0.500),
+ .CLKOUT2_DUTY_CYCLE (0.500),
+ .CLKOUT3_DUTY_CYCLE (0.500),
+ .CLKOUT4_DUTY_CYCLE (0.500),
+ .CLKOUT5_DUTY_CYCLE (0.500),
+ .COMPENSATION ("SYSTEM_SYNCHRONOUS"),
+ .REF_JITTER (0.005000)
+ )
+ u_pll_adv
+ (
+ .CLKFBIN (clkfbout_clkfbin),
+ .CLKINSEL (1'b1),
+ .CLKIN1 (osc_clk_ibufg),
+ .CLKIN2 (1'b0),
+ .DADDR (5'b0),
+ .DCLK (1'b0),
+ .DEN (1'b0),
+ .DI (16'b0),
+ .DWE (1'b0),
+ .REL (1'b0),
+ .RST (RST),
+ .CLKFBDCM (),
+ .CLKFBOUT (clkfbout_clkfbin),
+ .CLKOUTDCM0 (),
+ .CLKOUTDCM1 (),
+ .CLKOUTDCM2 (),
+ .CLKOUTDCM3 (),
+ .CLKOUTDCM4 (),
+ .CLKOUTDCM5 (),
+ .CLKOUT0 (MCBCLK_2X_0),
+ .CLKOUT1 (MCBCLK_2X_180),
+ .CLKOUT2 (),
+ .CLKOUT3 (),
+ .CLKOUT4 (),
+ .CLKOUT5 (),
+ .DO (),
+ .DRDY (),
+ .LOCKED (MCBCLK_PLL_LOCK)
+ );
+
+
+wire xclk125_tx;
+BUFG bufg125_tx(.I(xclk125_tx), .O(CLK125));
+
+
+ PLL_ADV #
+ (
+ .BANDWIDTH ("OPTIMIZED"),
+ .CLKIN1_PERIOD (5), // 200 MHz = 5ns
+ .CLKIN2_PERIOD (1),
+ .DIVCLK_DIVIDE (1),
+ .CLKFBOUT_MULT (5), // 200 * 5 = 1000 MHz
+ .CLKFBOUT_PHASE (0.0),
+ .CLKOUT0_DIVIDE (8), // 125 MHz
+ .CLKOUT1_DIVIDE (5), // 200 MHz
+ .CLKOUT2_DIVIDE (50), // 20 MHz
+ .CLKOUT3_DIVIDE (20), // 50 MHz
+ .CLKOUT4_DIVIDE (32), // 1000 / 32 = 31.25 MHz
+ .CLKOUT5_DIVIDE (),
+ .CLKOUT0_PHASE (0.000),
+ .CLKOUT1_PHASE (180.000),
+ .CLKOUT2_PHASE (0.000),
+ .CLKOUT3_PHASE (0.000),
+ .CLKOUT4_PHASE (0.000),
+ .CLKOUT5_PHASE (0.000),
+ .CLKOUT0_DUTY_CYCLE (0.500),
+ .CLKOUT1_DUTY_CYCLE (0.500),
+ .CLKOUT2_DUTY_CYCLE (0.500),
+ .CLKOUT3_DUTY_CYCLE (0.500),
+ .CLKOUT4_DUTY_CYCLE (0.500),
+ .CLKOUT5_DUTY_CYCLE (0.500),
+ .COMPENSATION ("SYSTEM_SYNCHRONOUS"),
+ .REF_JITTER (0.005000)
+ )
+ u_pll_adv_125
+ (
+ .CLKFBIN (clkfbout_clkfbin_125),
+ .CLKINSEL (1'b1),
+ .CLKIN1 (osc_clk_ibufg),
+ .CLKIN2 (1'b0),
+ .DADDR (5'b0),
+ .DCLK (1'b0),
+ .DEN (1'b0),
+ .DI (16'b0),
+ .DWE (1'b0),
+ .REL (1'b0),
+ .RST (RST),
+ .CLKFBDCM (),
+ .CLKFBOUT (clkfbout_clkfbin_125),
+ .CLKOUTDCM0 (),
+ .CLKOUTDCM1 (),
+ .CLKOUTDCM2 (),
+ .CLKOUTDCM3 (),
+ .CLKOUTDCM4 (),
+ .CLKOUTDCM5 (),
+ .CLKOUT0 (xclk125_tx),
+ .CLKOUT1 (clk200_bufg_in),
+ .CLKOUT2 (clk20_bufg_in),
+ .CLKOUT3 (calib_clk_bufg_in),
+ .CLKOUT4 (proc_clk_bufg_in),
+ .CLKOUT5 (),
+ .DO (),
+ .DRDY (),
+ .LOCKED (CLK_PLL_LOCK)
+ );
+
+
+
+wire phy_rxclk_ibufg;
+//psk replaced IBUFG with BUFIO2
+/*
+IBUFG ibufg125rx(.I(PHY_RXCLK), .O(CLK125_RX_int));
+
+
+
+
+//---------------------------------------------------------------------------
+// GMII Receiver Clock Logic
+//---------------------------------------------------------------------------
+
+// Route gmii_rx_clk through a BUFIO2/BUFG and onto global clock routing
+ BUFIO2 bufio_gmii_rx_clk (
+ .DIVCLK (),
+ .I (CLK125_RX_int),
+ .IOCLK (CLK125_RX_BUFIO),
+ .SERDESSTROBE ()
+ );
+
+ // Route rx_clk through a BUFG onto global clock routing
+ BUFG bufg_gmii_rx_clk (
+ .I (CLK125_RX_int),
+ .O (CLK125_RX)
+ );
+*/
+
+endmodule
Index: trunk/XILINX/BUILD_SCC_SRCH/SP6/DE2_USB_API.cdf
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/SP6/DE2_USB_API.cdf (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/SP6/DE2_USB_API.cdf (revision 17)
@@ -0,0 +1,13 @@
+/* Quartus II Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version */
+JedecChain;
+ FileRevision(JESD32A);
+ DefaultMfr(6E);
+
+ P ActionCode(Cfg)
+ Device PartName(EP2C35F672) Path("D:/My Documents/PhD_Research/MY_PAPERS/FPT2011/Connect6/DE2/HW1/") File("DE2_USB_API.sof") MfrSpec(OpMask(1));
+
+ChainEnd;
+
+AlteraBegin;
+ ChainType(JTAG);
+AlteraEnd;
Index: trunk/XILINX/BUILD_SCC_SRCH/SP6/LCD_Controller_safe.v
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/SP6/LCD_Controller_safe.v (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/SP6/LCD_Controller_safe.v (revision 17)
@@ -0,0 +1,82 @@
+module LCD_Controller ( // Host Side
+ iDATA,iRS,
+ iStart,oDone,
+ iCLK,iRST_N,
+ // LCD Interface
+ LCD_DATA,
+ LCD_RW,
+ LCD_EN,
+ LCD_RS );
+// CLK
+parameter CLK_Divide = 16;
+
+// Host Side
+input [7:0] iDATA;
+input iRS,iStart;
+input iCLK,iRST_N;
+output reg oDone;
+// LCD Interface
+output [7:0] LCD_DATA;
+output reg LCD_EN;
+output LCD_RW;
+output LCD_RS;
+// Internal Register
+reg [4:0] Cont;
+reg [1:0] ST;
+reg preStart,mStart;
+
+/////////////////////////////////////////////
+// Only write to LCD, bypass iRS to LCD_RS
+assign LCD_DATA = iDATA;
+assign LCD_RW = 1'b0;
+assign LCD_RS = iRS;
+/////////////////////////////////////////////
+
+always@(posedge iCLK or negedge iRST_N)
+begin
+ if(!iRST_N)
+ begin
+ oDone <= 1'b0;
+ LCD_EN <= 1'b0;
+ preStart<= 1'b0;
+ mStart <= 1'b0;
+ Cont <= 0;
+ ST <= 0;
+ end
+ else
+ begin
+ ////// Input Start Detect ///////
+ preStart<= iStart;
+ if({preStart,iStart}==2'b01)
+ begin
+ mStart <= 1'b1;
+ oDone <= 1'b0;
+ end
+ //////////////////////////////////
+ if(mStart)
+ begin
+ case(ST)
+ 0: ST <= 1; // Wait Setup
+ 1: begin
+ LCD_EN <= 1'b1;
+ ST <= 2;
+ end
+ 2: begin
+ if(ContiCLK,
+ --reset=>not(iRST_n),
+ reset=>iRST_p,
+ stallbar_out=>open,
+ rawdataout_pico_ret_connect6ai_synth_0_outenable=>open,
+ rawdataout_pico_connect6ai_synth_moveout_out_0_0_outenable=>out_enables(0),
+ rawdataout_pico_connect6ai_synth_moveout_out_1_0_outenable=>out_enables(1),
+ rawdataout_pico_connect6ai_synth_moveout_out_2_0_outenable=>out_enables(2),
+ rawdataout_pico_connect6ai_synth_moveout_out_3_0_outenable=>out_enables(3),
+ rawdataout_pico_connect6ai_synth_moveout_out_4_0_outenable=>out_enables(4),
+ rawdataout_pico_connect6ai_synth_moveout_out_5_0_outenable=>out_enables(5),
+ rawdataout_pico_connect6ai_synth_moveout_out_6_0_outenable=>out_enables(6),
+ rawdataout_pico_connect6ai_synth_moveout_out_7_0_outenable=>out_enables(7),
+ start=>iAI_start,
+ rawdatain_pico_connect6ai_synth_firstmove_in_0_0=>imovecount,
+ rawdatain_pico_connect6ai_synth_movein_0_in_1_0=>iAI_DATA(31 downto 24),
+ rawdatain_pico_connect6ai_synth_movein_1_in_2_0=>iAI_DATA(23 downto 16),
+ rawdatain_pico_connect6ai_synth_movein_2_in_3_0=>iAI_DATA(15 downto 8),
+ rawdatain_pico_connect6ai_synth_movein_3_in_4_0=>iAI_DATA(7 downto 0),
+ rawdatain_pico_connect6ai_synth_movein_4_in_5_0=>iAI_DATA(63 downto 56),
+ rawdatain_pico_connect6ai_synth_movein_5_in_6_0=>iAI_DATA(55 downto 48),
+ rawdatain_pico_connect6ai_synth_movein_6_in_7_0=>iAI_DATA(47 downto 40),
+ rawdatain_pico_connect6ai_synth_movein_7_in_8_0=>iAI_DATA(39 downto 32),
+ rawdatain_pico_connect6ai_synth_colour_in_9_0=>icolor,
+ --rawdatain_pico_connect6ai_synth_moveout_0_in_10_0=> to_stdlogicvector(x"00"),
+ --rawdatain_pico_connect6ai_synth_moveout_1_in_11_0=> to_stdlogicvector(x"00"),
+ --rawdatain_pico_connect6ai_synth_moveout_2_in_12_0=> to_stdlogicvector(x"00"),
+ --rawdatain_pico_connect6ai_synth_moveout_3_in_13_0=> to_stdlogicvector(x"00"),
+ --rawdatain_pico_connect6ai_synth_moveout_4_in_14_0=> to_stdlogicvector(x"00"),
+ --rawdatain_pico_connect6ai_synth_moveout_5_in_15_0=> to_stdlogicvector(x"00"),
+ --rawdatain_pico_connect6ai_synth_moveout_6_in_16_0=> to_stdlogicvector(x"00"),
+ --rawdatain_pico_connect6ai_synth_moveout_7_in_17_0=> to_stdlogicvector(x"00"),
+ rawdatain_pico_connect6ai_synth_moveout_0_in_10_0=> to_stdlogicvector(UNUSED_INPUT_VECTOR),
+ rawdatain_pico_connect6ai_synth_moveout_1_in_11_0=> to_stdlogicvector(UNUSED_INPUT_VECTOR),
+ rawdatain_pico_connect6ai_synth_moveout_2_in_12_0=> to_stdlogicvector(UNUSED_INPUT_VECTOR),
+ rawdatain_pico_connect6ai_synth_moveout_3_in_13_0=> to_stdlogicvector(UNUSED_INPUT_VECTOR),
+ rawdatain_pico_connect6ai_synth_moveout_4_in_14_0=> to_stdlogicvector(UNUSED_INPUT_VECTOR),
+ rawdatain_pico_connect6ai_synth_moveout_5_in_15_0=> to_stdlogicvector(UNUSED_INPUT_VECTOR),
+ rawdatain_pico_connect6ai_synth_moveout_6_in_16_0=> to_stdlogicvector(UNUSED_INPUT_VECTOR),
+ rawdatain_pico_connect6ai_synth_moveout_7_in_17_0=> to_stdlogicvector(UNUSED_INPUT_VECTOR),
+ rawdataout_pico_ret_connect6ai_synth_0=>open,
+ rawdataout_pico_connect6ai_synth_moveout_out_0_0=> mAI_DATA(63 downto 56),
+ rawdataout_pico_connect6ai_synth_moveout_out_1_0=> mAI_DATA(55 downto 48),
+ rawdataout_pico_connect6ai_synth_moveout_out_2_0=> mAI_DATA(47 downto 40),
+ rawdataout_pico_connect6ai_synth_moveout_out_3_0=> mAI_DATA(39 downto 32),
+ rawdataout_pico_connect6ai_synth_moveout_out_4_0=> mAI_DATA(31 downto 24),
+ rawdataout_pico_connect6ai_synth_moveout_out_5_0=> mAI_DATA(23 downto 16),
+ rawdataout_pico_connect6ai_synth_moveout_out_6_0=> mAI_DATA(15 downto 8),
+ rawdataout_pico_connect6ai_synth_moveout_out_7_0=> mAI_DATA(7 downto 0)
+ --instream_queue_di_0=>ils_fifo_queue_dismantle_outdata(47 downto 0),
+ --instream_queue_req_0=>tcab_instream_queue_req_0,
+ --instream_queue_ready_0=>ils_fifo_queue_dismantle_store_req,
+ --outstream_queue_do_1=>tcab_outstream_queue_do_1(47 downto 0),
+ --outstream_queue_req_1=>tcab_outstream_queue_req_1,
+ --outstream_queue_ready_1=>ils_fifo_queue_dismantle_load_req
+ );
+-- ils_fifo_queue_dismantle:bram_based_stream_buffer
+----#(.width(48), .depth(`CONNECT6AI_SYNTH_ILS_FIFO_QUEUE_DISMANTLE_LENGTH))
+-- port map(
+-- clk=>iCLK,
+-- --reset=>not(iRST_n),
+-- reset=>iRST_p,
+-- store_ready=>tcab_instream_queue_req_0,
+-- flush=>'0',
+-- store_req=>ils_fifo_queue_dismantle_store_req,
+-- load_req=>ils_fifo_queue_dismantle_load_req,
+-- load_ready=>tcab_outstream_queue_req_1,
+-- indata=>tcab_outstream_queue_do_1(47 downto 0),
+-- outdata=>ils_fifo_queue_dismantle_outdata(47 downto 0));
+
+process(iCLK)
+begin
+ if rising_edge(iCLK) then
+ if(iAI_start='1') then
+ out_enables_reg<="00000000";
+ for i in 0 to 7 loop
+ AI_DATA( 63-8*i downto 56-8*i)<="00000000";
+ end loop;
+ else
+ for i in 0 to 7 loop
+ if(out_enables(i)='1') then
+ out_enables_reg(i)<=out_enables(i);
+ AI_DATA( 63-8*i downto 56-8*i)<=mAI_DATA(63-8*i downto 56-8*i);
+ else
+ out_enables_reg(i)<=out_enables_reg(i);
+ AI_DATA( 63-8*i downto 56-8*i)<=AI_DATA(63-8*i downto 56-8*i);
+ end if;
+ end loop;
+ end if;
+ end if;
+end process;
+ oAI_Done<= out_enables_reg(0) and out_enables_reg(1) and out_enables_reg(2) and out_enables_reg(3) and
+ out_enables_reg(4) and out_enables_reg(5) and out_enables_reg(6) and out_enables_reg(7);
+
+ --oAI_Done<= out_enables(0) and out_enables(1) and out_enables(2) and out_enables(3);
+end architecture c_to_g;
Index: trunk/XILINX/BUILD_SCC_SRCH/SP6/setup.sh
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/SP6/setup.sh (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/SP6/setup.sh (revision 17)
@@ -0,0 +1,29 @@
+stty -F /dev/ttyS0 115200 cstopb -icanon -icrnl -ixon -opost -onlcr -imaxbel -echo -echoe -echok -echoke -echoctl -echonl min 1 time 0
+## SRSEL
+##echo -n -e '\x00\x00\x5B\x00\x00\x00\x00\xAA' > /dev/ttyS0
+#echo -n -e '\x61\x5B\x12\x34\x56\x00\x00\x33' > /dev/ttyS0
+## SETUP SRAM SRAM SRAM OUTSEL
+#echo -n -e '\x61\xA5\x12\x34\x56\x00\x00\x33' > /dev/ttyS0
+## WRITE SRAM NORMAL
+#echo -n -e '\x83\xA5\x00\x00\x00\x38\x41\xAA' > /dev/ttyS0
+## SETUP SRAM SRAM SRAM OUTSEL
+#echo -n -e '\x61\x4C\x12\x34\x56\xA5\xA5\x33' > /dev/ttyS0
+## SETUP SRAM SRAM SRAM OUTSEL
+#echo -n -e '\x61\xA5\x12\x34\x56\x00\x00\x33' > /dev/ttyS0
+## SRAM
+#echo -n -e '\x94\xA5\x00\x00\x00\x00\x00\xAA' > /dev/ttyS0
+## READ SRAM NORMAL
+#echo -n -e '\x94\xA5\x00\x00\x00\x00\x00\xAA' > /dev/ttyS0
+#
+# SDRSEL
+#echo -n -e '\x61\x1F\x12\x34\x56\x00\x00\x33' > /dev/ttyS0
+## SETUP SDRAM OUTSEL
+#echo -n -e '\x61\xB4\x12\x34\x56\x00\x00\x33' > /dev/ttyS0
+## WRITE SDRAM NORMAL
+#echo -n -e '\x83\xB4\x00\x00\x21\x45\x39\xAA' > /dev/ttyS0
+## SETUP SET_REG SRAM SRAM OUTSEL
+#echo -n -e '\x61\x4C\x12\x34\x56\xB4\xB4\x33' > /dev/ttyS0
+## SETUP SDRAM SDRAM OUTSEL
+#echo -n -e '\x61\xB4\x12\x34\x56\x00\x00\x33' > /dev/ttyS0
+## READ SDRAM
+#echo -n -e '\x94\xB4\x00\x00\x21\x00\x00\xAA' > /dev/ttyS0
trunk/XILINX/BUILD_SCC_SRCH/SP6/setup.sh
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC_SRCH/SP6/Makefile
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/SP6/Makefile (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/SP6/Makefile (revision 17)
@@ -0,0 +1,18 @@
+all:
+ quartus_map DE2_USB_API.qpf
+ quartus_fit DE2_USB_API.qpf
+ quartus_asm DE2_USB_API.qpf
+ quartus_pgm -c USB-Blaster -m jtag -o "p;DE2_USB_API.sof"
+test:
+ ./setup.sh
+ ../../FPT2011_AI_TERMINAL/connect6 -port /dev/ttyS0 -player D
+
+pgm:
+ quartus_pgm -c USB-Blaster -m jtag -o "p;DE2_USB_API.sof"
+
+sim:
+ vcom S_TO_AS.vhd
+ vcom S_TO_AS_CONFIG.vhd
+ vcom testbench.vhd
+clean:
+ rm -rf db *.msg *.smsg *.summary *.done *.rpt *.pof *.sof transcript incremental_db simulation
Index: trunk/XILINX/BUILD_SCC_SRCH/SP6/DE2.v
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/SP6/DE2.v (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/SP6/DE2.v (revision 17)
@@ -0,0 +1,163 @@
+
+module DE2
+ (
+ //////////////////// Clock Input ////////////////////
+ //OSC_27, // 27 MHz
+ //OSC_50, // 50 MHz
+
+ // Master clock input (muxed from many sources)
+ SYSCLK_P, SYSCLK_N,
+ EXT_CLOCK, // External Clock
+ //////////////////// Push Button ////////////////////
+ KEY, // Button[3:0]
+ //////////////////// DPDT Switch ////////////////////
+ DPDT_SW, // DPDT Switch[17:0]
+ //////////////////// 7-SEG Dispaly ////////////////////
+ HEX0, // Seven Segment Digital 0
+ HEX1, // Seven Segment Digital 1
+ HEX2, // Seven Segment Digital 2
+ HEX3, // Seven Segment Digital 3
+ HEX4, // Seven Segment Digital 4
+ HEX5, // Seven Segment Digital 5
+ HEX6, // Seven Segment Digital 6
+ HEX7, // Seven Segment Digital 7
+ //////////////////////// LED ////////////////////////
+ LED_GREEN, // LED Green[8:0]
+ LED_RED, // LED Red[17:0]
+ //////////////////////// UART ////////////////////////
+ UART_TXD, // UART Transmitter
+ UART_RXD, // UART Rceiver
+ TD_RESET
+
+ );
+
+//////////////////////// Clock Input ////////////////////////
+//input OSC_27; // 27 MHz
+//input OSC_50; // 50 MHz
+input SYSCLK_P, SYSCLK_N;
+input EXT_CLOCK; // External Clock
+//////////////////////// Push Button ////////////////////////
+input [3:0] KEY; // Button[3:0]
+//////////////////////// DPDT Switch ////////////////////////
+input [17:0] DPDT_SW; // DPDT Switch[17:0]
+//////////////////////// 7-SEG Dispaly ////////////////////////
+output [6:0] HEX0; // Seven Segment Digital 0
+output [6:0] HEX1; // Seven Segment Digital 1
+output [6:0] HEX2; // Seven Segment Digital 2
+output [6:0] HEX3; // Seven Segment Digital 3
+output [6:0] HEX4; // Seven Segment Digital 4
+output [6:0] HEX5; // Seven Segment Digital 5
+output [6:0] HEX6; // Seven Segment Digital 6
+output [6:0] HEX7; // Seven Segment Digital 7
+//////////////////////////// LED ////////////////////////////
+output [8:0] LED_GREEN; // LED Green[8:0]
+output [17:0] LED_RED; // LED Red[17:0]
+//////////////////////////// UART ////////////////////////////
+output UART_TXD; // UART Transmitter
+input UART_RXD; // UART Rceiver
+output TD_RESET;
+// USB JTAG
+wire [7:0] mRXD_DATA,mTXD_DATA;
+wire mRXD_Ready,mTXD_Done,mTXD_Start;
+wire mTCK;
+// SEG7
+wire [31:0] mSEG7_DIG;
+// AI
+wire [63:0] DATA_from_AI,DATA_to_AI;
+wire mAI_Start,mAI_Done;
+wire [7:0] mCOLOR;
+
+//------- Clocks -------
+wire clk200, clk20, clk50, proc_clk, clk125; // GCLK's
+wire mcbclk_2x_0, mcbclk_2x_180, mcbclk_pll_lock, calib_clk; // MCB sigs
+wire clk125_rx; // receive clock from PHY
+wire clk125_rx_bufio;
+wire PHY_RXCLK;
+assign clk50=calib_clk;
+
+SP605_BRD_CLOCKS //#(.PROC_CLK_FREQ(proc_clk_freq))
+clocks (
+ .SYSCLK_P(SYSCLK_P), .SYSCLK_N(SYSCLK_N),
+ .CLK20(clk20),
+ .CLK200(clk200),
+ .CLK125(clk125),
+ .PROC_CLK(proc_clk),
+ .MCBCLK_2X_0(mcbclk_2x_0), .MCBCLK_2X_180(mcbclk_2x_180), .MCBCLK_PLL_LOCK(mcbclk_pll_lock), .CALIB_CLK(calib_clk),
+ .PHY_RXCLK(PHY_RXCLK), .CLK125_RX(clk125_rx), .CLK125_RX_BUFIO(clk125_rx_bufio),
+ .RST(KEY[0])
+ );
+wire OSC_27; // 27 MHz
+wire OSC_50; // 50 MHz
+assign OSC_50 =clk20;
+//------- Clocks -------
+assign TD_RESET = 1'b1;
+
+
+
+
+SEG7_LUT_8 u0 ( HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7,mSEG7_DIG );
+
+wire mTXD_Done_not;
+RS232_Controller u1_bis( .iDATA(mTXD_DATA),.iTxD_Start(mTXD_Start),.oTxD_Busy(mTXD_Done_not),
+ .oDATA(mRXD_DATA),.oRxD_Ready(mRXD_Ready),.iCLK(OSC_50),.RST_n(KEY[0]),
+ .oTxD(UART_TXD),.iRxD(UART_RXD));
+//RS232_Controller u1_bis( .iDATA(8'b00101011),.iTxD_Start(1'b1),.oTxD_Busy(mTXD_Done_not),
+// .oDATA(mRXD_DATA),.oRxD_Ready(mRXD_Ready),.iCLK(OSC_50),.RST_n(KEY[0]),
+// .oTxD(UART_TXD),.iRxD(UART_RXD));
+assign mTXD_Done = !mTXD_Done_not;
+assign LED_RED[9] = mTXD_Done_not;
+
+//assign LED_RED[10] = ~mAI_Done;
+assign LED_RED[10]=~UART_RXD;
+assign LED_RED[11]=~UART_TXD;
+assign LED_RED[12]=KEY[0];
+//assign mRXD_DATA=LED_RED[12];
+
+wire rst=!(KEY[0]);
+
+assign UART_RXD_JP1_7 = UART_RXD;
+assign UART_TXD_JP1_50 = UART_TXD;
+
+wire [63:0] CMD_Tmp;
+
+CMD_Decode u5 ( // USB JTAG
+ .iRXD_DATA(mRXD_DATA),.iRXD_Ready(mRXD_Ready),
+ .oTXD_DATA(mTXD_DATA),.oTXD_Start(mTXD_Start),.iTXD_Done(mTXD_Done),
+ // Control
+ .iCLK(OSC_50),.iRST_n(rst), .oAI_RSTn(mAI_RSTn),
+ //AI
+ .oAI_DATA(DATA_to_AI),
+ .iAI_DATA(DATA_from_AI),
+ .oAI_Start(mAI_Start),
+ .iAI_Done(mAI_Done),.oCOLOR(mCOLOR),.d_cmd(CMD_Tmp[16:0]) );
+
+//CMD_Decode u5 ( // USB JTAG
+// .iRXD_DATA(mRXD_DATA),.iRXD_Ready(mRXD_Ready),
+// .oTXD_DATA(mTXD_DATA),.oTXD_Start(mTXD_Start),.iTXD_Done(mTXD_Done),
+// // Control
+// .iCLK(OSC_50),.iRST_n(rst), .oAI_RSTn(mAI_RSTn),
+// //AI
+// .oAI_DATA(DATA_to_AI),
+// .iAI_DATA(DATA_from_AI),
+// .oAI_Start(mAI_Start),
+// .iAI_Done(KEY[1]),.oCOLOR(mCOLOR),.d_cmd(CMD_Tmp[16:0]) );
+AI inst_AI (
+ .oAI_DATA(DATA_from_AI),
+ .iAI_DATA(DATA_to_AI),
+ .iCOLOR(mCOLOR),
+ .imovecount(CMD_Tmp[16:0]),
+ .iAI_Start(mAI_Start),
+ .oAI_Done(mAI_Done),
+
+ // Control
+ .iCLK(OSC_50),.iRST_n(mAI_RSTn) );
+
+//assign mSEG7_DIG = { CMD_Tmp[31:28],CMD_Tmp[27:24],CMD_Tmp[23:20],CMD_Tmp[19:16],
+// CMD_Tmp[15:12],CMD_Tmp[11:8],CMD_Tmp[7:4],CMD_Tmp[3:0] };
+assign mSEG7_DIG = {
+// DATA_to_AI[63:60],DATA_to_AI[59:56],DATA_to_AI[55:52],DATA_to_AI[51:48],
+// DATA_to_AI[47:44],DATA_to_AI[43:40],DATA_to_AI[39:36],DATA_to_AI[35:32] }
+ DATA_from_AI[31:28],DATA_from_AI[27:24],DATA_from_AI[23:20],DATA_from_AI[19:16],
+ DATA_from_AI[15:12],DATA_from_AI[11:8],DATA_from_AI[7:4],DATA_from_AI[3:0] }
+ ;
+endmodule
Index: trunk/XILINX/BUILD_SCC_SRCH/synth_src/threat_line.cpp
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/synth_src/threat_line.cpp (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/synth_src/threat_line.cpp (revision 17)
@@ -0,0 +1,253 @@
+
+/*
+
+connectk -- a program to play the connect-k family of games
+Copyright (C) 2007 Michael Levin
+
+This program is free software; you can redistribute it and/or
+modify it under the terms of the GNU General Public License
+as published by the Free Software Foundation; either version 2
+of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+//#include "config.h"
+//#include
+//#include h>
+//#include
+#include "./shared.h"
+//#include "./q.hpp"
+#include "pico.h"
+//#include
+
+/* Bits per threat level */
+#define BITS_PER_THREAT 6
+
+
+//FIFO_INTERFACE(queue,AIMove);
+static AIWEIGHT threat_bits(int threat, PIECE type, Board *b)
+/* Bit pack the threat value */
+{
+ if (threat < 1)
+ return 0;
+
+ /* No extra value for building sequences over k - p unless it is
+ enough to win */
+ if (b->turn == type && connect_k - threat <= b->moves_left)
+ threat = connect_k - place_p + 1;
+ else if (threat >= connect_k - place_p)
+ threat = connect_k - place_p - (type == b->turn);
+
+ return 1 << ((threat - 1) * BITS_PER_THREAT);
+}
+
+static void threat_mark(int i, int threat, PIECE type,Board *b,Line *line)
+{
+ int j, index = 0;
+
+ if (threat <= 0)
+ return;
+
+ /* No extra value for building sequences over k - p unless it is
+ enough to win */
+ if (b->turn == type && connect_k - threat <= b->moves_left)
+ threat = connect_k - place_p + 1;
+ else if (threat >= connect_k - place_p)
+ threat = connect_k - place_p - (type == b->turn);
+
+ /* Do not mark if this threat is dominated by a preceeding threat;
+ Likewise supress any smaller threats */
+ for (j = i; j >= 0 && j > i - connect_k; j--)
+ if (line[j].threat[0] > threat)
+ return;
+ else if (line[j].threat[0] < threat) {
+ line[j].threat[0] = 0;
+ line[j].threat[1] = 0;
+ }
+
+ /* Store up to two threats per tile in the line */
+ if (line[i].threat[index])
+ index++;
+ line[i].threat[index] = threat;
+ line[i].turn[index] = type;
+}
+
+int threat_window(int x, int y, int dx, int dy,
+ PIECE *ptype, int *pdouble,Board *b)
+{
+ int minimum, maximum, count = 0;
+ PIECE p, type = PIECE_NONE;
+
+ /* Check if this tile is empty */
+ p = piece_at(b, x, y);
+ if (!piece_empty(p))
+ return 0;
+
+ /* Push forward the maximum and find the window type */
+ //#pragma unroll
+ #pragma num_iterations(1,3,6)
+ for (maximum = 1; maximum < connect_k; maximum++) {
+ p = piece_at(b, x + dx * maximum, y + dy * maximum);
+ if (p == PIECE_ERROR)
+ break;
+ if (!piece_empty(p)) {
+ if (type == PIECE_NONE)
+ type = p;
+ else if (type != p)
+ break;
+ count++;
+ }
+ }
+ maximum--;
+
+ /* Try to push the entire window back */
+ //#pragma unroll
+ #pragma num_iterations(1,3,6)
+ for (minimum = -1; minimum > -connect_k; minimum--) {
+ p = piece_at(b, x + dx * minimum, y + dy * minimum);
+ if (p == PIECE_ERROR || piece_empty(p))
+ break;
+ if (type == PIECE_NONE)
+ type = p;
+ else if (type != p)
+ break;
+ if (maximum - minimum > connect_k - 1) {
+ p = piece_at(b, x + dx * maximum, y + dy * maximum);
+ if (p == type)
+ count--;
+ maximum--;
+ }
+ count++;
+ }
+ minimum++;
+
+ /* Push back minimum if we haven't formed a complete window, this window
+ can't be a double */
+ if (maximum - minimum < connect_k - 1) {
+ //#pragma unroll
+ #pragma num_iterations(1,3,6)
+ for (minimum--; minimum > maximum - connect_k; minimum--) {
+ p = piece_at(b, x + dx * minimum, y + dy * minimum);
+ if (p == PIECE_ERROR)
+ break;
+ if (!piece_empty(p)) {
+ if (type != p)
+ break;
+ if (type == PIECE_NONE)
+ type = p;
+ count++;
+ }
+ }
+ *pdouble = 0;
+ minimum++;
+ }
+
+ *ptype = type;
+ if (maximum - minimum >= connect_k - 1)
+ return count;
+ return 0;
+}
+
+/*static*/ AIWEIGHT threat_line(int x, int y, int dx, int dy,Board *b,Board *bwrite,int k,int loop_bound)
+{
+
+ //#pragma read_write_ports threat_counts.data combined 2
+ //#pragma internal_blockram threat_counts
+ //#pragma no_memory_analysis threat_counts
+
+ //#pragma read_write_ports b.data combined 2
+ //#pragma internal_blockram b
+ //#pragma internal_blockram bwrite
+ //#pragma read_write_ports b.data separate 1 readonly 2 writeonly
+ //#pragma no_memory_analysis b
+ /* This is the line of threats currently being processed */
+ Line line[board_size]={{1},{2}};
+ #pragma internal_fast line
+ //#pragma multi_buffer line 2
+ //#pragma no_memory_analysis line
+ /* Running tally of threats for both players */
+ //static int threat_counts[MAX_CONNECT_K + 1][2];
+ threat_count_array threat_counts={{0}};
+ #pragma internal_fast threat_counts
+ //#pragma multi_buffer threat_counts 2
+ //#pragma read_write_ports threat_counts.data combined 2
+ //#pragma no_memory_analysis threat_counts
+ static Board btmp;
+ #pragma internal_blockram btmp
+ //#pragma multi_buffer btmp 2
+ if (k==1) board_copy(b, bwrite);
+ //if (k==loop_bound) board_copy(&btmp, bwrite);
+ int i;
+ AIWEIGHT weight = 0;
+ ///* Clear threat tallys */
+ //for (i = 0; i < connect_k; i++) {
+ // threat_counts.data[i][0] = 1;
+ // threat_counts.data[i][1] = 1;
+ //}
+
+ /* Mark the maximum threat for each */
+ for (i = 0; x >= 0 && x < board_size && y >= 0 && y < board_size; i++) {
+ int count[2], tmp, double_threat = 1;
+ PIECE type[2];
+
+ count[0] = threat_window(x, y, dx, dy, type, &double_threat,bwrite);
+ count[1] = threat_window(x, y, -dx, -dy, type + 1,
+ &double_threat,bwrite);
+ if (count[1] > count[0]) {
+ tmp = count[1];
+ count[1] = count[0];
+ count[0] = tmp;
+ tmp = type[1];
+ type[1] = type[0];
+ type[0] = tmp;
+ }
+ line[i].threat[0] = 0;
+ line[i].threat[1] = 0;
+ threat_mark(i, count[0], type[0],bwrite,&line[0]);
+ if (double_threat)
+ threat_mark(i, count[1], type[1],bwrite,&line[0]);
+ x += dx;
+ y += dy;
+ }
+
+ /* Commit stored line values to the board */
+ x -= dx;
+ y -= dy;
+ for (i--; x >= 0 && x < board_size && y >= 0 && y < board_size; i--) {
+ AIWEIGHT bits[2];
+ PIECE p;
+
+ bits[0] = threat_bits(line[i].threat[0], line[i].turn[0],bwrite);
+ bits[1] = threat_bits(line[i].threat[1], line[i].turn[1],bwrite);
+ p = piece_at(bwrite, x, y);
+ if (piece_empty(p) && line[i].threat[0]) {
+ threat_counts.data[line[i].threat[0]][line[i].turn[0] - 1]++;
+ if (line[i].threat[1])
+ threat_counts.data[line[i].threat[1]]
+ [line[i].turn[1] - 1]++;
+ if (p >= PIECE_THREAT0)
+ place_threat(bwrite, x, y, p - PIECE_THREAT0 +
+ bits[0] + bits[1]);
+ else
+ place_threat(bwrite, x, y, bits[0] + bits[1]);
+ }
+ if (bwrite->turn != line[i].turn[0])
+ bits[0] = -bits[0];
+ if (bwrite->turn != line[i].turn[1])
+ bits[1] = -bits[1];
+ weight += bits[0] + bits[1];
+ x -= dx;
+ y -= dy;
+ }
+ return weight;
+}
+
trunk/XILINX/BUILD_SCC_SRCH/synth_src/threat_line.cpp
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC_SRCH/synth_src/q.cpp.tmplt
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/synth_src/q.cpp.tmplt (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/synth_src/q.cpp.tmplt (revision 17)
@@ -0,0 +1,213 @@
+
+#ifdef PICO_SYNTH
+#define Q_ASSERT(_cond, _msg)
+#include
+#include "pico.h"
+#include "shared.h"
+using namespace std;
+#else
+/* not synthesizable */
+#include
+#include
+#include
+#include
+
+static void debug_assert (bool cond, char * msg) {
+ if (!cond) {
+ printf("assert failed: %s\n", msg);
+ assert(0);
+ }
+}
+
+#define Q_ASSERT(_cond, _msg) debug_assert(_cond, _msg)
+#endif
+FIFO(queue,AIMove);
+//template
+class q {
+ //tp arr[max_size];
+ #pragma fifo_length queue max_size
+ unsigned int head, tail;
+ unsigned char wrapped;
+ #pragma bitsize q.head ptr_bw
+ #pragma bitsize q.tail ptr_bw
+ #pragma bitsize q.wrapped 1
+
+ public:
+
+ /* constructor */
+ q () { head = tail = 0; wrapped = false; };
+
+ // /* returns front data of queue */
+ // tp front () {
+ // return arr[head];
+ // }
+
+ bool active;
+ /* return true iff queue is empty */
+ bool empty () {
+ return ((head == tail) && !wrapped);
+ }
+
+ /* return true iff queue is full */
+ bool full () {
+ return ((head == tail) && wrapped);
+ }
+
+ /* pop front of queue, returning the front data */
+ /* q is corrupted if pop when empty */
+ AIMove pop (){
+ /* assert that before pop, queue is not empty (underflow check) */
+ Q_ASSERT((!wrapped && (head < tail)) || (wrapped && (head >= tail)),
+ "queue underflowed");
+ AIMove d = pico_stream_input_queue();
+ cout <<"pop: "<= tail)),
+ "Queue overflowed") ;
+ cout <<"push: "< moves_fifo;
+//
+//#include "shared.h"
+//#include"q.hpp"
+//
+//#ifdef PICO_SYNTH
+//#define Q_ASSERT(_cond, _msg)
+//#include
+//#include "pico.h"
+//using namespace std;
+//#else
+///* not synthesizable */
+//#include
+//#include
+//#include
+//#include
+//
+//static void debug_assert (bool cond, char * msg) {
+// if (!cond) {
+// printf("assert failed: %s\n", msg);
+// assert(0);
+// }
+//}
+//
+//#define Q_ASSERT(_cond, _msg) debug_assert(_cond, _msg)
+//#endif
+//FIFO(queue,AIMove);
+//
+// /* pop front of queue, returning the front data */
+// /* q is corrupted if pop when empty */
+// template
+// tp q::pop () {
+// /* assert that before pop, queue is not empty (underflow check) */
+// Q_ASSERT((!wrapped && (head < tail)) || (wrapped && (head >= tail)),
+// "queue underflowed");
+// tp d = pico_stream_input_queue();
+// cout <<"pop: "<
+// void q::push (tp d) {
+// pico_stream_output_queue(d);
+// if (tail == max_size-1) {
+// tail = 0;
+// wrapped = true;
+// } else {
+// tail = tail + 1;
+// }
+// /* assert that after push, queue is not empty (overflow check) */
+// Q_ASSERT((!wrapped && (head < tail)) || (wrapped && (head >= tail)),
+// "Queue overflowed") ;
+// cout <<"push: "<
+// int q::size () {
+// if (wrapped) {
+// return (max_size - head) + (tail - 0);
+// } else {
+// return tail - head;
+// }
+// }
+//
+//#ifndef PICO_SYNTH
+// /* not synthesizable */
+// std::string to_string () const {
+// std::string s;
+// std::stringstream out;
+//
+// out << "{ ";
+//
+// if (wrapped) {
+// for (int i=head; i
+//std::ostream& operator << (std::ostream &os, const q &f)
+//{
+// os << f.to_string();
+// return os;
+//}
+//#endif
Index: trunk/XILINX/BUILD_SCC_SRCH/synth_src/search_bfs.cpp
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/synth_src/search_bfs.cpp (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/synth_src/search_bfs.cpp (revision 17)
@@ -0,0 +1,333 @@
+
+/*
+
+connectk -- UMN CSci 5512W project
+
+*/
+
+//#include "config.h"
+//#include
+//#include
+//#include
+//#include
+#include "./shared.h"
+#include "pico.h"
+//#include "../connectk.h"
+
+/* Variables required to check for cache hits */
+//static int cache_id = -1, cache_depth = -1, cache_branch = -1;
+//static SEARCH cache_search = -1;
+//static AIMoves *cache_moves = NULL;
+//static AIWEIGHT cache_best;
+//static Player *cache_player;
+//static AIFunc cache_func;
+//static BCOORD cache_size;
+
+int ai_stop=0;
+int mini(int x,int y){
+ return (x<=y)?x:y;
+}
+int maxi(int x,int y){
+ return (x>=y)?x:y;
+}
+int mod2(int x){
+#pragma bitsize x 5
+int ans[16]={0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1};
+return ans[x];
+}
+int mod5(int x){
+#pragma bitsize x 5
+int ans[16]={0,1,2,3,4,0,1,2,3,4,0,1,2,3,4,0};
+return ans[x];
+}
+/*static*/ AIWEIGHT df_search(Board *b, AIMoves *moves,/*index_array *index,*/ Player *player,int depth, int cache_index, PIECE searched, AIWEIGHT alpha, AIWEIGHT beta)
+/* Depth is in _moves_ */
+{
+ #pragma internal_fast index
+ int i, j;
+ #pragma bitsize i 16
+ #pragma bitsize j 16
+ Board b_next[2][16];
+ #pragma internal_blockram b_next
+ AIMoves moves_next[2][16];
+ #pragma internal_fast moves_next
+ #pragma unpacked moves_next
+ AIWEIGHT utility[5][16];
+ #pragma internal_blockram utility
+ PIECE turn[5]={b->turn};
+ int branch=player->branch;
+
+ board_copy(b, &b_next[0][0]);
+ ai_threats(b_next,0,0,moves_next/*,index*/);
+ utility[0][0]=moves_next[0][0].utility;
+ turn[0]=b->turn;
+ for(i=0;idata[i].x=moves_next[0][0].data[i].x;
+ moves->data[i].y=moves_next[0][0].data[i].y;
+ //moves->data[i].weight=moves_next[1][i].utility;
+ }
+
+ ///* Search only the top moves beyond the minimum */
+ ////aimoves_sort(moves);
+ //if (moves->len > player->branch) {
+ // //for (i = player->branch; i < moves->len; i++)
+ // // if (moves->data[i].weight != moves->data[0].weight)
+ // // break;
+ // //moves->len = i;
+ // moves->len = player->branch;
+ //}
+
+ /* No moves left -- its a draw */
+
+ if (moves_next[0][0].len < 1) //"(%s)", bcoords_to_string(aim->x, aim->y));
+
+ return AIW_DRAW;
+ //board_copy(b, &b_next[0][0]);
+
+ /* Search each move available in depth first order */
+ for(j=0;jbranch)^j;
+ //printf("branches %d\n",branches);
+ //int current_j=j % 2;
+ //int next_j=(j+1) % 2;
+ int current_j=mod2(j);
+ int next_j=mod2(j+1);
+ if (b_next[current_j][0].moves_left <= 0) turn[j]=other_player(b_next[current_j][0].turn);
+ else turn[j]=b_next[current_j][0].turn;
+
+ for (i = 0; i < branches; i++) {
+ //if(!(moves_next[j][i>>1].utility==AIW_WIN || moves_next[j][i>>1].utility==-AIW_WIN)){
+ if(!(utility[j][i>>1]==AIW_WIN || utility[j][i>>1]==-AIW_WIN)){
+ //AIMove aim = *(moves_next[current_j][i>>1].data + (i % branch));
+ AIMove aim = *(moves_next[current_j][i>>1].data + mod2(i));
+ //printf ("aim->utility %d \n",utility[j][i>>1]);
+
+ board_copy(&b_next[current_j][i>>1], &b_next[next_j][i]);
+ //if(moves_next[j][i/2].lenx, aim->y));
+ //printf("bad move\n");
+ continue;
+ }
+
+ /* Already searched here? */
+ ///////////////////////////if (piece_at(&b_next[j+1][i], aim->x, aim->y) == searched){
+ /////////////////////////// moves_next[j+1][i].utility=moves_next[j+1][i>>1].utility;
+ /////////////////////////// continue;
+ ///////////////////////////}
+ ///////////////////////////place_piece_type(&b_next[j+1][i], aim->x, aim->y, searched);
+
+ //b_next = board_new();
+ place_piece(&b_next[next_j][i], aim.x, aim.y);
+ AIWEIGHT next_alpha = alpha, next_beta = beta;
+ //AIFunc func;
+
+
+ /* Player has changed */
+ //printf("depth %d branches %d turn %d \n\n",j,branches,turn[j]);
+ if (b_next[next_j][i].moves_left <= 0) {
+ b_next[next_j][i].moves_left = place_p;
+ b_next[next_j][i].turn = other_player(b_next[current_j][i].turn);
+ searched++;
+ next_alpha = -beta;
+ next_beta = -alpha;
+ }
+ b_next[next_j][i].moves_left--;
+
+ /* Did we win? */
+
+ if (check_win_full(&b_next[1][i], aim.x, aim.y,0,0,0,0)){
+ aim.weight = AIW_WIN;
+ moves_next[next_j][i].utility=AIW_WIN;
+ utility[j+1][i]=AIW_WIN;
+
+
+ //}else if(moves_next[j][i>>1].utility==AIW_WIN || moves_next[j][i>>1].utility==-AIW_WIN ){
+ }else if(utility[j][i>>1]==AIW_WIN || utility[j][i>>1]==-AIW_WIN ){
+ //moves_next[j+1][i].utility=AIW_WIN;
+ utility[j+1][i]=AIW_WIN;
+ /* Otherwise, search deeper */
+ }else {
+
+ //func = ai(player->ai)->func;
+ //if (!func) {
+ // g_warning("DFS player has no AI function");
+ // return moves->utility;
+ //}
+ //moves_next = func(b_next);
+ ai_threats(b_next,next_j,i,moves_next/*,index*/);
+ utility[j+1][i]=moves_next[next_j][i].utility;
+
+ //aim->weight = df_search(&b_next, &moves_next, index,player,
+ // depth - 1, next_ci, searched,
+ // next_alpha, next_beta);
+ //aimoves_free(moves_next);
+ }
+ ////////////////////////////////////////////////////////////////////////if (b_next[next_j][i].turn != b->turn)
+ //moves_next[j+1][i].utility=-moves_next[j+1][i].utility;
+ ////////////////////////////////////////////////////////////////utility[j+1][i]=-moves_next[1][i].utility;
+ //if (moves_next[j+1][i].utility >= AIW_WIN)
+ // moves_next[j+1][i].utility=AIW_WIN;
+
+ /* Debug search */
+ //if (opt_debug_dfsc) {
+ // for(j = MAX_DEPTH - depth; j > 0; j--)
+ // //g_print("-");
+ // //g_print("> d=%d, %s, u=%d, a=%d, b=%d %s\n",
+ // // depth, bcoords_to_string(aim->x, aim->y),
+ // // aim->weight, alpha, beta,
+ // // piece_to_string(b->turn));
+ //}
+
+ //board_free(b_next);
+ //if (aim->weight > alpha) {
+ // alpha = aim->weight;
+ // //cache_set(cache_index, aim);
+
+ // /* Victory abort */
+ // if (alpha >= AIW_WIN)
+ // return AIW_WIN;
+
+ // /* Alpha-beta pruning */
+ // if (alpha >= beta)
+ // return alpha;
+ //}
+ //printf("%d %d %d\n",j,i,moves_next[j+1][i].utility);
+ }else //moves_next[j+1][i].utility=AIW_WIN;
+ utility[j+1][i]=AIW_WIN;
+ }
+ }
+ for(j=depth-2;j>=0;j--){
+ int k,branches=1;
+ for(k=0;kbranch)^j;
+ //printf("branches %d player %d\n",branches,b_next[j+1][i].turn);
+ for (i = 0; i < branches; i=i+2) {
+ //if (b_next[next_j][i].turn != b->turn)
+ if (turn[j] != b->turn)
+ //moves_next[j][i>>1].utility=mini(moves_next[j+1][i].utility,moves_next[j+1][i+1].utility);
+ utility[j][i>>1]=mini(utility[j+1][i],utility[j+1][i+1]);
+ else
+ //moves_next[j][i>>1].utility=maxi(moves_next[j+1][i].utility,moves_next[j+1][i+1].utility);
+ utility[j][i>>1]=maxi(utility[j+1][i],utility[j+1][i+1]);
+
+ //printf("%d %d\n",moves_next[j+1][i].utility,moves_next[j+1][i+1].utility);
+ }
+ }
+
+ //for(i=0;idata[i].x;
+ //moves_next[0][0].data[i].y=moves->data[i].y;
+ //moves_next[0][0].data[i].weight=moves->data[i].weight;
+ //}
+ //moves_next[0][0].utility=moves->utility;
+ //moves_next[0][0].len=branch;
+ for(i=0;idata[i].x=moves_next[0][0].data[i].x;
+ //moves->data[i].y=moves_next[0][0].data[i].y;
+ //moves->data[i].weight=moves_next[1][i].utility;
+ moves->data[i].weight=utility[1][i];
+ }
+ moves->len=branch;
+
+ return alpha;
+}
+
+int search(Board *b, AIMove *move, Player *player)
+{
+ AIMoves moves;
+ #pragma internal_blockram moves
+ moves.len=0;
+ Board copy;
+ #pragma internal_blockram copy
+ /*index_array index={0};*/
+ #pragma internal_fast index
+ //AIFunc move_func = ai(player->ai)->func;
+
+ /* Player is not configured to search */
+ //if (player->search == SEARCH_NONE)
+ // return;
+
+ /* Moves list does not need to be searched */
+ //if (moves->len <= b->moves_left) {
+ //// if (opt_debug_dfsc)
+ //// g_debug("DFS no choice abort");
+ // return;
+ //}
+
+ ///* Board size changed, cache is invalidated */
+ //if (board_size != cache_size)
+ // cache_moves = NULL;
+ //cache_size = board_size;
+
+ ///* Cache hit, last or same board */
+ //if (player->cache && cache_moves && cache_moves->len &&
+ // cache_search == player->search &&
+ // cache_depth == player->depth &&
+ // cache_player == player &&
+ // cache_func == move_func &&
+ // cache_branch == player->branch) {
+ // if (b->parent && cache_id == b->parent->ac.id) {
+ // aimoves_remove(cache_moves, b->parent->move_x,
+ // b->parent->move_y);
+ // cache_id = b->ac.id;
+ // }
+ // if (cache_id == b->ac.id && cache_moves->len) {
+ // if (cache_moves->len) {
+ // aimoves_copy(cache_moves, moves);
+ // if (opt_debug_dfsc)
+ // g_debug("DFS cache HIT");
+ // return;
+ // }
+ // aimoves_free(cache_moves);
+ // cache_moves = NULL;
+ // }
+ //}
+
+ /* Cache miss */
+ //if (opt_debug_dfsc)
+ // g_debug("DFS cache MISS");
+ //cache_id = b->ac.id;
+ //if (!cache_moves)
+ // cache_moves = aimoves_new();
+ //cache_moves->len = 0;
+ //cache_best = AIW_MIN;
+ //copy = board_new();
+ board_copy(b, ©);
+ //ai_threats(©,&moves,&index);
+
+ //if (player->search == SEARCH_DFS) {
+ df_search(©, &moves, /*&index,*/player, player->depth, 0,
+ PIECE_SEARCHED, AIW_LOSE, AIW_WIN);
+ //printf("FINAL WEIGHTS %d %d \n\n",moves.data[0].weight,moves.data[1].weight);
+ int ret_val;
+ ret_val=aimoves_choose(&moves, move/*,&index*/);
+ if (!ret_val)
+ return 0;
+ else return 1;
+ // if (cache_moves->len)
+ // aimoves_copy(cache_moves, moves);
+ //} else {
+ // board_free(copy);
+ // g_warning("Unsupported search type %d", player->search);
+ // return;
+ //}
+ //board_free(copy);
+
+ ///* Debug DFS search */
+ //if (opt_debug_dfsc)
+ // dfs_cache_dump();
+
+ ///* Save params so we can check if we have a hit later */
+ //cache_player = player;
+ //cache_search = player->search;
+ //cache_depth = player->depth;
+ //cache_branch = player->branch;
+ //cache_func = move_func;
+}
trunk/XILINX/BUILD_SCC_SRCH/synth_src/search_bfs.cpp
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC_SRCH/synth_src/q.cpp
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/synth_src/q.cpp (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/synth_src/q.cpp (revision 17)
@@ -0,0 +1,206 @@
+
+//#ifdef PICO_SYNTH
+//#define Q_ASSERT(_cond, _msg)
+////#include
+//#include "pico.h"
+//#include "q.hpp"
+//#include "./shared.h"
+//using namespace std;
+//#else
+///* not synthesizable */
+//#include
+//#include
+//#include
+//#include
+//
+//static void debug_assert (bool cond, char * msg) {
+// if (!cond) {
+// printf("assert failed: %s\n", msg);
+// assert(0);
+// }
+//}
+//
+//#define Q_ASSERT(_cond, _msg) debug_assert(_cond, _msg)
+//#endif
+//#define max_size 361
+//#define ptr_bw 32
+//FIFO(queue,AIMove);
+//#pragma no_inter_loop_stream_analysis pico_stream_input_queue
+//#pragma no_inter_loop_stream_analysis pico_stream_output_queue
+//#pragma no_inter_task_stream_analysis pico_stream_input_queue
+//#pragma no_inter_task_stream_analysis pico_stream_output_queue
+//
+//#pragma fifo_length queue 361
+////template
+//
+// /* pop front of queue, returning the front data */
+// /* q is corrupted if pop when empty */
+// AIMove q::pop (){
+// /* assert that before pop, queue is not empty (underflow check) */
+// Q_ASSERT((!wrapped && (head < tail)) || (wrapped && (head >= tail)),
+// "queue underflowed");
+// AIMove d = pico_stream_input_queue();
+// //cout <<"pop: "<= tail)),
+// "Queue overflowed") ;
+// //cout <<"push: "<
+//#include "pico.h"
+//using namespace std;
+//#else
+///* not synthesizable */
+//#include
+//#include
+//#include
+//#include
+//
+//static void debug_assert (bool cond, char * msg) {
+// if (!cond) {
+// printf("assert failed: %s\n", msg);
+// assert(0);
+// }
+//}
+//
+//#define Q_ASSERT(_cond, _msg) debug_assert(_cond, _msg)
+//#endif
+//FIFO(queue,AIMove);
+//
+// /* pop front of queue, returning the front data */
+// /* q is corrupted if pop when empty */
+// template
+// tp q::pop () {
+// /* assert that before pop, queue is not empty (underflow check) */
+// Q_ASSERT((!wrapped && (head < tail)) || (wrapped && (head >= tail)),
+// "queue underflowed");
+// tp d = pico_stream_input_queue();
+// cout <<"pop: "<
+// void q::push (tp d) {
+// pico_stream_output_queue(d);
+// if (tail == max_size-1) {
+// tail = 0;
+// wrapped = true;
+// } else {
+// tail = tail + 1;
+// }
+// /* assert that after push, queue is not empty (overflow check) */
+// Q_ASSERT((!wrapped && (head < tail)) || (wrapped && (head >= tail)),
+// "Queue overflowed") ;
+// cout <<"push: "<
+// int q::size () {
+// if (wrapped) {
+// return (max_size - head) + (tail - 0);
+// } else {
+// return tail - head;
+// }
+// }
+//
+//#ifndef PICO_SYNTH
+// /* not synthesizable */
+// std::string to_string () const {
+// std::string s;
+// std::stringstream out;
+//
+// out << "{ ";
+//
+// if (wrapped) {
+// for (int i=head; i
+//std::ostream& operator << (std::ostream &os, const q &f)
+//{
+// os << f.to_string();
+// return os;
+//}
+//#endif
+//q moves_fifo;
+//#pragma internal_blockram moves_fifo
+//#pragma no_inter_loop_memory_analysis moves_fifo.head
+//#pragma no_inter_loop_memory_analysis moves_fifo.tail
+//#pragma no_inter_loop_memory_analysis moves_fifo.wrapped
+//#pragma no_inter_loop_memory_analysis moves_fifo.active
+//#pragma no_inter_loop_memory_analysis moves_fifo
+//q moves_fifo1;
+//#pragma internal_blockram moves_fifo1
+//#pragma no_inter_loop_memory_analysis moves_fifo1.head
+//#pragma no_inter_loop_memory_analysis moves_fifo1.tail
+//#pragma no_inter_loop_memory_analysis moves_fifo1.wrapped
+//#pragma no_inter_loop_memory_analysis moves_fifo1.active
+//#pragma no_inter_loop_memory_analysis moves_fifo1
Index: trunk/XILINX/BUILD_SCC_SRCH/synth_src/q.hpp.tmplt
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/synth_src/q.hpp.tmplt (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/synth_src/q.hpp.tmplt (revision 17)
@@ -0,0 +1,149 @@
+#ifndef Q_H
+#define Q_H
+
+
+//#ifdef PICO_SYNTH
+//#define Q_ASSERT(_cond, _msg)
+#include
+//#include "pico.h"
+using namespace std;
+//#else
+///* not synthesizable */
+//#include
+//#include
+//#include
+//#include
+//
+//static void debug_assert (bool cond, char * msg) {
+// if (!cond) {
+// printf("assert failed: %s\n", msg);
+// assert(0);
+// }
+//}
+//
+//#define Q_ASSERT(_cond, _msg) debug_assert(_cond, _msg)
+//#endif
+//
+//extern FIFO(queue,AIMove);
+template
+//class q {
+// //tp arr[max_size];
+// #pragma fifo_length queue max_size
+// unsigned int head, tail;
+// unsigned char wrapped;
+// #pragma bitsize q.head ptr_bw
+// #pragma bitsize q.tail ptr_bw
+// #pragma bitsize q.wrapped 1
+//
+// public:
+//
+// /* constructor */
+// q () { head = tail = 0; wrapped = false; };
+//
+// // /* returns front data of queue */
+// // tp front () {
+// // return arr[head];
+// // }
+//
+// bool active;
+// /* return true iff queue is empty */
+// bool empty () {
+// return ((head == tail) && !wrapped);
+// }
+//
+// /* return true iff queue is full */
+// bool full () {
+// return ((head == tail) && wrapped);
+// }
+//
+// /* pop front of queue, returning the front data */
+// /* q is corrupted if pop when empty */
+// tp pop (){
+// /* assert that before pop, queue is not empty (underflow check) */
+// Q_ASSERT((!wrapped && (head < tail)) || (wrapped && (head >= tail)),
+// "queue underflowed");
+// tp d = pico_stream_input_queue();
+// cout <<"pop: "<= tail)),
+// "Queue overflowed") ;
+// cout <<"push: "<
+//std::ostream& operator << (std::ostream &os, const q &f)
+//{
+// os << f.to_string();
+// return os;
+//}
+//#endif
+//
+//
+//#undef Q_ASSERT
+////extern q moves_fifo;
+#endif
Index: trunk/XILINX/BUILD_SCC_SRCH/synth_src/connect6_synth.cpp
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/synth_src/connect6_synth.cpp (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/synth_src/connect6_synth.cpp (revision 17)
@@ -0,0 +1,267 @@
+/*
+ connect6.cpp
+ June 9, 2011
+ This file contains the game AI
+ By Kevin Nam
+
+ */
+
+//#include
+//#include
+//
+//#include "util.h"
+//#include "connect6.h"
+//#include
+#include "./shared.h"
+//#ifdef PICO_SYSC_SIM
+#include "pico.h"
+//#endif
+
+// Subtract this many points for moves at the edges.
+#define EDGEPENALTY 5
+
+using namespace std;
+
+/* The cost function simply counts all of the consecutive stones of same colour in
+ every direction from the spot for which the points is being calculated.
+
+Ex:
+
+.DDLL
+.DLDD
+DXDDD
+...D.
+
+Above, X is the spot being calculated.
+The points would be 2 (above) + 2(topright) + 3(right) + 1 (left) = 8.
+It treats opponent's stones and own stones with equal weighting.
+
+Return 0 if the spot y,x is already taken, else return the calculated value
+
+ */
+void move_to_ascii(int x,int y, char *move){
+ if (y >= 10){
+ move[0] = '1';
+ y -= 10;
+ } else {
+ move[0] = '0';
+ }
+ if (y == 0) move[1] = '0';
+ else if (y == 1) move[1] = '1';
+ else if (y == 2) move[1] = '2';
+ else if (y == 3) move[1] = '3';
+ else if (y == 4) move[1] = '4';
+ else if (y == 5) move[1] = '5';
+ else if (y == 6) move[1] = '6';
+ else if (y == 7) move[1] = '7';
+ else if (y == 8) move[1] = '8';
+ else if (y == 9) move[1] = '9';
+
+ // Do same for x.
+ if (x >= 10){
+ move[2] = '1';
+ x -= 10;
+ } else {
+ move[2] = '0';
+ }
+ if (x == 0) move[3] = '0';
+ else if (x == 1) move[3] = '1';
+ else if (x == 2) move[3] = '2';
+ else if (x == 3) move[3] = '3';
+ else if (x == 4) move[3] = '4';
+ else if (x == 5) move[3] = '5';
+ else if (x == 6) move[3] = '6';
+ else if (x == 7) move[3] = '7';
+ else if (x == 8) move[3] = '8';
+ else if (x == 9) move[3] = '9';
+
+}
+
+static int char_to_int(short x){
+ if(x>=48)
+ return x-48;
+ else
+ return 0;
+}
+
+
+/*
+ The AI Function that calls the cost function for every spot on the board.
+ It returns the location with the highest points. In the event of a tie, randomly decide.
+ Input the board and the colour being played.
+ Puts the move (in ASCII chars) inside move[4]. This is from [1 ... 19]
+ Puts the move (in integers) in moveY and moveX. This is from [0 ... 18]
+ */
+//void backup_move(Board *board, AIMoves *moves,AIMove *move){
+////when the threat doesn't return any good move
+////put in a single function to parition and speedup synthesis
+// //#pragma read_write_ports board.data combined 2
+// //#pragma internal_blockram myboard
+// //#pragma no_memory_analysis myboard
+// //#pragma read_write_ports moves.data combined 3
+// //#pragma internal_blockram moves
+// //#pragma no_memory_analysis moves
+// move->x=-1;
+// move->y=-1;
+// if (!aimoves_choose(moves, move)) {
+// // aimoves_free(moves);
+// //moves->len=0;
+// // /*moves = */ai_adjacent(board,moves);
+// aimoves_choose(moves, move);
+// }
+//}
+int id;
+int connect6ai_synth(int firstmove,char movein[8], char colour, char moveout[8]){
+ //#ifdef PICO_SYSC_SIM
+ //id= PICO_initialize_PPA(ai_threats);
+ //PICO_set_task_overlap(id, 2);
+ //#endif
+ #pragma bitsize firstmove 17
+ char moveoutm[8];
+ #pragma internal_blockram moveoutm
+ short x,y,highx = 0;
+ //Board *myboard ;
+ static Board myboard;//={0,0,0,0,0,0,0,0,0,0,0,{{0}}};
+ //#pragma read_write_ports board.data combined 2
+ //#pragma preserve_array myboard.data
+ #pragma internal_blockram myboard
+ //#pragma multi_buffer myboard 2
+ //#pragma no_memory_analysis myboard
+ static unsigned int current_random = 10;
+ AIMove move,move_threat,move_adj;
+ //#pragma internal_blockram move
+ //#pragma no_memory_analysis move
+ if(firstmove==0||firstmove==1) {
+ //my_srandom(1,¤t_random);
+ new_game(&myboard,board_size);
+ }
+ if(firstmove==0) myboard.moves_left=1;
+ else myboard.moves_left=2;
+
+ //-------------------------------------------------------------------------
+ if((firstmove >= 1)){
+ //update the board
+ y = char_to_int(movein[0])*10 + char_to_int(movein[1]) - 1;
+ x = char_to_int(movein[2])*10 + char_to_int(movein[3]) - 1;
+ if(colour==68){//'D')
+ //myboard[y][x] = (char)2;//76;//'L';
+ place_piece_type(&myboard,x,y,PIECE_WHITE);
+ myboard.turn=PIECE_BLACK;
+ }else{
+ //board[y][x] = (char)1;//68;//'D';
+ place_piece_type(&myboard,x,y,PIECE_BLACK);
+ myboard.turn=PIECE_WHITE;
+ }
+ }
+ if((firstmove >=3)){
+ //update the board
+ y = char_to_int(movein[4])*10 + char_to_int(movein[5]) - 1;
+ x = char_to_int(movein[6])*10 + char_to_int(movein[7]) - 1;
+ if(colour==68){//'D')
+ //board[y][x] = (char)2;//76;//'L';
+ place_piece_type(&myboard,x,y,PIECE_WHITE);
+ myboard.turn=PIECE_BLACK;
+ }else{
+ //board[y][x] = (char)1;//68;//'D';
+ place_piece_type(&myboard,x,y,PIECE_BLACK);
+ myboard.turn=PIECE_WHITE;
+ }
+ }
+ int i;
+ #pragma bitsize i 6
+
+ //#pragma num_iterations(1,2,2)
+ //#pragma unroll
+ Player player;
+ player.depth=2;
+ player.branch=2;
+ for(i=myboard.moves_left;i>0;i--){
+ //aimoves_free(&moves);
+ move.x=-1;
+ move.y=-1;
+
+ if (!search(&myboard,&move_threat,&player)){
+ //aimoves_free(&moves);
+ //moves.len=0;
+ ai_adjacent(&myboard,&move_adj,current_random);
+ move.x=move_adj.x;
+ move.y=move_adj.y;
+ }else{
+ move.x=move_threat.x;
+ move.y=move_threat.y;
+ }
+
+ //backup_move(&myboard,&moves,&move);
+ //printf("DEBUG1:%d ",move.x);
+ // Modify the board based on current move.
+ place_piece_type(&myboard,move.x,move.y,myboard.turn);
+ /// Convert the int coordinates to corresponding ASCII chars
+
+ //if(firstmove==0)
+ //move_to_ascii(move.x+1,move.y+1,&moveout[0]);
+ //else if(myboard.moves_left==2)
+ //move_to_ascii(move.x+1,move.y+1,&moveout[0]);
+ //else
+ //move_to_ascii(move.x+1,move.y+1,&moveout[4]);
+ if(firstmove==0)
+ move_to_ascii(move.x+1,move.y+1,&moveoutm[0]);
+ else
+ move_to_ascii(move.x+1,move.y+1,&moveoutm[8-4*i]);
+ myboard.moves_left--;
+ }
+ if(firstmove==0){
+ #pragma unroll
+ for(i=0;i<4;i++)
+ moveout[i]=moveoutm[i];
+ }else{
+ #pragma unroll
+ for(i=0;i<8;i++)
+ moveout[i]=moveoutm[i];
+ }
+ //if(firstmove==0){
+ //moveout[0]=moveoutm[0];
+ //moveout[1]=moveoutm[1];
+ //moveout[2]=moveoutm[2];
+ //moveout[3]=moveoutm[3];
+ //}else{
+ //moveout[0]=moveoutm[0];
+ //moveout[1]=moveoutm[1];
+ //moveout[2]=moveoutm[2];
+ //moveout[3]=moveoutm[3];
+ //moveout[4]=moveoutm[4];
+ //moveout[5]=moveoutm[5];
+ //moveout[6]=moveoutm[6];
+ //moveout[7]=moveoutm[7];
+ //}
+
+ ////-------------------------------------------------------------------------
+ //if(firstmove>=1){
+ ////aimoves_free(&moves);
+ //moves.len=0;
+ //myboard.moves_left=1;
+ ///*moves=*/ai_threats(&myboard,&moves);
+ // move.x=-1;
+ // move.y=-1;
+ // if (!aimoves_choose(&moves, &move)) {
+ // //aimoves_free(&moves);
+ // moves.len=0;
+ // /*moves = */ai_adjacent(&myboard,&moves);
+ // aimoves_choose(&moves, &move);
+ // }
+ // //backup_move(&myboard,&moves,&move);
+ ////printf("DEBUG2%d\n",move.x);
+ //// Modify the board based on current move.
+ //place_piece_type(&myboard,move.x,move.y,myboard.turn);
+ //
+ // /// Convert the int coordinates to corresponding ASCII chars
+ //move_to_ascii(move.x+1,move.y+1,&moveout[4]);
+ //}
+ //#ifdef PICO_SYSC_SIM
+ //PICO_sync_task(id, 1);
+ //PICO_finalize_PPA(id);
+ //#endif
+ return 0;
+}
+
+
+
Index: trunk/XILINX/BUILD_SCC_SRCH/synth_src/connect6_synth.c
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/synth_src/connect6_synth.c (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/synth_src/connect6_synth.c (revision 17)
@@ -0,0 +1,145 @@
+/*
+ connect6.cpp
+ June 9, 2011
+ This file contains the game AI
+ By Kevin Nam
+
+ */
+
+//#include
+//#include
+//
+//#include "util.h"
+//#include "connect6.h"
+#include "./shared.h"
+
+// Subtract this many points for moves at the edges.
+#define EDGEPENALTY 5
+
+
+/* The cost function simply counts all of the consecutive stones of same colour in
+ every direction from the spot for which the points is being calculated.
+
+Ex:
+
+.DDLL
+.DLDD
+DXDDD
+...D.
+
+Above, X is the spot being calculated.
+The points would be 2 (above) + 2(topright) + 3(right) + 1 (left) = 8.
+It treats opponent's stones and own stones with equal weighting.
+
+Return 0 if the spot y,x is already taken, else return the calculated value
+
+ */
+void move_to_ascii(int x,int y, char *move){
+ if (y >= 10){
+ move[0] = '1';
+ y -= 10;
+ } else {
+ move[0] = '0';
+ }
+ if (y == 0) move[1] = '0';
+ else if (y == 1) move[1] = '1';
+ else if (y == 2) move[1] = '2';
+ else if (y == 3) move[1] = '3';
+ else if (y == 4) move[1] = '4';
+ else if (y == 5) move[1] = '5';
+ else if (y == 6) move[1] = '6';
+ else if (y == 7) move[1] = '7';
+ else if (y == 8) move[1] = '8';
+ else if (y == 9) move[1] = '9';
+
+ // Do same for x.
+ if (x >= 10){
+ move[2] = '1';
+ x -= 10;
+ } else {
+ move[2] = '0';
+ }
+ if (x == 0) move[3] = '0';
+ else if (x == 1) move[3] = '1';
+ else if (x == 2) move[3] = '2';
+ else if (x == 3) move[3] = '3';
+ else if (x == 4) move[3] = '4';
+ else if (x == 5) move[3] = '5';
+ else if (x == 6) move[3] = '6';
+ else if (x == 7) move[3] = '7';
+ else if (x == 8) move[3] = '8';
+ else if (x == 9) move[3] = '9';
+
+}
+
+static int char_to_int(short x){
+ if(x>=48)
+ return x-48;
+ else
+ return 0;
+}
+
+
+/*
+ The AI Function that calls the cost function for every spot on the board.
+ It returns the location with the highest points. In the event of a tie, randomly decide.
+ Input the board and the colour being played.
+ Puts the move (in ASCII chars) inside move[4]. This is from [1 ... 19]
+ Puts the move (in integers) in moveY and moveX. This is from [0 ... 18]
+ */
+int connect6ai_synth(int firstmove,char movein[8], char colour, char moveout[8]){
+ #pragma bitsize firstmove 17
+ short x,y,highx = 0;
+ Board *myboard ;
+ AIMoves *moves;
+ //-------------------------------------------------------------------------
+ if((firstmove >= 1)){
+ //update the board
+ y = char_to_int(movein[0])*10 + char_to_int(movein[1]) - 1;
+ x = char_to_int(movein[2])*10 + char_to_int(movein[3]) - 1;
+ if(colour==68){//'D')
+ //myboard[y][x] = (char)2;//76;//'L';
+ place_piece_type(myboard,x,y,PIECE_WHITE);
+ myboard->turn=PIECE_BLACK;
+ }else{
+ //myboard[y][x] = (char)1;//68;//'D';
+ place_piece_type(myboard,x,y,PIECE_BLACK);
+ myboard->turn=PIECE_WHITE;
+ }
+ }
+ if((firstmove >=3)){
+ //update the board
+ y = char_to_int(movein[4])*10 + char_to_int(movein[5]) - 1;
+ x = char_to_int(movein[6])*10 + char_to_int(movein[7]) - 1;
+ if(colour==68){//'D')
+ //myboard[y][x] = (char)2;//76;//'L';
+ place_piece_type(myboard,x,y,PIECE_WHITE);
+ myboard->turn=PIECE_BLACK;
+ }else{
+ //myboard[y][x] = (char)1;//68;//'D';
+ place_piece_type(myboard,x,y,PIECE_BLACK);
+ myboard->turn=PIECE_WHITE;
+ }
+ }
+ moves=ai_threats(myboard);
+ // Modify the myboard based on current move.
+ place_piece_type(myboard,moves->data[1].x,moves->data[1].y,myboard->turn);
+ /// Convert the int coordinates to corresponding ASCII chars
+
+ move_to_ascii(moves->data[1].x+1,moves->data[1].y+1,moveout);
+
+
+ //-------------------------------------------------------------------------
+ if(firstmove>=1){
+ moves=ai_threats(myboard);
+ // Modify the myboard based on current move.
+ place_piece_type(myboard,moves->data[1].x,moves->data[1].y,myboard->turn);
+
+ /// Convert the int coordinates to corresponding ASCII chars
+ move_to_ascii(moves->data[1].x+1,moves->data[1].y+1,&moveout[4]);
+ }
+ return 0;
+}
+
+
+
Index: trunk/XILINX/BUILD_SCC_SRCH/synth_src/q.hpp
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/synth_src/q.hpp (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/synth_src/q.hpp (revision 17)
@@ -0,0 +1,110 @@
+#ifndef Q_H
+#define Q_H
+
+#include "shared.h"
+#define max_size 361
+#define ptr_bw 32
+class q {
+ //tp arr[max_size];
+ unsigned int head, tail;
+ unsigned char wrapped;
+ #pragma bitsize q.head ptr_bw
+ #pragma bitsize q.tail ptr_bw
+ #pragma bitsize q.wrapped 1
+
+ public:
+
+ /* constructor */
+ q () { head = tail = 0; wrapped = false; };
+
+ // /* returns front data of queue */
+ // tp front () {
+ // return arr[head];
+ // }
+
+ bool active;
+ /* return true iff queue is empty */
+ bool empty () {
+ return ((head == tail) && !wrapped);
+ }
+
+ /* return true iff queue is full */
+ bool full () {
+ return ((head == tail) && wrapped);
+ }
+ void reset(){
+ head=tail=0;wrapped=false;active=1;
+ }
+
+ /* pop front of queue, returning the front data */
+ /* q is corrupted if pop when empty */
+ AIMove pop ();
+
+ /* push data into back of queue */
+ /* q is corrupted if push when full */
+ void push (AIMove d);
+
+ /* return current size of the queue */
+ int size ();
+};
+//extern q moves_fifo;
+//#pragma no_inter_loop_memory_analysis moves_fifo.head
+//#pragma no_inter_loop_memory_analysis moves_fifo.tail
+//#pragma no_inter_loop_memory_analysis moves_fifo.wrapped
+//#pragma no_inter_loop_memory_analysis moves_fifo.active
+// #pragma no_inter_loop_memory_analysis moves_fifo
+extern q moves_fifo1;
+#pragma no_inter_loop_memory_analysis moves_fifo1.head
+#pragma no_inter_loop_memory_analysis moves_fifo1.tail
+#pragma no_inter_loop_memory_analysis moves_fifo1.wrapped
+#pragma no_inter_loop_memory_analysis moves_fifo1.active
+ #pragma no_inter_loop_memory_analysis moves_fifo1
+//#ifndef PICO_SYNTH
+// /* not synthesizable */
+// std::string to_string () const {
+// std::string s;
+// std::stringstream out;
+//
+// out << "{ ";
+//
+// if (wrapped) {
+// for (int i=head; i
+//std::ostream& operator << (std::ostream &os, const q &f)
+//{
+// os << f.to_string();
+// return os;
+//}
+//#endif
+//
+//
+//#undef Q_ASSERT
+////extern q moves_fifo;
+#endif
Index: trunk/XILINX/BUILD_SCC_SRCH/synth_src/search.cpp
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/synth_src/search.cpp (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/synth_src/search.cpp (revision 17)
@@ -0,0 +1,238 @@
+
+/*
+
+connectk -- UMN CSci 5512W project
+
+*/
+
+//#include "config.h"
+//#include
+//#include
+//#include
+#include
+#include "./shared.h"
+#include "pico.h"
+//#include "../connectk.h"
+
+/* Variables required to check for cache hits */
+//static int cache_id = -1, cache_depth = -1, cache_branch = -1;
+//static SEARCH cache_search = -1;
+//static AIMoves *cache_moves = NULL;
+//static AIWEIGHT cache_best;
+//static Player *cache_player;
+//static AIFunc cache_func;
+//static BCOORD cache_size;
+
+int ai_stop=0;
+static AIWEIGHT df_search(Board *b, AIMoves *moves,unsigned int *index, Player *player,
+ int depth, int cache_index,
+ PIECE searched, AIWEIGHT alpha, AIWEIGHT beta)
+/* Depth is in _moves_ */
+{
+ int i, j;
+
+ /* Halt and depth abort */
+ if (ai_stop || depth < 1){
+ printf("dpeth %d %d\n",depth,moves->utility);
+ return moves->utility;
+ }
+ /* Alpha-beta sanity check */
+ if (alpha >= beta) {
+ //g_warning("DFS alpha-beta failed sanity check");
+ //printf("DFS alpha-beta failed sanity check\n");
+ return moves->utility;
+ }
+
+ /* Search only the top moves beyond the minimum */
+ //aimoves_sort(moves);
+ if (moves->len > player->branch) {
+ // for (i = player->branch; i < moves->len; i++)
+ // if (moves->data[i].weight != moves->data[0].weight)
+ // break;
+ // moves->len = i;
+ moves->len=player->branch;
+ }
+
+ /* No moves left -- its a draw */
+ if (moves->len < 1)
+ return AIW_DRAW;
+
+ /* Search each move available in depth first order */
+ for (i = 0; i < moves->len; i++) {
+ Board b_next;
+ AIMove *aim = moves->data + i;
+ AIMoves moves_next;
+
+ /* Did we get a bad move? */
+ if (!piece_empty(piece_at(b, aim->x, aim->y))) {
+ //g_warning("DFS utility function suggested a bad move "
+ //"(%s)", bcoords_to_string(aim->x, aim->y));
+ //printf("bad move\n");
+ continue;
+ }
+
+ /* Already searched here? */
+ if (piece_at(b, aim->x, aim->y) == searched)
+ continue;
+ place_piece_type(b, aim->x, aim->y, searched);
+
+ //b_next = board_new();
+ board_copy(b, &b_next);
+ place_piece(&b_next, aim->x, aim->y);
+
+ /* Did we win? */
+ if (check_win(&b_next, aim->x, aim->y))
+ aim->weight = AIW_WIN;
+
+ /* Otherwise, search deeper */
+ else {
+ int next_ci = cache_index + 1;
+ AIWEIGHT next_alpha = alpha, next_beta = beta;
+ //AIFunc func;
+
+ b_next.moves_left--;
+
+ /* Player has changed */
+ if (b_next.moves_left <= 0) {
+ b_next.moves_left = place_p;
+ b_next.turn = other_player(b->turn);
+ next_ci += place_p;
+ searched++;
+ next_alpha = -beta;
+ next_beta = -alpha;
+ }
+
+ //func = ai(player->ai)->func;
+ //if (!func) {
+ // g_warning("DFS player has no AI function");
+ // return moves->utility;
+ //}
+ //moves_next = func(b_next);
+ //printf("depth %d branch %d player %d moves_left %d alpha %d MOVE %d %d \n",depth,i,b_next.turn,b_next.moves_left,alpha,aim->y+1,aim->x+1);
+ ai_threats(&b_next,&moves_next,index);
+
+ aim->weight = df_search(&b_next, &moves_next, index,player,
+ depth - 1, next_ci, searched,
+ next_alpha, next_beta);
+ //aimoves_free(moves_next);
+ if (b_next.turn != b->turn)
+ aim->weight = -aim->weight;
+ }
+
+ /* Debug search */
+ //if (opt_debug_dfsc) {
+ // for(j = MAX_DEPTH - depth; j > 0; j--)
+ // //g_print("-");
+ // //g_print("> d=%d, %s, u=%d, a=%d, b=%d %s\n",
+ // // depth, bcoords_to_string(aim->x, aim->y),
+ // // aim->weight, alpha, beta,
+ // // piece_to_string(b->turn));
+ //}
+
+ //board_free(b_next);
+ if (aim->weight > alpha) {
+ alpha = aim->weight;
+ //cache_set(cache_index, aim);
+
+ /* Victory abort */
+ if (alpha >= AIW_WIN)
+ return AIW_WIN;
+
+ /* Alpha-beta pruning */
+ if (alpha >= beta)
+ return alpha;
+ }
+ }
+
+ return alpha;
+}
+
+int search(const Board *b, AIMove *move, Player *player)
+{
+ AIMoves moves;
+ Board copy;
+ #pragma internal_blockram copy
+ unsigned int index[361]={0};
+ //AIFunc move_func = ai(player->ai)->func;
+
+ /* Player is not configured to search */
+ //if (player->search == SEARCH_NONE)
+ // return;
+
+ /* Moves list does not need to be searched */
+ //if (moves->len <= b->moves_left) {
+ //// if (opt_debug_dfsc)
+ //// g_debug("DFS no choice abort");
+ // return;
+ //}
+
+ ///* Board size changed, cache is invalidated */
+ //if (board_size != cache_size)
+ // cache_moves = NULL;
+ //cache_size = board_size;
+
+ ///* Cache hit, last or same board */
+ //if (player->cache && cache_moves && cache_moves->len &&
+ // cache_search == player->search &&
+ // cache_depth == player->depth &&
+ // cache_player == player &&
+ // cache_func == move_func &&
+ // cache_branch == player->branch) {
+ // if (b->parent && cache_id == b->parent->ac.id) {
+ // aimoves_remove(cache_moves, b->parent->move_x,
+ // b->parent->move_y);
+ // cache_id = b->ac.id;
+ // }
+ // if (cache_id == b->ac.id && cache_moves->len) {
+ // if (cache_moves->len) {
+ // aimoves_copy(cache_moves, moves);
+ // if (opt_debug_dfsc)
+ // g_debug("DFS cache HIT");
+ // return;
+ // }
+ // aimoves_free(cache_moves);
+ // cache_moves = NULL;
+ // }
+ //}
+
+ /* Cache miss */
+ //if (opt_debug_dfsc)
+ // g_debug("DFS cache MISS");
+ //cache_id = b->ac.id;
+ //if (!cache_moves)
+ // cache_moves = aimoves_new();
+ //cache_moves->len = 0;
+ //cache_best = AIW_MIN;
+ //copy = board_new();
+ board_copy(b, ©);
+ ai_threats(©,&moves,&index[0]);
+
+ //if (player->search == SEARCH_DFS) {
+ df_search(©, &moves, &index[0],player, player->depth, 0,
+ PIECE_SEARCHED, AIW_LOSE, AIW_WIN);
+ printf("%d %d \n",moves.data[0].weight,moves.data[1].weight);
+ int ret_val;
+ ret_val=aimoves_choose(&moves, move,&index[0]);
+ if (!ret_val)
+ return 0;
+ else return 1;
+ // if (cache_moves->len)
+ // aimoves_copy(cache_moves, moves);
+ //} else {
+ // board_free(copy);
+ // g_warning("Unsupported search type %d", player->search);
+ // return;
+ //}
+ //board_free(copy);
+
+ ///* Debug DFS search */
+ //if (opt_debug_dfsc)
+ // dfs_cache_dump();
+
+ ///* Save params so we can check if we have a hit later */
+ //cache_player = player;
+ //cache_search = player->search;
+ //cache_depth = player->depth;
+ //cache_branch = player->branch;
+ //cache_func = move_func;
+}
trunk/XILINX/BUILD_SCC_SRCH/synth_src/search.cpp
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC_SRCH/synth_src/connect6_synth.h
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/synth_src/connect6_synth.h (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/synth_src/connect6_synth.h (revision 17)
@@ -0,0 +1,5 @@
+#ifndef _CONNECT6_H_SYNTH
+#define _CONNECT6_H_SYNTH
+
+int connect6ai_synth(int firstmove,char movein[8], char colour, char moveout[8]);
+#endif
Index: trunk/XILINX/BUILD_SCC_SRCH/synth_src/threats.cpp
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/synth_src/threats.cpp (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/synth_src/threats.cpp (revision 17)
@@ -0,0 +1,825 @@
+
+/*
+
+connectk -- a program to play the connect-k family of games
+Copyright (C) 2007 Michael Levin
+
+This program is free software; you can redistribute it and/or
+modify it under the terms of the GNU General Public License
+as published by the Free Software Foundation; either version 2
+of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+//#include "config.h"
+//#include
+//#include h>
+//#include
+#include "./shared.h"
+//#include "./q.hpp"
+#include "pico.h"
+//#include
+
+/* Bits per threat level */
+#define BITS_PER_THREAT 6
+
+//FIFO(x,int);
+//#pragma fifo_length x 24
+//#pragma no_inter_loop_stream_analysis pico_stream_input_x
+//#pragma no_inter_loop_stream_analysis pico_stream_output_x
+//#pragma no_inter_task_stream_analysis pico_stream_input_x
+//#pragma no_inter_task_stream_analysis pico_stream_output_x
+/*--------------------------------------------------------------------*/
+#ifdef PICO_SYNTH
+#define Q_ASSERT(_cond, _msg)
+//#include
+//#include "pico.h"
+//#include "q.hpp"
+//#include "./shared.h"
+using namespace std;
+#else
+/* not synthesizable */
+#include
+#include
+#include
+#include
+
+static void debug_assert (bool cond, char * msg) {
+ if (!cond) {
+ printf("assert failed: %s\n", msg);
+ assert(0);
+ }
+}
+
+#define Q_ASSERT(_cond, _msg) debug_assert(_cond, _msg)
+#endif
+#define max_size 361
+#define ptr_bw 32
+//FIFO(queue,AIMove);
+//#pragma no_inter_loop_stream_analysis pico_stream_input_queue
+//#pragma no_inter_loop_stream_analysis pico_stream_output_queue
+//#pragma no_inter_task_stream_analysis pico_stream_input_queue
+//#pragma no_inter_task_stream_analysis pico_stream_output_queue
+
+//FIFO(queue,AIMove);
+//FIFO_INTERFACE(queue,AIMove);
+//#pragma fifo_length pico_stream_input_queue 800
+//#pragma fifo_length pico_stream_output_queue 800
+//#pragma read_write_port queue separate
+//#pragma bandwidth pico_stream_input_queue 1
+//#pragma bandwidth pico_stream_output_queue 1
+//////template
+////
+//// /* pop front of queue, returning the front data */
+//// /* q is corrupted if pop when empty */
+//// AIMove q::pop (){
+//// /* assert that before pop, queue is not empty (underflow check) */
+//// Q_ASSERT((!wrapped && (head < tail)) || (wrapped && (head >= tail)),
+//// "queue underflowed");
+//// AIMove d = pico_stream_input_queue();
+//// //cout <<"pop: "<= tail)),
+//// "Queue overflowed") ;
+//// //cout <<"push: "<1) pico_stream_input_x();
+//// //for (i=0;i<10;i++) {if(!moves_fifo1.empty()) moves_fifo1.pop(); }
+//// AIMove m;
+//// while(1) {
+//// if(ready>1) m=pico_stream_input_queue();
+//// if(m.weight==-1) break;
+//// }
+////}
+////q moves_fifo1;
+
+static AIWEIGHT threat_bits(int threat, PIECE type, Board *b)
+/* Bit pack the threat value */
+{
+ if (threat < 1)
+ return 0;
+
+ /* No extra value for building sequences over k - p unless it is
+ enough to win */
+ if (b->turn == type && connect_k - threat <= b->moves_left)
+ threat = connect_k - place_p + 1;
+ else if (threat >= connect_k - place_p)
+ threat = connect_k - place_p - (type == b->turn);
+
+ return 1 << ((threat - 1) * BITS_PER_THREAT);
+}
+
+static void threat_mark(int i, int threat, PIECE type,Board *b,Line *line)
+{
+ int j, index = 0;
+
+ if (threat <= 0)
+ return;
+
+ /* No extra value for building sequences over k - p unless it is
+ enough to win */
+ if (b->turn == type && connect_k - threat <= b->moves_left)
+ threat = connect_k - place_p + 1;
+ else if (threat >= connect_k - place_p)
+ threat = connect_k - place_p - (type == b->turn);
+
+ /* Do not mark if this threat is dominated by a preceeding threat;
+ Likewise supress any smaller threats */
+ for (j = i; j >= 0 && j > i - connect_k; j--)
+ if (line[j].threat[0] > threat)
+ return;
+ else if (line[j].threat[0] < threat) {
+ line[j].threat[0] = 0;
+ line[j].threat[1] = 0;
+ }
+
+ /* Store up to two threats per tile in the line */
+ if (line[i].threat[index])
+ index++;
+ line[i].threat[index] = threat;
+ line[i].turn[index] = type;
+}
+
+int threat_window(int x, int y, int dx, int dy,
+ PIECE *ptype, int *pdouble,Board *b)
+{
+ int minimum, maximum, count = 0;
+ PIECE p, type = PIECE_NONE;
+
+ /* Check if this tile is empty */
+ p = piece_at(b, x, y);
+ if (!piece_empty(p))
+ return 0;
+
+ /* Push forward the maximum and find the window type */
+ #pragma unroll
+ #pragma num_iterations(1,3,6)
+ for (maximum = 1; maximum < connect_k; maximum++) {
+ p = piece_at(b, x + dx * maximum, y + dy * maximum);
+ if (p == PIECE_ERROR)
+ break;
+ if (!piece_empty(p)) {
+ if (type == PIECE_NONE)
+ type = p;
+ else if (type != p)
+ break;
+ count++;
+ }
+ }
+ maximum--;
+
+ /* Try to push the entire window back */
+ #pragma unroll
+ #pragma num_iterations(1,3,6)
+ for (minimum = -1; minimum > -connect_k; minimum--) {
+ p = piece_at(b, x + dx * minimum, y + dy * minimum);
+ if (p == PIECE_ERROR || piece_empty(p))
+ break;
+ if (type == PIECE_NONE)
+ type = p;
+ else if (type != p)
+ break;
+ if (maximum - minimum > connect_k - 1) {
+ p = piece_at(b, x + dx * maximum, y + dy * maximum);
+ if (p == type)
+ count--;
+ maximum--;
+ }
+ count++;
+ }
+ minimum++;
+
+ /* Push back minimum if we haven't formed a complete window, this window
+ can't be a double */
+ if (maximum - minimum < connect_k - 1) {
+ //#pragma unroll
+ #pragma num_iterations(1,3,6)
+ for (minimum--; minimum > maximum - connect_k; minimum--) {
+ p = piece_at(b, x + dx * minimum, y + dy * minimum);
+ if (p == PIECE_ERROR)
+ break;
+ if (!piece_empty(p)) {
+ if (type != p)
+ break;
+ if (type == PIECE_NONE)
+ type = p;
+ count++;
+ }
+ }
+ *pdouble = 0;
+ minimum++;
+ }
+
+ *ptype = type;
+ if (maximum - minimum >= connect_k - 1)
+ return count;
+ return 0;
+}
+
+/*static*/ AIWEIGHT threat_line(int x, int y, int dx, int dy,Board *b,Board *bwrite,int k,int loop_bound)
+{
+
+ //#pragma read_write_ports threat_counts.data combined 2
+ //#pragma internal_blockram threat_counts
+ //#pragma no_memory_analysis threat_counts
+
+ //#pragma read_write_ports b.data combined 2
+ //#pragma read_write_ports b.data separate 1 readonly 2 writeonly
+ //#pragma no_memory_analysis b
+ /* This is the line of threats currently being processed */
+ Line line[board_size]={{1},{2}};
+ #pragma internal_fast line
+ //#pragma no_memory_analysis line
+ /* Running tally of threats for both players */
+ //static int threat_counts[MAX_CONNECT_K + 1][2];
+ threat_count_array threat_counts={{0}};
+ #pragma internal_fast threat_counts
+ //#pragma read_write_ports threat_counts.data combined 2
+ //#pragma no_memory_analysis threat_counts
+ //if (k==1) board_copy(b, bwrite);
+ int i;
+ AIWEIGHT weight = 0;
+ ///* Clear threat tallys */
+ //for (i = 0; i < connect_k; i++) {
+ // threat_counts.data[i][0] = 1;
+ // threat_counts.data[i][1] = 1;
+ //}
+
+ /* Mark the maximum threat for each */
+ for (i = 0; x >= 0 && x < board_size && y >= 0 && y < board_size; i++) {
+ int count[2], tmp, double_threat = 1;
+ PIECE type[2];
+
+ count[0] = threat_window(x, y, dx, dy, type, &double_threat,bwrite);
+ count[1] = threat_window(x, y, -dx, -dy, type + 1,
+ &double_threat,bwrite);
+ if (count[1] > count[0]) {
+ tmp = count[1];
+ count[1] = count[0];
+ count[0] = tmp;
+ tmp = type[1];
+ type[1] = type[0];
+ type[0] = tmp;
+ }
+ line[i].threat[0] = 0;
+ line[i].threat[1] = 0;
+ threat_mark(i, count[0], type[0],bwrite,&line[0]);
+ if (double_threat)
+ threat_mark(i, count[1], type[1],bwrite,&line[0]);
+ x += dx;
+ y += dy;
+ }
+
+ /* Commit stored line values to the board */
+ x -= dx;
+ y -= dy;
+ for (i--; x >= 0 && x < board_size && y >= 0 && y < board_size; i--) {
+ AIWEIGHT bits[2];
+ PIECE p;
+
+ bits[0] = threat_bits(line[i].threat[0], line[i].turn[0],bwrite);
+ bits[1] = threat_bits(line[i].threat[1], line[i].turn[1],bwrite);
+ p = piece_at(bwrite, x, y);
+ if (piece_empty(p) && line[i].threat[0]) {
+ threat_counts.data[line[i].threat[0]][line[i].turn[0] - 1]++;
+ if (line[i].threat[1])
+ threat_counts.data[line[i].threat[1]]
+ [line[i].turn[1] - 1]++;
+ if (p >= PIECE_THREAT0)
+ place_threat(bwrite, x, y, p - PIECE_THREAT0 +
+ bits[0] + bits[1]);
+ else
+ place_threat(bwrite, x, y, bits[0] + bits[1]);
+ }
+ if (bwrite->turn != line[i].turn[0])
+ bits[0] = -bits[0];
+ if (bwrite->turn != line[i].turn[1])
+ bits[1] = -bits[1];
+ weight += bits[0] + bits[1];
+ x -= dx;
+ y -= dy;
+ }
+ return weight;
+}
+
+//FIFO(queue,AIMove);
+////FIFO_INTERFACE(queue,AIMove);
+//#pragma fifo_length pico_stream_input_queue 800
+//#pragma fifo_length pico_stream_output_queue 800
+//#pragma bandwidth pico_stream_input_queue 1
+//#pragma bandwidth pico_stream_output_queue 1
+/*AIMoves*/int ai_threats(Board board[2][16],int depth,int branch,AIMoves moves[2][16]/*,index_array *index*/)
+{
+ //#pragma read_write_ports board.data combined 2
+ //#pragma internal_blockram board
+ //#pragma no_memory_analysis board
+
+ //#pragma internal_blockram move
+ //#pragma no_memory_analysis move
+ index_array index={0};
+ #pragma internal_fast index
+
+ /////////* All threat functions work on this board */
+ /*static*/ Board b;//={0,0,0,0,0,0,0,0,0,0,0,{{0}}} ;//= NULL;
+ //#pragma read_write_ports b.data combined 2
+ #pragma internal_blockram b
+ //#pragma multi_buffer b 2
+ //#pragma read_write_ports b.data separate 1 readonly 2 writeonly
+ //#pragma no_memory_analysis b
+ /*static*/ Board bwrite;//={0,0,0,0,0,0,0,0,0,0,0,{{0}}} ;//= NULL;
+ //#pragma read_write_ports b.data combined 2
+ #pragma internal_blockram bwrite
+ //#pragma multi_buffer bwrite 22
+ //#pragma no_memory_analysis b
+ ///*static*/ AIMoves moves;//={0,0,0,{{0,0,0}}};
+ //#pragma read_write_ports moves.data combined 3
+ //#pragma internal_blockram moves
+ //#pragma no_memory_analysis moves
+
+ moves[depth][branch].len=0;
+ //AIMoves moves;
+ AIWEIGHT u_sum = 0;
+ int i;
+
+ //b = board_new();
+ //Board b;
+ board_copy(&board[depth][branch], &b);
+
+ /* Clear threat tallys */
+ //for (i = 0; i < connect_k; i++) {
+ // threat_counts.data[i][0] = 0;
+ // threat_counts.data[i][1] = 0;
+ //}
+/*---------------------------------------------------------------------------*/
+ // /* Horizontal lines */
+ // for (i = 0; i < board_size; i++)
+ // u_sum += threat_line(0, i, 1, 0,&b);
+
+ // /* Vertical lines */
+ // for (i = 0; i < board_size; i++)
+ // u_sum += threat_line(i, 0, 0, 1,&b);
+
+ // /* SE diagonals */
+ // for (i = 0; i < board_size - connect_k + 1; i++)
+ // u_sum += threat_line(i, 0, 1, 1,&b);
+ // for (i = 1; i < board_size - connect_k + 1; i++)
+ // u_sum += threat_line(0, i, 1, 1,&b);
+
+ // /* SW diagonals */
+ // for (i = connect_k - 1; i < board_size; i++)
+ // u_sum += threat_line(i, 0, -1, 1,&b);
+ // for (i = 1; i < board_size - connect_k + 1; i++)
+ // u_sum += threat_line(board_size - 1, i, -1, 1,&b);
+/*---------------------------------------------------------------------------*/
+//rewritten for hardware
+/*---------------------------------------------------------------------------*/
+ //int id= PICO_initialize_PPA(threat_line);
+ //PICO_set_task_overlap(id, 2);
+ int j;
+ int arg1,arg2,arg3,arg4,loop_bound,loop_begin;
+ int k=0;
+ for(j=0;j<6;j++){
+ switch(j){
+ case 0:
+ {
+ loop_begin=0;
+ loop_bound=board_size;
+ break;
+ }
+ case 1:
+ {
+ loop_begin=0;
+ loop_bound=board_size;
+ break;
+ }
+ case 2:
+ {
+ loop_begin=0;
+ loop_bound=board_size-connect_k+1;
+ break;
+ }
+ case 3:
+ {
+ loop_begin=1;
+ loop_bound=board_size-connect_k+1;
+ break;
+ }
+ case 4:
+ {
+ loop_begin=connect_k-1;
+ loop_bound=board_size;
+ break;
+ }
+ case 5:
+ {
+ loop_begin=1;
+ loop_bound=board_size-connect_k+1;
+ break;
+ }
+ default:{
+ break;
+ }
+ }
+ for (i = loop_begin; i < loop_bound; i++){
+ k++;
+ switch(j){
+ case 0:
+ {
+ arg1=0;
+ arg2=i;
+ arg3=1;
+ arg4=0;
+ break;
+ }
+ case 1:
+ {
+ arg1=i;
+ arg2=0;
+ arg3=0;
+ arg4=1;
+ break;
+ }
+ case 2:
+ {
+ arg1=i;
+ arg2=0;
+ arg3=1;
+ arg4=1;
+ break;
+ }
+ case 3:
+ {
+ arg1=0;
+ arg2=i;
+ arg3=1;
+ arg4=1;
+ break;
+ }
+ case 4:
+ {
+ arg1=i;
+ arg2=0;
+ arg3=-1;
+ arg4=1;
+ break;
+ }
+ case 5:
+ {
+ arg1=board_size-1;
+ arg2=i;
+ arg3=-1;
+ arg4=1;
+ break;
+ }
+ default:{
+ break;
+ }
+ }
+
+
+ if (k==1) board_copy(&b, &bwrite);
+ u_sum += threat_line(arg1, arg2, arg3, arg4,&b,&bwrite,k,loop_bound);
+ }
+ }
+ //PICO_sync_task(id, 1);
+ //PICO_finalize_PPA(id);
+/*---------------------------------------------------------------------------*/
+ //board_copy(&b,&b_marks);
+ //unsigned int index[max_size]={0};
+ //#pragma bitsize index 9
+ //#pragma internal_fast index
+ AIMoves moves1;
+ moves1.len=0;
+ #pragma internal_blockram moves1
+ /*moves = */ ai_marks(&bwrite, PIECE_THREAT(1),&moves[depth][branch]);
+ //test(ready);
+ //streamsort(&moves[depth][branch],&index);
+ aimoves_sort_bis(moves,depth,branch);
+ moves1.utility = u_sum;
+ moves[depth][branch].utility = u_sum;
+ /*----------------------------
+ rewritten for hardware
+ ----------------------------*/
+ //if (!aimoves_choose(&moves1, move))
+ // return 0;
+ //else return 1;
+ //int ret_val;
+ //AIMove move;
+ //ret_val=aimoves_choose(&moves[depth][branch], &move/*,&index[0]*/);
+ //if (!ret_val)
+ // return 0;
+ //else return 1;
+ /*----------------------------
+ end rewritten for hardware
+ ----------------------------*/
+ //board_free(b);
+ //return moves;
+ return 1;
+}
+
+//void debug_counts(void)
+//{
+// int i, sum = 0;
+//
+// if (!b)
+// return;
+//
+// g_debug("Threat counts (black, white):");
+// for (i = 1; i < connect_k; i++) {
+// g_debug("%d: %3d %3d", i, threat_counts[i][0],
+// threat_counts[i][1]);
+// sum += threat_counts[i][0] * threat_bits(i, b->turn) -
+// threat_counts[i][1] *
+// threat_bits(i, other_player(b->turn));
+// }
+// if (sum > 0)
+// g_debug("Threat sum: %d (10^%.2f)", sum, log10((double)sum));
+// else if (sum < 0)
+// g_debug("Threat sum: %d (-10^%.2f)", sum, log10((double)-sum));
+// else
+// g_debug("Threat sum: 0");
+//}
+
+//static int threat_number(int player, int threat,threat_count_array threat_counts)
+//{
+// return threat_counts.data[threat][player] / (connect_k - threat);
+//}
+
+//AIMoves *ai_priority(const Board *b)
+//{
+// AIMoves *moves;
+// int i, j, stage[2] = {1, 1}, mask, bits;
+//
+// moves = ai_threats(b);
+//
+// /* Do not prioritize if we've won */
+// if (threat_counts[connect_k - place_p + 1][b->turn - 1]) {
+// moves->utility = AIW_WIN;
+// return moves;
+// }
+//
+// /* Find the largest supported threat for each player */
+// for (i = 2; i < connect_k; i++) {
+// if (threat_number(0, i - 1) >= place_p &&
+// threat_number(0, i) > place_p)
+// stage[0] = i;
+// if (threat_number(1, i - 1) >= place_p &&
+// threat_number(1, i) > place_p)
+// stage[1] = i;
+// }
+//
+// //if (opt_debug_stage)
+// // g_debug("Stages %d/%d", stage[0], stage[1]);
+//
+// /* Do not prioritize if we're losing */
+// if (stage[b->turn - 1] <= stage[other_player(b->turn) - 1]) {
+// moves->utility = -stage[other_player(b->turn) - 1];
+// return moves;
+// }
+//
+// /* Threats above the player's stage are no more valuable than the
+// stage */
+// bits = 1 << (stage[b->turn - 1] * BITS_PER_THREAT);
+// mask = bits - 1;
+// for (i = 0; i < moves->len; i++) {
+// AIWEIGHT w = moves->data[i].weight, w2;
+//
+// if (w < AIW_THREAT_MAX && w >= bits) {
+// w2 = w & mask;
+// w = w & ~mask;
+// for (j = stage[b->turn - 1];
+// w && j < connect_k - place_p + 1; j++) {
+// w = w >> BITS_PER_THREAT;
+// w2 += w & mask;
+// }
+// moves->data[i].weight = w2;
+// }
+// }
+//
+// /* Stage determines weight */
+// moves->utility = stage[b->turn - 1];
+// return moves;
+//}
+/*AIMoves*/ void ai_marks(Board *b, PIECE minimum,AIMoves *moves)
+{
+ //#pragma read_write_ports b.data combined 2
+ //#pragma internal_blockram b
+ //#pragma no_memory_analysis b
+ //AIMoves *moves = aimoves_new();
+ //AIMoves moves;
+ //AIMoves moves[361];
+ AIMove move;
+ PIECE p;
+ //moves_fifo.resoet();
+ AIMove m;
+ #pragma num_iterations(19,19,19)
+ for (move.y = 0; move.y < board_size; move.y++)
+ #pragma num_iterations(19,19,19)
+ for (move.x = 0; move.x < board_size; move.x++){
+ if ((p = piece_at(b, move.x, move.y)) >= minimum) {
+ move.weight = p - PIECE_THREAT0;
+ aimoves_set(moves, &move);
+ //pico_stream_output_queue(move);
+ //cout<<"push"<data[0].weight=-100;
+// while(1) {
+// if(!moves_fifo.empty()){
+// val=moves_fifo.pop();
+// for(i=0;ii-1;j--){
+// list[j+1]=list[j];
+// }
+// break;
+// }
+// }
+// list[i]=val;
+// len++;
+// }
+// else break;
+// //if(!moves_fifo.active && moves_fifo.empty()) break;
+// }
+ //while(1) {
+ //int count=0;
+ #pragma num_iterations(1,150,368)
+ for(k=0;k<368;k++){
+ //count++;
+ //cout<6){
+
+ //if(ready>5){
+ //val=pico_stream_input_queue();
+ //cout<<"popped"<<","<len=len;break;}
+ else if(val.weight==-100) continue;
+ #pragma num_iterations(0,150,361)
+ for(i=0;idata[i].weight < val.weight){
+ for(j=len-1;j>i-1;j--){
+ moves->data[j+1]=moves->data[j];
+ //index[j+1]=index[j];
+ }
+ break;
+ }
+ }
+ index->data[i]=len;
+ moves->data[i]=val;
+ len++;
+ //cout<<"STREAMSORT"<<":";
+ //}
+ /*else*/ //{moves->len=len;break;}
+ }
+ }
+ moves->len=len;
+ //cout<<"STREAMSORT"<<":"<len<data[i].weight<<",";
+ //cout<data[index[i]].weight<<",";
+ //cout<x = board_size / 2;
+ move->y = board_size / 2;
+ move->weight = AIW_NONE;
+ //aimoves_append(&moves, move);
+ //aimoves_choose(&moves, move);
+ //return moves;
+}
trunk/XILINX/BUILD_SCC_SRCH/synth_src/threats.cpp
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC_SRCH/synth_src/shared.h
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/synth_src/shared.h (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/synth_src/shared.h (revision 17)
@@ -0,0 +1,493 @@
+#ifndef SHARED_H
+#define SHARED_H
+/*
+
+connectk -- a program to play the connect-k family of games
+Copyright (C) 2007 Michael Levin
+
+This program is free software; you can redistribute it and/or
+modify it under the terms of the GNU General Public License
+as published by the Free Software Foundation; either version 2
+of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+/* Some definitions in case glib is not included */
+//#ifndef TRUE
+#define TRUE 1
+#define FALSE 0
+//#define NULL ((void*)0)
+//#endif
+//#ifndef __G_TYPES_H__
+typedef unsigned int gboolean;
+#pragma bitsize gboolean 1
+typedef int gsize;
+//#endif
+#include
+#include "pico.h"
+
+
+/*
+ * Options
+ */
+
+/* These are boolean options the user can toggle through the "Options" menu.
+ Do not modify them directly as the "Options" menu will not reflect your
+ changes. You can add more options in connectk.c */
+extern int opt_pause_ai, /* Pause AI to inspect the board */
+// opt_det_ai, /* No randomness */
+ opt_print_u, /* Print utility after every move */
+ opt_debug_dfsc, /* Print out debug messages related to the DFS
+ cache */
+ opt_debug_thread, /* Print messages related to thread and mutex function */
+ opt_mark_log, /* Take log of weights before marking */
+ opt_mark_norm, /* Normalize to the largest weight */
+ opt_debug_stage, /* Debug priority stages */
+ opt_grayscale; /* Use grayscale rendering for print outs */
+
+/*
+ * Utility
+ */
+
+#ifdef _EFISTDARG_H_
+char *nvav(int *plen, const char *fmt, va_list va);
+#endif
+char *nva(int *plen, const char *fmt, ...);
+char *va(const char *fmt, ...);
+/* The va family of functions simplify string processing by allowing
+ printf-style substitution with any string-accepting function.
+
+ For example:
+ window_status(va("1 + 2 = %d", 1 + 2));
+
+ nva provides additional functionality by outputting the length of the
+ formatted string into the integer pointed to by plen. nvav accepts a variable
+ argument indirectly. */
+
+void window_status(const char *msg);
+/* Sets the status bar text of the main window */
+
+/*
+ * Allocation Chain
+ */
+
+typedef struct AllocChain {
+ gboolean free;
+ /* Is this object unallocated? */
+
+ unsigned int id;
+ /* Each object has a unique id */
+
+ struct AllocChain *next;
+ /* Next object in the chain */
+} AllocChain;
+
+typedef AllocChain *(*AllocFunc)(AllocChain *old_ac);
+
+AllocChain *achain_new(AllocChain **root, AllocFunc af);
+void achain_free(AllocChain *ac);
+void achain_copy(const AllocChain *src, AllocChain *dest, gsize mem);
+
+/*
+ * Game state
+ */
+
+/* We limit the maximum values of these variables; note that these are not
+ arbitrary limits and should be modified with care */
+#define MAX_BOARD_SIZE 59
+#define MAX_CONNECT_K 12
+#define MAX_PLACE_P 12
+#define MAX_START_Q 6
+#define MAX_DEPTH 9
+#define MAX_BRANCH 32
+
+
+#define board_size 19
+#define board_stride 21
+#define move_no 0
+#define move_last 0
+#define connect_k 6
+#define place_p 2
+#define start_q 1
+#define opt_det_ai 1
+//extern int board_size, board_stride, move_no, connect_k, place_p, start_q;
+/* Board size (for all boards), moves in the game, connect_k to win, place_p
+ moves at a time, black has start_q moves on the first move; do NOT modify
+ these directly! */
+
+enum {
+ PIECE_ERROR = -1,
+ /* Error pieces form a one tile deep border around the board */
+
+ PIECE_NONE = 0,
+ PIECE_BLACK,
+ PIECE_WHITE,
+ /* Empty and played pieces */
+
+ PIECES,
+ /* Total number of normal pieces (2) */
+
+ PIECE_SEARCHED,
+ PIECE_SEARCHED_MAX = PIECE_SEARCHED + MAX_DEPTH,
+ /* Markers used by the search system */
+
+ PIECE_THREAT0,
+ PIECE_MARKER = PIECE_THREAT0,
+ /* These threat markers are usable by the AIs */
+};
+typedef int PIECE;
+#pragma bitsize PIECE 32
+
+#define MAX_THREAT (INT_MAX - PIECE_THREAT0)
+/* Highest value a threat marker can have */
+
+#define PIECE_THREAT(n) (PIECE_THREAT0 + (n))
+/* This marker represents a threat n-turns (of that player) away */
+
+#define piece_empty(p) ((p) == PIECE_NONE || (p) >= PIECES)
+/* Checks if a piece is an empty or a marker */
+
+typedef unsigned int PLAYER;
+/* Type for AIs, this is the index of the AI entry in ai.c */
+
+typedef int BCOORD;
+#pragma bitsize BCOORD 8
+/* Type for board coordinates */
+
+typedef struct Board {
+ int ac;
+ /* Allocation chain must be the first member */
+ #pragma bitsize ac 4
+ unsigned int moves_left;
+ /* How many moves the current player has left */
+ #pragma bitsize moves_left 8
+
+ //struct Board *parent; //not synthesizable
+ int parent;
+ /* The board preceeding this one in history */
+ #pragma bitsize parent 4
+
+ gboolean won;
+ BCOORD win_x1, win_y1, win_x2, win_y2;
+ /* On won boards, used to indicate where the winning line is */
+
+ PIECE turn;
+ /* Whose turn it is on this board */
+
+ BCOORD move_x, move_y;
+ /* The move to the next Board in history */
+
+ PIECE data[board_stride][board_stride];
+} Board;
+/* The board structure represents the state of the game board. Do NOT preserve
+ board pointers across games. */
+typedef struct{
+ unsigned int data[361];
+ #pragma bitsize data 9
+} index_array;
+
+extern AllocChain *board_root;
+extern gsize board_mem;
+/* Variables for the allocation chain */
+
+//extern Board board;
+/* This is the current board. Do NOT modify it, that's cheating. :) */
+const char *bcoords_to_string(BCOORD x, BCOORD y);
+const char *bcoord_to_alpha(BCOORD c);
+/* Return a static string representing a board coordinate pair */
+
+void string_to_bcoords(const char *string, BCOORD *x, BCOORD *y);
+/* Attempts to convert a string to board coordinates */
+
+void new_game(Board *board,unsigned int size);
+
+AllocChain *board_alloc(AllocChain *data);
+#define board_new() ((Board*)achain_new(&board_root, board_alloc))
+#define board_free(b) achain_free((AllocChain*)b)
+/* Boards are dynamically allocated and must be free'd */
+
+//#define board_copy(from, to) achain_copy((AllocChain*)from, (AllocChain*)to,\
+ board_mem)
+void board_copy(const Board *from, Board *to);
+/* Overwrite one board with another */
+
+void board_clean(Board *b);
+/* Remove all threat markers from a board */
+
+int threat_count(const Board *b, PIECE player);
+/* Gives the number of threats on a board for the current player */
+
+Board *board_at(unsigned int move);
+/* Returns a static pointer to a board in the history at move */
+
+//int count_pieces(const Board *b, BCOORD x, BCOORD y, PIECE type,
+int count_pieces(const Board *b, BCOORD x, BCOORD y, PIECE type,
+ int dx, int dy, PIECE *out);
+/* Count consecutive pieces of type starting from (x, y) in the direction given
+ by (dx, dy); includes (x, y) itself in the count and outputs the final
+ piece to out if it is not NULL */
+
+gboolean check_win_full(const Board *b, BCOORD x, BCOORD y,
+ BCOORD *x1, BCOORD *y1, BCOORD *x2, BCOORD *y2);
+#define check_win(b, x, y) check_win_full(b, x, y, 0, 0, 0, 0)
+/* Returns non-zero if placing a piece of type at (x, y) on the current board
+ will result in a win for that player. The start and end coordinates of the
+ winning line will be placed in (x1, y1) and (x2, y2). */
+
+static inline PIECE piece_at(const Board *b, BCOORD x, BCOORD y)
+{
+ //return b->data[(y + 1) * board_stride + x + 1];
+ return b->data[y+1][x+1];
+}
+/* Returns the piece at (x, y) on board b. If the coordinates are out of range,
+ this function will return PIECE_ERROR. */
+
+char piece_to_char(PIECE piece);
+/* Returns a one character representation of a piece (e.g. 'W', 'B', etc) */
+
+const char *piece_to_string(PIECE piece);
+/* Returns a static string representation of a piece (e.g. "White" etc) */
+
+static inline void place_piece_type(Board *b, BCOORD x, BCOORD y, PIECE type)
+{
+ //b->data[(y + 1) * board_stride + x + 1] = type;
+ b->data[y+1][x+1]=type;
+}
+#define place_piece(b, x, y) place_piece_type(b, x, y, (b)->turn)
+#define place_threat(b, x, y, n) place_piece_type(b, x, y, PIECE_THREAT(n))
+/* Places a piece on board b, overwriting any piece that was previously in that
+ place */
+
+#define other_player(p) ((p) == PIECE_BLACK ? PIECE_WHITE : PIECE_BLACK)
+/* Invert a player piece */
+
+/*
+ * Move arrays
+ */
+
+/* Some guideline values for move weights: */
+#define AIW_MAX INT_MAX /* largest weight value */
+#define AIW_MIN INT_MIN /* smallest weight value */
+#define AIW_WIN AIW_MAX /* this move wins the game */
+#define AIW_DEFEND (AIW_WIN - 2) /* defends from an opponent win */
+#define AIW_NONE 0 /* does nothing */
+#define AIW_DRAW AIW_NONE /* draw game */
+#define AIW_LOSE (-AIW_WIN) /* this move loses the game */
+#define AIW_THREAT_MAX 262144 /* value of an immediate threat */
+
+typedef int AIWEIGHT;
+/* Type for AI move weights (utilities) */
+#pragma bitsize AIWEIGHT 32
+
+typedef struct {
+ AIWEIGHT weight;
+ BCOORD x, y;
+} AIMove;
+/* AIs return an array filled with these */
+
+typedef struct AIMoves {
+ int ac;
+ /* Allocation chain must be the first member */
+ #pragma bitsize ac 4
+
+ unsigned int len;
+ /* Number of members in data */
+ #pragma bitsize len 8
+
+ AIWEIGHT utility;
+ /* A composite utility value set by some AIs when producing a moves
+ list */
+
+ AIMove data[361];
+ /* Array of AIMove structures */
+} AIMoves;
+/* An array type for holding move lists */
+
+
+typedef struct {
+ int threat[2];
+ PIECE turn[2];
+} Line;
+typedef struct{
+ int data[MAX_CONNECT_K + 1][2];
+}threat_count_array;
+
+
+
+
+
+
+
+
+AllocChain *aimoves_alloc(AllocChain *data);
+#define aimoves_new() ((AIMoves*)achain_new(&aimoves_root, aimoves_alloc))
+//#define aimoves_free(m) achain_free((AllocChain*)(m))
+static inline void aimoves_free(AIMoves *m) {
+ m->len=0;
+}
+///////////* Move arrays are dynamically allocated and must be free'd */
+//////////
+//////////#define aimoves_copy(from, to) achain_copy((AllocChain*)(from),\
+////////// (AllocChain*)(to), aimoves_mem)
+///////////* Overwrite one array with another */
+//////////
+//////////void aimoves_add(AIMoves *moves, const AIMove *aim);
+///////////* Add an AIMove to an AIMoves array; move weights will be added to existing
+////////// weights */
+//////////
+void aimoves_append(AIMoves *moves, const AIMove *aim);
+#define aimoves_set aimoves_append
+///////////* Add an AIMove to an AIMoves array; existing moves weights will be
+////////// overwritten */
+//////////
+int aimoves_choose(AIMoves *moves, AIMove *move/*, index_array *index*/);
+/* Will choose one of the best moves from a GArray of AIMove structures at
+ random. Returns non-zero if a move was chosen or zero if a move could not
+ be chosen for some reason. */
+//////////
+int aimoves_compare(const void *a, const void *b);
+/* A comparison function for sorting move lists by weight */
+//////////
+//////////void aimoves_crop(AIMoves *moves, unsigned int n);
+///////////* Reduce a moves list to the top-n by weight */
+//////////
+//////////void aimoves_concat(AIMoves *m1, const AIMoves *m2);
+///////////* Concatenates m2 to m1 without checking for duplicates */
+//////////
+//////////AIMoves *aimoves_dup(const AIMoves *moves);
+///////////* Duplicate a GArray of moves */
+//////////
+int aimoves_find(const AIMoves *moves, BCOORD x, BCOORD y);
+///////////* Returns the index of (x, y) if it is in moves or -1 otherwise */
+//////////
+//////////void aimoves_range(AIMoves *moves, AIWEIGHT *min, AIWEIGHT *max);
+///////////* Find the smallest and largest weight in the move array */
+//////////
+//////////void aimoves_merge(AIMoves *m1, const AIMoves *m2);
+///////////* Merges m2 into m1, the highest weight is used for duplicates */
+//////////
+//////////void aimoves_print(const AIMoves *moves);
+///////////* Prints out an array of moves */
+//////////
+//////////void aimoves_remove(AIMoves *moves, BCOORD x, BCOORD y);
+///////////* Remove an AIMove from a GArray of AIMoves */
+//////////
+//////////void aimoves_remove_index_fast(AIMoves *moves, int i);
+///////////* Remove a move from the list by overwriting it by the last move and
+////////// decrementing the length */
+//////////
+void aimoves_shuffle(AIMoves *moves,unsigned int current_random);
+/* Shuffle a list of moves */
+
+void aimoves_sort(AIMoves *moves);
+void aimoves_sort_bis(AIMoves moves[2][16],int depth,int branch);
+/* Sort a list of moves by descending weight */
+
+//////////void aimoves_subtract(AIMoves *m1, const AIMoves *m2);
+///////////* Subtracts members of m2 from m1; O(n^2) */
+//////////
+extern AllocChain *aimoves_root;
+//////////extern gsize aimoves_mem;
+///////////* Allocation chain variables */
+//////////
+//////////const char *aiw_to_string(AIWEIGHT w);
+///////////* Convert a weight to a string representation */
+//////////
+//////////char *aimove_to_string(const AIMove *move);
+///////////* Convert a move to a string representation */
+//////////
+///////////*
+////////// * AI helper functions
+////////// */
+//////////
+extern int ai_stop;
+///////////* If this variable is non-zero, the system is trying to stop the AI thread
+////////// and your AI should exit. Do not set this yourself. */
+//////////
+//////////typedef AIMoves *(*AIFunc)(const Board *b);
+///////////* AIs are defined as functions that output an unsorted, weighted list of board
+////////// coordinates for an arbitrary board. To create an AI in a file other than
+////////// ai.c, add a prototype of the function here and in ai.c. */
+//////////
+//////////AIMoves *enum_top_n(const Board *b, int n);
+///////////* Returns an array containing the top n moves according to the utility
+////////// function */
+//////////
+/*AIMoves **/ void enum_adjacent(Board *b, int dist,AIMoves *moves,unsigned int current_random);
+/* Enumerate empty tiles at most dist away from some other piece on the board */
+
+void streamsort(AIMoves *moves,index_array *index);
+/*AIMoves **/void ai_marks(Board *b, PIECE min,AIMoves *moves);
+/* Fills a moves list with tiles marked at least PIECE_THREAT(min) */
+
+/*
+ * AI
+ */
+
+/* This table holds the information about all of the AIs in the program. Each
+ has a short and long description. The short description will be used for
+ the command line interface and the long description appears in the UI menu.
+ Each AI has an associated AIFunc which outputs a move for the current
+ board. */
+///////////typedef struct AI {
+/////////// char *s_desc, *l_desc;
+/////////// AIFunc func;
+///////////} AI;
+///////////
+///////////AIMoves *ai_sequences(const Board *b);
+////////////* The square of the number of pieces in a window */
+///////////
+///////////AIMoves *ai_mesh(const Board *b);
+////////////* The board as a mesh weighed down by the pieces */
+///////////
+///////////AIMoves *ai_monte_carlo(const Board *b);
+////////////* Chooses the best move based on which one wins the most random games */
+///////////
+///////////AIMoves *ai_random(const Board *b);
+////////////* Plays in a random tile */
+///////////
+/*AIMoves */ void ai_adjacent(Board *b,AIMove *move,unsigned int current_random);
+/* Plays in a random tile adjacent to any piece on the board */
+
+///////////AIMoves *ai_windows(const Board *b);
+////////////* Plays in the best defensive position */
+///////////
+///////////AIMoves *ai_utility(const Board *b);
+///////////AIMoves *ai_dfs_utility(const Board *b);
+////////////* Utility function */
+///////////
+/*AIMoves **/int ai_threats(Board board[2][16],int depth,int branch,AIMoves moves[2][16]/*,index_array *index*/);
+AIMoves *ai_priority(const Board *b);
+/* Multi-level threats */
+
+
+
+void my_srandom(int seed,unsigned int *current_random);
+int my_irand(int imax,unsigned int current_random);
+//void backup_move(Board *board, AIMoves *moves,AIMove *move);
+//AIWEIGHT threat_line(int x, int y, int dx, int dy,Board *b,Board *bwrite,int k,int loop_bound);
+//int threat_window(int x, int y, int dx, int dy,
+// PIECE *ptype, int *pdouble,Board *b);
+int connect6ai_synth(int firstmove,char movein[8], char colour, char moveout[8]);
+//extern "C" AIMove pico_stream_input_queue();
+//extern "C" void pico_stream_output_queue(AIMove);
+//extern "C" AIMove pico_ips_fifo_read_queue();
+//extern "C" void pico_ips_fifo_write_queue(AIMove);
+//extern int id;
+//extern int ready;
+typedef struct {
+ PLAYER ai;
+ //SEARCH search;
+ int depth, branch, cache, tss;
+} Player;
+/*AIMoves **/int search(Board *board,AIMove *move, Player *player);
+AIWEIGHT df_search(Board *b, AIMoves *moves,/*index_array *index,*/ Player *player,int depth, int cache_index,PIECE searched, AIWEIGHT alpha, AIWEIGHT beta);
+#endif
trunk/XILINX/BUILD_SCC_SRCH/synth_src/shared.h
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC_SRCH/synth_src/util.cpp
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/synth_src/util.cpp (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/synth_src/util.cpp (revision 17)
@@ -0,0 +1,131 @@
+/* util.cpp
+ June 9, 2011
+ Some helper functions.
+
+ Much of the code below is borrowed from Alastair Smith's program
+ from the 2010 FPT Othello competition
+
+ By Kevin Nam
+*/
+
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include "util.h"
+
+#define IA 1103515245u
+#define IC 12345u
+#define IM 2147483648u
+
+using namespace std;
+
+static unsigned int current_random = 0;
+
+
+char select_AI_colour (int argc, char **argv){
+ char ai_colour='L';
+ int i;
+ // cout<<"Please enter referee AI's colour. L or D"<> ai_colour;
+ for(i=0;i> ai_colour;
+ // }
+
+ // cout<<"AI is playing as "<> com_port;
+ }
+
+
+ port = open(com_port.c_str(), O_RDWR | O_NOCTTY | O_NONBLOCK);
+ while(port < 0) // if open is unsucessful keep trying until the user specifies a good port
+ {
+ cout << "Unable to open port " << com_port << ", try again, should be: (windows) /dev/comx or (linux) /dev/ttyx ?\n";
+ cin >> com_port;
+ port = open(com_port.c_str(), O_RDWR | O_NOCTTY | O_NONBLOCK);
+ }
+ setup_port(port);
+
+ cout << "COM port has been set up at a baud rate of 115200\n";
+ return port;
+}
+
+void setup_port(int fd) {
+ struct termios options;
+ fcntl(fd, F_SETFL, 0);
+ tcgetattr(fd, &options);
+ cfsetispeed(&options, B115200);
+ cfsetospeed(&options, B115200);
+ options.c_cflag |= (CLOCAL | CREAD);
+ tcsetattr(fd, TCSANOW, &options);
+
+ // set up non-blocking port, so that we can time out
+ int opts;
+ opts = fcntl(fd,F_GETFL);
+ if (opts < 0) {
+ perror("fcntl(F_GETFL)");
+ exit(EXIT_FAILURE);
+ }
+ opts = (opts | O_NONBLOCK);
+ if (fcntl(fd,F_SETFL,opts) < 0) {
+ perror("fcntl(F_SETFL)");
+ exit(EXIT_FAILURE);
+ }
+ return;
+}
+
+int char_to_int (char c){
+ if (c == '0') return 0;
+ else if (c == '1') return 1;
+ else if (c == '2') return 2;
+ else if (c == '3') return 3;
+ else if (c == '4') return 4;
+ else if (c == '5') return 5;
+ else if (c == '6') return 6;
+ else if (c == '7') return 7;
+ else if (c == '8') return 8;
+ else if (c == '9') return 9;
+
+ return 0;
+}
+
+void wait(double seconds){
+ timeval tim;
+ gettimeofday(&tim, NULL);
+ double t1=tim.tv_sec+(tim.tv_usec/1000000.0);
+ while (1){
+ gettimeofday(&tim, NULL);
+ double t2=tim.tv_sec+(tim.tv_usec/1000000.0);
+ if (t2-t1 >= seconds)
+ break;
+ }
+}
+
Index: trunk/XILINX/BUILD_SCC_SRCH/synth_src/connect6.cpp
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/synth_src/connect6.cpp (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/synth_src/connect6.cpp (revision 17)
@@ -0,0 +1,470 @@
+/*
+ connect6.cpp
+ June 9, 2011
+ This file contains the game AI
+ By Kevin Nam
+
+*/
+
+#include
+#include
+
+#include "util.h"
+#include "connect6.h"
+
+// Subtract this many points for moves at the edges.
+#define EDGEPENALTY 5
+
+using namespace std;
+
+/* The cost function simply counts all of the consecutive stones of same colour in
+ every direction from the spot for which the points is being calculated.
+
+ Ex:
+
+ .DDLL
+ .DLDD
+ DXDDD
+ ...D.
+
+ Above, X is the spot being calculated.
+ The points would be 2 (above) + 2(topright) + 3(right) + 1 (left) = 8.
+ It treats opponent's stones and own stones with equal weighting.
+
+ Return 0 if the spot y,x is already taken, else return the calculated value
+
+*/
+int calculatepoints(char board[][19], int y, int x, char colour){
+ int pts = 0, tempx = x, tempy = y, tcount = 0,bcount = 0;
+ int lcount = 0,rcount = 0,trcount = 0,tlcount = 0,brcount = 0,blcount = 0;
+ char tcolour = 0,bcolour = 0,lcolour = 0,rcolour = 0,tlcolour = 0,trcolour = 0,brcolour = 0,blcolour = 0;
+
+ if (board[y][x] != 0)
+ return 0;
+
+ // scan column above
+ if (y > 0){
+ tempy = y-1;
+ tempx = x;
+ tcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != tcolour || board[tempy][tempx] == 0) break;
+ tcount++;
+ if (tempy == 0) break;
+ tempy--;
+ }
+ }
+ // scan column below
+ if (y < 18){
+ tempy = y+1;
+ tempx = x;
+ bcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != bcolour || board[tempy][tempx] == 0) break;
+ bcount++;
+ if (tempy == 18) break;
+ tempy++;
+ }
+ }
+ // scan row to left
+ if (x > 0){
+ tempy = y;
+ tempx = x-1;
+ lcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != lcolour || board[tempy][tempx] == 0) break;
+ lcount++;
+ if (tempx == 0) break;
+ tempx--;
+ }
+ }
+ // scan row to right
+ if (x < 18){
+ tempy = y;
+ tempx = x+1;
+ rcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != rcolour || board[tempy][tempx] == 0) break;
+ rcount++;
+ if (tempx == 18) break;
+ tempx++;
+ }
+ }
+ // scan diagonal topleft
+ if (x > 0 && y > 0){
+ tempy = y-1;
+ tempx = x-1;
+ tlcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != tlcolour || board[tempy][tempx] == 0) break;
+ tlcount++;
+ if (tempx == 0 || tempy == 0) break;
+ tempx--;
+ tempy--;
+ }
+ }
+ // scan diagonal bottomright
+ if (x < 18 && y < 18){
+ tempy = y+1;
+ tempx = x+1;
+ brcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != brcolour || board[tempy][tempx] == 0) break;
+ brcount++;
+ if (tempx == 18 || tempy == 18) break;
+ tempx++;
+ tempy++;
+ }
+ }
+ // scan diagonal topright
+ if (x < 18 && y > 0){
+ tempy = y-1;
+ tempx = x+1;
+ trcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != trcolour || board[tempy][tempx] == 0) break;
+ trcount++;
+ if (tempx == 18 || tempy == 0) break;
+ tempx++;
+ tempy--;
+ }
+ }
+ // scan diagonal bottomleft
+ if (y < 18 && x > 0){
+ tempy = y+1;
+ tempx = x-1;
+ blcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != blcolour || board[tempy][tempx] == 0) break;
+ blcount++;
+ if (tempy == 18 || tempx == 0) break;
+ tempy++;
+ tempx--;
+ }
+ }
+
+ /// Now calculate the points
+ // Check if this is a winning move. Priority #1.
+ if ((tcount >= 5 && tcolour == colour) ||
+ (bcount >= 5 && bcolour == colour) ||
+ (lcount >= 5 && lcolour == colour) ||
+ (rcount >= 5 && rcolour == colour) ||
+ (tlcount >= 5 && tlcolour == colour) ||
+ (trcount >= 5 && trcolour == colour) ||
+ (brcount >= 5 && brcolour == colour) ||
+ (blcount >= 5 && blcolour == colour) ||
+ (tcount + bcount >= 5 && tcolour == colour && bcolour == colour) ||
+ (lcount + rcount >= 5 && lcolour == colour && rcolour == colour) ||
+ (tlcount + brcount >= 5 && tlcolour == colour && brcolour == colour) ||
+ (trcount + blcount >= 5 && trcolour == colour && blcolour == colour))
+ return 1000;
+
+ // Check if this move can stop opponent from winning. This move is priority #2.
+ if ((tcount >= 4 && tcolour != colour) ||
+ (bcount >= 4 && bcolour != colour) ||
+ (lcount >= 4 && lcolour != colour) ||
+ (rcount >= 4 && rcolour != colour) ||
+ (tlcount >= 4 && tlcolour != colour) ||
+ (trcount >= 4 && trcolour != colour) ||
+ (brcount >= 4 && brcolour != colour) ||
+ (blcount >= 4 && blcolour != colour) ||
+ (tcount + bcount >= 4 && tcolour != colour && bcolour != colour) ||
+ (lcount + rcount >= 4 && lcolour != colour && rcolour != colour) ||
+ (tlcount + brcount >= 4 && tlcolour != colour && brcolour != colour) ||
+ (trcount + blcount >= 4 && trcolour != colour && blcolour != colour))
+ return 500;
+
+ // Else sum up the counts, use this as the points.
+ pts = tcount + bcount + lcount + rcount + tlcount + trcount + blcount + brcount + 1;
+ // If at an edge, lower the points
+ if (x == 0 || x == 18 || y == 0 || y == 18){
+ if (pts >= EDGEPENALTY)
+ pts -= EDGEPENALTY;
+ else
+ pts = 0;
+ }
+ return pts;
+}
+
+/*
+ The AI Function that calls the cost function for every spot on the board.
+ It returns the location with the highest points. In the event of a tie, randomly decide.
+ Input the board and the colour being played.
+ Puts the move (in ASCII chars) inside move[4]. This is from [1 ... 19]
+ Puts the move (in integers) in moveY and moveX. This is from [0 ... 18]
+*/
+int connect6ai(char board[][19], char colour, char move[4]){
+ int x,y,highx = 0, highy = 0,currenthigh = 0, temp;
+ srand(time(NULL));
+#ifdef EMUL
+ int highRandom =rand();
+#else
+ int highRandom =1;//rand();
+#endif
+ // Sweep the entire board with the cost function
+ for (x = 0; x <= 18; x++){
+ for (y = 0; y <= 18; y++){
+
+ temp = calculatepoints(board,y,x, colour);
+ if (temp > currenthigh){
+ highx = x;
+ highy = y;
+ currenthigh = temp;
+#ifdef EMUL
+ highRandom =rand();
+#else
+ highRandom =1;//rand();
+#endif
+ }
+ // If a tie happens, pseudo-randomly choose one between them
+ if (temp == currenthigh && temp != 0){
+#ifdef EMUL
+ int tempRandom =rand();
+#else
+ int tempRandom =1;//rand();
+#endif
+ if (tempRandom > highRandom){
+ highx = x;
+ highy = y;
+ highRandom = tempRandom;
+ }
+ }
+ }
+ }
+
+ // Modify the board based on current move.
+ board[highy][highx] = colour;
+
+ // Increment by 1 because indexing starts at 1.
+ highy++;
+ highx++;
+
+ /// Convert the int coordinates to corresponding ASCII chars
+ if (highy >= 10){
+ move[0] = '1';
+ highy -= 10;
+ } else {
+ move[0] = '0';
+ }
+ if (highy == 0) move[1] = '0';
+ else if (highy == 1) move[1] = '1';
+ else if (highy == 2) move[1] = '2';
+ else if (highy == 3) move[1] = '3';
+ else if (highy == 4) move[1] = '4';
+ else if (highy == 5) move[1] = '5';
+ else if (highy == 6) move[1] = '6';
+ else if (highy == 7) move[1] = '7';
+ else if (highy == 8) move[1] = '8';
+ else if (highy == 9) move[1] = '9';
+
+ // Do same for x.
+ if (highx >= 10){
+ move[2] = '1';
+ highx -= 10;
+ } else {
+ move[2] = '0';
+ }
+ if (highx == 0) move[3] = '0';
+ else if (highx == 1) move[3] = '1';
+ else if (highx == 2) move[3] = '2';
+ else if (highx == 3) move[3] = '3';
+ else if (highx == 4) move[3] = '4';
+ else if (highx == 5) move[3] = '5';
+ else if (highx == 6) move[3] = '6';
+ else if (highx == 7) move[3] = '7';
+ else if (highx == 8) move[3] = '8';
+ else if (highx == 9) move[3] = '9';
+
+ return 0;
+}
+
+
+// scan board, return 'L' or 'D' for the winner, 'n' if no winner.
+char check_for_win (char board[][19]){
+ int y,x;
+ for (y = 0; y < 19; y++){
+ for (x = 0; x < 19; x++){
+ if (board[y][x] == 0)
+ continue;
+
+ int tempx, tempy, tcount = 0,bcount = 0;
+ int lcount = 0,rcount = 0,trcount = 0,tlcount = 0,brcount = 0,blcount = 0;
+ char tcolour = 0,bcolour = 0,lcolour = 0,rcolour = 0,tlcolour = 0,trcolour = 0,brcolour = 0,blcolour = 0;
+
+ // scan column above
+ if (y > 0){
+ tempy = y;
+ tempx = x;
+ tcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != tcolour || board[tempy][tempx] == 0) break;
+ tcount++;
+ if (tempy == 0) break;
+ tempy--;
+ }
+ }
+ // scan column below
+ if (y < 18){
+ tempy = y+1;
+ tempx = x;
+ bcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != bcolour || board[tempy][tempx] == 0) break;
+ bcount++;
+ if (tempy == 18) break;
+ tempy++;
+ }
+ }
+
+ if (tcolour == bcolour && tcount + bcount >= 6) return tcolour;
+
+ // scan row to left
+ if (x > 0){
+ tempy = y;
+ tempx = x;
+ lcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != lcolour || board[tempy][tempx] == 0) break;
+ lcount++;
+ if (tempx == 0) break;
+ tempx--;
+ }
+ }
+ // scan row to right
+ if (x < 18){
+ tempy = y;
+ tempx = x+1;
+ rcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != rcolour || board[tempy][tempx] == 0) break;
+ rcount++;
+ if (tempx == 18) break;
+ tempx++;
+ }
+ }
+
+ if (lcolour == rcolour && lcount + rcount >= 6) return lcolour;
+
+ // scan diagonal topleft
+ if (x > 0 && y > 0){
+ tempy = y;
+ tempx = x;
+ tlcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != tlcolour || board[tempy][tempx] == 0) break;
+ tlcount++;
+ if (tempx == 0 || tempy == 0) break;
+ tempx--;
+ tempy--;
+ }
+ }
+ // scan diagonal bottomright
+ if (x < 18 && y < 18){
+ tempy = y+1;
+ tempx = x+1;
+ brcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != brcolour || board[tempy][tempx] == 0) break;
+ brcount++;
+ if (tempx == 18 || tempy == 18) break;
+ tempx++;
+ tempy++;
+ }
+ }
+
+ if (tlcolour == brcolour && tlcount + brcount >= 6) return tlcolour;
+
+ // scan diagonal topright
+ if (x < 18 && y > 0){
+ tempy = y;
+ tempx = x;
+ trcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != trcolour || board[tempy][tempx] == 0) break;
+ trcount++;
+ if (tempx == 18 || tempy == 0) break;
+ tempx++;
+ tempy--;
+ }
+ }
+ // scan diagonal bottomleft
+ if (y < 18 && x > 0){
+ tempy = y+1;
+ tempx = x-1;
+ blcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != blcolour || board[tempy][tempx] == 0) break;
+ blcount++;
+ if (tempy == 18 || tempx == 0) break;
+ tempy++;
+ tempx--;
+ }
+ }
+
+ if (trcolour == blcolour && trcount + blcount >= 6) return trcolour;
+ }
+ }
+ // return 'n' for no victory
+ return 'n';
+}
+
+// Check if the board is full
+int check_board_full (char board[][19]){
+ int y,x;
+ // As soon as there is an empty intersection, return 0;
+ for (y = 0; y < 19; y++)
+ for (x = 0; x < 19; x++)
+ if (board[y][x] == 0)
+ return 0;
+
+ // By now, swept entire board and all filled.
+ return -1;
+}
+
+// Check if move y,x is valid. Here, y and x are [0 ... 18]
+int check_move_validity (char board[][19],int y, int x){
+ if (y < 0 || y > 18 || x < 0 || x > 18 || board[y][x] != 0){
+ return -1;
+ }
+ return 0;
+}
+
+
+void print_board (char board[][19]){
+ printf(" 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9");
+ unsigned short x,y;
+ for (x = 0; x <= 18; x++){
+ printf("\n");
+ printf("%d",x+1);
+ if (x < 9) printf(" ");
+ for (y = 0; y <= 18; y++){
+ if (board[x][y] == 0)
+ printf(".");
+ else printf("%c",board[x][y]);
+ printf(" ");
+ }
+
+ }
+ printf("\n");
+}
+
+void print_board_file (char board[][19]){
+char filename[12]="myboard.txt";
+FILE *fp=fopen(filename,"w");
+ fprintf(fp," 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9");
+ unsigned short x,y;
+ for (x = 0; x <= 18; x++){
+ fprintf(fp,"\n");
+ fprintf(fp,"%d",x+1);
+ if (x < 9) fprintf(fp," ");
+ for (y = 0; y <= 18; y++){
+ if (board[x][y] == 0)
+ fprintf(fp,".");
+ else fprintf(fp,"%c",board[x][y]);
+ fprintf(fp," ");
+ }
+
+ }
+ fprintf(fp,"\n");
+fclose(fp);
+}
Index: trunk/XILINX/BUILD_SCC_SRCH/synth_src/threats.h
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/synth_src/threats.h (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/synth_src/threats.h (revision 17)
@@ -0,0 +1,30 @@
+
+
+
+
+typedef int PIECE;
+
+typedef struct Board {
+ AllocChain ac;
+ /* Allocation chain must be the first member */
+
+ unsigned int moves_left;
+ /* How many moves the current player has left */
+
+ struct Board *parent;
+ /* The board preceeding this one in history */
+
+ gboolean won;
+ BCOORD win_x1, win_y1, win_x2, win_y2;
+ /* On won boards, used to indicate where the winning line is */
+
+ PIECE turn;
+ /* Whose turn it is on this board */
+
+ BCOORD move_x, move_y;
+ /* The move to the next Board in history */
+
+ PIECE data[];
+} Board;
+/* The board structure represents the state of the game board. Do NOT preserve
+ board pointers across games. */
Index: trunk/XILINX/BUILD_SCC_SRCH/synth_src/state.cpp
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/synth_src/state.cpp (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/synth_src/state.cpp (revision 17)
@@ -0,0 +1,835 @@
+
+/*
+
+connectk -- a program to play the connect-k family of games
+Copyright (C) 2007 Michael Levin
+
+This program is free software; you can redistribute it and/or
+modify it under the terms of the GNU General Public License
+as published by the Free Software Foundation; either version 2
+of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+//#include "config.h"
+//#include
+//#include
+//#include
+//#include
+//#include
+//#include
+//#include
+#include "shared.h"
+//#include "q.hpp"
+//#include "connectk.h"
+#ifdef PICO_SYNTH
+//#include "pico.h"
+#endif
+//#include "./q.hpp"
+using namespace std;
+/*
+ * Allocation chain
+ */
+
+#define IA 1103515245u
+#define IC 12345u
+#define IM 2147483648u
+#define CHECK_RAND
+//moved the following declaration to connect6_threat
+//static unsigned int current_random = 0;
+
+//from vpr uti.c code
+/* Portable random number generator defined below. Taken from ANSI C by *
+ * K & R. Not a great generator, but fast, and good enough for my needs. */
+
+
+//int ready=0;
+void my_srandom(int seed,unsigned int *current_random)
+{
+ *current_random = (unsigned int)seed;
+}
+
+
+int my_irand(int imax,unsigned int current_random)
+{
+
+///* Creates a random integer between 0 and imax, inclusive. i.e. [0..imax] */
+//
+// int ival;
+//
+///* current_random = (current_random * IA + IC) % IM; */
+// current_random = current_random * IA + IC; /* Use overflow to wrap */
+// ival = current_random & (IM - 1); /* Modulus */
+// //float not synthesizable
+// //ival = (int)((float)ival * (float)(imax + 0.999) / (float)IM);
+// ival = (int)(ival * (imax + 1) / IM);
+//
+//#ifdef CHECK_RAND
+// if((ival < 0) || (ival > imax))
+// {
+// //printf("Bad value in my_irand, imax = %d ival = %d\n", imax,
+// // ival);
+// //exit(1);
+// }
+//#endif
+//
+// return (ival);
+return(0);
+}
+
+
+//static void achain_init(AllocChain *ac)
+//{
+// static unsigned int ids;
+//
+// ac->free = FALSE;
+// ac->id = ids++;
+//}
+//
+//AllocChain *achain_new(AllocChain **root, AllocFunc afunc)
+//{
+// AllocChain *ac;
+//
+// if (!*root) {
+// *root = afunc(NULL);
+// achain_init(*root);
+// (*root)->next = NULL;
+// return *root;
+// }
+// ac = *root;
+// for (;;) {
+// if (ac->free) {
+// afunc(ac);
+// achain_init(ac);
+// return ac;
+// }
+// if (!ac->next)
+// break;
+// ac = ac->next;
+// }
+// ac->next = afunc(NULL);
+// achain_init(ac->next);
+// ac->next->next = NULL;
+// return ac->next;
+//}
+//
+//void achain_free(AllocChain *ac)
+//{
+// if (!ac)
+// return;
+// ac->free = TRUE;
+//}
+//
+//void achain_copy(const AllocChain *src, AllocChain *dest, gsize mem)
+//{
+// if (!src || !dest || !mem) {
+// g_warning("NULL argument(s) to achain_copy");
+// return;
+// }
+// memcpy((char*)dest + sizeof (AllocChain),
+// (char*)src + sizeof (AllocChain), mem - sizeof (AllocChain));
+//}
+//
+//static void achain_dealloc(AllocChain **root, gsize mem)
+//{
+// AllocChain *ac = *root, *ac_next;
+//
+// while (ac) {
+// ac_next = ac->next;
+// g_slice_free1(mem, ac);
+// ac = ac_next;
+// }
+// *root = NULL;
+//}
+
+
+// Move Arrays
+
+
+//AllocChain *aimoves_root = NULL;
+gsize aimoves_mem = 0;
+
+//AllocChain *aimoves_alloc(AllocChain *ac)
+//{
+// //if (!ac)
+// // ac = (AllocChain*)g_slice_alloc(aimoves_mem);
+// //memset((char*)ac + sizeof (AllocChain), 0, sizeof (AIMoves) -
+// // sizeof (AllocChain));
+// //return ac;
+//}
+
+void aimoves_add(AIMoves *moves, const AIMove *move)
+{
+ int i;
+
+ i = aimoves_find(moves, move->x, move->y);
+ if (i < 0) {
+ if (moves->len >= board_size * board_size)
+ //g_warning("Attempted to add a move to a full AIMoves");
+ //printf("Attempted to add a move to a full AIMoves");
+ return;
+ else
+ moves->data[moves->len++] = *move;
+ } else
+ moves->data[i].weight += move->weight;
+}
+//FIFO(moves_fifo,AIMove);
+//#pragma fifo_length moves_fifo 361
+void aimoves_append(AIMoves *moves, const AIMove *move)
+{
+ int i;
+
+ if (move->x >= board_size || move->y >= board_size)
+ return;
+ #pragma num_iterations(0,150,361)
+ for (i = 0; i < moves->len; i++) {
+ AIMove *aim = moves->data + i;
+
+ if (aim->x == move->x && aim->y == move->y) {
+ aim->weight = move->weight;
+ return;
+ }
+ }
+ if (moves->len >= board_size * board_size) {
+ //g_warning("Attempted to append a move to a full AIMoves");
+ //printf("Attempted to append a move to a full AIMoves");
+ return;
+ }
+ moves->data[moves->len++] = *move;
+ //if(!moves_fifo.full()) moves_fifo.push(*move);
+}
+
+int aimoves_compare(const void *a, const void *b)
+{
+ return ((AIMove*)b)->weight - ((AIMove*)a)->weight;
+}
+
+int aimoves_choose(AIMoves *moves, AIMove *move/*,index_array *index*/)
+{
+ //#pragma read_write_ports moves.data combined 3
+ //#pragma internal_blockram moves
+ //#pragma no_memory_analysis moves
+
+ int i = 0;
+ int top;
+ AIMoves moves1;
+ #pragma bitsize i 4
+ if (!moves || !moves->len)
+ return 0;
+ aimoves_sort(moves);
+ for (top = 0; top < moves->len &&
+ moves->data[top].weight == moves->data[0].weight; top++);
+ if (top)
+ //i = my_irand(top,current_random);//g_random_int_range(0, top);
+ i=0;
+
+ *move = moves->data[i];
+ return 1;
+ /*---------------------------------------
+ Rewritten for Hardware
+ ---------------------------------------*/
+ //for (top = 0; top < moves->len; top++){
+ // if(top==0) {
+ // if (!moves)
+ // return 0;
+ // }
+ // if(moves->data[index[top]].weight != moves->data[index[0]].weight){
+ // *move = moves->data[index[i]];
+ // return 1;
+ // }
+ // if(top==moves->len-1) {
+ // *move = moves->data[index[i]];
+ // return 1;
+ // }
+ //}
+ // return 0;
+ //if(!moves|| !moves->len) return 0;
+ //else {*move=moves->data[i];return 1;}
+
+
+}
+//
+//void aimoves_crop(AIMoves *moves, unsigned int n)
+//{
+// if (moves->len < n)
+// return;
+// aimoves_shuffle(moves);
+// aimoves_sort(moves);
+// moves->len = n;
+//}
+//
+//void aimoves_concat(AIMoves *m1, const AIMoves *m2)
+//{
+// gsize max_len = board_size * board_size, len;
+//
+// len = m2->len;
+// if (m1->len + len > max_len)
+// len = max_len - m1->len;
+// memcpy(m1->data + len, m2->data, len * sizeof (AIMove));
+// m1->len += len;
+//}
+//
+//AIMoves *aimoves_dup(const AIMoves *moves)
+//{
+// AIMoves *dup;
+//
+// if (!moves)
+// return NULL;
+// dup = aimoves_new();
+// dup->len = moves->len;
+// memcpy(dup->data, moves->data, moves->len * sizeof (AIMove));
+// return dup;
+//}
+//
+int aimoves_find(const AIMoves *moves, BCOORD x, BCOORD y)
+{
+ int i;
+
+ if (moves)
+ for (i = 0; i < moves->len; i++) {
+ const AIMove *aim = moves->data + i;
+
+ if (aim->x == x && aim->y == y)
+ return i;
+ }
+ return -1;
+}
+//
+//void aimoves_range(AIMoves *moves, AIWEIGHT *min, AIWEIGHT *max)
+//{
+// int i;
+//
+// *min = AIW_MAX;
+// *max = AIW_MIN;
+// for (i = 0; i < moves->len; i++) {
+// if (moves->data[i].weight > *max)
+// *max = moves->data[i].weight;
+// if (moves->data[i].weight < *min)
+// *min = moves->data[i].weight;
+// }
+//}
+//
+//void aimoves_merge(AIMoves *m1, const AIMoves *m2)
+//{
+// int len = m1->len, i, j;
+//
+// for (i = 0; i < m2->len; i++)
+// for (j = 0;; j++) {
+// if (j >= len) {
+// aimoves_append(m1, m2->data + i);
+// break;
+// }
+// if (m1->data[j].x == m2->data[i].x &&
+// m1->data[j].y == m2->data[i].y) {
+// if (m2->data[i].weight > m1->data[j].weight)
+// m1->data[j].weight = m2->data[i].weight;
+// break;
+// }
+// }
+//}
+//
+//char *aimove_to_string(const AIMove *aim)
+//{
+// static char buffer[32];
+//
+// g_snprintf(buffer, sizeof (buffer), "%s (%s)",
+// bcoords_to_string(aim->x, aim->y),
+// aiw_to_string(aim->weight));
+// return buffer;
+//}
+//
+//void aimoves_print(const AIMoves *moves)
+//{
+// int i;
+//
+// if (!moves || !moves->len) {
+// g_print("(empty)");
+// return;
+// }
+// for (i = 0; i < moves->len; i++) {
+// const AIMove *aim = moves->data + i;
+//
+// if (i)
+// g_print(", ");
+// g_print("%s", aimove_to_string(aim));
+// }
+//}
+//
+//void aimoves_remove_index_fast(AIMoves *moves, int i)
+//{
+// if (moves->len > i)
+// moves->data[i] = moves->data[moves->len - 1];
+// moves->len--;
+//}
+//
+//void aimoves_remove(AIMoves *moves, BCOORD x, BCOORD y)
+//{
+// int i;
+//
+// for (i = 0; i < moves->len; i++) {
+// AIMove *aim = moves->data + i;
+//
+// if (aim->x == x && aim->y == y) {
+// aimoves_remove_index_fast(moves, i);
+// return;
+// }
+// }
+//}
+//
+void aimoves_shuffle(AIMoves *moves,unsigned int current_random)
+{
+// int i;
+//
+// if (opt_det_ai)
+// return;
+//
+// /* Fisher-Yates shuffle */
+// for (i = 0; i < moves->len; i++) {
+// int j;
+//
+// j = my_irand(moves->len,current_random);//g_random_int_range(i, moves->len);
+// if (i != j) {
+// AIMove tmp;
+//
+// tmp = moves->data[i];
+// moves->data[i] = moves->data[j];
+// moves->data[j] = tmp;
+// }
+// }
+return;
+}
+
+
+//taken from http://cprogramminglanguage.net/c-bubble-sort-source-code.aspx
+void swap(AIMove *x,AIMove *y)
+{
+ AIMove temp;
+ temp = *x;
+ *x = *y;
+ *y = temp;
+}
+void swap_bis(AIMove *list,int index1,int index2){
+ AIMove temp;
+ temp=list[index1];
+ list[index1]=list[index2];
+ list[index2]=temp;
+
+}
+void bublesort(AIMove *list, int n)
+{
+ int i,j;
+ for(i=0;i<(n-1);i++)
+ for(j=0;j<(n-(i+1));j++)
+ if(list[j].weight < list[j+1].weight)
+ //swap(&list[j],&list[j+1]);
+ swap_bis(list,j,j+1);
+ //cout<<"BUBBLESORT"<<":"<data, moves->len, sizeof (AIMove), aimoves_compare);
+ bublesort(moves->data,moves->len);
+ //streamsort(moves->data,moves->len);
+
+}
+void aimoves_sort_bis(AIMoves moves[2][16],int depth,int branch)
+{
+ //qsort(moves->data, moves->len, sizeof (AIMove), aimoves_compare);
+ //bublesort(moves[depth][branch].data,moves[depth][branch].len);
+ int n=moves[depth][branch].len;
+ int i,j;
+ for(i=0;i<(n-1);i++)
+ for(j=0;j<(n-(i+1));j++)
+ if(moves[depth][branch].data[j].weight < moves[depth][branch].data[j+1].weight){
+ //swap
+ AIMove temp;
+ temp=moves[depth][branch].data[j];
+ moves[depth][branch].data[j]=moves[depth][branch].data[j+1];
+ moves[depth][branch].data[j+1]=temp;
+
+ }
+ //streamsort(moves->data,moves->len);
+
+}
+
+//void aimoves_subtract(AIMoves *m1, const AIMoves *m2)
+//{
+// int i, j;
+//
+// for (i = 0; i < m1->len; i++)
+// for (j = 0; j < m2->len; j++)
+// if (m1->data[i].x == m2->data[j].x &&
+// m1->data[i].y == m2->data[j].y) {
+// aimoves_remove_index_fast(m1, i--);
+// break;
+// }
+//}
+//
+//const char *aiw_to_string(AIWEIGHT w)
+//{
+// static char buffer[32];
+//
+// switch (w) {
+// case AIW_WIN:
+// return "WIN";
+// case AIW_LOSE:
+// return "LOSS";
+// case AIW_NONE:
+// return "NONE";
+// default:
+// break;
+// }
+// if (w > 0)
+// g_snprintf(buffer, sizeof (buffer), "%010d (10^%.2f)", w,
+// log10((double)w));
+// else if (w < 0)
+// g_snprintf(buffer, sizeof (buffer), "%010d (-10^%.2f)", w,
+// log10((double)-w));
+// return buffer;
+//}
+
+/*
+ * Boards
+ */
+
+//Board board;
+//AllocChain *board_root = NULL;
+//int board_size=19, board_stride=21, move_no, move_last,
+// connect_k = 6, place_p = 2, start_q = 1;
+//int opt_det_ai=1;
+//gsize board_mem = 0;
+
+//Player players[PIECES] = {
+// { PLAYER_HUMAN, SEARCH_NONE, 0 },
+// { PLAYER_HUMAN, SEARCH_NONE, 0 },
+// { PLAYER_HUMAN, SEARCH_NONE, 0 },
+//};
+//
+//static GPtrArray *history = NULL;
+
+static void board_init(Board *b)
+{
+// memset((char*)b + sizeof (AllocChain), 0, sizeof (Board) -
+// sizeof (AllocChain));
+int i,j;
+for(i=0;idata[i][0]=PIECE_ERROR;
+for(i=0;idata[i][board_stride-1]=PIECE_ERROR;
+for(j=0;jdata[0][j]=PIECE_ERROR;
+for(j=0;jdata[board_stride-1][j]=PIECE_ERROR;
+for(i=1;idata[i][j]=PIECE_NONE;
+
+ //b->ac=(const AllocChain )0;
+ b->moves_left=0;
+ b->parent =0;
+ b->won =0;
+ b->win_x1 =0;
+ b->win_y1 =0;
+ b->win_x2 =0;
+ b->win_y2 =0;
+ b->turn =0;
+ b->move_x =0;
+ b->move_y =0;
+}
+
+//AllocChain *board_alloc(AllocChain *ac)
+//{
+// //Board *b = (Board*)ac;
+// //int i;
+//
+// ///* Clear the old board */
+// //if (b) {
+// // for (i = 1; i <= board_size; i++)
+// // memset(b->data + board_stride * i + 1, 0,
+// // board_size * sizeof (PIECE));
+// // board_init(b);
+// // return (AllocChain*)b;
+// //}
+//
+// ///* New boards are allocated with a 1-tile wide boundary of PIECE_ERROR
+// // around the edges */
+// //b = (Board*)g_slice_alloc0(board_mem);
+// //memset(b->data, PIECE_ERROR, sizeof (PIECE) * board_stride);
+// //for (i = 1; i <= board_size; i++) {
+// // b->data[i * board_stride] = PIECE_ERROR;
+// // memset(b->data + board_stride * i + 1, 0,
+// // board_size * sizeof (PIECE));
+// // b->data[(i + 1) * board_stride - 1] = PIECE_ERROR;
+// //}
+// //memset(b->data + board_stride * (board_stride - 1), PIECE_ERROR,
+// // sizeof (PIECE) * board_stride);
+// //board_init(&b);
+// //return (AllocChain*)b;
+//}
+
+void board_clean(Board *b)
+{
+ int y, x;
+
+ for (y = 0; y < board_size; y++)
+ for (x = 0; x < board_size; x++)
+ if (piece_at(b, x, y) >= PIECES)
+ place_piece_type(b, x, y, PIECE_NONE);
+}
+
+//void set_board_size(unsigned int size)
+//{
+// //if (board_size == size)
+// // return;
+// ////draw_marks(NULL, FALSE);
+// //achain_dealloc(&board_root, board_mem);
+// achain_dealloc(&aimoves_root, aimoves_mem);
+// //board_size = size;
+// //board_stride = size + 2;
+// //board_mem = sizeof (Board) + board_stride * board_stride *
+// // sizeof (PIECE);
+// aimoves_mem = sizeof (AIMoves) + size * size * sizeof (AIMove);
+//}
+
+//Board *board_at(unsigned int move)
+//{
+// if (move >= history->len)
+// return NULL;
+// return (Board*)g_ptr_array_index(history, move);
+//}
+
+int count_pieces(const Board *b, BCOORD x, BCOORD y, PIECE type, int dx, int dy,
+ PIECE *out)
+{
+ int i;
+ PIECE p = PIECE_NONE;
+
+ if (!dx && !dy)
+ return piece_at(b, x, y) == type ? 1 : 0;
+ for (i = 0; x >= 0 && x < board_size && y >= 0 && y < board_size; i++) {
+ p = piece_at(b, x, y);
+ if (p != type)
+ break;
+ x += dx;
+ y += dy;
+ }
+ /* this two lines create problem in synthesis preprocess ?? */
+ if (out)
+ *out = p;
+ return i;
+}
+
+gboolean check_win_full(const Board *b, BCOORD x, BCOORD y,
+ BCOORD *x1, BCOORD *y1, BCOORD *x2, BCOORD *y2)
+{
+ int i, c1, c2, xs[] = {1, 1, 0, -1}, ys[] = {0, 1, 1, 1};
+ PIECE type;
+ PIECE p;
+
+ type = piece_at(b, x, y);
+ if (type != PIECE_BLACK && type != PIECE_WHITE)
+ return FALSE;
+ for (i = 0; i < 4; i++) {
+ c1 = count_pieces(b, x, y, type, xs[i], ys[i], &p);
+ c2 = count_pieces(b, x, y, type, -xs[i], -ys[i], &p);
+ if (c1 + c2 > connect_k) {
+ //if (x1)
+ // *x1 = x + xs[i] * (c1 - 1);
+ //if (y1)
+ // *y1 = y + ys[i] * (c1 - 1);
+ //if (x2)
+ // *x2 = x - xs[i] * (c2 - 1);
+ //if (y2)
+ // *y2 = y - ys[i] * (c2 - 1);
+ return TRUE;
+ }
+ }
+ return FALSE;
+}
+
+///* Convert a boord coordinate to alpha representation */
+//const char *bcoord_to_alpha(BCOORD x)
+//{
+// static char buf[2][32];
+// static int which;
+// int i, divisor = 26;
+//
+// which = !which;
+// for (i = 0; i < sizeof (buf[which]) - 1; i++) {
+// div_t result;
+//
+// result = div(x, divisor);
+// buf[which][i] = 'a' + result.rem * 26 / divisor;
+// if (i)
+// buf[which][i]--;
+// x -= result.rem;
+// if (!x)
+// break;
+// divisor *= 26;
+// }
+// buf[which][i + 1] = 0;
+// return g_strreverse(buf[which]);
+//}
+
+//// Get a string representation of board x/y coordinates (d7, h16, etc)
+//const char *bcoords_to_string(BCOORD x, BCOORD y)
+//{
+// static char buf[2][32];
+// static int which;
+//
+// which = !which;
+// g_snprintf(buf[which], sizeof (buf[which]), "%s%d",
+// bcoord_to_alpha(x), board_size - y);
+// return buf[which];
+//}
+//
+/* Convert a string representation to coordinates */
+void string_to_bcoords(const char *str, BCOORD *x, BCOORD *y)
+{
+ *x = 0;
+ *y = 0;
+ while (*str && *str >= 'a' && *str <= 'z') {
+ *x *= 26;
+ *x += *str - 'a';
+ str++;
+ }
+ while (*str && *str >= '0' && *str <= '9') {
+ *y *= 10;
+ *y += *str - '0';
+ str++;
+ }
+ if (*y)
+ *y = board_size - *y;
+}
+
+const char *piece_to_string(PIECE piece)
+{
+ switch (piece) {
+ case PIECE_WHITE:
+ return "White";
+ case PIECE_BLACK:
+ return "Black";
+ case PIECE_NONE:
+ return "None";
+ case PIECE_ERROR:
+ return "Error";
+ default:
+ return "Mark";
+ }
+}
+
+char piece_to_char(PIECE piece)
+{
+ switch (piece) {
+ case PIECE_WHITE:
+ return 'W';
+ case PIECE_BLACK:
+ return 'B';
+ case PIECE_NONE:
+ return '_';
+ case PIECE_ERROR:
+ return 'E';
+ default:
+ return 'M';
+ }
+}
+
+//char *search_to_string(SEARCH s)
+//{
+// switch (s) {
+// case SEARCH_NONE:
+// return "No search";
+// case SEARCH_DFS:
+// return "Depth first search";
+// case SEARCHES:
+// break;
+// }
+// return "Unknown";
+//}
+
+//void go_to_move(unsigned int move)
+//{
+// Board board2;
+//
+// if (!history)
+// history = g_ptr_array_sized_new(32);
+// if (move > history->len)
+// move = history->len;
+// if (move == history->len) {
+// //board2 = board_new();
+// if (&board)
+// board_copy(&board, &board2);
+// g_ptr_array_add(history, &board2);
+// board2.parent = &board;
+// } else
+// //board2 = (Board*)g_ptr_array_index(history, move);
+// //&board = &board2;
+// move_no = move;
+// if (move_no > move_last)
+// move_last = move_no;
+//}
+
+//void clear_history(unsigned int from)
+//{
+// int i;
+//
+// if (!history)
+// return;
+// if (from >= history->len) {
+// g_warning("Attempted to clear future history");
+// return;
+// }
+// for (i = from; i < history->len; i++)
+// board_free(g_ptr_array_index(history, i));
+// g_ptr_array_remove_range(history, from, history->len - from);
+// move_last = from;
+//}
+/* Clear the board and history for a new game */
+void new_game(Board *board,unsigned int size)
+{
+ //tree_view_clear(1);
+ //clear_history(0);
+ //set_board_size(size);
+ //board = NULL;
+ //go_to_move(0);
+ //move_last=0;
+ //move_no=0;
+ board_init(board);
+ board->moves_left = start_q;
+ board->turn = PIECE_BLACK;
+ //draw_board();
+ //stop_ai();
+ //setup_move();
+}
+void board_copy(const Board *from, Board *to){
+int i,j;
+for(i=0;idata[i][j]=from->data[i][j];
+
+ to->ac= from->ac;
+ to->moves_left= from->moves_left;
+ to->parent = from->parent;
+ to->won = from->won;
+ to->win_x1 = from->win_x1;
+ to->win_y1 = from->win_y1;
+ to->win_x2 = from->win_x2;
+ to->win_y2 = from->win_y2;
+ to->turn = from->turn;
+ to->move_x = from->move_x;
+ to->move_y = from->move_y;
+
+
+}
trunk/XILINX/BUILD_SCC_SRCH/synth_src/state.cpp
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC_SRCH/synth_src/util.h
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/synth_src/util.h (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/synth_src/util.h (revision 17)
@@ -0,0 +1,34 @@
+/* util.cpp
+ June 9, 2011
+ Some helper functions.
+
+ Much of the code below is borrowed from Alastair Smith's program
+ from the 2010 FPT Othello competition
+
+ By Kevin Nam
+*/
+
+#ifndef _UTILS_H
+#define _UTILS_H
+
+using namespace std;
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+//#include "commondefs.h"
+
+/*********************** Portable random number generators *******************/
+
+void setup_port(int fd);
+int select_com_port(int argc, char **argv);
+char select_AI_colour (int argc, char **argv);
+int char_to_int (char c);
+void wait(double seconds);
+#endif
Index: trunk/XILINX/BUILD_SCC_SRCH/synth_src/connect6.h
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/synth_src/connect6.h (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/synth_src/connect6.h (revision 17)
@@ -0,0 +1,19 @@
+/*
+ connect6.h
+ June 9, 2011
+ This file contains the game AI
+ By Kevin Nam
+
+*/
+
+#ifndef _CONNECT6_H
+#define _CONNECT6_H
+
+int calculatepoints(char board[][19], int y, int x, char colour);
+int connect6ai(char board[][19], char colour, char move[4]);
+char check_for_win (char board[][19]);
+int check_board_full (char board[][19]);
+int check_move_validity (char board[][19],int y, int x);
+void print_board (char board[][19]);
+void print_board_file (char board[][19]);
+#endif
Index: trunk/XILINX/BUILD_SCC_SRCH/synth_src/main.cpp
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/synth_src/main.cpp (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/synth_src/main.cpp (revision 17)
@@ -0,0 +1,332 @@
+/* main.cpp
+ June 9,2011
+
+ Software connect6 AI program.
+ Have your board polling for its colour before starting this program.
+
+ commandline option:
+ -port
+ Ex: "./connect6 -port /dev/ttyUSB0"
+
+ By: Kevin Nam
+*/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "util.h"
+#include "connect6.h"
+#include "connect6_synth.h"
+#ifndef EMUL
+#include "pico.h"
+#endif
+#include "shared.h"
+
+#ifndef EMUL
+// The AI has as much time as it wants, but moves after 1 second. Default is to wait 2 seconds
+#define AI_WAIT_TIME 0.1
+
+// FPGA has 1 second to make its move
+#define MOVE_TIME_LIMIT 0.1
+#endif
+
+#ifdef EMUL
+// The AI has as much time as it wants, but moves after 1 second. Default is to wait 2 seconds
+#define AI_WAIT_TIME 0.1
+
+// FPGA has 1 second to make its move
+#define MOVE_TIME_LIMIT 1
+#endif
+using namespace std;
+extern "C" int main(int argc, char **argv);
+// commandline option: -port
+int main(int argc, char **argv){
+ //for verification two runs and a reference board
+ int i,j,k;
+ char ref_board[19][19] = {{ 0 }};
+
+ char board[19][19] = {{ 0 }};
+ char move[4];
+ char moveport[8]={0};
+ char moveportout[8]={0};
+ int movecount=0;
+ int y,x;
+ char winning_colour;
+
+#ifdef EMUL
+ // Get the serial port
+ int port = select_com_port(argc,argv);
+#endif
+ // Get software AI's colour
+ char AI_colour = select_AI_colour(argc,argv);
+ char FPGA_colour;
+#ifndef EMUL
+ int id = PICO_initialize_PPA(connect6ai_synth);
+#endif
+ // Take care of the first few moves (including sending the colour)
+ if (AI_colour == 'D'){
+ FPGA_colour = 'L';
+#ifdef EMUL
+ write(port, "L",1);
+#endif
+
+ wait(AI_WAIT_TIME);
+
+ // AI makes a move
+ connect6ai(board,AI_colour,move);
+ movecount++;
+ cout<<"AI MOVE: "<=20) return 0 ; //reducing length of simulation
+ winning_colour = check_for_win(board);
+ if (winning_colour == AI_colour){
+ cout<<"AI has won! " << movecount << " moves " << "Exiting."<
+#include
+#include
+#include "../shared.h"
+#include "../connectk.h"
+
+/*
+ * AIs
+ */
+
+static AI ais[] = {
+ { "human", "Human", NULL },
+ { "random", "Random", ai_random },
+ { "adjacent", "Adjacent", ai_adjacent },
+ { "threats", "Threats", ai_threats },
+ /*{ "windows", "Windows", ai_windows },*/
+ /*{ "priority", "Prioritized Threats", ai_priority },*/
+ { "sequences", "Sequences", ai_sequences },
+ { "mesh", "Mesh", ai_mesh },
+ { "montecarlo", "Monte Carlo", ai_monte_carlo },
+};
+
+static gboolean is_adjacent(const Board *b, BCOORD x, BCOORD y, int dist)
+{
+ int dx, dy, count;
+ PIECE p;
+
+ if (!piece_empty(piece_at(b, x, y)))
+ return FALSE;
+ for (dy = -1; dy < 2; dy++)
+ for (dx = -1; dx < 2; dx++) {
+ if (!dx && !dy)
+ continue;
+ count = count_pieces(b, x, y, PIECE_NONE, dx, dy, &p);
+ if (count - 1 < dist && p != PIECE_NONE)
+ return TRUE;
+ }
+ return FALSE;
+}
+
+AIMoves *enum_adjacent(const Board *b, int dist)
+{
+ AIMoves *moves;
+ AIMove move;
+
+ move.weight = AIW_NONE;
+ moves = aimoves_new();
+ for (move.y = 0; move.y < board_size; move.y++)
+ for (move.x = 0; move.x < board_size; move.x++)
+ if (is_adjacent(b, move.x, move.y, dist))
+ aimoves_append(moves, &move);
+ aimoves_shuffle(moves);
+ return moves;
+}
+
+AIMoves *ai_marks(const Board *b, PIECE min)
+{
+ AIMoves *moves = aimoves_new();
+ AIMove move;
+ PIECE p;
+
+ for (move.y = 0; move.y < board_size; move.y++)
+ for (move.x = 0; move.x < board_size; move.x++)
+ if ((p = piece_at(b, move.x, move.y)) >= min) {
+ move.weight = p - PIECE_THREAT0;
+ aimoves_set(moves, &move);
+ }
+ return moves;
+}
+
+AIMoves *ai_random(const Board *b)
+/* Returns a list of all empty tiles */
+{
+ AIMove move;
+ AIMoves *moves;
+
+ moves = aimoves_new();
+ for (move.y = 0; move.y < board_size; move.y++)
+ for (move.x = 0; move.x < board_size; move.x++)
+ if (piece_empty(piece_at(b, move.x, move.y))) {
+ move.weight =
+ g_random_int_range(AIW_MIN, AIW_MAX);
+ aimoves_append(moves, &move);
+ }
+ return moves;
+}
+
+AIMoves *ai_adjacent(const Board *b)
+{
+ AIMove move;
+ AIMoves *moves;
+
+ /* Get all open tiles adjacent to any piece */
+ moves = enum_adjacent(b, 1);
+ if (moves->len)
+ return moves;
+
+ /* Play in the middle if there are no open adjacent tiles */
+ move.x = board_size / 2;
+ move.y = board_size / 2;
+ move.weight = AIW_NONE;
+ aimoves_append(moves, &move);
+ return moves;
+}
+
+const char *player_to_string(PLAYER p)
+{
+ return ais[p].l_desc;
+}
+
+int number_of_ais(void)
+{
+ return sizeof (ais) / sizeof (*ais);
+}
+
+AI *ai(int n)
+{
+ if (n >= 0 && n < number_of_ais())
+ return ais + n;
+ return NULL;
+}
+
trunk/XILINX/BUILD_SCC_SRCH/synth_src/ai.c
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC_SRCH/synth_src/main.cpp.base
===================================================================
--- trunk/XILINX/BUILD_SCC_SRCH/synth_src/main.cpp.base (nonexistent)
+++ trunk/XILINX/BUILD_SCC_SRCH/synth_src/main.cpp.base (revision 17)
@@ -0,0 +1,305 @@
+/* main.cpp
+ June 9,2011
+
+ Software connect6 AI program.
+ Have your board polling for its colour before starting this program.
+
+ commandline option:
+ -port
+ Ex: "./connect6 -port /dev/ttyUSB0"
+
+ By: Kevin Nam
+*/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "util.h"
+#include "connect6.h"
+#include "connect6_synth.h"
+#ifndef EMUL
+#include "pico.h"
+#endif
+#include "shared.h"
+
+// The AI has as much time as it wants, but moves after 1 second. Default is to wait 2 seconds
+#define AI_WAIT_TIME 0.1
+
+// FPGA has 1 second to make its move
+#define MOVE_TIME_LIMIT 0.1
+
+using namespace std;
+extern "C" int main(int argc, char **argv);
+// commandline option: -port
+int main(int argc, char **argv){
+ //for verification two runs and a reference board
+ int i,j,k;
+ char ref_board[19][19] = {{ 0 }};
+
+ char board[19][19] = {{ 0 }};
+ char move[4];
+ char moveport[8]={0};
+ char moveportout[8]={0};
+ int movecount=0;
+ int y,x;
+ char winning_colour;
+
+#ifdef EMUL
+ // Get the serial port
+ int port = select_com_port(argc,argv);
+#endif
+ // Get software AI's colour
+ char AI_colour = select_AI_colour(argc,argv);
+ char FPGA_colour;
+#ifndef EMUL
+ int id = PICO_initialize_PPA(connect6ai_synth);
+#endif
+ // Take care of the first few moves (including sending the colour)
+ if (AI_colour == 'D'){
+ FPGA_colour = 'L';
+#ifdef EMUL
+ write(port, "L",1);
+#endif
+
+ wait(AI_WAIT_TIME);
+
+ // AI makes a move
+ connect6ai(board,AI_colour,move);
+ movecount++;
+ cout<<"AI MOVE: "<=20) return 0 ; //reducing length of simulation
+ winning_colour = check_for_win(board);
+ if (winning_colour == AI_colour){
+ cout<<"AI has won! " << movecount << " moves " << "Exiting."<main.cpp
+ cp ${SYNTH_SRC}/main.cpp.base ${SYNTH_SRC}/main.cpp
+ ${SCC} ${SCC_SCRIPTS}/run_imp_window.tcl
+ echo "Done" > imp_window.tag
+imp_line.tag: imp_window.tag
+ sed -s 's/\\TCAB_NAME/threat_line/g' ${SYNTH_SRC}/main.cpp.base >${SYNTH_SRC}/main.cpp
+ #cp ${SYNTH_SRC}/main.cpp.base ${SYNTH_SRC}/main.cpp
+ ${SCC} ${SCC_SCRIPTS}/run_imp_line.tcl
+ echo "Done" > imp_line.tag
+imp_marks.tag:
+ sed -s 's/\\TCAB_NAME/ai_marks/g' ${SYNTH_SRC}/main.cpp.base >${SYNTH_SRC}/main.cpp
+ #cp ${SYNTH_SRC}/main.cpp.base ${SYNTH_SRC}/main.cpp
+ ${SCC} ${SCC_SCRIPTS}/run_imp_marks.tcl
+ echo "Done" > imp_marks.tag
+imp_sort.tag:
+ sed -s 's/\\TCAB_NAME/streamsort/g' ${SYNTH_SRC}/main.cpp.base >${SYNTH_SRC}/main.cpp
+ #cp ${SYNTH_SRC}/main.cpp.base ${SYNTH_SRC}/main.cpp
+ ${SCC} ${SCC_SCRIPTS}/run_imp_sort.tcl
+ echo "Done" > imp_sort.tag
+imp_threat.tag: imp_line.tag
+ sed -s 's/\\TCAB_NAME/ai_threats/g' ${SYNTH_SRC}/main.cpp.base >${SYNTH_SRC}/main.cpp
+ #cp ${SYNTH_SRC}/main.cpp.base ${SYNTH_SRC}/main.cpp
+ ${SCC} ${SCC_SCRIPTS}/run_imp_threat.tcl
+ echo "Done" > imp_threat.tag
+imp_adjacent.tag:
+ #cp ${SYNTH_SRC}/main.cpp.base ${SYNTH_SRC}/main.cpp
+ sed -s 's/\\TCAB_NAME/ai_adjacent/g' ${SYNTH_SRC}/main.cpp.base >${SYNTH_SRC}/main.cpp
+ ${SCC} ${SCC_SCRIPTS}/run_imp_adjacent.tcl
+ echo "Done" > imp_adjacent.tag
+imp_search.tag: imp_threat.tag
+ sed -s 's/\\TCAB_NAME/search/g' ${SYNTH_SRC}/main.cpp.base >${SYNTH_SRC}/main.cpp
+ ${SCC} ${SCC_SCRIPTS}/run_imp_search.tcl
+ echo "Done" > imp_search.tag
+imp_connect.tag: imp_search.tag imp_adjacent.tag
+ sed -s 's/\\TCAB_NAME/connect6ai_synth/g' ${SYNTH_SRC}/main.cpp.base >${SYNTH_SRC}/main.cpp
+ ${SCC} ${SCC_SCRIPTS}/run_imp_connect.tcl
+ echo "Done" > imp_connect.tag
+
+xilinx_synth:
+ cp -r ./imp_connect/rtl_package/ ./
+ cp SP6/SP6.do_synth imp_connect/rtl_package/synth/synplify_fpga/do_synth
+ cp SP6/SP6.synplify.tcl imp_connect/rtl_package/synth/synplify_fpga/synplify.tcl
+ cp SP6/SP6.ucf imp_connect/rtl_package/synth/synplify_fpga/
+ echo -e 'all:\n\t./do_synth' > imp_connect/rtl_package/synth/synplify_fpga/makefile
+ make -C imp_connect/rtl_package/synth/synplify_fpga/
+
+test:
+ ../scripts/serial_port_setup.sh
+ rm -f ./test.result
+ for i in `seq 1 100` ; do ../connect6 -port /dev/ttyS0 -player L >> test.result 2>&1; done
+ #grep "FPGA has won" ./test.result | wc -l
+ #grep "AI has won" ./test.result | wc -l
+ #grep "TIE" ./test.result | wc -l
+ python ../scripts/esult.py
+pgm:
+ cp ./rtl_package/synth/altera_fpga/run/DE2.sof ./
+ quartus_pgm -c USB-Blaster -m jtag -o "p;DE2.sof"
+
+
+prof:
+ valgrind --tool=callgrind ./connect6 -player L
+ kcachegrind
+
+altera_clean:
+ rm -rf ./rtl_package/
+
+ultraclean: altera_clean
+ rm -rf *.tag imp_line imp_marks imp_threat imp_choose imp_adjacent imp_connect imp_window Logs
Index: trunk/XILINX/BUILD_SCC/scc_scripts/run_imp_line.tcl
===================================================================
--- trunk/XILINX/BUILD_SCC/scc_scripts/run_imp_line.tcl (nonexistent)
+++ trunk/XILINX/BUILD_SCC/scc_scripts/run_imp_line.tcl (revision 17)
@@ -0,0 +1,51 @@
+set_project_params -directory ./
+set_project_params -results myboard.txt
+set_project_params -sources "synth_src/connect6.cpp synth_src/connect6_synth.cpp synth_src/main.cpp synth_src/q.cpp synth_src/state.cpp synth_src/threats.cpp synth_src/util.cpp"
+set_project_params -headers "synth_src/connect6.h synth_src/connect6_synth.h synth_src/q.hpp synth_src/shared.h synth_src/threats.h synth_src/util.h"
+set_project_params -cache_result_files no
+set_project_params -cache_data_files yes
+
+if [file exists imp_line] { delete_implementation imp_line }
+create_implementation imp_line
+
+set_implementation_params -systemc_source no
+set_implementation_params -memory_return_path_external_delay 0%
+set_implementation_params -memory_forward_path_external_delay 0%
+set_implementation_params -instream_forward_path_external_delay 0%
+set_implementation_params -import_tcab "imp_window"
+set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g"
+set_implementation_params -outstream_return_path_external_delay 0%
+set_implementation_params -appfiles "synth_src/state.cpp synth_src/threats.cpp"
+set_implementation_params -proc threat_line
+set_implementation_params -memory_forward_boundary_register infer
+set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive"
+#set_implementation_params -task_ii 441
+set_loop_params -ii 1
+#set_implementation_params -techlib altera-cyclone3
+#set_implementation_params -device ep3c25-ea144-7
+set_implementation_params -techlib xilinx-spartan6
+set_implementation_params -device xc6slx45t-fgg484-3
+set_implementation_params -init_data_registers yes
+set_implementation_params -memory_return_boundary_register infer
+set_implementation_params -cexec_args "-port /dev/ttyS0 -player L"
+set_implementation_params -host_memory_access never
+set_implementation_params -outstream_forward_path_external_delay 0%
+set_implementation_params -build_tcab yes
+set_implementation_params -reset_data_registers yes
+set_implementation_params -task_overlap 0
+set_implementation_params -instream_return_path_external_delay 0%
+set_implementation_params -simulator modelsim
+set_implementation_params -clock_freq 50
+
+
+setvar preprocess_auxopts "-L"
+
+
+csim -golden -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
+preprocess
+csim -preprocess -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
+schedule
+csim -schedule -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
+synthesize
+create_rtl_package -force
+
Index: trunk/XILINX/BUILD_SCC/scc_scripts/run_imp_threat.tcl
===================================================================
--- trunk/XILINX/BUILD_SCC/scc_scripts/run_imp_threat.tcl (nonexistent)
+++ trunk/XILINX/BUILD_SCC/scc_scripts/run_imp_threat.tcl (revision 17)
@@ -0,0 +1,53 @@
+set_project_params -directory ./
+set_project_params -results myboard.txt
+set_project_params -sources "synth_src/connect6.cpp synth_src/connect6_synth.cpp synth_src/main.cpp synth_src/q.cpp synth_src/state.cpp synth_src/threats.cpp synth_src/util.cpp"
+set_project_params -headers "synth_src/connect6.h synth_src/connect6_synth.h synth_src/q.hpp synth_src/shared.h synth_src/threats.h synth_src/util.h"
+set_project_params -cache_result_files no
+set_project_params -cache_data_files yes
+
+if [file exists imp_threat] { delete_implementation imp_threat }
+create_implementation imp_threat
+
+set_implementation_params -systemc_source no
+#set_implementation_params -instream_boundary_register infer
+set_implementation_params -memory_return_path_external_delay 0%
+set_implementation_params -memory_forward_path_external_delay 0%
+#set_implementation_params -instream_forward_path_external_delay 0%
+set_implementation_params -import_tcab "imp_line"
+set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g"
+#set_implementation_params -outstream_return_path_external_delay 0%
+set_implementation_params -appfiles "synth_src/state.cpp synth_src/threats.cpp"
+set_implementation_params -proc ai_threats
+set_implementation_params -memory_forward_boundary_register infer
+set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive"
+set_implementation_params -memory_return_boundary_register infer
+set_implementation_params -cexec_args "-port /dev/ttyS0 -player L"
+set_implementation_params -host_memory_access never
+#set_implementation_params -techlib altera-cyclone3
+#set_implementation_params -device ep3c25-ea144-7
+set_implementation_params -techlib xilinx-spartan6
+set_implementation_params -device xc6slx45t-fgg484-3
+#set_implementation_params -always_enabled_ppa yes
+set_implementation_params -init_data_registers yes
+#set_implementation_params -outstream_forward_path_external_delay 0%
+#set_implementation_params -outstream_boundary_register infer
+set_implementation_params -build_tcab yes
+set_implementation_params -reset_data_registers yes
+set_implementation_params -task_overlap 0
+#set_implementation_params -instream_return_path_external_delay 0%
+set_implementation_params -simulator modelsim
+set_implementation_params -clock_freq 50
+set_implementation_params -allow_latency_violation no
+
+
+setvar schedule_auxopts "-j"
+
+
+csim -golden -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
+preprocess
+csim -preprocess -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
+schedule
+csim -schedule -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
+synthesize
+create_rtl_package -force
+#vlogsim -online -detailed_perf_report
Index: trunk/XILINX/BUILD_SCC/scc_scripts/run_imp_window.tcl
===================================================================
--- trunk/XILINX/BUILD_SCC/scc_scripts/run_imp_window.tcl (nonexistent)
+++ trunk/XILINX/BUILD_SCC/scc_scripts/run_imp_window.tcl (revision 17)
@@ -0,0 +1,50 @@
+set_project_params -directory ./
+set_project_params -results myboard.txt
+set_project_params -sources "synth_src/connect6.cpp synth_src/connect6_synth.cpp synth_src/main.cpp synth_src/q.cpp synth_src/state.cpp synth_src/threats.cpp synth_src/util.cpp"
+set_project_params -headers "synth_src/connect6.h synth_src/connect6_synth.h synth_src/q.hpp synth_src/shared.h synth_src/threats.h synth_src/util.h"
+set_project_params -cache_result_files no
+set_project_params -cache_data_files yes
+
+if [file exists imp_window] { delete_implementation imp_window }
+create_implementation imp_window
+
+set_implementation_params -systemc_source no
+set_implementation_params -memory_return_path_external_delay 0%
+set_implementation_params -memory_forward_path_external_delay 0%
+set_implementation_params -instream_forward_path_external_delay 0%
+set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID"
+set_implementation_params -outstream_return_path_external_delay 0%
+set_implementation_params -appfiles "synth_src/state.cpp synth_src/threats.cpp"
+set_implementation_params -proc threat_window
+set_implementation_params -memory_forward_boundary_register infer
+set_implementation_params -architectural_pipelinability "1"
+set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive"
+#set_implementation_params -techlib altera-cyclone3
+#set_implementation_params -device ep3c25-ea144-7
+set_implementation_params -techlib xilinx-spartan6
+set_implementation_params -device xc6slx45t-fgg484-3
+set_implementation_params -memory_return_boundary_register infer
+set_implementation_params -cexec_args "-port /dev/ttyS0 -player L"
+set_implementation_params -host_memory_access never
+set_implementation_params -init_data_registers yes
+set_implementation_params -outstream_forward_path_external_delay 0%
+set_implementation_params -build_tcab yes
+set_implementation_params -reset_data_registers yes
+set_implementation_params -task_overlap infer
+set_implementation_params -instream_return_path_external_delay 0%
+set_implementation_params -simulator modelsim
+set_implementation_params -clock_freq 50
+
+
+
+#set_loop_params -ii 1
+
+csim -golden -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
+preprocess
+csim -preprocess -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
+schedule
+csim -schedule -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
+synthesize
+create_rtl_package
+#vlogsim -online -ccompiler_args "-g" -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -sccompiler_args "-DDONT_VERIFY_PPAID" -cexec_args "-port /dev/ttyS0 -player L" -simulator modelsim -vcompiler_args -vexec_args
+
Index: trunk/XILINX/BUILD_SCC/scc_scripts/run_imp_sort.tcl
===================================================================
--- trunk/XILINX/BUILD_SCC/scc_scripts/run_imp_sort.tcl (nonexistent)
+++ trunk/XILINX/BUILD_SCC/scc_scripts/run_imp_sort.tcl (revision 17)
@@ -0,0 +1,50 @@
+set_project_params -directory ./
+set_project_params -results myboard.txt
+set_project_params -sources "synth_src/connect6.cpp synth_src/connect6_synth.cpp synth_src/main.cpp synth_src/q.cpp synth_src/state.cpp synth_src/threats.cpp synth_src/util.cpp"
+set_project_params -headers "synth_src/connect6.h synth_src/connect6_synth.h synth_src/q.hpp synth_src/shared.h synth_src/threats.h synth_src/util.h"
+set_project_params -cache_result_files no
+set_project_params -cache_data_files yes
+
+if [file exists imp_sort] { delete_implementation imp_sort }
+create_implementation imp_sort
+
+set_implementation_params -systemc_source no
+set_implementation_params -instream_boundary_register infer
+set_implementation_params -memory_return_path_external_delay 0%
+set_implementation_params -memory_forward_path_external_delay 0%
+set_implementation_params -instream_forward_path_external_delay 0%
+set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID -g -g -g -g -g"
+set_implementation_params -outstream_return_path_external_delay 0%
+set_implementation_params -appfile synth_src/threats.cpp
+set_implementation_params -proc streamsort
+set_implementation_params -memory_forward_boundary_register infer
+set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive"
+#set_implementation_params -techlib altera-cyclone4gx
+#set_implementation_params -device ep4cgx110c-fc23-7
+set_implementation_params -techlib xilinx-spartan6
+set_implementation_params -device xc6slx45-csg324-2
+set_implementation_params -memory_return_boundary_register infer
+set_implementation_params -cexec_args "-port /dev/ttyS0 -player L"
+set_implementation_params -host_memory_access never
+set_implementation_params -init_data_registers yes
+set_implementation_params -outstream_forward_path_external_delay 0%
+set_implementation_params -outstream_boundary_register infer
+set_implementation_params -build_tcab yes
+set_implementation_params -reset_data_registers yes
+set_implementation_params -task_overlap infer
+set_implementation_params -instream_return_path_external_delay 0%
+set_implementation_params -simulator modelsim
+set_implementation_params -clock_freq 100
+
+
+
+set_loop_params -ii 1
+
+csim -golden -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
+preprocess
+csim -preprocess -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
+schedule
+csim -schedule -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
+synthesize
+create_rtl_package -force
+
Index: trunk/XILINX/BUILD_SCC/scc_scripts/run_imp_connect.tcl
===================================================================
--- trunk/XILINX/BUILD_SCC/scc_scripts/run_imp_connect.tcl (nonexistent)
+++ trunk/XILINX/BUILD_SCC/scc_scripts/run_imp_connect.tcl (revision 17)
@@ -0,0 +1,54 @@
+set SYNTH_SRC "synth_src"
+set_project_params -directory ./
+set_project_params -results myboard.txt
+set_project_params -sources "${SYNTH_SRC}/connect6.cpp ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/main.cpp ${SYNTH_SRC}/q.cpp ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/util.cpp"
+set_project_params -headers "${SYNTH_SRC}/connect6.h ${SYNTH_SRC}/connect6_synth.h ${SYNTH_SRC}/q.hpp ${SYNTH_SRC}/shared.h ${SYNTH_SRC}/threats.h ${SYNTH_SRC}/util.h"
+
+if [file exists imp_connect] { delete_implementation imp_connect }
+create_implementation imp_connect
+
+set_implementation_params -systemc_source no
+set_implementation_params -memory_return_path_external_delay 0%
+set_implementation_params -memory_forward_path_external_delay 0%
+set_implementation_params -instream_forward_path_external_delay 0%
+set_implementation_params -import_tcab "imp_threat imp_adjacent"
+set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID"
+set_implementation_params -outstream_return_path_external_delay 0%
+set_implementation_params -appfiles "${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/connect6_synth.cpp"
+set_implementation_params -proc connect6ai_synth
+set_implementation_params -memory_forward_boundary_register infer
+set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive"
+#set_implementation_params -techlib altera-cyclone3
+#set_implementation_params -device ep3c25-ea144-7
+set_implementation_params -techlib xilinx-spartan6
+set_implementation_params -device xc6slx45t-fgg484-3
+set_implementation_params -memory_return_boundary_register infer
+set_implementation_params -cexec_args "-port /dev/ttyS0 -player L"
+set_implementation_params -host_memory_access never,,,
+set_implementation_params -init_data_registers yes
+set_implementation_params -outstream_forward_path_external_delay 0%
+set_implementation_params -build_tcab yes
+set_implementation_params -reset_data_registers yes
+set_implementation_params -instream_return_path_external_delay 0%
+set_implementation_params -clock_freq 50
+set_implementation_params -allow_latency_violation no
+set_implementation_params -tcab_deployment conditional_outputs:yes
+#setvar preprocess_auxopts "-Xmax_loops_for_jamming=15"
+#set_implementation_params -user_supplied_fpga_memory_read_write_ports separate
+#set_implementation_params -internal_blockram_memory_read_write_ports separate
+
+
+
+setvar schedule_auxopts "-j"
+
+csim -golden -cexec_args "-port /dev/ttyS0 -player L"
+preprocess
+csim -preprocess -cexec_args "-port /dev/ttyS0 -player L"
+schedule
+csim -schedule -cexec_args "-port /dev/ttyS0 -player L"
+synthesize
+#csim -synthesize -dump_memory_access_trace -sim_after_synth_phase 5
+create_rtl_package
+#vlogsim -online -detailed_perf_report
+#set_implementation_params -simulator modelsim
+#vlogsim -offline -dotasks 1-30
Index: trunk/XILINX/BUILD_SCC/scc_scripts/run_imp_adjacent.tcl
===================================================================
--- trunk/XILINX/BUILD_SCC/scc_scripts/run_imp_adjacent.tcl (nonexistent)
+++ trunk/XILINX/BUILD_SCC/scc_scripts/run_imp_adjacent.tcl (revision 17)
@@ -0,0 +1,49 @@
+set SYNTH_SRC "synth_src"
+set_project_params -directory ./
+set_project_params -results myboard.txt
+set_project_params -sources "${SYNTH_SRC}/connect6.cpp ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/main.cpp ${SYNTH_SRC}/q.cpp ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/util.cpp"
+set_project_params -headers "${SYNTH_SRC}/connect6.h ${SYNTH_SRC}/connect6_synth.h ${SYNTH_SRC}/q.hpp ${SYNTH_SRC}/shared.h ${SYNTH_SRC}/threats.h ${SYNTH_SRC}/util.h"
+
+if [file exists imp_adjacent] { delete_implementation imp_adjacent }
+create_implementation imp_adjacent
+
+set_implementation_params -systemc_source no
+set_implementation_params -memory_return_path_external_delay 0%
+set_implementation_params -memory_forward_path_external_delay 0%
+set_implementation_params -instream_forward_path_external_delay 0%
+set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID"
+set_implementation_params -outstream_return_path_external_delay 0%
+set_implementation_params -appfiles " ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp"
+set_implementation_params -proc ai_adjacent
+set_implementation_params -memory_forward_boundary_register infer
+set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive"
+set_implementation_params -memory_return_boundary_register infer
+set_implementation_params -techlib xilinx-spartan6
+set_implementation_params -device xc6slx45t-fgg484-3
+#set_implementation_params -techlib altera-cyclone3
+#set_implementation_params -device ep3c25-ea144-7
+set_implementation_params -cexec_args "-port /dev/ttyS0 -player L"
+set_implementation_params -host_memory_access never,,,
+set_implementation_params -init_data_registers yes
+set_implementation_params -outstream_forward_path_external_delay 0%
+set_implementation_params -build_tcab yes
+set_implementation_params -reset_data_registers yes
+set_implementation_params -instream_return_path_external_delay 0%
+set_implementation_params -clock_freq 50
+set_implementation_params -allow_latency_violation no
+#set_implementation_params -user_supplied_fpga_memory_read_write_ports separate
+#set_implementation_params -internal_blockram_memory_read_write_ports separate
+
+
+
+
+csim -golden -cexec_args "-port /dev/ttyS0 -player L"
+preprocess
+csim -preprocess -cexec_args "-port /dev/ttyS0 -player L"
+schedule
+csim -schedule -cexec_args "-port /dev/ttyS0 -player L"
+synthesize
+#csim -synthesize -dump_memory_access_trace
+create_rtl_package
+#set_implementation_params -simulator modelsim
+#vlogsim -offline -dotasks 1-30
Index: trunk/XILINX/BUILD_SCC/scc_scripts/run_imp_threat_flat.tcl
===================================================================
--- trunk/XILINX/BUILD_SCC/scc_scripts/run_imp_threat_flat.tcl (nonexistent)
+++ trunk/XILINX/BUILD_SCC/scc_scripts/run_imp_threat_flat.tcl (revision 17)
@@ -0,0 +1,53 @@
+set SYNTH_SRC "synth_src"
+set_project_params -directory ./
+set_project_params -results myboard.txt
+set_project_params -sources "${SYNTH_SRC}/connect6.cpp ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/main.cpp ${SYNTH_SRC}/q.cpp ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/util.cpp"
+set_project_params -headers "${SYNTH_SRC}/connect6.h ${SYNTH_SRC}/connect6_synth.h ${SYNTH_SRC}/q.hpp ${SYNTH_SRC}/shared.h ${SYNTH_SRC}/threats.h ${SYNTH_SRC}/util.h"
+
+if [file exists imp_threat_flat] { delete_implementation imp_threat_flat }
+create_implementation imp_threat_flat
+
+set_implementation_params -systemc_source no
+set_implementation_params -memory_return_path_external_delay 0%
+set_implementation_params -memory_forward_path_external_delay 0%
+set_implementation_params -instream_forward_path_external_delay 0%
+#set_implementation_params -import_tcab "imp_line"
+#imp_line"
+set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID"
+set_implementation_params -outstream_return_path_external_delay 0%
+set_implementation_params -appfiles "${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp"
+set_implementation_params -proc ai_threats
+set_implementation_params -memory_forward_boundary_register infer
+set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive"
+set_implementation_params -techlib altera-cyclone3
+set_implementation_params -memory_return_boundary_register infer
+set_implementation_params -cexec_args "-port /dev/ttyS0 -player L"
+set_implementation_params -host_memory_access never
+set_implementation_params -device ep3c25-ea144-7
+set_implementation_params -force_independent_stalldomain_tcab yes
+set_implementation_params -init_data_registers yes
+set_implementation_params -outstream_forward_path_external_delay 0%
+set_implementation_params -build_tcab yes
+set_implementation_params -reset_data_registers yes
+set_implementation_params -instream_return_path_external_delay 0%
+set_implementation_params -clock_freq 100
+set_implementation_params -allow_latency_violation no
+#set_implementation_params -user_supplied_fpga_memory_read_write_ports separate
+#set_implementation_params -internal_blockram_memory_read_write_ports separate
+
+
+
+
+csim -golden -cexec_args "-port /dev/ttyS0 -player L"
+preprocess
+csim -preprocess -cexec_args "-port /dev/ttyS0 -player L"
+schedule
+csim -schedule -cexec_args "-port /dev/ttyS0 -player L"
+synthesize
+#csim -synthesize -dump_memory_access_trace
+#csim -synthesize with -dump_memory_access_trace -sim_after_synth_phase 5
+create_rtl_package
+#csim -synthesize
+
+#set_implementation_params -simulator modelsim
+#vlogsim -offline -dotasks 1-30
Index: trunk/XILINX/BUILD_SCC/scc_scripts/run_imp_marks.tcl
===================================================================
--- trunk/XILINX/BUILD_SCC/scc_scripts/run_imp_marks.tcl (nonexistent)
+++ trunk/XILINX/BUILD_SCC/scc_scripts/run_imp_marks.tcl (revision 17)
@@ -0,0 +1,48 @@
+set_project_params -directory ./
+set_project_params -results myboard.txt
+set_project_params -sources "synth_src/connect6.cpp synth_src/connect6_synth.cpp synth_src/main.cpp synth_src/q.cpp synth_src/state.cpp synth_src/threats.cpp synth_src/util.cpp"
+set_project_params -headers "synth_src/connect6.h synth_src/connect6_synth.h synth_src/q.hpp synth_src/shared.h synth_src/threats.h synth_src/util.h"
+set_project_params -cache_result_files no
+set_project_params -cache_data_files yes
+
+if [file exists imp_marks] { delete_implementation imp_marks }
+create_implementation imp_marks
+
+set_implementation_params -systemc_source no
+set_implementation_params -memory_return_path_external_delay 0%
+set_implementation_params -memory_forward_path_external_delay 0%
+set_implementation_params -instream_forward_path_external_delay 0%
+set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID -g -g -g -g"
+set_implementation_params -outstream_return_path_external_delay 0%
+set_implementation_params -appfiles "synth_src/state.cpp synth_src/threats.cpp"
+set_implementation_params -proc ai_marks
+set_implementation_params -memory_forward_boundary_register infer
+set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive"
+#set_implementation_params -techlib altera-cyclone4gx
+#set_implementation_params -device ep4cgx110c-fc23-7
+set_implementation_params -techlib xilinx-spartan6
+set_implementation_params -device xc6slx45-csg324-2
+set_implementation_params -memory_return_boundary_register infer
+set_implementation_params -cexec_args "-port /dev/ttyS0 -player L"
+set_implementation_params -host_memory_access never
+set_implementation_params -init_data_registers yes
+set_implementation_params -outstream_forward_path_external_delay 0%
+set_implementation_params -build_tcab yes
+set_implementation_params -reset_data_registers yes
+set_implementation_params -task_overlap 0
+set_implementation_params -instream_return_path_external_delay 0%
+set_implementation_params -simulator modelsim
+set_implementation_params -clock_freq 100
+
+
+
+set_loop_params -ii 3
+
+csim -golden -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
+preprocess
+csim -preprocess -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
+schedule
+csim -schedule -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
+synthesize
+create_rtl_package
+
Index: trunk/XILINX/BUILD_SCC/scc_scripts/run_imp_choose.tcl
===================================================================
--- trunk/XILINX/BUILD_SCC/scc_scripts/run_imp_choose.tcl (nonexistent)
+++ trunk/XILINX/BUILD_SCC/scc_scripts/run_imp_choose.tcl (revision 17)
@@ -0,0 +1,49 @@
+set SYNTH_SRC "synth_src"
+set_project_params -directory ./
+set_project_params -results myboard.txt
+set_project_params -sources "${SYNTH_SRC}/connect6.cpp ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/main.cpp ${SYNTH_SRC}/q.cpp ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/util.cpp"
+set_project_params -headers "${SYNTH_SRC}/connect6.h ${SYNTH_SRC}/connect6_synth.h ${SYNTH_SRC}/q.hpp ${SYNTH_SRC}/shared.h ${SYNTH_SRC}/threats.h ${SYNTH_SRC}/util.h"
+
+if [file exists imp_choose] { delete_implementation imp_choose }
+create_implementation imp_choose
+
+set_implementation_params -systemc_source no
+set_implementation_params -memory_return_path_external_delay 0%
+set_implementation_params -memory_forward_path_external_delay 0%
+set_implementation_params -instream_forward_path_external_delay 0%
+set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID"
+set_implementation_params -outstream_return_path_external_delay 0%
+set_implementation_params -appfiles "${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/connect6_synth.cpp"
+set_implementation_params -proc aimoves_choose
+set_implementation_params -memory_forward_boundary_register infer
+set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive"
+set_implementation_params -techlib altera-cyclone3
+set_implementation_params -memory_return_boundary_register infer
+set_implementation_params -cexec_args "-port /dev/ttyS0 -player L"
+set_implementation_params -host_memory_access never,,,
+set_implementation_params -device ep3c25-ea144-7
+set_implementation_params -init_data_registers yes
+set_implementation_params -outstream_forward_path_external_delay 0%
+set_implementation_params -build_tcab yes
+set_implementation_params -reset_data_registers yes
+set_implementation_params -instream_return_path_external_delay 0%
+set_implementation_params -clock_freq 100
+set_implementation_params -allow_latency_violation no
+#set_implementation_params -memory_size "moves.data:moves_size"
+#set_implementation_params -user_supplied_fpga_memory_read_write_ports separate
+#set_implementation_params -internal_blockram_memory_read_write_ports separate
+
+
+
+
+csim -golden -cexec_args "-port /dev/ttyS0 -player L"
+preprocess
+csim -preprocess -cexec_args "-port /dev/ttyS0 -player L"
+schedule
+csim -schedule -cexec_args "-port /dev/ttyS0 -player L"
+synthesize
+#csim -synthesize -dump_memory_access_trace
+create_rtl_package
+
+#set_implementation_params -simulator modelsim
+#vlogsim -offline -dotasks 1-30
Index: trunk/XILINX/BUILD_SCC/.picoferc
===================================================================
--- trunk/XILINX/BUILD_SCC/.picoferc (nonexistent)
+++ trunk/XILINX/BUILD_SCC/.picoferc (revision 17)
@@ -0,0 +1,17 @@
+bgcap 0
+c_compiler gcc
+cache_data_files yes
+cache_result_files no
+cpp_compiler g++
+editor xterm -e vi %FILE% &
+filter ERROR WARNING INTERNAL_ERROR
+headers synth_src/connect6.h synth_src/connect6_synth.h synth_src/q.hpp synth_src/shared.h synth_src/threats.h synth_src/util.h
+logdir Logs
+maxhist 0
+outputmode normal
+read_only_files 0
+results myboard.txt
+sc_compiler g++
+source_directory ./
+sources synth_src/connect6.cpp synth_src/connect6_synth.cpp synth_src/main.cpp synth_src/q.cpp synth_src/state.cpp synth_src/threats.cpp synth_src/util.cpp
+transcript 0
Index: trunk/XILINX/BUILD_SCC/SP6/constraints.sdc
===================================================================
--- trunk/XILINX/BUILD_SCC/SP6/constraints.sdc (nonexistent)
+++ trunk/XILINX/BUILD_SCC/SP6/constraints.sdc (revision 17)
@@ -0,0 +1,5 @@
+# clocks
+
+create_clock -period 30.0 -name clk [get_ports OSC_27]
+# input/output delays
+
Index: trunk/XILINX/BUILD_SCC/SP6/SP6.xise
===================================================================
--- trunk/XILINX/BUILD_SCC/SP6/SP6.xise (nonexistent)
+++ trunk/XILINX/BUILD_SCC/SP6/SP6.xise (revision 17)
@@ -0,0 +1,830 @@
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Index: trunk/XILINX/BUILD_SCC/SP6/RS232_Controller.v
===================================================================
--- trunk/XILINX/BUILD_SCC/SP6/RS232_Controller.v (nonexistent)
+++ trunk/XILINX/BUILD_SCC/SP6/RS232_Controller.v (revision 17)
@@ -0,0 +1,18 @@
+module RS232_Controller(oDATA,iDATA,oTxD,oTxD_Busy,iTxD_Start,
+ iRxD,oRxD_Ready,oRxD_ERROR,oRxD_idle,iCLK,RST_n);
+input [7:0] iDATA;
+input iTxD_Start,iRxD,iCLK,RST_n;
+output [7:0] oDATA;
+output oTxD,oTxD_Busy,oRxD_Ready,oRxD_ERROR,oRxD_idle;
+
+async_receiver u0 ( /*.RST_n(RST_n),*/.clk(iCLK), .RxD(iRxD),
+ .RxD_data_ready(oRxD_Ready),/*.RxD_data_error(oRxD_ERROR),*/
+ .RxD_data(oDATA),.RxD_idle(oRxD_idle));
+//serie u0 ( .n_reset(RST_n),.clk(iCLK), .rx_in(iRxD),
+// .d_rdy(oRxD_Ready),.d_err(oRxD_ERROR),
+// .rx_data(oDATA));
+async_transmitter u1 ( /*.RST_n(RST_n),*/.clk(iCLK), .TxD_start(iTxD_Start),
+ .TxD_data(iDATA), .TxD(oTxD),
+ .TxD_busy(oTxD_Busy));
+
+endmodule
trunk/XILINX/BUILD_SCC/SP6/RS232_Controller.v
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC/SP6/CMD_Decode_simple.v
===================================================================
--- trunk/XILINX/BUILD_SCC/SP6/CMD_Decode_simple.v (nonexistent)
+++ trunk/XILINX/BUILD_SCC/SP6/CMD_Decode_simple.v (revision 17)
@@ -0,0 +1,314 @@
+
+module CMD_Decode( // USB JTAG
+ iRXD_DATA,oTXD_DATA,iRXD_Ready,iTXD_Done,oTXD_Start,
+ // AI
+ oAI_DATA,iAI_DATA,oAI_Start,iAI_Done,oCOLOR,
+ // Control
+ iCLK,iRST_n,oAI_RSTn,
+ //Debug
+ d_cmd
+ );
+// USB JTAG
+input [7:0] iRXD_DATA;
+input iRXD_Ready,iTXD_Done;
+output [7:0] oTXD_DATA;
+output oTXD_Start;
+// AI
+input [63:0] iAI_DATA;
+output [63:0] oAI_DATA;
+output reg oAI_Start;
+input iAI_Done;
+output [7:0] oCOLOR;
+// Control
+input iCLK,iRST_n;
+output oAI_RSTn;
+//output oAI_RSTn =AI_RSTn; //doesn't work in synplify
+//Debug
+output [16:0] d_cmd ;
+// Internal Register
+reg [63:0] CMD_Tmp;
+reg [71:0] AI_RESULT;
+reg [71:0] AI_RESULT_next;
+reg [2:0] mAI_ST /* synthesis syn_encoding = "safe,onehot" */;
+reg [2:0] mAI_ST_next;
+
+reg [63:0] AI_INPUT;
+reg [63:0] AI_INPUT_next;
+reg [16:0] AI_INPUT_MOVE;
+reg [16:0] AI_INPUT_MOVE_next;
+// USB JTAG TXD Output
+reg oSR_TXD_Start;
+reg [7:0] oSR_TXD_DATA;
+
+//
+reg AI_RSTn;
+assign oAI_RSTn =AI_RSTn; // this one works in synplify. see line 24
+reg [16:0] move_count_me,move_count_you; //maximum no. of moves= 361
+reg [16:0] move_count_me_next; //maximum no. of moves= 361
+wire [16:0] move_count=(move_count_me+move_count_you) >> 2;
+
+reg [7:0] CMD;
+
+reg TXD_Start;
+reg TXD_Start_next;
+reg rst_count;
+assign oTXD_Start =TXD_Start;
+assign d_cmd=AI_INPUT_MOVE;
+assign oCOLOR = CMD;
+
+/////////////////////////////////////////////////////////
+/////// Shift Register For Command Temp /////////////
+always@(posedge iCLK or negedge iRST_n)
+begin
+ if(!iRST_n)
+ begin
+ CMD_Tmp<=0;
+ CMD<=0;
+ move_count_you<=0;
+ AI_RSTn<=1'b0;
+ end
+ else
+ begin
+ CMD_Tmp<=CMD_Tmp;
+ CMD<=CMD;
+ move_count_you<=move_count_you;
+ AI_RSTn<=AI_RSTn;
+ if(iRXD_Ready)
+ begin
+ CMD_Tmp<={CMD_Tmp[55:0],iRXD_DATA};
+
+
+ if(iRXD_DATA !=8'h44 && iRXD_DATA!=8'h4C)
+ begin
+
+ move_count_you<=move_count_you+1;//4 ascii chars == 1 move
+ AI_RSTn<=1'b1;
+ end
+ else
+ begin
+
+ CMD<=iRXD_DATA;
+ move_count_you<=0;
+ AI_RSTn<=1'b0;
+
+ end
+ end
+ else
+
+ AI_RSTn<=1'b1;
+ end
+end
+/////////////////////////////////////////////////////////
+/////////////////////////////////////////////////////////
+//////////////// AI Control /////////////////////
+reg [3:0] wait_count;
+reg [3:0] wait_count_next;
+reg [3:0] NO_OF_MOVES;
+reg [3:0] NO_OF_MOVES_next;
+parameter state0=3'b000,state1=3'b001,state2=3'b010,state3=3'b011,state4=3'b100,state5=3'b101,state6=3'b110;
+
+always@(posedge iCLK or negedge AI_RSTn)
+
+begin
+ if(!AI_RSTn)
+ begin
+ mAI_ST<= state0;
+ wait_count <=0;
+ move_count_me<=0;
+ AI_RESULT<=0;
+ TXD_Start<=1'b0;
+ NO_OF_MOVES<=0;
+ AI_INPUT<=0;
+ AI_INPUT_MOVE<=0;
+
+ end
+ else
+ begin
+ mAI_ST<=mAI_ST_next;
+ wait_count <=wait_count_next;
+ move_count_me<=move_count_me_next;
+ AI_RESULT<=AI_RESULT_next;
+ TXD_Start<=TXD_Start_next;
+ NO_OF_MOVES<=NO_OF_MOVES_next;
+ AI_INPUT<=AI_INPUT_next;
+ AI_INPUT_MOVE<=AI_INPUT_MOVE_next;
+
+ end
+end
+
+
+always@*//(mAI_ST,move_count,iTXD_Done,TXD_Start,iAI_Done,iAI_DATA)
+begin
+ mAI_ST_next<=mAI_ST;
+ wait_count_next<=wait_count;
+ move_count_me_next<=move_count_me;
+ AI_RESULT_next<=AI_RESULT;
+ TXD_Start_next<=TXD_Start;
+ NO_OF_MOVES_next<=NO_OF_MOVES;
+ AI_INPUT_next <=AI_INPUT;
+ AI_INPUT_MOVE_next<=AI_INPUT_MOVE;
+ case(mAI_ST)
+
+
+ state0: begin
+ if( (CMD == 8'h44) && (move_count ==0))
+ begin
+ mAI_ST_next <= state1;
+ AI_INPUT_next<=CMD_Tmp;
+ AI_INPUT_MOVE_next<=move_count;
+ end
+ else if ( (CMD == 8'h4C) && (move_count ==1))
+ begin
+ mAI_ST_next <= state4;
+ AI_INPUT_next<=CMD_Tmp;
+ AI_INPUT_MOVE_next<=move_count;
+ end
+
+ else
+ mAI_ST_next <= state0;
+
+
+
+ end
+ state1: begin
+ mAI_ST_next <= state2;
+ end
+ state2: begin
+ if(iAI_Done == 1'b1)
+ begin
+ mAI_ST_next <= state3;
+ NO_OF_MOVES_next<=4;
+ AI_RESULT_next[63:0]<=iAI_DATA;
+ //AI_RESULT_next[63:0]<=CMD_Tmp;loop back
+
+ end
+ else begin
+ mAI_ST_next <= state2;
+ end
+
+
+ end
+ state3: begin
+
+ if(iTXD_Done == 1'b1 && TXD_Start ==1'b0)
+ begin
+ if(wait_count==NO_OF_MOVES) begin
+ mAI_ST_next <= state4;
+ wait_count_next<=0;
+ TXD_Start_next <=1'b0;
+ end
+ else begin
+ mAI_ST_next <= state3;
+ TXD_Start_next <=1'b1;
+ wait_count_next<=wait_count+1;
+ AI_RESULT_next<={AI_RESULT[63:0],8'h0};
+ move_count_me_next<=move_count_me+1;
+ end
+ end
+ else begin
+ TXD_Start_next <=1'b0;
+ end
+
+ end
+ state4: begin
+ //move_count % 4 == 0 means dark's turn, (move_count % 4 == 1 ) means light's turn
+ if((((move_count % 4) == 3 ) && (CMD ==8'h44))|| (((move_count % 4) == 1 ) && (CMD ==8'h4C)))
+ begin
+ //if(((move_count ==1|| move_count ==5|| move_count ==9) && (CMD ==8'h4C)))
+ mAI_ST_next <= state5;
+ AI_INPUT_next<=CMD_Tmp;
+ AI_INPUT_MOVE_next<=move_count;
+ end
+ else
+ mAI_ST_next <= state4;
+
+ end
+ state5: begin
+ mAI_ST_next <= state6;
+ AI_INPUT_next<=CMD_Tmp;
+ end
+ state6: begin
+ if(iAI_Done == 1'b1) begin
+ mAI_ST_next <= state3;
+ AI_RESULT_next[63:0]<=iAI_DATA;
+ //AI_RESULT_next[63:0]<=CMD_Tmp; loop back
+ NO_OF_MOVES_next<=8 ;
+ end
+
+ else begin
+ mAI_ST_next <= state6;
+ AI_RESULT_next<=0;
+ NO_OF_MOVES_next<=NO_OF_MOVES;
+ end
+
+ end
+ default:mAI_ST_next <= mAI_ST;
+ endcase
+
+
+end
+
+assign oTXD_DATA = AI_RESULT[71:64];
+
+assign oAI_DATA = AI_INPUT;
+
+always@(mAI_ST)
+begin
+ case(mAI_ST)
+
+
+ state0: begin
+
+ oAI_Start <=1'b0;
+ //oAI_DATA<=0;
+
+
+ end
+ state1: begin
+ oAI_Start <=1'b1;
+ //oAI_DATA<=CMD_Tmp[63:0];
+
+
+ //end
+ end
+ state2: begin
+
+ oAI_Start <=1'b0;
+ //oAI_DATA<=0;
+ //end
+ end
+ state3: begin
+ oAI_Start <=1'b0;
+ //oAI_DATA<=0;
+
+ //end
+ end
+ state4: begin
+ oAI_Start <=1'b0;
+ //oAI_DATA<=CMD_Tmp[63:0];
+
+
+ end
+ state5: begin
+ oAI_Start <=1'b1;
+ //oAI_DATA<=CMD_Tmp[63:0];
+
+
+ //end
+ end
+ state6: begin
+ oAI_Start <=1'b0;
+ //oAI_DATA<=CMD_Tmp[63:0];
+
+
+ //end
+ end
+ default:begin
+ oAI_Start <=1'b0;
+ //oAI_DATA<=CMD_Tmp[63:0];
+ end
+ endcase
+
+
+end
+endmodule
Index: trunk/XILINX/BUILD_SCC/SP6/SEG7_LUT_8.v
===================================================================
--- trunk/XILINX/BUILD_SCC/SP6/SEG7_LUT_8.v (nonexistent)
+++ trunk/XILINX/BUILD_SCC/SP6/SEG7_LUT_8.v (revision 17)
@@ -0,0 +1,14 @@
+module SEG7_LUT_8 ( oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7,iDIG );
+input [31:0] iDIG;
+output [6:0] oSEG0,oSEG1,oSEG2,oSEG3,oSEG4,oSEG5,oSEG6,oSEG7;
+
+SEG7_LUT u0 ( oSEG0,iDIG[3:0] );
+SEG7_LUT u1 ( oSEG1,iDIG[7:4] );
+SEG7_LUT u2 ( oSEG2,iDIG[11:8] );
+SEG7_LUT u3 ( oSEG3,iDIG[15:12] );
+SEG7_LUT u4 ( oSEG4,iDIG[19:16] );
+SEG7_LUT u5 ( oSEG5,iDIG[23:20] );
+SEG7_LUT u6 ( oSEG6,iDIG[27:24] );
+SEG7_LUT u7 ( oSEG7,iDIG[31:28] );
+
+endmodule
\ No newline at end of file
trunk/XILINX/BUILD_SCC/SP6/SEG7_LUT_8.v
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC/SP6/SP6.ucf
===================================================================
--- trunk/XILINX/BUILD_SCC/SP6/SP6.ucf (nonexistent)
+++ trunk/XILINX/BUILD_SCC/SP6/SP6.ucf (revision 17)
@@ -0,0 +1,48 @@
+#
+# Constraints generated by Synplify Pro map500rc, Build 036R
+#
+
+# Period Constraints
+NET "SYSCLK_P" TNM_NET = "SYSCLK_P";
+TIMESPEC "TS_SYSCLK_P" = PERIOD "SYSCLK_P" 5 ns HIGH 50 %;
+
+#Begin clock constraints
+NET "clocks/clk20_bufg_in" TNM_NET = "clocks_clk20_bufg_in";
+TIMESPEC "TS_clocks_clk20_bufg_in" = PERIOD "clocks_clk20_bufg_in" 50.000 ns HIGH 50.00%;
+#NET "clocks/clkfbout_clkfbin_125" TNM_NET = "clocks_clkfbout_clkfbin_125";
+#TIMESPEC "TS_clocks_clkfbout_clkfbin_125" = PERIOD "clocks_clkfbout_clkfbin_125" 50.000 ns HIGH 50.00%;
+#NET "clocks/osc_clk_ibufg" TNM_NET = "clocks_osc_clk_ibufg";
+#TIMESPEC "TS_clocks_osc_clk_ibufg" = PERIOD "clocks_osc_clk_ibufg" 50.000 ns HIGH 50.00%;
+#End clock constraints
+
+# Unconstrained Outputs
+
+NET "HEX0[*]" TIG; # port HEX0[6:0]
+NET "HEX1[*]" TIG; # port HEX1[6:0]
+NET "HEX2[*]" TIG; # port HEX2[6:0]
+NET "HEX3[*]" TIG; # port HEX3[6:0]
+NET "HEX4[*]" TIG; # port HEX4[6:0]
+NET "HEX5[*]" TIG; # port HEX5[6:0]
+NET "HEX6[*]" TIG; # port HEX6[6:0]
+NET "HEX7[*]" TIG; # port HEX7[6:0]
+#NET "LED_GREEN[*]" TIG; # port LED_GREEN[8:0]
+#NET "LED_RED[*]" TIG; # port LED_RED[17:0]
+#NET "UART_TXD" TIG;
+NET "TD_RESET" TIG;
+
+
+# Location Constraints
+#PIN "clocks/clk20_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;
+
+## Clock inputs
+NET "SYSCLK_P" LOC = "K21" |IOSTANDARD=LVDS_25;
+NET "SYSCLK_N" LOC = "K22" |IOSTANDARD=LVDS_25;
+
+NET "LED_RED[9]" LOC = "D17"; ## 2 on DS3 LED
+NET "LED_RED[10]" LOC = "AB4"; ## 2 on DS4 LED
+NET "LED_RED[11]" LOC = "D21"; ## 2 on DS5 LED
+NET "LED_RED[12]" LOC = "W15"; ## 2 on DS6 LED
+NET "KEY[0]" LOC = "F3"; ## 2 on SW4 pushbutton (active-high)
+NET "UART_TXD" LOC = "B21"; ##
+NET "UART_RXD" LOC = "H17"; ##
+# End of generated constraints
Index: trunk/XILINX/BUILD_SCC/SP6/quartus.tcl
===================================================================
--- trunk/XILINX/BUILD_SCC/SP6/quartus.tcl (nonexistent)
+++ trunk/XILINX/BUILD_SCC/SP6/quartus.tcl (revision 17)
@@ -0,0 +1,554 @@
+
+#set project_name connect6ai_synth_tcab
+#set top_level connect6ai_synth_tcab
+set project_name DE2
+set top_level DE2
+set family "CycloneII"
+set device EP2C35F672C6
+set sdc_constraints ../constraints.sdc
+
+# create new project
+project_new ${project_name}
+
+# project settings
+
+set_global_assignment -name TOP_LEVEL_ENTITY ${top_level}
+set_global_assignment -name family ${family}
+set_global_assignment -name device ${device}
+set_global_assignment -name SDC_FILE ${sdc_constraints}
+set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS OFF
+#set_global_assignment -name AUTO_RESOURCE_SHARING ON
+
+create_base_clock -fmax 50MHz clk -target OSC_50
+#verilog files
+set mcsfiles [glob -directory ../../../macrocells -nocomplain -tails -types f -- {*\.v}]
+foreach mcs ${mcsfiles} {
+ if [ regexp -- {assertions} ${mcs} ] {
+ continue
+}
+ set_global_assignment -name VERILOG_FILE "../../../macrocells/${mcs}"
+}
+
+set rtlfiles [glob -directory ../../../rtl -nocomplain -tails -types f -- {*\.v}]
+foreach rtl ${rtlfiles} {
+ if [ regexp -- {assertions} ${rtl} ] {
+ continue
+ }
+ set_global_assignment -name VERILOG_FILE "../../../rtl/${rtl}"
+}
+#set_global_assignment -name VERILOG_FILE ../../../../rtl_package/simu_stubs/vsim/bram_based_stream_buffer.v
+#DE2 files
+set de2files [glob -directory ../../../../DE2/ -nocomplain -tails -types f -- {*\.v}]
+foreach mcs ${de2files} {
+ if [ regexp -- {assertions} ${mcs} ] {
+ continue
+}
+ set_global_assignment -name VERILOG_FILE "../../../../DE2/${mcs}"
+}
+set de2files [glob -directory ../../../../DE2/ -nocomplain -tails -types f -- {*\.vhd}]
+foreach mcs ${de2files} {
+ if [ regexp -- {assertions} ${mcs} ] {
+ continue
+}
+ set_global_assignment -name VHDL_FILE "../../../../DE2/${mcs}"
+}
+set_global_assignment -name VHDL_FILE "../../../../DE2/pll/pll.vhd"
+set_global_assignment -name MISC_FILE "../../../../DE2/pll/pll_inst.vhd"
+set_global_assignment -name MISC_FILE "../../../../DE2/pll/pll.cmp"
+set_global_assignment -name MISC_FILE "../../../../DE2/pll/pll.ppf"
+set_global_assignment -name MISC_FILE "../../../../DE2/pll/pll_syn.v"
+
+# run the flow
+#execute_flow -compile
+
+#load_package flow
+#execute_module -tool map
+#set name_ids [get_names -filter * -node_type pin]
+#foreach_in_collection name_id $name_ids {
+# set pin_name [get_name_info -info full_path $name_id]
+# post_message "Making VIRTUAL_PIN assignment to $pin_name"
+# set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
+#}
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_N25 -to DPDT_SW[0]
+set_location_assignment PIN_N26 -to DPDT_SW[1]
+set_location_assignment PIN_P25 -to DPDT_SW[2]
+set_location_assignment PIN_AE14 -to DPDT_SW[3]
+set_location_assignment PIN_AF14 -to DPDT_SW[4]
+set_location_assignment PIN_AD13 -to DPDT_SW[5]
+set_location_assignment PIN_AC13 -to DPDT_SW[6]
+set_location_assignment PIN_C13 -to DPDT_SW[7]
+set_location_assignment PIN_B13 -to DPDT_SW[8]
+set_location_assignment PIN_A13 -to DPDT_SW[9]
+set_location_assignment PIN_N1 -to DPDT_SW[10]
+set_location_assignment PIN_P1 -to DPDT_SW[11]
+set_location_assignment PIN_P2 -to DPDT_SW[12]
+set_location_assignment PIN_T7 -to DPDT_SW[13]
+set_location_assignment PIN_U3 -to DPDT_SW[14]
+set_location_assignment PIN_U4 -to DPDT_SW[15]
+set_location_assignment PIN_V1 -to DPDT_SW[16]
+set_location_assignment PIN_V2 -to DPDT_SW[17]
+set_location_assignment PIN_T6 -to DRAM_ADDR[0]
+set_location_assignment PIN_V4 -to DRAM_ADDR[1]
+set_location_assignment PIN_V3 -to DRAM_ADDR[2]
+set_location_assignment PIN_W2 -to DRAM_ADDR[3]
+set_location_assignment PIN_W1 -to DRAM_ADDR[4]
+set_location_assignment PIN_U6 -to DRAM_ADDR[5]
+set_location_assignment PIN_U7 -to DRAM_ADDR[6]
+set_location_assignment PIN_U5 -to DRAM_ADDR[7]
+set_location_assignment PIN_W4 -to DRAM_ADDR[8]
+set_location_assignment PIN_W3 -to DRAM_ADDR[9]
+set_location_assignment PIN_Y1 -to DRAM_ADDR[10]
+set_location_assignment PIN_V5 -to DRAM_ADDR[11]
+set_location_assignment PIN_AE2 -to DRAM_BA_0
+set_location_assignment PIN_AE3 -to DRAM_BA_1
+set_location_assignment PIN_AB3 -to DRAM_CAS_N
+set_location_assignment PIN_AA6 -to DRAM_CKE
+set_location_assignment PIN_AA7 -to DRAM_CLK
+set_location_assignment PIN_AC3 -to DRAM_CS_N
+set_location_assignment PIN_V6 -to DRAM_DQ[0]
+set_location_assignment PIN_AA2 -to DRAM_DQ[1]
+set_location_assignment PIN_AA1 -to DRAM_DQ[2]
+set_location_assignment PIN_Y3 -to DRAM_DQ[3]
+set_location_assignment PIN_Y4 -to DRAM_DQ[4]
+set_location_assignment PIN_R8 -to DRAM_DQ[5]
+set_location_assignment PIN_T8 -to DRAM_DQ[6]
+set_location_assignment PIN_V7 -to DRAM_DQ[7]
+set_location_assignment PIN_W6 -to DRAM_DQ[8]
+set_location_assignment PIN_AB2 -to DRAM_DQ[9]
+set_location_assignment PIN_AB1 -to DRAM_DQ[10]
+set_location_assignment PIN_AA4 -to DRAM_DQ[11]
+set_location_assignment PIN_AA3 -to DRAM_DQ[12]
+set_location_assignment PIN_AC2 -to DRAM_DQ[13]
+set_location_assignment PIN_AC1 -to DRAM_DQ[14]
+set_location_assignment PIN_AA5 -to DRAM_DQ[15]
+set_location_assignment PIN_AD2 -to DRAM_LDQM
+set_location_assignment PIN_Y5 -to DRAM_UDQM
+set_location_assignment PIN_AB4 -to DRAM_RAS_N
+set_location_assignment PIN_AD3 -to DRAM_WE_N
+set_location_assignment PIN_AC18 -to FL_ADDR[0]
+set_location_assignment PIN_AB18 -to FL_ADDR[1]
+set_location_assignment PIN_AE19 -to FL_ADDR[2]
+set_location_assignment PIN_AF19 -to FL_ADDR[3]
+set_location_assignment PIN_AE18 -to FL_ADDR[4]
+set_location_assignment PIN_AF18 -to FL_ADDR[5]
+set_location_assignment PIN_Y16 -to FL_ADDR[6]
+set_location_assignment PIN_AA16 -to FL_ADDR[7]
+set_location_assignment PIN_AD17 -to FL_ADDR[8]
+set_location_assignment PIN_AC17 -to FL_ADDR[9]
+set_location_assignment PIN_AE17 -to FL_ADDR[10]
+set_location_assignment PIN_AF17 -to FL_ADDR[11]
+set_location_assignment PIN_W16 -to FL_ADDR[12]
+set_location_assignment PIN_W15 -to FL_ADDR[13]
+set_location_assignment PIN_AC16 -to FL_ADDR[14]
+set_location_assignment PIN_AD16 -to FL_ADDR[15]
+set_location_assignment PIN_AE16 -to FL_ADDR[16]
+set_location_assignment PIN_AC15 -to FL_ADDR[17]
+set_location_assignment PIN_AB15 -to FL_ADDR[18]
+set_location_assignment PIN_AA15 -to FL_ADDR[19]
+set_location_assignment PIN_V17 -to FL_CE_N
+set_location_assignment PIN_W17 -to FL_OE_N
+set_location_assignment PIN_AD19 -to FL_DQ[0]
+set_location_assignment PIN_AC19 -to FL_DQ[1]
+set_location_assignment PIN_AF20 -to FL_DQ[2]
+set_location_assignment PIN_AE20 -to FL_DQ[3]
+set_location_assignment PIN_AB20 -to FL_DQ[4]
+set_location_assignment PIN_AC20 -to FL_DQ[5]
+set_location_assignment PIN_AF21 -to FL_DQ[6]
+set_location_assignment PIN_AE21 -to FL_DQ[7]
+set_location_assignment PIN_AA18 -to FL_RST_N
+set_location_assignment PIN_AA17 -to FL_WE_N
+set_location_assignment PIN_AF10 -to HEX0[0]
+set_location_assignment PIN_AB12 -to HEX0[1]
+set_location_assignment PIN_AC12 -to HEX0[2]
+set_location_assignment PIN_AD11 -to HEX0[3]
+set_location_assignment PIN_AE11 -to HEX0[4]
+set_location_assignment PIN_V14 -to HEX0[5]
+set_location_assignment PIN_V13 -to HEX0[6]
+set_location_assignment PIN_V20 -to HEX1[0]
+set_location_assignment PIN_V21 -to HEX1[1]
+set_location_assignment PIN_W21 -to HEX1[2]
+set_location_assignment PIN_Y22 -to HEX1[3]
+set_location_assignment PIN_AA24 -to HEX1[4]
+set_location_assignment PIN_AA23 -to HEX1[5]
+set_location_assignment PIN_AB24 -to HEX1[6]
+set_location_assignment PIN_AB23 -to HEX2[0]
+set_location_assignment PIN_V22 -to HEX2[1]
+set_location_assignment PIN_AC25 -to HEX2[2]
+set_location_assignment PIN_AC26 -to HEX2[3]
+set_location_assignment PIN_AB26 -to HEX2[4]
+set_location_assignment PIN_AB25 -to HEX2[5]
+set_location_assignment PIN_Y24 -to HEX2[6]
+set_location_assignment PIN_Y23 -to HEX3[0]
+set_location_assignment PIN_AA25 -to HEX3[1]
+set_location_assignment PIN_AA26 -to HEX3[2]
+set_location_assignment PIN_Y26 -to HEX3[3]
+set_location_assignment PIN_Y25 -to HEX3[4]
+set_location_assignment PIN_U22 -to HEX3[5]
+set_location_assignment PIN_W24 -to HEX3[6]
+set_location_assignment PIN_U9 -to HEX4[0]
+set_location_assignment PIN_U1 -to HEX4[1]
+set_location_assignment PIN_U2 -to HEX4[2]
+set_location_assignment PIN_T4 -to HEX4[3]
+set_location_assignment PIN_R7 -to HEX4[4]
+set_location_assignment PIN_R6 -to HEX4[5]
+set_location_assignment PIN_T3 -to HEX4[6]
+set_location_assignment PIN_T2 -to HEX5[0]
+set_location_assignment PIN_P6 -to HEX5[1]
+set_location_assignment PIN_P7 -to HEX5[2]
+set_location_assignment PIN_T9 -to HEX5[3]
+set_location_assignment PIN_R5 -to HEX5[4]
+set_location_assignment PIN_R4 -to HEX5[5]
+set_location_assignment PIN_R3 -to HEX5[6]
+set_location_assignment PIN_R2 -to HEX6[0]
+set_location_assignment PIN_P4 -to HEX6[1]
+set_location_assignment PIN_P3 -to HEX6[2]
+set_location_assignment PIN_M2 -to HEX6[3]
+set_location_assignment PIN_M3 -to HEX6[4]
+set_location_assignment PIN_M5 -to HEX6[5]
+set_location_assignment PIN_M4 -to HEX6[6]
+set_location_assignment PIN_L3 -to HEX7[0]
+set_location_assignment PIN_L2 -to HEX7[1]
+set_location_assignment PIN_L9 -to HEX7[2]
+set_location_assignment PIN_L6 -to HEX7[3]
+set_location_assignment PIN_L7 -to HEX7[4]
+set_location_assignment PIN_P9 -to HEX7[5]
+set_location_assignment PIN_N9 -to HEX7[6]
+set_location_assignment PIN_G26 -to KEY[0]
+set_location_assignment PIN_N23 -to KEY[1]
+set_location_assignment PIN_P23 -to KEY[2]
+set_location_assignment PIN_W26 -to KEY[3]
+set_location_assignment PIN_AE23 -to LED_RED[0]
+set_location_assignment PIN_AF23 -to LED_RED[1]
+set_location_assignment PIN_AB21 -to LED_RED[2]
+set_location_assignment PIN_AC22 -to LED_RED[3]
+set_location_assignment PIN_AD22 -to LED_RED[4]
+set_location_assignment PIN_AD23 -to LED_RED[5]
+set_location_assignment PIN_AD21 -to LED_RED[6]
+set_location_assignment PIN_AC21 -to LED_RED[7]
+set_location_assignment PIN_AA14 -to LED_RED[8]
+set_location_assignment PIN_Y13 -to LED_RED[9]
+set_location_assignment PIN_AA13 -to LED_RED[10]
+set_location_assignment PIN_AC14 -to LED_RED[11]
+set_location_assignment PIN_AD15 -to LED_RED[12]
+set_location_assignment PIN_AE15 -to LED_RED[13]
+set_location_assignment PIN_AF13 -to LED_RED[14]
+set_location_assignment PIN_AE13 -to LED_RED[15]
+set_location_assignment PIN_AE12 -to LED_RED[16]
+set_location_assignment PIN_AD12 -to LED_RED[17]
+set_location_assignment PIN_AE22 -to LED_GREEN[0]
+set_location_assignment PIN_AF22 -to LED_GREEN[1]
+set_location_assignment PIN_W19 -to LED_GREEN[2]
+set_location_assignment PIN_V18 -to LED_GREEN[3]
+set_location_assignment PIN_U18 -to LED_GREEN[4]
+set_location_assignment PIN_U17 -to LED_GREEN[5]
+set_location_assignment PIN_AA20 -to LED_GREEN[6]
+set_location_assignment PIN_Y18 -to LED_GREEN[7]
+set_location_assignment PIN_Y12 -to LED_GREEN[8]
+set_location_assignment PIN_D13 -to OSC_27
+set_location_assignment PIN_N2 -to OSC_50
+set_location_assignment PIN_P26 -to EXT_CLOCK
+set_location_assignment PIN_D26 -to PS2_CLK
+set_location_assignment PIN_C24 -to PS2_DAT
+set_location_assignment PIN_C25 -to UART_RXD
+set_location_assignment PIN_B25 -to UART_TXD
+set_location_assignment PIN_K4 -to LCD_RW
+set_location_assignment PIN_K3 -to LCD_EN
+set_location_assignment PIN_K1 -to LCD_RS
+set_location_assignment PIN_J1 -to LCD_DATA[0]
+set_location_assignment PIN_J2 -to LCD_DATA[1]
+set_location_assignment PIN_H1 -to LCD_DATA[2]
+set_location_assignment PIN_H2 -to LCD_DATA[3]
+set_location_assignment PIN_J4 -to LCD_DATA[4]
+set_location_assignment PIN_J3 -to LCD_DATA[5]
+set_location_assignment PIN_H4 -to LCD_DATA[6]
+set_location_assignment PIN_H3 -to LCD_DATA[7]
+set_location_assignment PIN_L4 -to LCD_ON
+set_location_assignment PIN_K2 -to LCD_BLON
+set_location_assignment PIN_AE4 -to SRAM_ADDR[0]
+set_location_assignment PIN_AF4 -to SRAM_ADDR[1]
+set_location_assignment PIN_AC5 -to SRAM_ADDR[2]
+set_location_assignment PIN_AC6 -to SRAM_ADDR[3]
+set_location_assignment PIN_AD4 -to SRAM_ADDR[4]
+set_location_assignment PIN_AD5 -to SRAM_ADDR[5]
+set_location_assignment PIN_AE5 -to SRAM_ADDR[6]
+set_location_assignment PIN_AF5 -to SRAM_ADDR[7]
+set_location_assignment PIN_AD6 -to SRAM_ADDR[8]
+set_location_assignment PIN_AD7 -to SRAM_ADDR[9]
+set_location_assignment PIN_V10 -to SRAM_ADDR[10]
+set_location_assignment PIN_V9 -to SRAM_ADDR[11]
+set_location_assignment PIN_AC7 -to SRAM_ADDR[12]
+set_location_assignment PIN_W8 -to SRAM_ADDR[13]
+set_location_assignment PIN_W10 -to SRAM_ADDR[14]
+set_location_assignment PIN_Y10 -to SRAM_ADDR[15]
+set_location_assignment PIN_AB8 -to SRAM_ADDR[16]
+set_location_assignment PIN_AC8 -to SRAM_ADDR[17]
+set_location_assignment PIN_AD8 -to SRAM_DQ[0]
+set_location_assignment PIN_AE6 -to SRAM_DQ[1]
+set_location_assignment PIN_AF6 -to SRAM_DQ[2]
+set_location_assignment PIN_AA9 -to SRAM_DQ[3]
+set_location_assignment PIN_AA10 -to SRAM_DQ[4]
+set_location_assignment PIN_AB10 -to SRAM_DQ[5]
+set_location_assignment PIN_AA11 -to SRAM_DQ[6]
+set_location_assignment PIN_Y11 -to SRAM_DQ[7]
+set_location_assignment PIN_AE7 -to SRAM_DQ[8]
+set_location_assignment PIN_AF7 -to SRAM_DQ[9]
+set_location_assignment PIN_AE8 -to SRAM_DQ[10]
+set_location_assignment PIN_AF8 -to SRAM_DQ[11]
+set_location_assignment PIN_W11 -to SRAM_DQ[12]
+set_location_assignment PIN_W12 -to SRAM_DQ[13]
+set_location_assignment PIN_AC9 -to SRAM_DQ[14]
+set_location_assignment PIN_AC10 -to SRAM_DQ[15]
+set_location_assignment PIN_AE10 -to SRAM_WE_N
+set_location_assignment PIN_AD10 -to SRAM_OE_N
+set_location_assignment PIN_AF9 -to SRAM_UB_N
+set_location_assignment PIN_AE9 -to SRAM_LB_N
+set_location_assignment PIN_AC11 -to SRAM_CE_N
+set_location_assignment PIN_K7 -to OTG_ADDR[0]
+set_location_assignment PIN_F2 -to OTG_ADDR[1]
+set_location_assignment PIN_F1 -to OTG_CS_N
+set_location_assignment PIN_G2 -to OTG_RD_N
+set_location_assignment PIN_G1 -to OTG_WR_N
+set_location_assignment PIN_G5 -to OTG_RST_N
+set_location_assignment PIN_F4 -to OTG_DATA[0]
+set_location_assignment PIN_D2 -to OTG_DATA[1]
+set_location_assignment PIN_D1 -to OTG_DATA[2]
+set_location_assignment PIN_F7 -to OTG_DATA[3]
+set_location_assignment PIN_J5 -to OTG_DATA[4]
+set_location_assignment PIN_J8 -to OTG_DATA[5]
+set_location_assignment PIN_J7 -to OTG_DATA[6]
+set_location_assignment PIN_H6 -to OTG_DATA[7]
+set_location_assignment PIN_E2 -to OTG_DATA[8]
+set_location_assignment PIN_E1 -to OTG_DATA[9]
+set_location_assignment PIN_K6 -to OTG_DATA[10]
+set_location_assignment PIN_K5 -to OTG_DATA[11]
+set_location_assignment PIN_G4 -to OTG_DATA[12]
+set_location_assignment PIN_G3 -to OTG_DATA[13]
+set_location_assignment PIN_J6 -to OTG_DATA[14]
+set_location_assignment PIN_K8 -to OTG_DATA[15]
+set_location_assignment PIN_B3 -to OTG_INT0
+set_location_assignment PIN_C3 -to OTG_INT1
+set_location_assignment PIN_C2 -to OTG_DACK0_N
+set_location_assignment PIN_B2 -to OTG_DACK1_N
+set_location_assignment PIN_F6 -to OTG_DREQ0
+set_location_assignment PIN_E5 -to OTG_DREQ1
+set_location_assignment PIN_F3 -to OTG_FSPEED
+set_location_assignment PIN_G6 -to OTG_LSPEED
+set_location_assignment PIN_B14 -to TDI
+set_location_assignment PIN_A14 -to TCS
+set_location_assignment PIN_D14 -to TCK
+set_location_assignment PIN_F14 -to TDO
+set_location_assignment PIN_C4 -to TD_RESET
+set_location_assignment PIN_C8 -to VGA_R[0]
+set_location_assignment PIN_F10 -to VGA_R[1]
+set_location_assignment PIN_G10 -to VGA_R[2]
+set_location_assignment PIN_D9 -to VGA_R[3]
+set_location_assignment PIN_C9 -to VGA_R[4]
+set_location_assignment PIN_A8 -to VGA_R[5]
+set_location_assignment PIN_H11 -to VGA_R[6]
+set_location_assignment PIN_H12 -to VGA_R[7]
+set_location_assignment PIN_F11 -to VGA_R[8]
+set_location_assignment PIN_E10 -to VGA_R[9]
+set_location_assignment PIN_B9 -to VGA_G[0]
+set_location_assignment PIN_A9 -to VGA_G[1]
+set_location_assignment PIN_C10 -to VGA_G[2]
+set_location_assignment PIN_D10 -to VGA_G[3]
+set_location_assignment PIN_B10 -to VGA_G[4]
+set_location_assignment PIN_A10 -to VGA_G[5]
+set_location_assignment PIN_G11 -to VGA_G[6]
+set_location_assignment PIN_D11 -to VGA_G[7]
+set_location_assignment PIN_E12 -to VGA_G[8]
+set_location_assignment PIN_D12 -to VGA_G[9]
+set_location_assignment PIN_J13 -to VGA_B[0]
+set_location_assignment PIN_J14 -to VGA_B[1]
+set_location_assignment PIN_F12 -to VGA_B[2]
+set_location_assignment PIN_G12 -to VGA_B[3]
+set_location_assignment PIN_J10 -to VGA_B[4]
+set_location_assignment PIN_J11 -to VGA_B[5]
+set_location_assignment PIN_C11 -to VGA_B[6]
+set_location_assignment PIN_B11 -to VGA_B[7]
+set_location_assignment PIN_C12 -to VGA_B[8]
+set_location_assignment PIN_B12 -to VGA_B[9]
+set_location_assignment PIN_B8 -to VGA_CLK
+set_location_assignment PIN_D6 -to VGA_BLANK
+set_location_assignment PIN_A7 -to VGA_HS
+set_location_assignment PIN_D8 -to VGA_VS
+set_location_assignment PIN_B7 -to VGA_SYNC
+set_location_assignment PIN_A6 -to I2C_SCLK
+set_location_assignment PIN_B6 -to I2C_SDAT
+set_location_assignment PIN_J9 -to TD_DATA[0]
+set_location_assignment PIN_E8 -to TD_DATA[1]
+set_location_assignment PIN_H8 -to TD_DATA[2]
+set_location_assignment PIN_H10 -to TD_DATA[3]
+set_location_assignment PIN_G9 -to TD_DATA[4]
+set_location_assignment PIN_F9 -to TD_DATA[5]
+set_location_assignment PIN_D7 -to TD_DATA[6]
+set_location_assignment PIN_C7 -to TD_DATA[7]
+set_location_assignment PIN_D5 -to TD_HS
+set_location_assignment PIN_K9 -to TD_VS
+set_location_assignment PIN_C5 -to AUD_ADCLRCK
+set_location_assignment PIN_B5 -to AUD_ADCDAT
+set_location_assignment PIN_C6 -to AUD_DACLRCK
+set_location_assignment PIN_A4 -to AUD_DACDAT
+set_location_assignment PIN_A5 -to AUD_XCK
+set_location_assignment PIN_B4 -to AUD_BCLK
+set_location_assignment PIN_D17 -to ENET_DATA[0]
+set_location_assignment PIN_C17 -to ENET_DATA[1]
+set_location_assignment PIN_B18 -to ENET_DATA[2]
+set_location_assignment PIN_A18 -to ENET_DATA[3]
+set_location_assignment PIN_B17 -to ENET_DATA[4]
+set_location_assignment PIN_A17 -to ENET_DATA[5]
+set_location_assignment PIN_B16 -to ENET_DATA[6]
+set_location_assignment PIN_B15 -to ENET_DATA[7]
+set_location_assignment PIN_B20 -to ENET_DATA[8]
+set_location_assignment PIN_A20 -to ENET_DATA[9]
+set_location_assignment PIN_C19 -to ENET_DATA[10]
+set_location_assignment PIN_D19 -to ENET_DATA[11]
+set_location_assignment PIN_B19 -to ENET_DATA[12]
+set_location_assignment PIN_A19 -to ENET_DATA[13]
+set_location_assignment PIN_E18 -to ENET_DATA[14]
+set_location_assignment PIN_D18 -to ENET_DATA[15]
+set_location_assignment PIN_B24 -to ENET_CLK
+set_location_assignment PIN_A21 -to ENET_CMD
+set_location_assignment PIN_A23 -to ENET_CS_N
+set_location_assignment PIN_B21 -to ENET_INT
+set_location_assignment PIN_A22 -to ENET_RD_N
+set_location_assignment PIN_B22 -to ENET_WR_N
+set_location_assignment PIN_B23 -to ENET_RST_N
+set_location_assignment PIN_AE24 -to IRDA_TXD
+set_location_assignment PIN_AE25 -to IRDA_RXD
+set_location_assignment PIN_AD24 -to SD_DAT
+set_location_assignment PIN_AC23 -to SD_DAT3
+set_location_assignment PIN_Y21 -to SD_CMD
+set_location_assignment PIN_AD25 -to SD_CLK
+#set_location_assignment PIN_D25 -to GPIO_0[0]
+#set_location_assignment PIN_J22 -to GPIO_0[1]
+#set_location_assignment PIN_E26 -to GPIO_0[2]
+#set_location_assignment PIN_E25 -to GPIO_0[3]
+#set_location_assignment PIN_F24 -to GPIO_0[4]
+#set_location_assignment PIN_F23 -to GPIO_0[5]
+#set_location_assignment PIN_J21 -to GPIO_0[6]
+set_location_assignment PIN_J21 -to UART_RXD_JP1_7
+#set_location_assignment PIN_J20 -to GPIO_0[7]
+#set_location_assignment PIN_F25 -to GPIO_0[8]
+#set_location_assignment PIN_F26 -to GPIO_0[9]
+set_location_assignment PIN_N18 -to GPIO_0_10
+#set_location_assignment PIN_P18 -to GPIO_0[11]
+#set_location_assignment PIN_G23 -to GPIO_0[12]
+#set_location_assignment PIN_G24 -to GPIO_0[13]
+#set_location_assignment PIN_K22 -to GPIO_0[14]
+#set_location_assignment PIN_G25 -to GPIO_0[15]
+#set_location_assignment PIN_H23 -to GPIO_0[16]
+#set_location_assignment PIN_H24 -to GPIO_0[17]
+#set_location_assignment PIN_J23 -to GPIO_0[18]
+#set_location_assignment PIN_J24 -to GPIO_0[19]
+#set_location_assignment PIN_H25 -to GPIO_0[20]
+set_location_assignment PIN_H25 -to I_OR7_JP1_35_bis
+#set_location_assignment PIN_H26 -to GPIO_0[21]
+#set_location_assignment PIN_H19 -to GPIO_0[22]
+set_location_assignment PIN_H19 -to I_OR8_JP1_36_bis
+#set_location_assignment PIN_K18 -to GPIO_0_[23]
+#set_location_assignment PIN_K19 -to GPIO_0[24]
+set_location_assignment PIN_K19 -to UART_TXD_JP1_27
+#set_location_assignment PIN_K21 -to GPIO_0[25]
+#set_location_assignment PIN_K23 -to GPIO_0[26]
+#set_location_assignment PIN_K24 -to GPIO_0[27]
+#set_location_assignment PIN_L21 -to GPIO_0[28]
+#set_location_assignment PIN_L20 -to GPIO_0[29]
+#set_location_assignment PIN_J25 -to GPIO_0[30]
+set_location_assignment PIN_J25 -to I_OR7_JP1_35
+#set_location_assignment PIN_J26 -to GPIO_0[31]
+set_location_assignment PIN_J26 -to I_OR8_JP1_36
+#set_location_assignment PIN_L23 -to GPIO_0[32]
+set_location_assignment PIN_L23 -to CONFIG_MODE_JP1_37
+#set_location_assignment PIN_L24 -to GPIO_0[33]
+set_location_assignment PIN_L24 -to I_OT2_JP1_38
+#set_location_assignment PIN_L25 -to GPIO_0[34]
+#set_location_assignment PIN_L19 -to GPIO_0[35]
+set_location_assignment PIN_L25 -to INIT_JP1_39
+#set_location_assignment PIN_K25 -to GPIO_1[0]
+set_location_assignment PIN_K25 -to I_OT7_JP2_41
+#set_location_assignment PIN_K26 -to GPIO_1[1]
+set_location_assignment PIN_K26 -to I_OT6_JP2_42
+#set_location_assignment PIN_M22 -to GPIO_1[2]
+set_location_assignment PIN_M22 -to I_OT4_JP2_43
+#set_location_assignment PIN_M23 -to GPIO_1[3]
+set_location_assignment PIN_M23 -to I_OT3_JP2_44
+#set_location_assignment PIN_M19 -to GPIO_1[4]
+set_location_assignment PIN_M19 -to I_OT1_JP2_45
+#set_location_assignment PIN_M20 -to GPIO_1[5]
+set_location_assignment PIN_M20 -to I_OT0_JP2_46
+#set_location_assignment PIN_N20 -to GPIO_1[6]
+set_location_assignment PIN_N20 -to CONFIG_OUT0_JP2_47
+#set_location_assignment PIN_M21 -to GPIO_1[7]
+set_location_assignment PIN_M21 -to I_OL6_JP2_48
+#set_location_assignment PIN_M24 -to GPIO_1[8]
+set_location_assignment PIN_M24 -to CONFIG_OUT1_JP2_49
+#set_location_assignment PIN_M25 -to GPIO_1[9]
+set_location_assignment PIN_M25 -to I_OL3_JP2_50
+#set_location_assignment PIN_N24 -to GPIO_1_10
+set_location_assignment PIN_N24 -to I_OL7_JP2_53
+#set_location_assignment PIN_P24 -to GPIO_1[11]
+set_location_assignment PIN_P24 -to I_OL0_JP2_54
+#set_location_assignment PIN_R25 -to GPIO_1[12]
+set_location_assignment PIN_R25 -to I_OL4_JP2_55
+#set_location_assignment PIN_R24 -to GPIO_1[13]
+set_location_assignment PIN_R24 -to I_OL8_JP2_56
+#set_location_assignment PIN_R20 -to GPIO_1[14]
+set_location_assignment PIN_R20 -to I_OL1_JP2_57
+#set_location_assignment PIN_T22 -to GPIO_1[15]
+set_location_assignment PIN_T22 -to I_OT8_JP2_58
+#set_location_assignment PIN_T23 -to GPIO_1_16
+set_location_assignment PIN_T23 -to I_OL2_JP2_59
+#set_location_assignment PIN_T24 -to GPIO_1[17]
+set_location_assignment PIN_T24 -to I_OB2_JP2_60
+#set_location_assignment PIN_T25 -to GPIO_1[18]
+set_location_assignment PIN_T25 -to I_OL5_JP2_61
+#set_location_assignment PIN_T18 -to GPIO_1[19]
+set_location_assignment PIN_T18 -to I_OB5_JP2_62
+#set_location_assignment PIN_T21 -to GPIO_1[20]
+set_location_assignment PIN_T21 -to I_OT5_JP2_63
+#set_location_assignment PIN_T20 -to GPIO_1[21]
+set_location_assignment PIN_T20 -to I_OR2_JP2_64
+#set_location_assignment PIN_U26 -to GPIO_1[22]
+set_location_assignment PIN_U26 -to I_OB8_JP2_65
+#set_location_assignment PIN_U25 -to GPIO_1[23]
+set_location_assignment PIN_U25 -to CONFIG_ACK_IN_JP2_66
+#set_location_assignment PIN_U23 -to GPIO_1[24]
+set_location_assignment PIN_U23 -to I_OR5_JP2_67
+#set_location_assignment PIN_U24 -to GPIO_1[25]
+set_location_assignment PIN_U24 -to I_OB0_JP2_68
+#set_location_assignment PIN_R19 -to GPIO_1[26]
+set_location_assignment PIN_R19 -to I_OB1_JP2_71
+#set_location_assignment PIN_T19 -to GPIO_1[27]
+set_location_assignment PIN_T19 -to I_OB3_JP2_72
+#set_location_assignment PIN_U20 -to GPIO_1[28]
+set_location_assignment PIN_U20 -to I_OB4_JP2_73
+#set_location_assignment PIN_U21 -to GPIO_1[29]
+set_location_assignment PIN_U21 -to I_OB6_JP2_74
+#set_location_assignment PIN_V26 -to GPIO_1[30]
+set_location_assignment PIN_V26 -to I_OB7_JP2_75
+#set_location_assignment PIN_V25 -to GPIO_1[31]
+set_location_assignment PIN_V25 -to I_OR0_JP2_76
+#set_location_assignment PIN_V24 -to GPIO_1[32]
+set_location_assignment PIN_V24 -to I_OR1_JP2_77
+#set_location_assignment PIN_V23 -to GPIO_1[33]
+set_location_assignment PIN_V23 -to I_OR3_JP2_78
+#set_location_assignment PIN_W25 -to GPIO_1[34]
+set_location_assignment PIN_W25 -to I_OR4_JP2_79
+#set_location_assignment PIN_W23 -to GPIO_1[35]
+set_location_assignment PIN_W23 -to I_OR6_JP2_80
+
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
+
+
+export_assignments
+
+# close the project
+project_close
+
Index: trunk/XILINX/BUILD_SCC/SP6/DE2.ucf
===================================================================
--- trunk/XILINX/BUILD_SCC/SP6/DE2.ucf (nonexistent)
+++ trunk/XILINX/BUILD_SCC/SP6/DE2.ucf (revision 17)
@@ -0,0 +1,48 @@
+#
+# Constraints generated by Synplify Pro map500rc, Build 036R
+#
+
+# Period Constraints
+NET "SYSCLK_P" TNM_NET = "SYSCLK_P";
+TIMESPEC "TS_SYSCLK_P" = PERIOD "SYSCLK_P" 5 ns HIGH 50 %;
+
+#Begin clock constraints
+NET "clocks/clk20_bufg_in" TNM_NET = "clocks_clk20_bufg_in";
+TIMESPEC "TS_clocks_clk20_bufg_in" = PERIOD "clocks_clk20_bufg_in" 50.000 ns HIGH 50.00%;
+#NET "clocks/clkfbout_clkfbin_125" TNM_NET = "clocks_clkfbout_clkfbin_125";
+#TIMESPEC "TS_clocks_clkfbout_clkfbin_125" = PERIOD "clocks_clkfbout_clkfbin_125" 50.000 ns HIGH 50.00%;
+#NET "clocks/osc_clk_ibufg" TNM_NET = "clocks_osc_clk_ibufg";
+#TIMESPEC "TS_clocks_osc_clk_ibufg" = PERIOD "clocks_osc_clk_ibufg" 50.000 ns HIGH 50.00%;
+#End clock constraints
+
+# Unconstrained Outputs
+
+NET "HEX0[*]" TIG; # port HEX0[6:0]
+NET "HEX1[*]" TIG; # port HEX1[6:0]
+NET "HEX2[*]" TIG; # port HEX2[6:0]
+NET "HEX3[*]" TIG; # port HEX3[6:0]
+NET "HEX4[*]" TIG; # port HEX4[6:0]
+NET "HEX5[*]" TIG; # port HEX5[6:0]
+NET "HEX6[*]" TIG; # port HEX6[6:0]
+NET "HEX7[*]" TIG; # port HEX7[6:0]
+#NET "LED_GREEN[*]" TIG; # port LED_GREEN[8:0]
+#NET "LED_RED[*]" TIG; # port LED_RED[17:0]
+#NET "UART_TXD" TIG;
+NET "TD_RESET" TIG;
+
+
+# Location Constraints
+#PIN "clocks/clk20_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;
+
+## Clock inputs
+NET "SYSCLK_P" LOC = "K21" |IOSTANDARD=LVDS_25;
+NET "SYSCLK_N" LOC = "K22" |IOSTANDARD=LVDS_25;
+
+NET "LED_RED[9]" LOC = "D17"; ## 2 on DS3 LED
+NET "LED_RED[10]" LOC = "AB4"; ## 2 on DS4 LED
+NET "LED_RED[11]" LOC = "D21"; ## 2 on DS5 LED
+NET "LED_RED[12]" LOC = "W15"; ## 2 on DS6 LED
+NET "KEY[0]" LOC = "F3"; ## 2 on SW4 pushbutton (active-high)
+NET "UART_TXD" LOC = "B21"; ##
+NET "UART_RXD" LOC = "H17"; ##
+# End of generated constraints
Index: trunk/XILINX/BUILD_SCC/SP6/do_synth
===================================================================
--- trunk/XILINX/BUILD_SCC/SP6/do_synth (nonexistent)
+++ trunk/XILINX/BUILD_SCC/SP6/do_synth (revision 17)
@@ -0,0 +1,49 @@
+
+#!/bin/sh
+
+run_logic_synthesis_only=0 ;
+while getopts ":s i" options; do
+ case $options in
+ i ) run_logic_synthesis_only=0;;
+ s ) run_logic_synthesis_only=1;;
+ ? ) echo $usage
+ exit 1;;
+ esac
+done
+
+################################
+# set up the verilog filelists:
+################################
+
+export date_of_run=`date +%Y.%m.%d_%H.%M.%S`
+mkdir run_$date_of_run
+rm -f run
+ln -s run_$date_of_run run
+
+cd run
+
+if [ $run_logic_synthesis_only -eq 1 ]; then
+ touch .LOGIC_SYNTHESIS_ONLY
+fi
+
+quartus_sh -t ../quartus.tcl
+if [[ $? != 0 ]]; then exit 1; fi
+
+quartus_map DE2
+if [[ $? != 0 ]]; then exit 1; fi
+
+if [ $run_logic_synthesis_only -eq 1 ]; then
+ quartus_fit --early_timing_estimate=realistic DE2
+ if [[ $? != 0 ]]; then exit 1; fi
+else
+ quartus_fit DE2
+ if [[ $? != 0 ]]; then exit 1; fi
+fi
+
+quartus_sta --do_report_timing DE2
+if [[ $? != 0 ]]; then exit 1; fi
+quartus_asm DE2
+quartus_pgm -c USB-Blaster -m jtag -o "p;DE2.sof"
+cd -
+exit 0
+
trunk/XILINX/BUILD_SCC/SP6/do_synth
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC/SP6/bram_based_stream_buffer.v
===================================================================
--- trunk/XILINX/BUILD_SCC/SP6/bram_based_stream_buffer.v (nonexistent)
+++ trunk/XILINX/BUILD_SCC/SP6/bram_based_stream_buffer.v (revision 17)
@@ -0,0 +1,244 @@
+// Copyright (c) 2011 Synopsys, Inc. All rights reserved.
+//
+//
+// $Revision: 1.8 $
+
+
+`timescale 1ns / 1ps
+
+`ifdef PICO_CLOCK_EDGE
+`else
+ `define PICO_CLOCK_EDGE posedge
+`endif
+`ifdef PICO_CLOCK_SENSITIVITY
+`else
+ `define PICO_CLOCK_SENSITIVITY clk
+`endif
+`ifdef PICO_RESET_SENSITIVITY
+`else
+ `define PICO_RESET_SENSITIVITY
+`endif
+`ifdef PICO_RESET_SENSITIVITY2
+`else
+ `define PICO_RESET_SENSITIVITY2 reset
+`endif
+
+`timescale 1 ns / 10 ps
+
+module bram_based_stream_buffer (clk, indata, outdata, store_ready, load_ready, reset, flush, load_req, store_req );
+
+ parameter width = 48;
+ parameter depth = 800;
+ parameter awidth = clogb2(depth);
+
+input clk, load_ready, store_ready, reset, flush;
+wire clk, load_ready, store_ready, reset, flush;
+
+input [width-1:0] indata;
+wire [width-1:0] indata;
+
+output load_req, store_req;
+wire load_req, store_req;
+
+output [width-1:0] outdata;
+wire [width-1:0] outdata;
+
+
+function integer clogb2(input integer depth);
+ begin
+ for (clogb2=0; depth>0; clogb2=clogb2+1)
+ depth= depth>>1;
+ end
+ endfunction
+
+ // 0in assert -var (depth >= 1)
+ // coverage off
+ // pragma coverage off
+ // VCS coverage off
+ // synopsys translate_off
+ initial begin
+ if ( depth < 1 ) begin
+ $display ("ERROR::::");
+ $display ("mc_log: ERROR: bram_based_stream_buffer of depth %0d in %m. This is unsupported.Stopping simulation",depth);
+ $display ("END ERROR");
+ $finish;
+ end
+ end
+ // synopsys translate_on
+ // VCS coverage on
+ // pragma coverage on
+ // coverage on
+
+reg [awidth-1:0] read_addr_ff, next_read_addr_ff, write_addr_ff;
+reg [awidth-1:0] count_ff ;
+reg full_ff, not_empty_ff, onefull_ff, init_ff;
+
+reg [width-1:0] bypass_reg_ff;
+reg bypass_reg_valid_ff;
+
+wire [width-1:0] bram_outdata;
+wire addq_only, shiftq_only, shiftq_addq, mem_is_empty;
+
+wire addq = load_ready;
+wire shiftq = store_ready;
+
+wire full_mem = full_ff;
+assign mem_is_empty = ~not_empty_ff;
+
+assign addq_only = (addq & !full_ff & (!shiftq |(shiftq & mem_is_empty)));
+assign shiftq_only = (shiftq & !mem_is_empty & (!addq | (addq & full_mem)) );
+assign shiftq_addq = (shiftq & addq & not_empty_ff & !full_mem);
+
+wire rreq, wreq;
+
+assign rreq = not_empty_ff;
+assign wreq = addq & !full_mem;
+assign load_req = !full_mem;
+assign store_req = !mem_is_empty;
+
+always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY ) begin
+ if (`PICO_RESET_SENSITIVITY2) begin
+ not_empty_ff <= 1'b0;
+ full_ff <= 1'b0;
+ init_ff <= 1'b0;
+ end
+ else if (flush) begin
+ not_empty_ff <= 1'b0;
+ full_ff <= 1'b0;
+ init_ff <= 1'b0;
+ end
+ else begin
+ init_ff <= 1'b1;
+ if (addq & mem_is_empty) begin
+ not_empty_ff <= 1'b1;
+ end
+ else if (shiftq & !addq & onefull_ff) begin
+ not_empty_ff <= 1'b0;
+ end
+
+ if (addq_only & (count_ff == depth-1)) full_ff <= 1'b1;
+ else if (shiftq_only) full_ff <= 1'b0;
+
+ end
+end
+
+always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY ) begin
+ if (`PICO_RESET_SENSITIVITY2) begin
+ onefull_ff <= 1'b0;
+ end
+ else if (flush) begin
+ onefull_ff <= 1'b0;
+ end
+ else begin
+ if (addq_only) begin
+ if (mem_is_empty) begin
+ onefull_ff <= 1'b1;
+ end
+ else begin
+ onefull_ff <= 1'b0;
+ end
+ end
+ else if (shiftq_only) begin
+ if (onefull_ff) begin
+ onefull_ff <= 1'b0;
+ end
+ else if (count_ff == 2'b10) begin
+ onefull_ff <= 1'b1;
+ end
+ end
+ end
+end
+
+always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY ) begin
+ if (`PICO_RESET_SENSITIVITY2) begin
+ read_addr_ff <= {awidth{1'b0}};
+ next_read_addr_ff <= {awidth{1'b0}};
+ end
+ else if (flush) begin
+ read_addr_ff <= {awidth{1'b0}};
+ next_read_addr_ff <= {awidth{1'b0}};
+ end
+ else begin
+
+ if ( (shiftq & not_empty_ff) | ~init_ff ) begin
+ read_addr_ff <= next_read_addr_ff;
+ if (next_read_addr_ff == depth-1) begin
+ next_read_addr_ff <= {awidth{1'b0}};
+ end
+ else begin
+ next_read_addr_ff <= next_read_addr_ff + 1'b1;
+ end
+ end
+ end
+end
+
+always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY ) begin
+ if (`PICO_RESET_SENSITIVITY2) begin
+ write_addr_ff <= {awidth{1'b0}};
+ end
+ else if (flush) begin
+ write_addr_ff <= {awidth{1'b0}};
+ end
+ else begin
+ if (wreq) begin
+ if (write_addr_ff == depth-1)
+ write_addr_ff <= {awidth{1'b0}};
+ else
+ write_addr_ff <= write_addr_ff + 1'b1;
+ end
+ end
+end
+
+always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY ) begin
+ if (`PICO_RESET_SENSITIVITY2) begin
+ count_ff <= {awidth{1'b0}};
+ end
+ else if (flush) begin
+ count_ff <= {awidth{1'b0}};
+ end
+ else begin
+ if (addq_only) begin
+ count_ff <= count_ff + 1'b1;
+ end
+ else if (shiftq_only) begin
+ count_ff <= count_ff - 1'b1;
+ end
+ end
+end
+
+ always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY) begin
+ if (`PICO_RESET_SENSITIVITY2)
+ begin
+ bypass_reg_valid_ff <= 1'b0;
+ bypass_reg_ff <= {(width){1'b0}};
+ end
+ else if (flush)
+ begin
+ bypass_reg_valid_ff <= 1'b0;
+ end
+ else
+ begin
+ bypass_reg_valid_ff <= addq & ( mem_is_empty | (shiftq & onefull_ff) );
+ bypass_reg_ff <= indata;
+ end
+ end
+ assign outdata = bypass_reg_valid_ff ? bypass_reg_ff[width-1:0] : bram_outdata[width-1:0];
+
+ wire [awidth-1:0] speculative_read_addr = (shiftq & not_empty_ff) ? next_read_addr_ff : read_addr_ff;
+
+ RA2SH #(.dwidth(width), .depth(depth), .awidth(awidth) ) fifo_storage(
+ .QA(),
+ .CLKA(clk),
+ .CENA(~wreq),
+ .WENA(1'b0),
+ .AA(write_addr_ff[awidth-1:0]),
+ .DA(indata[width-1:0]),
+ .QB(bram_outdata[width-1:0]),
+ .CLKB(clk),
+ .CENB(~rreq),
+ .WENB(1'b1),
+ .AB(speculative_read_addr),
+ .DB({width{1'b0}}));
+
+
+endmodule
Index: trunk/XILINX/BUILD_SCC/SP6/SP6.tcl
===================================================================
--- trunk/XILINX/BUILD_SCC/SP6/SP6.tcl (nonexistent)
+++ trunk/XILINX/BUILD_SCC/SP6/SP6.tcl (revision 17)
@@ -0,0 +1,639 @@
+#
+# Project automation script for DE2
+#
+# Created for ISE version 13.4
+#
+# This file contains several Tcl procedures (procs) that you can use to automate
+# your project by running from xtclsh or the Project Navigator Tcl console.
+# If you load this file (using the Tcl command: source DE2.tcl), then you can
+# run any of the procs included here.
+#
+# This script is generated assuming your project has HDL sources.
+# Several of the defined procs won't apply to an EDIF or NGC based project.
+# If that is the case, simply remove them from this script.
+#
+# You may also edit any of these procs to customize them. See comments in each
+# proc for more instructions.
+#
+# This file contains the following procedures:
+#
+# Top Level procs (meant to be called directly by the user):
+# run_process: you can use this top-level procedure to run any processes
+# that you choose to by adding and removing comments, or by
+# adding new entries.
+# rebuild_project: you can alternatively use this top-level procedure
+# to recreate your entire project, and the run selected processes.
+#
+# Lower Level (helper) procs (called under in various cases by the top level procs):
+# show_help: print some basic information describing how this script works
+# add_source_files: adds the listed source files to your project.
+# set_project_props: sets the project properties that were in effect when this
+# script was generated.
+# create_libraries: creates and adds file to VHDL libraries that were defined when
+# this script was generated.
+# set_process_props: set the process properties as they were set for your project
+# when this script was generated.
+#
+
+set myProject "DE2"
+set myScript "DE2.tcl"
+
+#
+# Main (top-level) routines
+#
+# run_process
+# This procedure is used to run processes on an existing project. You may comment or
+# uncomment lines to control which processes are run. This routine is set up to run
+# the Implement Design and Generate Programming File processes by default. This proc
+# also sets process properties as specified in the "set_process_props" proc. Only
+# those properties which have values different from their current settings in the project
+# file will be modified in the project.
+#
+proc run_process {} {
+
+ global myScript
+ global myProject
+
+ ## put out a 'heartbeat' - so we know something's happening.
+ puts "\n$myScript: running ($myProject)...\n"
+
+ if { ! [ open_project ] } {
+ return false
+ }
+
+ set_process_props
+ #
+ # Remove the comment characters (#'s) to enable the following commands
+ # process run "Synthesize"
+ # process run "Translate"
+ # process run "Map"
+ # process run "Place & Route"
+ #
+ set task "Implement Design"
+ if { ! [run_task $task] } {
+ puts "$myScript: $task run failed, check run output for details."
+ project close
+ return
+ }
+
+ set task "Generate Programming File"
+ if { ! [run_task $task] } {
+ puts "$myScript: $task run failed, check run output for details."
+ project close
+ return
+ }
+
+ puts "Run completed (successfully)."
+ project close
+
+}
+
+#
+# rebuild_project
+#
+# This procedure renames the project file (if it exists) and recreates the project.
+# It then sets project properties and adds project sources as specified by the
+# set_project_props and add_source_files support procs. It recreates VHDL Libraries
+# as they existed at the time this script was generated.
+#
+# It then calls run_process to set process properties and run selected processes.
+#
+proc rebuild_project {} {
+
+ global myScript
+ global myProject
+
+ project close
+ ## put out a 'heartbeat' - so we know something's happening.
+ puts "\n$myScript: Rebuilding ($myProject)...\n"
+
+ set proj_exts [ list ise xise gise ]
+ foreach ext $proj_exts {
+ set proj_name "${myProject}.$ext"
+ if { [ file exists $proj_name ] } {
+ file delete $proj_name
+ }
+ }
+
+ project new $myProject
+ set_project_props
+ add_source_files
+ create_libraries
+ puts "$myScript: project rebuild completed."
+
+ run_process
+
+}
+
+#
+# Support Routines
+#
+
+#
+proc run_task { task } {
+
+ # helper proc for run_process
+
+ puts "Running '$task'"
+ set result [ process run "$task" ]
+ #
+ # check process status (and result)
+ set status [ process get $task status ]
+ if { ( ( $status != "up_to_date" ) && \
+ ( $status != "warnings" ) ) || \
+ ! $result } {
+ return false
+ }
+ return true
+}
+
+#
+# show_help: print information to help users understand the options available when
+# running this script.
+#
+proc show_help {} {
+
+ global myScript
+
+ puts ""
+ puts "usage: xtclsh $myScript "
+ puts " or you can run xtclsh and then enter 'source $myScript'."
+ puts ""
+ puts "options:"
+ puts " run_process - set properties and run processes."
+ puts " rebuild_project - rebuild the project from scratch and run processes."
+ puts " set_project_props - set project properties (device, speed, etc.)"
+ puts " add_source_files - add source files"
+ puts " create_libraries - create vhdl libraries"
+ puts " set_process_props - set process property values"
+ puts " show_help - print this message"
+ puts ""
+}
+
+proc open_project {} {
+
+ global myScript
+ global myProject
+
+ if { ! [ file exists ${myProject}.xise ] } {
+ ## project file isn't there, rebuild it.
+ puts "Project $myProject not found. Use project_rebuild to recreate it."
+ return false
+ }
+
+ project open $myProject
+
+ return true
+
+}
+#
+# set_project_props
+#
+# This procedure sets the project properties as they were set in the project
+# at the time this script was generated.
+#
+proc set_project_props {} {
+
+ global myScript
+
+ if { ! [ open_project ] } {
+ return false
+ }
+
+ puts "$myScript: Setting project properties..."
+
+ project set family "Spartan6"
+ project set device "xc6slx45t"
+ project set package "fgg484"
+ project set speed "-3"
+ project set top_level_module_type "HDL"
+ project set synthesis_tool "XST (VHDL/Verilog)"
+ project set simulator "ISim (VHDL/Verilog)"
+ project set "Preferred Language" "Verilog"
+ project set "Enable Message Filtering" "false"
+
+}
+
+
+#
+# add_source_files
+#
+# This procedure add the source files that were known to the project at the
+# time this script was generated.
+#
+proc add_source_files {} {
+
+ global myScript
+
+ if { ! [ open_project ] } {
+ return false
+ }
+
+ puts "$myScript: Adding sources to project..."
+
+ xfile add "../../../../../../SP6/AI.vhd"
+ xfile add "../../../../../../SP6/CMD_Decode_simple.v"
+ xfile add "../../../../../../SP6/DE2.v"
+ xfile add "../../../../../../SP6/LCD_Controller_safe.v"
+ xfile add "../../../../../../SP6/LCD_TEST_SAFE.v"
+ xfile add "../../../../../../SP6/RS232_Command.h"
+ xfile add "../../../../../../SP6/RS232_Controller.v"
+ xfile add "../../../../../../SP6/Reset_Delay.v"
+ xfile add "../../../../../../SP6/SEG7_LUT.v"
+ xfile add "../../../../../../SP6/SEG7_LUT_8.v"
+ xfile add "../../../../../../SP6/async_receiver_altera.v"
+ xfile add "../../../../../../SP6/async_transmitter_altera.v"
+ xfile add "../../../../../../SP6/bram_based_stream_buffer.v"
+ xfile add "../../../../../../SP6/safe_test.vhd"
+ xfile add "../../../../macrocells/RA1SH.v"
+ xfile add "../../../../macrocells/RA2SH.v"
+ xfile add "../../../../macrocells/SRAM_4.v"
+ xfile add "../../../../macrocells/addsubw.v"
+ xfile add "../../../../macrocells/addw.v"
+ xfile add "../../../../macrocells/andw.v"
+ xfile add "../../../../macrocells/brf.v"
+ xfile add "../../../../macrocells/cmpp_eq_1_4.v"
+ xfile add "../../../../macrocells/cmpp_eq_2_4.v"
+ xfile add "../../../../macrocells/cmpp_ineq_13_40.v"
+ xfile add "../../../../macrocells/cmpp_ineq_21_40.v"
+ xfile add "../../../../macrocells/cmpp_ineq_29_40.v"
+ xfile add "../../../../macrocells/cmpp_ineq_37_40.v"
+ xfile add "../../../../macrocells/cmpp_neq_1_4.v"
+ xfile add "../../../../macrocells/cmpp_neq_2_4.v"
+ xfile add "../../../../macrocells/cmpr_eq.v"
+ xfile add "../../../../macrocells/cmpr_ineq_3.v"
+ xfile add "../../../../macrocells/cmpr_ineq_4.v"
+ xfile add "../../../../macrocells/cmpr_ineq_5.v"
+ xfile add "../../../../macrocells/cmpr_ineq_7.v"
+ xfile add "../../../../macrocells/cmpr_ineq_8.v"
+ xfile add "../../../../macrocells/cmpr_ineq_9.v"
+ xfile add "../../../../macrocells/cmpr_neq.v"
+ xfile add "../../../../macrocells/combine12_wn.v"
+ xfile add "../../../../macrocells/combine26_wn.v"
+ xfile add "../../../../macrocells/combine2_wn.v"
+ xfile add "../../../../macrocells/combine32_wn.v"
+ xfile add "../../../../macrocells/combine3_wn.v"
+ xfile add "../../../../macrocells/counter.v"
+ xfile add "../../../../macrocells/decode.v"
+ xfile add "../../../../macrocells/delayn.v"
+ xfile add "../../../../macrocells/equal.v"
+ xfile add "../../../../macrocells/fifo.v"
+ xfile add "../../../../macrocells/ldlm_lx.v"
+ xfile add "../../../../macrocells/ldlmff_raw_lx.v"
+ xfile add "../../../../macrocells/ldstlm_lx.v"
+ xfile add "../../../../macrocells/ldstlmff_lx.v"
+ xfile add "../../../../macrocells/ldstr_sx.v"
+ xfile add "../../../../macrocells/lshiftw.v"
+ xfile add "../../../../macrocells/minmaxw_0.v"
+ xfile add "../../../../macrocells/minmaxw_1.v"
+ xfile add "../../../../macrocells/mpyw_1_stage.v"
+ xfile add "../../../../macrocells/mpyw_multi_stage.v"
+ xfile add "../../../../macrocells/orw.v"
+ xfile add "../../../../macrocells/rsflipflop_noinit.v"
+ xfile add "../../../../macrocells/select_11_1_wn.v"
+ xfile add "../../../../macrocells/select_12_1_wn.v"
+ xfile add "../../../../macrocells/select_17_1_wn.v"
+ xfile add "../../../../macrocells/select_1_1_wn.v"
+ xfile add "../../../../macrocells/select_2_1_wn.v"
+ xfile add "../../../../macrocells/select_3_1_wn.v"
+ xfile add "../../../../macrocells/select_4_1_wn.v"
+ xfile add "../../../../macrocells/select_5_1_wn.v"
+ xfile add "../../../../macrocells/select_6_1_wn.v"
+ xfile add "../../../../macrocells/select_7_1_wn.v"
+ xfile add "../../../../macrocells/select_8_1_wn.v"
+ xfile add "../../../../macrocells/select_9_1_wn.v"
+ xfile add "../../../../macrocells/sext.v"
+ xfile add "../../../../macrocells/shlkw.v"
+ xfile add "../../../../macrocells/shrkw.v"
+ xfile add "../../../../macrocells/sramff_raw_1.v"
+ xfile add "../../../../macrocells/sramff_raw_2.v"
+ xfile add "../../../../macrocells/sramff_raw_4.v"
+ xfile add "../../../../macrocells/sregn_noinit.v"
+ xfile add "../../../../macrocells/staller.v"
+ xfile add "../../../../macrocells/stlm_lx.v"
+ xfile add "../../../../macrocells/stlmff_raw_lx.v"
+ xfile add "../../../../macrocells/ststr_sx.v"
+ xfile add "../../../../macrocells/xorw.v"
+ xfile add "../../../../rtl/ai_adjacent_pa_0.v"
+ xfile add "../../../../rtl/ai_adjacent_paw_0.v"
+ xfile add "../../../../rtl/ai_adjacent_pe_0.v"
+ xfile add "../../../../rtl/ai_adjacent_tcab.v"
+ xfile add "../../../../rtl/ai_adjacent_tcab_assertions.v"
+ xfile add "../../../../rtl/ai_threats_pa_0.v"
+ xfile add "../../../../rtl/ai_threats_paw_0.v"
+ xfile add "../../../../rtl/ai_threats_pe_0.v"
+ xfile add "../../../../rtl/ai_threats_tcab.v"
+ xfile add "../../../../rtl/ai_threats_tcab_assertions.v"
+ xfile add "../../../../rtl/ai_threats_wide_ldstream0_0.v"
+ xfile add "../../../../rtl/ai_threats_wide_ststream0_0.v"
+ xfile add "../../../../rtl/connect6ai_synth_pa_0.v"
+ xfile add "../../../../rtl/connect6ai_synth_paw_0.v"
+ xfile add "../../../../rtl/connect6ai_synth_pe_0.v"
+ xfile add "../../../../rtl/connect6ai_synth_tcab.v"
+ xfile add "../../../../rtl/connect6ai_synth_tcab_assertions.v"
+ xfile add "../../../../rtl/threat_line_pa_0.v"
+ xfile add "../../../../rtl/threat_line_paw_0.v"
+ xfile add "../../../../rtl/threat_line_pe_0.v"
+ xfile add "../../../../rtl/threat_line_tcab.v"
+ xfile add "../../../../rtl/threat_line_tcab_assertions.v"
+ xfile add "../../../../rtl/threat_window_pa_0.v"
+ xfile add "../../../../rtl/threat_window_paw_0.v"
+ xfile add "../../../../rtl/threat_window_pe_0.v"
+ xfile add "../../../../rtl/threat_window_tcab.v"
+ xfile add "../../../../rtl/threat_window_tcab_assertions.v"
+
+ # Set the Top Module as well...
+ project set top "DE2"
+
+ puts "$myScript: project sources reloaded."
+
+} ; # end add_source_files
+
+#
+# create_libraries
+#
+# This procedure defines VHDL libraries and associates files with those libraries.
+# It is expected to be used when recreating the project. Any libraries defined
+# when this script was generated are recreated by this procedure.
+#
+proc create_libraries {} {
+
+ global myScript
+
+ if { ! [ open_project ] } {
+ return false
+ }
+
+ puts "$myScript: Creating libraries..."
+
+
+ # must close the project or library definitions aren't saved.
+ project save
+
+} ; # end create_libraries
+
+#
+# set_process_props
+#
+# This procedure sets properties as requested during script generation (either
+# all of the properties, or only those modified from their defaults).
+#
+proc set_process_props {} {
+
+ global myScript
+
+ if { ! [ open_project ] } {
+ return false
+ }
+
+ puts "$myScript: setting process properties..."
+
+ #project set "Compiled Library Directory" "\$XILINX//"
+ ##project set "Global Optimization" "Off" -process "Map"
+ #project set "Pack I/O Registers/Latches into IOBs" "Off" -process "Map"
+ #project set "Place And Route Mode" "Route Only" -process "Place & Route"
+ #project set "Regenerate Core" "Under Current Project Setting" -process "Regenerate Core"
+ #project set "Filter Files From Compile Order" "true"
+ #project set "Last Applied Goal" "Balanced"
+ #project set "Last Applied Strategy" "Xilinx Default (unlocked)"
+ #project set "Last Unlock Status" "false"
+ #project set "Manual Compile Order" "false"
+ #project set "Placer Effort Level" "High" -process "Map"
+ #project set "Extra Cost Tables" "0" -process "Map"
+ #project set "LUT Combining" "Off" -process "Map"
+ #project set "Combinatorial Logic Optimization" "false" -process "Map"
+ #project set "Starting Placer Cost Table (1-100)" "1" -process "Map"
+ #project set "Power Reduction" "Off" -process "Map"
+ #project set "Report Fastest Path(s) in Each Constraint" "true" -process "Generate Post-Place & Route Static Timing"
+ #project set "Generate Datasheet Section" "true" -process "Generate Post-Place & Route Static Timing"
+ #project set "Generate Timegroups Section" "false" -process "Generate Post-Place & Route Static Timing"
+ #project set "Report Fastest Path(s) in Each Constraint" "true" -process "Generate Post-Map Static Timing"
+ #project set "Generate Datasheet Section" "true" -process "Generate Post-Map Static Timing"
+ #project set "Generate Timegroups Section" "false" -process "Generate Post-Map Static Timing"
+ #project set "Project Description" ""
+ #project set "Property Specification in Project File" "Store all values"
+ #project set "Reduce Control Sets" "Auto" -process "Synthesize - XST"
+ #project set "Shift Register Minimum Size" "2" -process "Synthesize - XST"
+ #project set "Case Implementation Style" "None" -process "Synthesize - XST"
+ #project set "RAM Extraction" "true" -process "Synthesize - XST"
+ #project set "ROM Extraction" "true" -process "Synthesize - XST"
+ #project set "FSM Encoding Algorithm" "Auto" -process "Synthesize - XST"
+ #project set "Optimization Goal" "Speed" -process "Synthesize - XST"
+ #project set "Optimization Effort" "Normal" -process "Synthesize - XST"
+ #project set "Resource Sharing" "true" -process "Synthesize - XST"
+ #project set "Shift Register Extraction" "true" -process "Synthesize - XST"
+ #project set "User Browsed Strategy Files" "/opt/Xilinx/13.4/ISE_DS/ISE/data/default.xds"
+ #project set "VHDL Source Analysis Standard" "VHDL-93"
+ ##project set "Analysis Effort Level" "Standard" -process "Analyze Power Distribution (XPower Analyzer)"
+ ##project set "Analysis Effort Level" "Standard" -process "Generate Text Power Report"
+ #project set "Input TCL Command Script" "" -process "Generate Text Power Report"
+ #project set "Load Physical Constraints File" "Default" -process "Analyze Power Distribution (XPower Analyzer)"
+ #project set "Load Physical Constraints File" "Default" -process "Generate Text Power Report"
+ #project set "Load Simulation File" "Default" -process "Analyze Power Distribution (XPower Analyzer)"
+ #project set "Load Simulation File" "Default" -process "Generate Text Power Report"
+ #project set "Load Setting File" "" -process "Analyze Power Distribution (XPower Analyzer)"
+ #project set "Load Setting File" "" -process "Generate Text Power Report"
+ #project set "Setting Output File" "" -process "Generate Text Power Report"
+ #project set "Produce Verbose Report" "false" -process "Generate Text Power Report"
+ #project set "Other XPWR Command Line Options" "" -process "Generate Text Power Report"
+ ##project set "Essential Bits" "false" -process "Generate Programming File"
+ #project set "Other Bitgen Command Line Options" "" -process "Generate Programming File"
+ #project set "Maximum Signal Name Length" "20" -process "Generate IBIS Model"
+ #project set "Show All Models" "false" -process "Generate IBIS Model"
+ ##project set "VCCAUX Voltage Level" "2.5V" -process "Generate IBIS Model"
+ #project set "Disable Detailed Package Model Insertion" "false" -process "Generate IBIS Model"
+ #project set "Launch SDK after Export" "true" -process "Export Hardware Design To SDK with Bitstream"
+ #project set "Launch SDK after Export" "true" -process "Export Hardware Design To SDK without Bitstream"
+ #project set "Target UCF File Name" "" -process "Back-annotate Pin Locations"
+ #project set "Ignore User Timing Constraints" "false" -process "Map"
+ #project set "Register Ordering" "4" -process "Map"
+ #project set "Use RLOC Constraints" "Yes" -process "Map"
+ #project set "Other Map Command Line Options" "" -process "Map"
+ #project set "Use LOC Constraints" "true" -process "Translate"
+ #project set "Other Ngdbuild Command Line Options" "" -process "Translate"
+ #project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "Floorplan Area/IO/Logic (PlanAhead)"
+ #project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "I/O Pin Planning (PlanAhead) - Pre-Synthesis"
+ #project set "Use 64-bit PlanAhead on 64-bit Systems" "true" -process "I/O Pin Planning (PlanAhead) - Post-Synthesis"
+ #project set "Ignore User Timing Constraints" "false" -process "Place & Route"
+ #project set "Other Place & Route Command Line Options" "" -process "Place & Route"
+ #project set "Use DSP Block" "Auto" -process "Synthesize - XST"
+ #project set "UserID Code (8 Digit Hexadecimal)" "0xFFFFFFFF" -process "Generate Programming File"
+ #project set "Configuration Pin Done" "Pull Up" -process "Generate Programming File"
+ ##project set "Enable External Master Clock" "false" -process "Generate Programming File"
+ #project set "Create ASCII Configuration File" "false" -process "Generate Programming File"
+ #project set "Create Bit File" "true" -process "Generate Programming File"
+ #project set "Enable BitStream Compression" "false" -process "Generate Programming File"
+ #project set "Run Design Rules Checker (DRC)" "true" -process "Generate Programming File"
+ #project set "Enable Cyclic Redundancy Checking (CRC)" "true" -process "Generate Programming File"
+ #project set "Create IEEE 1532 Configuration File" "false" -process "Generate Programming File"
+ #project set "Create ReadBack Data Files" "false" -process "Generate Programming File"
+ #project set "Configuration Pin Program" "Pull Up" -process "Generate Programming File"
+ #project set "Place MultiBoot Settings into Bitstream" "false" -process "Generate Programming File"
+ #project set "Configuration Rate" "2" -process "Generate Programming File"
+ #project set "Set SPI Configuration Bus Width" "1" -process "Generate Programming File"
+ #project set "JTAG Pin TCK" "Pull Up" -process "Generate Programming File"
+ #project set "JTAG Pin TDI" "Pull Up" -process "Generate Programming File"
+ #project set "JTAG Pin TDO" "Pull Up" -process "Generate Programming File"
+ #project set "JTAG Pin TMS" "Pull Up" -process "Generate Programming File"
+ #project set "Unused IOB Pins" "Pull Down" -process "Generate Programming File"
+ #project set "Watchdog Timer Value" "0xFFFF" -process "Generate Programming File"
+ #project set "Security" "Enable Readback and Reconfiguration" -process "Generate Programming File"
+ #project set "FPGA Start-Up Clock" "CCLK" -process "Generate Programming File"
+ #project set "Done (Output Events)" "Default (4)" -process "Generate Programming File"
+ #project set "Drive Done Pin High" "false" -process "Generate Programming File"
+ #project set "Enable Outputs (Output Events)" "Default (5)" -process "Generate Programming File"
+ #project set "Wait for DCM and PLL Lock (Output Events)" "Default (NoWait)" -process "Generate Programming File"
+ #project set "Release Write Enable (Output Events)" "Default (6)" -process "Generate Programming File"
+ #project set "Enable Internal Done Pipe" "false" -process "Generate Programming File"
+ #project set "Drive Awake Pin During Suspend/Wake Sequence" "false" -process "Generate Programming File"
+ #project set "Enable Suspend/Wake Global Set/Reset" "false" -process "Generate Programming File"
+ #project set "Enable Multi-Pin Wake-Up Suspend Mode" "false" -process "Generate Programming File"
+ #project set "GTS Cycle During Suspend/Wakeup Sequence" "4" -process "Generate Programming File"
+ #project set "GWE Cycle During Suspend/Wakeup Sequence" "5" -process "Generate Programming File"
+ #project set "Wakeup Clock" "Startup Clock" -process "Generate Programming File"
+ #project set "Allow Logic Optimization Across Hierarchy" "false" -process "Map"
+ #project set "Maximum Compression" "false" -process "Map"
+ #project set "Generate Detailed MAP Report" "false" -process "Map"
+ #project set "Map Slice Logic into Unused Block RAMs" "false" -process "Map"
+ #project set "Perform Timing-Driven Packing and Placement" "false"
+ #project set "Trim Unconnected Signals" "true" -process "Map"
+ #project set "Create I/O Pads from Ports" "false" -process "Translate"
+ #project set "Macro Search Path" "" -process "Translate"
+ #project set "Netlist Translation Type" "Timestamp" -process "Translate"
+ #project set "User Rules File for Netlister Launcher" "" -process "Translate"
+ #project set "Allow Unexpanded Blocks" "false" -process "Translate"
+ #project set "Allow Unmatched LOC Constraints" "false" -process "Translate"
+ #project set "Allow Unmatched Timing Group Constraints" "false" -process "Translate"
+ #project set "Perform Advanced Analysis" "false" -process "Generate Post-Place & Route Static Timing"
+ #project set "Report Paths by Endpoint" "3" -process "Generate Post-Place & Route Static Timing"
+ #project set "Report Type" "Verbose Report" -process "Generate Post-Place & Route Static Timing"
+ #project set "Number of Paths in Error/Verbose Report" "3" -process "Generate Post-Place & Route Static Timing"
+ #project set "Stamp Timing Model Filename" "" -process "Generate Post-Place & Route Static Timing"
+ #project set "Report Unconstrained Paths" "" -process "Generate Post-Place & Route Static Timing"
+ #project set "Perform Advanced Analysis" "false" -process "Generate Post-Map Static Timing"
+ #project set "Report Paths by Endpoint" "3" -process "Generate Post-Map Static Timing"
+ #project set "Report Type" "Verbose Report" -process "Generate Post-Map Static Timing"
+ #project set "Number of Paths in Error/Verbose Report" "3" -process "Generate Post-Map Static Timing"
+ #project set "Report Unconstrained Paths" "" -process "Generate Post-Map Static Timing"
+ #project set "Number of Clock Buffers" "16" -process "Synthesize - XST"
+ #project set "Add I/O Buffers" "true" -process "Synthesize - XST"
+ #project set "Global Optimization Goal" "AllClockNets" -process "Synthesize - XST"
+ #project set "Keep Hierarchy" "No" -process "Synthesize - XST"
+ #project set "Max Fanout" "100000" -process "Synthesize - XST"
+ #project set "Register Balancing" "No" -process "Synthesize - XST"
+ #project set "Register Duplication" "true" -process "Synthesize - XST"
+ #project set "Library for Verilog Sources" "" -process "Synthesize - XST"
+ #project set "Export Results to XPower Estimator" "" -process "Generate Text Power Report"
+ #project set "Asynchronous To Synchronous" "false" -process "Synthesize - XST"
+ #project set "Automatic BRAM Packing" "false" -process "Synthesize - XST"
+ #project set "BRAM Utilization Ratio" "100" -process "Synthesize - XST"
+ #project set "Bus Delimiter" "<>" -process "Synthesize - XST"
+ #project set "Case" "Maintain" -process "Synthesize - XST"
+ #project set "Cores Search Directories" "" -process "Synthesize - XST"
+ #project set "Cross Clock Analysis" "false" -process "Synthesize - XST"
+ #project set "DSP Utilization Ratio" "100" -process "Synthesize - XST"
+ #project set "Equivalent Register Removal" "true" -process "Synthesize - XST"
+ #project set "FSM Style" "LUT" -process "Synthesize - XST"
+ #project set "Generate RTL Schematic" "Yes" -process "Synthesize - XST"
+ #project set "Generics, Parameters" "" -process "Synthesize - XST"
+ #project set "Hierarchy Separator" "/" -process "Synthesize - XST"
+ #project set "HDL INI File" "" -process "Synthesize - XST"
+ #project set "LUT Combining" "Auto" -process "Synthesize - XST"
+ #project set "Library Search Order" "" -process "Synthesize - XST"
+ #project set "Netlist Hierarchy" "As Optimized" -process "Synthesize - XST"
+ #project set "Optimize Instantiated Primitives" "false" -process "Synthesize - XST"
+ #project set "Pack I/O Registers into IOBs" "Auto" -process "Synthesize - XST"
+ #project set "Power Reduction" "false" -process "Synthesize - XST"
+ #project set "Read Cores" "true" -process "Synthesize - XST"
+ #project set "Use Clock Enable" "Auto" -process "Synthesize - XST"
+ #project set "Use Synchronous Reset" "Auto" -process "Synthesize - XST"
+ #project set "Use Synchronous Set" "Auto" -process "Synthesize - XST"
+ #project set "Use Synthesis Constraints File" "true" -process "Synthesize - XST"
+ #project set "Verilog Include Directories" "" -process "Synthesize - XST"
+ #project set "Verilog Macros" "" -process "Synthesize - XST"
+ #project set "Work Directory" "/tmp/BUILD_SCC/imp_connect/rtl_package/synth/synplify_fpga/run_2012.05.04_15.04.58/DE2/xst" -process "Synthesize - XST"
+ #project set "Write Timing Constraints" "false" -process "Synthesize - XST"
+ #project set "Other XST Command Line Options" "" -process "Synthesize - XST"
+ #project set "Timing Mode" "Performance Evaluation" -process "Map"
+ #project set "Generate Asynchronous Delay Report" "false" -process "Place & Route"
+ #project set "Generate Clock Region Report" "false" -process "Place & Route"
+ #project set "Generate Post-Place & Route Power Report" "false" -process "Place & Route"
+ #project set "Generate Post-Place & Route Simulation Model" "false" -process "Place & Route"
+ #project set "Power Reduction" "false" -process "Place & Route"
+ #project set "Place & Route Effort Level (Overall)" "High" -process "Place & Route"
+ #project set "Auto Implementation Compile Order" "true"
+ #project set "Equivalent Register Removal" "true" -process "Map"
+ #project set "Placer Extra Effort" "None" -process "Map"
+ #project set "Power Activity File" "" -process "Map"
+ #project set "Register Duplication" "Off" -process "Map"
+ #project set "Generate Constraints Interaction Report" "false" -process "Generate Post-Map Static Timing"
+ #project set "Synthesis Constraints File" "" -process "Synthesize - XST"
+ #project set "RAM Style" "Auto" -process "Synthesize - XST"
+ #project set "Maximum Number of Lines in Report" "1000" -process "Generate Text Power Report"
+ #project set "MultiBoot: Insert IPROG CMD in the Bitfile" "Enable" -process "Generate Programming File"
+ #project set "Output File Name" "ai_adjacent_tcab" -process "Generate IBIS Model"
+ #project set "Timing Mode" "Performance Evaluation" -process "Place & Route"
+ #project set "Create Binary Configuration File" "false" -process "Generate Programming File"
+ #project set "Enable Debugging of Serial Mode BitStream" "false" -process "Generate Programming File"
+ #project set "Create Logic Allocation File" "false" -process "Generate Programming File"
+ #project set "Create Mask File" "false" -process "Generate Programming File"
+ #project set "Retry Configuration if CRC Error Occurs" "false" -process "Generate Programming File"
+ #project set "MultiBoot: Starting Address for Next Configuration" "0x00000000" -process "Generate Programming File"
+ #project set "MultiBoot: Starting Address for Golden Configuration" "0x00000000" -process "Generate Programming File"
+ #project set "MultiBoot: Use New Mode for Next Configuration" "true" -process "Generate Programming File"
+ #project set "MultiBoot: User-Defined Register for Failsafe Scheme" "0x0000" -process "Generate Programming File"
+ #project set "Setup External Master Clock Division" "1" -process "Generate Programming File"
+ #project set "Allow SelectMAP Pins to Persist" "false" -process "Generate Programming File"
+ #project set "Mask Pins for Multi-Pin Wake-Up Suspend Mode" "0x00" -process "Generate Programming File"
+ #project set "Enable Multi-Threading" "Off" -process "Map"
+ #project set "Generate Constraints Interaction Report" "false" -process "Generate Post-Place & Route Static Timing"
+ #project set "Move First Flip-Flop Stage" "true" -process "Synthesize - XST"
+ #project set "Move Last Flip-Flop Stage" "true" -process "Synthesize - XST"
+ #project set "ROM Style" "Auto" -process "Synthesize - XST"
+ #project set "Safe Implementation" "No" -process "Synthesize - XST"
+ #project set "Power Activity File" "" -process "Place & Route"
+ #project set "Extra Effort (Highest PAR level only)" "None" -process "Place & Route"
+ #project set "MultiBoot: Next Configuration Mode" "001" -process "Generate Programming File"
+ #project set "Encrypt Bitstream" "false" -process "Generate Programming File"
+ #project set "Enable Multi-Threading" "Off" -process "Place & Route"
+ #project set "AES Initial Vector" "" -process "Generate Programming File"
+ #project set "Encrypt Key Select" "BBRAM" -process "Generate Programming File"
+ #project set "AES Key (Hex String)" "" -process "Generate Programming File"
+ #project set "Input Encryption Key File" "" -process "Generate Programming File"
+ #project set "Functional Model Target Language" "Verilog" -process "View HDL Source"
+ #project set "Change Device Speed To" "-3" -process "Generate Post-Place & Route Static Timing"
+ #project set "Change Device Speed To" "-3" -process "Generate Post-Map Static Timing"
+
+ puts "$myScript: project property values set."
+
+} ; # end set_process_props
+
+proc main {} {
+
+ if { [llength $::argv] == 0 } {
+ show_help
+ return true
+ }
+
+ foreach option $::argv {
+ switch $option {
+ "show_help" { show_help }
+ "run_process" { run_process }
+ "rebuild_project" { rebuild_project }
+ "set_project_props" { set_project_props }
+ "add_source_files" { add_source_files }
+ "create_libraries" { create_libraries }
+ "set_process_props" { set_process_props }
+ default { puts "unrecognized option: $option"; show_help }
+ }
+ }
+}
+
+if { $tcl_interactive } {
+ show_help
+} else {
+ if {[catch {main} result]} {
+ puts "$myScript failed: $result."
+ }
+}
+
Index: trunk/XILINX/BUILD_SCC/SP6/async_receiver_altera.v
===================================================================
--- trunk/XILINX/BUILD_SCC/SP6/async_receiver_altera.v (nonexistent)
+++ trunk/XILINX/BUILD_SCC/SP6/async_receiver_altera.v (revision 17)
@@ -0,0 +1,92 @@
+module async_receiver(clk, RxD, RxD_data_ready, RxD_data, RxD_endofpacket, RxD_idle);
+input clk, RxD;
+output RxD_data_ready; // onc clock pulse when RxD_data is valid
+output [7:0] RxD_data;
+
+//parameter ClkFrequency = 62500000; // 50MHz
+parameter ClkFrequency = 20000000; // 50MHz
+//parameter ClkFrequency = 27000000; // 27MHz
+parameter Baud = 115200;
+
+// We also detect if a gap occurs in the received stream of characters
+// That can be useful if multiple characters are sent in burst
+// so that multiple characters can be treated as a "packet"
+output RxD_endofpacket; // one clock pulse, when no more data is received (RxD_idle is going high)
+output RxD_idle; // no data is being received
+
+// Baud generator (we use 8 times oversampling)
+parameter Baud8 = Baud*8;
+parameter Baud8GeneratorAccWidth = 16;
+parameter Baud8GeneratorInc = ((Baud8<<(Baud8GeneratorAccWidth-7))+(ClkFrequency>>8))/(ClkFrequency>>7);
+reg [Baud8GeneratorAccWidth:0] Baud8GeneratorAcc;
+always @(posedge clk) Baud8GeneratorAcc <= Baud8GeneratorAcc[Baud8GeneratorAccWidth-1:0] + Baud8GeneratorInc;
+wire Baud8Tick = Baud8GeneratorAcc[Baud8GeneratorAccWidth];
+
+////////////////////////////
+reg [1:0] RxD_sync_inv;
+always @(posedge clk) if(Baud8Tick) RxD_sync_inv <= {RxD_sync_inv[0], ~RxD};
+// we invert RxD, so that the idle becomes "0", to prevent a phantom character to be received at startup
+
+reg [1:0] RxD_cnt_inv;
+reg RxD_bit_inv;
+
+always @(posedge clk)
+if(Baud8Tick)
+begin
+ if( RxD_sync_inv[1] && RxD_cnt_inv!=2'b11) RxD_cnt_inv <= RxD_cnt_inv + 1;
+ else
+ if(~RxD_sync_inv[1] && RxD_cnt_inv!=2'b00) RxD_cnt_inv <= RxD_cnt_inv - 1;
+
+ if(RxD_cnt_inv==2'b00) RxD_bit_inv <= 0;
+ else
+ if(RxD_cnt_inv==2'b11) RxD_bit_inv <= 1;
+end
+
+reg [3:0] state;
+reg [3:0] bit_spacing;
+
+// "next_bit" controls when the data sampling occurs
+// depending on how noisy the RxD is, different values might work better
+// with a clean connection, values from 8 to 11 work
+wire next_bit = (bit_spacing==10);
+
+always @(posedge clk)
+if(state==0)
+ bit_spacing <= 0;
+else
+if(Baud8Tick)
+ bit_spacing <= {bit_spacing[2:0] + 1} | {bit_spacing[3], 3'b000};
+
+always @(posedge clk)
+if(Baud8Tick)
+case(state)
+ 4'b0000: if(RxD_bit_inv) state <= 4'b1000; // start bit found?
+ 4'b1000: if(next_bit) state <= 4'b1001; // bit 0
+ 4'b1001: if(next_bit) state <= 4'b1010; // bit 1
+ 4'b1010: if(next_bit) state <= 4'b1011; // bit 2
+ 4'b1011: if(next_bit) state <= 4'b1100; // bit 3
+ 4'b1100: if(next_bit) state <= 4'b1101; // bit 4
+ 4'b1101: if(next_bit) state <= 4'b1110; // bit 5
+ 4'b1110: if(next_bit) state <= 4'b1111; // bit 6
+ 4'b1111: if(next_bit) state <= 4'b0001; // bit 7
+ 4'b0001: if(next_bit) state <= 4'b0000; // stop bit
+ default: state <= 4'b0000;
+endcase
+
+reg [7:0] RxD_data;
+always @(posedge clk)
+if(Baud8Tick && next_bit && state[3]) RxD_data <= {~RxD_bit_inv, RxD_data[7:1]};
+
+reg RxD_data_ready, RxD_data_error;
+always @(posedge clk)
+begin
+ RxD_data_ready <= (Baud8Tick && next_bit && state==4'b0001 && ~RxD_bit_inv); // ready only if the stop bit is received
+ RxD_data_error <= (Baud8Tick && next_bit && state==4'b0001 && RxD_bit_inv); // error if the stop bit is not received
+end
+
+reg [4:0] gap_count;
+always @(posedge clk) if (state!=0) gap_count<=0; else if(Baud8Tick & ~gap_count[4]) gap_count <= gap_count + 1;
+assign RxD_idle = gap_count[4];
+reg RxD_endofpacket; always @(posedge clk) RxD_endofpacket <= Baud8Tick & (gap_count==15);
+
+endmodule
trunk/XILINX/BUILD_SCC/SP6/async_receiver_altera.v
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC/SP6/SEG7_LUT.v
===================================================================
--- trunk/XILINX/BUILD_SCC/SP6/SEG7_LUT.v (nonexistent)
+++ trunk/XILINX/BUILD_SCC/SP6/SEG7_LUT.v (revision 17)
@@ -0,0 +1,28 @@
+module SEG7_LUT ( oSEG,iDIG );
+input [3:0] iDIG;
+output [6:0] oSEG;
+reg [6:0] oSEG;
+
+always @(iDIG)
+begin
+ case(iDIG)
+ 4'h1: oSEG = 7'b1111001; // ---t----
+ 4'h2: oSEG = 7'b0100100; // | |
+ 4'h3: oSEG = 7'b0110000; // lt rt
+ 4'h4: oSEG = 7'b0011001; // | |
+ 4'h5: oSEG = 7'b0010010; // ---m----
+ 4'h6: oSEG = 7'b0000010; // | |
+ 4'h7: oSEG = 7'b1111000; // lb rb
+ 4'h8: oSEG = 7'b0000000; // | |
+ 4'h9: oSEG = 7'b0011000; // ---b----
+ 4'ha: oSEG = 7'b0001000;
+ 4'hb: oSEG = 7'b0000011;
+ 4'hc: oSEG = 7'b1000110;
+ 4'hd: oSEG = 7'b0100001;
+ 4'he: oSEG = 7'b0000110;
+ 4'hf: oSEG = 7'b0001110;
+ 4'h0: oSEG = 7'b1000000;
+ endcase
+end
+
+endmodule
trunk/XILINX/BUILD_SCC/SP6/SEG7_LUT.v
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC/SP6/safe_test.vhd
===================================================================
--- trunk/XILINX/BUILD_SCC/SP6/safe_test.vhd (nonexistent)
+++ trunk/XILINX/BUILD_SCC/SP6/safe_test.vhd (revision 17)
@@ -0,0 +1,384 @@
+library ieee;
+use ieee.std_logic_1164.all;
+--use ieee.numeric_bit.all;
+use ieee.std_logic_arith.all;
+
+
+
+entity safe_test is
+generic(INPUT_LENGTH:integer:=6;OUTPUT_LENGTH:integer:=6);
+ port(
+ clk:in std_ulogic;
+ rst:in std_ulogic;
+ --Config Signals
+ init_out:out std_ulogic;
+ config_mode_out:out std_ulogic;
+ config_out0:out std_ulogic;
+ config_out1:out std_ulogic;
+ config_ack_in:in std_ulogic;
+ --DE2 Control SIgnals
+ msg_out:out std_ulogic_vector(2 downto 0);
+ Ack_count_out:out std_logic_vector(31 downto 0);
+ cmd:in std_ulogic_vector(4 downto 0);
+ --SRAM
+ SRAM_DATA_OUT: OUT std_logic_vector(15 downto 0);
+ SRAM_DATA: in std_logic_vector(15 downto 0);
+ SRAM_ADDR: out std_logic_vector(23 downto 0);
+ SRAM_WEN: out std_logic;
+ SRAM_OEN: out std_logic;
+ --SDRAM
+ SDRAM_DATA: out std_logic_vector(15 downto 0);
+ SDRAM_ADDR: out std_logic_vector(23 downto 0);
+ SDRAM_WEN: out std_logic;
+ SDRAM_OEN: out std_logic;
+ --Result Vectors
+ INPUT_ASYNC_0: in std_ulogic_vector(INPUT_LENGTH-1 downto 0);
+ INPUT_ASYNC_1: in std_ulogic_vector(INPUT_LENGTH-1 downto 0);
+ INPUT_ASYNC_ACKOUT: out std_ulogic_vector(INPUT_LENGTH-1 downto 0);
+ --Test Vectors
+ OUTPUT_ASYNC_0: out std_ulogic_vector(OUTPUT_LENGTH-1 downto 0);
+ OUTPUT_ASYNC_1: out std_ulogic_vector(OUTPUT_LENGTH-1 downto 0);
+ OUTPUT_ASYNC_ACKIN: in std_ulogic_vector(OUTPUT_LENGTH-1 downto 0);
+
+ --Trigger for oscilloscope
+ trigger: out std_ulogic
+
+ );
+end entity safe_test;
+
+
+architecture machine_a_etat of safe_test is
+component S_TO_AS_CONFIG is
+generic (BEGIN_ADDR:integer:=0;END_ADDR:integer:=0;LENGTH:integer:=16);
+ port(
+ clk:in std_ulogic;
+ rst:in std_ulogic;
+
+ SRAM_DATA_OUT: out std_logic_vector(15 downto 0);
+ SRAM_DATA: in std_logic_vector(15 downto 0);
+ SRAM_ADDR: out std_logic_vector(23 downto 0);
+ SRAM_WEN: out std_logic;
+ SRAM_OEN: out std_logic;
+
+ AS_OUT0: out std_ulogic;
+ AS_OUT1: out std_ulogic;
+ ACK_IN: in std_ulogic;
+
+ config_enable: in std_ulogic; -- Command from the state_machine up there
+ ACK_COUNT_OUT: out std_logic_vector(31 downto 0)
+ );
+end component S_TO_AS_CONFIG;
+
+component AS_TO_S_VECTOR is
+generic (BEGIN_ADDR:integer:=0;END_ADDR:integer:=0;LENGTH:integer:=16);
+ port(
+ clk:in std_ulogic;
+ rst:in std_ulogic;
+
+ SRAM_DATA: out std_logic_vector(15 downto 0);
+ SRAM_ADDR: out std_logic_vector(23 downto 0);
+ SRAM_WEN: out std_logic;
+ SRAM_OEN: out std_logic;
+
+ I_ASYNC_0: in std_ulogic_vector(LENGTH-1 downto 0);
+ I_ASYNC_1: in std_ulogic_vector(LENGTH-1 downto 0);
+ I_ASYNC_ACK_OUT: out std_ulogic_vector(LENGTH-1 downto 0);
+
+ vector_enable: in std_ulogic; -- Command from the state_machine up there
+ ACK_COUNT_OUT: out std_logic_vector(31 downto 0)
+ );
+end component AS_TO_S_VECTOR;
+
+component S_TO_AS_VECTOR is
+generic (BEGIN_ADDR:integer:=0;END_ADDR:integer:=0;LENGTH:integer:=16);
+ port(
+ clk:in std_ulogic;
+ rst:in std_ulogic;
+ trigger:out std_ulogic;
+
+ SRAM_DATA: in std_logic_vector(15 downto 0);
+ SRAM_ADDR: out std_logic_vector(23 downto 0);
+ SRAM_WEN: out std_logic;
+ SRAM_OEN: out std_logic;
+
+ O_ASYNC_0: out std_ulogic_vector(LENGTH-1 downto 0);
+ O_ASYNC_1: out std_ulogic_vector(LENGTH-1 downto 0);
+ O_ASYNC_ACK_IN: in std_ulogic_vector(LENGTH-1 downto 0);
+
+ vector_enable: in std_ulogic; -- Command from the state_machine up there
+ ACK_COUNT_OUT: out std_logic_vector(31 downto 0)
+ );
+end component S_TO_AS_VECTOR;
+
+--type STATE_TYPE is(IDLE,INIT,CONFIG,RUNNING);
+--signal state,next_state:STATE_TYPE;
+signal msg_out_int:std_ulogic_vector(2 downto 0);
+signal count:integer range 0 to integer'high;
+signal count_in,count_out:std_logic_vector(31 downto 0);
+signal config_enable,run_enable,safe_rst:std_ulogic;
+signal SRAM_DATA_TEST,SRAM_DATA_CONFIG:std_logic_vector(15 downto 0);
+signal SRAM_ADDR_TEST,SRAM_ADDR_CONFIG:std_logic_vector(23 downto 0);
+signal SRAM_WEN_CONFIG,SRAM_WEN_TEST,SRAM_OEN_CONFIG,SRAM_OEN_TEST:std_logic;
+signal trig_count:integer range 0 to integer'high;
+begin
+ msg_out<=msg_out_int;
+ TRANSLATE: S_TO_AS_CONFIG
+ generic map(BEGIN_ADDR=>0,END_ADDR=>293,LENGTH=>1)
+ port map(
+ clk=>clk,
+ rst=>rst,
+
+ SRAM_DATA_OUT=>SRAM_DATA_OUT,
+ SRAM_DATA=>SRAM_DATA,
+ SRAM_ADDR=>SRAM_ADDR_CONFIG,
+ SRAM_WEN=>SRAM_WEN_CONFIG,
+ SRAM_OEN=>SRAM_OEN_CONFIG,
+
+ AS_OUT0=>config_out0,
+ AS_OUT1=>config_out1,
+ ACK_IN=>config_ack_in,
+
+ config_enable=>config_enable,
+ ACK_COUNT_OUT=>Ack_count_out);
+
+
+ TRANSLATE_S_TO_AS:S_TO_AS_VECTOR
+ generic map(BEGIN_ADDR=>4096,END_ADDR=>4159,LENGTH=>OUTPUT_LENGTH)
+ port map(
+ clk=>clk,
+ rst=>safe_rst,
+ trigger=>trigger,
+
+ SRAM_DATA=>SRAM_DATA,
+ SRAM_ADDR=>SRAM_ADDR_TEST,
+ SRAM_WEN=>SRAM_WEN_TEST,
+ SRAM_OEN=>SRAM_OEN_TEST,
+
+ O_ASYNC_0=>OUTPUT_ASYNC_0,
+ O_ASYNC_1=>OUTPUT_ASYNC_1,
+ O_ASYNC_ACK_IN=>OUTPUT_ASYNC_ACKIN,
+
+ vector_enable=>run_enable,
+ ACK_COUNT_OUT=>count_out
+ );
+ TRANSLATE_AS_TO_S:AS_TO_S_VECTOR
+ generic map(BEGIN_ADDR=>0,END_ADDR=>63,LENGTH=>INPUT_LENGTH)
+ port map(
+ clk=>clk,
+ rst=>safe_rst,
+
+ SRAM_DATA=>SDRAM_DATA,
+ SRAM_ADDR=>SDRAM_ADDR,
+ SRAM_WEN=>SDRAM_WEN,
+ SRAM_OEN=>SDRAM_OEN,
+
+ I_ASYNC_0=>INPUT_ASYNC_0,
+ I_ASYNC_1=>INPUT_ASYNC_1,
+ I_ASYNC_ACK_OUT=>INPUT_ASYNC_ACKOUT,
+
+ vector_enable=>run_enable,
+ ACK_COUNT_OUT=>count_in
+ );
+ p1:process(cmd,SRAM_ADDR_CONFIG,SRAM_WEN_CONFIG,SRAM_OEN_CONFIG,SRAM_ADDR_TEST,SRAM_WEN_TEST,SRAM_OEN_TEST)
+ begin
+-- if(rst='0') then
+-- --state<=IDLE;
+-- msg_out_int<="111";
+-- init_out<='0';
+-- config_mode_out<='0';
+-- config_enable<='0';
+-- I_OL7_JP2_53<='0';
+-- elsif rising_edge(clk) then
+ -- state<=next_state;
+ case cmd is
+ when "00000"=>--IDLE
+ msg_out_int<="111";
+ init_out<='0';
+ config_mode_out<='0';
+ config_enable<='0';
+ run_enable<='0';
+ SRAM_ADDR<=SRAM_ADDR_CONFIG;
+ SRAM_WEN<=SRAM_WEN_CONFIG;
+ SRAM_OEN<=SRAM_OEN_CONFIG;
+ safe_rst<='0';
+
+ when "00001"=>--CONNECTED
+ msg_out_int<="000";
+ init_out<='0';
+ config_mode_out<='0';
+ config_enable<='0';
+ run_enable<='0';
+ SRAM_ADDR<=SRAM_ADDR_CONFIG;
+ SRAM_WEN<=SRAM_WEN_CONFIG;
+ SRAM_OEN<=SRAM_OEN_CONFIG;
+ safe_rst<='0';
+
+ when "00011"=>--INIT
+ msg_out_int<="001";
+ init_out<='0';
+ config_mode_out<='0';
+ config_enable<='0';
+ run_enable<='0';
+ SRAM_ADDR<=SRAM_ADDR_CONFIG;
+ SRAM_WEN<=SRAM_WEN_CONFIG;
+ SRAM_OEN<=SRAM_OEN_CONFIG;
+ safe_rst<='0';
+
+ when "00101"=>--CONFIG
+ msg_out_int<="010";
+ init_out<='1';
+ config_mode_out<='0';
+ config_enable<='1';
+ run_enable<='0';
+ SRAM_ADDR<=SRAM_ADDR_CONFIG;
+ SRAM_WEN<=SRAM_WEN_CONFIG;
+ SRAM_OEN<=SRAM_OEN_CONFIG;
+ safe_rst<='0';
+
+ when "10001"=>--SAFE_RESET,Only I/Os there is no reset for safe!!
+ msg_out_int<="011";
+ init_out<='1';
+ config_mode_out<='1';
+ config_enable<='1';
+ run_enable<='0';
+ SRAM_ADDR<=SRAM_ADDR_TEST;
+ SRAM_WEN<=SRAM_WEN_TEST;
+ SRAM_OEN<=SRAM_OEN_TEST;
+ safe_rst<='0';
+ when "01001"=>--RUNNING
+ msg_out_int<="011";
+ init_out<='1';
+ config_mode_out<='1';
+ config_enable<='1';
+ run_enable<='1';
+ SRAM_ADDR<=SRAM_ADDR_TEST;
+ SRAM_WEN<=SRAM_WEN_TEST;
+ SRAM_OEN<=SRAM_OEN_TEST;
+ safe_rst<='1';
+
+ when others=>
+ msg_out_int<= "111";
+ init_out<='1';
+ config_mode_out<='0';
+ config_enable<='0';
+ run_enable<='0';
+ SRAM_ADDR<=SRAM_ADDR_CONFIG;
+ SRAM_WEN<=SRAM_WEN_CONFIG;
+ SRAM_OEN<=SRAM_OEN_CONFIG;
+ safe_rst<='0';
+ end case;
+-- end if;
+ end process;
+
+-- p2:process(state,init_config,config_mode)
+-- begin
+-- case state is
+--
+-- when IDLE=>
+-- if(init_config='0') then
+-- next_state<=INIT;
+-- else
+-- next_state<=IDLE;
+-- end if;
+---- when CONNECT=>
+----
+---- if(init_config='0') then
+---- next_state<= INIT;
+---- else
+---- next_state<= CONNECT;
+---- end if;
+--
+-- when INIT=>
+-- if(config_mode='1') then
+-- next_state<=CONFIG;
+-- else
+-- next_state<=INIT;
+-- end if;
+--
+-- when CONFIG=>
+-- -- if(init_config='0') then
+-- -- next_state<=INIT;
+-- if(config_mode='0') then
+-- next_state<=RUNNING;
+-- elsif(config_mode='1') then
+-- next_state<=CONFIG;
+-- end if;
+--
+-- when RUNNING=>
+-- --if(init_config='0') then
+-- -- next_state<=INIT;
+-- if(config_mode='1') then
+-- next_state<=CONFIG;
+-- elsif(config_mode='0') then
+-- next_state<=RUNNING;
+-- end if;
+--
+-- when others=>
+-- next_state<=state;
+-- end case;
+-- end process;
+
+-- p3:process(state)
+-- begin
+-- case state is
+-- when IDLE=>
+-- msg_out_int<="111";
+-- init_out<='0';
+-- config_mode_out<='0';
+-- config_enable<='0';
+-- I_OL7_JP2_53<='0';
+--
+-- when CONNECT=>
+-- msg_out_int<="000";
+-- init_out<='0';
+-- config_mode_out<='0';
+-- config_enable<='0';
+-- I_OL7_JP2_53<='0';
+--
+-- when INIT=>
+-- msg_out_int<="001";
+-- init_out<='0';
+-- config_mode_out<='0';
+-- config_enable<='0';
+-- I_OL7_JP2_53<='0';
+--
+-- when CONFIG=>
+-- msg_out_int<="010";
+-- init_out<='1';
+-- config_mode_out<='0';
+-- config_enable<='1';
+-- I_OL7_JP2_53<='0';
+--
+-- when RUNNING=>
+-- msg_out_int<="011";
+-- init_out<='1';
+-- config_mode_out<='1';
+-- config_enable<='0';
+-- I_OL7_JP2_53<='1';
+--
+-- when others=>
+-- msg_out_int<= "111";
+-- init_out<='1';
+-- config_mode_out<='0';
+-- config_enable<='0';
+-- I_OL7_JP2_53<='0';
+-- end case;
+-- end process;
+-- --Main State Machine------------------------------------
+--p_trigger:process(clk,rst)
+-- begin
+-- if(rst='0') then
+-- trig_count<=0;
+-- trigger<='0';
+-- elsif rising_edge(clk) then
+-- trig_count<=trig_count+1;
+-- if(trig_count=1024) then
+-- trigger<='1';
+-- elsif(trig_count=2048) then
+-- trig_count<=0;
+-- trigger<='0';
+-- end if;
+-- end if;
+-- end process;
+--trigger<=clk;
+end architecture machine_a_etat;
Index: trunk/XILINX/BUILD_SCC/SP6/SP6.do_synth
===================================================================
--- trunk/XILINX/BUILD_SCC/SP6/SP6.do_synth (nonexistent)
+++ trunk/XILINX/BUILD_SCC/SP6/SP6.do_synth (revision 17)
@@ -0,0 +1,53 @@
+#!/bin/sh
+
+run_logic_synthesis_only=0;
+while getopts ":s i" options; do
+ case $options in
+ i ) run_logic_synthesis_only=0;;
+ s ) run_logic_synthesis_only=1;;
+ ? ) echo $usage
+ exit 1;;
+ esac
+done
+
+export date_of_run=`date +%Y.%m.%d_%H.%M.%S`
+
+mkdir run_$date_of_run
+rm -f run
+ln -s run_$date_of_run run
+
+mkdir run/synthesis
+
+if [ $run_logic_synthesis_only -eq 1 ] ; then
+ touch run/synthesis/.LOGIC_SYNTHESIS_ONLY
+fi
+
+synplify_premier_dp -batch synplify.tcl
+if [[ $? != 0 ]]; then exit 1; fi
+
+if [ $run_logic_synthesis_only -ne 1 ] ; then
+
+ mkdir run/implementation
+ cd run/implementation
+ ngdbuild -uc ../../SP6.ucf -sd ../../../../coregen/ip_rtl/ -dd _ngo -nt timestamp -p xc6slx45t-fgg484-3 ../synthesis/DE2.edf DE2.ngd
+ if [[ $? != 0 ]]; then exit 1; fi
+ map -u -timing -p xc6slx45t-fgg484-3 -ol high -pr b -detail -o DE2_map.ncd DE2.ngd DE2.pcf
+ if [[ $? != 0 ]]; then exit 1; fi
+ par -ol high -w -nopad DE2_map.ncd DE2.ncd DE2.pcf
+ if [[ $? != 0 ]]; then exit 1; fi
+ trce -v 20 -u 64 -o DE2.twr DE2.ncd DE2.pcf
+ if [[ $? != 0 ]]; then exit 1; fi
+ bitgen -intstyle xflow -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:Yes -g DriveDone:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 DE2.ncd -g INIT_9K:yes
+ #if [[ $? != 0 ]]; then exit 1; fi
+ #setMode -bs
+ #setCable -port auto
+ #Identify -inferir
+ #identifyMPM
+ #assignFile -p 2 -file"/tmp/BUILD_SCC/imp_connect/rtl_package/synth/synplify_fpga/run/implementation/DE2.bit"
+ #Program -p 2
+
+ if [[ $? != 0 ]]; then exit 1; fi
+ cd -
+
+fi
+exit 0
trunk/XILINX/BUILD_SCC/SP6/SP6.do_synth
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC/SP6/RS232_Command.h
===================================================================
--- trunk/XILINX/BUILD_SCC/SP6/RS232_Command.h (nonexistent)
+++ trunk/XILINX/BUILD_SCC/SP6/RS232_Command.h (revision 17)
@@ -0,0 +1,27 @@
+////////////////// Command Action /////////////////////
+parameter SETUP = 8'h61;
+parameter ERASE = 8'h72;
+parameter WRITE = 8'h83;
+parameter READ = 8'h94;
+parameter LCD_DAT = 8'h83;
+parameter LCD_CMD = 8'h94;
+////////////////// Command Target /////////////////////
+parameter LED = 8'hF0;
+parameter SEG7 = 8'hE1;
+parameter PS2 = 8'hD2;
+parameter FLASH = 8'hC3;
+parameter SDRAM = 8'hB4;
+parameter SRAM = 8'hA5;
+parameter LCD = 8'h96;
+parameter VGA = 8'h87;
+parameter SDRSEL = 8'h1F;
+parameter FLSEL = 8'h2E;
+parameter EXTIO = 8'h3D;
+parameter SET_REG = 8'h4C;
+parameter SRSEL = 8'h5B;
+parameter SAFE = 8'h6A;
+////////////////// Command Mode /////////////////////
+parameter OUTSEL = 8'h33;
+parameter NORMAL = 8'hAA;
+parameter DISPLAY = 8'hCC;
+parameter BURST = 8'hFF;
trunk/XILINX/BUILD_SCC/SP6/RS232_Command.h
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC/SP6/DE2.qpf
===================================================================
--- trunk/XILINX/BUILD_SCC/SP6/DE2.qpf (nonexistent)
+++ trunk/XILINX/BUILD_SCC/SP6/DE2.qpf (revision 17)
@@ -0,0 +1,23 @@
+# Copyright (C) 1991-2005 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+
+
+QUARTUS_VERSION = "5.0"
+DATE = "11:08:53 August 22, 2005"
+
+
+# Revisions
+
+PROJECT_REVISION = "DE2"
trunk/XILINX/BUILD_SCC/SP6/DE2.qpf
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC/SP6/DE2_USB_API.pin
===================================================================
--- trunk/XILINX/BUILD_SCC/SP6/DE2_USB_API.pin (nonexistent)
+++ trunk/XILINX/BUILD_SCC/SP6/DE2_USB_API.pin (revision 17)
@@ -0,0 +1,742 @@
+ -- Copyright (C) 1991-2010 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions
+ -- and other software and tools, and its AMPP partner logic
+ -- functions, and any output files from any of the foregoing
+ -- (including device programming or simulation files), and any
+ -- associated documentation or information are expressly subject
+ -- to the terms and conditions of the Altera Program License
+ -- Subscription Agreement, Altera MegaCore Function License
+ -- Agreement, or other applicable license agreement, including,
+ -- without limitation, that your use is for the sole purpose of
+ -- programming logic devices manufactured by Altera and sold by
+ -- Altera or its authorized distributors. Please refer to the
+ -- applicable agreement for further details.
+ --
+ -- This is a Quartus II output file. It is for reporting purposes only, and is
+ -- not intended for use as a Quartus II input file. This file cannot be used
+ -- to make Quartus II pin assignments - for instructions on how to make pin
+ -- assignments, please see Quartus II help.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- NC : No Connect. This pin has no internal connection to the device.
+ -- DNU : Do Not Use. This pin MUST NOT be connected.
+ -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V).
+ -- VCCIO : Dedicated power pin, which MUST be connected to VCC
+ -- of its bank.
+ -- Bank 1: 3.3V
+ -- Bank 2: 3.3V
+ -- Bank 3: 3.3V
+ -- Bank 4: 3.3V
+ -- Bank 5: 3.3V
+ -- Bank 6: 3.3V
+ -- Bank 7: 3.3V
+ -- Bank 8: 3.3V
+ -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
+ -- It can also be used to report unused dedicated pins. The connection
+ -- on the board for unused dedicated pins depends on whether this will
+ -- be used in a future design. One example is device migration. When
+ -- using device migration, refer to the device pin-tables. If it is a
+ -- GND pin in the pin table or if it will not be used in a future design
+ -- for another purpose the it MUST be connected to GND. If it is an unused
+ -- dedicated pin, then it can be connected to a valid signal on the board
+ -- (low, high, or toggling) if that signal is required for a different
+ -- revision of the design.
+ -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
+ -- This pin should be connected to GND. It may also be connected to a
+ -- valid signal on the board (low, high, or toggling) if that signal
+ -- is required for a different revision of the design.
+ -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
+ -- or leave it unconnected.
+ -- RESERVED : Unused I/O pin, which MUST be left unconnected.
+ -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
+ -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
+ -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
+ -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
+ ---------------------------------------------------------------------------------
+
+
+
+ ---------------------------------------------------------------------------------
+ -- Pin directions (input, output or bidir) are based on device operating in user mode.
+ ---------------------------------------------------------------------------------
+
+Quartus II Version 10.0 Build 218 06/27/2010 SJ Full Version
+CHIP "DE2_USB_API" ASSIGNED TO AN: EP2C35F672C6
+
+Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
+-------------------------------------------------------------------------------------------------------------
+GND : A2 : gnd : : : :
+VCCIO3 : A3 : power : : 3.3V : 3 :
+RESERVED_INPUT : A4 : : : : 3 :
+RESERVED_INPUT : A5 : : : : 3 :
+RESERVED_INPUT : A6 : : : : 3 :
+RESERVED_INPUT : A7 : : : : 3 :
+RESERVED_INPUT : A8 : : : : 3 :
+RESERVED_INPUT : A9 : : : : 3 :
+RESERVED_INPUT : A10 : : : : 3 :
+VCCIO3 : A11 : power : : 3.3V : 3 :
+GND : A12 : gnd : : : :
+DPDT_SW[9] : A13 : input : 3.3-V LVTTL : : 4 : Y
+RESERVED_INPUT : A14 : : : : 4 :
+GND : A15 : gnd : : : :
+VCCIO4 : A16 : power : : 3.3V : 4 :
+RESERVED_INPUT : A17 : : : : 4 :
+RESERVED_INPUT : A18 : : : : 4 :
+RESERVED_INPUT : A19 : : : : 4 :
+RESERVED_INPUT : A20 : : : : 4 :
+RESERVED_INPUT : A21 : : : : 4 :
+RESERVED_INPUT : A22 : : : : 4 :
+RESERVED_INPUT : A23 : : : : 4 :
+VCCIO4 : A24 : power : : 3.3V : 4 :
+GND : A25 : gnd : : : :
+RESERVED_INPUT : AA1 : : : : 1 :
+RESERVED_INPUT : AA2 : : : : 1 :
+RESERVED_INPUT : AA3 : : : : 1 :
+RESERVED_INPUT : AA4 : : : : 1 :
+RESERVED_INPUT : AA5 : : : : 1 :
+RESERVED_INPUT : AA6 : : : : 1 :
+RESERVED_INPUT : AA7 : : : : 1 :
+VCCA_PLL1 : AA8 : power : : 1.2V : :
+RESERVED_INPUT : AA9 : : : : 8 :
+RESERVED_INPUT : AA10 : : : : 8 :
+RESERVED_INPUT : AA11 : : : : 8 :
+RESERVED_INPUT : AA12 : : : : 8 :
+LED_RED[10] : AA13 : output : 3.3-V LVTTL : : 7 : Y
+LED_RED[8] : AA14 : output : 3.3-V LVTTL : : 7 : Y
+RESERVED_INPUT : AA15 : : : : 7 :
+RESERVED_INPUT : AA16 : : : : 7 :
+RESERVED_INPUT : AA17 : : : : 7 :
+RESERVED_INPUT : AA18 : : : : 7 :
+VCCA_PLL4 : AA19 : power : : 1.2V : :
+LED_GREEN[6] : AA20 : output : 3.3-V LVTTL : : 7 : Y
+GND_PLL4 : AA21 : gnd : : : :
+VCCIO6 : AA22 : power : : 3.3V : 6 :
+HEX1[5] : AA23 : output : 3.3-V LVTTL : : 6 : Y
+HEX1[4] : AA24 : output : 3.3-V LVTTL : : 6 : Y
+HEX3[1] : AA25 : output : 3.3-V LVTTL : : 6 : Y
+HEX3[2] : AA26 : output : 3.3-V LVTTL : : 6 : Y
+RESERVED_INPUT : AB1 : : : : 1 :
+RESERVED_INPUT : AB2 : : : : 1 :
+RESERVED_INPUT : AB3 : : : : 1 :
+RESERVED_INPUT : AB4 : : : : 1 :
+VCCIO1 : AB5 : power : : 3.3V : 1 :
+VCCIO8 : AB6 : power : : 3.3V : 8 :
+GND : AB7 : gnd : : : :
+RESERVED_INPUT : AB8 : : : : 8 :
+VCCIO8 : AB9 : power : : 3.3V : 8 :
+RESERVED_INPUT : AB10 : : : : 8 :
+GND : AB11 : gnd : : : :
+HEX0[1] : AB12 : output : 3.3-V LVTTL : : 8 : Y
+VCCIO8 : AB13 : power : : 3.3V : 8 :
+VCCIO7 : AB14 : power : : 3.3V : 7 :
+RESERVED_INPUT : AB15 : : : : 7 :
+GND : AB16 : gnd : : : :
+VCCIO7 : AB17 : power : : 3.3V : 7 :
+RESERVED_INPUT : AB18 : : : : 7 :
+GND : AB19 : gnd : : : :
+RESERVED_INPUT : AB20 : : : : 7 :
+LED_RED[2] : AB21 : output : 3.3-V LVTTL : : 7 : Y
+VCCIO7 : AB22 : power : : 3.3V : 7 :
+HEX2[0] : AB23 : output : 3.3-V LVTTL : : 6 : Y
+HEX1[6] : AB24 : output : 3.3-V LVTTL : : 6 : Y
+HEX2[5] : AB25 : output : 3.3-V LVTTL : : 6 : Y
+HEX2[4] : AB26 : output : 3.3-V LVTTL : : 6 : Y
+RESERVED_INPUT : AC1 : : : : 1 :
+RESERVED_INPUT : AC2 : : : : 1 :
+RESERVED_INPUT : AC3 : : : : 1 :
+GND : AC4 : gnd : : : :
+RESERVED_INPUT : AC5 : : : : 8 :
+RESERVED_INPUT : AC6 : : : : 8 :
+RESERVED_INPUT : AC7 : : : : 8 :
+RESERVED_INPUT : AC8 : : : : 8 :
+RESERVED_INPUT : AC9 : : : : 8 :
+RESERVED_INPUT : AC10 : : : : 8 :
+RESERVED_INPUT : AC11 : : : : 8 :
+HEX0[2] : AC12 : output : 3.3-V LVTTL : : 8 : Y
+DPDT_SW[6] : AC13 : input : 3.3-V LVTTL : : 8 : Y
+LED_RED[11] : AC14 : output : 3.3-V LVTTL : : 7 : Y
+RESERVED_INPUT : AC15 : : : : 7 :
+RESERVED_INPUT : AC16 : : : : 7 :
+RESERVED_INPUT : AC17 : : : : 7 :
+RESERVED_INPUT : AC18 : : : : 7 :
+RESERVED_INPUT : AC19 : : : : 7 :
+RESERVED_INPUT : AC20 : : : : 7 :
+LED_RED[7] : AC21 : output : 3.3-V LVTTL : : 7 : Y
+LED_RED[3] : AC22 : output : 3.3-V LVTTL : : 7 : Y
+RESERVED_INPUT : AC23 : : : : 6 :
+NC : AC24 : : : : :
+HEX2[2] : AC25 : output : 3.3-V LVTTL : : 6 : Y
+HEX2[3] : AC26 : output : 3.3-V LVTTL : : 6 : Y
+VCCIO1 : AD1 : power : : 3.3V : 1 :
+RESERVED_INPUT : AD2 : : : : 1 :
+RESERVED_INPUT : AD3 : : : : 1 :
+RESERVED_INPUT : AD4 : : : : 8 :
+RESERVED_INPUT : AD5 : : : : 8 :
+RESERVED_INPUT : AD6 : : : : 8 :
+RESERVED_INPUT : AD7 : : : : 8 :
+RESERVED_INPUT : AD8 : : : : 8 :
+GND : AD9 : gnd : : : :
+RESERVED_INPUT : AD10 : : : : 8 :
+HEX0[3] : AD11 : output : 3.3-V LVTTL : : 8 : Y
+LED_RED[17] : AD12 : output : 3.3-V LVTTL : : 8 : Y
+DPDT_SW[5] : AD13 : input : 3.3-V LVTTL : : 8 : Y
+GND : AD14 : gnd : : : :
+LED_RED[12] : AD15 : output : 3.3-V LVTTL : : 7 : Y
+RESERVED_INPUT : AD16 : : : : 7 :
+RESERVED_INPUT : AD17 : : : : 7 :
+GND : AD18 : gnd : : : :
+RESERVED_INPUT : AD19 : : : : 7 :
+VCCIO7 : AD20 : power : : 3.3V : 7 :
+LED_RED[6] : AD21 : output : 3.3-V LVTTL : : 7 : Y
+LED_RED[4] : AD22 : output : 3.3-V LVTTL : : 7 : Y
+LED_RED[5] : AD23 : output : 3.3-V LVTTL : : 7 : Y
+RESERVED_INPUT : AD24 : : : : 6 :
+RESERVED_INPUT : AD25 : : : : 6 :
+VCCIO6 : AD26 : power : : 3.3V : 6 :
+GND : AE1 : gnd : : : :
+RESERVED_INPUT : AE2 : : : : 1 :
+RESERVED_INPUT : AE3 : : : : 1 :
+RESERVED_INPUT : AE4 : : : : 8 :
+RESERVED_INPUT : AE5 : : : : 8 :
+RESERVED_INPUT : AE6 : : : : 8 :
+RESERVED_INPUT : AE7 : : : : 8 :
+RESERVED_INPUT : AE8 : : : : 8 :
+RESERVED_INPUT : AE9 : : : : 8 :
+RESERVED_INPUT : AE10 : : : : 8 :
+HEX0[4] : AE11 : output : 3.3-V LVTTL : : 8 : Y
+LED_RED[16] : AE12 : output : 3.3-V LVTTL : : 8 : Y
+LED_RED[15] : AE13 : output : 3.3-V LVTTL : : 8 : Y
+DPDT_SW[3] : AE14 : input : 3.3-V LVTTL : : 7 : Y
+LED_RED[13] : AE15 : output : 3.3-V LVTTL : : 7 : Y
+RESERVED_INPUT : AE16 : : : : 7 :
+RESERVED_INPUT : AE17 : : : : 7 :
+RESERVED_INPUT : AE18 : : : : 7 :
+RESERVED_INPUT : AE19 : : : : 7 :
+RESERVED_INPUT : AE20 : : : : 7 :
+RESERVED_INPUT : AE21 : : : : 7 :
+LED_GREEN[0] : AE22 : output : 3.3-V LVTTL : : 7 : Y
+LED_RED[0] : AE23 : output : 3.3-V LVTTL : : 7 : Y
+RESERVED_INPUT : AE24 : : : : 6 :
+RESERVED_INPUT : AE25 : : : : 6 :
+GND : AE26 : gnd : : : :
+GND : AF2 : gnd : : : :
+VCCIO8 : AF3 : power : : 3.3V : 8 :
+RESERVED_INPUT : AF4 : : : : 8 :
+RESERVED_INPUT : AF5 : : : : 8 :
+RESERVED_INPUT : AF6 : : : : 8 :
+RESERVED_INPUT : AF7 : : : : 8 :
+RESERVED_INPUT : AF8 : : : : 8 :
+RESERVED_INPUT : AF9 : : : : 8 :
+HEX0[0] : AF10 : output : 3.3-V LVTTL : : 8 : Y
+VCCIO8 : AF11 : power : : 3.3V : 8 :
+GND : AF12 : gnd : : : :
+LED_RED[14] : AF13 : output : 3.3-V LVTTL : : 8 : Y
+DPDT_SW[4] : AF14 : input : 3.3-V LVTTL : : 7 : Y
+GND : AF15 : gnd : : : :
+VCCIO7 : AF16 : power : : 3.3V : 7 :
+RESERVED_INPUT : AF17 : : : : 7 :
+RESERVED_INPUT : AF18 : : : : 7 :
+RESERVED_INPUT : AF19 : : : : 7 :
+RESERVED_INPUT : AF20 : : : : 7 :
+RESERVED_INPUT : AF21 : : : : 7 :
+LED_GREEN[1] : AF22 : output : 3.3-V LVTTL : : 7 : Y
+LED_RED[1] : AF23 : output : 3.3-V LVTTL : : 7 : Y
+VCCIO7 : AF24 : power : : 3.3V : 7 :
+GND : AF25 : gnd : : : :
+GND : B1 : gnd : : : :
+RESERVED_INPUT : B2 : : : : 2 :
+RESERVED_INPUT : B3 : : : : 2 :
+RESERVED_INPUT : B4 : : : : 3 :
+RESERVED_INPUT : B5 : : : : 3 :
+RESERVED_INPUT : B6 : : : : 3 :
+RESERVED_INPUT : B7 : : : : 3 :
+RESERVED_INPUT : B8 : : : : 3 :
+RESERVED_INPUT : B9 : : : : 3 :
+RESERVED_INPUT : B10 : : : : 3 :
+RESERVED_INPUT : B11 : : : : 3 :
+RESERVED_INPUT : B12 : : : : 3 :
+DPDT_SW[8] : B13 : input : 3.3-V LVTTL : : 4 : Y
+RESERVED_INPUT : B14 : : : : 4 :
+RESERVED_INPUT : B15 : : : : 4 :
+RESERVED_INPUT : B16 : : : : 4 :
+RESERVED_INPUT : B17 : : : : 4 :
+RESERVED_INPUT : B18 : : : : 4 :
+RESERVED_INPUT : B19 : : : : 4 :
+RESERVED_INPUT : B20 : : : : 4 :
+RESERVED_INPUT : B21 : : : : 4 :
+RESERVED_INPUT : B22 : : : : 4 :
+RESERVED_INPUT : B23 : : : : 4 :
+RESERVED_INPUT : B24 : : : : 5 :
+UART_TXD : B25 : output : 3.3-V LVTTL : : 5 : Y
+GND : B26 : gnd : : : :
+VCCIO2 : C1 : power : : 3.3V : 2 :
+RESERVED_INPUT : C2 : : : : 2 :
+RESERVED_INPUT : C3 : : : : 2 :
+RESERVED_INPUT : C4 : : : : 3 :
+RESERVED_INPUT : C5 : : : : 3 :
+RESERVED_INPUT : C6 : : : : 3 :
+RESERVED_INPUT : C7 : : : : 3 :
+RESERVED_INPUT : C8 : : : : 3 :
+RESERVED_INPUT : C9 : : : : 3 :
+RESERVED_INPUT : C10 : : : : 3 :
+RESERVED_INPUT : C11 : : : : 3 :
+RESERVED_INPUT : C12 : : : : 3 :
+DPDT_SW[7] : C13 : input : 3.3-V LVTTL : : 3 : Y
+GND : C14 : gnd : : : :
+RESERVED_INPUT : C15 : : : : 4 :
+RESERVED_INPUT : C16 : : : : 4 :
+RESERVED_INPUT : C17 : : : : 4 :
+GND : C18 : gnd : : : :
+RESERVED_INPUT : C19 : : : : 4 :
+VCCIO4 : C20 : power : : 3.3V : 4 :
+RESERVED_INPUT : C21 : : : : 4 :
+RESERVED_INPUT : C22 : : : : 4 :
+RESERVED_INPUT : C23 : : : : 4 :
+RESERVED_INPUT : C24 : : : : 5 :
+UART_RXD : C25 : input : 3.3-V LVTTL : : 5 : Y
+VCCIO5 : C26 : power : : 3.3V : 5 :
+RESERVED_INPUT : D1 : : : : 2 :
+RESERVED_INPUT : D2 : : : : 2 :
+~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : D3 : input : 3.3-V LVTTL : : 2 : N
+GND : D4 : gnd : : : :
+RESERVED_INPUT : D5 : : : : 3 :
+RESERVED_INPUT : D6 : : : : 3 :
+RESERVED_INPUT : D7 : : : : 3 :
+RESERVED_INPUT : D8 : : : : 3 :
+RESERVED_INPUT : D9 : : : : 3 :
+RESERVED_INPUT : D10 : : : : 3 :
+RESERVED_INPUT : D11 : : : : 3 :
+RESERVED_INPUT : D12 : : : : 3 :
+OSC_27 : D13 : input : 3.3-V LVTTL : : 3 : Y
+RESERVED_INPUT : D14 : : : : 4 :
+RESERVED_INPUT : D15 : : : : 4 :
+RESERVED_INPUT : D16 : : : : 4 :
+RESERVED_INPUT : D17 : : : : 4 :
+RESERVED_INPUT : D18 : : : : 4 :
+RESERVED_INPUT : D19 : : : : 4 :
+RESERVED_INPUT : D20 : : : : 4 :
+RESERVED_INPUT : D21 : : : : 4 :
+VCCIO4 : D22 : power : : 3.3V : 4 :
+RESERVED_INPUT : D23 : : : : 5 :
+GND : D24 : gnd : : : :
+RESERVED_INPUT : D25 : : : : 5 :
+RESERVED_INPUT : D26 : : : : 5 :
+RESERVED_INPUT : E1 : : : : 2 :
+RESERVED_INPUT : E2 : : : : 2 :
+~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : input : 3.3-V LVTTL : : 2 : N
+GND_PLL3 : E4 : gnd : : : :
+RESERVED_INPUT : E5 : : : : 2 :
+VCCIO3 : E6 : power : : 3.3V : 3 :
+GND : E7 : gnd : : : :
+RESERVED_INPUT : E8 : : : : 3 :
+VCCIO3 : E9 : power : : 3.3V : 3 :
+RESERVED_INPUT : E10 : : : : 3 :
+GND : E11 : gnd : : : :
+RESERVED_INPUT : E12 : : : : 3 :
+VCCIO3 : E13 : power : : 3.3V : 3 :
+VCCIO4 : E14 : power : : 3.3V : 4 :
+RESERVED_INPUT : E15 : : : : 4 :
+GND : E16 : gnd : : : :
+VCCIO4 : E17 : power : : 3.3V : 4 :
+RESERVED_INPUT : E18 : : : : 4 :
+GND : E19 : gnd : : : :
+RESERVED_INPUT : E20 : : : : 4 :
+GND_PLL2 : E21 : gnd : : : :
+RESERVED_INPUT : E22 : : : : 5 :
+RESERVED_INPUT : E23 : : : : 5 :
+RESERVED_INPUT : E24 : : : : 5 :
+RESERVED_INPUT : E25 : : : : 5 :
+RESERVED_INPUT : E26 : : : : 5 :
+RESERVED_INPUT : F1 : : : : 2 :
+RESERVED_INPUT : F2 : : : : 2 :
+RESERVED_INPUT : F3 : : : : 2 :
+RESERVED_INPUT : F4 : : : : 2 :
+VCCIO2 : F5 : power : : 3.3V : 2 :
+RESERVED_INPUT : F6 : : : : 2 :
+RESERVED_INPUT : F7 : : : : 2 :
+GNDA_PLL3 : F8 : gnd : : : :
+RESERVED_INPUT : F9 : : : : 3 :
+RESERVED_INPUT : F10 : : : : 3 :
+RESERVED_INPUT : F11 : : : : 3 :
+RESERVED_INPUT : F12 : : : : 3 :
+RESERVED_INPUT : F13 : : : : 4 :
+RESERVED_INPUT : F14 : : : : 4 :
+RESERVED_INPUT : F15 : : : : 4 :
+RESERVED_INPUT : F16 : : : : 4 :
+RESERVED_INPUT : F17 : : : : 4 :
+RESERVED_INPUT : F18 : : : : 4 :
+GNDA_PLL2 : F19 : gnd : : : :
+RESERVED_INPUT : F20 : : : : 5 :
+RESERVED_INPUT : F21 : : : : 5 :
+VCCIO5 : F22 : power : : 3.3V : 5 :
+RESERVED_INPUT : F23 : : : : 5 :
+RESERVED_INPUT : F24 : : : : 5 :
+RESERVED_INPUT : F25 : : : : 5 :
+RESERVED_INPUT : F26 : : : : 5 :
+RESERVED_INPUT : G1 : : : : 2 :
+RESERVED_INPUT : G2 : : : : 2 :
+RESERVED_INPUT : G3 : : : : 2 :
+RESERVED_INPUT : G4 : : : : 2 :
+RESERVED_INPUT : G5 : : : : 2 :
+RESERVED_INPUT : G6 : : : : 2 :
+GND_PLL3 : G7 : gnd : : : :
+VCCA_PLL3 : G8 : power : : 1.2V : :
+RESERVED_INPUT : G9 : : : : 3 :
+RESERVED_INPUT : G10 : : : : 3 :
+RESERVED_INPUT : G11 : : : : 3 :
+RESERVED_INPUT : G12 : : : : 3 :
+RESERVED_INPUT : G13 : : : : 4 :
+RESERVED_INPUT : G14 : : : : 4 :
+RESERVED_INPUT : G15 : : : : 4 :
+RESERVED_INPUT : G16 : : : : 4 :
+RESERVED_INPUT : G17 : : : : 4 :
+RESERVED_INPUT : G18 : : : : 4 :
+VCCA_PLL2 : G19 : power : : 1.2V : :
+GND_PLL2 : G20 : gnd : : : :
+RESERVED_INPUT : G21 : : : : 5 :
+RESERVED_INPUT : G22 : : : : 5 :
+RESERVED_INPUT : G23 : : : : 5 :
+RESERVED_INPUT : G24 : : : : 5 :
+RESERVED_INPUT : G25 : : : : 5 :
+KEY[0] : G26 : input : 3.3-V LVTTL : : 5 : Y
+RESERVED_INPUT : H1 : : : : 2 :
+RESERVED_INPUT : H2 : : : : 2 :
+RESERVED_INPUT : H3 : : : : 2 :
+RESERVED_INPUT : H4 : : : : 2 :
+GND : H5 : gnd : : : :
+RESERVED_INPUT : H6 : : : : 2 :
+VCCD_PLL3 : H7 : power : : 1.2V : :
+RESERVED_INPUT : H8 : : : : 3 :
+VCCIO3 : H9 : power : : 3.3V : 3 :
+RESERVED_INPUT : H10 : : : : 3 :
+RESERVED_INPUT : H11 : : : : 3 :
+RESERVED_INPUT : H12 : : : : 3 :
+GND : H13 : gnd : : : :
+GND : H14 : gnd : : : :
+RESERVED_INPUT : H15 : : : : 4 :
+RESERVED_INPUT : H16 : : : : 4 :
+RESERVED_INPUT : H17 : : : : 4 :
+VCCIO4 : H18 : power : : 3.3V : 4 :
+RESERVED_INPUT : H19 : : : : 5 :
+VCCD_PLL2 : H20 : power : : 1.2V : :
+RESERVED_INPUT : H21 : : : : 5 :
+GND : H22 : gnd : : : :
+RESERVED_INPUT : H23 : : : : 5 :
+RESERVED_INPUT : H24 : : : : 5 :
+RESERVED_INPUT : H25 : : : : 5 :
+RESERVED_INPUT : H26 : : : : 5 :
+RESERVED_INPUT : J1 : : : : 2 :
+RESERVED_INPUT : J2 : : : : 2 :
+RESERVED_INPUT : J3 : : : : 2 :
+RESERVED_INPUT : J4 : : : : 2 :
+RESERVED_INPUT : J5 : : : : 2 :
+RESERVED_INPUT : J6 : : : : 2 :
+RESERVED_INPUT : J7 : : : : 2 :
+RESERVED_INPUT : J8 : : : : 2 :
+RESERVED_INPUT : J9 : : : : 3 :
+RESERVED_INPUT : J10 : : : : 3 :
+RESERVED_INPUT : J11 : : : : 3 :
+VCCIO3 : J12 : power : : 3.3V : 3 :
+RESERVED_INPUT : J13 : : : : 3 :
+RESERVED_INPUT : J14 : : : : 3 :
+VCCIO4 : J15 : power : : 3.3V : 4 :
+RESERVED_INPUT : J16 : : : : 4 :
+RESERVED_INPUT : J17 : : : : 4 :
+RESERVED_INPUT : J18 : : : : 4 :
+VCCIO5 : J19 : power : : 3.3V : 5 :
+RESERVED_INPUT : J20 : : : : 5 :
+RESERVED_INPUT : J21 : : : : 5 :
+RESERVED_INPUT : J22 : : : : 5 :
+RESERVED_INPUT : J23 : : : : 5 :
+RESERVED_INPUT : J24 : : : : 5 :
+RESERVED_INPUT : J25 : : : : 5 :
+RESERVED_INPUT : J26 : : : : 5 :
+RESERVED_INPUT : K1 : : : : 2 :
+RESERVED_INPUT : K2 : : : : 2 :
+RESERVED_INPUT : K3 : : : : 2 :
+RESERVED_INPUT : K4 : : : : 2 :
+RESERVED_INPUT : K5 : : : : 2 :
+RESERVED_INPUT : K6 : : : : 2 :
+RESERVED_INPUT : K7 : : : : 2 :
+RESERVED_INPUT : K8 : : : : 2 :
+RESERVED_INPUT : K9 : : : : 3 :
+VCCINT : K10 : power : : 1.2V : :
+VCCINT : K11 : power : : 1.2V : :
+VCCINT : K12 : power : : 1.2V : :
+VCCINT : K13 : power : : 1.2V : :
+VCCINT : K14 : power : : 1.2V : :
+VCCINT : K15 : power : : 1.2V : :
+RESERVED_INPUT : K16 : : : : 4 :
+RESERVED_INPUT : K17 : : : : 4 :
+RESERVED_INPUT : K18 : : : : 5 :
+RESERVED_INPUT : K19 : : : : 5 :
+GND : K20 : gnd : : : :
+RESERVED_INPUT : K21 : : : : 5 :
+RESERVED_INPUT : K22 : : : : 5 :
+RESERVED_INPUT : K23 : : : : 5 :
+RESERVED_INPUT : K24 : : : : 5 :
+RESERVED_INPUT : K25 : : : : 5 :
+RESERVED_INPUT : K26 : : : : 5 :
+VCCIO2 : L1 : power : : 3.3V : 2 :
+HEX7[1] : L2 : output : 3.3-V LVTTL : : 2 : Y
+HEX7[0] : L3 : output : 3.3-V LVTTL : : 2 : Y
+RESERVED_INPUT : L4 : : : : 2 :
+GND : L5 : gnd : : : :
+HEX7[3] : L6 : output : 3.3-V LVTTL : : 2 : Y
+HEX7[4] : L7 : output : 3.3-V LVTTL : : 2 : Y
+TMS : L8 : input : : : 2 :
+HEX7[2] : L9 : output : 3.3-V LVTTL : : 2 : Y
+RESERVED_INPUT : L10 : : : : 2 :
+VCCINT : L11 : power : : 1.2V : :
+GND : L12 : gnd : : : :
+GND : L13 : gnd : : : :
+GND : L14 : gnd : : : :
+GND : L15 : gnd : : : :
+VCCINT : L16 : power : : 1.2V : :
+VCCINT : L17 : power : : 1.2V : :
+VCCINT : L18 : power : : 1.2V : :
+RESERVED_INPUT : L19 : : : : 5 :
+RESERVED_INPUT : L20 : : : : 5 :
+RESERVED_INPUT : L21 : : : : 5 :
+GND : L22 : gnd : : : :
+RESERVED_INPUT : L23 : : : : 5 :
+RESERVED_INPUT : L24 : : : : 5 :
+RESERVED_INPUT : L25 : : : : 5 :
+VCCIO5 : L26 : power : : 3.3V : 5 :
+GND : M1 : gnd : : : :
+HEX6[3] : M2 : output : 3.3-V LVTTL : : 2 : Y
+HEX6[4] : M3 : output : 3.3-V LVTTL : : 2 : Y
+HEX6[6] : M4 : output : 3.3-V LVTTL : : 2 : Y
+HEX6[5] : M5 : output : 3.3-V LVTTL : : 2 : Y
+TCK : M6 : input : : : 2 :
+TDO : M7 : output : : : 2 :
+TDI : M8 : input : : : 2 :
+VCCIO2 : M9 : power : : 3.3V : 2 :
+VCCINT : M10 : power : : 1.2V : :
+VCCINT : M11 : power : : 1.2V : :
+GND : M12 : gnd : : : :
+GND : M13 : gnd : : : :
+GND : M14 : gnd : : : :
+GND : M15 : gnd : : : :
+VCCINT : M16 : power : : 1.2V : :
+VCCINT : M17 : power : : 1.2V : :
+VCCIO5 : M18 : power : : 3.3V : 5 :
+RESERVED_INPUT : M19 : : : : 5 :
+RESERVED_INPUT : M20 : : : : 5 :
+RESERVED_INPUT : M21 : : : : 5 :
+RESERVED_INPUT : M22 : : : : 5 :
+RESERVED_INPUT : M23 : : : : 5 :
+RESERVED_INPUT : M24 : : : : 5 :
+RESERVED_INPUT : M25 : : : : 5 :
+GND : M26 : gnd : : : :
+DPDT_SW[10] : N1 : input : 3.3-V LVTTL : : 2 : Y
+OSC_50 : N2 : input : 3.3-V LVTTL : : 2 : Y
+DATA0 : N3 : input : : : 2 :
+nCE : N4 : : : : 2 :
+VCCIO2 : N5 : power : : 3.3V : 2 :
+DCLK : N6 : : : : 2 :
+nCONFIG : N7 : : : : 2 :
+GND : N8 : gnd : : : :
+HEX7[6] : N9 : output : 3.3-V LVTTL : : 2 : Y
+VCCINT : N10 : power : : 1.2V : :
+GND : N11 : gnd : : : :
+GND : N12 : gnd : : : :
+GND : N13 : gnd : : : :
+GND : N14 : gnd : : : :
+GND : N15 : gnd : : : :
+GND : N16 : gnd : : : :
+VCCINT : N17 : power : : 1.2V : :
+RESERVED_INPUT : N18 : : : : 5 :
+GND : N19 : gnd : : : :
+RESERVED_INPUT : N20 : : : : 5 :
+NC : N21 : : : : :
+VCCIO5 : N22 : power : : 3.3V : 5 :
+KEY[1] : N23 : input : 3.3-V LVTTL : : 5 : Y
+RESERVED_INPUT : N24 : : : : 5 :
+DPDT_SW[0] : N25 : input : 3.3-V LVTTL : : 5 : Y
+DPDT_SW[1] : N26 : input : 3.3-V LVTTL : : 5 : Y
+DPDT_SW[11] : P1 : input : 3.3-V LVTTL : : 1 : Y
+DPDT_SW[12] : P2 : input : 3.3-V LVTTL : : 1 : Y
+HEX6[2] : P3 : output : 3.3-V LVTTL : : 1 : Y
+HEX6[1] : P4 : output : 3.3-V LVTTL : : 1 : Y
+VCCIO1 : P5 : power : : 3.3V : 1 :
+HEX5[1] : P6 : output : 3.3-V LVTTL : : 1 : Y
+HEX5[2] : P7 : output : 3.3-V LVTTL : : 1 : Y
+GND : P8 : gnd : : : :
+HEX7[5] : P9 : output : 3.3-V LVTTL : : 2 : Y
+VCCINT : P10 : power : : 1.2V : :
+GND : P11 : gnd : : : :
+GND : P12 : gnd : : : :
+GND : P13 : gnd : : : :
+GND : P14 : gnd : : : :
+GND : P15 : gnd : : : :
+GND : P16 : gnd : : : :
+RESERVED_INPUT : P17 : : : : 6 :
+RESERVED_INPUT : P18 : : : : 5 :
+GND : P19 : gnd : : : :
+MSEL0 : P20 : : : : 6 :
+MSEL1 : P21 : : : : 6 :
+VCCIO6 : P22 : power : : 3.3V : 6 :
+KEY[2] : P23 : input : 3.3-V LVTTL : : 6 : Y
+RESERVED_INPUT : P24 : : : : 6 :
+DPDT_SW[2] : P25 : input : 3.3-V LVTTL : : 6 : Y
+EXT_CLOCK : P26 : input : 3.3-V LVTTL : : 6 : Y
+GND : R1 : gnd : : : :
+HEX6[0] : R2 : output : 3.3-V LVTTL : : 1 : Y
+HEX5[6] : R3 : output : 3.3-V LVTTL : : 1 : Y
+HEX5[5] : R4 : output : 3.3-V LVTTL : : 1 : Y
+HEX5[4] : R5 : output : 3.3-V LVTTL : : 1 : Y
+HEX4[5] : R6 : output : 3.3-V LVTTL : : 1 : Y
+HEX4[4] : R7 : output : 3.3-V LVTTL : : 1 : Y
+RESERVED_INPUT : R8 : : : : 1 :
+VCCIO1 : R9 : power : : 3.3V : 1 :
+VCCINT : R10 : power : : 1.2V : :
+VCCINT : R11 : power : : 1.2V : :
+GND : R12 : gnd : : : :
+GND : R13 : gnd : : : :
+GND : R14 : gnd : : : :
+GND : R15 : gnd : : : :
+VCCINT : R16 : power : : 1.2V : :
+RESERVED_INPUT : R17 : : : : 6 :
+VCCIO6 : R18 : power : : 3.3V : 6 :
+RESERVED_INPUT : R19 : : : : 6 :
+RESERVED_INPUT : R20 : : : : 6 :
+GND : R21 : gnd : : : :
+nSTATUS : R22 : : : : 6 :
+CONF_DONE : R23 : : : : 6 :
+RESERVED_INPUT : R24 : : : : 6 :
+RESERVED_INPUT : R25 : : : : 6 :
+GND : R26 : gnd : : : :
+VCCIO1 : T1 : power : : 3.3V : 1 :
+HEX5[0] : T2 : output : 3.3-V LVTTL : : 1 : Y
+HEX4[6] : T3 : output : 3.3-V LVTTL : : 1 : Y
+HEX4[3] : T4 : output : 3.3-V LVTTL : : 1 : Y
+GND : T5 : gnd : : : :
+RESERVED_INPUT : T6 : : : : 1 :
+DPDT_SW[13] : T7 : input : 3.3-V LVTTL : : 1 : Y
+RESERVED_INPUT : T8 : : : : 1 :
+HEX5[3] : T9 : output : 3.3-V LVTTL : : 1 : Y
+RESERVED_INPUT : T10 : : : : 1 :
+VCCINT : T11 : power : : 1.2V : :
+GND : T12 : gnd : : : :
+GND : T13 : gnd : : : :
+GND : T14 : gnd : : : :
+GND : T15 : gnd : : : :
+VCCINT : T16 : power : : 1.2V : :
+RESERVED_INPUT : T17 : : : : 6 :
+RESERVED_INPUT : T18 : : : : 6 :
+RESERVED_INPUT : T19 : : : : 6 :
+RESERVED_INPUT : T20 : : : : 6 :
+RESERVED_INPUT : T21 : : : : 6 :
+RESERVED_INPUT : T22 : : : : 6 :
+RESERVED_INPUT : T23 : : : : 6 :
+RESERVED_INPUT : T24 : : : : 6 :
+RESERVED_INPUT : T25 : : : : 6 :
+VCCIO6 : T26 : power : : 3.3V : 6 :
+HEX4[1] : U1 : output : 3.3-V LVTTL : : 1 : Y
+HEX4[2] : U2 : output : 3.3-V LVTTL : : 1 : Y
+DPDT_SW[14] : U3 : input : 3.3-V LVTTL : : 1 : Y
+DPDT_SW[15] : U4 : input : 3.3-V LVTTL : : 1 : Y
+RESERVED_INPUT : U5 : : : : 1 :
+RESERVED_INPUT : U6 : : : : 1 :
+RESERVED_INPUT : U7 : : : : 1 :
+GND : U8 : gnd : : : :
+HEX4[0] : U9 : output : 3.3-V LVTTL : : 1 : Y
+RESERVED_INPUT : U10 : : : : 1 :
+VCCINT : U11 : power : : 1.2V : :
+RESERVED_INPUT : U12 : : : : 8 :
+VCCINT : U13 : power : : 1.2V : :
+VCCINT : U14 : power : : 1.2V : :
+VCCINT : U15 : power : : 1.2V : :
+VCCINT : U16 : power : : 1.2V : :
+LED_GREEN[5] : U17 : output : 3.3-V LVTTL : : 7 : Y
+LED_GREEN[4] : U18 : output : 3.3-V LVTTL : : 7 : Y
+GND : U19 : gnd : : : :
+RESERVED_INPUT : U20 : : : : 6 :
+RESERVED_INPUT : U21 : : : : 6 :
+HEX3[5] : U22 : output : 3.3-V LVTTL : : 6 : Y
+RESERVED_INPUT : U23 : : : : 6 :
+RESERVED_INPUT : U24 : : : : 6 :
+RESERVED_INPUT : U25 : : : : 6 :
+RESERVED_INPUT : U26 : : : : 6 :
+DPDT_SW[16] : V1 : input : 3.3-V LVTTL : : 1 : Y
+DPDT_SW[17] : V2 : input : 3.3-V LVTTL : : 1 : Y
+RESERVED_INPUT : V3 : : : : 1 :
+RESERVED_INPUT : V4 : : : : 1 :
+RESERVED_INPUT : V5 : : : : 1 :
+RESERVED_INPUT : V6 : : : : 1 :
+RESERVED_INPUT : V7 : : : : 1 :
+VCCIO1 : V8 : power : : 3.3V : 1 :
+RESERVED_INPUT : V9 : : : : 8 :
+RESERVED_INPUT : V10 : : : : 8 :
+RESERVED_INPUT : V11 : : : : 8 :
+VCCIO8 : V12 : power : : 3.3V : 8 :
+HEX0[6] : V13 : output : 3.3-V LVTTL : : 8 : Y
+HEX0[5] : V14 : output : 3.3-V LVTTL : : 8 : Y
+VCCIO7 : V15 : power : : 3.3V : 7 :
+VCCINT : V16 : power : : 1.2V : :
+RESERVED_INPUT : V17 : : : : 7 :
+LED_GREEN[3] : V18 : output : 3.3-V LVTTL : : 7 : Y
+VCCIO6 : V19 : power : : 3.3V : 6 :
+HEX1[0] : V20 : output : 3.3-V LVTTL : : 6 : Y
+HEX1[1] : V21 : output : 3.3-V LVTTL : : 6 : Y
+HEX2[1] : V22 : output : 3.3-V LVTTL : : 6 : Y
+RESERVED_INPUT : V23 : : : : 6 :
+RESERVED_INPUT : V24 : : : : 6 :
+RESERVED_INPUT : V25 : : : : 6 :
+RESERVED_INPUT : V26 : : : : 6 :
+RESERVED_INPUT : W1 : : : : 1 :
+RESERVED_INPUT : W2 : : : : 1 :
+RESERVED_INPUT : W3 : : : : 1 :
+RESERVED_INPUT : W4 : : : : 1 :
+GND : W5 : gnd : : : :
+RESERVED_INPUT : W6 : : : : 1 :
+GND_PLL1 : W7 : gnd : : : :
+RESERVED_INPUT : W8 : : : : 8 :
+VCCIO8 : W9 : power : : 3.3V : 8 :
+RESERVED_INPUT : W10 : : : : 8 :
+RESERVED_INPUT : W11 : : : : 8 :
+RESERVED_INPUT : W12 : : : : 8 :
+GND : W13 : gnd : : : :
+GND : W14 : gnd : : : :
+RESERVED_INPUT : W15 : : : : 7 :
+RESERVED_INPUT : W16 : : : : 7 :
+RESERVED_INPUT : W17 : : : : 7 :
+VCCIO7 : W18 : power : : 3.3V : 7 :
+LED_GREEN[2] : W19 : output : 3.3-V LVTTL : : 7 : Y
+GND_PLL4 : W20 : gnd : : : :
+HEX1[2] : W21 : output : 3.3-V LVTTL : : 6 : Y
+GND : W22 : gnd : : : :
+RESERVED_INPUT : W23 : : : : 6 :
+HEX3[6] : W24 : output : 3.3-V LVTTL : : 6 : Y
+RESERVED_INPUT : W25 : : : : 6 :
+KEY[3] : W26 : input : 3.3-V LVTTL : : 6 : Y
+RESERVED_INPUT : Y1 : : : : 1 :
+NC : Y2 : : : : :
+RESERVED_INPUT : Y3 : : : : 1 :
+RESERVED_INPUT : Y4 : : : : 1 :
+RESERVED_INPUT : Y5 : : : : 1 :
+GND_PLL1 : Y6 : gnd : : : :
+VCCD_PLL1 : Y7 : power : : 1.2V : :
+GNDA_PLL1 : Y8 : gnd : : : :
+GND : Y9 : gnd : : : :
+RESERVED_INPUT : Y10 : : : : 8 :
+RESERVED_INPUT : Y11 : : : : 8 :
+LED_GREEN[8] : Y12 : output : 3.3-V LVTTL : : 8 : Y
+LED_RED[9] : Y13 : output : 3.3-V LVTTL : : 7 : Y
+RESERVED_INPUT : Y14 : : : : 7 :
+RESERVED_INPUT : Y15 : : : : 7 :
+RESERVED_INPUT : Y16 : : : : 7 :
+GND : Y17 : gnd : : : :
+LED_GREEN[7] : Y18 : output : 3.3-V LVTTL : : 7 : Y
+GNDA_PLL4 : Y19 : gnd : : : :
+VCCD_PLL4 : Y20 : power : : 1.2V : :
+RESERVED_INPUT : Y21 : : : : 6 :
+HEX1[3] : Y22 : output : 3.3-V LVTTL : : 6 : Y
+HEX3[0] : Y23 : output : 3.3-V LVTTL : : 6 : Y
+HEX2[6] : Y24 : output : 3.3-V LVTTL : : 6 : Y
+HEX3[4] : Y25 : output : 3.3-V LVTTL : : 6 : Y
+HEX3[3] : Y26 : output : 3.3-V LVTTL : : 6 : Y
Index: trunk/XILINX/BUILD_SCC/SP6/DE2.qsf
===================================================================
--- trunk/XILINX/BUILD_SCC/SP6/DE2.qsf (nonexistent)
+++ trunk/XILINX/BUILD_SCC/SP6/DE2.qsf (revision 17)
@@ -0,0 +1,546 @@
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name LAST_QUARTUS_VERSION 10.0
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_N25 -to DPDT_SW[0]
+set_location_assignment PIN_N26 -to DPDT_SW[1]
+set_location_assignment PIN_P25 -to DPDT_SW[2]
+set_location_assignment PIN_AE14 -to DPDT_SW[3]
+set_location_assignment PIN_AF14 -to DPDT_SW[4]
+set_location_assignment PIN_AD13 -to DPDT_SW[5]
+set_location_assignment PIN_AC13 -to DPDT_SW[6]
+set_location_assignment PIN_C13 -to DPDT_SW[7]
+set_location_assignment PIN_B13 -to DPDT_SW[8]
+set_location_assignment PIN_A13 -to DPDT_SW[9]
+set_location_assignment PIN_N1 -to DPDT_SW[10]
+set_location_assignment PIN_P1 -to DPDT_SW[11]
+set_location_assignment PIN_P2 -to DPDT_SW[12]
+set_location_assignment PIN_T7 -to DPDT_SW[13]
+set_location_assignment PIN_U3 -to DPDT_SW[14]
+set_location_assignment PIN_U4 -to DPDT_SW[15]
+set_location_assignment PIN_V1 -to DPDT_SW[16]
+set_location_assignment PIN_V2 -to DPDT_SW[17]
+set_location_assignment PIN_T6 -to DRAM_ADDR[0]
+set_location_assignment PIN_V4 -to DRAM_ADDR[1]
+set_location_assignment PIN_V3 -to DRAM_ADDR[2]
+set_location_assignment PIN_W2 -to DRAM_ADDR[3]
+set_location_assignment PIN_W1 -to DRAM_ADDR[4]
+set_location_assignment PIN_U6 -to DRAM_ADDR[5]
+set_location_assignment PIN_U7 -to DRAM_ADDR[6]
+set_location_assignment PIN_U5 -to DRAM_ADDR[7]
+set_location_assignment PIN_W4 -to DRAM_ADDR[8]
+set_location_assignment PIN_W3 -to DRAM_ADDR[9]
+set_location_assignment PIN_Y1 -to DRAM_ADDR[10]
+set_location_assignment PIN_V5 -to DRAM_ADDR[11]
+set_location_assignment PIN_AE2 -to DRAM_BA_0
+set_location_assignment PIN_AE3 -to DRAM_BA_1
+set_location_assignment PIN_AB3 -to DRAM_CAS_N
+set_location_assignment PIN_AA6 -to DRAM_CKE
+set_location_assignment PIN_AA7 -to DRAM_CLK
+set_location_assignment PIN_AC3 -to DRAM_CS_N
+set_location_assignment PIN_V6 -to DRAM_DQ[0]
+set_location_assignment PIN_AA2 -to DRAM_DQ[1]
+set_location_assignment PIN_AA1 -to DRAM_DQ[2]
+set_location_assignment PIN_Y3 -to DRAM_DQ[3]
+set_location_assignment PIN_Y4 -to DRAM_DQ[4]
+set_location_assignment PIN_R8 -to DRAM_DQ[5]
+set_location_assignment PIN_T8 -to DRAM_DQ[6]
+set_location_assignment PIN_V7 -to DRAM_DQ[7]
+set_location_assignment PIN_W6 -to DRAM_DQ[8]
+set_location_assignment PIN_AB2 -to DRAM_DQ[9]
+set_location_assignment PIN_AB1 -to DRAM_DQ[10]
+set_location_assignment PIN_AA4 -to DRAM_DQ[11]
+set_location_assignment PIN_AA3 -to DRAM_DQ[12]
+set_location_assignment PIN_AC2 -to DRAM_DQ[13]
+set_location_assignment PIN_AC1 -to DRAM_DQ[14]
+set_location_assignment PIN_AA5 -to DRAM_DQ[15]
+set_location_assignment PIN_AD2 -to DRAM_LDQM
+set_location_assignment PIN_Y5 -to DRAM_UDQM
+set_location_assignment PIN_AB4 -to DRAM_RAS_N
+set_location_assignment PIN_AD3 -to DRAM_WE_N
+set_location_assignment PIN_AC18 -to FL_ADDR[0]
+set_location_assignment PIN_AB18 -to FL_ADDR[1]
+set_location_assignment PIN_AE19 -to FL_ADDR[2]
+set_location_assignment PIN_AF19 -to FL_ADDR[3]
+set_location_assignment PIN_AE18 -to FL_ADDR[4]
+set_location_assignment PIN_AF18 -to FL_ADDR[5]
+set_location_assignment PIN_Y16 -to FL_ADDR[6]
+set_location_assignment PIN_AA16 -to FL_ADDR[7]
+set_location_assignment PIN_AD17 -to FL_ADDR[8]
+set_location_assignment PIN_AC17 -to FL_ADDR[9]
+set_location_assignment PIN_AE17 -to FL_ADDR[10]
+set_location_assignment PIN_AF17 -to FL_ADDR[11]
+set_location_assignment PIN_W16 -to FL_ADDR[12]
+set_location_assignment PIN_W15 -to FL_ADDR[13]
+set_location_assignment PIN_AC16 -to FL_ADDR[14]
+set_location_assignment PIN_AD16 -to FL_ADDR[15]
+set_location_assignment PIN_AE16 -to FL_ADDR[16]
+set_location_assignment PIN_AC15 -to FL_ADDR[17]
+set_location_assignment PIN_AB15 -to FL_ADDR[18]
+set_location_assignment PIN_AA15 -to FL_ADDR[19]
+set_location_assignment PIN_V17 -to FL_CE_N
+set_location_assignment PIN_W17 -to FL_OE_N
+set_location_assignment PIN_AD19 -to FL_DQ[0]
+set_location_assignment PIN_AC19 -to FL_DQ[1]
+set_location_assignment PIN_AF20 -to FL_DQ[2]
+set_location_assignment PIN_AE20 -to FL_DQ[3]
+set_location_assignment PIN_AB20 -to FL_DQ[4]
+set_location_assignment PIN_AC20 -to FL_DQ[5]
+set_location_assignment PIN_AF21 -to FL_DQ[6]
+set_location_assignment PIN_AE21 -to FL_DQ[7]
+set_location_assignment PIN_AA18 -to FL_RST_N
+set_location_assignment PIN_AA17 -to FL_WE_N
+set_location_assignment PIN_AF10 -to HEX0[0]
+set_location_assignment PIN_AB12 -to HEX0[1]
+set_location_assignment PIN_AC12 -to HEX0[2]
+set_location_assignment PIN_AD11 -to HEX0[3]
+set_location_assignment PIN_AE11 -to HEX0[4]
+set_location_assignment PIN_V14 -to HEX0[5]
+set_location_assignment PIN_V13 -to HEX0[6]
+set_location_assignment PIN_V20 -to HEX1[0]
+set_location_assignment PIN_V21 -to HEX1[1]
+set_location_assignment PIN_W21 -to HEX1[2]
+set_location_assignment PIN_Y22 -to HEX1[3]
+set_location_assignment PIN_AA24 -to HEX1[4]
+set_location_assignment PIN_AA23 -to HEX1[5]
+set_location_assignment PIN_AB24 -to HEX1[6]
+set_location_assignment PIN_AB23 -to HEX2[0]
+set_location_assignment PIN_V22 -to HEX2[1]
+set_location_assignment PIN_AC25 -to HEX2[2]
+set_location_assignment PIN_AC26 -to HEX2[3]
+set_location_assignment PIN_AB26 -to HEX2[4]
+set_location_assignment PIN_AB25 -to HEX2[5]
+set_location_assignment PIN_Y24 -to HEX2[6]
+set_location_assignment PIN_Y23 -to HEX3[0]
+set_location_assignment PIN_AA25 -to HEX3[1]
+set_location_assignment PIN_AA26 -to HEX3[2]
+set_location_assignment PIN_Y26 -to HEX3[3]
+set_location_assignment PIN_Y25 -to HEX3[4]
+set_location_assignment PIN_U22 -to HEX3[5]
+set_location_assignment PIN_W24 -to HEX3[6]
+set_location_assignment PIN_U9 -to HEX4[0]
+set_location_assignment PIN_U1 -to HEX4[1]
+set_location_assignment PIN_U2 -to HEX4[2]
+set_location_assignment PIN_T4 -to HEX4[3]
+set_location_assignment PIN_R7 -to HEX4[4]
+set_location_assignment PIN_R6 -to HEX4[5]
+set_location_assignment PIN_T3 -to HEX4[6]
+set_location_assignment PIN_T2 -to HEX5[0]
+set_location_assignment PIN_P6 -to HEX5[1]
+set_location_assignment PIN_P7 -to HEX5[2]
+set_location_assignment PIN_T9 -to HEX5[3]
+set_location_assignment PIN_R5 -to HEX5[4]
+set_location_assignment PIN_R4 -to HEX5[5]
+set_location_assignment PIN_R3 -to HEX5[6]
+set_location_assignment PIN_R2 -to HEX6[0]
+set_location_assignment PIN_P4 -to HEX6[1]
+set_location_assignment PIN_P3 -to HEX6[2]
+set_location_assignment PIN_M2 -to HEX6[3]
+set_location_assignment PIN_M3 -to HEX6[4]
+set_location_assignment PIN_M5 -to HEX6[5]
+set_location_assignment PIN_M4 -to HEX6[6]
+set_location_assignment PIN_L3 -to HEX7[0]
+set_location_assignment PIN_L2 -to HEX7[1]
+set_location_assignment PIN_L9 -to HEX7[2]
+set_location_assignment PIN_L6 -to HEX7[3]
+set_location_assignment PIN_L7 -to HEX7[4]
+set_location_assignment PIN_P9 -to HEX7[5]
+set_location_assignment PIN_N9 -to HEX7[6]
+set_location_assignment PIN_G26 -to KEY[0]
+set_location_assignment PIN_N23 -to KEY[1]
+set_location_assignment PIN_P23 -to KEY[2]
+set_location_assignment PIN_W26 -to KEY[3]
+set_location_assignment PIN_AE23 -to LED_RED[0]
+set_location_assignment PIN_AF23 -to LED_RED[1]
+set_location_assignment PIN_AB21 -to LED_RED[2]
+set_location_assignment PIN_AC22 -to LED_RED[3]
+set_location_assignment PIN_AD22 -to LED_RED[4]
+set_location_assignment PIN_AD23 -to LED_RED[5]
+set_location_assignment PIN_AD21 -to LED_RED[6]
+set_location_assignment PIN_AC21 -to LED_RED[7]
+set_location_assignment PIN_AA14 -to LED_RED[8]
+set_location_assignment PIN_Y13 -to LED_RED[9]
+set_location_assignment PIN_AA13 -to LED_RED[10]
+set_location_assignment PIN_AC14 -to LED_RED[11]
+set_location_assignment PIN_AD15 -to LED_RED[12]
+set_location_assignment PIN_AE15 -to LED_RED[13]
+set_location_assignment PIN_AF13 -to LED_RED[14]
+set_location_assignment PIN_AE13 -to LED_RED[15]
+set_location_assignment PIN_AE12 -to LED_RED[16]
+set_location_assignment PIN_AD12 -to LED_RED[17]
+set_location_assignment PIN_AE22 -to LED_GREEN[0]
+set_location_assignment PIN_AF22 -to LED_GREEN[1]
+set_location_assignment PIN_W19 -to LED_GREEN[2]
+set_location_assignment PIN_V18 -to LED_GREEN[3]
+set_location_assignment PIN_U18 -to LED_GREEN[4]
+set_location_assignment PIN_U17 -to LED_GREEN[5]
+set_location_assignment PIN_AA20 -to LED_GREEN[6]
+set_location_assignment PIN_Y18 -to LED_GREEN[7]
+set_location_assignment PIN_Y12 -to LED_GREEN[8]
+set_location_assignment PIN_D13 -to OSC_27
+set_location_assignment PIN_N2 -to OSC_50
+set_location_assignment PIN_P26 -to EXT_CLOCK
+set_location_assignment PIN_D26 -to PS2_CLK
+set_location_assignment PIN_C24 -to PS2_DAT
+set_location_assignment PIN_C25 -to UART_RXD
+set_location_assignment PIN_B25 -to UART_TXD
+set_location_assignment PIN_K4 -to LCD_RW
+set_location_assignment PIN_K3 -to LCD_EN
+set_location_assignment PIN_K1 -to LCD_RS
+set_location_assignment PIN_J1 -to LCD_DATA[0]
+set_location_assignment PIN_J2 -to LCD_DATA[1]
+set_location_assignment PIN_H1 -to LCD_DATA[2]
+set_location_assignment PIN_H2 -to LCD_DATA[3]
+set_location_assignment PIN_J4 -to LCD_DATA[4]
+set_location_assignment PIN_J3 -to LCD_DATA[5]
+set_location_assignment PIN_H4 -to LCD_DATA[6]
+set_location_assignment PIN_H3 -to LCD_DATA[7]
+set_location_assignment PIN_L4 -to LCD_ON
+set_location_assignment PIN_K2 -to LCD_BLON
+set_location_assignment PIN_AE4 -to SRAM_ADDR[0]
+set_location_assignment PIN_AF4 -to SRAM_ADDR[1]
+set_location_assignment PIN_AC5 -to SRAM_ADDR[2]
+set_location_assignment PIN_AC6 -to SRAM_ADDR[3]
+set_location_assignment PIN_AD4 -to SRAM_ADDR[4]
+set_location_assignment PIN_AD5 -to SRAM_ADDR[5]
+set_location_assignment PIN_AE5 -to SRAM_ADDR[6]
+set_location_assignment PIN_AF5 -to SRAM_ADDR[7]
+set_location_assignment PIN_AD6 -to SRAM_ADDR[8]
+set_location_assignment PIN_AD7 -to SRAM_ADDR[9]
+set_location_assignment PIN_V10 -to SRAM_ADDR[10]
+set_location_assignment PIN_V9 -to SRAM_ADDR[11]
+set_location_assignment PIN_AC7 -to SRAM_ADDR[12]
+set_location_assignment PIN_W8 -to SRAM_ADDR[13]
+set_location_assignment PIN_W10 -to SRAM_ADDR[14]
+set_location_assignment PIN_Y10 -to SRAM_ADDR[15]
+set_location_assignment PIN_AB8 -to SRAM_ADDR[16]
+set_location_assignment PIN_AC8 -to SRAM_ADDR[17]
+set_location_assignment PIN_AD8 -to SRAM_DQ[0]
+set_location_assignment PIN_AE6 -to SRAM_DQ[1]
+set_location_assignment PIN_AF6 -to SRAM_DQ[2]
+set_location_assignment PIN_AA9 -to SRAM_DQ[3]
+set_location_assignment PIN_AA10 -to SRAM_DQ[4]
+set_location_assignment PIN_AB10 -to SRAM_DQ[5]
+set_location_assignment PIN_AA11 -to SRAM_DQ[6]
+set_location_assignment PIN_Y11 -to SRAM_DQ[7]
+set_location_assignment PIN_AE7 -to SRAM_DQ[8]
+set_location_assignment PIN_AF7 -to SRAM_DQ[9]
+set_location_assignment PIN_AE8 -to SRAM_DQ[10]
+set_location_assignment PIN_AF8 -to SRAM_DQ[11]
+set_location_assignment PIN_W11 -to SRAM_DQ[12]
+set_location_assignment PIN_W12 -to SRAM_DQ[13]
+set_location_assignment PIN_AC9 -to SRAM_DQ[14]
+set_location_assignment PIN_AC10 -to SRAM_DQ[15]
+set_location_assignment PIN_AE10 -to SRAM_WE_N
+set_location_assignment PIN_AD10 -to SRAM_OE_N
+set_location_assignment PIN_AF9 -to SRAM_UB_N
+set_location_assignment PIN_AE9 -to SRAM_LB_N
+set_location_assignment PIN_AC11 -to SRAM_CE_N
+set_location_assignment PIN_K7 -to OTG_ADDR[0]
+set_location_assignment PIN_F2 -to OTG_ADDR[1]
+set_location_assignment PIN_F1 -to OTG_CS_N
+set_location_assignment PIN_G2 -to OTG_RD_N
+set_location_assignment PIN_G1 -to OTG_WR_N
+set_location_assignment PIN_G5 -to OTG_RST_N
+set_location_assignment PIN_F4 -to OTG_DATA[0]
+set_location_assignment PIN_D2 -to OTG_DATA[1]
+set_location_assignment PIN_D1 -to OTG_DATA[2]
+set_location_assignment PIN_F7 -to OTG_DATA[3]
+set_location_assignment PIN_J5 -to OTG_DATA[4]
+set_location_assignment PIN_J8 -to OTG_DATA[5]
+set_location_assignment PIN_J7 -to OTG_DATA[6]
+set_location_assignment PIN_H6 -to OTG_DATA[7]
+set_location_assignment PIN_E2 -to OTG_DATA[8]
+set_location_assignment PIN_E1 -to OTG_DATA[9]
+set_location_assignment PIN_K6 -to OTG_DATA[10]
+set_location_assignment PIN_K5 -to OTG_DATA[11]
+set_location_assignment PIN_G4 -to OTG_DATA[12]
+set_location_assignment PIN_G3 -to OTG_DATA[13]
+set_location_assignment PIN_J6 -to OTG_DATA[14]
+set_location_assignment PIN_K8 -to OTG_DATA[15]
+set_location_assignment PIN_B3 -to OTG_INT0
+set_location_assignment PIN_C3 -to OTG_INT1
+set_location_assignment PIN_C2 -to OTG_DACK0_N
+set_location_assignment PIN_B2 -to OTG_DACK1_N
+set_location_assignment PIN_F6 -to OTG_DREQ0
+set_location_assignment PIN_E5 -to OTG_DREQ1
+set_location_assignment PIN_F3 -to OTG_FSPEED
+set_location_assignment PIN_G6 -to OTG_LSPEED
+set_location_assignment PIN_B14 -to TDI
+set_location_assignment PIN_A14 -to TCS
+set_location_assignment PIN_D14 -to TCK
+set_location_assignment PIN_F14 -to TDO
+set_location_assignment PIN_C4 -to TD_RESET
+set_location_assignment PIN_C8 -to VGA_R[0]
+set_location_assignment PIN_F10 -to VGA_R[1]
+set_location_assignment PIN_G10 -to VGA_R[2]
+set_location_assignment PIN_D9 -to VGA_R[3]
+set_location_assignment PIN_C9 -to VGA_R[4]
+set_location_assignment PIN_A8 -to VGA_R[5]
+set_location_assignment PIN_H11 -to VGA_R[6]
+set_location_assignment PIN_H12 -to VGA_R[7]
+set_location_assignment PIN_F11 -to VGA_R[8]
+set_location_assignment PIN_E10 -to VGA_R[9]
+set_location_assignment PIN_B9 -to VGA_G[0]
+set_location_assignment PIN_A9 -to VGA_G[1]
+set_location_assignment PIN_C10 -to VGA_G[2]
+set_location_assignment PIN_D10 -to VGA_G[3]
+set_location_assignment PIN_B10 -to VGA_G[4]
+set_location_assignment PIN_A10 -to VGA_G[5]
+set_location_assignment PIN_G11 -to VGA_G[6]
+set_location_assignment PIN_D11 -to VGA_G[7]
+set_location_assignment PIN_E12 -to VGA_G[8]
+set_location_assignment PIN_D12 -to VGA_G[9]
+set_location_assignment PIN_J13 -to VGA_B[0]
+set_location_assignment PIN_J14 -to VGA_B[1]
+set_location_assignment PIN_F12 -to VGA_B[2]
+set_location_assignment PIN_G12 -to VGA_B[3]
+set_location_assignment PIN_J10 -to VGA_B[4]
+set_location_assignment PIN_J11 -to VGA_B[5]
+set_location_assignment PIN_C11 -to VGA_B[6]
+set_location_assignment PIN_B11 -to VGA_B[7]
+set_location_assignment PIN_C12 -to VGA_B[8]
+set_location_assignment PIN_B12 -to VGA_B[9]
+set_location_assignment PIN_B8 -to VGA_CLK
+set_location_assignment PIN_D6 -to VGA_BLANK
+set_location_assignment PIN_A7 -to VGA_HS
+set_location_assignment PIN_D8 -to VGA_VS
+set_location_assignment PIN_B7 -to VGA_SYNC
+set_location_assignment PIN_A6 -to I2C_SCLK
+set_location_assignment PIN_B6 -to I2C_SDAT
+set_location_assignment PIN_J9 -to TD_DATA[0]
+set_location_assignment PIN_E8 -to TD_DATA[1]
+set_location_assignment PIN_H8 -to TD_DATA[2]
+set_location_assignment PIN_H10 -to TD_DATA[3]
+set_location_assignment PIN_G9 -to TD_DATA[4]
+set_location_assignment PIN_F9 -to TD_DATA[5]
+set_location_assignment PIN_D7 -to TD_DATA[6]
+set_location_assignment PIN_C7 -to TD_DATA[7]
+set_location_assignment PIN_D5 -to TD_HS
+set_location_assignment PIN_K9 -to TD_VS
+set_location_assignment PIN_C5 -to AUD_ADCLRCK
+set_location_assignment PIN_B5 -to AUD_ADCDAT
+set_location_assignment PIN_C6 -to AUD_DACLRCK
+set_location_assignment PIN_A4 -to AUD_DACDAT
+set_location_assignment PIN_A5 -to AUD_XCK
+set_location_assignment PIN_B4 -to AUD_BCLK
+set_location_assignment PIN_D17 -to ENET_DATA[0]
+set_location_assignment PIN_C17 -to ENET_DATA[1]
+set_location_assignment PIN_B18 -to ENET_DATA[2]
+set_location_assignment PIN_A18 -to ENET_DATA[3]
+set_location_assignment PIN_B17 -to ENET_DATA[4]
+set_location_assignment PIN_A17 -to ENET_DATA[5]
+set_location_assignment PIN_B16 -to ENET_DATA[6]
+set_location_assignment PIN_B15 -to ENET_DATA[7]
+set_location_assignment PIN_B20 -to ENET_DATA[8]
+set_location_assignment PIN_A20 -to ENET_DATA[9]
+set_location_assignment PIN_C19 -to ENET_DATA[10]
+set_location_assignment PIN_D19 -to ENET_DATA[11]
+set_location_assignment PIN_B19 -to ENET_DATA[12]
+set_location_assignment PIN_A19 -to ENET_DATA[13]
+set_location_assignment PIN_E18 -to ENET_DATA[14]
+set_location_assignment PIN_D18 -to ENET_DATA[15]
+set_location_assignment PIN_B24 -to ENET_CLK
+set_location_assignment PIN_A21 -to ENET_CMD
+set_location_assignment PIN_A23 -to ENET_CS_N
+set_location_assignment PIN_B21 -to ENET_INT
+set_location_assignment PIN_A22 -to ENET_RD_N
+set_location_assignment PIN_B22 -to ENET_WR_N
+set_location_assignment PIN_B23 -to ENET_RST_N
+set_location_assignment PIN_AE24 -to IRDA_TXD
+set_location_assignment PIN_AE25 -to IRDA_RXD
+set_location_assignment PIN_AD24 -to SD_DAT
+set_location_assignment PIN_AC23 -to SD_DAT3
+set_location_assignment PIN_Y21 -to SD_CMD
+set_location_assignment PIN_AD25 -to SD_CLK
+#set_location_assignment PIN_D25 -to GPIO_0[0]
+#set_location_assignment PIN_J22 -to GPIO_0[1]
+#set_location_assignment PIN_E26 -to GPIO_0[2]
+#set_location_assignment PIN_E25 -to GPIO_0[3]
+#set_location_assignment PIN_F24 -to GPIO_0[4]
+#set_location_assignment PIN_F23 -to GPIO_0[5]
+#set_location_assignment PIN_J21 -to GPIO_0[6]
+set_location_assignment PIN_J21 -to UART_RXD_JP1_7
+#set_location_assignment PIN_J20 -to GPIO_0[7]
+#set_location_assignment PIN_F25 -to GPIO_0[8]
+#set_location_assignment PIN_F26 -to GPIO_0[9]
+set_location_assignment PIN_N18 -to GPIO_0_10
+#set_location_assignment PIN_P18 -to GPIO_0[11]
+#set_location_assignment PIN_G23 -to GPIO_0[12]
+#set_location_assignment PIN_G24 -to GPIO_0[13]
+#set_location_assignment PIN_K22 -to GPIO_0[14]
+#set_location_assignment PIN_G25 -to GPIO_0[15]
+#set_location_assignment PIN_H23 -to GPIO_0[16]
+#set_location_assignment PIN_H24 -to GPIO_0[17]
+#set_location_assignment PIN_J23 -to GPIO_0[18]
+#set_location_assignment PIN_J24 -to GPIO_0[19]
+#set_location_assignment PIN_H25 -to GPIO_0[20]
+set_location_assignment PIN_H25 -to I_OR7_JP1_35_bis
+#set_location_assignment PIN_H26 -to GPIO_0[21]
+#set_location_assignment PIN_H19 -to GPIO_0[22]
+set_location_assignment PIN_H19 -to I_OR8_JP1_36_bis
+#set_location_assignment PIN_K18 -to GPIO_0_[23]
+#set_location_assignment PIN_K19 -to GPIO_0[24]
+set_location_assignment PIN_K19 -to UART_TXD_JP1_27
+#set_location_assignment PIN_K21 -to GPIO_0[25]
+#set_location_assignment PIN_K23 -to GPIO_0[26]
+#set_location_assignment PIN_K24 -to GPIO_0[27]
+#set_location_assignment PIN_L21 -to GPIO_0[28]
+#set_location_assignment PIN_L20 -to GPIO_0[29]
+#set_location_assignment PIN_J25 -to GPIO_0[30]
+set_location_assignment PIN_J25 -to I_OR7_JP1_35
+#set_location_assignment PIN_J26 -to GPIO_0[31]
+set_location_assignment PIN_J26 -to I_OR8_JP1_36
+#set_location_assignment PIN_L23 -to GPIO_0[32]
+set_location_assignment PIN_L23 -to CONFIG_MODE_JP1_37
+#set_location_assignment PIN_L24 -to GPIO_0[33]
+set_location_assignment PIN_L24 -to I_OT2_JP1_38
+#set_location_assignment PIN_L25 -to GPIO_0[34]
+#set_location_assignment PIN_L19 -to GPIO_0[35]
+set_location_assignment PIN_L25 -to INIT_JP1_39
+#set_location_assignment PIN_K25 -to GPIO_1[0]
+set_location_assignment PIN_K25 -to I_OT7_JP2_41
+#set_location_assignment PIN_K26 -to GPIO_1[1]
+set_location_assignment PIN_K26 -to I_OT6_JP2_42
+#set_location_assignment PIN_M22 -to GPIO_1[2]
+set_location_assignment PIN_M22 -to I_OT4_JP2_43
+#set_location_assignment PIN_M23 -to GPIO_1[3]
+set_location_assignment PIN_M23 -to I_OT3_JP2_44
+#set_location_assignment PIN_M19 -to GPIO_1[4]
+set_location_assignment PIN_M19 -to I_OT1_JP2_45
+#set_location_assignment PIN_M20 -to GPIO_1[5]
+set_location_assignment PIN_M20 -to I_OT0_JP2_46
+#set_location_assignment PIN_N20 -to GPIO_1[6]
+set_location_assignment PIN_N20 -to CONFIG_OUT0_JP2_47
+#set_location_assignment PIN_M21 -to GPIO_1[7]
+set_location_assignment PIN_M21 -to I_OL6_JP2_48
+#set_location_assignment PIN_M24 -to GPIO_1[8]
+set_location_assignment PIN_M24 -to CONFIG_OUT1_JP2_49
+#set_location_assignment PIN_M25 -to GPIO_1[9]
+set_location_assignment PIN_M25 -to I_OL3_JP2_50
+#set_location_assignment PIN_N24 -to GPIO_1_10
+set_location_assignment PIN_N24 -to I_OL7_JP2_53
+#set_location_assignment PIN_P24 -to GPIO_1[11]
+set_location_assignment PIN_P24 -to I_OL0_JP2_54
+#set_location_assignment PIN_R25 -to GPIO_1[12]
+set_location_assignment PIN_R25 -to I_OL4_JP2_55
+#set_location_assignment PIN_R24 -to GPIO_1[13]
+set_location_assignment PIN_R24 -to I_OL8_JP2_56
+#set_location_assignment PIN_R20 -to GPIO_1[14]
+set_location_assignment PIN_R20 -to I_OL1_JP2_57
+#set_location_assignment PIN_T22 -to GPIO_1[15]
+set_location_assignment PIN_T22 -to I_OT8_JP2_58
+#set_location_assignment PIN_T23 -to GPIO_1_16
+set_location_assignment PIN_T23 -to I_OL2_JP2_59
+#set_location_assignment PIN_T24 -to GPIO_1[17]
+set_location_assignment PIN_T24 -to I_OB2_JP2_60
+#set_location_assignment PIN_T25 -to GPIO_1[18]
+set_location_assignment PIN_T25 -to I_OL5_JP2_61
+#set_location_assignment PIN_T18 -to GPIO_1[19]
+set_location_assignment PIN_T18 -to I_OB5_JP2_62
+#set_location_assignment PIN_T21 -to GPIO_1[20]
+set_location_assignment PIN_T21 -to I_OT5_JP2_63
+#set_location_assignment PIN_T20 -to GPIO_1[21]
+set_location_assignment PIN_T20 -to I_OR2_JP2_64
+#set_location_assignment PIN_U26 -to GPIO_1[22]
+set_location_assignment PIN_U26 -to I_OB8_JP2_65
+#set_location_assignment PIN_U25 -to GPIO_1[23]
+set_location_assignment PIN_U25 -to CONFIG_ACK_IN_JP2_66
+#set_location_assignment PIN_U23 -to GPIO_1[24]
+set_location_assignment PIN_U23 -to I_OR5_JP2_67
+#set_location_assignment PIN_U24 -to GPIO_1[25]
+set_location_assignment PIN_U24 -to I_OB0_JP2_68
+#set_location_assignment PIN_R19 -to GPIO_1[26]
+set_location_assignment PIN_R19 -to I_OB1_JP2_71
+#set_location_assignment PIN_T19 -to GPIO_1[27]
+set_location_assignment PIN_T19 -to I_OB3_JP2_72
+#set_location_assignment PIN_U20 -to GPIO_1[28]
+set_location_assignment PIN_U20 -to I_OB4_JP2_73
+#set_location_assignment PIN_U21 -to GPIO_1[29]
+set_location_assignment PIN_U21 -to I_OB6_JP2_74
+#set_location_assignment PIN_V26 -to GPIO_1[30]
+set_location_assignment PIN_V26 -to I_OB7_JP2_75
+#set_location_assignment PIN_V25 -to GPIO_1[31]
+set_location_assignment PIN_V25 -to I_OR0_JP2_76
+#set_location_assignment PIN_V24 -to GPIO_1[32]
+set_location_assignment PIN_V24 -to I_OR1_JP2_77
+#set_location_assignment PIN_V23 -to GPIO_1[33]
+set_location_assignment PIN_V23 -to I_OR3_JP2_78
+#set_location_assignment PIN_W25 -to GPIO_1[34]
+set_location_assignment PIN_W25 -to I_OR4_JP2_79
+#set_location_assignment PIN_W23 -to GPIO_1[35]
+set_location_assignment PIN_W23 -to I_OR6_JP2_80
+
+# Timing Assignments
+# ==================
+#set_global_assignment -name REPORT_IO_PATHS_SEPARATELY ON
+#set_global_assignment -name FLOW_ENABLE_TIMING_CONSTRAINT_CHECK ON
+#set_global_assignment -name DO_COMBINED_ANALYSIS OFF
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name FAMILY "Cyclone II"
+set_global_assignment -name TOP_LEVEL_ENTITY DE2
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name DEVICE EP2C35F672C6
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_instance_assignment -name IO_STANDARD LVTTL -to TD_DATA[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to TD_DATA[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to TD_DATA[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to TD_DATA[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to TD_DATA[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to TD_DATA[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to TD_DATA[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to TD_DATA[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to TD_HS
+set_instance_assignment -name IO_STANDARD LVTTL -to TD_VS
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to ENET_DATA[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to SD_DAT3
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD LVTTL
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+
+# Timing Analysis Assignments
+# ===========================
+set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS ON
+set_global_assignment -name ENABLE_CLOCK_LATENCY ON
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
+set_global_assignment -name FMAX_REQUIREMENT "50 MHz" -section_id OSC_50
+set_instance_assignment -name CLOCK_SETTINGS OSC_50 -to OSC_50
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+
+set_global_assignment -name FMAX_REQUIREMENT "50 MHz"
+set_global_assignment -name FLOW_ENABLE_TIMING_CONSTRAINT_CHECK OFF
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+
+set_global_assignment -name VERILOG_FILE CMD_Decode_simple.v
+set_global_assignment -name VHDL_FILE AI.vhd
+set_global_assignment -name SOURCE_FILE RS232_Command.h
+set_global_assignment -name VERILOG_FILE async_receiver_altera.v
+set_global_assignment -name VERILOG_FILE async_transmitter_altera.v
+set_global_assignment -name VERILOG_FILE DE2.v
+set_global_assignment -name VERILOG_FILE LCD_TEST_SAFE.v
+set_global_assignment -name VERILOG_FILE RS232_Controller.v
+set_global_assignment -name VERILOG_FILE SEG7_LUT.v
+set_global_assignment -name VERILOG_FILE SEG7_LUT_8.v
+
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
trunk/XILINX/BUILD_SCC/SP6/DE2.qsf
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC/SP6/LCD_TEST_SAFE.v
===================================================================
--- trunk/XILINX/BUILD_SCC/SP6/LCD_TEST_SAFE.v (nonexistent)
+++ trunk/XILINX/BUILD_SCC/SP6/LCD_TEST_SAFE.v (revision 17)
@@ -0,0 +1,335 @@
+module LCD_TEST ( // Host Side
+ iCLK,iRST_N,msg_in,
+ // LCD Side
+ LCD_DATA,LCD_RW,LCD_EN,LCD_RS );
+// Host Side
+input iCLK,iRST_N;
+input [2:0] msg_in;
+// LCD Side
+output [7:0] LCD_DATA;
+output LCD_RW,LCD_EN,LCD_RS;
+// Internal Wires/Registers
+reg [5:0] LUT_INDEX;
+reg[5:0] LUT_INDEX_NEXT;
+reg [8:0] LUT_DATA;
+reg [5:0] mLCD_ST,mLCD_nxt_ST;
+reg [17:0] mDLY;
+reg [17:0] mDLY_NEXT;
+reg mLCD_Start;
+reg mLCD_Start_NEXT;
+reg [7:0] mLCD_DATA;
+reg mLCD_RS;
+reg [2:0] msg_in_int;
+wire mLCD_Done;
+
+parameter LCD_INTIAL = 0;
+parameter LCD_LINE1 = 5;
+parameter LCD_CH_LINE = LCD_LINE1+16;
+parameter LCD_LINE2 = LCD_LINE1+16+1;
+parameter LUT_SIZE = LCD_LINE1+32+1;
+
+always@(posedge iCLK or negedge iRST_N)
+begin
+ if(!iRST_N)
+ begin
+ mLCD_ST<=4;
+ mLCD_DATA <= 0;
+ mLCD_RS <= 0;
+ msg_in_int <= 0;
+ end
+ else
+ begin
+ mLCD_ST<=mLCD_nxt_ST;
+ LUT_INDEX<=LUT_INDEX_NEXT;
+ mDLY<=mDLY_NEXT;
+ mLCD_Start<=mLCD_Start_NEXT;
+ msg_in_int<=msg_in;
+ mLCD_DATA <= LUT_DATA[7:0];
+ mLCD_RS <= LUT_DATA[8];
+ end
+end
+
+
+//always@(mLCD_ST or msg_in or msg_in_int or LUT_INDEX or LUT_DATA or msg_in_int)
+always@(*)
+ begin
+ case(mLCD_ST)
+ 0: begin
+ mLCD_Start_NEXT <= 1;
+ mDLY_NEXT <= mDLY;
+ if(msg_in_int!=msg_in)
+ begin
+ LUT_INDEX_NEXT<=0;
+ end
+ else begin
+ LUT_INDEX_NEXT<=LUT_INDEX;
+ end
+
+ if( LUT_INDEX"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
+set_global_assignment -name FAMILY "Stratix II"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS On
+set_global_assignment -name PARALLEL_SYNTHESIS -value OFF
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Cyclone III LS"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Cyclone III"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Stratix III"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "HardCopy III"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Arria GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Cyclone II"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "HardCopy II"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Cyclone IV E"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Stratix IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "Arria II GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS -value OFF -family "HardCopy IV"
+set_global_assignment -name REPORT_PARAMETER_SETTINGS On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
+set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy III"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone II"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Cyclone
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy II"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix II"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Stratix
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy IV"
+set_global_assignment -name MAX_LABS "-1 (Unlimited)"
+set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
+set_global_assignment -name SYNTHESIS_SEED 1
+set_global_assignment -name TXPMA_SLEW_RATE Low
+set_global_assignment -name ADCE_ENABLED Auto
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name ENABLE_NCEO_OUTPUT Off
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name CVPCIE_MODE Off
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name INIT_DONE_OPEN_DRAIN On
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Cyclone II"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family Cyclone
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II GX"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "HardCopy II"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Arria GX"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name INTERNAL_SCRUBBING Off
+set_global_assignment -name PR_ERROR_OPEN_DRAIN On
+set_global_assignment -name PR_READY_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CVPCIE_CONFDONE Off
+set_global_assignment -name CVPCIE_CONFDONE_OPEN_DRAIN On
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "HardCopy III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Cyclone II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "HardCopy IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Cyclone III LS"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Stratix III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Arria GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Cyclone
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Stratix
+set_global_assignment -name OPTIMIZE_HOLD_TIMING -value "IO PATHS AND MINIMUM TPD PATHS" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "Force All Tiles with Failing Timing Paths to High Speed"
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone III LS"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Stratix III"
+set_global_assignment -name OPTIMIZE_SSN Off -family "HardCopy III"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_SSN Off -family "HardCopy IV"
+set_global_assignment -name OPTIMIZE_SSN Off -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING -value ON
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS Off
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name STOP_AFTER_CONGESTION_MAP Off
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION -value OFF
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "HardCopy III"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III LS"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Stratix III"
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
+set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
+set_global_assignment -name PR_DONE_OPEN_DRAIN On
+set_global_assignment -name NCEO_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
+set_global_assignment -name ENABLE_PR_PINS Off
+set_global_assignment -name CLAMPING_DIODE Off
+set_global_assignment -name TRI_STATE_SPI_PINS Off
+set_global_assignment -name EDA_SIMULATION_TOOL ""
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL ""
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL ""
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL ""
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL ""
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL ""
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL ""
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL ""
+set_global_assignment -name EDA_RESYNTHESIS_TOOL ""
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000B
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE -value ON -family "Cyclone IV E"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE -value ON -family "Cyclone III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000AE
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Cyclone
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000S
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Cyclone II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE -value ON -family "Cyclone IV GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE -value ON -family "Cyclone III LS"
+set_global_assignment -name USE_CONFIGURATION_DEVICE -value ON -family "Stratix III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Arria GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX3000A
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Stratix
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT Off
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY -value OFF
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION -value OFF
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name INCREMENTAL_COMPILATION FULL_INCREMENTAL_COMPILATION
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name INVERT_BASE_CLOCK Off -section_id ?
+set_global_assignment -name MULTIPLY_BASE_CLOCK_PERIOD_BY 1 -section_id ?
+set_global_assignment -name DIVIDE_BASE_CLOCK_PERIOD_BY 1 -section_id ?
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY Off -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
Index: trunk/XILINX/BUILD_SCC/SP6/async_transmitter_altera.v
===================================================================
--- trunk/XILINX/BUILD_SCC/SP6/async_transmitter_altera.v (nonexistent)
+++ trunk/XILINX/BUILD_SCC/SP6/async_transmitter_altera.v (revision 17)
@@ -0,0 +1,58 @@
+module async_transmitter(clk, TxD_start, TxD_data, TxD, TxD_busy);
+input clk, TxD_start;
+input [7:0] TxD_data;
+output TxD, TxD_busy;
+
+//parameter ClkFrequency = 62500000; // 60MHz
+parameter ClkFrequency = 20000000; // 50MHz
+//parameter ClkFrequency = 27000000; // 27MHz
+parameter Baud = 115200;
+
+// Baud generator
+parameter BaudGeneratorAccWidth = 16;
+parameter BaudGeneratorInc = ((Baud<<(BaudGeneratorAccWidth-4))+(ClkFrequency>>5))/(ClkFrequency>>4);
+reg [BaudGeneratorAccWidth:0] BaudGeneratorAcc;
+wire BaudTick = BaudGeneratorAcc[BaudGeneratorAccWidth];
+wire TxD_busy;
+always @(posedge clk) if(TxD_busy) BaudGeneratorAcc <= BaudGeneratorAcc[BaudGeneratorAccWidth-1:0] + BaudGeneratorInc;
+
+// Transmitter state machine
+reg [3:0] state;
+assign TxD_busy = (state!=0);
+
+always @(posedge clk)
+case(state)
+ 4'b0000: if(TxD_start) state <= 4'b0100;
+ 4'b0100: if(BaudTick) state <= 4'b1000; // start
+ 4'b1000: if(BaudTick) state <= 4'b1001; // bit 0
+ 4'b1001: if(BaudTick) state <= 4'b1010; // bit 1
+ 4'b1010: if(BaudTick) state <= 4'b1011; // bit 2
+ 4'b1011: if(BaudTick) state <= 4'b1100; // bit 3
+ 4'b1100: if(BaudTick) state <= 4'b1101; // bit 4
+ 4'b1101: if(BaudTick) state <= 4'b1110; // bit 5
+ 4'b1110: if(BaudTick) state <= 4'b1111; // bit 6
+ 4'b1111: if(BaudTick) state <= 4'b0001; // bit 7
+ 4'b0001: if(BaudTick) state <= 4'b0010; // stop1
+ 4'b0010: if(BaudTick) state <= 4'b0000; // stop2
+ default: if(BaudTick) state <= 4'b0000;
+endcase
+
+// Output mux
+reg muxbit;
+always @(state[2:0] or TxD_data)
+case(state[2:0])
+ 0: muxbit <= TxD_data[0];
+ 1: muxbit <= TxD_data[1];
+ 2: muxbit <= TxD_data[2];
+ 3: muxbit <= TxD_data[3];
+ 4: muxbit <= TxD_data[4];
+ 5: muxbit <= TxD_data[5];
+ 6: muxbit <= TxD_data[6];
+ 7: muxbit <= TxD_data[7];
+endcase
+
+// Put together the start, data and stop bits
+reg TxD;
+always @(posedge clk) TxD <= (state<4) | (state[3] & muxbit); // register the output to make it glitch free
+
+endmodule
trunk/XILINX/BUILD_SCC/SP6/async_transmitter_altera.v
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC/SP6/SP6.synplify.tcl
===================================================================
--- trunk/XILINX/BUILD_SCC/SP6/SP6.synplify.tcl (nonexistent)
+++ trunk/XILINX/BUILD_SCC/SP6/SP6.synplify.tcl (revision 17)
@@ -0,0 +1,99 @@
+
+set project_name DE2
+set top_level DE2
+set sdc_constraints constraints.sdc
+
+# create a new project
+project -new ${project_name}
+
+# add coregen related files, if present
+if {[file exists coregen.tcl]} {
+ source coregen.tcl
+}
+
+# add verilog files
+# top level design must be last
+
+set mcsfiles [glob -directory ../../macrocells -nocomplain -tails -types f -- {*.v}]
+foreach mcs ${mcsfiles} {
+ if [ regexp -- {assertions} ${mcs} ] {
+ continue
+ }
+ add_file -verilog "../../macrocells/${mcs}"
+}
+
+set rtlfiles [glob -directory ../../rtl -nocomplain -tails -types f -- {*.v}]
+foreach rtl ${rtlfiles} {
+ if [ regexp -- {assertions} ${rtl} ] {
+ continue
+ }
+ add_file -verilog "../../rtl/${rtl}"
+}
+#set_global_assignment -name VERILOG_FILE ../../../../rtl_package/simu_stubs/vsim/bram_based_stream_buffer.v
+set sp6files [glob -directory ../../../../SP6/ -nocomplain -tails -types f -- {*\.vhd}]
+foreach mcs ${sp6files} {
+ if [ regexp -- {assertions} ${mcs} ] {
+ continue
+}
+ add_file -vhdl "../../../../SP6/${mcs}"
+}
+#DE2 files
+set sp6files [glob -directory ../../../../SP6/ -nocomplain -tails -types f -- {*\.v}]
+foreach mcs ${sp6files} {
+ if [ regexp -- {assertions} ${mcs} ] {
+ continue
+}
+ add_file -verilog "../../../../SP6/${mcs}"
+}
+
+# setting options and constraints
+
+set_option -top_module ${top_level}
+add_file "${sdc_constraints}"
+set_option -technology spartan6
+set_option -part xc6slx45t
+set_option -package fgg484
+set_option -speed_grade -3
+
+#compilation/mapping options
+set_option -default_enum_encoding onehot
+set_option -symbolic_fsm_compiler 1
+set_option -resource_sharing 1
+set_option -use_fsm_explorer 0
+
+#map options
+set_option -frequency 20
+set_option -run_prop_extract 1
+
+#Not setting the fanout limit.
+#Synplify to pick up appropriate fanout
+#set_option -fanout_limit 10000
+
+set_option -disable_io_insertion 0
+set_option -pipe 1
+set_option -update_models_cp 0
+set_option -verification_mode 0
+set_option -modular 0
+set_option -retiming 0
+set_option -no_sequential_opt 0
+set_option -fixgatedclocks 0
+
+#simulation options
+set_option -write_verilog 1
+set_option -write_vhdl 0
+#VIF options
+set_option -write_vif 1
+
+#automatic place and route (vendor) options
+set_option -write_apr_constraint 1
+
+project -result_file run/synthesis/${top_level}.edf
+
+#implementation attributes
+set_option -vlog_std v2001
+set_option -synthesis_onoff_pragma 0
+set_option -project_relative_includes 1
+
+# compile the design
+project -run
+project -save
Index: trunk/XILINX/BUILD_SCC/SP6/SP605_BRD_clocks.v
===================================================================
--- trunk/XILINX/BUILD_SCC/SP6/SP605_BRD_clocks.v (nonexistent)
+++ trunk/XILINX/BUILD_SCC/SP6/SP605_BRD_clocks.v (revision 17)
@@ -0,0 +1,217 @@
+`timescale 100 ps / 10 ps
+//-------------------------------------
+// SP601_BRD_CLOCKS.v
+//-------------------------------------
+// History of Changes:
+// 5-5-2009 Initial creation
+// 6-15-2009 Added PLL to generate MCB clocks, also used PLL to generate some others.
+//-------------------------------------
+// This module contains all of the clock related stuff
+//-------------------------------------
+//
+module SP605_BRD_CLOCKS(
+
+// Differential sys clock
+input wire SYSCLK_P,SYSCLK_N,
+
+output wire CLK20, // 20 Mhz
+output wire CLK200, // 200 Mhz
+output wire PROC_CLK, // Processing Clock (200 Mhz?)
+output wire CLK125, // 125 Mhz
+
+// Master Clock for memory controller block
+output wire MCBCLK_2X_0, // CLKOUT0 from PLL @ 667 MHz
+output wire MCBCLK_2X_180, // CLKOUT1 from PLL @ 667 MHz, 180 degree phase
+output wire MCBCLK_PLL_LOCK, CLK_PLL_LOCK,// from PLL
+output wire CALIB_CLK, // GCLK. MIN = 50MHz, MAX = 100MHz.
+
+// 125 Mhz clocks (from PHY RXCLK)
+input wire PHY_RXCLK,
+output wire CLK125_RX, // 125 Mhz
+output wire CLK125_RX_BUFIO,
+input wire RST // system reset - resets PLLs, DCM's
+
+);
+
+parameter [7:0] PROC_CLK_FREQ = 8'd100;
+
+/* System Clock */
+// IBUFG the raw clock input
+wire osc_clk_ibufg;
+IBUFGDS #(
+ .DIFF_TERM("FALSE"), // Differential Termination (Virtex-4/5, Spartan-3E/3A)
+ .IBUF_DELAY_VALUE("0"), // Specify the amount of added input delay for
+ // the buffer, "0"-"16" (Spartan-3E/3A only)
+ .IOSTANDARD("LVDS_25") // Specify the input I/O standard
+) inibufg (
+ .O(osc_clk_ibufg), // Clock buffer output
+ .I(SYSCLK_P), // Diff_p clock buffer input (connect directly to top-level port)
+ .IB(SYSCLK_N) // Diff_n clock buffer input (connect directly to top-level port)
+);
+
+ wire clk20_bufg_in, calib_clk_bufg_in, clk200_bufg_in, proc_clk_bufg_in; // raw PLL outputs
+ BUFG clk20_bufg (.I(clk20_bufg_in), .O(CLK20) );
+ BUFG calib_clk_bufg (.I(calib_clk_bufg_in), .O(CALIB_CLK) );
+ BUFG clk200_bufg (.I(clk200_bufg_in), .O(CLK200) );
+ BUFG proc_clk_bufg (.I(proc_clk_bufg_in), .O(PROC_CLK) );
+
+
+ wire clkfbout_clkfbin; // Clock from PLLFBOUT to PLLFBIN
+ wire clkfbout_clkfbin_125; // Clock from PLLFBOUT to PLLFBIN
+
+ PLL_ADV #
+ (
+ .BANDWIDTH ("OPTIMIZED"),
+ .CLKIN1_PERIOD (5), // 200 MHz = 5ns
+ .CLKIN2_PERIOD (1),
+ .DIVCLK_DIVIDE (3),
+ .CLKFBOUT_MULT (10), // 200 MHz x 10 / 3 = 667 Mhz
+ .CLKFBOUT_PHASE (0.0),
+ .CLKOUT0_DIVIDE (1), // 667 Mhz /1 = 667 Mhz
+ .CLKOUT1_DIVIDE (1), // 667 Mhz /1 = 667 Mhz
+ .CLKOUT2_DIVIDE (),
+ .CLKOUT3_DIVIDE (),
+ .CLKOUT4_DIVIDE (),
+ .CLKOUT5_DIVIDE (),
+ .CLKOUT0_PHASE (0.000),
+ .CLKOUT1_PHASE (180.000),
+ .CLKOUT2_PHASE (0.000),
+ .CLKOUT3_PHASE (0.000),
+ .CLKOUT4_PHASE (0.000),
+ .CLKOUT5_PHASE (0.000),
+ .CLKOUT0_DUTY_CYCLE (0.500),
+ .CLKOUT1_DUTY_CYCLE (0.500),
+ .CLKOUT2_DUTY_CYCLE (0.500),
+ .CLKOUT3_DUTY_CYCLE (0.500),
+ .CLKOUT4_DUTY_CYCLE (0.500),
+ .CLKOUT5_DUTY_CYCLE (0.500),
+ .COMPENSATION ("SYSTEM_SYNCHRONOUS"),
+ .REF_JITTER (0.005000)
+ )
+ u_pll_adv
+ (
+ .CLKFBIN (clkfbout_clkfbin),
+ .CLKINSEL (1'b1),
+ .CLKIN1 (osc_clk_ibufg),
+ .CLKIN2 (1'b0),
+ .DADDR (5'b0),
+ .DCLK (1'b0),
+ .DEN (1'b0),
+ .DI (16'b0),
+ .DWE (1'b0),
+ .REL (1'b0),
+ .RST (RST),
+ .CLKFBDCM (),
+ .CLKFBOUT (clkfbout_clkfbin),
+ .CLKOUTDCM0 (),
+ .CLKOUTDCM1 (),
+ .CLKOUTDCM2 (),
+ .CLKOUTDCM3 (),
+ .CLKOUTDCM4 (),
+ .CLKOUTDCM5 (),
+ .CLKOUT0 (MCBCLK_2X_0),
+ .CLKOUT1 (MCBCLK_2X_180),
+ .CLKOUT2 (),
+ .CLKOUT3 (),
+ .CLKOUT4 (),
+ .CLKOUT5 (),
+ .DO (),
+ .DRDY (),
+ .LOCKED (MCBCLK_PLL_LOCK)
+ );
+
+
+wire xclk125_tx;
+BUFG bufg125_tx(.I(xclk125_tx), .O(CLK125));
+
+
+ PLL_ADV #
+ (
+ .BANDWIDTH ("OPTIMIZED"),
+ .CLKIN1_PERIOD (5), // 200 MHz = 5ns
+ .CLKIN2_PERIOD (1),
+ .DIVCLK_DIVIDE (1),
+ .CLKFBOUT_MULT (5), // 200 * 5 = 1000 MHz
+ .CLKFBOUT_PHASE (0.0),
+ .CLKOUT0_DIVIDE (8), // 125 MHz
+ .CLKOUT1_DIVIDE (5), // 200 MHz
+ .CLKOUT2_DIVIDE (50), // 20 MHz
+ .CLKOUT3_DIVIDE (20), // 50 MHz
+ .CLKOUT4_DIVIDE (32), // 1000 / 32 = 31.25 MHz
+ .CLKOUT5_DIVIDE (),
+ .CLKOUT0_PHASE (0.000),
+ .CLKOUT1_PHASE (180.000),
+ .CLKOUT2_PHASE (0.000),
+ .CLKOUT3_PHASE (0.000),
+ .CLKOUT4_PHASE (0.000),
+ .CLKOUT5_PHASE (0.000),
+ .CLKOUT0_DUTY_CYCLE (0.500),
+ .CLKOUT1_DUTY_CYCLE (0.500),
+ .CLKOUT2_DUTY_CYCLE (0.500),
+ .CLKOUT3_DUTY_CYCLE (0.500),
+ .CLKOUT4_DUTY_CYCLE (0.500),
+ .CLKOUT5_DUTY_CYCLE (0.500),
+ .COMPENSATION ("SYSTEM_SYNCHRONOUS"),
+ .REF_JITTER (0.005000)
+ )
+ u_pll_adv_125
+ (
+ .CLKFBIN (clkfbout_clkfbin_125),
+ .CLKINSEL (1'b1),
+ .CLKIN1 (osc_clk_ibufg),
+ .CLKIN2 (1'b0),
+ .DADDR (5'b0),
+ .DCLK (1'b0),
+ .DEN (1'b0),
+ .DI (16'b0),
+ .DWE (1'b0),
+ .REL (1'b0),
+ .RST (RST),
+ .CLKFBDCM (),
+ .CLKFBOUT (clkfbout_clkfbin_125),
+ .CLKOUTDCM0 (),
+ .CLKOUTDCM1 (),
+ .CLKOUTDCM2 (),
+ .CLKOUTDCM3 (),
+ .CLKOUTDCM4 (),
+ .CLKOUTDCM5 (),
+ .CLKOUT0 (xclk125_tx),
+ .CLKOUT1 (clk200_bufg_in),
+ .CLKOUT2 (clk20_bufg_in),
+ .CLKOUT3 (calib_clk_bufg_in),
+ .CLKOUT4 (proc_clk_bufg_in),
+ .CLKOUT5 (),
+ .DO (),
+ .DRDY (),
+ .LOCKED (CLK_PLL_LOCK)
+ );
+
+
+
+wire phy_rxclk_ibufg;
+//psk replaced IBUFG with BUFIO2
+IBUFG ibufg125rx(.I(PHY_RXCLK), .O(CLK125_RX_int));
+
+
+
+
+//---------------------------------------------------------------------------
+// GMII Receiver Clock Logic
+//---------------------------------------------------------------------------
+
+// Route gmii_rx_clk through a BUFIO2/BUFG and onto global clock routing
+ BUFIO2 bufio_gmii_rx_clk (
+ .DIVCLK (),
+ .I (CLK125_RX_int),
+ .IOCLK (CLK125_RX_BUFIO),
+ .SERDESSTROBE ()
+ );
+
+ // Route rx_clk through a BUFG onto global clock routing
+ BUFG bufg_gmii_rx_clk (
+ .I (CLK125_RX_int),
+ .O (CLK125_RX)
+ );
+
+
+endmodule
Index: trunk/XILINX/BUILD_SCC/SP6/DE2_USB_API.cdf
===================================================================
--- trunk/XILINX/BUILD_SCC/SP6/DE2_USB_API.cdf (nonexistent)
+++ trunk/XILINX/BUILD_SCC/SP6/DE2_USB_API.cdf (revision 17)
@@ -0,0 +1,13 @@
+/* Quartus II Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version */
+JedecChain;
+ FileRevision(JESD32A);
+ DefaultMfr(6E);
+
+ P ActionCode(Cfg)
+ Device PartName(EP2C35F672) Path("D:/My Documents/PhD_Research/MY_PAPERS/FPT2011/Connect6/DE2/HW1/") File("DE2_USB_API.sof") MfrSpec(OpMask(1));
+
+ChainEnd;
+
+AlteraBegin;
+ ChainType(JTAG);
+AlteraEnd;
Index: trunk/XILINX/BUILD_SCC/SP6/LCD_Controller_safe.v
===================================================================
--- trunk/XILINX/BUILD_SCC/SP6/LCD_Controller_safe.v (nonexistent)
+++ trunk/XILINX/BUILD_SCC/SP6/LCD_Controller_safe.v (revision 17)
@@ -0,0 +1,82 @@
+module LCD_Controller ( // Host Side
+ iDATA,iRS,
+ iStart,oDone,
+ iCLK,iRST_N,
+ // LCD Interface
+ LCD_DATA,
+ LCD_RW,
+ LCD_EN,
+ LCD_RS );
+// CLK
+parameter CLK_Divide = 16;
+
+// Host Side
+input [7:0] iDATA;
+input iRS,iStart;
+input iCLK,iRST_N;
+output reg oDone;
+// LCD Interface
+output [7:0] LCD_DATA;
+output reg LCD_EN;
+output LCD_RW;
+output LCD_RS;
+// Internal Register
+reg [4:0] Cont;
+reg [1:0] ST;
+reg preStart,mStart;
+
+/////////////////////////////////////////////
+// Only write to LCD, bypass iRS to LCD_RS
+assign LCD_DATA = iDATA;
+assign LCD_RW = 1'b0;
+assign LCD_RS = iRS;
+/////////////////////////////////////////////
+
+always@(posedge iCLK or negedge iRST_N)
+begin
+ if(!iRST_N)
+ begin
+ oDone <= 1'b0;
+ LCD_EN <= 1'b0;
+ preStart<= 1'b0;
+ mStart <= 1'b0;
+ Cont <= 0;
+ ST <= 0;
+ end
+ else
+ begin
+ ////// Input Start Detect ///////
+ preStart<= iStart;
+ if({preStart,iStart}==2'b01)
+ begin
+ mStart <= 1'b1;
+ oDone <= 1'b0;
+ end
+ //////////////////////////////////
+ if(mStart)
+ begin
+ case(ST)
+ 0: ST <= 1; // Wait Setup
+ 1: begin
+ LCD_EN <= 1'b1;
+ ST <= 2;
+ end
+ 2: begin
+ if(ContiCLK,
+ --reset=>not(iRST_n),
+ reset=>iRST_p,
+ stallbar_out=>open,
+ rawdataout_pico_ret_connect6ai_synth_0_outenable=>open,
+ rawdataout_pico_connect6ai_synth_moveout_out_0_0_outenable=>out_enables(0),
+ rawdataout_pico_connect6ai_synth_moveout_out_1_0_outenable=>out_enables(1),
+ rawdataout_pico_connect6ai_synth_moveout_out_2_0_outenable=>out_enables(2),
+ rawdataout_pico_connect6ai_synth_moveout_out_3_0_outenable=>out_enables(3),
+ rawdataout_pico_connect6ai_synth_moveout_out_4_0_outenable=>out_enables(4),
+ rawdataout_pico_connect6ai_synth_moveout_out_5_0_outenable=>out_enables(5),
+ rawdataout_pico_connect6ai_synth_moveout_out_6_0_outenable=>out_enables(6),
+ rawdataout_pico_connect6ai_synth_moveout_out_7_0_outenable=>out_enables(7),
+ start=>iAI_start,
+ rawdatain_pico_connect6ai_synth_firstmove_in_0_0=>imovecount,
+ rawdatain_pico_connect6ai_synth_movein_0_in_1_0=>iAI_DATA(31 downto 24),
+ rawdatain_pico_connect6ai_synth_movein_1_in_2_0=>iAI_DATA(23 downto 16),
+ rawdatain_pico_connect6ai_synth_movein_2_in_3_0=>iAI_DATA(15 downto 8),
+ rawdatain_pico_connect6ai_synth_movein_3_in_4_0=>iAI_DATA(7 downto 0),
+ rawdatain_pico_connect6ai_synth_movein_4_in_5_0=>iAI_DATA(63 downto 56),
+ rawdatain_pico_connect6ai_synth_movein_5_in_6_0=>iAI_DATA(55 downto 48),
+ rawdatain_pico_connect6ai_synth_movein_6_in_7_0=>iAI_DATA(47 downto 40),
+ rawdatain_pico_connect6ai_synth_movein_7_in_8_0=>iAI_DATA(39 downto 32),
+ rawdatain_pico_connect6ai_synth_colour_in_9_0=>icolor,
+ --rawdatain_pico_connect6ai_synth_moveout_0_in_10_0=> to_stdlogicvector(x"00"),
+ --rawdatain_pico_connect6ai_synth_moveout_1_in_11_0=> to_stdlogicvector(x"00"),
+ --rawdatain_pico_connect6ai_synth_moveout_2_in_12_0=> to_stdlogicvector(x"00"),
+ --rawdatain_pico_connect6ai_synth_moveout_3_in_13_0=> to_stdlogicvector(x"00"),
+ --rawdatain_pico_connect6ai_synth_moveout_4_in_14_0=> to_stdlogicvector(x"00"),
+ --rawdatain_pico_connect6ai_synth_moveout_5_in_15_0=> to_stdlogicvector(x"00"),
+ --rawdatain_pico_connect6ai_synth_moveout_6_in_16_0=> to_stdlogicvector(x"00"),
+ --rawdatain_pico_connect6ai_synth_moveout_7_in_17_0=> to_stdlogicvector(x"00"),
+ rawdatain_pico_connect6ai_synth_moveout_0_in_10_0=> to_stdlogicvector(UNUSED_INPUT_VECTOR),
+ rawdatain_pico_connect6ai_synth_moveout_1_in_11_0=> to_stdlogicvector(UNUSED_INPUT_VECTOR),
+ rawdatain_pico_connect6ai_synth_moveout_2_in_12_0=> to_stdlogicvector(UNUSED_INPUT_VECTOR),
+ rawdatain_pico_connect6ai_synth_moveout_3_in_13_0=> to_stdlogicvector(UNUSED_INPUT_VECTOR),
+ rawdatain_pico_connect6ai_synth_moveout_4_in_14_0=> to_stdlogicvector(UNUSED_INPUT_VECTOR),
+ rawdatain_pico_connect6ai_synth_moveout_5_in_15_0=> to_stdlogicvector(UNUSED_INPUT_VECTOR),
+ rawdatain_pico_connect6ai_synth_moveout_6_in_16_0=> to_stdlogicvector(UNUSED_INPUT_VECTOR),
+ rawdatain_pico_connect6ai_synth_moveout_7_in_17_0=> to_stdlogicvector(UNUSED_INPUT_VECTOR),
+ rawdataout_pico_ret_connect6ai_synth_0=>open,
+ rawdataout_pico_connect6ai_synth_moveout_out_0_0=> mAI_DATA(63 downto 56),
+ rawdataout_pico_connect6ai_synth_moveout_out_1_0=> mAI_DATA(55 downto 48),
+ rawdataout_pico_connect6ai_synth_moveout_out_2_0=> mAI_DATA(47 downto 40),
+ rawdataout_pico_connect6ai_synth_moveout_out_3_0=> mAI_DATA(39 downto 32),
+ rawdataout_pico_connect6ai_synth_moveout_out_4_0=> mAI_DATA(31 downto 24),
+ rawdataout_pico_connect6ai_synth_moveout_out_5_0=> mAI_DATA(23 downto 16),
+ rawdataout_pico_connect6ai_synth_moveout_out_6_0=> mAI_DATA(15 downto 8),
+ rawdataout_pico_connect6ai_synth_moveout_out_7_0=> mAI_DATA(7 downto 0)
+ --instream_queue_di_0=>ils_fifo_queue_dismantle_outdata(47 downto 0),
+ --instream_queue_req_0=>tcab_instream_queue_req_0,
+ --instream_queue_ready_0=>ils_fifo_queue_dismantle_store_req,
+ --outstream_queue_do_1=>tcab_outstream_queue_do_1(47 downto 0),
+ --outstream_queue_req_1=>tcab_outstream_queue_req_1,
+ --outstream_queue_ready_1=>ils_fifo_queue_dismantle_load_req
+ );
+-- ils_fifo_queue_dismantle:bram_based_stream_buffer
+----#(.width(48), .depth(`CONNECT6AI_SYNTH_ILS_FIFO_QUEUE_DISMANTLE_LENGTH))
+-- port map(
+-- clk=>iCLK,
+-- --reset=>not(iRST_n),
+-- reset=>iRST_p,
+-- store_ready=>tcab_instream_queue_req_0,
+-- flush=>'0',
+-- store_req=>ils_fifo_queue_dismantle_store_req,
+-- load_req=>ils_fifo_queue_dismantle_load_req,
+-- load_ready=>tcab_outstream_queue_req_1,
+-- indata=>tcab_outstream_queue_do_1(47 downto 0),
+-- outdata=>ils_fifo_queue_dismantle_outdata(47 downto 0));
+
+process(iCLK)
+begin
+ if rising_edge(iCLK) then
+ if(iAI_start='1') then
+ out_enables_reg<="00000000";
+ for i in 0 to 7 loop
+ AI_DATA( 63-8*i downto 56-8*i)<="00000000";
+ end loop;
+ else
+ for i in 0 to 7 loop
+ if(out_enables(i)='1') then
+ out_enables_reg(i)<=out_enables(i);
+ AI_DATA( 63-8*i downto 56-8*i)<=mAI_DATA(63-8*i downto 56-8*i);
+ else
+ out_enables_reg(i)<=out_enables_reg(i);
+ AI_DATA( 63-8*i downto 56-8*i)<=AI_DATA(63-8*i downto 56-8*i);
+ end if;
+ end loop;
+ end if;
+ end if;
+end process;
+ oAI_Done<= out_enables_reg(0) and out_enables_reg(1) and out_enables_reg(2) and out_enables_reg(3) and
+ out_enables_reg(4) and out_enables_reg(5) and out_enables_reg(6) and out_enables_reg(7);
+
+ --oAI_Done<= out_enables(0) and out_enables(1) and out_enables(2) and out_enables(3);
+end architecture c_to_g;
Index: trunk/XILINX/BUILD_SCC/SP6/setup.sh
===================================================================
--- trunk/XILINX/BUILD_SCC/SP6/setup.sh (nonexistent)
+++ trunk/XILINX/BUILD_SCC/SP6/setup.sh (revision 17)
@@ -0,0 +1,29 @@
+stty -F /dev/ttyS0 115200 cstopb -icanon -icrnl -ixon -opost -onlcr -imaxbel -echo -echoe -echok -echoke -echoctl -echonl min 1 time 0
+## SRSEL
+##echo -n -e '\x00\x00\x5B\x00\x00\x00\x00\xAA' > /dev/ttyS0
+#echo -n -e '\x61\x5B\x12\x34\x56\x00\x00\x33' > /dev/ttyS0
+## SETUP SRAM SRAM SRAM OUTSEL
+#echo -n -e '\x61\xA5\x12\x34\x56\x00\x00\x33' > /dev/ttyS0
+## WRITE SRAM NORMAL
+#echo -n -e '\x83\xA5\x00\x00\x00\x38\x41\xAA' > /dev/ttyS0
+## SETUP SRAM SRAM SRAM OUTSEL
+#echo -n -e '\x61\x4C\x12\x34\x56\xA5\xA5\x33' > /dev/ttyS0
+## SETUP SRAM SRAM SRAM OUTSEL
+#echo -n -e '\x61\xA5\x12\x34\x56\x00\x00\x33' > /dev/ttyS0
+## SRAM
+#echo -n -e '\x94\xA5\x00\x00\x00\x00\x00\xAA' > /dev/ttyS0
+## READ SRAM NORMAL
+#echo -n -e '\x94\xA5\x00\x00\x00\x00\x00\xAA' > /dev/ttyS0
+#
+# SDRSEL
+#echo -n -e '\x61\x1F\x12\x34\x56\x00\x00\x33' > /dev/ttyS0
+## SETUP SDRAM OUTSEL
+#echo -n -e '\x61\xB4\x12\x34\x56\x00\x00\x33' > /dev/ttyS0
+## WRITE SDRAM NORMAL
+#echo -n -e '\x83\xB4\x00\x00\x21\x45\x39\xAA' > /dev/ttyS0
+## SETUP SET_REG SRAM SRAM OUTSEL
+#echo -n -e '\x61\x4C\x12\x34\x56\xB4\xB4\x33' > /dev/ttyS0
+## SETUP SDRAM SDRAM OUTSEL
+#echo -n -e '\x61\xB4\x12\x34\x56\x00\x00\x33' > /dev/ttyS0
+## READ SDRAM
+#echo -n -e '\x94\xB4\x00\x00\x21\x00\x00\xAA' > /dev/ttyS0
trunk/XILINX/BUILD_SCC/SP6/setup.sh
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC/SP6/Makefile
===================================================================
--- trunk/XILINX/BUILD_SCC/SP6/Makefile (nonexistent)
+++ trunk/XILINX/BUILD_SCC/SP6/Makefile (revision 17)
@@ -0,0 +1,18 @@
+all:
+ quartus_map DE2_USB_API.qpf
+ quartus_fit DE2_USB_API.qpf
+ quartus_asm DE2_USB_API.qpf
+ quartus_pgm -c USB-Blaster -m jtag -o "p;DE2_USB_API.sof"
+test:
+ ./setup.sh
+ ../../FPT2011_AI_TERMINAL/connect6 -port /dev/ttyS0 -player D
+
+pgm:
+ quartus_pgm -c USB-Blaster -m jtag -o "p;DE2_USB_API.sof"
+
+sim:
+ vcom S_TO_AS.vhd
+ vcom S_TO_AS_CONFIG.vhd
+ vcom testbench.vhd
+clean:
+ rm -rf db *.msg *.smsg *.summary *.done *.rpt *.pof *.sof transcript incremental_db simulation
Index: trunk/XILINX/BUILD_SCC/SP6/DE2.v
===================================================================
--- trunk/XILINX/BUILD_SCC/SP6/DE2.v (nonexistent)
+++ trunk/XILINX/BUILD_SCC/SP6/DE2.v (revision 17)
@@ -0,0 +1,163 @@
+
+module DE2
+ (
+ //////////////////// Clock Input ////////////////////
+ //OSC_27, // 27 MHz
+ //OSC_50, // 50 MHz
+
+ // Master clock input (muxed from many sources)
+ SYSCLK_P, SYSCLK_N,
+ EXT_CLOCK, // External Clock
+ //////////////////// Push Button ////////////////////
+ KEY, // Button[3:0]
+ //////////////////// DPDT Switch ////////////////////
+ DPDT_SW, // DPDT Switch[17:0]
+ //////////////////// 7-SEG Dispaly ////////////////////
+ HEX0, // Seven Segment Digital 0
+ HEX1, // Seven Segment Digital 1
+ HEX2, // Seven Segment Digital 2
+ HEX3, // Seven Segment Digital 3
+ HEX4, // Seven Segment Digital 4
+ HEX5, // Seven Segment Digital 5
+ HEX6, // Seven Segment Digital 6
+ HEX7, // Seven Segment Digital 7
+ //////////////////////// LED ////////////////////////
+ LED_GREEN, // LED Green[8:0]
+ LED_RED, // LED Red[17:0]
+ //////////////////////// UART ////////////////////////
+ UART_TXD, // UART Transmitter
+ UART_RXD, // UART Rceiver
+ TD_RESET
+
+ );
+
+//////////////////////// Clock Input ////////////////////////
+//input OSC_27; // 27 MHz
+//input OSC_50; // 50 MHz
+input SYSCLK_P, SYSCLK_N;
+input EXT_CLOCK; // External Clock
+//////////////////////// Push Button ////////////////////////
+input [3:0] KEY; // Button[3:0]
+//////////////////////// DPDT Switch ////////////////////////
+input [17:0] DPDT_SW; // DPDT Switch[17:0]
+//////////////////////// 7-SEG Dispaly ////////////////////////
+output [6:0] HEX0; // Seven Segment Digital 0
+output [6:0] HEX1; // Seven Segment Digital 1
+output [6:0] HEX2; // Seven Segment Digital 2
+output [6:0] HEX3; // Seven Segment Digital 3
+output [6:0] HEX4; // Seven Segment Digital 4
+output [6:0] HEX5; // Seven Segment Digital 5
+output [6:0] HEX6; // Seven Segment Digital 6
+output [6:0] HEX7; // Seven Segment Digital 7
+//////////////////////////// LED ////////////////////////////
+output [8:0] LED_GREEN; // LED Green[8:0]
+output [17:0] LED_RED; // LED Red[17:0]
+//////////////////////////// UART ////////////////////////////
+output UART_TXD; // UART Transmitter
+input UART_RXD; // UART Rceiver
+output TD_RESET;
+// USB JTAG
+wire [7:0] mRXD_DATA,mTXD_DATA;
+wire mRXD_Ready,mTXD_Done,mTXD_Start;
+wire mTCK;
+// SEG7
+wire [31:0] mSEG7_DIG;
+// AI
+wire [63:0] DATA_from_AI,DATA_to_AI;
+wire mAI_Start,mAI_Done;
+wire [7:0] mCOLOR;
+
+//------- Clocks -------
+wire clk200, clk20, clk50, proc_clk, clk125; // GCLK's
+wire mcbclk_2x_0, mcbclk_2x_180, mcbclk_pll_lock, calib_clk; // MCB sigs
+wire clk125_rx; // receive clock from PHY
+wire clk125_rx_bufio;
+
+assign clk50=calib_clk;
+
+SP605_BRD_CLOCKS //#(.PROC_CLK_FREQ(proc_clk_freq))
+clocks (
+ .SYSCLK_P(SYSCLK_P), .SYSCLK_N(SYSCLK_N),
+ .CLK20(clk20),
+ .CLK200(clk200),
+ .CLK125(clk125),
+ .PROC_CLK(proc_clk),
+ .MCBCLK_2X_0(mcbclk_2x_0), .MCBCLK_2X_180(mcbclk_2x_180), .MCBCLK_PLL_LOCK(mcbclk_pll_lock), .CALIB_CLK(calib_clk),
+ .PHY_RXCLK(PHY_RXCLK), .CLK125_RX(clk125_rx), .CLK125_RX_BUFIO(clk125_rx_bufio),
+ .RST(KEY[0])
+ );
+wire OSC_27; // 27 MHz
+wire OSC_50; // 50 MHz
+assign OSC_50 =clk20;
+//------- Clocks -------
+assign TD_RESET = 1'b1;
+
+
+
+
+SEG7_LUT_8 u0 ( HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7,mSEG7_DIG );
+
+wire mTXD_Done_not;
+RS232_Controller u1_bis( .iDATA(mTXD_DATA),.iTxD_Start(mTXD_Start),.oTxD_Busy(mTXD_Done_not),
+ .oDATA(mRXD_DATA),.oRxD_Ready(mRXD_Ready),.iCLK(OSC_50),.RST_n(KEY[0]),
+ .oTxD(UART_TXD),.iRxD(UART_RXD));
+//RS232_Controller u1_bis( .iDATA(8'b00101011),.iTxD_Start(1'b1),.oTxD_Busy(mTXD_Done_not),
+// .oDATA(mRXD_DATA),.oRxD_Ready(mRXD_Ready),.iCLK(OSC_50),.RST_n(KEY[0]),
+// .oTxD(UART_TXD),.iRxD(UART_RXD));
+assign mTXD_Done = !mTXD_Done_not;
+assign LED_RED[9] = mTXD_Done_not;
+
+//assign LED_RED[10] = ~mAI_Done;
+assign LED_RED[10]=~UART_RXD;
+assign LED_RED[11]=~UART_TXD;
+assign LED_RED[12]=KEY[0];
+//assign mRXD_DATA=LED_RED[12];
+
+wire rst=!(KEY[0]);
+
+assign UART_RXD_JP1_7 = UART_RXD;
+assign UART_TXD_JP1_50 = UART_TXD;
+
+wire [63:0] CMD_Tmp;
+
+CMD_Decode u5 ( // USB JTAG
+ .iRXD_DATA(mRXD_DATA),.iRXD_Ready(mRXD_Ready),
+ .oTXD_DATA(mTXD_DATA),.oTXD_Start(mTXD_Start),.iTXD_Done(mTXD_Done),
+ // Control
+ .iCLK(OSC_50),.iRST_n(rst), .oAI_RSTn(mAI_RSTn),
+ //AI
+ .oAI_DATA(DATA_to_AI),
+ .iAI_DATA(DATA_from_AI),
+ .oAI_Start(mAI_Start),
+ .iAI_Done(mAI_Done),.oCOLOR(mCOLOR),.d_cmd(CMD_Tmp[16:0]) );
+
+//CMD_Decode u5 ( // USB JTAG
+// .iRXD_DATA(mRXD_DATA),.iRXD_Ready(mRXD_Ready),
+// .oTXD_DATA(mTXD_DATA),.oTXD_Start(mTXD_Start),.iTXD_Done(mTXD_Done),
+// // Control
+// .iCLK(OSC_50),.iRST_n(rst), .oAI_RSTn(mAI_RSTn),
+// //AI
+// .oAI_DATA(DATA_to_AI),
+// .iAI_DATA(DATA_from_AI),
+// .oAI_Start(mAI_Start),
+// .iAI_Done(KEY[1]),.oCOLOR(mCOLOR),.d_cmd(CMD_Tmp[16:0]) );
+AI inst_AI (
+ .oAI_DATA(DATA_from_AI),
+ .iAI_DATA(DATA_to_AI),
+ .iCOLOR(mCOLOR),
+ .imovecount(CMD_Tmp[16:0]),
+ .iAI_Start(mAI_Start),
+ .oAI_Done(mAI_Done),
+
+ // Control
+ .iCLK(OSC_50),.iRST_n(mAI_RSTn) );
+
+//assign mSEG7_DIG = { CMD_Tmp[31:28],CMD_Tmp[27:24],CMD_Tmp[23:20],CMD_Tmp[19:16],
+// CMD_Tmp[15:12],CMD_Tmp[11:8],CMD_Tmp[7:4],CMD_Tmp[3:0] };
+assign mSEG7_DIG = {
+// DATA_to_AI[63:60],DATA_to_AI[59:56],DATA_to_AI[55:52],DATA_to_AI[51:48],
+// DATA_to_AI[47:44],DATA_to_AI[43:40],DATA_to_AI[39:36],DATA_to_AI[35:32] }
+ DATA_from_AI[31:28],DATA_from_AI[27:24],DATA_from_AI[23:20],DATA_from_AI[19:16],
+ DATA_from_AI[15:12],DATA_from_AI[11:8],DATA_from_AI[7:4],DATA_from_AI[3:0] }
+ ;
+endmodule
Index: trunk/XILINX/BUILD_SCC/synth_src/q.cpp
===================================================================
--- trunk/XILINX/BUILD_SCC/synth_src/q.cpp (nonexistent)
+++ trunk/XILINX/BUILD_SCC/synth_src/q.cpp (revision 17)
@@ -0,0 +1,206 @@
+
+//#ifdef PICO_SYNTH
+//#define Q_ASSERT(_cond, _msg)
+////#include
+//#include "pico.h"
+//#include "q.hpp"
+//#include "./shared.h"
+//using namespace std;
+//#else
+///* not synthesizable */
+//#include
+//#include
+//#include
+//#include
+//
+//static void debug_assert (bool cond, char * msg) {
+// if (!cond) {
+// printf("assert failed: %s\n", msg);
+// assert(0);
+// }
+//}
+//
+//#define Q_ASSERT(_cond, _msg) debug_assert(_cond, _msg)
+//#endif
+//#define max_size 361
+//#define ptr_bw 32
+//FIFO(queue,AIMove);
+//#pragma no_inter_loop_stream_analysis pico_stream_input_queue
+//#pragma no_inter_loop_stream_analysis pico_stream_output_queue
+//#pragma no_inter_task_stream_analysis pico_stream_input_queue
+//#pragma no_inter_task_stream_analysis pico_stream_output_queue
+//
+//#pragma fifo_length queue 361
+////template
+//
+// /* pop front of queue, returning the front data */
+// /* q is corrupted if pop when empty */
+// AIMove q::pop (){
+// /* assert that before pop, queue is not empty (underflow check) */
+// Q_ASSERT((!wrapped && (head < tail)) || (wrapped && (head >= tail)),
+// "queue underflowed");
+// AIMove d = pico_stream_input_queue();
+// //cout <<"pop: "<= tail)),
+// "Queue overflowed") ;
+// //cout <<"push: "<
+//#include "pico.h"
+//using namespace std;
+//#else
+///* not synthesizable */
+//#include
+//#include
+//#include
+//#include
+//
+//static void debug_assert (bool cond, char * msg) {
+// if (!cond) {
+// printf("assert failed: %s\n", msg);
+// assert(0);
+// }
+//}
+//
+//#define Q_ASSERT(_cond, _msg) debug_assert(_cond, _msg)
+//#endif
+//FIFO(queue,AIMove);
+//
+// /* pop front of queue, returning the front data */
+// /* q is corrupted if pop when empty */
+// template
+// tp q::pop () {
+// /* assert that before pop, queue is not empty (underflow check) */
+// Q_ASSERT((!wrapped && (head < tail)) || (wrapped && (head >= tail)),
+// "queue underflowed");
+// tp d = pico_stream_input_queue();
+// cout <<"pop: "<
+// void q::push (tp d) {
+// pico_stream_output_queue(d);
+// if (tail == max_size-1) {
+// tail = 0;
+// wrapped = true;
+// } else {
+// tail = tail + 1;
+// }
+// /* assert that after push, queue is not empty (overflow check) */
+// Q_ASSERT((!wrapped && (head < tail)) || (wrapped && (head >= tail)),
+// "Queue overflowed") ;
+// cout <<"push: "<
+// int q::size () {
+// if (wrapped) {
+// return (max_size - head) + (tail - 0);
+// } else {
+// return tail - head;
+// }
+// }
+//
+//#ifndef PICO_SYNTH
+// /* not synthesizable */
+// std::string to_string () const {
+// std::string s;
+// std::stringstream out;
+//
+// out << "{ ";
+//
+// if (wrapped) {
+// for (int i=head; i
+//std::ostream& operator << (std::ostream &os, const q &f)
+//{
+// os << f.to_string();
+// return os;
+//}
+//#endif
+//q moves_fifo;
+//#pragma internal_blockram moves_fifo
+//#pragma no_inter_loop_memory_analysis moves_fifo.head
+//#pragma no_inter_loop_memory_analysis moves_fifo.tail
+//#pragma no_inter_loop_memory_analysis moves_fifo.wrapped
+//#pragma no_inter_loop_memory_analysis moves_fifo.active
+//#pragma no_inter_loop_memory_analysis moves_fifo
+//q moves_fifo1;
+//#pragma internal_blockram moves_fifo1
+//#pragma no_inter_loop_memory_analysis moves_fifo1.head
+//#pragma no_inter_loop_memory_analysis moves_fifo1.tail
+//#pragma no_inter_loop_memory_analysis moves_fifo1.wrapped
+//#pragma no_inter_loop_memory_analysis moves_fifo1.active
+//#pragma no_inter_loop_memory_analysis moves_fifo1
Index: trunk/XILINX/BUILD_SCC/synth_src/connect6_synth.c
===================================================================
--- trunk/XILINX/BUILD_SCC/synth_src/connect6_synth.c (nonexistent)
+++ trunk/XILINX/BUILD_SCC/synth_src/connect6_synth.c (revision 17)
@@ -0,0 +1,145 @@
+/*
+ connect6.cpp
+ June 9, 2011
+ This file contains the game AI
+ By Kevin Nam
+
+ */
+
+//#include
+//#include
+//
+//#include "util.h"
+//#include "connect6.h"
+#include "./shared.h"
+
+// Subtract this many points for moves at the edges.
+#define EDGEPENALTY 5
+
+
+/* The cost function simply counts all of the consecutive stones of same colour in
+ every direction from the spot for which the points is being calculated.
+
+Ex:
+
+.DDLL
+.DLDD
+DXDDD
+...D.
+
+Above, X is the spot being calculated.
+The points would be 2 (above) + 2(topright) + 3(right) + 1 (left) = 8.
+It treats opponent's stones and own stones with equal weighting.
+
+Return 0 if the spot y,x is already taken, else return the calculated value
+
+ */
+void move_to_ascii(int x,int y, char *move){
+ if (y >= 10){
+ move[0] = '1';
+ y -= 10;
+ } else {
+ move[0] = '0';
+ }
+ if (y == 0) move[1] = '0';
+ else if (y == 1) move[1] = '1';
+ else if (y == 2) move[1] = '2';
+ else if (y == 3) move[1] = '3';
+ else if (y == 4) move[1] = '4';
+ else if (y == 5) move[1] = '5';
+ else if (y == 6) move[1] = '6';
+ else if (y == 7) move[1] = '7';
+ else if (y == 8) move[1] = '8';
+ else if (y == 9) move[1] = '9';
+
+ // Do same for x.
+ if (x >= 10){
+ move[2] = '1';
+ x -= 10;
+ } else {
+ move[2] = '0';
+ }
+ if (x == 0) move[3] = '0';
+ else if (x == 1) move[3] = '1';
+ else if (x == 2) move[3] = '2';
+ else if (x == 3) move[3] = '3';
+ else if (x == 4) move[3] = '4';
+ else if (x == 5) move[3] = '5';
+ else if (x == 6) move[3] = '6';
+ else if (x == 7) move[3] = '7';
+ else if (x == 8) move[3] = '8';
+ else if (x == 9) move[3] = '9';
+
+}
+
+static int char_to_int(short x){
+ if(x>=48)
+ return x-48;
+ else
+ return 0;
+}
+
+
+/*
+ The AI Function that calls the cost function for every spot on the board.
+ It returns the location with the highest points. In the event of a tie, randomly decide.
+ Input the board and the colour being played.
+ Puts the move (in ASCII chars) inside move[4]. This is from [1 ... 19]
+ Puts the move (in integers) in moveY and moveX. This is from [0 ... 18]
+ */
+int connect6ai_synth(int firstmove,char movein[8], char colour, char moveout[8]){
+ #pragma bitsize firstmove 17
+ short x,y,highx = 0;
+ Board *myboard ;
+ AIMoves *moves;
+ //-------------------------------------------------------------------------
+ if((firstmove >= 1)){
+ //update the board
+ y = char_to_int(movein[0])*10 + char_to_int(movein[1]) - 1;
+ x = char_to_int(movein[2])*10 + char_to_int(movein[3]) - 1;
+ if(colour==68){//'D')
+ //myboard[y][x] = (char)2;//76;//'L';
+ place_piece_type(myboard,x,y,PIECE_WHITE);
+ myboard->turn=PIECE_BLACK;
+ }else{
+ //myboard[y][x] = (char)1;//68;//'D';
+ place_piece_type(myboard,x,y,PIECE_BLACK);
+ myboard->turn=PIECE_WHITE;
+ }
+ }
+ if((firstmove >=3)){
+ //update the board
+ y = char_to_int(movein[4])*10 + char_to_int(movein[5]) - 1;
+ x = char_to_int(movein[6])*10 + char_to_int(movein[7]) - 1;
+ if(colour==68){//'D')
+ //myboard[y][x] = (char)2;//76;//'L';
+ place_piece_type(myboard,x,y,PIECE_WHITE);
+ myboard->turn=PIECE_BLACK;
+ }else{
+ //myboard[y][x] = (char)1;//68;//'D';
+ place_piece_type(myboard,x,y,PIECE_BLACK);
+ myboard->turn=PIECE_WHITE;
+ }
+ }
+ moves=ai_threats(myboard);
+ // Modify the myboard based on current move.
+ place_piece_type(myboard,moves->data[1].x,moves->data[1].y,myboard->turn);
+ /// Convert the int coordinates to corresponding ASCII chars
+
+ move_to_ascii(moves->data[1].x+1,moves->data[1].y+1,moveout);
+
+
+ //-------------------------------------------------------------------------
+ if(firstmove>=1){
+ moves=ai_threats(myboard);
+ // Modify the myboard based on current move.
+ place_piece_type(myboard,moves->data[1].x,moves->data[1].y,myboard->turn);
+
+ /// Convert the int coordinates to corresponding ASCII chars
+ move_to_ascii(moves->data[1].x+1,moves->data[1].y+1,&moveout[4]);
+ }
+ return 0;
+}
+
+
+
Index: trunk/XILINX/BUILD_SCC/synth_src/connect6_synth.cpp
===================================================================
--- trunk/XILINX/BUILD_SCC/synth_src/connect6_synth.cpp (nonexistent)
+++ trunk/XILINX/BUILD_SCC/synth_src/connect6_synth.cpp (revision 17)
@@ -0,0 +1,252 @@
+/*
+ connect6.cpp
+ June 9, 2011
+ This file contains the game AI
+ By Kevin Nam
+
+ */
+
+//#include
+//#include
+//
+//#include "util.h"
+//#include "connect6.h"
+//#include
+#include "./shared.h"
+//#include "pico.h"
+
+// Subtract this many points for moves at the edges.
+#define EDGEPENALTY 5
+
+using namespace std;
+
+/* The cost function simply counts all of the consecutive stones of same colour in
+ every direction from the spot for which the points is being calculated.
+
+Ex:
+
+.DDLL
+.DLDD
+DXDDD
+...D.
+
+Above, X is the spot being calculated.
+The points would be 2 (above) + 2(topright) + 3(right) + 1 (left) = 8.
+It treats opponent's stones and own stones with equal weighting.
+
+Return 0 if the spot y,x is already taken, else return the calculated value
+
+ */
+void move_to_ascii(int x,int y, char *move){
+ if (y >= 10){
+ move[0] = '1';
+ y -= 10;
+ } else {
+ move[0] = '0';
+ }
+ if (y == 0) move[1] = '0';
+ else if (y == 1) move[1] = '1';
+ else if (y == 2) move[1] = '2';
+ else if (y == 3) move[1] = '3';
+ else if (y == 4) move[1] = '4';
+ else if (y == 5) move[1] = '5';
+ else if (y == 6) move[1] = '6';
+ else if (y == 7) move[1] = '7';
+ else if (y == 8) move[1] = '8';
+ else if (y == 9) move[1] = '9';
+
+ // Do same for x.
+ if (x >= 10){
+ move[2] = '1';
+ x -= 10;
+ } else {
+ move[2] = '0';
+ }
+ if (x == 0) move[3] = '0';
+ else if (x == 1) move[3] = '1';
+ else if (x == 2) move[3] = '2';
+ else if (x == 3) move[3] = '3';
+ else if (x == 4) move[3] = '4';
+ else if (x == 5) move[3] = '5';
+ else if (x == 6) move[3] = '6';
+ else if (x == 7) move[3] = '7';
+ else if (x == 8) move[3] = '8';
+ else if (x == 9) move[3] = '9';
+
+}
+
+static int char_to_int(short x){
+ if(x>=48)
+ return x-48;
+ else
+ return 0;
+}
+
+
+/*
+ The AI Function that calls the cost function for every spot on the board.
+ It returns the location with the highest points. In the event of a tie, randomly decide.
+ Input the board and the colour being played.
+ Puts the move (in ASCII chars) inside move[4]. This is from [1 ... 19]
+ Puts the move (in integers) in moveY and moveX. This is from [0 ... 18]
+ */
+//void backup_move(Board *board, AIMoves *moves,AIMove *move){
+////when the threat doesn't return any good move
+////put in a single function to parition and speedup synthesis
+// //#pragma read_write_ports board.data combined 2
+// //#pragma internal_blockram myboard
+// //#pragma no_memory_analysis myboard
+// //#pragma read_write_ports moves.data combined 3
+// //#pragma internal_blockram moves
+// //#pragma no_memory_analysis moves
+// move->x=-1;
+// move->y=-1;
+// if (!aimoves_choose(moves, move)) {
+// // aimoves_free(moves);
+// //moves->len=0;
+// // /*moves = */ai_adjacent(board,moves);
+// aimoves_choose(moves, move);
+// }
+//}
+int connect6ai_synth(int firstmove,char movein[8], char colour, char moveout[8]){
+ //int id= PICO_initialize_PPA(ai_threats);
+ #pragma bitsize firstmove 17
+ char moveoutm[8];
+ #pragma internal_blockram moveoutm
+ short x,y,highx = 0;
+ //Board *myboard ;
+ static Board myboard;//={0,0,0,0,0,0,0,0,0,0,0,{{0}}};
+ //#pragma read_write_ports board.data combined 2
+ //#pragma preserve_array myboard.data
+ #pragma internal_blockram myboard
+ //#pragma no_memory_analysis myboard
+ static unsigned int current_random = 10;
+ AIMove move,move_threat,move_adj;
+ //#pragma internal_blockram move
+ //#pragma no_memory_analysis move
+ if(firstmove==0||firstmove==1) {
+ //my_srandom(1,¤t_random);
+ new_game(&myboard,board_size);
+ }
+ if(firstmove==0) myboard.moves_left=1;
+ else myboard.moves_left=2;
+
+ //-------------------------------------------------------------------------
+ if((firstmove >= 1)){
+ //update the board
+ y = char_to_int(movein[0])*10 + char_to_int(movein[1]) - 1;
+ x = char_to_int(movein[2])*10 + char_to_int(movein[3]) - 1;
+ if(colour==68){//'D')
+ //myboard[y][x] = (char)2;//76;//'L';
+ place_piece_type(&myboard,x,y,PIECE_WHITE);
+ myboard.turn=PIECE_BLACK;
+ }else{
+ //board[y][x] = (char)1;//68;//'D';
+ place_piece_type(&myboard,x,y,PIECE_BLACK);
+ myboard.turn=PIECE_WHITE;
+ }
+ }
+ if((firstmove >=3)){
+ //update the board
+ y = char_to_int(movein[4])*10 + char_to_int(movein[5]) - 1;
+ x = char_to_int(movein[6])*10 + char_to_int(movein[7]) - 1;
+ if(colour==68){//'D')
+ //board[y][x] = (char)2;//76;//'L';
+ place_piece_type(&myboard,x,y,PIECE_WHITE);
+ myboard.turn=PIECE_BLACK;
+ }else{
+ //board[y][x] = (char)1;//68;//'D';
+ place_piece_type(&myboard,x,y,PIECE_BLACK);
+ myboard.turn=PIECE_WHITE;
+ }
+ }
+ int i;
+ #pragma bitsize i 6
+
+ for(i=myboard.moves_left;i>0;i--){
+ //aimoves_free(&moves);
+ move.x=-1;
+ move.y=-1;
+
+ if (!ai_threats(&myboard,&move_threat)){
+ //aimoves_free(&moves);
+ //moves.len=0;
+ ai_adjacent(&myboard,&move_adj,current_random);
+ move.x=move_adj.x;
+ move.y=move_adj.y;
+ }else{
+ move.x=move_threat.x;
+ move.y=move_threat.y;
+ }
+
+ //backup_move(&myboard,&moves,&move);
+ //printf("DEBUG1:%d ",move.x);
+ // Modify the board based on current move.
+ place_piece_type(&myboard,move.x,move.y,myboard.turn);
+ /// Convert the int coordinates to corresponding ASCII chars
+
+ //if(firstmove==0)
+ //move_to_ascii(move.x+1,move.y+1,&moveout[0]);
+ //else if(myboard.moves_left==2)
+ //move_to_ascii(move.x+1,move.y+1,&moveout[0]);
+ //else
+ //move_to_ascii(move.x+1,move.y+1,&moveout[4]);
+ if(firstmove==0)
+ move_to_ascii(move.x+1,move.y+1,&moveoutm[0]);
+ else
+ move_to_ascii(move.x+1,move.y+1,&moveoutm[8-4*i]);
+ myboard.moves_left--;
+ }
+ if(firstmove==0){
+ #pragma unroll
+ for(i=0;i<4;i++)
+ moveout[i]=moveoutm[i];
+ }else{
+ #pragma unroll
+ for(i=0;i<8;i++)
+ moveout[i]=moveoutm[i];
+ }
+ //if(firstmove==0){
+ //moveout[0]=moveoutm[0];
+ //moveout[1]=moveoutm[1];
+ //moveout[2]=moveoutm[2];
+ //moveout[3]=moveoutm[3];
+ //}else{
+ //moveout[0]=moveoutm[0];
+ //moveout[1]=moveoutm[1];
+ //moveout[2]=moveoutm[2];
+ //moveout[3]=moveoutm[3];
+ //moveout[4]=moveoutm[4];
+ //moveout[5]=moveoutm[5];
+ //moveout[6]=moveoutm[6];
+ //moveout[7]=moveoutm[7];
+ //}
+
+ ////-------------------------------------------------------------------------
+ //if(firstmove>=1){
+ ////aimoves_free(&moves);
+ //moves.len=0;
+ //myboard.moves_left=1;
+ ///*moves=*/ai_threats(&myboard,&moves);
+ // move.x=-1;
+ // move.y=-1;
+ // if (!aimoves_choose(&moves, &move)) {
+ // //aimoves_free(&moves);
+ // moves.len=0;
+ // /*moves = */ai_adjacent(&myboard,&moves);
+ // aimoves_choose(&moves, &move);
+ // }
+ // //backup_move(&myboard,&moves,&move);
+ ////printf("DEBUG2%d\n",move.x);
+ //// Modify the board based on current move.
+ //place_piece_type(&myboard,move.x,move.y,myboard.turn);
+ //
+ // /// Convert the int coordinates to corresponding ASCII chars
+ //move_to_ascii(move.x+1,move.y+1,&moveout[4]);
+ //}
+ //PICO_finalize_PPA(id);
+ return 0;
+}
+
+
+
Index: trunk/XILINX/BUILD_SCC/synth_src/q.hpp
===================================================================
--- trunk/XILINX/BUILD_SCC/synth_src/q.hpp (nonexistent)
+++ trunk/XILINX/BUILD_SCC/synth_src/q.hpp (revision 17)
@@ -0,0 +1,110 @@
+#ifndef Q_H
+#define Q_H
+
+#include "shared.h"
+#define max_size 361
+#define ptr_bw 32
+class q {
+ //tp arr[max_size];
+ unsigned int head, tail;
+ unsigned char wrapped;
+ #pragma bitsize q.head ptr_bw
+ #pragma bitsize q.tail ptr_bw
+ #pragma bitsize q.wrapped 1
+
+ public:
+
+ /* constructor */
+ q () { head = tail = 0; wrapped = false; };
+
+ // /* returns front data of queue */
+ // tp front () {
+ // return arr[head];
+ // }
+
+ bool active;
+ /* return true iff queue is empty */
+ bool empty () {
+ return ((head == tail) && !wrapped);
+ }
+
+ /* return true iff queue is full */
+ bool full () {
+ return ((head == tail) && wrapped);
+ }
+ void reset(){
+ head=tail=0;wrapped=false;active=1;
+ }
+
+ /* pop front of queue, returning the front data */
+ /* q is corrupted if pop when empty */
+ AIMove pop ();
+
+ /* push data into back of queue */
+ /* q is corrupted if push when full */
+ void push (AIMove d);
+
+ /* return current size of the queue */
+ int size ();
+};
+//extern q moves_fifo;
+//#pragma no_inter_loop_memory_analysis moves_fifo.head
+//#pragma no_inter_loop_memory_analysis moves_fifo.tail
+//#pragma no_inter_loop_memory_analysis moves_fifo.wrapped
+//#pragma no_inter_loop_memory_analysis moves_fifo.active
+// #pragma no_inter_loop_memory_analysis moves_fifo
+extern q moves_fifo1;
+#pragma no_inter_loop_memory_analysis moves_fifo1.head
+#pragma no_inter_loop_memory_analysis moves_fifo1.tail
+#pragma no_inter_loop_memory_analysis moves_fifo1.wrapped
+#pragma no_inter_loop_memory_analysis moves_fifo1.active
+ #pragma no_inter_loop_memory_analysis moves_fifo1
+//#ifndef PICO_SYNTH
+// /* not synthesizable */
+// std::string to_string () const {
+// std::string s;
+// std::stringstream out;
+//
+// out << "{ ";
+//
+// if (wrapped) {
+// for (int i=head; i
+//std::ostream& operator << (std::ostream &os, const q &f)
+//{
+// os << f.to_string();
+// return os;
+//}
+//#endif
+//
+//
+//#undef Q_ASSERT
+////extern q moves_fifo;
+#endif
Index: trunk/XILINX/BUILD_SCC/synth_src/connect6_synth.h
===================================================================
--- trunk/XILINX/BUILD_SCC/synth_src/connect6_synth.h (nonexistent)
+++ trunk/XILINX/BUILD_SCC/synth_src/connect6_synth.h (revision 17)
@@ -0,0 +1,5 @@
+#ifndef _CONNECT6_H_SYNTH
+#define _CONNECT6_H_SYNTH
+
+int connect6ai_synth(int firstmove,char movein[8], char colour, char moveout[8]);
+#endif
Index: trunk/XILINX/BUILD_SCC/synth_src/threats.cpp
===================================================================
--- trunk/XILINX/BUILD_SCC/synth_src/threats.cpp (nonexistent)
+++ trunk/XILINX/BUILD_SCC/synth_src/threats.cpp (revision 17)
@@ -0,0 +1,591 @@
+
+/*
+
+connectk -- a program to play the connect-k family of games
+Copyright (C) 2007 Michael Levin
+
+This program is free software; you can redistribute it and/or
+modify it under the terms of the GNU General Public License
+as published by the Free Software Foundation; either version 2
+of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+//#include "config.h"
+//#include
+//#include h>
+#include "./shared.h"
+//#include
+
+/* Bits per threat level */
+#define BITS_PER_THREAT 6
+
+
+typedef struct {
+ int threat[2];
+ PIECE turn[2];
+} Line;
+typedef struct{
+ int data[MAX_CONNECT_K + 1][2];
+}threat_count_array;
+
+static AIWEIGHT threat_bits(int threat, PIECE type, Board *b)
+/* Bit pack the threat value */
+{
+ if (threat < 1)
+ return 0;
+
+ /* No extra value for building sequences over k - p unless it is
+ enough to win */
+ if (b->turn == type && connect_k - threat <= b->moves_left)
+ threat = connect_k - place_p + 1;
+ else if (threat >= connect_k - place_p)
+ threat = connect_k - place_p - (type == b->turn);
+
+ return 1 << ((threat - 1) * BITS_PER_THREAT);
+}
+
+static void threat_mark(int i, int threat, PIECE type,Board *b,Line *line)
+{
+ int j, index = 0;
+
+ if (threat <= 0)
+ return;
+
+ /* No extra value for building sequences over k - p unless it is
+ enough to win */
+ if (b->turn == type && connect_k - threat <= b->moves_left)
+ threat = connect_k - place_p + 1;
+ else if (threat >= connect_k - place_p)
+ threat = connect_k - place_p - (type == b->turn);
+
+ /* Do not mark if this threat is dominated by a preceeding threat;
+ Likewise supress any smaller threats */
+ for (j = i; j >= 0 && j > i - connect_k; j--)
+ if (line[j].threat[0] > threat)
+ return;
+ else if (line[j].threat[0] < threat) {
+ line[j].threat[0] = 0;
+ line[j].threat[1] = 0;
+ }
+
+ /* Store up to two threats per tile in the line */
+ if (line[i].threat[index])
+ index++;
+ line[i].threat[index] = threat;
+ line[i].turn[index] = type;
+}
+
+int threat_window(int x, int y, int dx, int dy,
+ PIECE *ptype, int *pdouble,Board *b)
+{
+ int minimum, maximum, count = 0;
+ PIECE p, type = PIECE_NONE;
+
+ /* Check if this tile is empty */
+ p = piece_at(b, x, y);
+ if (!piece_empty(p))
+ return 0;
+
+ /* Push forward the maximum and find the window type */
+ #pragma unroll
+ for (maximum = 1; maximum < connect_k; maximum++) {
+ p = piece_at(b, x + dx * maximum, y + dy * maximum);
+ if (p == PIECE_ERROR)
+ break;
+ if (!piece_empty(p)) {
+ if (type == PIECE_NONE)
+ type = p;
+ else if (type != p)
+ break;
+ count++;
+ }
+ }
+ maximum--;
+
+ /* Try to push the entire window back */
+ #pragma unroll
+ for (minimum = -1; minimum > -connect_k; minimum--) {
+ p = piece_at(b, x + dx * minimum, y + dy * minimum);
+ if (p == PIECE_ERROR || piece_empty(p))
+ break;
+ if (type == PIECE_NONE)
+ type = p;
+ else if (type != p)
+ break;
+ if (maximum - minimum > connect_k - 1) {
+ p = piece_at(b, x + dx * maximum, y + dy * maximum);
+ if (p == type)
+ count--;
+ maximum--;
+ }
+ count++;
+ }
+ minimum++;
+
+ /* Push back minimum if we haven't formed a complete window, this window
+ can't be a double */
+ if (maximum - minimum < connect_k - 1) {
+ for (minimum--; minimum > maximum - connect_k; minimum--) {
+ p = piece_at(b, x + dx * minimum, y + dy * minimum);
+ if (p == PIECE_ERROR)
+ break;
+ if (!piece_empty(p)) {
+ if (type != p)
+ break;
+ if (type == PIECE_NONE)
+ type = p;
+ count++;
+ }
+ }
+ *pdouble = 0;
+ minimum++;
+ }
+
+ *ptype = type;
+ if (maximum - minimum >= connect_k - 1)
+ return count;
+ return 0;
+}
+
+/*static*/ AIWEIGHT threat_line(int x, int y, int dx, int dy,Board *b,Board *bwrite,AIMoves *moves,int k)
+{
+
+ //#pragma read_write_ports threat_counts.data combined 2
+ //#pragma internal_blockram threat_counts
+ //#pragma no_memory_analysis threat_counts
+
+ //#pragma read_write_ports b.data combined 2
+ #pragma internal_blockram b
+ #pragma internal_blockram bwrite
+ //#pragma read_write_ports b.data separate 1 readonly 2 writeonly
+ //#pragma no_memory_analysis b
+ /* This is the line of threats currently being processed */
+ Line line[board_size]={{1},{2}};
+ #pragma internal_fast line
+ //#pragma no_memory_analysis line
+ /* Running tally of threats for both players */
+ //static int threat_counts[MAX_CONNECT_K + 1][2];
+ threat_count_array threat_counts={{0}};
+ #pragma internal_fast threat_counts
+ //#pragma read_write_ports threat_counts.data combined 2
+ //#pragma no_memory_analysis threat_counts
+ if (k==1) board_copy(b, bwrite);
+ int i;
+ AIWEIGHT weight = 0;
+ ///* Clear threat tallys */
+ //for (i = 0; i < connect_k; i++) {
+ // threat_counts.data[i][0] = 1;
+ // threat_counts.data[i][1] = 1;
+ //}
+
+ /* Mark the maximum threat for each */
+ for (i = 0; x >= 0 && x < board_size && y >= 0 && y < board_size; i++) {
+ int count[2], tmp, double_threat = 1;
+ PIECE type[2];
+
+ count[0] = threat_window(x, y, dx, dy, type, &double_threat,bwrite);
+ count[1] = threat_window(x, y, -dx, -dy, type + 1,
+ &double_threat,bwrite);
+ if (count[1] > count[0]) {
+ tmp = count[1];
+ count[1] = count[0];
+ count[0] = tmp;
+ tmp = type[1];
+ type[1] = type[0];
+ type[0] = tmp;
+ }
+ line[i].threat[0] = 0;
+ line[i].threat[1] = 0;
+ threat_mark(i, count[0], type[0],bwrite,&line[0]);
+ if (double_threat)
+ threat_mark(i, count[1], type[1],bwrite,&line[0]);
+ x += dx;
+ y += dy;
+ }
+
+ /* Commit stored line values to the board */
+ x -= dx;
+ y -= dy;
+ for (i--; x >= 0 && x < board_size && y >= 0 && y < board_size; i--) {
+ AIWEIGHT bits[2];
+ PIECE p;
+
+ bits[0] = threat_bits(line[i].threat[0], line[i].turn[0],bwrite);
+ bits[1] = threat_bits(line[i].threat[1], line[i].turn[1],bwrite);
+ p = piece_at(bwrite, x, y);
+ if (piece_empty(p) && line[i].threat[0]) {
+ threat_counts.data[line[i].threat[0]][line[i].turn[0] - 1]++;
+ if (line[i].threat[1])
+ threat_counts.data[line[i].threat[1]]
+ [line[i].turn[1] - 1]++;
+ if (p >= PIECE_THREAT0)
+ place_threat(bwrite, x, y, p - PIECE_THREAT0 +
+ bits[0] + bits[1]);
+ else
+ place_threat(bwrite, x, y, bits[0] + bits[1]);
+ }
+ if (bwrite->turn != line[i].turn[0])
+ bits[0] = -bits[0];
+ if (bwrite->turn != line[i].turn[1])
+ bits[1] = -bits[1];
+ weight += bits[0] + bits[1];
+ x -= dx;
+ y -= dy;
+ }
+ return weight;
+}
+
+/*AIMoves*/int ai_threats(Board *board,AIMove *move)
+{
+ //#pragma read_write_ports board.data combined 2
+ #pragma internal_blockram board
+ //#pragma no_memory_analysis board
+
+ //#pragma internal_blockram move
+ //#pragma no_memory_analysis move
+
+ /////////* All threat functions work on this board */
+ /*static*/ Board b;//={0,0,0,0,0,0,0,0,0,0,0,{{0}}} ;//= NULL;
+ //#pragma read_write_ports b.data combined 2
+ #pragma internal_blockram b
+ //#pragma read_write_ports b.data separate 1 readonly 2 writeonly
+ //#pragma no_memory_analysis b
+ /*static*/ Board bwrite;//={0,0,0,0,0,0,0,0,0,0,0,{{0}}} ;//= NULL;
+ //#pragma read_write_ports b.data combined 2
+ #pragma internal_blockram bwrite
+ //#pragma no_memory_analysis b
+ /*static*/ AIMoves moves;//={{0,0,0,{{0,0,0}}}};
+ //#pragma read_write_ports moves.data combined 3
+ #pragma internal_blockram moves
+ //#pragma no_memory_analysis moves
+
+ moves.len=0;
+ //AIMoves moves;
+ AIWEIGHT u_sum = 0;
+ int i;
+
+ //b = board_new();
+ //Board b;
+ board_copy(board, &b);
+
+ /* Clear threat tallys */
+ //for (i = 0; i < connect_k; i++) {
+ // threat_counts.data[i][0] = 0;
+ // threat_counts.data[i][1] = 0;
+ //}
+/*---------------------------------------------------------------------------*/
+ // /* Horizontal lines */
+ // for (i = 0; i < board_size; i++)
+ // u_sum += threat_line(0, i, 1, 0,&b);
+
+ // /* Vertical lines */
+ // for (i = 0; i < board_size; i++)
+ // u_sum += threat_line(i, 0, 0, 1,&b);
+
+ // /* SE diagonals */
+ // for (i = 0; i < board_size - connect_k + 1; i++)
+ // u_sum += threat_line(i, 0, 1, 1,&b);
+ // for (i = 1; i < board_size - connect_k + 1; i++)
+ // u_sum += threat_line(0, i, 1, 1,&b);
+
+ // /* SW diagonals */
+ // for (i = connect_k - 1; i < board_size; i++)
+ // u_sum += threat_line(i, 0, -1, 1,&b);
+ // for (i = 1; i < board_size - connect_k + 1; i++)
+ // u_sum += threat_line(board_size - 1, i, -1, 1,&b);
+/*---------------------------------------------------------------------------*/
+//rewritten for hardware
+/*---------------------------------------------------------------------------*/
+ int j;
+ int arg1,arg2,arg3,arg4,loop_bound,loop_begin;
+ int k=0;
+ for(j=0;j<6;j++){
+ switch(j){
+ case 0:
+ {
+ loop_begin=0;
+ loop_bound=board_size;
+ break;
+ }
+ case 1:
+ {
+ loop_begin=0;
+ loop_bound=board_size;
+ break;
+ }
+ case 2:
+ {
+ loop_begin=0;
+ loop_bound=board_size-connect_k+1;
+ break;
+ }
+ case 3:
+ {
+ loop_begin=1;
+ loop_bound=board_size-connect_k+1;
+ break;
+ }
+ case 4:
+ {
+ loop_begin=connect_k-1;
+ loop_bound=board_size;
+ break;
+ }
+ case 5:
+ {
+ loop_begin=1;
+ loop_bound=board_size-connect_k+1;
+ break;
+ }
+ default:{
+ break;
+ }
+ }
+ for (i = loop_begin; i < loop_bound; i++){
+ k++;
+ switch(j){
+ case 0:
+ {
+ arg1=0;
+ arg2=i;
+ arg3=1;
+ arg4=0;
+ break;
+ }
+ case 1:
+ {
+ arg1=i;
+ arg2=0;
+ arg3=0;
+ arg4=1;
+ break;
+ }
+ case 2:
+ {
+ arg1=i;
+ arg2=0;
+ arg3=1;
+ arg4=1;
+ break;
+ }
+ case 3:
+ {
+ arg1=0;
+ arg2=i;
+ arg3=1;
+ arg4=1;
+ break;
+ }
+ case 4:
+ {
+ arg1=i;
+ arg2=0;
+ arg3=-1;
+ arg4=1;
+ break;
+ }
+ case 5:
+ {
+ arg1=board_size-1;
+ arg2=i;
+ arg3=-1;
+ arg4=1;
+ break;
+ }
+ default:{
+ break;
+ }
+ }
+
+
+ u_sum += threat_line(arg1, arg2, arg3, arg4,&b,&bwrite,&moves,k);
+ }
+ }
+/*---------------------------------------------------------------------------*/
+ //board_copy(&b,&b_marks);
+ /*moves = */ ai_marks(&bwrite, PIECE_THREAT(1),&moves);
+ moves.utility = u_sum;
+ if (!aimoves_choose(&moves, move))
+ return 0;
+ else return 1;
+ //board_free(b);
+ //return moves;
+ //return 0;
+}
+
+//void debug_counts(void)
+//{
+// int i, sum = 0;
+//
+// if (!b)
+// return;
+//
+// g_debug("Threat counts (black, white):");
+// for (i = 1; i < connect_k; i++) {
+// g_debug("%d: %3d %3d", i, threat_counts[i][0],
+// threat_counts[i][1]);
+// sum += threat_counts[i][0] * threat_bits(i, b->turn) -
+// threat_counts[i][1] *
+// threat_bits(i, other_player(b->turn));
+// }
+// if (sum > 0)
+// g_debug("Threat sum: %d (10^%.2f)", sum, log10((double)sum));
+// else if (sum < 0)
+// g_debug("Threat sum: %d (-10^%.2f)", sum, log10((double)-sum));
+// else
+// g_debug("Threat sum: 0");
+//}
+
+//static int threat_number(int player, int threat,threat_count_array threat_counts)
+//{
+// return threat_counts.data[threat][player] / (connect_k - threat);
+//}
+
+//AIMoves *ai_priority(const Board *b)
+//{
+// AIMoves *moves;
+// int i, j, stage[2] = {1, 1}, mask, bits;
+//
+// moves = ai_threats(b);
+//
+// /* Do not prioritize if we've won */
+// if (threat_counts[connect_k - place_p + 1][b->turn - 1]) {
+// moves->utility = AIW_WIN;
+// return moves;
+// }
+//
+// /* Find the largest supported threat for each player */
+// for (i = 2; i < connect_k; i++) {
+// if (threat_number(0, i - 1) >= place_p &&
+// threat_number(0, i) > place_p)
+// stage[0] = i;
+// if (threat_number(1, i - 1) >= place_p &&
+// threat_number(1, i) > place_p)
+// stage[1] = i;
+// }
+//
+// //if (opt_debug_stage)
+// // g_debug("Stages %d/%d", stage[0], stage[1]);
+//
+// /* Do not prioritize if we're losing */
+// if (stage[b->turn - 1] <= stage[other_player(b->turn) - 1]) {
+// moves->utility = -stage[other_player(b->turn) - 1];
+// return moves;
+// }
+//
+// /* Threats above the player's stage are no more valuable than the
+// stage */
+// bits = 1 << (stage[b->turn - 1] * BITS_PER_THREAT);
+// mask = bits - 1;
+// for (i = 0; i < moves->len; i++) {
+// AIWEIGHT w = moves->data[i].weight, w2;
+//
+// if (w < AIW_THREAT_MAX && w >= bits) {
+// w2 = w & mask;
+// w = w & ~mask;
+// for (j = stage[b->turn - 1];
+// w && j < connect_k - place_p + 1; j++) {
+// w = w >> BITS_PER_THREAT;
+// w2 += w & mask;
+// }
+// moves->data[i].weight = w2;
+// }
+// }
+//
+// /* Stage determines weight */
+// moves->utility = stage[b->turn - 1];
+// return moves;
+//}
+/*AIMoves*/ void ai_marks(Board *b, PIECE minimum,AIMoves *moves)
+{
+ //#pragma read_write_ports b.data combined 2
+ #pragma internal_blockram b
+ //#pragma no_memory_analysis b
+ //AIMoves *moves = aimoves_new();
+ //AIMoves moves;
+ //AIMoves moves[361];
+ AIMove move;
+ PIECE p;
+ for (move.y = 0; move.y < board_size; move.y++)
+ for (move.x = 0; move.x < board_size; move.x++)
+ if ((p = piece_at(b, move.x, move.y)) >= minimum) {
+ move.weight = p - PIECE_THREAT0;
+ aimoves_set(moves, &move);
+ }
+ //return moves;
+}
+
+static gboolean is_adjacent( Board *b, BCOORD x, BCOORD y, int dist)
+{
+ int dx, dy, count;
+ #pragma bitsize dx 4
+ #pragma bitsize dy 4
+ PIECE p;
+
+ if (!piece_empty(piece_at(b, x, y)))
+ return FALSE;
+ for (dy = -1; dy < 2; dy++)
+ for (dx = -1; dx < 2; dx++) {
+ if (!dx && !dy)
+ continue;
+ count = count_pieces(b, x, y, PIECE_NONE, dx, dy, &p);
+ if (count - 1 < dist && p != PIECE_NONE)
+ return TRUE;
+ }
+ return FALSE;
+}
+/*AIMoves **/ void enum_adjacent(Board *b, int dist,AIMoves *moves,unsigned int current_random)
+{
+ //AIMoves *moves;
+ AIMove move;
+
+ move.weight = AIW_NONE;
+ //moves = aimoves_new();
+ for (move.y = 0; move.y < board_size; move.y++)
+ for (move.x = 0; move.x < board_size; move.x++)
+ if (is_adjacent(b, move.x, move.y, dist))
+ aimoves_append(moves, &move);
+ //aimoves_shuffle(moves,current_random);
+ //return moves;
+}
+/*AIMoves **/void ai_adjacent( Board *b, AIMove *move,unsigned int current_random)
+{
+ //#pragma read_write_ports board.data combined 2
+ #pragma internal_blockram b
+ //#pragma no_memory_analysis b
+
+ /*static*/ AIMoves moves;//={{0,0,0,{{0,0,0}}}};
+ //#pragma read_write_ports moves.data combined 3
+ #pragma internal_blockram moves
+ //#pragma no_memory_analysis moves
+ //#pragma read_write_ports moves.data combined 3
+ //#pragma internal_blockram moves
+ //#pragma no_memory_analysis moves
+ //AIMove move;
+ //AIMoves *moves;
+ moves.len=0;
+ /* Get all open tiles adjacent to any piece */
+ /*moves =*/ enum_adjacent(b, 1,&moves,current_random);
+ if (moves.len){
+ aimoves_choose(&moves, move);
+
+ return ;//moves;
+ }
+ /* Play in the middle if there are no open adjacent tiles */
+ move->x = board_size / 2;
+ move->y = board_size / 2;
+ move->weight = AIW_NONE;
+ //aimoves_append(&moves, move);
+ //aimoves_choose(&moves, move);
+ //return moves;
+}
trunk/XILINX/BUILD_SCC/synth_src/threats.cpp
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC/synth_src/shared.h
===================================================================
--- trunk/XILINX/BUILD_SCC/synth_src/shared.h (nonexistent)
+++ trunk/XILINX/BUILD_SCC/synth_src/shared.h (revision 17)
@@ -0,0 +1,454 @@
+
+/*
+
+connectk -- a program to play the connect-k family of games
+Copyright (C) 2007 Michael Levin
+
+This program is free software; you can redistribute it and/or
+modify it under the terms of the GNU General Public License
+as published by the Free Software Foundation; either version 2
+of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+/* Some definitions in case glib is not included */
+//#ifndef TRUE
+#define TRUE 1
+#define FALSE 0
+#define NULL ((void*)0)
+//#endif
+//#ifndef __G_TYPES_H__
+typedef unsigned int gboolean;
+#pragma bitsize gboolean 1
+typedef int gsize;
+//#endif
+
+
+/*
+ * Options
+ */
+
+/* These are boolean options the user can toggle through the "Options" menu.
+ Do not modify them directly as the "Options" menu will not reflect your
+ changes. You can add more options in connectk.c */
+extern int opt_pause_ai, /* Pause AI to inspect the board */
+// opt_det_ai, /* No randomness */
+ opt_print_u, /* Print utility after every move */
+ opt_debug_dfsc, /* Print out debug messages related to the DFS
+ cache */
+ opt_debug_thread, /* Print messages related to thread and mutex function */
+ opt_mark_log, /* Take log of weights before marking */
+ opt_mark_norm, /* Normalize to the largest weight */
+ opt_debug_stage, /* Debug priority stages */
+ opt_grayscale; /* Use grayscale rendering for print outs */
+
+/*
+ * Utility
+ */
+
+#ifdef _EFISTDARG_H_
+char *nvav(int *plen, const char *fmt, va_list va);
+#endif
+char *nva(int *plen, const char *fmt, ...);
+char *va(const char *fmt, ...);
+/* The va family of functions simplify string processing by allowing
+ printf-style substitution with any string-accepting function.
+
+ For example:
+ window_status(va("1 + 2 = %d", 1 + 2));
+
+ nva provides additional functionality by outputting the length of the
+ formatted string into the integer pointed to by plen. nvav accepts a variable
+ argument indirectly. */
+
+void window_status(const char *msg);
+/* Sets the status bar text of the main window */
+
+/*
+ * Allocation Chain
+ */
+
+typedef struct AllocChain {
+ gboolean free;
+ /* Is this object unallocated? */
+
+ unsigned int id;
+ /* Each object has a unique id */
+
+ struct AllocChain *next;
+ /* Next object in the chain */
+} AllocChain;
+
+typedef AllocChain *(*AllocFunc)(AllocChain *old_ac);
+
+AllocChain *achain_new(AllocChain **root, AllocFunc af);
+void achain_free(AllocChain *ac);
+void achain_copy(const AllocChain *src, AllocChain *dest, gsize mem);
+
+/*
+ * Game state
+ */
+
+/* We limit the maximum values of these variables; note that these are not
+ arbitrary limits and should be modified with care */
+#define MAX_BOARD_SIZE 59
+#define MAX_CONNECT_K 12
+#define MAX_PLACE_P 12
+#define MAX_START_Q 6
+#define MAX_DEPTH 9
+#define MAX_BRANCH 32
+
+
+#define board_size 19
+#define board_stride 21
+#define move_no 0
+#define move_last 0
+#define connect_k 6
+#define place_p 2
+#define start_q 1
+#define opt_det_ai 1
+//extern int board_size, board_stride, move_no, connect_k, place_p, start_q;
+/* Board size (for all boards), moves in the game, connect_k to win, place_p
+ moves at a time, black has start_q moves on the first move; do NOT modify
+ these directly! */
+
+enum {
+ PIECE_ERROR = -1,
+ /* Error pieces form a one tile deep border around the board */
+
+ PIECE_NONE = 0,
+ PIECE_BLACK,
+ PIECE_WHITE,
+ /* Empty and played pieces */
+
+ PIECES,
+ /* Total number of normal pieces (2) */
+
+ PIECE_SEARCHED,
+ PIECE_SEARCHED_MAX = PIECE_SEARCHED + MAX_DEPTH,
+ /* Markers used by the search system */
+
+ PIECE_THREAT0,
+ PIECE_MARKER = PIECE_THREAT0,
+ /* These threat markers are usable by the AIs */
+};
+typedef int PIECE;
+//#pragma bitsize PIECE 16
+
+#define MAX_THREAT (INT_MAX - PIECE_THREAT0)
+/* Highest value a threat marker can have */
+
+#define PIECE_THREAT(n) (PIECE_THREAT0 + (n))
+/* This marker represents a threat n-turns (of that player) away */
+
+#define piece_empty(p) ((p) == PIECE_NONE || (p) >= PIECES)
+/* Checks if a piece is an empty or a marker */
+
+typedef unsigned int PLAYER;
+/* Type for AIs, this is the index of the AI entry in ai.c */
+
+typedef int BCOORD;
+#pragma bitsize BCOORD 8
+/* Type for board coordinates */
+
+typedef struct Board {
+ int ac;
+ /* Allocation chain must be the first member */
+ #pragma bitsize ac 4
+ unsigned int moves_left;
+ /* How many moves the current player has left */
+ #pragma bitsize moves_left 8
+
+ //struct Board *parent; //not synthesizable
+ int parent;
+ /* The board preceeding this one in history */
+ #pragma bitsize parent 4
+
+ gboolean won;
+ BCOORD win_x1, win_y1, win_x2, win_y2;
+ /* On won boards, used to indicate where the winning line is */
+
+ PIECE turn;
+ /* Whose turn it is on this board */
+
+ BCOORD move_x, move_y;
+ /* The move to the next Board in history */
+
+ PIECE data[board_stride][board_stride];
+} Board;
+/* The board structure represents the state of the game board. Do NOT preserve
+ board pointers across games. */
+
+extern AllocChain *board_root;
+extern gsize board_mem;
+/* Variables for the allocation chain */
+
+//extern Board board;
+/* This is the current board. Do NOT modify it, that's cheating. :) */
+const char *bcoords_to_string(BCOORD x, BCOORD y);
+const char *bcoord_to_alpha(BCOORD c);
+/* Return a static string representing a board coordinate pair */
+
+void string_to_bcoords(const char *string, BCOORD *x, BCOORD *y);
+/* Attempts to convert a string to board coordinates */
+
+void new_game(Board *board,unsigned int size);
+
+AllocChain *board_alloc(AllocChain *data);
+#define board_new() ((Board*)achain_new(&board_root, board_alloc))
+#define board_free(b) achain_free((AllocChain*)b)
+/* Boards are dynamically allocated and must be free'd */
+
+//#define board_copy(from, to) achain_copy((AllocChain*)from, (AllocChain*)to,\
+ board_mem)
+void board_copy(const Board *from, Board *to);
+/* Overwrite one board with another */
+
+void board_clean(Board *b);
+/* Remove all threat markers from a board */
+
+int threat_count(const Board *b, PIECE player);
+/* Gives the number of threats on a board for the current player */
+
+Board *board_at(unsigned int move);
+/* Returns a static pointer to a board in the history at move */
+
+//int count_pieces(const Board *b, BCOORD x, BCOORD y, PIECE type,
+int count_pieces(const Board *b, BCOORD x, BCOORD y, PIECE type,
+ int dx, int dy, PIECE *out);
+/* Count consecutive pieces of type starting from (x, y) in the direction given
+ by (dx, dy); includes (x, y) itself in the count and outputs the final
+ piece to out if it is not NULL */
+
+gboolean check_win_full(const Board *b, BCOORD x, BCOORD y,
+ BCOORD *x1, BCOORD *y1, BCOORD *x2, BCOORD *y2);
+#define check_win(b, x, y) check_win_full(b, x, y, 0, 0, 0, 0)
+/* Returns non-zero if placing a piece of type at (x, y) on the current board
+ will result in a win for that player. The start and end coordinates of the
+ winning line will be placed in (x1, y1) and (x2, y2). */
+
+static inline PIECE piece_at(const Board *b, BCOORD x, BCOORD y)
+{
+ //return b->data[(y + 1) * board_stride + x + 1];
+ return b->data[y+1][x+1];
+}
+/* Returns the piece at (x, y) on board b. If the coordinates are out of range,
+ this function will return PIECE_ERROR. */
+
+char piece_to_char(PIECE piece);
+/* Returns a one character representation of a piece (e.g. 'W', 'B', etc) */
+
+const char *piece_to_string(PIECE piece);
+/* Returns a static string representation of a piece (e.g. "White" etc) */
+
+static inline void place_piece_type(Board *b, BCOORD x, BCOORD y, PIECE type)
+{
+ //b->data[(y + 1) * board_stride + x + 1] = type;
+ b->data[y+1][x+1]=type;
+}
+#define place_piece(b, x, y) place_piece_type(b, x, y, (b)->turn)
+#define place_threat(b, x, y, n) place_piece_type(b, x, y, PIECE_THREAT(n))
+/* Places a piece on board b, overwriting any piece that was previously in that
+ place */
+
+#define other_player(p) ((p) == PIECE_BLACK ? PIECE_WHITE : PIECE_BLACK)
+/* Invert a player piece */
+
+/*
+ * Move arrays
+ */
+
+/* Some guideline values for move weights: */
+#define AIW_MAX INT_MAX /* largest weight value */
+#define AIW_MIN INT_MIN /* smallest weight value */
+#define AIW_WIN AIW_MAX /* this move wins the game */
+#define AIW_DEFEND (AIW_WIN - 2) /* defends from an opponent win */
+#define AIW_NONE 0 /* does nothing */
+#define AIW_DRAW AIW_NONE /* draw game */
+#define AIW_LOSE (-AIW_WIN) /* this move loses the game */
+#define AIW_THREAT_MAX 262144 /* value of an immediate threat */
+
+typedef int AIWEIGHT;
+/* Type for AI move weights (utilities) */
+#pragma bitsize AIWEIGHT 32
+
+typedef struct {
+ AIWEIGHT weight;
+ BCOORD x, y;
+} AIMove;
+/* AIs return an array filled with these */
+
+typedef struct AIMoves {
+ int ac;
+ /* Allocation chain must be the first member */
+ #pragma bitsize ac 4
+
+ unsigned int len;
+ /* Number of members in data */
+ #pragma bitsize len 8
+
+ AIWEIGHT utility;
+ /* A composite utility value set by some AIs when producing a moves
+ list */
+
+ AIMove data[361];
+ /* Array of AIMove structures */
+} AIMoves;
+/* An array type for holding move lists */
+
+AllocChain *aimoves_alloc(AllocChain *data);
+#define aimoves_new() ((AIMoves*)achain_new(&aimoves_root, aimoves_alloc))
+//#define aimoves_free(m) achain_free((AllocChain*)(m))
+static inline void aimoves_free(AIMoves *m) {
+ m->len=0;
+}
+///////////* Move arrays are dynamically allocated and must be free'd */
+//////////
+//////////#define aimoves_copy(from, to) achain_copy((AllocChain*)(from),\
+////////// (AllocChain*)(to), aimoves_mem)
+///////////* Overwrite one array with another */
+//////////
+//////////void aimoves_add(AIMoves *moves, const AIMove *aim);
+///////////* Add an AIMove to an AIMoves array; move weights will be added to existing
+////////// weights */
+//////////
+void aimoves_append(AIMoves *moves, const AIMove *aim);
+#define aimoves_set aimoves_append
+///////////* Add an AIMove to an AIMoves array; existing moves weights will be
+////////// overwritten */
+//////////
+int aimoves_choose(AIMoves *moves, AIMove *move);
+/* Will choose one of the best moves from a GArray of AIMove structures at
+ random. Returns non-zero if a move was chosen or zero if a move could not
+ be chosen for some reason. */
+//////////
+int aimoves_compare(const void *a, const void *b);
+/* A comparison function for sorting move lists by weight */
+//////////
+//////////void aimoves_crop(AIMoves *moves, unsigned int n);
+///////////* Reduce a moves list to the top-n by weight */
+//////////
+//////////void aimoves_concat(AIMoves *m1, const AIMoves *m2);
+///////////* Concatenates m2 to m1 without checking for duplicates */
+//////////
+//////////AIMoves *aimoves_dup(const AIMoves *moves);
+///////////* Duplicate a GArray of moves */
+//////////
+int aimoves_find(const AIMoves *moves, BCOORD x, BCOORD y);
+///////////* Returns the index of (x, y) if it is in moves or -1 otherwise */
+//////////
+//////////void aimoves_range(AIMoves *moves, AIWEIGHT *min, AIWEIGHT *max);
+///////////* Find the smallest and largest weight in the move array */
+//////////
+//////////void aimoves_merge(AIMoves *m1, const AIMoves *m2);
+///////////* Merges m2 into m1, the highest weight is used for duplicates */
+//////////
+//////////void aimoves_print(const AIMoves *moves);
+///////////* Prints out an array of moves */
+//////////
+//////////void aimoves_remove(AIMoves *moves, BCOORD x, BCOORD y);
+///////////* Remove an AIMove from a GArray of AIMoves */
+//////////
+//////////void aimoves_remove_index_fast(AIMoves *moves, int i);
+///////////* Remove a move from the list by overwriting it by the last move and
+////////// decrementing the length */
+//////////
+void aimoves_shuffle(AIMoves *moves,unsigned int current_random);
+/* Shuffle a list of moves */
+
+void aimoves_sort(AIMoves *moves);
+/* Sort a list of moves by descending weight */
+
+//////////void aimoves_subtract(AIMoves *m1, const AIMoves *m2);
+///////////* Subtracts members of m2 from m1; O(n^2) */
+//////////
+extern AllocChain *aimoves_root;
+//////////extern gsize aimoves_mem;
+///////////* Allocation chain variables */
+//////////
+//////////const char *aiw_to_string(AIWEIGHT w);
+///////////* Convert a weight to a string representation */
+//////////
+//////////char *aimove_to_string(const AIMove *move);
+///////////* Convert a move to a string representation */
+//////////
+///////////*
+////////// * AI helper functions
+////////// */
+//////////
+//////////extern int ai_stop;
+///////////* If this variable is non-zero, the system is trying to stop the AI thread
+////////// and your AI should exit. Do not set this yourself. */
+//////////
+//////////typedef AIMoves *(*AIFunc)(const Board *b);
+///////////* AIs are defined as functions that output an unsorted, weighted list of board
+////////// coordinates for an arbitrary board. To create an AI in a file other than
+////////// ai.c, add a prototype of the function here and in ai.c. */
+//////////
+//////////AIMoves *enum_top_n(const Board *b, int n);
+///////////* Returns an array containing the top n moves according to the utility
+////////// function */
+//////////
+/*AIMoves **/ void enum_adjacent(Board *b, int dist,AIMoves *moves,unsigned int current_random);
+/* Enumerate empty tiles at most dist away from some other piece on the board */
+
+/*AIMoves **/void ai_marks(Board *b, PIECE min,AIMoves *moves);
+/* Fills a moves list with tiles marked at least PIECE_THREAT(min) */
+
+/*
+ * AI
+ */
+
+/* This table holds the information about all of the AIs in the program. Each
+ has a short and long description. The short description will be used for
+ the command line interface and the long description appears in the UI menu.
+ Each AI has an associated AIFunc which outputs a move for the current
+ board. */
+///////////typedef struct AI {
+/////////// char *s_desc, *l_desc;
+/////////// AIFunc func;
+///////////} AI;
+///////////
+///////////AIMoves *ai_sequences(const Board *b);
+////////////* The square of the number of pieces in a window */
+///////////
+///////////AIMoves *ai_mesh(const Board *b);
+////////////* The board as a mesh weighed down by the pieces */
+///////////
+///////////AIMoves *ai_monte_carlo(const Board *b);
+////////////* Chooses the best move based on which one wins the most random games */
+///////////
+///////////AIMoves *ai_random(const Board *b);
+////////////* Plays in a random tile */
+///////////
+/*AIMoves */ void ai_adjacent(Board *b,AIMove *move,unsigned int current_random);
+/* Plays in a random tile adjacent to any piece on the board */
+
+///////////AIMoves *ai_windows(const Board *b);
+////////////* Plays in the best defensive position */
+///////////
+///////////AIMoves *ai_utility(const Board *b);
+///////////AIMoves *ai_dfs_utility(const Board *b);
+////////////* Utility function */
+///////////
+/*AIMoves **/int ai_threats(Board *board,AIMove *move);
+AIMoves *ai_priority(const Board *b);
+/* Multi-level threats */
+
+
+
+void my_srandom(int seed,unsigned int *current_random);
+int my_irand(int imax,unsigned int current_random);
+//void backup_move(Board *board, AIMoves *moves,AIMove *move);
+AIWEIGHT threat_line(int x, int y, int dx, int dy,Board *b,Board *bwrite,AIMoves *moves,int k);
+int threat_window(int x, int y, int dx, int dy,
+ PIECE *ptype, int *pdouble,Board *b);
+int connect6ai_synth(int firstmove,char movein[8], char colour, char moveout[8]);
trunk/XILINX/BUILD_SCC/synth_src/shared.h
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC/synth_src/util.cpp
===================================================================
--- trunk/XILINX/BUILD_SCC/synth_src/util.cpp (nonexistent)
+++ trunk/XILINX/BUILD_SCC/synth_src/util.cpp (revision 17)
@@ -0,0 +1,131 @@
+/* util.cpp
+ June 9, 2011
+ Some helper functions.
+
+ Much of the code below is borrowed from Alastair Smith's program
+ from the 2010 FPT Othello competition
+
+ By Kevin Nam
+*/
+
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include "util.h"
+
+#define IA 1103515245u
+#define IC 12345u
+#define IM 2147483648u
+
+using namespace std;
+
+static unsigned int current_random = 0;
+
+
+char select_AI_colour (int argc, char **argv){
+ char ai_colour;
+ int i;
+ //cout<<"Please enter referee AI's colour. L or D"<> ai_colour;
+ for(i=0;i> ai_colour;
+ }
+
+ cout<<"AI is playing as "<> com_port;
+ }
+
+
+ port = open(com_port.c_str(), O_RDWR | O_NOCTTY | O_NONBLOCK);
+ while(port < 0) // if open is unsucessful keep trying until the user specifies a good port
+ {
+ cout << "Unable to open port " << com_port << ", try again, should be: (windows) /dev/comx or (linux) /dev/ttyx ?\n";
+ cin >> com_port;
+ port = open(com_port.c_str(), O_RDWR | O_NOCTTY | O_NONBLOCK);
+ }
+ setup_port(port);
+
+ cout << "COM port has been set up at a baud rate of 115200\n";
+ return port;
+}
+
+void setup_port(int fd) {
+ struct termios options;
+ fcntl(fd, F_SETFL, 0);
+ tcgetattr(fd, &options);
+ cfsetispeed(&options, B115200);
+ cfsetospeed(&options, B115200);
+ options.c_cflag |= (CLOCAL | CREAD);
+ tcsetattr(fd, TCSANOW, &options);
+
+ // set up non-blocking port, so that we can time out
+ int opts;
+ opts = fcntl(fd,F_GETFL);
+ if (opts < 0) {
+ perror("fcntl(F_GETFL)");
+ exit(EXIT_FAILURE);
+ }
+ opts = (opts | O_NONBLOCK);
+ if (fcntl(fd,F_SETFL,opts) < 0) {
+ perror("fcntl(F_SETFL)");
+ exit(EXIT_FAILURE);
+ }
+ return;
+}
+
+int char_to_int (char c){
+ if (c == '0') return 0;
+ else if (c == '1') return 1;
+ else if (c == '2') return 2;
+ else if (c == '3') return 3;
+ else if (c == '4') return 4;
+ else if (c == '5') return 5;
+ else if (c == '6') return 6;
+ else if (c == '7') return 7;
+ else if (c == '8') return 8;
+ else if (c == '9') return 9;
+
+ return 0;
+}
+
+void wait(double seconds){
+ timeval tim;
+ gettimeofday(&tim, NULL);
+ double t1=tim.tv_sec+(tim.tv_usec/1000000.0);
+ while (1){
+ gettimeofday(&tim, NULL);
+ double t2=tim.tv_sec+(tim.tv_usec/1000000.0);
+ if (t2-t1 >= seconds)
+ break;
+ }
+}
+
Index: trunk/XILINX/BUILD_SCC/synth_src/connect6.cpp
===================================================================
--- trunk/XILINX/BUILD_SCC/synth_src/connect6.cpp (nonexistent)
+++ trunk/XILINX/BUILD_SCC/synth_src/connect6.cpp (revision 17)
@@ -0,0 +1,470 @@
+/*
+ connect6.cpp
+ June 9, 2011
+ This file contains the game AI
+ By Kevin Nam
+
+*/
+
+#include
+#include
+
+#include "util.h"
+#include "connect6.h"
+
+// Subtract this many points for moves at the edges.
+#define EDGEPENALTY 5
+
+using namespace std;
+
+/* The cost function simply counts all of the consecutive stones of same colour in
+ every direction from the spot for which the points is being calculated.
+
+ Ex:
+
+ .DDLL
+ .DLDD
+ DXDDD
+ ...D.
+
+ Above, X is the spot being calculated.
+ The points would be 2 (above) + 2(topright) + 3(right) + 1 (left) = 8.
+ It treats opponent's stones and own stones with equal weighting.
+
+ Return 0 if the spot y,x is already taken, else return the calculated value
+
+*/
+int calculatepoints(char board[][19], int y, int x, char colour){
+ int pts = 0, tempx = x, tempy = y, tcount = 0,bcount = 0;
+ int lcount = 0,rcount = 0,trcount = 0,tlcount = 0,brcount = 0,blcount = 0;
+ char tcolour = 0,bcolour = 0,lcolour = 0,rcolour = 0,tlcolour = 0,trcolour = 0,brcolour = 0,blcolour = 0;
+
+ if (board[y][x] != 0)
+ return 0;
+
+ // scan column above
+ if (y > 0){
+ tempy = y-1;
+ tempx = x;
+ tcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != tcolour || board[tempy][tempx] == 0) break;
+ tcount++;
+ if (tempy == 0) break;
+ tempy--;
+ }
+ }
+ // scan column below
+ if (y < 18){
+ tempy = y+1;
+ tempx = x;
+ bcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != bcolour || board[tempy][tempx] == 0) break;
+ bcount++;
+ if (tempy == 18) break;
+ tempy++;
+ }
+ }
+ // scan row to left
+ if (x > 0){
+ tempy = y;
+ tempx = x-1;
+ lcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != lcolour || board[tempy][tempx] == 0) break;
+ lcount++;
+ if (tempx == 0) break;
+ tempx--;
+ }
+ }
+ // scan row to right
+ if (x < 18){
+ tempy = y;
+ tempx = x+1;
+ rcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != rcolour || board[tempy][tempx] == 0) break;
+ rcount++;
+ if (tempx == 18) break;
+ tempx++;
+ }
+ }
+ // scan diagonal topleft
+ if (x > 0 && y > 0){
+ tempy = y-1;
+ tempx = x-1;
+ tlcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != tlcolour || board[tempy][tempx] == 0) break;
+ tlcount++;
+ if (tempx == 0 || tempy == 0) break;
+ tempx--;
+ tempy--;
+ }
+ }
+ // scan diagonal bottomright
+ if (x < 18 && y < 18){
+ tempy = y+1;
+ tempx = x+1;
+ brcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != brcolour || board[tempy][tempx] == 0) break;
+ brcount++;
+ if (tempx == 18 || tempy == 18) break;
+ tempx++;
+ tempy++;
+ }
+ }
+ // scan diagonal topright
+ if (x < 18 && y > 0){
+ tempy = y-1;
+ tempx = x+1;
+ trcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != trcolour || board[tempy][tempx] == 0) break;
+ trcount++;
+ if (tempx == 18 || tempy == 0) break;
+ tempx++;
+ tempy--;
+ }
+ }
+ // scan diagonal bottomleft
+ if (y < 18 && x > 0){
+ tempy = y+1;
+ tempx = x-1;
+ blcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != blcolour || board[tempy][tempx] == 0) break;
+ blcount++;
+ if (tempy == 18 || tempx == 0) break;
+ tempy++;
+ tempx--;
+ }
+ }
+
+ /// Now calculate the points
+ // Check if this is a winning move. Priority #1.
+ if ((tcount >= 5 && tcolour == colour) ||
+ (bcount >= 5 && bcolour == colour) ||
+ (lcount >= 5 && lcolour == colour) ||
+ (rcount >= 5 && rcolour == colour) ||
+ (tlcount >= 5 && tlcolour == colour) ||
+ (trcount >= 5 && trcolour == colour) ||
+ (brcount >= 5 && brcolour == colour) ||
+ (blcount >= 5 && blcolour == colour) ||
+ (tcount + bcount >= 5 && tcolour == colour && bcolour == colour) ||
+ (lcount + rcount >= 5 && lcolour == colour && rcolour == colour) ||
+ (tlcount + brcount >= 5 && tlcolour == colour && brcolour == colour) ||
+ (trcount + blcount >= 5 && trcolour == colour && blcolour == colour))
+ return 1000;
+
+ // Check if this move can stop opponent from winning. This move is priority #2.
+ if ((tcount >= 4 && tcolour != colour) ||
+ (bcount >= 4 && bcolour != colour) ||
+ (lcount >= 4 && lcolour != colour) ||
+ (rcount >= 4 && rcolour != colour) ||
+ (tlcount >= 4 && tlcolour != colour) ||
+ (trcount >= 4 && trcolour != colour) ||
+ (brcount >= 4 && brcolour != colour) ||
+ (blcount >= 4 && blcolour != colour) ||
+ (tcount + bcount >= 4 && tcolour != colour && bcolour != colour) ||
+ (lcount + rcount >= 4 && lcolour != colour && rcolour != colour) ||
+ (tlcount + brcount >= 4 && tlcolour != colour && brcolour != colour) ||
+ (trcount + blcount >= 4 && trcolour != colour && blcolour != colour))
+ return 500;
+
+ // Else sum up the counts, use this as the points.
+ pts = tcount + bcount + lcount + rcount + tlcount + trcount + blcount + brcount + 1;
+ // If at an edge, lower the points
+ if (x == 0 || x == 18 || y == 0 || y == 18){
+ if (pts >= EDGEPENALTY)
+ pts -= EDGEPENALTY;
+ else
+ pts = 0;
+ }
+ return pts;
+}
+
+/*
+ The AI Function that calls the cost function for every spot on the board.
+ It returns the location with the highest points. In the event of a tie, randomly decide.
+ Input the board and the colour being played.
+ Puts the move (in ASCII chars) inside move[4]. This is from [1 ... 19]
+ Puts the move (in integers) in moveY and moveX. This is from [0 ... 18]
+*/
+int connect6ai(char board[][19], char colour, char move[4]){
+ int x,y,highx = 0, highy = 0,currenthigh = 0, temp;
+ srand(time(NULL));
+#ifdef EMUL
+ int highRandom =rand();
+#else
+ int highRandom =1;//rand();
+#endif
+ // Sweep the entire board with the cost function
+ for (x = 0; x <= 18; x++){
+ for (y = 0; y <= 18; y++){
+
+ temp = calculatepoints(board,y,x, colour);
+ if (temp > currenthigh){
+ highx = x;
+ highy = y;
+ currenthigh = temp;
+#ifdef EMUL
+ highRandom =rand();
+#else
+ highRandom =1;//rand();
+#endif
+ }
+ // If a tie happens, pseudo-randomly choose one between them
+ if (temp == currenthigh && temp != 0){
+#ifdef EMUL
+ int tempRandom =rand();
+#else
+ int tempRandom =1;//rand();
+#endif
+ if (tempRandom > highRandom){
+ highx = x;
+ highy = y;
+ highRandom = tempRandom;
+ }
+ }
+ }
+ }
+
+ // Modify the board based on current move.
+ board[highy][highx] = colour;
+
+ // Increment by 1 because indexing starts at 1.
+ highy++;
+ highx++;
+
+ /// Convert the int coordinates to corresponding ASCII chars
+ if (highy >= 10){
+ move[0] = '1';
+ highy -= 10;
+ } else {
+ move[0] = '0';
+ }
+ if (highy == 0) move[1] = '0';
+ else if (highy == 1) move[1] = '1';
+ else if (highy == 2) move[1] = '2';
+ else if (highy == 3) move[1] = '3';
+ else if (highy == 4) move[1] = '4';
+ else if (highy == 5) move[1] = '5';
+ else if (highy == 6) move[1] = '6';
+ else if (highy == 7) move[1] = '7';
+ else if (highy == 8) move[1] = '8';
+ else if (highy == 9) move[1] = '9';
+
+ // Do same for x.
+ if (highx >= 10){
+ move[2] = '1';
+ highx -= 10;
+ } else {
+ move[2] = '0';
+ }
+ if (highx == 0) move[3] = '0';
+ else if (highx == 1) move[3] = '1';
+ else if (highx == 2) move[3] = '2';
+ else if (highx == 3) move[3] = '3';
+ else if (highx == 4) move[3] = '4';
+ else if (highx == 5) move[3] = '5';
+ else if (highx == 6) move[3] = '6';
+ else if (highx == 7) move[3] = '7';
+ else if (highx == 8) move[3] = '8';
+ else if (highx == 9) move[3] = '9';
+
+ return 0;
+}
+
+
+// scan board, return 'L' or 'D' for the winner, 'n' if no winner.
+char check_for_win (char board[][19]){
+ int y,x;
+ for (y = 0; y < 19; y++){
+ for (x = 0; x < 19; x++){
+ if (board[y][x] == 0)
+ continue;
+
+ int tempx, tempy, tcount = 0,bcount = 0;
+ int lcount = 0,rcount = 0,trcount = 0,tlcount = 0,brcount = 0,blcount = 0;
+ char tcolour = 0,bcolour = 0,lcolour = 0,rcolour = 0,tlcolour = 0,trcolour = 0,brcolour = 0,blcolour = 0;
+
+ // scan column above
+ if (y > 0){
+ tempy = y;
+ tempx = x;
+ tcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != tcolour || board[tempy][tempx] == 0) break;
+ tcount++;
+ if (tempy == 0) break;
+ tempy--;
+ }
+ }
+ // scan column below
+ if (y < 18){
+ tempy = y+1;
+ tempx = x;
+ bcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != bcolour || board[tempy][tempx] == 0) break;
+ bcount++;
+ if (tempy == 18) break;
+ tempy++;
+ }
+ }
+
+ if (tcolour == bcolour && tcount + bcount >= 6) return tcolour;
+
+ // scan row to left
+ if (x > 0){
+ tempy = y;
+ tempx = x;
+ lcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != lcolour || board[tempy][tempx] == 0) break;
+ lcount++;
+ if (tempx == 0) break;
+ tempx--;
+ }
+ }
+ // scan row to right
+ if (x < 18){
+ tempy = y;
+ tempx = x+1;
+ rcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != rcolour || board[tempy][tempx] == 0) break;
+ rcount++;
+ if (tempx == 18) break;
+ tempx++;
+ }
+ }
+
+ if (lcolour == rcolour && lcount + rcount >= 6) return lcolour;
+
+ // scan diagonal topleft
+ if (x > 0 && y > 0){
+ tempy = y;
+ tempx = x;
+ tlcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != tlcolour || board[tempy][tempx] == 0) break;
+ tlcount++;
+ if (tempx == 0 || tempy == 0) break;
+ tempx--;
+ tempy--;
+ }
+ }
+ // scan diagonal bottomright
+ if (x < 18 && y < 18){
+ tempy = y+1;
+ tempx = x+1;
+ brcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != brcolour || board[tempy][tempx] == 0) break;
+ brcount++;
+ if (tempx == 18 || tempy == 18) break;
+ tempx++;
+ tempy++;
+ }
+ }
+
+ if (tlcolour == brcolour && tlcount + brcount >= 6) return tlcolour;
+
+ // scan diagonal topright
+ if (x < 18 && y > 0){
+ tempy = y;
+ tempx = x;
+ trcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != trcolour || board[tempy][tempx] == 0) break;
+ trcount++;
+ if (tempx == 18 || tempy == 0) break;
+ tempx++;
+ tempy--;
+ }
+ }
+ // scan diagonal bottomleft
+ if (y < 18 && x > 0){
+ tempy = y+1;
+ tempx = x-1;
+ blcolour = board[tempy][tempx];
+ while (1){
+ if (board[tempy][tempx] != blcolour || board[tempy][tempx] == 0) break;
+ blcount++;
+ if (tempy == 18 || tempx == 0) break;
+ tempy++;
+ tempx--;
+ }
+ }
+
+ if (trcolour == blcolour && trcount + blcount >= 6) return trcolour;
+ }
+ }
+ // return 'n' for no victory
+ return 'n';
+}
+
+// Check if the board is full
+int check_board_full (char board[][19]){
+ int y,x;
+ // As soon as there is an empty intersection, return 0;
+ for (y = 0; y < 19; y++)
+ for (x = 0; x < 19; x++)
+ if (board[y][x] == 0)
+ return 0;
+
+ // By now, swept entire board and all filled.
+ return -1;
+}
+
+// Check if move y,x is valid. Here, y and x are [0 ... 18]
+int check_move_validity (char board[][19],int y, int x){
+ if (y < 0 || y > 18 || x < 0 || x > 18 || board[y][x] != 0){
+ return -1;
+ }
+ return 0;
+}
+
+
+void print_board (char board[][19]){
+ printf(" 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9");
+ unsigned short x,y;
+ for (x = 0; x <= 18; x++){
+ printf("\n");
+ printf("%d",x+1);
+ if (x < 9) printf(" ");
+ for (y = 0; y <= 18; y++){
+ if (board[x][y] == 0)
+ printf(".");
+ else printf("%c",board[x][y]);
+ printf(" ");
+ }
+
+ }
+ printf("\n");
+}
+
+void print_board_file (char board[][19]){
+char filename[12]="myboard.txt";
+FILE *fp=fopen(filename,"w");
+ fprintf(fp," 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9");
+ unsigned short x,y;
+ for (x = 0; x <= 18; x++){
+ fprintf(fp,"\n");
+ fprintf(fp,"%d",x+1);
+ if (x < 9) fprintf(fp," ");
+ for (y = 0; y <= 18; y++){
+ if (board[x][y] == 0)
+ fprintf(fp,".");
+ else fprintf(fp,"%c",board[x][y]);
+ fprintf(fp," ");
+ }
+
+ }
+ fprintf(fp,"\n");
+fclose(fp);
+}
Index: trunk/XILINX/BUILD_SCC/synth_src/threats.h
===================================================================
--- trunk/XILINX/BUILD_SCC/synth_src/threats.h (nonexistent)
+++ trunk/XILINX/BUILD_SCC/synth_src/threats.h (revision 17)
@@ -0,0 +1,30 @@
+
+
+
+
+typedef int PIECE;
+
+typedef struct Board {
+ AllocChain ac;
+ /* Allocation chain must be the first member */
+
+ unsigned int moves_left;
+ /* How many moves the current player has left */
+
+ struct Board *parent;
+ /* The board preceeding this one in history */
+
+ gboolean won;
+ BCOORD win_x1, win_y1, win_x2, win_y2;
+ /* On won boards, used to indicate where the winning line is */
+
+ PIECE turn;
+ /* Whose turn it is on this board */
+
+ BCOORD move_x, move_y;
+ /* The move to the next Board in history */
+
+ PIECE data[];
+} Board;
+/* The board structure represents the state of the game board. Do NOT preserve
+ board pointers across games. */
Index: trunk/XILINX/BUILD_SCC/synth_src/state.cpp
===================================================================
--- trunk/XILINX/BUILD_SCC/synth_src/state.cpp (nonexistent)
+++ trunk/XILINX/BUILD_SCC/synth_src/state.cpp (revision 17)
@@ -0,0 +1,767 @@
+
+/*
+
+connectk -- a program to play the connect-k family of games
+Copyright (C) 2007 Michael Levin
+
+This program is free software; you can redistribute it and/or
+modify it under the terms of the GNU General Public License
+as published by the Free Software Foundation; either version 2
+of the License, or (at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+//#include "config.h"
+//#include
+//#include
+//#include
+//#include
+//#include
+//#include
+#include "./shared.h"
+//#include "connectk.h"
+
+/*
+ * Allocation chain
+ */
+
+#define IA 1103515245u
+#define IC 12345u
+#define IM 2147483648u
+#define CHECK_RAND
+//moved the following declaration to connect6_threat
+//static unsigned int current_random = 0;
+
+//from vpr uti.c code
+/* Portable random number generator defined below. Taken from ANSI C by *
+ * K & R. Not a great generator, but fast, and good enough for my needs. */
+
+
+void my_srandom(int seed,unsigned int *current_random)
+{
+ *current_random = (unsigned int)seed;
+}
+
+
+int my_irand(int imax,unsigned int current_random)
+{
+
+///* Creates a random integer between 0 and imax, inclusive. i.e. [0..imax] */
+//
+// int ival;
+//
+///* current_random = (current_random * IA + IC) % IM; */
+// current_random = current_random * IA + IC; /* Use overflow to wrap */
+// ival = current_random & (IM - 1); /* Modulus */
+// //float not synthesizable
+// //ival = (int)((float)ival * (float)(imax + 0.999) / (float)IM);
+// ival = (int)(ival * (imax + 1) / IM);
+//
+//#ifdef CHECK_RAND
+// if((ival < 0) || (ival > imax))
+// {
+// //printf("Bad value in my_irand, imax = %d ival = %d\n", imax,
+// // ival);
+// //exit(1);
+// }
+//#endif
+//
+// return (ival);
+return(0);
+}
+
+
+//static void achain_init(AllocChain *ac)
+//{
+// static unsigned int ids;
+//
+// ac->free = FALSE;
+// ac->id = ids++;
+//}
+//
+//AllocChain *achain_new(AllocChain **root, AllocFunc afunc)
+//{
+// AllocChain *ac;
+//
+// if (!*root) {
+// *root = afunc(NULL);
+// achain_init(*root);
+// (*root)->next = NULL;
+// return *root;
+// }
+// ac = *root;
+// for (;;) {
+// if (ac->free) {
+// afunc(ac);
+// achain_init(ac);
+// return ac;
+// }
+// if (!ac->next)
+// break;
+// ac = ac->next;
+// }
+// ac->next = afunc(NULL);
+// achain_init(ac->next);
+// ac->next->next = NULL;
+// return ac->next;
+//}
+//
+//void achain_free(AllocChain *ac)
+//{
+// if (!ac)
+// return;
+// ac->free = TRUE;
+//}
+//
+//void achain_copy(const AllocChain *src, AllocChain *dest, gsize mem)
+//{
+// if (!src || !dest || !mem) {
+// g_warning("NULL argument(s) to achain_copy");
+// return;
+// }
+// memcpy((char*)dest + sizeof (AllocChain),
+// (char*)src + sizeof (AllocChain), mem - sizeof (AllocChain));
+//}
+//
+//static void achain_dealloc(AllocChain **root, gsize mem)
+//{
+// AllocChain *ac = *root, *ac_next;
+//
+// while (ac) {
+// ac_next = ac->next;
+// g_slice_free1(mem, ac);
+// ac = ac_next;
+// }
+// *root = NULL;
+//}
+
+
+// Move Arrays
+
+
+//AllocChain *aimoves_root = NULL;
+gsize aimoves_mem = 0;
+
+//AllocChain *aimoves_alloc(AllocChain *ac)
+//{
+// //if (!ac)
+// // ac = (AllocChain*)g_slice_alloc(aimoves_mem);
+// //memset((char*)ac + sizeof (AllocChain), 0, sizeof (AIMoves) -
+// // sizeof (AllocChain));
+// //return ac;
+//}
+
+void aimoves_add(AIMoves *moves, const AIMove *move)
+{
+ int i;
+
+ i = aimoves_find(moves, move->x, move->y);
+ if (i < 0) {
+ if (moves->len >= board_size * board_size)
+ //g_warning("Attempted to add a move to a full AIMoves");
+ //printf("Attempted to add a move to a full AIMoves");
+ return;
+ else
+ moves->data[moves->len++] = *move;
+ } else
+ moves->data[i].weight += move->weight;
+}
+
+void aimoves_append(AIMoves *moves, const AIMove *move)
+{
+ int i;
+
+ if (move->x >= board_size || move->y >= board_size)
+ return;
+ for (i = 0; i < moves->len; i++) {
+ AIMove *aim = moves->data + i;
+
+ if (aim->x == move->x && aim->y == move->y) {
+ aim->weight = move->weight;
+ return;
+ }
+ }
+ if (moves->len >= board_size * board_size) {
+ //g_warning("Attempted to append a move to a full AIMoves");
+ //printf("Attempted to append a move to a full AIMoves");
+ return;
+ }
+ moves->data[moves->len++] = *move;
+}
+
+int aimoves_compare(const void *a, const void *b)
+{
+ return ((AIMove*)b)->weight - ((AIMove*)a)->weight;
+}
+
+int aimoves_choose(AIMoves *moves, AIMove *move)
+{
+ //#pragma read_write_ports moves.data combined 3
+ //#pragma internal_blockram moves
+ //#pragma no_memory_analysis moves
+ int i = 0, top = 0;
+ #pragma bitsize i 4
+ if (!moves || !moves->len)
+ return 0;
+ aimoves_sort(moves);
+ for (top = 0; top < moves->len &&
+ moves->data[top].weight == moves->data[0].weight; top++);
+ if (top)
+ //i = my_irand(top,current_random);//g_random_int_range(0, top);
+ i=0;
+
+ *move = moves->data[i];
+ return 1;
+}
+//
+//void aimoves_crop(AIMoves *moves, unsigned int n)
+//{
+// if (moves->len < n)
+// return;
+// aimoves_shuffle(moves);
+// aimoves_sort(moves);
+// moves->len = n;
+//}
+//
+//void aimoves_concat(AIMoves *m1, const AIMoves *m2)
+//{
+// gsize max_len = board_size * board_size, len;
+//
+// len = m2->len;
+// if (m1->len + len > max_len)
+// len = max_len - m1->len;
+// memcpy(m1->data + len, m2->data, len * sizeof (AIMove));
+// m1->len += len;
+//}
+//
+//AIMoves *aimoves_dup(const AIMoves *moves)
+//{
+// AIMoves *dup;
+//
+// if (!moves)
+// return NULL;
+// dup = aimoves_new();
+// dup->len = moves->len;
+// memcpy(dup->data, moves->data, moves->len * sizeof (AIMove));
+// return dup;
+//}
+//
+int aimoves_find(const AIMoves *moves, BCOORD x, BCOORD y)
+{
+ int i;
+
+ if (moves)
+ for (i = 0; i < moves->len; i++) {
+ const AIMove *aim = moves->data + i;
+
+ if (aim->x == x && aim->y == y)
+ return i;
+ }
+ return -1;
+}
+//
+//void aimoves_range(AIMoves *moves, AIWEIGHT *min, AIWEIGHT *max)
+//{
+// int i;
+//
+// *min = AIW_MAX;
+// *max = AIW_MIN;
+// for (i = 0; i < moves->len; i++) {
+// if (moves->data[i].weight > *max)
+// *max = moves->data[i].weight;
+// if (moves->data[i].weight < *min)
+// *min = moves->data[i].weight;
+// }
+//}
+//
+//void aimoves_merge(AIMoves *m1, const AIMoves *m2)
+//{
+// int len = m1->len, i, j;
+//
+// for (i = 0; i < m2->len; i++)
+// for (j = 0;; j++) {
+// if (j >= len) {
+// aimoves_append(m1, m2->data + i);
+// break;
+// }
+// if (m1->data[j].x == m2->data[i].x &&
+// m1->data[j].y == m2->data[i].y) {
+// if (m2->data[i].weight > m1->data[j].weight)
+// m1->data[j].weight = m2->data[i].weight;
+// break;
+// }
+// }
+//}
+//
+//char *aimove_to_string(const AIMove *aim)
+//{
+// static char buffer[32];
+//
+// g_snprintf(buffer, sizeof (buffer), "%s (%s)",
+// bcoords_to_string(aim->x, aim->y),
+// aiw_to_string(aim->weight));
+// return buffer;
+//}
+//
+//void aimoves_print(const AIMoves *moves)
+//{
+// int i;
+//
+// if (!moves || !moves->len) {
+// g_print("(empty)");
+// return;
+// }
+// for (i = 0; i < moves->len; i++) {
+// const AIMove *aim = moves->data + i;
+//
+// if (i)
+// g_print(", ");
+// g_print("%s", aimove_to_string(aim));
+// }
+//}
+//
+//void aimoves_remove_index_fast(AIMoves *moves, int i)
+//{
+// if (moves->len > i)
+// moves->data[i] = moves->data[moves->len - 1];
+// moves->len--;
+//}
+//
+//void aimoves_remove(AIMoves *moves, BCOORD x, BCOORD y)
+//{
+// int i;
+//
+// for (i = 0; i < moves->len; i++) {
+// AIMove *aim = moves->data + i;
+//
+// if (aim->x == x && aim->y == y) {
+// aimoves_remove_index_fast(moves, i);
+// return;
+// }
+// }
+//}
+//
+void aimoves_shuffle(AIMoves *moves,unsigned int current_random)
+{
+// int i;
+//
+// if (opt_det_ai)
+// return;
+//
+// /* Fisher-Yates shuffle */
+// for (i = 0; i < moves->len; i++) {
+// int j;
+//
+// j = my_irand(moves->len,current_random);//g_random_int_range(i, moves->len);
+// if (i != j) {
+// AIMove tmp;
+//
+// tmp = moves->data[i];
+// moves->data[i] = moves->data[j];
+// moves->data[j] = tmp;
+// }
+// }
+return;
+}
+
+
+//taken from http://cprogramminglanguage.net/c-bubble-sort-source-code.aspx
+void swap(AIMove *x,AIMove *y)
+{
+ AIMove temp;
+ temp = *x;
+ *x = *y;
+ *y = temp;
+}
+void bublesort(AIMove *list, int n)
+{
+ int i,j;
+ for(i=0;i<(n-1);i++)
+ for(j=0;j<(n-(i+1));j++)
+ if(list[j].weight < list[j+1].weight)
+ swap(&list[j],&list[j+1]);
+}
+//taken from http://cprogramminglanguage.net/c-bubble-sort-source-code.aspx
+void aimoves_sort(AIMoves *moves)
+{
+ //qsort(moves->data, moves->len, sizeof (AIMove), aimoves_compare);
+ bublesort(moves->data,moves->len);
+
+}
+
+//void aimoves_subtract(AIMoves *m1, const AIMoves *m2)
+//{
+// int i, j;
+//
+// for (i = 0; i < m1->len; i++)
+// for (j = 0; j < m2->len; j++)
+// if (m1->data[i].x == m2->data[j].x &&
+// m1->data[i].y == m2->data[j].y) {
+// aimoves_remove_index_fast(m1, i--);
+// break;
+// }
+//}
+//
+//const char *aiw_to_string(AIWEIGHT w)
+//{
+// static char buffer[32];
+//
+// switch (w) {
+// case AIW_WIN:
+// return "WIN";
+// case AIW_LOSE:
+// return "LOSS";
+// case AIW_NONE:
+// return "NONE";
+// default:
+// break;
+// }
+// if (w > 0)
+// g_snprintf(buffer, sizeof (buffer), "%010d (10^%.2f)", w,
+// log10((double)w));
+// else if (w < 0)
+// g_snprintf(buffer, sizeof (buffer), "%010d (-10^%.2f)", w,
+// log10((double)-w));
+// return buffer;
+//}
+
+/*
+ * Boards
+ */
+
+//Board board;
+//AllocChain *board_root = NULL;
+//int board_size=19, board_stride=21, move_no, move_last,
+// connect_k = 6, place_p = 2, start_q = 1;
+//int opt_det_ai=1;
+//gsize board_mem = 0;
+
+//Player players[PIECES] = {
+// { PLAYER_HUMAN, SEARCH_NONE, 0 },
+// { PLAYER_HUMAN, SEARCH_NONE, 0 },
+// { PLAYER_HUMAN, SEARCH_NONE, 0 },
+//};
+//
+//static GPtrArray *history = NULL;
+
+static void board_init(Board *b)
+{
+// memset((char*)b + sizeof (AllocChain), 0, sizeof (Board) -
+// sizeof (AllocChain));
+int i,j;
+for(i=0;idata[i][0]=PIECE_ERROR;
+for(i=0;idata[i][board_stride-1]=PIECE_ERROR;
+for(j=0;jdata[0][j]=PIECE_ERROR;
+for(j=0;jdata[board_stride-1][j]=PIECE_ERROR;
+for(i=1;idata[i][j]=PIECE_NONE;
+
+ //b->ac=(const AllocChain )0;
+ b->moves_left=0;
+ b->parent =0;
+ b->won =0;
+ b->win_x1 =0;
+ b->win_y1 =0;
+ b->win_x2 =0;
+ b->win_y2 =0;
+ b->turn =0;
+ b->move_x =0;
+ b->move_y =0;
+}
+
+//AllocChain *board_alloc(AllocChain *ac)
+//{
+// //Board *b = (Board*)ac;
+// //int i;
+//
+// ///* Clear the old board */
+// //if (b) {
+// // for (i = 1; i <= board_size; i++)
+// // memset(b->data + board_stride * i + 1, 0,
+// // board_size * sizeof (PIECE));
+// // board_init(b);
+// // return (AllocChain*)b;
+// //}
+//
+// ///* New boards are allocated with a 1-tile wide boundary of PIECE_ERROR
+// // around the edges */
+// //b = (Board*)g_slice_alloc0(board_mem);
+// //memset(b->data, PIECE_ERROR, sizeof (PIECE) * board_stride);
+// //for (i = 1; i <= board_size; i++) {
+// // b->data[i * board_stride] = PIECE_ERROR;
+// // memset(b->data + board_stride * i + 1, 0,
+// // board_size * sizeof (PIECE));
+// // b->data[(i + 1) * board_stride - 1] = PIECE_ERROR;
+// //}
+// //memset(b->data + board_stride * (board_stride - 1), PIECE_ERROR,
+// // sizeof (PIECE) * board_stride);
+// //board_init(&b);
+// //return (AllocChain*)b;
+//}
+
+void board_clean(Board *b)
+{
+ int y, x;
+
+ for (y = 0; y < board_size; y++)
+ for (x = 0; x < board_size; x++)
+ if (piece_at(b, x, y) >= PIECES)
+ place_piece_type(b, x, y, PIECE_NONE);
+}
+
+//void set_board_size(unsigned int size)
+//{
+// //if (board_size == size)
+// // return;
+// ////draw_marks(NULL, FALSE);
+// //achain_dealloc(&board_root, board_mem);
+// achain_dealloc(&aimoves_root, aimoves_mem);
+// //board_size = size;
+// //board_stride = size + 2;
+// //board_mem = sizeof (Board) + board_stride * board_stride *
+// // sizeof (PIECE);
+// aimoves_mem = sizeof (AIMoves) + size * size * sizeof (AIMove);
+//}
+
+//Board *board_at(unsigned int move)
+//{
+// if (move >= history->len)
+// return NULL;
+// return (Board*)g_ptr_array_index(history, move);
+//}
+
+int count_pieces(const Board *b, BCOORD x, BCOORD y, PIECE type, int dx, int dy,
+ PIECE *out)
+{
+ int i;
+ PIECE p = PIECE_NONE;
+
+ if (!dx && !dy)
+ return piece_at(b, x, y) == type ? 1 : 0;
+ for (i = 0; x >= 0 && x < board_size && y >= 0 && y < board_size; i++) {
+ p = piece_at(b, x, y);
+ if (p != type)
+ break;
+ x += dx;
+ y += dy;
+ }
+ if (out)
+ *out = p;
+ return i;
+}
+
+gboolean check_win_full(const Board *b, BCOORD x, BCOORD y,
+ BCOORD *x1, BCOORD *y1, BCOORD *x2, BCOORD *y2)
+{
+ int i, c1, c2, xs[] = {1, 1, 0, -1}, ys[] = {0, 1, 1, 1};
+ PIECE type;
+
+ type = piece_at(b, x, y);
+ if (type != PIECE_BLACK && type != PIECE_WHITE)
+ return FALSE;
+ for (i = 0; i < 4; i++) {
+ c1 = count_pieces(b, x, y, type, xs[i], ys[i], 0);
+ c2 = count_pieces(b, x, y, type, -xs[i], -ys[i], 0);
+ if (c1 + c2 > connect_k) {
+ if (x1)
+ *x1 = x + xs[i] * (c1 - 1);
+ if (y1)
+ *y1 = y + ys[i] * (c1 - 1);
+ if (x2)
+ *x2 = x - xs[i] * (c2 - 1);
+ if (y2)
+ *y2 = y - ys[i] * (c2 - 1);
+ return TRUE;
+ }
+ }
+ return FALSE;
+}
+
+///* Convert a boord coordinate to alpha representation */
+//const char *bcoord_to_alpha(BCOORD x)
+//{
+// static char buf[2][32];
+// static int which;
+// int i, divisor = 26;
+//
+// which = !which;
+// for (i = 0; i < sizeof (buf[which]) - 1; i++) {
+// div_t result;
+//
+// result = div(x, divisor);
+// buf[which][i] = 'a' + result.rem * 26 / divisor;
+// if (i)
+// buf[which][i]--;
+// x -= result.rem;
+// if (!x)
+// break;
+// divisor *= 26;
+// }
+// buf[which][i + 1] = 0;
+// return g_strreverse(buf[which]);
+//}
+
+//// Get a string representation of board x/y coordinates (d7, h16, etc)
+//const char *bcoords_to_string(BCOORD x, BCOORD y)
+//{
+// static char buf[2][32];
+// static int which;
+//
+// which = !which;
+// g_snprintf(buf[which], sizeof (buf[which]), "%s%d",
+// bcoord_to_alpha(x), board_size - y);
+// return buf[which];
+//}
+//
+/* Convert a string representation to coordinates */
+void string_to_bcoords(const char *str, BCOORD *x, BCOORD *y)
+{
+ *x = 0;
+ *y = 0;
+ while (*str && *str >= 'a' && *str <= 'z') {
+ *x *= 26;
+ *x += *str - 'a';
+ str++;
+ }
+ while (*str && *str >= '0' && *str <= '9') {
+ *y *= 10;
+ *y += *str - '0';
+ str++;
+ }
+ if (*y)
+ *y = board_size - *y;
+}
+
+const char *piece_to_string(PIECE piece)
+{
+ switch (piece) {
+ case PIECE_WHITE:
+ return "White";
+ case PIECE_BLACK:
+ return "Black";
+ case PIECE_NONE:
+ return "None";
+ case PIECE_ERROR:
+ return "Error";
+ default:
+ return "Mark";
+ }
+}
+
+char piece_to_char(PIECE piece)
+{
+ switch (piece) {
+ case PIECE_WHITE:
+ return 'W';
+ case PIECE_BLACK:
+ return 'B';
+ case PIECE_NONE:
+ return '_';
+ case PIECE_ERROR:
+ return 'E';
+ default:
+ return 'M';
+ }
+}
+
+//char *search_to_string(SEARCH s)
+//{
+// switch (s) {
+// case SEARCH_NONE:
+// return "No search";
+// case SEARCH_DFS:
+// return "Depth first search";
+// case SEARCHES:
+// break;
+// }
+// return "Unknown";
+//}
+
+//void go_to_move(unsigned int move)
+//{
+// Board board2;
+//
+// if (!history)
+// history = g_ptr_array_sized_new(32);
+// if (move > history->len)
+// move = history->len;
+// if (move == history->len) {
+// //board2 = board_new();
+// if (&board)
+// board_copy(&board, &board2);
+// g_ptr_array_add(history, &board2);
+// board2.parent = &board;
+// } else
+// //board2 = (Board*)g_ptr_array_index(history, move);
+// //&board = &board2;
+// move_no = move;
+// if (move_no > move_last)
+// move_last = move_no;
+//}
+
+//void clear_history(unsigned int from)
+//{
+// int i;
+//
+// if (!history)
+// return;
+// if (from >= history->len) {
+// g_warning("Attempted to clear future history");
+// return;
+// }
+// for (i = from; i < history->len; i++)
+// board_free(g_ptr_array_index(history, i));
+// g_ptr_array_remove_range(history, from, history->len - from);
+// move_last = from;
+//}
+/* Clear the board and history for a new game */
+void new_game(Board *board,unsigned int size)
+{
+ //tree_view_clear(1);
+ //clear_history(0);
+ //set_board_size(size);
+ //board = NULL;
+ //go_to_move(0);
+ //move_last=0;
+ //move_no=0;
+ board_init(board);
+ board->moves_left = start_q;
+ board->turn = PIECE_BLACK;
+ //draw_board();
+ //stop_ai();
+ //setup_move();
+}
+void board_copy(const Board *from, Board *to){
+int i,j;
+for(i=0;idata[i][j]=from->data[i][j];
+
+ to->ac= from->ac;
+ to->moves_left= from->moves_left;
+ to->parent = from->parent;
+ to->won = from->won;
+ to->win_x1 = from->win_x1;
+ to->win_y1 = from->win_y1;
+ to->win_x2 = from->win_x2;
+ to->win_y2 = from->win_y2;
+ to->turn = from->turn;
+ to->move_x = from->move_x;
+ to->move_y = from->move_y;
+
+
+}
trunk/XILINX/BUILD_SCC/synth_src/state.cpp
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC/synth_src/util.h
===================================================================
--- trunk/XILINX/BUILD_SCC/synth_src/util.h (nonexistent)
+++ trunk/XILINX/BUILD_SCC/synth_src/util.h (revision 17)
@@ -0,0 +1,34 @@
+/* util.cpp
+ June 9, 2011
+ Some helper functions.
+
+ Much of the code below is borrowed from Alastair Smith's program
+ from the 2010 FPT Othello competition
+
+ By Kevin Nam
+*/
+
+#ifndef _UTILS_H
+#define _UTILS_H
+
+using namespace std;
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+//#include "commondefs.h"
+
+/*********************** Portable random number generators *******************/
+
+void setup_port(int fd);
+int select_com_port(int argc, char **argv);
+char select_AI_colour (int argc, char **argv);
+int char_to_int (char c);
+void wait(double seconds);
+#endif
Index: trunk/XILINX/BUILD_SCC/synth_src/connect6.h
===================================================================
--- trunk/XILINX/BUILD_SCC/synth_src/connect6.h (nonexistent)
+++ trunk/XILINX/BUILD_SCC/synth_src/connect6.h (revision 17)
@@ -0,0 +1,19 @@
+/*
+ connect6.h
+ June 9, 2011
+ This file contains the game AI
+ By Kevin Nam
+
+*/
+
+#ifndef _CONNECT6_H
+#define _CONNECT6_H
+
+int calculatepoints(char board[][19], int y, int x, char colour);
+int connect6ai(char board[][19], char colour, char move[4]);
+char check_for_win (char board[][19]);
+int check_board_full (char board[][19]);
+int check_move_validity (char board[][19],int y, int x);
+void print_board (char board[][19]);
+void print_board_file (char board[][19]);
+#endif
Index: trunk/XILINX/BUILD_SCC/synth_src/main.cpp
===================================================================
--- trunk/XILINX/BUILD_SCC/synth_src/main.cpp (nonexistent)
+++ trunk/XILINX/BUILD_SCC/synth_src/main.cpp (revision 17)
@@ -0,0 +1,332 @@
+/* main.cpp
+ June 9,2011
+
+ Software connect6 AI program.
+ Have your board polling for its colour before starting this program.
+
+ commandline option:
+ -port
+ Ex: "./connect6 -port /dev/ttyUSB0"
+
+ By: Kevin Nam
+*/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "util.h"
+#include "connect6.h"
+#include "connect6_synth.h"
+#ifndef EMUL
+#include "pico.h"
+#endif
+#include "shared.h"
+
+#ifndef EMUL
+// The AI has as much time as it wants, but moves after 1 second. Default is to wait 2 seconds
+#define AI_WAIT_TIME 0.1
+
+// FPGA has 1 second to make its move
+#define MOVE_TIME_LIMIT 0.1
+#endif
+
+#ifdef EMUL
+// The AI has as much time as it wants, but moves after 1 second. Default is to wait 2 seconds
+#define AI_WAIT_TIME 0.1
+
+// FPGA has 1 second to make its move
+#define MOVE_TIME_LIMIT 1
+#endif
+using namespace std;
+extern "C" int main(int argc, char **argv);
+// commandline option: -port
+int main(int argc, char **argv){
+ //for verification two runs and a reference board
+ int i,j,k;
+ char ref_board[19][19] = {{ 0 }};
+
+ char board[19][19] = {{ 0 }};
+ char move[4];
+ char moveport[8]={0};
+ char moveportout[8]={0};
+ int movecount=0;
+ int y,x;
+ char winning_colour;
+
+#ifdef EMUL
+ // Get the serial port
+ int port = select_com_port(argc,argv);
+#endif
+ // Get software AI's colour
+ char AI_colour = select_AI_colour(argc,argv);
+ char FPGA_colour;
+#ifndef EMUL
+ int id = PICO_initialize_PPA(connect6ai_synth);
+#endif
+ // Take care of the first few moves (including sending the colour)
+ if (AI_colour == 'D'){
+ FPGA_colour = 'L';
+#ifdef EMUL
+ write(port, "L",1);
+#endif
+
+ wait(AI_WAIT_TIME);
+
+ // AI makes a move
+ connect6ai(board,AI_colour,move);
+ movecount++;
+ cout<<"AI MOVE: "<=20) return 0 ; //reducing length of simulation
+ winning_colour = check_for_win(board);
+ if (winning_colour == AI_colour){
+ cout<<"AI has won! " << movecount << " moves " << "Exiting."<
+#include
+#include
+#include "../shared.h"
+#include "../connectk.h"
+
+/*
+ * AIs
+ */
+
+static AI ais[] = {
+ { "human", "Human", NULL },
+ { "random", "Random", ai_random },
+ { "adjacent", "Adjacent", ai_adjacent },
+ { "threats", "Threats", ai_threats },
+ /*{ "windows", "Windows", ai_windows },*/
+ /*{ "priority", "Prioritized Threats", ai_priority },*/
+ { "sequences", "Sequences", ai_sequences },
+ { "mesh", "Mesh", ai_mesh },
+ { "montecarlo", "Monte Carlo", ai_monte_carlo },
+};
+
+static gboolean is_adjacent(const Board *b, BCOORD x, BCOORD y, int dist)
+{
+ int dx, dy, count;
+ PIECE p;
+
+ if (!piece_empty(piece_at(b, x, y)))
+ return FALSE;
+ for (dy = -1; dy < 2; dy++)
+ for (dx = -1; dx < 2; dx++) {
+ if (!dx && !dy)
+ continue;
+ count = count_pieces(b, x, y, PIECE_NONE, dx, dy, &p);
+ if (count - 1 < dist && p != PIECE_NONE)
+ return TRUE;
+ }
+ return FALSE;
+}
+
+AIMoves *enum_adjacent(const Board *b, int dist)
+{
+ AIMoves *moves;
+ AIMove move;
+
+ move.weight = AIW_NONE;
+ moves = aimoves_new();
+ for (move.y = 0; move.y < board_size; move.y++)
+ for (move.x = 0; move.x < board_size; move.x++)
+ if (is_adjacent(b, move.x, move.y, dist))
+ aimoves_append(moves, &move);
+ aimoves_shuffle(moves);
+ return moves;
+}
+
+AIMoves *ai_marks(const Board *b, PIECE min)
+{
+ AIMoves *moves = aimoves_new();
+ AIMove move;
+ PIECE p;
+
+ for (move.y = 0; move.y < board_size; move.y++)
+ for (move.x = 0; move.x < board_size; move.x++)
+ if ((p = piece_at(b, move.x, move.y)) >= min) {
+ move.weight = p - PIECE_THREAT0;
+ aimoves_set(moves, &move);
+ }
+ return moves;
+}
+
+AIMoves *ai_random(const Board *b)
+/* Returns a list of all empty tiles */
+{
+ AIMove move;
+ AIMoves *moves;
+
+ moves = aimoves_new();
+ for (move.y = 0; move.y < board_size; move.y++)
+ for (move.x = 0; move.x < board_size; move.x++)
+ if (piece_empty(piece_at(b, move.x, move.y))) {
+ move.weight =
+ g_random_int_range(AIW_MIN, AIW_MAX);
+ aimoves_append(moves, &move);
+ }
+ return moves;
+}
+
+AIMoves *ai_adjacent(const Board *b)
+{
+ AIMove move;
+ AIMoves *moves;
+
+ /* Get all open tiles adjacent to any piece */
+ moves = enum_adjacent(b, 1);
+ if (moves->len)
+ return moves;
+
+ /* Play in the middle if there are no open adjacent tiles */
+ move.x = board_size / 2;
+ move.y = board_size / 2;
+ move.weight = AIW_NONE;
+ aimoves_append(moves, &move);
+ return moves;
+}
+
+const char *player_to_string(PLAYER p)
+{
+ return ais[p].l_desc;
+}
+
+int number_of_ais(void)
+{
+ return sizeof (ais) / sizeof (*ais);
+}
+
+AI *ai(int n)
+{
+ if (n >= 0 && n < number_of_ais())
+ return ais + n;
+ return NULL;
+}
+
trunk/XILINX/BUILD_SCC/synth_src/ai.c
Property changes :
Added: svn:executable
Index: trunk/XILINX/BUILD_SCC/synth_src/main.cpp.base
===================================================================
--- trunk/XILINX/BUILD_SCC/synth_src/main.cpp.base (nonexistent)
+++ trunk/XILINX/BUILD_SCC/synth_src/main.cpp.base (revision 17)
@@ -0,0 +1,276 @@
+/* main.cpp
+ June 9,2011
+
+ Software connect6 AI program.
+ Have your board polling for its colour before starting this program.
+
+ commandline option:
+ -port
+ Ex: "./connect6 -port /dev/ttyUSB0"
+
+ By: Kevin Nam
+*/
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "util.h"
+#include "connect6.h"
+#include "connect6_synth.h"
+//#include "pico.h"
+//#include "shared.h"
+
+// The AI has as much time as it wants, but moves after 1 second. Default is to wait 2 seconds
+#define AI_WAIT_TIME 0.1
+
+// FPGA has 1 second to make its move
+#define MOVE_TIME_LIMIT 0.1
+
+using namespace std;
+
+// commandline option: -port
+int main(int argc, char **argv){
+ //for verification two runs and a reference board
+ int i,j,k;
+ char ref_board[19][19] = {{ 0 }};
+
+ char board[19][19] = {{ 0 }};
+ char move[4];
+ char moveport[8]={0};
+ char moveportout[8]={0};
+ int movecount=0;
+ int y,x;
+ char winning_colour;
+
+ // Get the serial port
+ //int port = select_com_port(argc,argv);
+ // Get software AI's colour
+ char AI_colour = select_AI_colour(argc,argv);
+ char FPGA_colour;
+ //int id = PICO_initialize_PPA(\TCAB_NAME);
+ // Take care of the first few moves (including sending the colour)
+ if (AI_colour == 'D'){
+ FPGA_colour = 'L';
+ //write(port, "L",1);
+
+ wait(AI_WAIT_TIME);
+
+ // AI makes a move
+ connect6ai(board,AI_colour,move);
+ movecount++;
+ cout<<"AI MOVE: "<main.cpp
+ cp ${SYNTH_SRC}/main.cpp.base ${SYNTH_SRC}/main.cpp
+ ${SCC} ${SCC_SCRIPTS}/run_imp_window.tcl
+ echo "Done" > imp_window.tag
+imp_line.tag: imp_window.tag
+ sed -s 's/\\TCAB_NAME/threat_line/g' ${SYNTH_SRC}/main.cpp.base >${SYNTH_SRC}/main.cpp
+ #cp ${SYNTH_SRC}/main.cpp.base ${SYNTH_SRC}/main.cpp
+ ${SCC} ${SCC_SCRIPTS}/run_imp_line.tcl
+ echo "Done" > imp_line.tag
+imp_marks.tag:
+ sed -s 's/\\TCAB_NAME/ai_marks/g' ${SYNTH_SRC}/main.cpp.base >${SYNTH_SRC}/main.cpp
+ #cp ${SYNTH_SRC}/main.cpp.base ${SYNTH_SRC}/main.cpp
+ ${SCC} ${SCC_SCRIPTS}/run_imp_marks.tcl
+ echo "Done" > imp_marks.tag
+imp_sort.tag:
+ sed -s 's/\\TCAB_NAME/streamsort/g' ${SYNTH_SRC}/main.cpp.base >${SYNTH_SRC}/main.cpp
+ #cp ${SYNTH_SRC}/main.cpp.base ${SYNTH_SRC}/main.cpp
+ ${SCC} ${SCC_SCRIPTS}/run_imp_sort.tcl
+ echo "Done" > imp_sort.tag
+imp_threat.tag: imp_line.tag
+ sed -s 's/\\TCAB_NAME/ai_threats/g' ${SYNTH_SRC}/main.cpp.base >${SYNTH_SRC}/main.cpp
+ #cp ${SYNTH_SRC}/main.cpp.base ${SYNTH_SRC}/main.cpp
+ ${SCC} ${SCC_SCRIPTS}/run_imp_threat.tcl
+ echo "Done" > imp_threat.tag
+imp_adjacent.tag:
+ #cp ${SYNTH_SRC}/main.cpp.base ${SYNTH_SRC}/main.cpp
+ sed -s 's/\\TCAB_NAME/ai_adjacent/g' ${SYNTH_SRC}/main.cpp.base >${SYNTH_SRC}/main.cpp
+ ${SCC} ${SCC_SCRIPTS}/run_imp_adjacent.tcl
+ echo "Done" > imp_adjacent.tag
+imp_connect.tag: imp_threat.tag imp_adjacent.tag
+ sed -s 's/\\TCAB_NAME/connect6ai_synth/g' ${SYNTH_SRC}/main.cpp.base >${SYNTH_SRC}/main.cpp
+ ${SCC} ${SCC_SCRIPTS}/run_imp_connect.tcl
+ echo "Done" > imp_connect.tag
+
+xilinx_synth:
+ cp -r ./imp_connect/rtl_package/ ./
+ cp SP6/SP6.do_synth imp_connect/rtl_package/synth/synplify_fpga/do_synth
+ cp SP6/SP6.synplify.tcl imp_connect/rtl_package/synth/synplify_fpga/synplify.tcl
+ cp SP6/SP6.ucf imp_connect/rtl_package/synth/synplify_fpga/
+ echo -e 'all:\n\t./do_synth' > imp_connect/rtl_package/synth/synplify_fpga/makefile
+ make -C imp_connect/rtl_package/synth/synplify_fpga/
+
+test:
+ schroot -c centos5-i386 make emul
+ #../scripts/serial_port_setup.sh
+ rm -f ./test.result
+ for i in `seq 1 100` ; do ./connect6 -port /dev/ttyS0 -player L >> test.result 2>&1; done
+ #grep "FPGA has won" ./test.result | wc -l
+ #grep "AI has won" ./test.result | wc -l
+ #grep "TIE" ./test.result | wc -l
+ python ../scripts/esult.py
+pgm:
+ cp ./rtl_package/synth/altera_fpga/run/DE2.sof ./
+ quartus_pgm -c USB-Blaster -m jtag -o "p;DE2.sof"
+
+
+prof:
+ valgrind --tool=callgrind ./connect6 -player L
+ kcachegrind
+
+altera_clean:
+ rm -rf ./rtl_package/
+
+ultraclean: altera_clean
+ rm -rf *.tag imp_line imp_marks imp_threat imp_choose imp_adjacent imp_connect imp_window Logs