OpenCores
URL https://opencores.org/ocsvn/connect-6/connect-6/trunk

Subversion Repositories connect-6

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /connect-6
    from Rev 7 to Rev 8
    ↔ Reverse comparison
  •

Rev 7 → Rev 8

/trunk/BUILD_SCC/scc_scripts/run_imp_line.tcl
12,6 → 12,7
set_implementation_params -memory_return_path_external_delay 0%
set_implementation_params -memory_forward_path_external_delay 0%
set_implementation_params -instream_forward_path_external_delay 0%
set_implementation_params -import_tcab "imp_window"
set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g"
set_implementation_params -outstream_return_path_external_delay 0%
set_implementation_params -appfiles "synth_src/state.cpp synth_src/threats.cpp"
18,7 → 19,8
set_implementation_params -proc threat_line
set_implementation_params -memory_forward_boundary_register infer
set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive"
set_implementation_params -task_ii 441
#set_implementation_params -task_ii 441
set_loop_params -ii 1
set_implementation_params -techlib altera-cyclone3
set_implementation_params -device ep3c25-ea144-7
set_implementation_params -init_data_registers yes
31,7 → 33,7
set_implementation_params -task_overlap 0
set_implementation_params -instream_return_path_external_delay 0%
set_implementation_params -simulator modelsim
set_implementation_params -clock_freq 100
set_implementation_params -clock_freq 50
 
 
setvar preprocess_auxopts "-L"
/trunk/BUILD_SCC/scc_scripts/run_imp_threat.tcl
13,7 → 13,7
set_implementation_params -memory_return_path_external_delay 0%
set_implementation_params -memory_forward_path_external_delay 0%
#set_implementation_params -instream_forward_path_external_delay 0%
set_implementation_params -import_tcab "imp_line "
set_implementation_params -import_tcab "imp_line"
set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g -g"
#set_implementation_params -outstream_return_path_external_delay 0%
set_implementation_params -appfiles "synth_src/state.cpp synth_src/threats.cpp"
34,7 → 34,7
set_implementation_params -task_overlap 0
#set_implementation_params -instream_return_path_external_delay 0%
set_implementation_params -simulator modelsim
set_implementation_params -clock_freq 100
set_implementation_params -clock_freq 50
set_implementation_params -allow_latency_violation no
 
 
/trunk/BUILD_SCC/scc_scripts/run_imp_window.tcl
1,51 → 1,48
set SYNTH_SRC "synth_src"
set_project_params -directory ./
set_project_params -results myboard.txt
set_project_params -sources "${SYNTH_SRC}/connect6.cpp ${SYNTH_SRC}/connect6_synth.cpp ${SYNTH_SRC}/main.cpp ${SYNTH_SRC}/q.cpp ${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threats.cpp ${SYNTH_SRC}/threat_line.cpp ${SYNTH_SRC}/util.cpp"
set_project_params -headers "${SYNTH_SRC}/connect6.h ${SYNTH_SRC}/connect6_synth.h ${SYNTH_SRC}/q.hpp ${SYNTH_SRC}/shared.h ${SYNTH_SRC}/threats.h ${SYNTH_SRC}/util.h"
set_project_params -sources "synth_src/connect6.cpp synth_src/connect6_synth.cpp synth_src/main.cpp synth_src/q.cpp synth_src/state.cpp synth_src/threats.cpp synth_src/util.cpp"
set_project_params -headers "synth_src/connect6.h synth_src/connect6_synth.h synth_src/q.hpp synth_src/shared.h synth_src/threats.h synth_src/util.h"
set_project_params -cache_result_files no
set_project_params -cache_data_files yes
 
if [file exists imp_window] { delete_implementation imp_window }
create_implementation imp_window
 
set_implementation_params -systemc_source no
#set_implementation_params -memory_return_path_external_delay 0%
#set_implementation_params -memory_forward_path_external_delay 0%
#set_implementation_params -instream_forward_path_external_delay 0%
set_implementation_params -memory_return_path_external_delay 0%
set_implementation_params -memory_forward_path_external_delay 0%
set_implementation_params -instream_forward_path_external_delay 0%
set_implementation_params -sccompiler_args "-DDONT_VERIFY_PPAID"
#set_implementation_params -outstream_return_path_external_delay 0%
set_implementation_params -appfiles "${SYNTH_SRC}/state.cpp ${SYNTH_SRC}/threat_line.cpp"
set_implementation_params -outstream_return_path_external_delay 0%
set_implementation_params -appfiles "synth_src/state.cpp synth_src/threats.cpp"
set_implementation_params -proc threat_window
#set_implementation_params -task_ii 9
#set_implementation_params -memory_forward_boundary_register infer
set_implementation_params -memory_forward_boundary_register infer
set_implementation_params -architectural_pipelinability "1"
set_implementation_params -cppcompiler_args "-g -DPICO_SYNTH -fpermissive"
set_implementation_params -techlib altera-cyclone3
#set_implementation_params -memory_return_boundary_register infer
set_implementation_params -memory_return_boundary_register infer
set_implementation_params -cexec_args "-port /dev/ttyS0 -player L"
set_implementation_params -host_memory_access never,,,
set_implementation_params -host_memory_access never
set_implementation_params -device ep3c25-ea144-7
#set_implementation_params -force_independent_stalldomain_tcab yes
set_implementation_params -init_data_registers yes
#set_implementation_params -outstream_forward_path_external_delay 0%
set_implementation_params -outstream_forward_path_external_delay 0%
set_implementation_params -build_tcab yes
set_implementation_params -reset_data_registers yes
#set_implementation_params -instream_return_path_external_delay 0%
set_implementation_params -clock_freq 100
set_implementation_params -task_overlap infer
#set_implementation_params -allow_latency_violation no
#set_implementation_params -user_supplied_fpga_memory_read_write_ports separate
#set_implementation_params -internal_blockram_memory_read_write_ports separate
set_implementation_params -instream_return_path_external_delay 0%
set_implementation_params -simulator modelsim
set_implementation_params -clock_freq 50
 
 
 
set_loop_params -ii 1
csim -golden -cexec_args "-port /dev/ttyS0 -player L"
csim -golden -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
preprocess
csim -preprocess -cexec_args "-port /dev/ttyS0 -player L"
csim -preprocess -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
schedule
csim -schedule -cexec_args "-port /dev/ttyS0 -player L"
csim -schedule -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -cexec_args "-port /dev/ttyS0 -player L"
synthesize
#csim -synthesize -dump_memory_access_trace -sim_after_synth_phase 5
create_rtl_package
#vlogsim -online -ccompiler_args "-g" -cppcompiler_args "-g -DPICO_SYNTH -fpermissive" -sccompiler_args "-DDONT_VERIFY_PPAID" -cexec_args "-port /dev/ttyS0 -player L" -simulator modelsim -vcompiler_args -vexec_args
 
#set_implementation_params -simulator modelsim
#vlogsim -offline -dotasks 1-30
/trunk/BUILD_SCC/scc_scripts/run_imp_adjacent.tcl
27,7 → 27,7
set_implementation_params -build_tcab yes
set_implementation_params -reset_data_registers yes
set_implementation_params -instream_return_path_external_delay 0%
set_implementation_params -clock_freq 100
set_implementation_params -clock_freq 50
set_implementation_params -allow_latency_violation no
#set_implementation_params -user_supplied_fpga_memory_read_write_ports separate
#set_implementation_params -internal_blockram_memory_read_write_ports separate
/trunk/BUILD_SCC/scc_scripts/run_imp_connect.tcl
28,7 → 28,7
set_implementation_params -build_tcab yes
set_implementation_params -reset_data_registers yes
set_implementation_params -instream_return_path_external_delay 0%
set_implementation_params -clock_freq 100
set_implementation_params -clock_freq 50
set_implementation_params -allow_latency_violation no
set_implementation_params -tcab_deployment conditional_outputs:yes
#setvar preprocess_auxopts "-Xmax_loops_for_jamming=15"
/trunk/BUILD_SCC/search.c
0,0 → 1,234
 
/*
 
connectk -- UMN CSci 5512W project
 
*/
 
#include "config.h"
#include <string.h>
#include <glib.h>
#include "../shared.h"
#include "../connectk.h"
 
/* Variables required to check for cache hits */
static int cache_id = -1, cache_depth = -1, cache_branch = -1;
static SEARCH cache_search = -1;
static AIMoves *cache_moves = NULL;
static AIWEIGHT cache_best;
static Player *cache_player;
static AIFunc cache_func;
static BCOORD cache_size;
 
void dfs_cache_dump(void)
/* Called from tests.c to print out the DFS cache */
{
g_debug("DFS cache: ");
aimoves_print(cache_moves);
g_print("\n");
}
 
static void cache_set(int index, AIMove *move)
{
if (move->weight < cache_best || index > place_p)
return;
if (cache_moves->len <= index)
cache_moves->len = index + 1;
cache_moves->data[index] = *move;
cache_best = move->weight;
}
 
static AIWEIGHT df_search(Board *b, AIMoves *moves, Player *player,
int depth, int cache_index,
PIECE searched, AIWEIGHT alpha, AIWEIGHT beta)
/* Depth is in _moves_ */
{
int i, j;
 
/* Halt and depth abort */
if (ai_stop || depth < 1)
return moves->utility;
 
/* Alpha-beta sanity check */
if (alpha >= beta) {
g_warning("DFS alpha-beta failed sanity check");
return moves->utility;
}
 
/* Search only the top moves beyond the minimum */
aimoves_sort(moves);
if (moves->len > player->branch) {
for (i = player->branch; i < moves->len; i++)
if (moves->data[i].weight != moves->data[0].weight)
break;
moves->len = i;
}
 
/* No moves left -- its a draw */
if (moves->len < 1)
return AIW_DRAW;
 
/* Search each move available in depth first order */
for (i = 0; i < moves->len; i++) {
Board *b_next;
AIMove *aim = moves->data + i;
AIMoves *moves_next;
 
/* Did we get a bad move? */
if (!piece_empty(piece_at(b, aim->x, aim->y))) {
g_warning("DFS utility function suggested a bad move "
"(%s)", bcoords_to_string(aim->x, aim->y));
continue;
}
 
/* Already searched here? */
if (piece_at(b, aim->x, aim->y) == searched)
continue;
place_piece_type(b, aim->x, aim->y, searched);
 
b_next = board_new();
board_copy(b, b_next);
place_piece(b_next, aim->x, aim->y);
 
/* Did we win? */
if (check_win(b_next, aim->x, aim->y))
aim->weight = AIW_WIN;
 
/* Otherwise, search deeper */
else {
int next_ci = cache_index + 1;
AIWEIGHT next_alpha = alpha, next_beta = beta;
AIFunc func;
 
b_next->moves_left--;
 
/* Player has changed */
if (b_next->moves_left <= 0) {
b_next->moves_left = place_p;
b_next->turn = other_player(b->turn);
next_ci += place_p;
searched++;
next_alpha = -beta;
next_beta = -alpha;
}
 
func = ai(player->ai)->func;
if (!func) {
g_warning("DFS player has no AI function");
return moves->utility;
}
moves_next = func(b_next);
aim->weight = df_search(b_next, moves_next, player,
depth - 1, next_ci, searched,
next_alpha, next_beta);
aimoves_free(moves_next);
if (b_next->turn != b->turn)
aim->weight = -aim->weight;
}
 
/* Debug search */
if (opt_debug_dfsc) {
for(j = MAX_DEPTH - depth; j > 0; j--)
g_print("-");
g_print("> d=%d, %s, u=%d, a=%d, b=%d %s\n",
depth, bcoords_to_string(aim->x, aim->y),
aim->weight, alpha, beta,
piece_to_string(b->turn));
}
 
board_free(b_next);
if (aim->weight > alpha) {
alpha = aim->weight;
cache_set(cache_index, aim);
 
/* Victory abort */
if (alpha >= AIW_WIN)
return AIW_WIN;
 
/* Alpha-beta pruning */
if (alpha >= beta)
return alpha;
}
}
 
return alpha;
}
 
void search(const Board *b, AIMoves *moves, Player *player)
{
Board *copy;
AIFunc move_func = ai(player->ai)->func;
 
/* Player is not configured to search */
if (player->search == SEARCH_NONE)
return;
 
/* Moves list does not need to be searched */
if (moves->len <= b->moves_left) {
if (opt_debug_dfsc)
g_debug("DFS no choice abort");
return;
}
 
/* Board size changed, cache is invalidated */
if (board_size != cache_size)
cache_moves = NULL;
cache_size = board_size;
 
/* Cache hit, last or same board */
if (player->cache && cache_moves && cache_moves->len &&
cache_search == player->search &&
cache_depth == player->depth &&
cache_player == player &&
cache_func == move_func &&
cache_branch == player->branch) {
if (b->parent && cache_id == b->parent->ac.id) {
aimoves_remove(cache_moves, b->parent->move_x,
b->parent->move_y);
cache_id = b->ac.id;
}
if (cache_id == b->ac.id && cache_moves->len) {
if (cache_moves->len) {
aimoves_copy(cache_moves, moves);
if (opt_debug_dfsc)
g_debug("DFS cache HIT");
return;
}
aimoves_free(cache_moves);
cache_moves = NULL;
}
}
 
/* Cache miss */
if (opt_debug_dfsc)
g_debug("DFS cache MISS");
cache_id = b->ac.id;
if (!cache_moves)
cache_moves = aimoves_new();
cache_moves->len = 0;
cache_best = AIW_MIN;
copy = board_new();
board_copy(b, copy);
if (player->search == SEARCH_DFS) {
df_search(copy, moves, player, player->depth, 0,
PIECE_SEARCHED, AIW_LOSE, AIW_WIN);
if (cache_moves->len)
aimoves_copy(cache_moves, moves);
} else {
board_free(copy);
g_warning("Unsupported search type %d", player->search);
return;
}
board_free(copy);
 
/* Debug DFS search */
if (opt_debug_dfsc)
dfs_cache_dump();
 
/* Save params so we can check if we have a hit later */
cache_player = player;
cache_search = player->search;
cache_depth = player->depth;
cache_branch = player->branch;
cache_func = move_func;
}
trunk/BUILD_SCC/search.c Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/BUILD_SCC/DE2/constraints.sdc =================================================================== --- trunk/BUILD_SCC/DE2/constraints.sdc (revision 7) +++ trunk/BUILD_SCC/DE2/constraints.sdc (revision 8) @@ -1,5 +1,5 @@ # clocks -create_clock -period 20.0 -name clk [get_ports OSC_50] +create_clock -period 30.0 -name clk [get_ports OSC_27] # input/output delays
/trunk/BUILD_SCC/DE2/quartus.tcl
36,7 → 36,7
}
set_global_assignment -name VERILOG_FILE "../../../rtl/${rtl}"
}
 
#set_global_assignment -name VERILOG_FILE ../../../../rtl_package/simu_stubs/vsim/bram_based_stream_buffer.v
#DE2 files
set de2files [glob -directory ../../../../DE2/ -nocomplain -tails -types f -- {*\.v}]
foreach mcs ${de2files} {
52,6 → 52,11
}
set_global_assignment -name VHDL_FILE "../../../../DE2/${mcs}"
}
set_global_assignment -name VHDL_FILE "../../../../DE2/pll/pll.vhd"
set_global_assignment -name MISC_FILE "../../../../DE2/pll/pll_inst.vhd"
set_global_assignment -name MISC_FILE "../../../../DE2/pll/pll.cmp"
set_global_assignment -name MISC_FILE "../../../../DE2/pll/pll.ppf"
set_global_assignment -name MISC_FILE "../../../../DE2/pll/pll_syn.v"
 
# run the flow
#execute_flow -compile
/trunk/BUILD_SCC/DE2/bram_based_stream_buffer.v
0,0 → 1,244
// Copyright (c) 2011 Synopsys, Inc. All rights reserved.
//
//
// $Revision: 1.8 $
 
 
`timescale 1ns / 1ps
 
`ifdef PICO_CLOCK_EDGE
`else
`define PICO_CLOCK_EDGE posedge
`endif
`ifdef PICO_CLOCK_SENSITIVITY
`else
`define PICO_CLOCK_SENSITIVITY clk
`endif
`ifdef PICO_RESET_SENSITIVITY
`else
`define PICO_RESET_SENSITIVITY
`endif
`ifdef PICO_RESET_SENSITIVITY2
`else
`define PICO_RESET_SENSITIVITY2 reset
`endif
 
`timescale 1 ns / 10 ps
 
module bram_based_stream_buffer (clk, indata, outdata, store_ready, load_ready, reset, flush, load_req, store_req );
 
parameter width = 48;
parameter depth = 800;
parameter awidth = clogb2(depth);
 
input clk, load_ready, store_ready, reset, flush;
wire clk, load_ready, store_ready, reset, flush;
 
input [width-1:0] indata;
wire [width-1:0] indata;
 
output load_req, store_req;
wire load_req, store_req;
 
output [width-1:0] outdata;
wire [width-1:0] outdata;
 
 
function integer clogb2(input integer depth);
begin
for (clogb2=0; depth>0; clogb2=clogb2+1)
depth= depth>>1;
end
endfunction
 
// 0in assert -var (depth >= 1)
// coverage off
// pragma coverage off
// VCS coverage off
// synopsys translate_off
initial begin
if ( depth < 1 ) begin
$display ("ERROR::::");
$display ("mc_log: ERROR: bram_based_stream_buffer of depth %0d in %m. This is unsupported.Stopping simulation",depth);
$display ("END ERROR");
$finish;
end
end
// synopsys translate_on
// VCS coverage on
// pragma coverage on
// coverage on
 
reg [awidth-1:0] read_addr_ff, next_read_addr_ff, write_addr_ff;
reg [awidth-1:0] count_ff ;
reg full_ff, not_empty_ff, onefull_ff, init_ff;
 
reg [width-1:0] bypass_reg_ff;
reg bypass_reg_valid_ff;
 
wire [width-1:0] bram_outdata;
wire addq_only, shiftq_only, shiftq_addq, mem_is_empty;
 
wire addq = load_ready;
wire shiftq = store_ready;
 
wire full_mem = full_ff;
assign mem_is_empty = ~not_empty_ff;
 
assign addq_only = (addq & !full_ff & (!shiftq |(shiftq & mem_is_empty)));
assign shiftq_only = (shiftq & !mem_is_empty & (!addq | (addq & full_mem)) );
assign shiftq_addq = (shiftq & addq & not_empty_ff & !full_mem);
 
wire rreq, wreq;
 
assign rreq = not_empty_ff;
assign wreq = addq & !full_mem;
assign load_req = !full_mem;
assign store_req = !mem_is_empty;
 
always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY ) begin
if (`PICO_RESET_SENSITIVITY2) begin
not_empty_ff <= 1'b0;
full_ff <= 1'b0;
init_ff <= 1'b0;
end
else if (flush) begin
not_empty_ff <= 1'b0;
full_ff <= 1'b0;
init_ff <= 1'b0;
end
else begin
init_ff <= 1'b1;
if (addq & mem_is_empty) begin
not_empty_ff <= 1'b1;
end
else if (shiftq & !addq & onefull_ff) begin
not_empty_ff <= 1'b0;
end
if (addq_only & (count_ff == depth-1)) full_ff <= 1'b1;
else if (shiftq_only) full_ff <= 1'b0;
end
end
 
always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY ) begin
if (`PICO_RESET_SENSITIVITY2) begin
onefull_ff <= 1'b0;
end
else if (flush) begin
onefull_ff <= 1'b0;
end
else begin
if (addq_only) begin
if (mem_is_empty) begin
onefull_ff <= 1'b1;
end
else begin
onefull_ff <= 1'b0;
end
end
else if (shiftq_only) begin
if (onefull_ff) begin
onefull_ff <= 1'b0;
end
else if (count_ff == 2'b10) begin
onefull_ff <= 1'b1;
end
end
end
end
 
always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY ) begin
if (`PICO_RESET_SENSITIVITY2) begin
read_addr_ff <= {awidth{1'b0}};
next_read_addr_ff <= {awidth{1'b0}};
end
else if (flush) begin
read_addr_ff <= {awidth{1'b0}};
next_read_addr_ff <= {awidth{1'b0}};
end
else begin
if ( (shiftq & not_empty_ff) | ~init_ff ) begin
read_addr_ff <= next_read_addr_ff;
if (next_read_addr_ff == depth-1) begin
next_read_addr_ff <= {awidth{1'b0}};
end
else begin
next_read_addr_ff <= next_read_addr_ff + 1'b1;
end
end
end
end
 
always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY ) begin
if (`PICO_RESET_SENSITIVITY2) begin
write_addr_ff <= {awidth{1'b0}};
end
else if (flush) begin
write_addr_ff <= {awidth{1'b0}};
end
else begin
if (wreq) begin
if (write_addr_ff == depth-1)
write_addr_ff <= {awidth{1'b0}};
else
write_addr_ff <= write_addr_ff + 1'b1;
end
end
end
 
always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY ) begin
if (`PICO_RESET_SENSITIVITY2) begin
count_ff <= {awidth{1'b0}};
end
else if (flush) begin
count_ff <= {awidth{1'b0}};
end
else begin
if (addq_only) begin
count_ff <= count_ff + 1'b1;
end
else if (shiftq_only) begin
count_ff <= count_ff - 1'b1;
end
end
end
 
always @ (`PICO_CLOCK_EDGE `PICO_CLOCK_SENSITIVITY `PICO_RESET_SENSITIVITY) begin
if (`PICO_RESET_SENSITIVITY2)
begin
bypass_reg_valid_ff <= 1'b0;
bypass_reg_ff <= {(width){1'b0}};
end
else if (flush)
begin
bypass_reg_valid_ff <= 1'b0;
end
else
begin
bypass_reg_valid_ff <= addq & ( mem_is_empty | (shiftq & onefull_ff) );
bypass_reg_ff <= indata;
end
end
assign outdata = bypass_reg_valid_ff ? bypass_reg_ff[width-1:0] : bram_outdata[width-1:0];
 
wire [awidth-1:0] speculative_read_addr = (shiftq & not_empty_ff) ? next_read_addr_ff : read_addr_ff;
 
RA2SH #(.dwidth(width), .depth(depth), .awidth(awidth) ) fifo_storage(
.QA(),
.CLKA(clk),
.CENA(~wreq),
.WENA(1'b0),
.AA(write_addr_ff[awidth-1:0]),
.DA(indata[width-1:0]),
.QB(bram_outdata[width-1:0]),
.CLKB(clk),
.CENB(~rreq),
.WENB(1'b1),
.AB(speculative_read_addr),
.DB({width{1'b0}}));
 
 
endmodule
/trunk/BUILD_SCC/DE2/async_receiver_altera.v
3,8 → 3,9
output RxD_data_ready; // onc clock pulse when RxD_data is valid
output [7:0] RxD_data;
 
//parameter ClkFrequency = 50000000; // 50MHz
parameter ClkFrequency = 27000000; // 27MHz
//parameter ClkFrequency = 62500000; // 50MHz
parameter ClkFrequency = 50000000; // 50MHz
//parameter ClkFrequency = 27000000; // 27MHz
parameter Baud = 115200;
 
// We also detect if a gap occurs in the received stream of characters
/trunk/BUILD_SCC/DE2/async_transmitter_altera.v
3,8 → 3,9
input [7:0] TxD_data;
output TxD, TxD_busy;
 
//parameter ClkFrequency = 50000000; // 50MHz
parameter ClkFrequency = 27000000; // 27MHz
//parameter ClkFrequency = 62500000; // 60MHz
parameter ClkFrequency = 50000000; // 50MHz
//parameter ClkFrequency = 27000000; // 27MHz
parameter Baud = 115200;
 
// Baud generator
/trunk/BUILD_SCC/DE2/AI.vhd
20,6 → 20,20
 
 
architecture c_to_g of AI is
component bram_based_stream_buffer is
--#(.width(48), .depth(`CONNECT6AI_SYNTH_ILS_FIFO_QUEUE_DISMANTLE_LENGTH))
port(
clk:in std_logic;
reset:in std_logic;
store_ready:in std_logic;
flush:in std_logic;
store_req:out std_logic;
load_req:out std_logic;
load_ready:in std_logic;
indata:in std_logic_vector(47 downto 0);
outdata:out std_logic_vector(47 downto 0)
);
end component bram_based_stream_buffer;
 
component connect6ai_synth_tcab is
port(
62,7 → 76,13
rawdataout_pico_connect6ai_synth_moveout_out_4_0: out std_logic_vector(7 downto 0);
rawdataout_pico_connect6ai_synth_moveout_out_5_0: out std_logic_vector(7 downto 0);
rawdataout_pico_connect6ai_synth_moveout_out_6_0: out std_logic_vector(7 downto 0);
rawdataout_pico_connect6ai_synth_moveout_out_7_0: out std_logic_vector(7 downto 0)
rawdataout_pico_connect6ai_synth_moveout_out_7_0: out std_logic_vector(7 downto 0);
instream_queue_di_0:in std_logic_vector(47 downto 0);
instream_queue_req_0:out std_logic;
instream_queue_ready_0:in std_logic;
outstream_queue_do_1:out std_logic_vector(47 downto 0);
outstream_queue_req_1:out std_logic;
outstream_queue_ready_1:in std_logic
 
);
end component connect6ai_synth_tcab;
69,6 → 89,12
signal out_enables:std_logic_vector(7 downto 0);
signal out_enables_reg:std_logic_vector(7 downto 0);
signal AI_DATA,mAI_DATA: std_logic_vector(63 downto 0);
signal ils_fifo_queue_dismantle_outdata:std_logic_vector(47 downto 0);
signal tcab_instream_queue_req_0:std_logic;
signal ils_fifo_queue_dismantle_store_req: std_logic;
signal tcab_outstream_queue_do_1:std_logic_vector(47 downto 0);
signal tcab_outstream_queue_req_1:std_logic;
signal ils_fifo_queue_dismantle_load_req: std_logic;
begin
oAI_DATA<=AI_DATA;
inst_ai:connect6ai_synth_tcab
113,8 → 139,26
rawdataout_pico_connect6ai_synth_moveout_out_4_0=> mAI_DATA(31 downto 24),
rawdataout_pico_connect6ai_synth_moveout_out_5_0=> mAI_DATA(23 downto 16),
rawdataout_pico_connect6ai_synth_moveout_out_6_0=> mAI_DATA(15 downto 8),
rawdataout_pico_connect6ai_synth_moveout_out_7_0=> mAI_DATA(7 downto 0)
rawdataout_pico_connect6ai_synth_moveout_out_7_0=> mAI_DATA(7 downto 0),
instream_queue_di_0=>ils_fifo_queue_dismantle_outdata(47 downto 0),
instream_queue_req_0=>tcab_instream_queue_req_0,
instream_queue_ready_0=>ils_fifo_queue_dismantle_store_req,
outstream_queue_do_1=>tcab_outstream_queue_do_1(47 downto 0),
outstream_queue_req_1=>tcab_outstream_queue_req_1,
outstream_queue_ready_1=>ils_fifo_queue_dismantle_load_req
);
ils_fifo_queue_dismantle:bram_based_stream_buffer
--#(.width(48), .depth(`CONNECT6AI_SYNTH_ILS_FIFO_QUEUE_DISMANTLE_LENGTH))
port map(
clk=>iCLK,
reset=>not(iRST_n),
store_ready=>tcab_instream_queue_req_0,
flush=>'0',
store_req=>ils_fifo_queue_dismantle_store_req,
load_req=>ils_fifo_queue_dismantle_load_req,
load_ready=>tcab_outstream_queue_req_1,
indata=>tcab_outstream_queue_do_1(47 downto 0),
outdata=>ils_fifo_queue_dismantle_outdata(47 downto 0));
 
process(iCLK)
begin
/trunk/BUILD_SCC/DE2/DE2.v
72,7 → 72,7
 
wire mTXD_Done_not;
RS232_Controller u1_bis( .iDATA(mTXD_DATA),.iTxD_Start(mTXD_Start),.oTxD_Busy(mTXD_Done_not),
.oDATA(mRXD_DATA),.oRxD_Ready(mRXD_Ready),.iCLK(OSC_27),.RST_n(KEY[0]),
.oDATA(mRXD_DATA),.oRxD_Ready(mRXD_Ready),.iCLK(OSC_100),.RST_n(KEY[0]),
.oTxD(UART_TXD),.iRxD(UART_RXD));
assign mTXD_Done = !mTXD_Done_not;
assign LED_RED[9] = mTXD_Done_not;
88,7 → 88,7
.iRXD_DATA(mRXD_DATA),.iRXD_Ready(mRXD_Ready),
.oTXD_DATA(mTXD_DATA),.oTXD_Start(mTXD_Start),.iTXD_Done(mTXD_Done),
// Control
.iCLK(OSC_27),.iRST_n(KEY[0]), .oAI_RSTn(mAI_RSTn),
.iCLK(OSC_100),.iRST_n(KEY[0]), .oAI_RSTn(mAI_RSTn),
//AI
.oAI_DATA(DATA_to_AI),
.iAI_DATA(DATA_from_AI),
103,17 → 103,19
.oAI_Done(mAI_Done),
// Control
.iCLK(OSC_27),.iRST_n(mAI_RSTn) );
.iCLK(OSC_100),.iRST_n(mAI_RSTn) );
wire [63:0] CMD_Tmp;
 
//assign mSEG7_DIG = { CMD_Tmp[31:28],CMD_Tmp[27:24],CMD_Tmp[23:20],CMD_Tmp[19:16],
// CMD_Tmp[15:12],CMD_Tmp[11:8],CMD_Tmp[7:4],CMD_Tmp[3:0] };
assign mSEG7_DIG = {
DATA_to_AI[63:60],DATA_to_AI[59:56],DATA_to_AI[55:52],DATA_to_AI[51:48],
DATA_to_AI[47:44],DATA_to_AI[43:40],DATA_to_AI[39:36],DATA_to_AI[35:32] }
// DATA_from_AI[31:28],DATA_from_AI[27:24],DATA_from_AI[23:20],DATA_from_AI[19:16],
// DATA_from_AI[15:12],DATA_from_AI[11:8],DATA_from_AI[7:4],DATA_from_AI[3:0] }
// DATA_to_AI[63:60],DATA_to_AI[59:56],DATA_to_AI[55:52],DATA_to_AI[51:48],
// DATA_to_AI[47:44],DATA_to_AI[43:40],DATA_to_AI[39:36],DATA_to_AI[35:32] }
DATA_from_AI[31:28],DATA_from_AI[27:24],DATA_from_AI[23:20],DATA_from_AI[19:16],
DATA_from_AI[15:12],DATA_from_AI[11:8],DATA_from_AI[7:4],DATA_from_AI[3:0] }
;
wire rst=!(KEY[0]);
wire OSC_100,lock;
assign LED_GREEN[7] = lock;
pll inst_pll(.areset(rst),.inclk0(OSC_50),.c0(OSC_100),.locked(lock));
endmodule
/trunk/BUILD_SCC/synth_src/main.cpp
219,7 → 219,7
connect6ai(board,AI_colour,move);
movecount++;
cout<<"AI MOVE: "<<move[0]<<move[1]<<move[2]<<move[3]<<endl;
//if(movecount >=20) return 0 ; //reducing length of simulation
if(movecount >=20) return 0 ; //reducing length of simulation
winning_colour = check_for_win(board);
if (winning_colour == AI_colour){
cout<<"AI has won! " << movecount << " moves " << "Exiting."<<endl;
/trunk/BUILD_SCC/synth_src/threats.cpp
192,8 → 192,8
return 0;
 
/* Push forward the maximum and find the window type */
//#pragma unroll
//#pragma num_iterations(1,3,6)
#pragma unroll
#pragma num_iterations(1,3,6)
for (maximum = 1; maximum < connect_k; maximum++) {
p = piece_at(b, x + dx * maximum, y + dy * maximum);
if (p == PIECE_ERROR)
209,8 → 209,8
maximum--;
 
/* Try to push the entire window back */
//#pragma unroll
//#pragma num_iterations(1,3,6)
#pragma unroll
#pragma num_iterations(1,3,6)
for (minimum = -1; minimum > -connect_k; minimum--) {
p = piece_at(b, x + dx * minimum, y + dy * minimum);
if (p == PIECE_ERROR || piece_empty(p))
232,8 → 232,8
/* Push back minimum if we haven't formed a complete window, this window
can't be a double */
if (maximum - minimum < connect_k - 1) {
//#pragma unroll
//#pragma num_iterations(1,3,6)
//#pragma unroll
#pragma num_iterations(1,3,6)
for (minimum--; minimum > maximum - connect_k; minimum--) {
p = piece_at(b, x + dx * minimum, y + dy * minimum);
if (p == PIECE_ERROR)
276,7 → 276,7
#pragma internal_fast threat_counts
//#pragma read_write_ports threat_counts.data combined 2
//#pragma no_memory_analysis threat_counts
if (k==1) board_copy(b, bwrite);
//if (k==1) board_copy(b, bwrite);
int i;
AIWEIGHT weight = 0;
///* Clear threat tallys */
367,7 → 367,7
/*static*/ Board bwrite;//={0,0,0,0,0,0,0,0,0,0,0,{{0}}} ;//= NULL;
//#pragma read_write_ports b.data combined 2
#pragma internal_blockram bwrite
//#pragma multi_buffer bwrite 2
//#pragma multi_buffer bwrite 22
//#pragma no_memory_analysis b
/*static*/ AIMoves moves;//={0,0,0,{{0,0,0}}};
//#pragma read_write_ports moves.data combined 3
515,6 → 515,7
}
 
 
if (k==1) board_copy(&b, &bwrite);
u_sum += threat_line(arg1, arg2, arg3, arg4,&b,&bwrite,k,loop_bound);
}
}
712,11 → 713,11
// }
//while(1) {
//int count=0;
#pragma num_iterations(1,150,1362)
for(k=0;k<1362;k++){
#pragma num_iterations(1,150,368)
for(k=0;k<368;k++){
//count++;
//cout<<count<<endl;
if (k>1000){
if (k>6){
//if(ready>5){
val=pico_stream_input_queue();
/trunk/BUILD_SCC/Makefile
49,7 → 49,7
cp ${SYNTH_SRC}/main.cpp.base ${SYNTH_SRC}/main.cpp
${SCC} ${SCC_SCRIPTS}/run_imp_window.tcl
echo "Done" > imp_window.tag
imp_line.tag:
imp_line.tag: imp_window.tag
sed -s 's/\\TCAB_NAME/threat_line/g' ${SYNTH_SRC}/main.cpp.base >${SYNTH_SRC}/main.cpp
#cp ${SYNTH_SRC}/main.cpp.base ${SYNTH_SRC}/main.cpp
${SCC} ${SCC_SCRIPTS}/run_imp_line.tcl

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