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URL https://opencores.org/ocsvn/copyblaze/copyblaze/trunk

Subversion Repositories copyblaze

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  • This comparison shows the changes necessary to convert path 
    /copyblaze/trunk
    from Rev 56 to Rev 57
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  •

Rev 56 → Rev 57

/copyblaze/rtl/vhdl/cp_Alu.vhd File deleted
/copyblaze/rtl/vhdl/cp_Usefull_Pkg.vhd File deleted
/copyblaze/rtl/vhdl/cp_Flags.vhd File deleted
/copyblaze/rtl/vhdl/cp_ScratchPad.vhd File deleted
/copyblaze/rtl/vhdl/cp_FullAdder.vhd File deleted
/copyblaze/rtl/vhdl/cp_DecodeControl.vhd File deleted
/copyblaze/rtl/vhdl/cp_Toggle.vhd File deleted
/copyblaze/rtl/vhdl/cp_copyBlaze.vhd File deleted \ No newline at end of file
/copyblaze/rtl/vhdl/cp_ProgramCounter.vhd File deleted
/copyblaze/rtl/vhdl/cp_Stack.vhd File deleted
/copyblaze/rtl/vhdl/cp_copyBlaze_ecoSystem.vhd File deleted \ No newline at end of file
/copyblaze/rtl/vhdl/cp_BancRegister.vhd File deleted
/copyblaze/rtl/vhdl/cp_CLAAdder.vhd File deleted
/copyblaze/rtl/vhdl/cp_ProgramFlowControl.vhd File deleted
/copyblaze/rtl/vhdl/cp_Interrupt.vhd File deleted
/copyblaze/rtl/vhdl/cpu/cp_CLAAdder.vhd
0,0 → 1,116
--------------------------------------------------------------------------------
-- Company:
--
-- File: cp_CLAAdder.vhd
--
-- Description:
-- projet copyblaze
-- carry look-ahead adder by recursively expanding the carry term to each stage
--
-- File history:
-- v1.0: 14/10/11: Creation
--
-- Targeted device: ProAsic A3P250 VQFP100
-- Author: AbdAllah Meziti
--------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.Usefull_Pkg.all; -- Usefull Package
 
--------------------------------------------------------------------------------
-- Entity: cp_CLAAdder
--
-- Description:
--
-- REMARQUE:
--
--
-- History:
-- 14/10/11 AM: Creation
-- ---------------------
-- xx/xx/xx AM:
--
--------------------------------------------------------------------------------
entity cp_CLAAdder is
generic
(
GEN_WIDTH_DATA : positive := 8
);
port (
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
CarryIn_i : in std_ulogic;
sX_i : in std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
sY_i : in std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
 
CarryOut_o : out std_ulogic;
Result_o : out std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0)
);
end cp_CLAAdder;
 
--------------------------------------------------------------------------------
-- Architecture: RTL
-- of entity : cp_CLAAdder
--------------------------------------------------------------------------------
architecture rtl of cp_CLAAdder is
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
signal iCarry: std_ulogic_vector (GEN_WIDTH_DATA downto 0);
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
component cp_FullAdder
port (
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
Ci_i : in std_ulogic;
A_i : in std_ulogic;
B_i : in std_ulogic;
Co_o : out std_ulogic;
S_o : out std_ulogic
);
end component;
 
begin
 
--------------------------------------------------------------------------------
-- Full adder
--------------------------------------------------------------------------------
Adder_Gen: for i in 0 to GEN_WIDTH_DATA-1 generate
U_FullAdder : cp_FullAdder
port map(
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
Ci_i => iCarry(i) ,
A_i => sX_i(i) ,
B_i => sY_i(i) ,
 
Co_o => iCarry(i+1) ,
S_o => Result_o(i)
);
end generate Adder_Gen;
 
iCarry(0) <= CarryIn_i;
CarryOut_o <= iCarry(GEN_WIDTH_DATA);
 
end rtl;
 
/copyblaze/rtl/vhdl/cpu/cp_ProgramFlowControl.vhd
0,0 → 1,249
--------------------------------------------------------------------------------
-- Company:
--
-- File: cp_ProgramFlowControl.vhd
--
-- Description:
-- projet copyblaze
-- Program Flow Control management
--
-- File history:
-- v1.0: 10/10/11: Creation
-- v1.1: 11/10/11: Add Condionnal management
-- v1.2: 12/10/11: Modification du traitement des conditions de saut
--
-- Targeted device: ProAsic A3P250 VQFP100
-- Author: AbdAllah Meziti
--------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.Usefull_Pkg.all; -- Usefull Package
 
--------------------------------------------------------------------------------
-- Entity: cp_ProgramFlowControl
--
-- Description:
--
-- REMARQUE:
--
--
-- History:
-- 10/10/11 AM: Creation
-- ---------------------
-- xx/xx/xx AM:
--
--------------------------------------------------------------------------------
entity cp_ProgramFlowControl is
generic
(
GEN_WIDTH_PC : positive := 8;
GEN_INT_VECTOR : std_ulogic_vector(11 downto 0) := x"0F0";
GEN_DEPTH_STACK : positive := 15
);
port (
--------------------------------------------------------------------------------
-- Signaux Systeme
--------------------------------------------------------------------------------
 
 
 
Enable_i : in std_ulogic;
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
aaa_i : in std_ulogic_vector(GEN_WIDTH_PC-1 downto 0); --
Interrupt_i : in std_ulogic; --
 
Jump_i : in std_ulogic;
Call_i : in std_ulogic;
Return_i : in std_ulogic;
ReturnI_i : in std_ulogic;
ConditionCtrl_i : in std_ulogic_vector(2 downto 0);
FlagC_i : in std_ulogic;
FlagZ_i : in std_ulogic;
PC_o : out std_ulogic_vector(GEN_WIDTH_PC-1 downto 0) --
);
end cp_ProgramFlowControl;
 
--------------------------------------------------------------------------------
-- Architecture: RTL
-- of entity : cp_ProgramFlowControl
--------------------------------------------------------------------------------
architecture rtl of cp_ProgramFlowControl is
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
signal iPC : std_ulogic_vector(GEN_WIDTH_PC-1 downto 0); -- Programm Counter Signal
signal iPCin : std_ulogic_vector(GEN_WIDTH_PC-1 downto 0); -- Programm Counter Signal
 
signal iDataStackToPC : std_ulogic_vector(GEN_WIDTH_PC-1 downto 0);
signal iChangePC : std_ulogic;
alias iUnConditionnal : std_ulogic is ConditionCtrl_i(2);
alias iConditionnal : std_ulogic_vector(1 downto 0) is ConditionCtrl_i(1 downto 0);
signal iCondition : std_ulogic;
 
signal iPush : std_ulogic;
signal iPop : std_ulogic;
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
component cp_ProgramCounter
generic
(
GEN_WIDTH_PC : positive := 8
);
port (
--------------------------------------------------------------------------------
-- Signaux Systeme
--------------------------------------------------------------------------------
 
 
Enable_i : in std_ulogic;
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
PC_i : in std_ulogic_vector(GEN_WIDTH_PC-1 downto 0);
Change_i : in std_ulogic;
PC_o : out std_ulogic_vector(GEN_WIDTH_PC-1 downto 0)
);
end component;
 
component cp_Stack
generic
(
GEN_WIDTH_PC : positive := 8;
GEN_DETPH : positive := 15
);
port (
--------------------------------------------------------------------------------
-- Signaux Systeme
--------------------------------------------------------------------------------
 
 
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
Data_i : in std_ulogic_vector(GEN_WIDTH_PC-1 downto 0); --
Data_o : out std_ulogic_vector(GEN_WIDTH_PC-1 downto 0); --
Enable_i : in std_ulogic;
Push_i : in std_ulogic;
Pop_i : in std_ulogic
);
end component;
begin
 
--------------------------------------------------------------------------------
-- Traitement des conditions du saut du PC
--------------------------------------------------------------------------------
iCondition <= '1' when (iUnConditionnal='0') else
FlagZ_i when (iConditionnal="00") else
not(FlagZ_i) when (iConditionnal="01") else
FlagC_i when (iConditionnal="10") else
not(FlagC_i) when (iConditionnal="11") else
'0';
 
 
iChangePC <= ((Jump_i or Call_i or Return_i) and (iCondition))
or
(Interrupt_i) or (ReturnI_i);
-- Nouvelle valeur du PC
iPCin <= -- !TODO : Who has the priority, Jump or Interrupt?
(GEN_INT_VECTOR(GEN_WIDTH_PC-1 downto 0)) when (Interrupt_i='1') else
(iDataStackToPC) when (ReturnI_i='1') else
(std_ulogic_vector(UNSIGNED(iDataStackToPC) + 1)) when (Return_i='1') else
(aaa_i);
--------------------------------------------------------------------------------
-- Traitement des commande de Push & Pop de la stack
--------------------------------------------------------------------------------
iPush <= (iCondition and Call_i) or (Interrupt_i);
iPop <= (iCondition and Return_i) or (ReturnI_i);
--------------------------------------------------------------------------------
-- Instantiation du composant "cp_ProgramCounter"
--------------------------------------------------------------------------------
U_ProgramCounter : cp_ProgramCounter
generic map
(
GEN_WIDTH_PC => GEN_WIDTH_PC
)
port map(
--------------------------------------------------------------------------------
-- Signaux Systeme
--------------------------------------------------------------------------------
Clk_i => Clk_i,
Rst_i_n => Rst_i_n,
Enable_i => Enable_i,
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
PC_i => iPCin,
Change_i => iChangePC,
PC_o => iPC
);
 
--------------------------------------------------------------------------------
-- Instantiation du composant "cp_Stack"
--------------------------------------------------------------------------------
U_Stack : cp_Stack
generic map
(
GEN_WIDTH_PC => GEN_WIDTH_PC,
GEN_DETPH => GEN_DEPTH_STACK
)
port map(
--------------------------------------------------------------------------------
-- Signaux Systeme
--------------------------------------------------------------------------------
Clk_i => Clk_i,
Rst_i_n => Rst_i_n,
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
Data_i => iPC,
Data_o => iDataStackToPC,
Enable_i => Enable_i,
Push_i => iPush,
Pop_i => iPop
);
--------------------------------------------------------------------------------
-- Sorties
--------------------------------------------------------------------------------
PC_o <= iPC;
 
end rtl;
 
/copyblaze/rtl/vhdl/cpu/cp_Usefull_Pkg.vhd
0,0 → 1,128
--------------------------------------------------------------------------------
-- Company:
--
-- File: cp_Usefull_Pkg.vhd
--
-- Description:
-- projet copyBlaze
 
--
-- File history:
-- v1.0: 31/08/11: Creation
 
-- v1.2: 27/11/11: Ajout des fonctions OR_Func, AND_Func
--
-- Targeted device: ProAsic A3P250 VQFP100
-- Author: AbdAllah Meziti
--------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
--------------------------------------------------------------------------------
-- Package: Usefull_Pkg
--------------------------------------------------------------------------------
package Usefull_Pkg is
--- frequence of the fpga core
constant FREQ : real := 40.0e6;
constant FREQ_LOW : real := 10.0e6;
 
--- find minimum number of bits required to
--- represent N as an unsigned binary number
function log2_ceil(N: natural) return positive;
function log2(A: integer) return integer;
 
-- OR sur tout les bits d'un vecteur
function OR_Func (x : std_ulogic_vector) return std_ulogic;
-- AND sur tout les bits d'un vecteur
function AND_Func (x : std_ulogic_vector) return std_ulogic;
 
function ODD_Func (x : std_ulogic_vector) return std_ulogic;
end;
 
--------------------------------------------------------------------------------
-- Body: Usefull_Pkg
--------------------------------------------------------------------------------
package body Usefull_Pkg is
 
--- find minimum number of bits required to
--- represent N as an unsigned binary number
function log2_ceil(N: natural) return positive is
begin
if N < 2 then
return 1;
else
return 1 + log2_ceil(N/2);
end if;
end;
 
-- function log2_ceil(N : integer) return integer is
-- begin
-- if (N <= 2) then
-- return 1;
-- else
-- if (N mod 2 = 0) then
-- return 1 + log2_ceil(N/2);
-- else
-- return 1 + log2_ceil((N+1)/2);
-- end if;
-- end if;
-- end function log2_ceil;
 
-- function log2_ceil (constant x : natural) return positive is
--
-- variable v_tmp : natural := x;
-- variable v_ret : natural := 0;
-- variable v_line : integer;
--
-- begin -- function log2
--
-- while (v_tmp > 0) loop
-- v_tmp := v_tmp / 2;
-- v_ret := v_ret + 1;
-- end loop;
--
-- v_line := v_ret;
-- report "value: " & integer'image(v_line);
-- return v_ret;
-- end function log2_ceil;
 
function log2(A: integer) return integer is
begin
for I in 1 to 30 loop -- Works for up to 32 bit integers
if(2**I > A) then return(I-1); end if;
end loop;
return(30);
end;
-- OR sur tout les bits d'un vecteur
function OR_Func (x : std_ulogic_vector) return std_ulogic is
variable tmp : std_ulogic := '0';
begin
for j in x'range loop
tmp := tmp or x(j);
end loop;
return tmp;
end OR_Func;
 
-- AND sur tout les bits d'un vecteur
function AND_Func (x : std_ulogic_vector) return std_ulogic is
variable tmp : std_ulogic := '1';
begin
for j in x'range loop
tmp := tmp and x(j);
end loop;
return tmp;
end AND_Func;
 
function ODD_Func (x : std_ulogic_vector) return std_ulogic is
variable tmp : std_ulogic := '0';
begin
for j in x'range loop
tmp := tmp xor x(j);
end loop;
return tmp;
end ODD_Func;
 
end package body;
/copyblaze/rtl/vhdl/cpu/cp_Alu.vhd
0,0 → 1,234
--------------------------------------------------------------------------------
-- Company:
--
-- File: cp_Alu.vhd
--
-- Description:
-- projet copyblaze
-- Arithmetic, Logic, Shift, Rotate
--
-- File history:
-- v1.0: 07/10/11: Creation
--
-- Targeted device: ProAsic A3P250 VQFP100
-- Author: AbdAllah Meziti
--------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.Usefull_Pkg.all; -- Usefull Package
 
--------------------------------------------------------------------------------
-- Entity: cp_Alu
--
-- Description:
--
-- REMARQUE:
--
--
-- History:
-- 07/10/11 AM: Creation
-- ---------------------
-- xx/xx/xx AM:
--
--------------------------------------------------------------------------------
entity cp_Alu is
generic
(
GEN_WIDTH_DATA : positive := 8
);
port (
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
OperationSelect_i : in std_ulogic_vector(2 downto 0);
LogicOper_i : in std_ulogic_vector(1 downto 0);
ArithOper_i : in std_ulogic_vector(1 downto 0);
 
OperandSelect_i : in std_ulogic;
CY_i : in std_ulogic;
sX_i : in std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); --
sY_i : in std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); --
kk_i : in std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); --
ShiftBit_i : in std_ulogic_vector( 2 downto 0 );
ShiftSens_i : in std_ulogic;
Result_o : out std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); --
C_o : out std_ulogic;
Z_o : out std_ulogic
);
end cp_Alu;
 
--------------------------------------------------------------------------------
-- Architecture: RTL
-- of entity : cp_Alu
--------------------------------------------------------------------------------
architecture rtl of cp_Alu is
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
signal iOperand1 : std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
signal iOperand2 : std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
signal iOperand1Arith : std_ulogic_vector(GEN_WIDTH_DATA downto 0);
signal iOperand2Arith : std_ulogic_vector(GEN_WIDTH_DATA downto 0);
 
signal iShiftResult : std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
signal iLogicalResult : std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
signal iArithResult : std_ulogic_vector(GEN_WIDTH_DATA downto 0);
 
signal iTotalResult : std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
signal iShiftBit : std_ulogic;
 
signal iShiftC : std_ulogic;
signal iLogicC : std_ulogic;
signal iArithC : std_ulogic;
signal iArithCin : std_ulogic;
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
component cp_CLAAdder
generic
(
GEN_WIDTH_DATA : positive := 8
);
port (
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
CarryIn_i : in std_ulogic;
sX_i : in std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
sY_i : in std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
CarryOut_o : out std_ulogic;
Result_o : out std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0)
);
end component;
 
begin
 
iOperand1 <= sX_i;
iOperand2 <= sY_i when ( OperandSelect_i = '1' ) else
kk_i;
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
with ShiftBit_i select
iShiftBit <=
('0') when "110",
('1') when "111",
(CY_i) when "000",
iOperand1(GEN_WIDTH_DATA-1) when "010",
iOperand1(0) when "100",
 
'0' when others;
with ShiftSens_i select
iShiftResult <=
iOperand1(GEN_WIDTH_DATA-2 downto 0) & iShiftBit when '0', -- Left
iShiftBit & iOperand1(GEN_WIDTH_DATA-1 downto 1) when '1', -- Right
iOperand1 when others;
with ShiftSens_i select
iShiftC <=
iOperand1(GEN_WIDTH_DATA-1) when '0', -- Left
iOperand1(0) when '1', -- Right
'0' when others;
 
--------------------------------------------------------------------------------
-- Operation Logique
--------------------------------------------------------------------------------
with LogicOper_i select
iLogicalResult <=
iOperand2 when "00",
iOperand1 and iOperand2 when "01",
iOperand1 or iOperand2 when "10",
iOperand1 xor iOperand2 when "11",
iOperand1 when others;
 
iLogicC <= ODD_Func(iLogicalResult);
--------------------------------------------------------------------------------
-- Operation Arithmetique
--------------------------------------------------------------------------------
-- Instruction | #ADD/SUB | Include CY | Cin
-- ADD | 0 | 0 | 0
-- ADDCY | 0 | 1 | CY
-- SUB | 1 | 0 | 1
-- SUBCY | 1 | 1 | not CY
with ArithOper_i select
iArithCin <=
('0') when "00", -- ADD
(CY_i) when "01", -- ADDCY
('1') when "10", -- SUB
not(CY_i) when "11", -- SUBCY
('0') when others;
 
iOperand1Arith <= '0' & iOperand1;
-- A SUB B => A ADD (not(B) + 1)
iOperand2Arith <= not('0' & iOperand2) when (ArithOper_i(1)='1') else ('0' & iOperand2);
 
U_Adder : cp_CLAAdder
generic map
(
GEN_WIDTH_DATA => GEN_WIDTH_DATA+1
)
port map(
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
CarryIn_i => iArithCin ,
sX_i => iOperand1Arith ,
sY_i => iOperand2Arith ,
CarryOut_o => open ,
Result_o => iArithResult
);
iArithC <= iArithResult(GEN_WIDTH_DATA);
--------------------------------------------------------------------------------
-- Choix de l'operation
--------------------------------------------------------------------------------
with OperationSelect_i select
iTotalResult <=
iShiftResult when "000",
iLogicalResult when "001",
iArithResult(iTotalResult'range) when "010",
iOperand2 when "011",
iOperand1 when others;
 
--------------------------------------------------------------------------------
-- Resultats et Flags
--------------------------------------------------------------------------------
Result_o <= iTotalResult;
Z_o <= not ( OR_Func( iTotalResult ) );
with OperationSelect_i select
C_o <=
iShiftC when "000", -- (Shift/Rotate) :
iLogicC when "001", -- (Test) : Odd parity
iArithC when others; -- (Add/Sub/Compare) : Carry, Borrow
 
end rtl;
 
/copyblaze/rtl/vhdl/cpu/cp_Toggle.vhd
0,0 → 1,153
--------------------------------------------------------------------------------
-- Company:
--
-- File: cp_Toggle.vhd
--
-- Description:
-- projet copyblaze
-- Toggle horloge clock (divisor by 2)
--
-- File history:
-- v1.0: 07/10/11: Creation
-- v2.0: 25/10/11: Add Freeze Management
--
-- Targeted device: ProAsic A3P250 VQFP100
-- Author: AbdAllah Meziti
--------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.Usefull_Pkg.all; -- Usefull Package
 
--------------------------------------------------------------------------------
-- Entity: cp_Toggle
--
-- Description:
--
-- REMARQUE:
--
--
-- History:
-- 07/10/11 AM: Creation
-- ---------------------
-- xx/xx/xx AM:
--
--------------------------------------------------------------------------------
entity cp_Toggle is
port (
--------------------------------------------------------------------------------
-- Signaux Systeme
--------------------------------------------------------------------------------
 
 
 
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
Freeze_i : in std_ulogic;
 
Phase1_o : out std_ulogic;
Phase2_o : out std_ulogic
);
end cp_Toggle;
 
--------------------------------------------------------------------------------
-- Architecture: RTL
-- of entity : cp_Toggle
--------------------------------------------------------------------------------
architecture rtl of cp_Toggle is
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
type States_TYPE is
(
S_NORMAL , --
S_FREEZE -- for external "Freeze processor" signal
);
 
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
signal iPhase1 : std_ulogic;
signal iPhase2 : std_ulogic;
signal iPhase1Out : std_ulogic;
signal iPhase2Out : std_ulogic;
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
begin
 
--------------------------------------------------------------------------------
-- Process : Phase_Proc
-- Description: generate the Phase1 and Phase2 of the processor
--------------------------------------------------------------------------------
Phase_Proc : process(Rst_i_n, Clk_i)
begin
if ( Rst_i_n = '0' ) then
iPhase1 <= '0';
iPhase2 <= '0';
 
elsif ( rising_edge(Clk_i) ) then
iPhase1 <= not( iPhase1 );
iPhase2 <= iPhase1;
end if;
end process Phase_Proc;
 
--------------------------------------------------------------------------------
-- Process : Freeze_Proc
-- Description: if Freeze_i signal is active, then the processor exectution is freezed (stoped)
--------------------------------------------------------------------------------
Freeze_Proc : process(Rst_i_n, Clk_i)
begin
if ( Rst_i_n = '0' ) then
iFSM_State <= S_NORMAL;
 
elsif ( rising_edge(Clk_i) ) then
case iFSM_State is
when S_NORMAL =>
if ( ( iPhase2 = '1' ) and (Freeze_i = '1') ) then
iFSM_State <= S_FREEZE;
end if;
when S_FREEZE =>
if ( ( iPhase2 = '1' ) and (Freeze_i = '0') ) then
iFSM_State <= S_NORMAL;
end if;
end case;
 
end if;
end process Freeze_Proc;
 
with iFSM_State select
iPhase1Out <= iPhase1 when S_NORMAL,
'0' when S_FREEZE, -- Phase 1 to 0
'0' when others;
with iFSM_State select
iPhase2Out <= iPhase2 when S_NORMAL,
'0' when S_FREEZE, -- Phase 2 to 0
'0' when others;
 
Phase1_o <= iPhase1Out;
Phase2_o <= iPhase2Out;
 
end rtl;
 
/copyblaze/rtl/vhdl/cpu/cp_FullAdder.vhd
0,0 → 1,86
--------------------------------------------------------------------------------
-- Company:
--
-- File: cp_FullAdder.vhd
--
-- Description:
-- projet copyblaze
-- 1 bit Full adder
--
-- File history:
-- v1.0: 14/10/11: Creation
--
-- Targeted device: ProAsic A3P250 VQFP100
-- Author: AbdAllah Meziti
--------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.Usefull_Pkg.all; -- Usefull Package
 
--------------------------------------------------------------------------------
-- Entity: cp_FullAdder
--
-- Description:
--
-- REMARQUE:
--
--
-- History:
-- 14/10/11 AM: Creation
-- ---------------------
-- xx/xx/xx AM:
--
--------------------------------------------------------------------------------
entity cp_FullAdder is
port (
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
Ci_i : in std_ulogic;
A_i : in std_ulogic;
B_i : in std_ulogic;
 
Co_o : out std_ulogic;
S_o : out std_ulogic
);
end cp_FullAdder;
 
--------------------------------------------------------------------------------
-- Architecture: RTL
-- of entity : cp_FullAdder
--------------------------------------------------------------------------------
architecture rtl of cp_FullAdder is
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
begin
 
--------------------------------------------------------------------------------
-- Full adder
--------------------------------------------------------------------------------
-- SUM
S_o <= A_i xor B_i xor Ci_i;
-- CARRY
Co_o <= (A_i and B_i) or (B_i and Ci_i) or (A_i and Ci_i);
 
end rtl;
 
/copyblaze/rtl/vhdl/cpu/cp_copyBlaze_ecoSystem.vhd
0,0 → 1,277
--------------------------------------------------------------------------------
-- Company:
--
-- File: cp_copyBlaze_ecoSystem.vhd
--
-- Description:
-- projet copyblaze
-- copyBlaze processor + ROM => system
--
-- File history:
-- v1.0: 11/10/11: Creation
--
-- Targeted device: ProAsic A3P250 VQFP100
-- Author: AbdAllah Meziti
--------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.Usefull_Pkg.all; -- Usefull Package
 
--------------------------------------------------------------------------------
-- Entity: cp_copyBlaze_ecoSystem
--
-- Description:
--
-- REMARQUE:
--
--
-- History:
-- 11/10/11 AM: Creation
-- ---------------------
-- xx/xx/xx AM:
--
--------------------------------------------------------------------------------
entity cp_copyBlaze_ecoSystem is
generic
(
GEN_WIDTH_DATA : positive := 8;
GEN_WIDTH_PC : positive := 10;
GEN_WIDTH_INST : positive := 18;
GEN_DEPTH_STACK : positive := 15; -- Taille (en octet) de la Stack
GEN_DEPTH_BANC : positive := 16; -- Taille (en octet) du Banc Register
GEN_DEPTH_SCRATCH : positive := 64; -- Taille (en octet) du Scratch Pad
GEN_INT_VECTOR : std_ulogic_vector(11 downto 0) := x"3FF"
);
Port (
--------------------------------------------------------------------------------
-- Signaux Systeme
--------------------------------------------------------------------------------
Clk_i : in std_ulogic;
--Rst_i_n : in std_ulogic;
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
Interrupt_i : in std_ulogic;
Interrupt_Ack_o : out std_ulogic;
IN_PORT_i : in std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
OUT_PORT_o : out std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
PORT_ID_o : out std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
READ_STROBE_o : out std_ulogic;
WRITE_STROBE_o : out std_ulogic;
--------------------------------------------------------------------------------
-- Signaux WishBone
--------------------------------------------------------------------------------
Freeze_i : in std_ulogic;
--------------------------------------------------------------------------------
-- Signaux Wishbone Interface
--------------------------------------------------------------------------------
-- RST_I : in std_ulogic;
-- CLK_I : in std_ulogic;
ADR_O : out std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
DAT_I : in std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
DAT_O : out std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
WE_O : out std_ulogic;
SEL_O : out std_ulogic_vector(1 downto 0);
STB_O : out std_ulogic;
ACK_I : in std_ulogic;
CYC_O : out std_ulogic
);
end cp_copyBlaze_ecoSystem;
 
--------------------------------------------------------------------------------
-- Architecture: RTL
-- of entity : cp_copyBlaze_ecoSystem
--------------------------------------------------------------------------------
architecture rtl of cp_copyBlaze_ecoSystem is
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
constant RESET_LENGTH : positive := 7;
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
component cp_copyBlaze
generic
(
GEN_WIDTH_DATA : positive := 8;
GEN_WIDTH_PC : positive := 10;
GEN_WIDTH_INST : positive := 18;
GEN_DEPTH_STACK : positive := 15; -- Taille (en octet) de la Stack
GEN_DEPTH_BANC : positive := 16; -- Taille (en octet) du Banc Register
GEN_DEPTH_SCRATCH : positive := 64; -- Taille (en octet) du Scratch Pad
GEN_INT_VECTOR : std_ulogic_vector(11 downto 0) := x"3FF" -- Interrupt Vector
);
port (
--------------------------------------------------------------------------------
-- Signaux Systeme
--------------------------------------------------------------------------------
 
 
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
Address_o : out std_ulogic_vector(GEN_WIDTH_PC-1 downto 0);
Instruction_i : in std_ulogic_vector(GEN_WIDTH_INST-1 downto 0);
Interrupt_i : in std_ulogic; --
Interrupt_Ack_o : out std_ulogic; --
IN_PORT_i : in std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); --
OUT_PORT_o : out std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); --
PORT_ID_o : out std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); --
READ_STROBE_o : out std_ulogic;
WRITE_STROBE_o : out std_ulogic;
--------------------------------------------------------------------------------
-- Signaux Speciaux
--------------------------------------------------------------------------------
Freeze_i : in std_ulogic;
--------------------------------------------------------------------------------
-- Signaux Wishbone Interface
--------------------------------------------------------------------------------
--RST_I : in std_ulogic;
--CLK_I : in std_ulogic;
ADR_O : out std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
DAT_I : in std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
DAT_O : out std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
WE_O : out std_ulogic;
SEL_O : out std_ulogic_vector(1 downto 0);
STB_O : out std_ulogic;
ACK_I : in std_ulogic;
CYC_O : out std_ulogic
);
end component;
 
component cp_ROM_Code
generic
(
GEN_WIDTH_PC : positive := 10;
GEN_WIDTH_INST : positive := 18
);
port(
Clk_i : in std_ulogic;
Address_i : in std_ulogic_vector(GEN_WIDTH_PC-1 downto 0);
Dout_o : out std_ulogic_vector(GEN_WIDTH_INST-1 downto 0)
);
end component;
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
signal iAddress : std_ulogic_vector(9 downto 0);
signal iInstruction : std_ulogic_vector(17 downto 0);
signal iReset : std_ulogic := '0';
signal iReset_counter : natural range 0 to RESET_LENGTH := RESET_LENGTH; -- VERY BAD SOLUTION
 
begin
 
-- ************************** --
-- The copyBlaze CPU instance --
-- ************************** --
processor: cp_copyBlaze
generic map
(
GEN_WIDTH_DATA => GEN_WIDTH_DATA,
GEN_WIDTH_PC => GEN_WIDTH_PC,
GEN_WIDTH_INST => GEN_WIDTH_INST,
 
GEN_DEPTH_STACK => GEN_DEPTH_STACK,
GEN_DEPTH_BANC => GEN_DEPTH_BANC,
 
GEN_DEPTH_SCRATCH => GEN_DEPTH_SCRATCH,
GEN_INT_VECTOR => GEN_INT_VECTOR
)
port map(
--------------------------------------------------------------------------------
-- Signaux Systeme
--------------------------------------------------------------------------------
Clk_i => Clk_i,
Rst_i_n => iReset,
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
Address_o => iAddress,
Instruction_i => iInstruction,
Interrupt_i => Interrupt_i,
Interrupt_Ack_o => Interrupt_Ack_o,
IN_PORT_i => IN_PORT_i,
OUT_PORT_o => OUT_PORT_o,
PORT_ID_o => PORT_ID_o,
READ_STROBE_o => READ_STROBE_o,
WRITE_STROBE_o => WRITE_STROBE_o,
--------------------------------------------------------------------------------
-- Signaux Speciaux
--------------------------------------------------------------------------------
Freeze_i => Freeze_i,
--------------------------------------------------------------------------------
-- Signaux Wishbone Interface
--------------------------------------------------------------------------------
--RST_I => RST_I,
--CLK_I => CLK_I,
 
ADR_O => ADR_O,
DAT_I => DAT_I,
DAT_O => DAT_O,
WE_O => WE_O,
SEL_O => SEL_O,
 
STB_O => STB_O,
ACK_I => ACK_I,
CYC_O => CYC_O
);
 
-- *************** --
-- ROM code memory --
-- *************** --
program : cp_ROM_Code
generic map
(
GEN_WIDTH_PC => GEN_WIDTH_PC,
GEN_WIDTH_INST => GEN_WIDTH_INST
)
port map
(
Clk_i => Clk_i,
Address_i => iAddress,
Dout_o => iInstruction
);
 
--------------------------------------------------------------------------------
-- Process : ProcessorReset_Proc
-- Description: Generate the reset of the processor
--------------------------------------------------------------------------------
ProcessorReset_Proc : process(Clk_i)
begin
if ( rising_edge(Clk_i) ) then
if ( iReset_counter = 0 ) then
iReset <= '1';
else
iReset <= '0';
iReset_counter <= iReset_counter - 1;
end if;
end if;
end process ProcessorReset_Proc;
 
end rtl;
/copyblaze/rtl/vhdl/cpu/cp_DecodeControl.vhd
0,0 → 1,300
--------------------------------------------------------------------------------
-- Company:
--
-- File: cp_DecodeControl.vhd
--
-- Description:
-- projet copyblaze
-- instruction decoding & Operational control
--
-- File history:
-- v1.0: 21/10/11: Creation
-- v2.0: 26/10/11: Add Wishbone instructions
--
-- Targeted device: ProAsic A3P250 VQFP100
-- Author: AbdAllah Meziti
--------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.Usefull_Pkg.all; -- Usefull Package
 
--------------------------------------------------------------------------------
-- Entity: cp_DecodeControl
--
-- Description:
--
-- REMARQUE:
--
--
-- History:
-- 21/10/11 AM: Creation
-- ---------------------
-- xx/xx/xx AM:
--
--------------------------------------------------------------------------------
entity cp_DecodeControl is
generic
(
GEN_WIDTH_INST : positive := 18;
GEN_WIDTH_PC : positive := 10;
 
GEN_DEPTH_BANC : positive := 16; -- Taille (en octet) du Banc Register
GEN_DEPTH_SCRATCH : positive := 64 -- Taille (en octet) du Scratch Pad
);
port (
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
--Phase1_i : in std_ulogic;
Phase2_i : in std_ulogic;
IEvent_i : in std_ulogic;
Instruction_i : in std_ulogic_vector(GEN_WIDTH_INST-1 downto 0);
 
Fetch_o : out std_ulogic;
Input_o : out std_ulogic;
Ouput_o : out std_ulogic;
Jump_o : out std_ulogic;
Call_o : out std_ulogic;
Return_o : out std_ulogic;
ReturnI_o : out std_ulogic;
IEWrite_o : out std_ulogic;
BancWrite_o : out std_ulogic;
ScratchWrite_o : out std_ulogic;
OperationSelect_o : out std_ulogic_vector(2 downto 0);
FlagsWrite_o : out std_ulogic;
FlagsPush_o : out std_ulogic;
FlagsPop_o : out std_ulogic;
aaa_o : out std_ulogic_vector(GEN_WIDTH_PC-1 downto 0);
kk_o : out std_ulogic_vector(7 downto 0);
ss_o : out std_ulogic_vector(log2(GEN_DEPTH_SCRATCH)-1 downto 0);
pp_o : out std_ulogic_vector(7 downto 0);
 
SxPtr_o : out std_ulogic_vector(log2(GEN_DEPTH_BANC)-1 downto 0);
SyPtr_o : out std_ulogic_vector(log2(GEN_DEPTH_BANC)-1 downto 0);
 
OperandSelect_o : out std_ulogic;
ArithOper_o : out std_ulogic_vector(1 downto 0);
LogicOper_o : out std_ulogic_vector(1 downto 0);
ShiftBit_o : out std_ulogic_vector(2 downto 0);
ShiftSens_o : out std_ulogic;
ConditionCtrl_o : out std_ulogic_vector(2 downto 0);
IEValue_o : out std_ulogic;
wbRdSing_o : out std_ulogic;
wbWrSing_o : out std_ulogic
);
end cp_DecodeControl;
 
--------------------------------------------------------------------------------
-- Architecture: RTL
-- of entity : cp_DecodeControl
--------------------------------------------------------------------------------
architecture rtl of cp_DecodeControl is
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
signal iInstruction : std_ulogic_vector(GEN_WIDTH_INST-1 downto 0);
 
alias iInstructionCode : std_ulogic_vector(4 downto 0) is iInstruction(17 downto 13);
-- **** --
-- PATH --
-- **** --
alias iaaa : std_ulogic_vector(GEN_WIDTH_PC-1 downto 0) is iInstruction(GEN_WIDTH_PC-1 downto 0);
alias ikk : std_ulogic_vector(7 downto 0) is iInstruction(7 downto 0);
alias iss : std_ulogic_vector(log2(GEN_DEPTH_SCRATCH)-1 downto 0) is iInstruction(log2(GEN_DEPTH_SCRATCH)-1 downto 0);
alias ipp : std_ulogic_vector(7 downto 0) is iInstruction(7 downto 0);
 
alias iSxPtr : std_ulogic_vector(log2(GEN_DEPTH_BANC)-1 downto 0) is iInstruction(8+log2(GEN_DEPTH_BANC)-1 downto 8);
alias iSyPtr : std_ulogic_vector(log2(GEN_DEPTH_BANC)-1 downto 0) is iInstruction(4+log2(GEN_DEPTH_BANC)-1 downto 4);
-- ******* --
-- CONTROL --
-- ******* --
-- Alu
signal iOperationSelect : std_ulogic_vector(2 downto 0);
alias iOperandSelect : std_ulogic is iInstruction(12);
alias iArithOper : std_ulogic_vector(1 downto 0) is iInstruction(14 downto 13);
alias iLogicOper : std_ulogic_vector(1 downto 0) is iInstruction(14 downto 13);
alias iShiftBit : std_ulogic_vector(2 downto 0) is iInstruction(2 downto 0);
alias iShiftSens : std_ulogic is iInstruction(3);
-- Banc
signal iBancWrite : std_ulogic;
-- Scratch
signal iScratchWrite : std_ulogic;
-- Flags
signal iFlagsWrite ,
iFlagsPush ,
iFlagsPop : std_ulogic;
 
signal iIEWrite : std_ulogic;
signal iAddSub ,
iCompare ,
iLoad ,
iLogic ,
iTest ,
iShift ,
iStore ,
iFetch ,
iInput ,
iOuput ,
iJump ,
iCall ,
iReturn ,
iReturnI ,
iSetInterrupt ,
-- Wishbone instructions
iWBWrSing ,
iWBRdSing
: std_ulogic;
-- Flow
alias iConditionCtrl : std_ulogic_vector(2 downto 0) is iInstruction(12 downto 10);
-- Int
alias iIEValue : std_ulogic is iInstruction(0);
signal iIEvent : std_ulogic;
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
begin
--------------------------------------------------------------------------------
-- DECODER
--------------------------------------------------------------------------------
iIEvent <= IEvent_i;
 
-- Preempte the instruction in case of interrupt event
iInstruction <= (others => '1') when (iIEvent='1') else Instruction_i;
 
--------------------------------------------------------------------------------
-- INSTRUCTION DECODER
--------------------------------------------------------------------------------
-- Arithmetic Group
iAddSub <= '1' when ((iInstructionCode = '0' & x"C") or
(iInstructionCode = '0' & x"D") or
(iInstructionCode = '0' & x"E") or
(iInstructionCode = '0' & x"F")) else '0';
iCompare <= '1' when ( iInstructionCode = '0' & x"A" ) else '0';
 
-- Logic Group
iLoad <= '1' when ( iInstructionCode = '0' & x"0" ) else '0';
iLogic <= '1' when ((iInstructionCode = '0' & x"5") or
(iInstructionCode = '0' & x"6") or
(iInstructionCode = '0' & x"7")) else '0';
iTest <= '1' when ( iInstructionCode = '0' & x"9" ) else '0';
 
-- Shift and Rotate Group
iShift <= '1' when ( iInstructionCode = '1' & x"0" ) else '0';
 
-- Storage Group
iStore <= '1' when ( iInstructionCode = '1' & x"7" ) else '0';
iFetch <= '1' when ( iInstructionCode = '0' & x"3" ) else '0';
 
-- Input/Ouput Group
iInput <= '1' when ( iInstructionCode = '0' & x"2" ) else '0';
iOuput <= '1' when ( iInstructionCode = '1' & x"6" ) else '0';
-- Program Control Group
iJump <= '1' when ( iInstructionCode = '1' & x"A" ) else '0';
iCall <= '1' when ( iInstructionCode = '1' & x"8" ) else '0';
iReturn <= '1' when ( iInstructionCode = '1' & x"5" ) else '0';
 
-- Interrupt Group
iReturnI <= '1' when ( iInstructionCode = '1' & x"C" ) else '0';
-- TODO : The ENABLE INTERRUPT instruction must clear the "iIEvent" bit if is set while the interrupts are disabled.
iSetInterrupt <= '1' when ( iInstructionCode = '1' & x"E" ) else '0';
 
-- Reserved for extension 6
-- STAR = '0' & "B"
-- TESTCY = '0' & "7"
-- COMPARECY = '0' & "F"
-- REGBANK = '1' & "B"
-- OUTPUTK = '1' & "5"
-- CALL@ = '1' & "2"
-- LOAD&RETURN = '1' & "0"
-- HWBUILD = '0' & "A"
-- Wishbone instructions
iWBRdSing <= '1' when ( iInstructionCode = '0' & x"1" ) else '0';
iWBWrSing <= '1' when ( iInstructionCode = '0' & x"4" ) else '0';
--------------------------------------------------------------------------------
-- CONTROL SIGNAL
--------------------------------------------------------------------------------
-- Flow
iIEWrite <= (Phase2_i and (iSetInterrupt or iReturnI));
-- Banc
iBancWrite <= (Phase2_i and (iAddSub or iLoad or iLogic or iShift or iFetch or iInput));
-- Scratch
iScratchWrite <= (Phase2_i and (iStore));
-- Alu
iOperationSelect <= "000" when (iShift='1') else
"001" when (iLogic='1' or iTest='1') else
"010" when (iAddSub='1' or iCompare='1') else
"011" when (iLoad='1') else
"111";
 
-- Flags
iFlagsWrite <= (Phase2_i and (iAddSub or iCompare or iLogic or iTest or iShift));
iFlagsPush <= (Phase2_i and (IEvent_i));
iFlagsPop <= (Phase2_i and (iReturnI));
 
--------------------------------------------------------------------------------
-- Outputs
--------------------------------------------------------------------------------
Fetch_o <= iFetch ;
Input_o <= iInput ;
Ouput_o <= iOuput ;
Jump_o <= iJump ;
Call_o <= iCall ;
Return_o <= iReturn ;
ReturnI_o <= iReturnI ;
IEWrite_o <= iIEWrite ;
BancWrite_o <= iBancWrite ;
ScratchWrite_o <= iScratchWrite ;
OperationSelect_o <= iOperationSelect ;
FlagsWrite_o <= iFlagsWrite ;
FlagsPush_o <= iFlagsPush ;
FlagsPop_o <= iFlagsPop ;
 
aaa_o <= iaaa ;
kk_o <= ikk ;
ss_o <= iss ;
pp_o <= ipp ;
 
SxPtr_o <= iSxPtr ;
SyPtr_o <= iSyPtr ;
OperandSelect_o <= iOperandSelect ;
ArithOper_o <= iArithOper ;
LogicOper_o <= iLogicOper ;
ShiftBit_o <= iShiftBit ;
ShiftSens_o <= iShiftSens ;
ConditionCtrl_o <= iConditionCtrl ;
IEValue_o <= iIEValue ;
wbRdSing_o <= iWBRdSing ;
wbWrSing_o <= iWBWrSing ;
 
end rtl;
/copyblaze/rtl/vhdl/cpu/cp_Stack.vhd
0,0 → 1,157
--------------------------------------------------------------------------------
-- Company:
--
-- File: cp_Stack.vhd
--
-- Description:
-- projet copyblaze
-- Program Counter stack
--
-- File history:
-- v1.0: 07/10/11: Creation
--
-- Targeted device: ProAsic A3P250 VQFP100
-- Author: AbdAllah Meziti
--------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.Usefull_Pkg.all; -- Usefull Package
 
--------------------------------------------------------------------------------
-- Entity: cp_Stack
--
-- Description:
--
-- REMARQUE:
--
--
-- History:
-- 07/10/11 AM: Creation
-- ---------------------
-- xx/xx/xx AM:
--
--------------------------------------------------------------------------------
entity cp_Stack is
generic
(
GEN_WIDTH_PC : positive := 8;
GEN_DETPH : positive := 15
);
port (
--------------------------------------------------------------------------------
-- Signaux Systeme
--------------------------------------------------------------------------------
 
 
 
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
Data_i : in std_ulogic_vector(GEN_WIDTH_PC-1 downto 0); --
Data_o : out std_ulogic_vector(GEN_WIDTH_PC-1 downto 0); --
Enable_i : in std_ulogic;
Push_i : in std_ulogic;
Pop_i : in std_ulogic
);
end cp_Stack;
 
--------------------------------------------------------------------------------
-- Architecture: RTL
-- of entity : cp_Stack
--------------------------------------------------------------------------------
architecture rtl of cp_Stack is
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
type RAM_TYPE is array (0 to GEN_DETPH-1) of std_ulogic_vector(GEN_WIDTH_PC-1 downto 0);--(Data_i'range);
 
signal iStackMem : RAM_TYPE;
signal iStackEn : std_ulogic;
 
signal iPointer : natural range 0 to GEN_DETPH-1;
signal iPtrUp : std_ulogic;
signal iPtrDown : std_ulogic;
signal iTempo : std_ulogic_vector(GEN_WIDTH_PC-1 downto 0);
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
begin
iStackEn <= not(Enable_i) and Push_i;
--------------------------------------------------------------------------------
-- Process : Stack_Proc
-- Description: Stack Memory
--------------------------------------------------------------------------------
Stack_Proc : process(Rst_i_n, Clk_i)
begin
if ( Rst_i_n = '0' ) then
for i in 0 to GEN_DETPH-1 loop
iStackMem(i) <= (others=>'0');
end loop;
iTempo <= (others=>'0');
elsif ( rising_edge(Clk_i) ) then
if ( iPtrUp = '1' ) then
iTempo <= Data_i;
end if;
if ( iStackEn = '1' ) then
iStackMem( iPointer ) <= iTempo;
end if;
end if;
end process Stack_Proc;
iPtrUp <= Enable_i and Push_i;
iPtrDown <= Enable_i and Pop_i;
--------------------------------------------------------------------------------
-- Process : Ptr_Proc
-- Description: Stack pointer
--------------------------------------------------------------------------------
Ptr_Proc : process(Rst_i_n, Clk_i)
begin
if ( Rst_i_n = '0' ) then
iPointer <= GEN_DETPH-1;
elsif ( rising_edge(Clk_i) ) then
if ( iPtrUp = '1' ) then
if ( iPointer + 1 = GEN_DETPH ) then
iPointer <= 0;
else
iPointer <= (iPointer + 1) ;
end if;
end if;
if ( iPtrDown = '1' ) then
if ( iPointer = 0 ) then
iPointer <= GEN_DETPH-1;
else
iPointer <= (iPointer - 1) ;
end if;
end if;
end if;
end process Ptr_Proc;
 
Data_o <= iStackMem( iPointer );
 
end rtl;
 
/copyblaze/rtl/vhdl/cpu/cp_ProgramCounter.vhd
0,0 → 1,110
--------------------------------------------------------------------------------
-- Company:
--
-- File: cp_ProgramCounter.vhd
--
-- Description:
-- projet copyblaze
-- Program Counter management
--
-- File history:
-- v1.0: 04/10/11: Creation
-- v1.1: 12/10/11: Modification du traitement des conditions de saut
--
-- Targeted device: ProAsic A3P250 VQFP100
-- Author: AbdAllah Meziti
--------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.Usefull_Pkg.all; -- Usefull Package
 
--------------------------------------------------------------------------------
-- Entity: cp_ProgramCounter
--
-- Description:
--
-- REMARQUE:
--
--
-- History:
-- 04/10/11 AM: Creation
-- ---------------------
-- xx/xx/xx AM:
--
--------------------------------------------------------------------------------
entity cp_ProgramCounter is
generic
(
GEN_WIDTH_PC : positive := 8
);
port (
--------------------------------------------------------------------------------
-- Signaux Systeme
--------------------------------------------------------------------------------
 
 
 
Enable_i : in std_ulogic;
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
PC_i : in std_ulogic_vector(GEN_WIDTH_PC-1 downto 0);
Change_i : in std_ulogic;
 
PC_o : out std_ulogic_vector(GEN_WIDTH_PC-1 downto 0)
);
end cp_ProgramCounter;
 
--------------------------------------------------------------------------------
-- Architecture: RTL
-- of entity : cp_ProgramCounter
--------------------------------------------------------------------------------
architecture rtl of cp_ProgramCounter is
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
signal iPC : std_ulogic_vector(GEN_WIDTH_PC-1 downto 0);
signal iPcNext : std_ulogic_vector(GEN_WIDTH_PC-1 downto 0);
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
begin
 
 
iPcNext <= (PC_i) when ( Change_i = '1' ) else
std_ulogic_vector(UNSIGNED(iPC) + 1);
 
--------------------------------------------------------------------------------
-- Process : PC_Proc
-- Description:
--------------------------------------------------------------------------------
PC_Proc : process(Rst_i_n, Clk_i)
begin
if ( Rst_i_n = '0' ) then
iPC <= (others=>'0');
elsif ( rising_edge(Clk_i) ) then
if (Enable_i = '1') then
iPC <= iPcNext;
end if;
end if;
end process PC_Proc;
 
PC_o <= iPC;
 
end rtl;
 
/copyblaze/rtl/vhdl/cpu/cp_BancRegister.vhd
0,0 → 1,118
--------------------------------------------------------------------------------
-- Company:
--
-- File: cp_BancRegister.vhd
--
-- Description:
-- projet copyblaze
-- Banc Registers
--
-- File history:
-- v1.0: 10/10/11: Creation
--
-- Targeted device: ProAsic A3P250 VQFP100
-- Author: AbdAllah Meziti
--------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.Usefull_Pkg.all; -- Usefull Package
 
--------------------------------------------------------------------------------
-- Entity: cp_BancRegister
--
-- Description:
--
-- REMARQUE:
--
--
-- History:
-- 10/10/11 AM: Creation
-- ---------------------
-- xx/xx/xx AM:
--
--------------------------------------------------------------------------------
entity cp_BancRegister is
generic
(
GEN_WIDTH_DATA : positive := 8;
GEN_DEPTH_BANC : positive := 16
);
port (
--------------------------------------------------------------------------------
-- Signaux Systeme
--------------------------------------------------------------------------------
 
 
 
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
SxPtr_i : in std_ulogic_vector(log2(GEN_DEPTH_BANC)-1 downto 0);
SyPtr_i : in std_ulogic_vector(log2(GEN_DEPTH_BANC)-1 downto 0);
Write_i : in std_ulogic;
SxData_i : in std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); --
SxData_o : out std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); --
SyData_o : out std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0)
);
end cp_BancRegister;
 
--------------------------------------------------------------------------------
-- Architecture: RTL
-- of entity : cp_BancRegister
--------------------------------------------------------------------------------
architecture rtl of cp_BancRegister is
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
type RAM_TYPE is array (0 to GEN_DEPTH_BANC-1) of std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
 
signal iBancRegMem : RAM_TYPE;
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
begin
--------------------------------------------------------------------------------
-- Process : BancReg_Proc
-- Description: BancRegister Memory
--------------------------------------------------------------------------------
BancReg_Proc : process(Rst_i_n, Clk_i)
begin
if ( Rst_i_n = '0' ) then
for i in 0 to GEN_DEPTH_BANC-1 loop
iBancRegMem(i) <= (others=>'0');
end loop;
 
elsif ( rising_edge(Clk_i) ) then
if ( Write_i = '1' ) then
iBancRegMem( to_integer(unsigned(SxPtr_i)) ) <= SxData_i;
end if;
end if;
end process BancReg_Proc;
 
SxData_o <= iBancRegMem( to_integer(unsigned(SxPtr_i)) );
SyData_o <= iBancRegMem( to_integer(unsigned(SyPtr_i)) );
 
end rtl;
 
/copyblaze/rtl/vhdl/cpu/cp_copyBlaze.vhd
0,0 → 1,814
--------------------------------------------------------------------------------
-- Company:
--
-- File: cp_copyBlaze.vhd
--
-- Description:
-- projet copyblaze
-- copyBlaze processor
--
-- File history:
-- v1.0: 10/10/11: Creation
-- v1.1: 24/10/11: Add the "Decode & Control" module
--
-- Targeted device: ProAsic A3P250 VQFP100
-- Author: AbdAllah Meziti
--------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.Usefull_Pkg.all; -- Usefull Package
 
--------------------------------------------------------------------------------
-- Entity: cp_copyBlaze
--
-- Description:
--
-- REMARQUE:
--
--
-- History:
-- 10/10/11 AM: Creation
-- ---------------------
-- xx/xx/xx AM:
--
--------------------------------------------------------------------------------
entity cp_copyBlaze is
generic
(
GEN_WIDTH_DATA : positive := 8;
GEN_WIDTH_PC : positive := 10;
GEN_WIDTH_INST : positive := 18;
GEN_DEPTH_STACK : positive := 15; -- Taille (en octet) de la Stack
GEN_DEPTH_BANC : positive := 16; -- Taille (en octet) du Banc Register
GEN_DEPTH_SCRATCH : positive := 64; -- Taille (en octet) du Scratch Pad
GEN_INT_VECTOR : std_ulogic_vector(11 downto 0) := x"3FF" -- Interrupt Vector
);
port (
--------------------------------------------------------------------------------
-- Signaux Systeme
--------------------------------------------------------------------------------
 
 
 
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
Address_o : out std_ulogic_vector(GEN_WIDTH_PC-1 downto 0);
Instruction_i : in std_ulogic_vector(GEN_WIDTH_INST-1 downto 0);
Interrupt_i : in std_ulogic; --
Interrupt_Ack_o : out std_ulogic; --
IN_PORT_i : in std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); --
OUT_PORT_o : out std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); --
PORT_ID_o : out std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); --
READ_STROBE_o : out std_ulogic;
WRITE_STROBE_o : out std_ulogic;
--------------------------------------------------------------------------------
-- Signaux Speciaux
--------------------------------------------------------------------------------
Freeze_i : in std_ulogic;
--------------------------------------------------------------------------------
-- Signaux Wishbone Interface
--------------------------------------------------------------------------------
-- RST_I : in std_ulogic;
-- CLK_I : in std_ulogic;
ADR_O : out std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
DAT_I : in std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
DAT_O : out std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
WE_O : out std_ulogic;
SEL_O : out std_ulogic_vector(1 downto 0);
 
STB_O : out std_ulogic;
ACK_I : in std_ulogic;
CYC_O : out std_ulogic
);
end cp_copyBlaze;
 
--------------------------------------------------------------------------------
-- Architecture: RTL
-- of entity : cp_copyBlaze
--------------------------------------------------------------------------------
architecture rtl of cp_copyBlaze is
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
signal iPhase1 : std_ulogic;
signal iPhase2 : std_ulogic;
 
-- **** --
-- PATH --
-- **** --
signal iaaa : std_ulogic_vector(GEN_WIDTH_PC-1 downto 0) ;
signal ikk : std_ulogic_vector(7 downto 0) ;
signal iss : std_ulogic_vector(log2(GEN_DEPTH_SCRATCH)-1 downto 0) ;
signal ipp : std_ulogic_vector(7 downto 0) ;
-- Flags
signal iZ : std_ulogic;
signal iC : std_ulogic;
signal iZi : std_ulogic;
signal iCi : std_ulogic;
-- Alu
signal iAluResult : std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
-- Banc
signal iSxDataIn : std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
signal iSxData : std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
signal iSyData : std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
signal iSxPtr : std_ulogic_vector(log2(GEN_DEPTH_BANC)-1 downto 0);
signal iSyPtr : std_ulogic_vector(log2(GEN_DEPTH_BANC)-1 downto 0);
-- Scratch
signal iScratchPtr : std_ulogic_vector(log2(GEN_DEPTH_SCRATCH)-1 downto 0);
signal iScratchDataOut : std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
-- ******* --
-- CONTROL --
-- ******* --
-- Banc
signal iBancWriteOP ,
iBancWrite : std_ulogic;
-- Scratch
signal iScratchWrite : std_ulogic;
signal iFetch : std_ulogic;
signal iInput : std_ulogic;
signal iOuput : std_ulogic;
-- Alu
signal iOperationSelect : std_ulogic_vector(2 downto 0);
signal iOperandSelect : std_ulogic;
signal iArithOper : std_ulogic_vector(1 downto 0);
signal iLogicOper : std_ulogic_vector(1 downto 0);
signal iShiftBit : std_ulogic_vector(2 downto 0);
signal iShiftSens : std_ulogic ;
-- Flags
signal iFlagsWrite ,
iFlagsPush ,
iFlagsPop : std_ulogic;
-- Flow
signal iConditionCtrl : std_ulogic_vector(2 downto 0);
signal iJump ,
iCall ,
iReturn ,
iReturnI : std_ulogic;
signal iPcEnable : std_ulogic;
 
-- Int
signal iIEvent : std_ulogic; -- Interrupt Event Flags
signal iIEWrite ,
iIEValue : std_ulogic;
 
-- System
signal iFreeze : std_ulogic; -- Freeze the processor
 
--------------------------------------------------------------------------------
-- WISHBONE
--------------------------------------------------------------------------------
-- Signaux Wishbone Interface
-- signal iwbRST_I : std_ulogic;
-- signal iwbCLK_I : std_ulogic;
 
signal iwbADR_O : std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
signal iwbDAT_I ,
iwbDAT : std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
signal iwbDAT_O : std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
signal iwbWE_O : std_ulogic;
signal iwbSEL_O : std_ulogic_vector(1 downto 0);
 
signal iwbSTB_O : std_ulogic;
signal iwbACK_I : std_ulogic;
signal iwbCYC : std_ulogic;
 
-- Signaux de management du Wishbone
signal iWbWrSing : std_ulogic; -- "Single Write Cycle" Wishbone instruction
signal iWbRdSing : std_ulogic; -- "Single Read Cycle" Wishbone instruction
 
--signal iWB_inst : std_ulogic; -- WB Instruction
signal iWB_validHandshake : std_ulogic; -- WB valid Handshake
signal iWB_validPC : std_ulogic; -- WB valid PC increment
signal iWB_validOperand : std_ulogic; -- WB valid Operation
 
 
-- type wbStates_TYPE is
-- (
-- S_WB_RESET ,
--
-- S_WB_RD ,
-- S_WB_RD_ACK ,
--
-- S_WB_WR ,
-- S_WB_WR_ACK
-- );
-- signal iWbFSM : wbStates_TYPE;
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
component cp_Toggle
port (
--------------------------------------------------------------------------------
-- Signaux Systeme
--------------------------------------------------------------------------------
 
 
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
Freeze_i : in std_ulogic;
 
Phase1_o : out std_ulogic;
Phase2_o : out std_ulogic
);
end component;
 
component cp_Interrupt
port (
--------------------------------------------------------------------------------
-- Signaux Systeme
--------------------------------------------------------------------------------
 
 
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
IEWrite_i : in std_ulogic;
IEValue_i : in std_ulogic;
--Phase1_i : in std_ulogic;
Phase2_i : in std_ulogic;
Interrupt_i : in std_ulogic;
IEvent_o : out std_ulogic
);
end component;
component cp_ProgramFlowControl
generic
(
GEN_WIDTH_PC : positive := 8;
GEN_INT_VECTOR : std_ulogic_vector(11 downto 0) := x"0F0";
GEN_DEPTH_STACK : positive := 15
);
port (
--------------------------------------------------------------------------------
-- Signaux Systeme
--------------------------------------------------------------------------------
 
 
Enable_i : in std_ulogic;
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
aaa_i : in std_ulogic_vector(GEN_WIDTH_PC-1 downto 0); --
Interrupt_i : in std_ulogic; --
Jump_i : in std_ulogic;
Call_i : in std_ulogic;
Return_i : in std_ulogic;
ReturnI_i : in std_ulogic;
ConditionCtrl_i : in std_ulogic_vector(2 downto 0);
FlagC_i : in std_ulogic;
FlagZ_i : in std_ulogic;
PC_o : out std_ulogic_vector(GEN_WIDTH_PC-1 downto 0) --
);
end component;
component cp_Alu
generic
(
GEN_WIDTH_DATA : positive := 8
);
port (
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
OperationSelect_i : in std_ulogic_vector(2 downto 0);
LogicOper_i : in std_ulogic_vector(1 downto 0);
ArithOper_i : in std_ulogic_vector(1 downto 0);
 
OperandSelect_i : in std_ulogic;
CY_i : in std_ulogic;
sX_i : in std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); --
sY_i : in std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); --
kk_i : in std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); --
ShiftBit_i : in std_ulogic_vector( 2 downto 0 );
ShiftSens_i : in std_ulogic;
Result_o : out std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); --
C_o : out std_ulogic;
Z_o : out std_ulogic
);
end component;
component cp_Flags
port (
--------------------------------------------------------------------------------
-- Signaux Systeme
--------------------------------------------------------------------------------
 
 
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
Z_i : in std_ulogic;
C_i : in std_ulogic;
Z_o : out std_ulogic;
C_o : out std_ulogic;
Push_i : in std_ulogic;
Pop_i : in std_ulogic;
Write_i : in std_ulogic
);
end component;
component cp_BancRegister
generic
(
GEN_WIDTH_DATA : positive := 8;
GEN_DEPTH_BANC : positive := 16
);
port (
--------------------------------------------------------------------------------
-- Signaux Systeme
--------------------------------------------------------------------------------
 
 
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
SxPtr_i : in std_ulogic_vector(log2(GEN_DEPTH_BANC)-1 downto 0);
SyPtr_i : in std_ulogic_vector(log2(GEN_DEPTH_BANC)-1 downto 0);
Write_i : in std_ulogic;
SxData_i : in std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); --
SxData_o : out std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); --
SyData_o : out std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0)
);
end component;
 
component cp_ScratchPad
generic
(
GEN_WIDTH_DATA : positive := 8;
GEN_DEPTH_SCRATCH : positive := 64
);
port (
--------------------------------------------------------------------------------
-- Signaux Systeme
--------------------------------------------------------------------------------
 
 
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
Ptr_i : in std_ulogic_vector(log2(GEN_DEPTH_SCRATCH)-1 downto 0);
Write_i : in std_ulogic;
Data_i : in std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); --
Data_o : out std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0)
);
end component;
 
component cp_DecodeControl
generic
(
GEN_WIDTH_INST : positive := 18;
GEN_WIDTH_PC : positive := 10;
 
GEN_DEPTH_BANC : positive := 16; -- Taille (en octet) du Banc Register
GEN_DEPTH_SCRATCH : positive := 64 -- Taille (en octet) du Scratch Pad
);
port (
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
--Phase1_i : in std_ulogic;
Phase2_i : in std_ulogic;
IEvent_i : in std_ulogic;
Instruction_i : in std_ulogic_vector(GEN_WIDTH_INST-1 downto 0);
Fetch_o : out std_ulogic;
Input_o : out std_ulogic;
Ouput_o : out std_ulogic;
Jump_o : out std_ulogic;
Call_o : out std_ulogic;
Return_o : out std_ulogic;
ReturnI_o : out std_ulogic;
IEWrite_o : out std_ulogic;
BancWrite_o : out std_ulogic;
ScratchWrite_o : out std_ulogic;
OperationSelect_o : out std_ulogic_vector(2 downto 0);
FlagsWrite_o : out std_ulogic;
FlagsPush_o : out std_ulogic;
FlagsPop_o : out std_ulogic;
 
aaa_o : out std_ulogic_vector(GEN_WIDTH_PC-1 downto 0);
kk_o : out std_ulogic_vector(7 downto 0);
ss_o : out std_ulogic_vector(log2(GEN_DEPTH_SCRATCH)-1 downto 0);
pp_o : out std_ulogic_vector(7 downto 0);
 
SxPtr_o : out std_ulogic_vector(log2(GEN_DEPTH_BANC)-1 downto 0);
SyPtr_o : out std_ulogic_vector(log2(GEN_DEPTH_BANC)-1 downto 0);
OperandSelect_o : out std_ulogic;
ArithOper_o : out std_ulogic_vector(1 downto 0);
LogicOper_o : out std_ulogic_vector(1 downto 0);
ShiftBit_o : out std_ulogic_vector(2 downto 0);
ShiftSens_o : out std_ulogic;
ConditionCtrl_o : out std_ulogic_vector(2 downto 0);
IEValue_o : out std_ulogic;
wbRdSing_o : out std_ulogic;
wbWrSing_o : out std_ulogic
 
);
end component;
 
begin
U_Toggle : cp_Toggle
port map(
--------------------------------------------------------------------------------
-- Signaux Systeme
--------------------------------------------------------------------------------
Clk_i => Clk_i,
Rst_i_n => Rst_i_n,
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
Freeze_i => iFreeze ,
 
Phase1_o => iPhase1 ,
Phase2_o => iPhase2
);
 
U_Interrupt : cp_Interrupt
port map(
--------------------------------------------------------------------------------
-- Signaux Systeme
--------------------------------------------------------------------------------
Clk_i => Clk_i,
Rst_i_n => Rst_i_n,
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
IEWrite_i => iIEWrite,
IEValue_i => iIEValue,
--Phase1_i => iPhase1,
Phase2_i => iPhase2,
Interrupt_i => Interrupt_i,
IEvent_o => iIEvent
);
 
U_ProgramFlowControl : cp_ProgramFlowControl
generic map
(
GEN_WIDTH_PC => GEN_WIDTH_PC,
GEN_INT_VECTOR => GEN_INT_VECTOR,
GEN_DEPTH_STACK => GEN_DEPTH_STACK
)
port map(
--------------------------------------------------------------------------------
-- Signaux Systeme
--------------------------------------------------------------------------------
Clk_i => Clk_i,
Rst_i_n => Rst_i_n,
Enable_i => iPcEnable, --iPhase1,
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
aaa_i => iaaa,
Interrupt_i => iIEvent,--'0', -- '0' when substitue the IEvent by a "Call ISR" instruction
Jump_i => iJump,
Call_i => iCall,
Return_i => iReturn,
ReturnI_i => iReturnI,
ConditionCtrl_i => iConditionCtrl,
FlagC_i => iC,
FlagZ_i => iZ,
PC_o => Address_o
);
 
U_ALU : cp_Alu
generic map
(
GEN_WIDTH_DATA => GEN_WIDTH_DATA
)
port map(
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
OperationSelect_i => iOperationSelect,
LogicOper_i => iLogicOper,
ArithOper_i => iArithOper,
 
OperandSelect_i => iOperandSelect,
CY_i => iC,
sX_i => iSxData,
sY_i => iSyData,
kk_i => ikk,
ShiftBit_i => iShiftBit,
ShiftSens_i => iShiftSens,
Result_o => iAluResult,
C_o => iCi,
Z_o => iZi
);
 
U_Flags : cp_Flags
port map(
--------------------------------------------------------------------------------
-- Signaux Systeme
--------------------------------------------------------------------------------
Clk_i => Clk_i,
Rst_i_n => Rst_i_n,
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
Z_i => iZi,
C_i => iCi,
Z_o => iZ,
C_o => iC,
Push_i => iFlagsPush,
Pop_i => iFlagsPop,
Write_i => iFlagsWrite
);
 
U_BancRegister : cp_BancRegister
generic map
(
GEN_WIDTH_DATA => GEN_WIDTH_DATA,
GEN_DEPTH_BANC => GEN_DEPTH_BANC
)
port map(
--------------------------------------------------------------------------------
-- Signaux Systeme
--------------------------------------------------------------------------------
Clk_i => Clk_i,
Rst_i_n => Rst_i_n,
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
SxPtr_i => iSxPtr,
SyPtr_i => iSyPtr,
Write_i => iBancWrite,
SxData_i => iSxDataIn,
SxData_o => iSxData,
SyData_o => iSyData
);
 
U_ScratchPad : cp_ScratchPad
generic map
(
GEN_WIDTH_DATA => GEN_WIDTH_DATA,
GEN_DEPTH_SCRATCH => GEN_DEPTH_SCRATCH
)
port map(
--------------------------------------------------------------------------------
-- Signaux Systeme
--------------------------------------------------------------------------------
Clk_i => Clk_i,
Rst_i_n => Rst_i_n,
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
Ptr_i => iScratchPtr,
Write_i => iScratchWrite,
Data_i => iSxData,
Data_o => iScratchDataOut
);
U_DecodeControl : cp_DecodeControl
generic map
(
GEN_WIDTH_INST => GEN_WIDTH_INST,
GEN_WIDTH_PC => GEN_WIDTH_PC,
 
GEN_DEPTH_BANC => GEN_DEPTH_BANC,
GEN_DEPTH_SCRATCH => GEN_DEPTH_SCRATCH
)
port map(
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
--Phase1_i : in std_ulogic;
Phase2_i => iPhase2,
IEvent_i => iIEvent,
Instruction_i => Instruction_i,
Fetch_o => iFetch,
Input_o => iInput,
Ouput_o => iOuput,
Jump_o => iJump,
Call_o => iCall,
Return_o => iReturn,
ReturnI_o => iReturnI,
IEWrite_o => iIEWrite,
BancWrite_o => iBancWriteOP,
ScratchWrite_o => iScratchWrite,
OperationSelect_o => iOperationSelect,
FlagsWrite_o => iFlagsWrite,
FlagsPush_o => iFlagsPush,
FlagsPop_o => iFlagsPop,
 
aaa_o => iaaa,
kk_o => ikk,
ss_o => iss,
pp_o => ipp,
SxPtr_o => iSxPtr,
SyPtr_o => iSyPtr,
 
OperandSelect_o => iOperandSelect,
 
ArithOper_o => iArithOper,
LogicOper_o => iLogicOper,
ShiftBit_o => iShiftBit,
ShiftSens_o => iShiftSens,
ConditionCtrl_o => iConditionCtrl,
IEValue_o => iIEValue,
wbRdSing_o => iWbRdSing,
wbWrSing_o => iWbWrSing
 
);
 
-- **** --
-- PATH --
-- **** --
-- Banc --
iSxDataIn <= iScratchDataOut when ( iFetch = '1' ) else
IN_PORT_i when ( iInput = '1' ) else
iwbDAT when ( iWbRdSing = '1') else
iAluResult ;
 
iBancWrite <= iWB_validOperand when ( iWbRdSing = '1') else
iBancWriteOP ;
 
-- Scratch --
iScratchPtr <= iSyData(iScratchPtr'range) when ( iOperandSelect = '1' ) else
iss;
 
--------------------------------------------------------------------------------
-- Outputs
--------------------------------------------------------------------------------
 
-- TODO : Take care when the "iIE" bit is not set. In this case how to manage "Interrupt_Ack_o" !!!
Interrupt_Ack_o <= ((iPhase2) and (iIEvent));
OUT_PORT_o <= iSxData;
PORT_ID_o <= iSyData when ( iOperandSelect = '1' ) else
ipp ;
READ_STROBE_o <= ((iPhase2) and (iInput));
WRITE_STROBE_o <= ((iPhase2) and (iOuput));
--------------------------------------------------------------------------------
-- System
--------------------------------------------------------------------------------
iFreeze <= Freeze_i;
-- Evolution of the PC:
-- condition : in Phase1 and the processor is not in stall by wishbone
--iPcEnable <= (iPhase1 and not(iwbStall));
iPcEnable <= ((iPhase1) and (iWB_validHandshake)) when (iwbCYC='1') else
(iPhase1);
 
--------------------------------------------------------------------------------
-- WISHBONE
--------------------------------------------------------------------------------
-- =================== --
-- Wishbone Management --
-- =================== --
--iWB_inst <= iWbRdSing or iWbWrSing; -- wishbone instruction
iWB_validHandshake <= iwbCYC and iwbACK_I; -- wishbone VALID ACKNOWLEDGE
-- Valid PC write --
-- ************** --
iWB_validPC <= ((iPhase1) and (iWB_validHandshake)); -- Valid PC incremente
-- Then Valid Operand Read/Write
-- ************************** --
wbvOp_Proc : process (Rst_i_n, Clk_i)
begin
if ( Rst_i_n = '0' ) then
iWB_validOperand <= '0';
iwbDAT <= (others => '0');
elsif ( rising_edge(Clk_i) ) then
iWB_validOperand <= iWB_validPC; -- Valid Operand Read/Write
if ( iWB_validPC = '1' ) then
iwbDAT <= iwbDAT_I;
end if;
end if;
end process wbvOp_Proc;
-- CYCle determination --
-- ******************* --
wbCYC_Proc : process (Rst_i_n, Clk_i, iPhase2, iWB_validOperand)
begin
-- reset or end of wishbone cycle : after wishbone Operand Validation
if ( ( Rst_i_n = '0' ) or ((iPhase2='1') and (iWB_validOperand='1')) ) then
iwbCYC <= '0';
-- valid a begining Wishbone Cycle: in Phase1 and wishbone instruction
elsif ( falling_edge(Clk_i) ) then
if ( (iPhase1='1') and ((iWbRdSing='1') or (iWbWrSing='1')) ) then
iwbCYC <= '1';
end if;
end if;
end process wbCYC_Proc;
-- ============== --
-- Inputs/Outputs --
-- ============== --
--iwbRST_I <= RST_I;
--iwbCLK_I <= CLK_I;
 
iwbSTB_O <= iwbCYC;
iwbSEL_O <= (others => '0');
 
ADR_O <= iwbADR_O;
iwbDAT_I <= DAT_I;
DAT_O <= iwbDAT_O;
WE_O <= iwbWE_O ;
SEL_O <= iwbSEL_O;
STB_O <= iwbSTB_O ;
iwbACK_I <= ACK_I;
CYC_O <= iwbCYC ;
 
iwbWE_O <= iWbWrSing;
iwbDAT_O <= iSxData;
iwbADR_O <= iSyData when ( iOperandSelect = '1' ) else
ikk ;
 
 
end rtl;
/copyblaze/rtl/vhdl/cpu/cp_Flags.vhd
0,0 → 1,135
--------------------------------------------------------------------------------
-- Company:
--
-- File: cp_Flags.vhd
--
-- Description:
-- projet copyblaze
-- Flags ZERO & CARRY management
--
-- File history:
-- v1.0: 10/10/11: Creation
--
-- Targeted device: ProAsic A3P250 VQFP100
-- Author: AbdAllah Meziti
--------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.Usefull_Pkg.all; -- Usefull Package
 
--------------------------------------------------------------------------------
-- Entity: cp_Flags
--
-- Description:
--
-- REMARQUE:
--
--
-- History:
-- 10/10/11 AM: Creation
-- ---------------------
-- xx/xx/xx AM:
--
--------------------------------------------------------------------------------
entity cp_Flags is
port (
--------------------------------------------------------------------------------
-- Signaux Systeme
--------------------------------------------------------------------------------
 
 
 
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
Z_i : in std_ulogic;
C_i : in std_ulogic;
Z_o : out std_ulogic;
C_o : out std_ulogic;
Push_i : in std_ulogic;
Pop_i : in std_ulogic;
Write_i : in std_ulogic
);
end cp_Flags;
 
--------------------------------------------------------------------------------
-- Architecture: RTL
-- of entity : cp_Flags
--------------------------------------------------------------------------------
architecture rtl of cp_Flags is
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
signal iZ : std_ulogic; -- flag
signal iC : std_ulogic; -- flag
signal iZs : std_ulogic; -- Shadow flag
signal iCs : std_ulogic; -- Shadow flag
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
begin
--------------------------------------------------------------------------------
-- Process : Flags_Proc
-- Description: Flags Management
--------------------------------------------------------------------------------
Flags_Proc : process(Rst_i_n, Clk_i)
begin
if ( Rst_i_n = '0' ) then
iZ <= '0';
iC <= '0';
 
elsif ( rising_edge(Clk_i) ) then
if ( Write_i = '1' ) then
iZ <= Z_i;
iC <= C_i;
elsif ( Pop_i = '1' ) then
iZ <= iZs;
iC <= iCs;
end if;
end if;
end process Flags_Proc;
--------------------------------------------------------------------------------
-- Process : ShadowFlags_Proc
-- Description: Shadow Flags Management
--------------------------------------------------------------------------------
ShadowFlags_Proc : process(Rst_i_n, Clk_i)
begin
if ( Rst_i_n = '0' ) then
iZs <= '0';
iCs <= '0';
 
elsif ( rising_edge(Clk_i) ) then
if ( Push_i = '1' ) then
iZs <= iZ;
iCs <= iC;
end if;
end if;
end process ShadowFlags_Proc;
Z_o <= iZ;
C_o <= iC;
 
end rtl;
 
/copyblaze/rtl/vhdl/cpu/cp_Interrupt.vhd
0,0 → 1,147
--------------------------------------------------------------------------------
-- Company:
--
-- File: cp_Interrupt.vhd
--
-- Description:
-- projet copyblaze
-- Interrupt Module
--
-- File history:
-- v1.0: 17/10/11: Creation
--
-- Targeted device: ProAsic A3P250 VQFP100
-- Author: AbdAllah Meziti
--------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.Usefull_Pkg.all; -- Usefull Package
 
--------------------------------------------------------------------------------
-- Entity: cp_Interrupt
--
-- Description:
--
-- REMARQUE:
--
--
-- History:
-- 17/10/11 AM: Creation
-- ---------------------
-- xx/xx/xx AM:
--
--------------------------------------------------------------------------------
entity cp_Interrupt is
port (
--------------------------------------------------------------------------------
-- Signaux Systeme
--------------------------------------------------------------------------------
 
 
 
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
IEWrite_i : in std_ulogic;
IEValue_i : in std_ulogic;
--Phase1_i : in std_ulogic;
Phase2_i : in std_ulogic;
 
Interrupt_i : in std_ulogic;
IEvent_o : out std_ulogic
);
end cp_Interrupt;
 
--------------------------------------------------------------------------------
-- Architecture: RTL
-- of entity : cp_Interrupt
--------------------------------------------------------------------------------
architecture rtl of cp_Interrupt is
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
signal iInterrupt_i_old : std_ulogic;
signal iInterrupt_i_edge : std_ulogic;
signal iIDetect : std_ulogic;
 
signal iIE : std_ulogic; -- Interrupt Enable Flags
signal iIEvent : std_ulogic; -- Interrupt Event Flags
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
begin
iInterrupt_i_edge <= (Interrupt_i) and ( not(iInterrupt_i_old) );
 
--------------------------------------------------------------------------------
-- Process : IE_Proc
-- Description: Interrupt management
--------------------------------------------------------------------------------
-- Interrupt Flag --
IE_Proc : process(Rst_i_n, Clk_i)
begin
if ( Rst_i_n = '0' ) then
iInterrupt_i_old <= '0';
iIE <= '0';
iIEvent <= '0';
iIDetect <= '0';
elsif ( rising_edge(Clk_i) ) then
-- Interrupt Input sampling
iInterrupt_i_old <= Interrupt_i;
-- Set the IE bit
if ( IEWrite_i ='1' ) then
iIE <= IEValue_i;
end if;
if ( iIEvent = '1' ) then
iIE <= '0';
end if;
 
-- Save the interrupt edge detection for a phase cycle
if ( iInterrupt_i_edge = '1' ) then
iIDetect <= '1';
elsif ( (Phase2_i = '1') and (iIDetect = '1') ) then
iIDetect <= '0';
end if;
-- Proceding the interrupt Event
if ( (Phase2_i = '1') and (iIDetect = '1') and (iIE = '1') ) then
iIEvent <= '1'; -- Interrupt Event proceding now
iIDetect <= '0'; -- Now, can clear the EdgeDectection
-- Next phase clear the IEvent
-- TODO : The ENABLE INTERRUPT instruction must clear the "iIEvent" bit if is set while the interrupts are disabled.
elsif ( (Phase2_i = '1') and (iIEvent = '1') ) then
iIEvent <= '0'; -- Clear the Interrupt Event
end if;
end if;
end process IE_Proc;
 
IEvent_o <= iIEvent;
 
end rtl;
 
/copyblaze/rtl/vhdl/cpu/cp_ScratchPad.vhd
0,0 → 1,111
--------------------------------------------------------------------------------
-- Company:
--
-- File: cp_ScratchPad.vhd
--
-- Description:
-- projet copyblaze
-- Scratch Pad Memory
--
-- File history:
-- v1.0: 10/10/11: Creation
--
-- Targeted device: ProAsic A3P250 VQFP100
-- Author: AbdAllah Meziti
--------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.Usefull_Pkg.all; -- Usefull Package
 
--------------------------------------------------------------------------------
-- Entity: cp_ScratchPad
--
-- Description:
--
-- REMARQUE:
--
--
-- History:
-- 10/10/11 AM: Creation
-- ---------------------
-- xx/xx/xx AM:
--
--------------------------------------------------------------------------------
entity cp_ScratchPad is
generic
(
GEN_WIDTH_DATA : positive := 8;
GEN_DEPTH_SCRATCH : positive := 64
);
port (
--------------------------------------------------------------------------------
-- Signaux Systeme
--------------------------------------------------------------------------------
 
 
 
--------------------------------------------------------------------------------
-- Signaux Fonctionels
--------------------------------------------------------------------------------
Ptr_i : in std_ulogic_vector(log2(GEN_DEPTH_SCRATCH)-1 downto 0);
Write_i : in std_ulogic;
Data_i : in std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0); --
Data_o : out std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0)
);
end cp_ScratchPad;
 
--------------------------------------------------------------------------------
-- Architecture: RTL
-- of entity : cp_ScratchPad
--------------------------------------------------------------------------------
architecture rtl of cp_ScratchPad is
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
type RAM_TYPE is array (0 to GEN_DEPTH_SCRATCH-1) of std_ulogic_vector(GEN_WIDTH_DATA-1 downto 0);
 
signal iScratchPadMem : RAM_TYPE;
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 
begin
--------------------------------------------------------------------------------
-- Process : ScratchPad_Proc
-- Description: ScratchPad Memory
--------------------------------------------------------------------------------
ScratchPad_Proc : process(Rst_i_n, Clk_i)
begin
if ( Rst_i_n = '0' ) then
for i in 0 to GEN_DEPTH_SCRATCH-1 loop
iScratchPadMem(i) <= (others=>'0');
end loop;
 
elsif ( rising_edge(Clk_i) ) then
if ( Write_i = '1' ) then
iScratchPadMem( to_integer(unsigned(Ptr_i)) ) <= Data_i;
end if;
end if;
end process ScratchPad_Proc;
 
Data_o <= iScratchPadMem( to_integer(unsigned(Ptr_i)) );
 
end rtl;
 

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