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Rev 64 → Rev 65

/trunk/copyblaze/rtl/vhdl/ip/wb_sram/asram_core.v File deleted
/trunk/copyblaze/rtl/vhdl/ip/wb_sram/asram_top.v File deleted
/trunk/copyblaze/rtl/vhdl/ip/wb_3p_spram_wrapper/sp_ram.vhd
0,0 → 1,40
------------------------------------
-- SINGLE PORT BLOCKRAM INFERENCE --
------------------------------------
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.std_logic_unsigned.all;
--use IEEE.NUMERIC_STD.ALL;
 
entity sp_ram is
generic (data_width : integer := 32;
addr_width : integer := 8);
port (
clka: IN std_logic;
wea: IN std_logic_vector(0 downto 0); --direct drop-in replacement of coregen's spram
addra: IN std_logic_vector(addr_width-1 downto 0);
dina: IN std_logic_vector(data_width-1 downto 0);
douta: OUT std_logic_vector(data_width-1 downto 0));
end sp_ram;
 
architecture sp_ram_arch of sp_ram is
 
type mem_type is array (2**addr_width-1 downto 0) of std_logic_vector(data_width-1 downto 0);
signal mem: mem_type; --Synplicity may need it to infer the RAM
--attribute syn_ramstyle : string; --Synplicity may need it to infer the RAM
--attribute syn_ramstyle of mem : signal is "block_ram"; --Synplicity may need it to infer the RAM
begin
mem_write : process (clka)
begin
if (clka = '1' and clka'event) then
--douta <= mem(to_integer(unsigned(addra))); --read first ram
douta <= mem(conv_integer(addra)); --read first ram
if (wea(0) = '1') then
mem(conv_integer(addra)) <= dina;
end if;
end if;
end process mem_write;
end sp_ram_arch;
/trunk/copyblaze/rtl/vhdl/ip/wb_3p_spram_wrapper/wb_Np_ram.vhd
0,0 → 1,329
----------------------------------------------------------------------------------
-- Company: VISENGI S.L. (www.visengi.com)
-- Engineer: Victor Lopez Lorenzo (victor.lopez (at) visengi (dot) com)
--
-- Create Date: 23:44:13 22/August/2008
-- Project Name: Triple Port WISHBONE SPRAM Wrapper
-- Tool versions: Xilinx ISE 9.2i
-- Description:
--
-- Description: This is a wrapper for an inferred single port RAM, that converts it
-- into a Three-port RAM with one WISHBONE slave interface for each port.
--
--
-- LICENSE TERMS: GNU LESSER GENERAL PUBLIC LICENSE Version 2.1
-- That is you may use it in ANY project (commercial or not) without paying a cent.
-- You are only required to include in the copyrights/about section of accompanying
-- software and manuals of use that your system contains a "3P WB SPRAM Wrapper
-- (C) VISENGI S.L. under LGPL license"
-- This holds also in the case where you modify the core, as the resulting core
-- would be a derived work.
-- Also, we would like to know if you use this core in a project of yours, just an email will do.
--
-- Please take good note of the disclaimer section of the LPGL license, as we don't
-- take any responsability for anything that this core does.
----------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity wb_Np_ram is
generic (data_width : integer := 32;
addr_width : integer := 8);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
wb1_cyc_i : in std_logic;
wb1_stb_i : in std_logic;
wb1_we_i : in std_logic;
wb1_adr_i : in std_logic_vector(addr_width-1 downto 0);
wb1_dat_i : in std_logic_vector(data_width-1 downto 0);
wb1_dat_o : out std_logic_vector(data_width-1 downto 0);
wb1_ack_o : out std_logic;
wb2_cyc_i : in std_logic;
wb2_stb_i : in std_logic;
wb2_we_i : in std_logic;
wb2_adr_i : in std_logic_vector(addr_width-1 downto 0);
wb2_dat_i : in std_logic_vector(data_width-1 downto 0);
wb2_dat_o : out std_logic_vector(data_width-1 downto 0);
wb2_ack_o : out std_logic;
wb3_cyc_i : in std_logic;
wb3_stb_i : in std_logic;
wb3_we_i : in std_logic;
wb3_adr_i : in std_logic_vector(addr_width-1 downto 0);
wb3_dat_i : in std_logic_vector(data_width-1 downto 0);
wb3_dat_o : out std_logic_vector(data_width-1 downto 0);
wb3_ack_o : out std_logic);
end wb_Np_ram;
 
architecture Behavioral of wb_Np_ram is
component sp_ram is --uncomment to use an inferred spram
generic (data_width : integer := 32;
addr_width : integer := 8);
--component sp_ram_core is --uncomment to use the coregen spram
port (
clka: IN std_logic;
wea: IN std_logic_vector(0 downto 0);
addra: IN std_logic_vector(addr_width-1 downto 0);
dina: IN std_logic_vector(data_width-1 downto 0);
douta: OUT std_logic_vector(data_width-1 downto 0));
end component;
signal we: std_logic_vector(0 downto 0);
signal a : std_logic_vector(addr_width-1 downto 0);
signal d,q : std_logic_vector(data_width-1 downto 0);
begin
 
 
u_sp_ram : sp_ram --uncomment to use an inferred spram
generic map (data_width,addr_width)
--u_sp_ram : sp_ram_core --uncomment to use the coregen spram
port map (
clka => wb_clk_i,
wea => we,
addra => a,
dina => d,
douta => q);
wb1_dat_o <= q;
wb2_dat_o <= q;
wb3_dat_o <= q;
WB_interconnect: process (wb_clk_i, wb_rst_i)
variable ack1, ack2, ack3 : std_logic;
variable lock : integer;
variable State : integer;
begin
if (wb_rst_i = '1') then
we(0) <= '0';
a <= (others => '0');
d <= (others => '0');
ack1 := '0';
wb1_ack_o <= '0';
ack2 := '0';
wb2_ack_o <= '0';
ack3 := '0';
wb3_ack_o <= '0';
lock := 0;
State := 0;
elsif (wb_clk_i = '1' and wb_clk_i'event) then
--defaults (unless overriden afterwards)
we(0) <= '0';
case State is
when 0 => --priority for wb1
--unlockers
if (lock = 1 and wb1_cyc_i = '0') then lock := 0; end if;
if (lock = 2 and wb2_cyc_i = '0') then lock := 0; end if;
if (lock = 3 and wb3_cyc_i = '0') then lock := 0; end if;
if (wb1_cyc_i = '1' and (lock = 0 or lock=1)) then --lock request (grant if lock is available)
ack2 := '0';
ack3 := '0';
lock := 1;
if (wb1_stb_i = '1' and ack1 = '0') then --operation request
we(0) <= wb1_we_i;
a <= wb1_adr_i;
d <= wb1_dat_i;
if (wb1_we_i = '1') then
ack1 := '1'; --ack now and stay in this state waiting for new ops
State := 1;
else
State := 11; --wait one cycle for operation to end
end if;
else
ack1 := '0'; --force one cycle wait between operations
--or else the wb master could issue a write, then receive two acks (first legal ack and then
--a spurious one due to being in the cycle where the master is still reading the first ack)
--followed by a read and misinterpret the spurious ack as an ack for the read
end if;
elsif (wb2_cyc_i = '1' and (lock = 0 or lock=2)) then --lock request (grant if lock is available)
ack1 := '0';
ack3 := '0';
lock := 2;
if (wb2_stb_i = '1' and ack2 = '0') then --operation request
we(0) <= wb2_we_i;
a <= wb2_adr_i;
d <= wb2_dat_i;
if (wb2_we_i = '1') then
ack2 := '1'; --ack now and stay in this state waiting for new ops
State := 2;
else
State := 12; --wait one cycle for operation to end
end if;
else
ack2 := '0'; --force one cycle wait between operations
end if;
elsif (wb3_cyc_i = '1' and (lock = 0 or lock=3)) then --lock request (grant if lock is available)
ack1 := '0';
ack2 := '0';
lock := 3;
if (wb3_stb_i = '1' and ack3 = '0') then --operation request
we(0) <= wb3_we_i;
a <= wb3_adr_i;
d <= wb3_dat_i;
if (wb3_we_i = '1') then
ack3 := '1'; --ack now and stay in this state waiting for new ops
State := 0;
else
State := 13; --wait one cycle for operation to end
end if;
else
ack3 := '0'; --force one cycle wait between operations
end if;
end if;
 
when 1 => --priority for wb2 (same code as previous State but changing the order of the if...elsifs)
--unlockers
if (lock = 1 and wb1_cyc_i = '0') then lock := 0; end if;
if (lock = 2 and wb2_cyc_i = '0') then lock := 0; end if;
if (lock = 3 and wb3_cyc_i = '0') then lock := 0; end if;
if (wb2_cyc_i = '1' and (lock = 0 or lock=2)) then --lock request (grant if lock is available)
ack1 := '0';
ack3 := '0';
lock := 2;
if (wb2_stb_i = '1' and ack2 = '0') then --operation request
we(0) <= wb2_we_i;
a <= wb2_adr_i;
d <= wb2_dat_i;
if (wb2_we_i = '1') then
ack2 := '1'; --ack now and stay in this state waiting for new ops
State := 2;
else
State := 12; --wait one cycle for operation to end
end if;
else
ack2 := '0'; --force one cycle wait between operations
end if;
elsif (wb3_cyc_i = '1' and (lock = 0 or lock=3)) then --lock request (grant if lock is available)
ack1 := '0';
ack2 := '0';
lock := 3;
if (wb3_stb_i = '1' and ack3 = '0') then --operation request
we(0) <= wb3_we_i;
a <= wb3_adr_i;
d <= wb3_dat_i;
if (wb3_we_i = '1') then
ack3 := '1'; --ack now and stay in this state waiting for new ops
State := 0;
else
State := 13; --wait one cycle for operation to end
end if;
else
ack3 := '0'; --force one cycle wait between operations
end if;
elsif (wb1_cyc_i = '1' and (lock = 0 or lock=1)) then --lock request (grant if lock is available)
ack2 := '0';
ack3 := '0';
lock := 1;
if (wb1_stb_i = '1' and ack1 = '0') then --operation request
we(0) <= wb1_we_i;
a <= wb1_adr_i;
d <= wb1_dat_i;
if (wb1_we_i = '1') then
ack1 := '1'; --ack now and stay in this state waiting for new ops
State := 1;
else
State := 11; --wait one cycle for operation to end
end if;
else
ack1 := '0'; --force one cycle wait between operations
end if;
end if;
 
when 2 => --priority for wb3 (same code as previous State but changing the order of the if...elsifs)
--unlockers
if (lock = 1 and wb1_cyc_i = '0') then lock := 0; end if;
if (lock = 2 and wb2_cyc_i = '0') then lock := 0; end if;
if (lock = 3 and wb3_cyc_i = '0') then lock := 0; end if;
if (wb3_cyc_i = '1' and (lock = 0 or lock=3)) then --lock request (grant if lock is available)
ack1 := '0';
ack2 := '0';
lock := 3;
if (wb3_stb_i = '1' and ack3 = '0') then --operation request
we(0) <= wb3_we_i;
a <= wb3_adr_i;
d <= wb3_dat_i;
if (wb3_we_i = '1') then
ack3 := '1'; --ack now and stay in this state waiting for new ops
State := 0;
else
State := 13; --wait one cycle for operation to end
end if;
else
ack3 := '0'; --force one cycle wait between operations
end if;
elsif (wb1_cyc_i = '1' and (lock = 0 or lock=1)) then --lock request (grant if lock is available)
ack2 := '0';
ack3 := '0';
lock := 1;
if (wb1_stb_i = '1' and ack1 = '0') then --operation request
we(0) <= wb1_we_i;
a <= wb1_adr_i;
d <= wb1_dat_i;
if (wb1_we_i = '1') then
ack1 := '1'; --ack now and stay in this state waiting for new ops
State := 1;
else
State := 11; --wait one cycle for operation to end
end if;
else
ack1 := '0'; --force one cycle wait between operations
end if;
elsif (wb2_cyc_i = '1' and (lock = 0 or lock=2)) then --lock request (grant if lock is available)
ack1 := '0';
ack3 := '0';
lock := 2;
if (wb2_stb_i = '1' and ack2 = '0') then --operation request
we(0) <= wb2_we_i;
a <= wb2_adr_i;
d <= wb2_dat_i;
if (wb2_we_i = '1') then
ack2 := '1'; --ack now and stay in this state waiting for new ops
State := 2;
else
State := 12; --wait one cycle for operation to end
end if;
else
ack2 := '0'; --force one cycle wait between operations
end if;
end if;
 
when 11 =>
ack1 := '1'; --ack operation
ack2 := '0';
ack3 := '0';
State := 1;
when 12 =>
ack1 := '0';
ack2 := '1'; --ack operation
ack3 := '0';
State := 2;
when 13 =>
ack1 := '0';
ack2 := '0';
ack3 := '1'; --ack operation
State := 0;
when others => --sanity
ack1 := '0';
ack2 := '0';
ack3 := '0';
State := 0;
end case;
wb1_ack_o <= (ack1 and wb1_stb_i and wb1_cyc_i); --to don't ack aborted operations
wb2_ack_o <= (ack2 and wb2_stb_i and wb2_cyc_i); --to don't ack aborted operations
wb3_ack_o <= (ack3 and wb3_stb_i and wb3_cyc_i); --to don't ack aborted operations
end if;
end process WB_interconnect;
end Behavioral;
 
/trunk/copyblaze/rtl/vhdl/ip/wb_3p_spram_wrapper/tb_wb_Np_ram.vhd
0,0 → 1,401
----------------------------------------------------------------------------------
-- Company: VISENGI S.L. (www.visengi.com)
-- Engineer: Victor Lopez Lorenzo (victor.lopez (at) visengi (dot) com)
--
-- Create Date: 23:44:13 22/August/2008
-- Project Name: Triple Port WISHBONE SPRAM Wrapper
-- Tool versions: Xilinx ISE 9.2i
-- Description:
--
-- Description: This is a wrapper for an inferred single port RAM, that converts it
-- into a Three-port RAM with one WISHBONE slave interface for each port.
--
--
-- LICENSE TERMS: GNU LESSER GENERAL PUBLIC LICENSE Version 2.1
-- That is you may use it in ANY project (commercial or not) without paying a cent.
-- You are only required to include in the copyrights/about section of accompanying
-- software and manuals of use that your system contains a "3P WB SPRAM Wrapper
-- (C) VISENGI S.L. under LGPL license"
-- This holds also in the case where you modify the core, as the resulting core
-- would be a derived work.
-- Also, we would like to know if you use this core in a project of yours, just an email will do.
--
-- Please take good note of the disclaimer section of the LPGL license, as we don't
-- take any responsability for anything that this core does.
----------------------------------------------------------------------------------
 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY tb_wb_Np_ram_vhd IS
END tb_wb_Np_ram_vhd;
 
ARCHITECTURE behavior OF tb_wb_Np_ram_vhd IS
 
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT wb_Np_ram
PORT(
wb_clk_i : IN std_logic;
wb_rst_i : IN std_logic;
wb1_cyc_i : IN std_logic;
wb1_stb_i : IN std_logic;
wb1_we_i : IN std_logic;
wb1_adr_i : IN std_logic_vector(7 downto 0);
wb1_dat_i : IN std_logic_vector(31 downto 0);
wb2_cyc_i : IN std_logic;
wb2_stb_i : IN std_logic;
wb2_we_i : IN std_logic;
wb2_adr_i : IN std_logic_vector(7 downto 0);
wb2_dat_i : IN std_logic_vector(31 downto 0);
wb3_cyc_i : IN std_logic;
wb3_stb_i : IN std_logic;
wb3_we_i : IN std_logic;
wb3_adr_i : IN std_logic_vector(7 downto 0);
wb3_dat_i : IN std_logic_vector(31 downto 0);
wb1_dat_o : OUT std_logic_vector(31 downto 0);
wb1_ack_o : OUT std_logic;
wb2_dat_o : OUT std_logic_vector(31 downto 0);
wb2_ack_o : OUT std_logic;
wb3_dat_o : OUT std_logic_vector(31 downto 0);
wb3_ack_o : OUT std_logic
);
END COMPONENT;
 
--Inputs
SIGNAL wb_clk_i : std_logic := '0';
SIGNAL wb_rst_i : std_logic := '0';
SIGNAL wb1_cyc_i : std_logic := '0';
SIGNAL wb1_stb_i : std_logic := '0';
SIGNAL wb1_we_i : std_logic := '0';
SIGNAL wb2_cyc_i : std_logic := '0';
SIGNAL wb2_stb_i : std_logic := '0';
SIGNAL wb2_we_i : std_logic := '0';
SIGNAL wb3_cyc_i : std_logic := '0';
SIGNAL wb3_stb_i : std_logic := '0';
SIGNAL wb3_we_i : std_logic := '0';
SIGNAL wb1_adr_i : std_logic_vector(7 downto 0) := (others=>'0');
SIGNAL wb1_dat_i : std_logic_vector(31 downto 0) := (others=>'0');
SIGNAL wb2_adr_i : std_logic_vector(7 downto 0) := (others=>'0');
SIGNAL wb2_dat_i : std_logic_vector(31 downto 0) := (others=>'0');
SIGNAL wb3_adr_i : std_logic_vector(7 downto 0) := (others=>'0');
SIGNAL wb3_dat_i : std_logic_vector(31 downto 0) := (others=>'0');
 
--Outputs
SIGNAL wb1_dat_o : std_logic_vector(31 downto 0);
SIGNAL wb1_ack_o : std_logic;
SIGNAL wb2_dat_o : std_logic_vector(31 downto 0);
SIGNAL wb2_ack_o : std_logic;
SIGNAL wb3_dat_o : std_logic_vector(31 downto 0);
SIGNAL wb3_ack_o : std_logic;
 
BEGIN
 
-- Instantiate the Unit Under Test (UUT)
uut: wb_Np_ram PORT MAP(
wb_clk_i => wb_clk_i,
wb_rst_i => wb_rst_i,
wb1_cyc_i => wb1_cyc_i,
wb1_stb_i => wb1_stb_i,
wb1_we_i => wb1_we_i,
wb1_adr_i => wb1_adr_i,
wb1_dat_i => wb1_dat_i,
wb1_dat_o => wb1_dat_o,
wb1_ack_o => wb1_ack_o,
wb2_cyc_i => wb2_cyc_i,
wb2_stb_i => wb2_stb_i,
wb2_we_i => wb2_we_i,
wb2_adr_i => wb2_adr_i,
wb2_dat_i => wb2_dat_i,
wb2_dat_o => wb2_dat_o,
wb2_ack_o => wb2_ack_o,
wb3_cyc_i => wb3_cyc_i,
wb3_stb_i => wb3_stb_i,
wb3_we_i => wb3_we_i,
wb3_adr_i => wb3_adr_i,
wb3_dat_i => wb3_dat_i,
wb3_dat_o => wb3_dat_o,
wb3_ack_o => wb3_ack_o
);
 
 
 
 
 
wb1_control : process (wb_rst_i, wb_clk_i)
variable WaitACKWB : std_logic;
variable data : std_logic_vector(31 downto 0);
variable State : integer;
begin
if (wb_rst_i = '1') then
wb1_dat_i <= (others => '0');
wb1_adr_i <= (others => '0');
wb1_we_i <= '0';
wb1_stb_i <= '0';
wb1_cyc_i <= '0';
data := (others => '0');
WaitACKWB := '0';
State := 0;
elsif (wb_clk_i = '1' and wb_clk_i'event) then
if (WaitACKWB = '1') then
if (wb1_ack_o = '1') then
WaitACKWB := '0';
wb1_we_i <= '0';
wb1_stb_i <= '0';
wb1_cyc_i <= '0';
data := wb1_dat_o;
end if;
end if;
if (WaitACKWB = '0') then
case State is
when 0 => --init
wb1_adr_i <= X"00";
wb1_dat_i <= x"00000001";
wb1_we_i <= '1';
WaitACKWB := '1';
State := State + 1;
when 1 =>
wb1_adr_i <= X"01";
wb1_dat_i <= x"00000002";
wb1_we_i <= '1';
WaitACKWB := '1';
State := State + 1;
when 2 =>
wb1_adr_i <= X"02";
wb1_dat_i <= x"00000003";
wb1_we_i <= '1';
WaitACKWB := '1';
State := State + 1;
when 3 =>
State := State + 1;
when 4 =>
wb1_adr_i <= X"00";
wb1_we_i <= '0';
WaitACKWB := '1';
State := State + 1;
when 5 =>
State := State + 1;
when 6 =>
State := State + 1;
when 7 =>
wb1_adr_i <= X"01";
wb1_dat_i <= data;
wb1_we_i <= '1';
WaitACKWB := '1';
State := State + 1;
when 8 =>
wb1_adr_i <= X"05";
wb1_dat_i <= x"00500FA0";
wb1_we_i <= '1';
WaitACKWB := '1';
State := 0;
when 45 =>
report "-----------> Testbench Finished OK!" severity FAILURE; --everything went fine, it's just to stop the simulation
when others =>
null;
end case;
if (WaitACKWB = '1') then
wb1_stb_i <= '1';
wb1_cyc_i <= '1';
end if;
end if;
end if;
end process wb1_control;
 
 
 
 
 
wb2_control : process (wb_rst_i, wb_clk_i)
variable WaitACKWB : std_logic;
variable data : std_logic_vector(31 downto 0);
variable State : integer;
begin
if (wb_rst_i = '1') then
wb2_dat_i <= (others => '0');
wb2_adr_i <= (others => '0');
wb2_we_i <= '0';
wb2_stb_i <= '0';
wb2_cyc_i <= '0';
data := (others => '0');
WaitACKWB := '0';
State := 0;
elsif (wb_clk_i = '1' and wb_clk_i'event) then
if (WaitACKWB = '1') then
if (wb2_ack_o = '1') then
WaitACKWB := '0';
wb2_we_i <= '0';
wb2_stb_i <= '0';
wb2_cyc_i <= '0';
data := wb2_dat_o;
end if;
end if;
if (WaitACKWB = '0') then
case State is
when 0 => --init
wb2_adr_i <= X"05";
wb2_we_i <= '0';
WaitACKWB := '1';
State := State + 1;
when 1 =>
State := State + 1;
when 2 =>
State := State + 1;
when 3 =>
State := State + 1;
when 4 =>
wb2_adr_i <= X"04";
wb2_dat_i <= x"00000002";
wb2_we_i <= '1';
WaitACKWB := '1';
State := State + 1;
when 5 =>
State := State + 1;
when 6 =>
State := State + 1;
when 7 =>
State := State + 1;
when 8 =>
wb2_adr_i <= X"03";
wb2_we_i <= '0';
WaitACKWB := '1';
State := State + 1;
when 9 =>
State := State + 1;
when 10 =>
wb2_adr_i <= X"02";
wb2_we_i <= '0';
WaitACKWB := '1';
State := State + 1;
when 11 =>
State := State + 1;
when 12 =>
State := State + 1;
when 13 =>
State := State + 1;
when 14 =>
wb2_adr_i <= X"01";
wb2_we_i <= '0';
WaitACKWB := '1';
State := State + 1;
when 15 =>
State := State + 1;
when 16 =>
State := State + 1;
when 17 =>
wb2_adr_i <= X"05";
wb2_dat_i <= data;
wb2_we_i <= '1';
WaitACKWB := '1';
State := 0;
when others =>
null;
end case;
if (WaitACKWB = '1') then
wb2_stb_i <= '1';
wb2_cyc_i <= '1';
end if;
end if;
end if;
end process wb2_control;
 
 
 
wb3_control : process (wb_rst_i, wb_clk_i)
variable WaitACKWB : std_logic;
variable data : std_logic_vector(31 downto 0);
variable State : integer;
begin
if (wb_rst_i = '1') then
wb3_dat_i <= (others => '0');
wb3_adr_i <= (others => '0');
wb3_we_i <= '0';
wb3_stb_i <= '0';
wb3_cyc_i <= '0';
data := (others => '0');
WaitACKWB := '0';
State := 0;
elsif (wb_clk_i = '1' and wb_clk_i'event) then
if (WaitACKWB = '1') then
if (wb3_ack_o = '1') then
WaitACKWB := '0';
wb3_we_i <= '0';
wb3_stb_i <= '0';
wb3_cyc_i <= '0';
data := wb3_dat_o;
end if;
end if;
if (WaitACKWB = '0') then
case State is
when 0 =>
State := State + 1;
when 1 => --init
wb3_adr_i <= X"05";
wb3_we_i <= '0';
WaitACKWB := '1';
State := State + 1;
when 2 =>
wb3_adr_i <= X"02";
wb3_dat_i <= x"00000002";
wb3_we_i <= '1';
WaitACKWB := '1';
State := State + 1;
when 3 =>
State := State + 1;
when 4 =>
wb3_adr_i <= X"01";
wb3_dat_i <= x"00000003";
wb3_we_i <= '1';
WaitACKWB := '1';
State := State + 1;
when 5 =>
wb3_adr_i <= X"05";
wb3_we_i <= '0';
WaitACKWB := '1';
State := State + 1;
when 6 =>
State := State + 1;
when 7 =>
State := State + 1;
when 8 =>
wb3_adr_i <= X"01";
wb3_dat_i <= data;
wb3_we_i <= '1';
WaitACKWB := '1';
State := 0;
when others =>
null;
end case;
if (WaitACKWB = '1') then
wb3_stb_i <= '1';
wb3_cyc_i <= '1';
end if;
end if;
end if;
end process wb3_control;
 
 
 
wb_rst_i <= '1', '0' after 60 ns; --active high
Clocking : process --50 MHz -> T = 20 ns
begin
wb_clk_i <= '1';
wait for 10 ns;
wb_clk_i <= '0';
wait for 10 ns;
end process;
 
END;

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