URL
https://opencores.org/ocsvn/csa/csa/trunk
Subversion Repositories csa
Compare Revisions
- This comparison shows the changes necessary to convert path
/csa/trunk
- from Rev 37 to Rev 38
- ↔ Reverse comparison
Rev 37 → Rev 38
/pc/misc.h
20,9 → 20,10
#define __MISC__ |
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#include <stdio.h> |
//#include <unistd.h> |
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#define DEBUG_LINE(fmt,arg...) \ |
do{ printf(fmt,##arg);printf("\n");fsync(stdout);}while(0) |
do{ printf(fmt,##arg);printf("\n");fflush(stdout);}while(0) |
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#endif |
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/pc/csa_test.c
17,6 → 17,8
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#include <memory.h> |
#include <stdlib.h> |
#include "misc.h" |
#include "imgdev.h" |
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23,6 → 25,7
int main() |
{ |
int i; |
unsigned char buf[256]; |
if(img_dev_open()<0) |
{ |
DEBUG_LINE("can not open image device"); |
31,8 → 34,11
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for(i=0;i<100;i++) |
{ |
//DEBUG_LINE("i=%d",i); |
img_write_data((unsigned char*)&i,sizeof i,0x08); |
DEBUG_LINE("i=%d",i); |
memset(buf,i,sizeof buf); |
//img_write_data((unsigned char*)buf,sizeof buf,0x08); |
img_write_data((unsigned char*)&i,2,0x08); |
sleep(1); |
} |
img_dev_close(); |
return 0; |
/pc/imgdev.c
75,6 → 75,9
return -3; |
i=usb_bulk_write(img_dev_handle, addr, (char*)buf, len, 500); |
if(i!=len) |
{ |
DEBUG_LINE("write data have some error i= %d",i); |
return -1; |
} |
return i; |
} |
/quartus10/csa_fpga.v
54,10 → 54,10
assign slcs =1'h0; |
assign pktend=1'h1; |
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`define EP2_W 2'h0 |
`define EP6_R 2'h1 |
`define EP8_R 2'h2 |
`define NO_ACT 2'h3 |
`define EP2_W 2'h3 |
`define EP6_R 2'h2 |
`define EP8_R 2'h1 |
`define NO_ACT 2'h0 |
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reg [ 1:0] last_action; |
reg [15:0] usb_dat_out; |
90,7 → 90,6
slwr<=1'h0; |
slrd<=1'h1; |
last_action<=`EP2_W; |
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end |
else |
begin |
101,6 → 100,7
last_action<=`NO_ACT; |
end |
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always @(posedge usbclk) |
if(last_action==`EP8_R ) |
usb_dat_in<=fd; |
/quartus10/hex2seg.v
4,6 → 4,7
, output reg [7:0] seg |
); |
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always @(hex) |
case (hex) // hgfedcba |
4'h0:seg<=~8'b00111111; |
/quartus10/ledseg_cnt.v
12,23 → 12,23
, output [ 7:0] segd // led segment output |
); |
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`define CNT_W 11 // count reg width |
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`define CNT_W 15 // count reg width |
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// interival variable |
reg [`CNT_W-1:0] cnt; |
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always @(posedge clk) |
cnt<=cnt+11'h001; // up reg |
cnt<=cnt+`CNT_W'h1; // up reg |
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reg h; |
reg [3:0] h; |
always @(cnt or data) |
begin |
case (cnt[`CNT_W-1:`CNT_W-2]) |
2'b00:h = data[15:12]; |
2'b01:h = data[11: 8]; |
2'b10:h = data[7 : 4]; |
2'b11:h = data[3 : 0]; |
default:h = 4'hf; |
2'b00:h <= data[15:12]; |
2'b01:h <= data[11: 8]; |
2'b10:h <= data[ 7: 4]; |
2'b11:h <= data[ 3: 0]; |
endcase |
end |
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39,7 → 39,6
2'b01:seg = 4'b1101; |
2'b10:seg = 4'b1011; |
2'b11:seg = 4'b0111; |
default:seg = 4'hf; |
endcase |
end |
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