URL
https://opencores.org/ocsvn/csa/csa/trunk
Subversion Repositories csa
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/csa
- from Rev 49 to Rev 50
- ↔ Reverse comparison
Rev 49 → Rev 50
/trunk/doc/readme
33,7 → 33,7
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cas core |
csa core |
=============== |
attached is a cas core implementation in verilog. it implement |
a cas descrambler |
42,13 → 42,55
csa.c and csa.h in vlc opensource project. |
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archecture |
=============== |
the top module is the group_decrypt. |
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Status |
====== |
7-sep-2007 added key csa_ComputeKey |
4-May-2009 group_decrypt module pass modelsim basicly |
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How to test this core |
======================== |
this project mainly has three dictories: |
rtl bench and sw_sim |
every module have a file in these dictories |
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i simualted my modules by open source program veriwell and iverilog in the early time , but |
they don't work well, and generate some error result sometime. so i use the modelsim now. |
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1) generate test data |
cd <core_root_dir> |
make MODULE=<module_name> preare_<module_name> ( for example: make MODULE=group_decrypt preare_group_decrypt ) |
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this command will generate a binary file <core_root_dir>/test_dat/<module_name>.in |
(for example: test_dat/group_decrypt.in ) |
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2) software simulate |
cd <core_root_dir>/sw_sim |
make MODULE=<module_name> tt |
this command will compile and run the module test program |
and will generate a binary output file <core_root_dir>/test_dat/<module_name>.out.sw |
(for example: test_dat/group_decrypt.out.sw ) |
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3) run test bench |
start the modelsim (i use the modelsim 6.2b LE) |
cd <core_root_dir>/modelsim6.2b |
run <module_name>.do tcl script, ( for example: do group_decrypt.do ) |
and will generate a binary output file <core_root_dir>/test_dat/<module_name>.out.v |
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if the two output file is same, this module is pass |
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Directory Structure |
=================== |
[core_root] |
58,9 → 100,21
+-bench--+ Test Bench |
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+-rtl----+ Core RTL Sources |
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+-modelsim6.2b--+ modelsim files |
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+-quartus10--+ altera quartus 10.1 project file |
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+-sw_sim-----+ the pc programs for generate some test data |
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+-test_data--+ the test datas for test bench |
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about the author |
================ |
if you have some issues and advance, please contact me: |
mengxipeng@gmail.com |
mengxipeng@gmail.com |
/trunk/makefile
1,4 → 1,4
MODULE=key_schedule |
MODULE:=key_schedule |
TEST_IN_FILE=test_dat/$(MODULE).in |
TEST_TIMES=1 |
DEBUG=n |
57,6 → 57,9
preare_key_schedule: |
$(call preare_bin_fn,8) |
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preare_group_decrypt: |
$(call preare_bin_fn,192) |
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preare_decrypt: |
#$(call preare_fn,204) # evenkey + oddkey + ts pacted (188) |
str=""; |
/trunk/README
0,0 → 1,9
see the doc/README |