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/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_rd_gray_cntr.vhd
0,0 → 1,147
--*****************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.6.1
-- \ \ Application : MIG
-- / / Filename : DDR2_Ram_Core_rd_gray_cntr.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
--
-- Device : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Purpose : This module generates read address for the FIFOs.
--*****************************************************************************
 
-- fifo_rd_addr gray counter with synchronous reset
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use UNISIM.VCOMPONENTS.all;
 
entity DDR2_Ram_Core_rd_gray_cntr is
port (
clk90 : in std_logic;
reset90 : in std_logic;
cnt_en : in std_logic;
rgc_gcnt : out std_logic_vector(3 downto 0)
);
end DDR2_Ram_Core_rd_gray_cntr;
 
architecture arc of DDR2_Ram_Core_rd_gray_cntr is
 
signal gc_int : std_logic_vector(3 downto 0);
signal d_in : std_logic_vector(3 downto 0);
signal reset90_r : std_logic;
 
begin
 
rgc_gcnt <= gc_int(3 downto 0);
process(clk90)
begin
if(clk90'event and clk90 = '1') then
reset90_r <= reset90;
end if;
end process;
 
process(gc_int)
begin
case gc_int is
when "0000" => d_in <= "0001"; --0 > 1
when "0001" => d_in <= "0011"; --1 > 3
when "0010" => d_in <= "0110"; --2 > 6
when "0011" => d_in <= "0010"; --3 > 2
when "0100" => d_in <= "1100"; --4 > c
when "0101" => d_in <= "0100"; --5 > 4
when "0110" => d_in <= "0111"; --6 > 7
when "0111" => d_in <= "0101"; --7 > 5
when "1000" => d_in <= "0000"; --8 > 0
when "1001" => d_in <= "1000"; --9 > 8
when "1010" => d_in <= "1011"; --10 > b
when "1011" => d_in <= "1001"; --11 > 9
when "1100" => d_in <= "1101"; --12 > d
when "1101" => d_in <= "1111"; --13 > f
when "1110" => d_in <= "1010"; --14 > a
when "1111" => d_in <= "1110"; --15 > e
when others => d_in <= "0001"; --0 > 1
end case;
end process;
 
bit0 : FDRE
port map (
Q => gc_int(0),
C => clk90,
CE => cnt_en,
D => d_in(0),
R => reset90_r
);
 
bit1 : FDRE
port map (
Q => gc_int(1),
C => clk90,
CE => cnt_en,
D => d_in(1),
R => reset90_r
);
 
bit2 : FDRE
port map (
Q => gc_int(2),
C => clk90,
CE => cnt_en,
D => d_in(2),
R => reset90_r
);
 
bit3 : FDRE
port map (
Q => gc_int(3),
C => clk90,
CE => cnt_en,
D => d_in(3),
R => reset90_r
);
end arc;
/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_controller_iobs_0.vhd
0,0 → 1,255
--*****************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.6.1
-- \ \ Application : MIG
-- / / Filename : DDR2_Ram_Core_controller_iobs_0.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
-- Device : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Purpose : This module has the IOB instantiations to address and control
-- signals.
--*****************************************************************************
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use UNISIM.VCOMPONENTS.all;
use work.DDR2_Ram_Core_parameters_0.all;
 
entity DDR2_Ram_Core_controller_iobs_0 is
port(
clk0 : in std_logic;
ddr_rasb_cntrl : in std_logic;
ddr_casb_cntrl : in std_logic;
ddr_web_cntrl : in std_logic;
ddr_cke_cntrl : in std_logic;
ddr_csb_cntrl : in std_logic;
ddr_odt_cntrl : in std_logic;
ddr_address_cntrl : in std_logic_vector((ROW_ADDRESS -1) downto 0);
ddr_ba_cntrl : in std_logic_vector((BANK_ADDRESS -1) downto 0);
rst_dqs_div_int : in std_logic;
ddr_odt : out std_logic;
ddr_rasb : out std_logic;
ddr_casb : out std_logic;
ddr_web : out std_logic;
ddr_ba : out std_logic_vector((BANK_ADDRESS -1) downto 0);
ddr_address : out std_logic_vector((ROW_ADDRESS -1) downto 0);
ddr_cke : out std_logic;
ddr_csb : out std_logic;
rst_dqs_div : out std_logic;
rst_dqs_div_in : in std_logic;
rst_dqs_div_out : out std_logic
);
end DDR2_Ram_Core_controller_iobs_0;
 
architecture arc of DDR2_Ram_Core_controller_iobs_0 is
 
signal ddr_web_q : std_logic;
signal ddr_rasb_q : std_logic;
signal ddr_casb_q : std_logic;
signal ddr_cke_q : std_logic;
signal ddr_cke_int : std_logic;
signal ddr_address_reg : std_logic_vector((ROW_ADDRESS -1) downto 0);
signal ddr_ba_reg : std_logic_vector((BANK_ADDRESS -1) downto 0);
signal ddr_odt_reg : std_logic;
signal clk180 : std_logic;
attribute iob : string;
attribute syn_useioff : boolean;
 
attribute iob of iob_rasb : label is "FORCE";
attribute iob of iob_casb : label is "FORCE";
attribute iob of iob_web : label is "FORCE";
attribute iob of iob_cke : label is "FORCE";
attribute iob of iob_odt : label is "FORCE";
attribute syn_useioff of iob_rasb : label is true;
attribute syn_useioff of iob_casb : label is true;
attribute syn_useioff of iob_web : label is true;
attribute syn_useioff of iob_cke : label is true;
attribute syn_useioff of iob_odt : label is true;
 
begin
 
clk180 <= not clk0;
 
---- ******************************************* ----
---- Includes the instantiation of FD for cntrl ----
---- signals ----
---- ******************************************* ----
 
iob_web : FD
port map (
Q => ddr_web_q,
D => ddr_web_cntrl,
C => clk180
);
 
iob_rasb : FD
port map (
Q => ddr_rasb_q,
D => ddr_rasb_cntrl,
C => clk180
);
 
iob_casb : FD
port map (
Q => ddr_casb_q,
D => ddr_casb_cntrl,
C => clk180
);
 
---- ************************************* ----
---- Output buffers for control signals ----
---- ************************************* ----
 
r16 : OBUF
port map (
I => ddr_web_q,
O => ddr_web
);
 
r17 : OBUF
port map (
I => ddr_rasb_q,
O => ddr_rasb
);
 
r18 : OBUF
port map (
I => ddr_casb_q,
O => ddr_casb
);
 
r19 : OBUF
port map (
I => ddr_csb_cntrl,
O => ddr_csb
);
 
iob_cke1 : FD
port map(
Q => ddr_cke_int,
D => ddr_cke_cntrl,
C => clk0
);
 
iob_cke : FD
port map(
Q => ddr_cke_q,
D => ddr_cke_int,
C => clk180
);
 
r20 : OBUF
port map (
I => ddr_cke_q,
O => ddr_cke
);
 
iob_odt : FD
port map (
Q => ddr_ODT_reg,
D => ddr_ODT_cntrl,
C => clk180
);
 
ODT_iob_obuf : OBUF
port map (
I => ddr_ODT_reg,
O => ddr_ODT
);
 
---- ******************************************* ----
---- Includes the instantiation of FD and OBUF ----
---- for row address and bank address ----
---- ******************************************* ----
 
gen_addr : for i in (ROW_ADDRESS -1) downto 0 generate
attribute IOB of iob_addr : label is "FORCE";
attribute syn_useioff of iob_addr : label is true;
begin
iob_addr : FD
port map (
Q => ddr_address_reg(i),
D => ddr_address_cntrl(i),
C => clk180
);
r : OBUF
port map (
I => ddr_address_reg(i),
O => ddr_address(i)
);
end generate;
 
gen_ba : for i in (BANK_ADDRESS -1) downto 0 generate
attribute IOB of iob_ba : label is "FORCE";
attribute syn_useioff of iob_ba : label is true;
begin
iob_ba : FD
port map (
Q => ddr_ba_reg(i),
D => ddr_ba_cntrl(i),
C => clk180
);
r : OBUF
port map (
I => ddr_ba_reg(i),
O => ddr_ba(i)
);
end generate;
 
rst_iob_inbuf : IBUF
port map(
I => rst_dqs_div_in,
O => rst_dqs_div
);
 
rst_iob_outbuf : OBUF
port map (
I => rst_dqs_div_int,
O => rst_dqs_div_out
);
 
end arc;
/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_infrastructure.vhd
0,0 → 1,110
--*****************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.6.1
-- \ \ Application : MIG
-- / / Filename : DDR2_Ram_Core_infrastructure.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
-- Device : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Purpose :
--*****************************************************************************
 
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use UNISIM.VCOMPONENTS.all;
 
 
entity DDR2_Ram_Core_infrastructure is
port(
delay_sel_val1_val : out std_logic_vector(4 downto 0);
delay_sel_val : in std_logic_vector(4 downto 0);
rst_calib1 : in std_logic;
clk_int : in std_logic;
-- debug signals
dbg_delay_sel : out std_logic_vector(4 downto 0);
dbg_rst_calib : out std_logic
);
end DDR2_Ram_Core_infrastructure;
 
architecture arc of DDR2_Ram_Core_infrastructure is
signal delay_sel_val1 : std_logic_vector(4 downto 0);
signal rst_calib1_r1 : std_logic;
signal rst_calib1_r2 : std_logic;
begin
 
delay_sel_val1_val <= delay_sel_val1;
dbg_delay_sel <= delay_sel_val1;
dbg_rst_calib <= rst_calib1_r2;
 
process(clk_int)
begin
if clk_int 'event and clk_int = '0' then
rst_calib1_r1 <= rst_calib1;
end if;
end process;
 
process(clk_int)
begin
if clk_int 'event and clk_int = '1' then
rst_calib1_r2 <= rst_calib1_r1;
end if;
end process;
 
process(clk_int)
begin
if clk_int 'event and clk_int = '1' then
if (rst_calib1_r2 = '0') then
delay_sel_val1 <= delay_sel_val;
else
delay_sel_val1 <= delay_sel_val1;
end if;
end if;
end process;
 
end arc;
/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core.vhd
0,0 → 1,289
--*****************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.6.1
-- \ \ Application : MIG
-- / / Filename : %module_name.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
-- Device : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Purpose : This module has the instantiations infrastructure_top and
-- main modules.
--*****************************************************************************
 
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use UNISIM.VCOMPONENTS.all;
 
entity DDR2_Ram_Core is
port (
cntrl0_ddr2_dq : inout std_logic_vector(15 downto 0);
cntrl0_ddr2_a : out std_logic_vector(12 downto 0);
cntrl0_ddr2_ba : out std_logic_vector(1 downto 0);
cntrl0_ddr2_cke : out std_logic;
cntrl0_ddr2_cs_n : out std_logic;
cntrl0_ddr2_ras_n : out std_logic;
cntrl0_ddr2_cas_n : out std_logic;
cntrl0_ddr2_we_n : out std_logic;
cntrl0_ddr2_odt : out std_logic;
cntrl0_ddr2_dm : out std_logic_vector(1 downto 0);
cntrl0_rst_dqs_div_in : in std_logic;
cntrl0_rst_dqs_div_out : out std_logic;
sys_clk_in : in std_logic;
reset_in_n : in std_logic;
cntrl0_burst_done : in std_logic;
cntrl0_init_done : out std_logic;
cntrl0_ar_done : out std_logic;
cntrl0_user_data_valid : out std_logic;
cntrl0_auto_ref_req : out std_logic;
cntrl0_user_cmd_ack : out std_logic;
cntrl0_user_command_register : in std_logic_vector(2 downto 0);
cntrl0_clk_tb : out std_logic;
cntrl0_clk90_tb : out std_logic;
cntrl0_sys_rst_tb : out std_logic;
cntrl0_sys_rst90_tb : out std_logic;
cntrl0_sys_rst180_tb : out std_logic;
cntrl0_user_output_data : out std_logic_vector(31 downto 0);
cntrl0_user_input_data : in std_logic_vector(31 downto 0);
cntrl0_user_data_mask : in std_logic_vector(3 downto 0);
cntrl0_user_input_address : in std_logic_vector(24 downto 0);
cntrl0_ddr2_dqs : inout std_logic_vector(1 downto 0);
cntrl0_ddr2_dqs_n : inout std_logic_vector(1 downto 0);
cntrl0_ddr2_ck : out std_logic_vector(0 downto 0);
cntrl0_ddr2_ck_n : out std_logic_vector(0 downto 0)
);
end DDR2_Ram_Core;
 
architecture arc_mem_interface_top of DDR2_Ram_Core is
 
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO : STRING;
 
ATTRIBUTE X_CORE_INFO of arc_mem_interface_top : ARCHITECTURE IS "mig_v3_61_ddr2_sp3, Coregen 12.4";
ATTRIBUTE CORE_GENERATION_INFO of arc_mem_interface_top : ARCHITECTURE IS "ddr2_sp3,mig_v3_61,{component_name=ddr2_sp3, data_width=16, memory_width=8, clk_width=1, bank_address=2, row_address=13, column_address=10, no_of_cs=1, cke_width=1, registered=0, data_mask=1, mask_enable=1, load_mode_register=0010100110010, ext_load_mode_register=0000000000000, language=VHDL, synthesis_tool=ISE, interface_type=DDR2_SDRAM, no_of_controllers=1}";
 
component DDR2_Ram_Core_top_0
port(
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_a : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(1 downto 0);
ddr2_cke : out std_logic;
ddr2_cs_n : out std_logic;
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_odt : out std_logic;
ddr2_dm : out std_logic_vector(1 downto 0);
rst_dqs_div_in : in std_logic;
rst_dqs_div_out : out std_logic;
burst_done : in std_logic;
init_done : out std_logic;
ar_done : out std_logic;
user_data_valid : out std_logic;
auto_ref_req : out std_logic;
user_cmd_ack : out std_logic;
user_command_register : in std_logic_vector(2 downto 0);
clk_tb : out std_logic;
clk90_tb : out std_logic;
sys_rst_tb : out std_logic;
sys_rst90_tb : out std_logic;
sys_rst180_tb : out std_logic;
user_output_data : out std_logic_vector(31 downto 0);
user_input_data : in std_logic_vector(31 downto 0);
user_data_mask : in std_logic_vector(3 downto 0);
user_input_address : in std_logic_vector(24 downto 0);
ddr2_dqs : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
ddr2_ck : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
clk_int : in std_logic;
clk90_int : in std_logic;
wait_200us : in std_logic;
sys_rst : in std_logic;
sys_rst90 : in std_logic;
sys_rst180 : in std_logic;
delay_sel_val : in std_logic_vector(4 downto 0);
--Debug ports
 
dbg_delay_sel : out std_logic_vector(4 downto 0);
dbg_rst_calib : out std_logic;
vio_out_dqs : in std_logic_vector(4 downto 0);
vio_out_dqs_en : in std_logic;
vio_out_rst_dqs_div : in std_logic_vector(4 downto 0);
vio_out_rst_dqs_div_en : in std_logic
);
end component;
 
component DDR2_Ram_Core_infrastructure_top
port (
sys_clkb : in std_logic;
sys_clk : in std_logic;
sys_clk_in : in std_logic;
reset_in_n : in std_logic;
wait_200us : out std_logic;
delay_sel_val1_val : out std_logic_vector(4 downto 0);
sys_rst_val : out std_logic;
sys_rst90_val : out std_logic;
clk_int_val : out std_logic;
clk90_int_val : out std_logic;
sys_rst180_val : out std_logic;
dbg_phase_cnt : out std_logic_vector(4 downto 0);
dbg_cnt : out std_logic_vector(5 downto 0);
dbg_trans_onedtct : out std_logic;
dbg_trans_twodtct : out std_logic;
dbg_enb_trans_two_dtct : out std_logic
);
end component;
 
 
 
signal sys_rst : std_logic;
signal wait_200us : std_logic;
signal sys_rst90 : std_logic;
signal sys_rst180 : std_logic;
signal clk_0 : std_logic;
signal clk90_0 : std_logic;
signal delay_sel : std_logic_vector(4 downto 0);
-- debug signals
signal dbg_phase_cnt : std_logic_vector(4 downto 0);
signal dbg_cnt : std_logic_vector(5 downto 0);
signal dbg_trans_onedtct : std_logic;
signal dbg_trans_twodtct : std_logic;
signal dbg_enb_trans_two_dtct : std_logic;
signal dbg_delay_sel : std_logic_vector(4 downto 0);
signal dbg_rst_calib : std_logic;
-- chipscope signals
signal dbg_data : std_logic_vector(19 downto 0);
signal dbg_trig : std_logic_vector(3 downto 0);
signal control0 : std_logic_vector(35 downto 0);
signal control1 : std_logic_vector(35 downto 0);
signal vio_out_dqs : std_logic_vector(4 downto 0);
signal vio_out_dqs_en : std_logic;
signal vio_out_rst_dqs_div : std_logic_vector(4 downto 0);
signal vio_out_rst_dqs_div_en : std_logic;
signal vio_out : std_logic_vector(11 downto 0);
signal sys_clkb : std_logic;
signal sys_clk : std_logic;
 
begin
 
sys_clkb <= '0';
sys_clk <= '0';
 
top_00 : DDR2_Ram_Core_top_0
port map (
ddr2_dq => cntrl0_ddr2_dq,
ddr2_a => cntrl0_ddr2_a,
ddr2_ba => cntrl0_ddr2_ba,
ddr2_cke => cntrl0_ddr2_cke,
ddr2_cs_n => cntrl0_ddr2_cs_n,
ddr2_ras_n => cntrl0_ddr2_ras_n,
ddr2_cas_n => cntrl0_ddr2_cas_n,
ddr2_we_n => cntrl0_ddr2_we_n,
ddr2_odt => cntrl0_ddr2_odt,
ddr2_dm => cntrl0_ddr2_dm,
rst_dqs_div_in => cntrl0_rst_dqs_div_in,
rst_dqs_div_out => cntrl0_rst_dqs_div_out,
burst_done => cntrl0_burst_done,
init_done => cntrl0_init_done,
ar_done => cntrl0_ar_done,
user_data_valid => cntrl0_user_data_valid,
auto_ref_req => cntrl0_auto_ref_req,
user_cmd_ack => cntrl0_user_cmd_ack,
user_command_register => cntrl0_user_command_register,
clk_tb => cntrl0_clk_tb,
clk90_tb => cntrl0_clk90_tb,
sys_rst_tb => cntrl0_sys_rst_tb,
sys_rst90_tb => cntrl0_sys_rst90_tb,
sys_rst180_tb => cntrl0_sys_rst180_tb,
user_output_data => cntrl0_user_output_data,
user_input_data => cntrl0_user_input_data,
user_data_mask => cntrl0_user_data_mask,
user_input_address => cntrl0_user_input_address,
ddr2_dqs => cntrl0_ddr2_dqs,
ddr2_dqs_n => cntrl0_ddr2_dqs_n,
ddr2_ck => cntrl0_ddr2_ck,
ddr2_ck_n => cntrl0_ddr2_ck_n,
wait_200us => wait_200us,
delay_sel_val => delay_sel,
clk_int => clk_0,
clk90_int => clk90_0,
sys_rst => sys_rst,
sys_rst90 => sys_rst90,
sys_rst180 => sys_rst180,
 
--Debug signals
 
dbg_delay_sel => dbg_delay_sel,
dbg_rst_calib => dbg_rst_calib,
vio_out_dqs => vio_out_dqs,
vio_out_dqs_en => vio_out_dqs_en,
vio_out_rst_dqs_div => vio_out_rst_dqs_div,
vio_out_rst_dqs_div_en => vio_out_rst_dqs_div_en
);
 
infrastructure_top0 : DDR2_Ram_Core_infrastructure_top
port map (
wait_200us => wait_200us,
delay_sel_val1_val => delay_sel,
clk_int_val => clk_0,
clk90_int_val => clk90_0,
sys_rst_val => sys_rst,
sys_rst90_val => sys_rst90,
sys_rst180_val => sys_rst180,
dbg_phase_cnt => dbg_phase_cnt,
dbg_cnt => dbg_cnt,
dbg_trans_onedtct => dbg_trans_onedtct,
dbg_trans_twodtct => dbg_trans_twodtct,
dbg_enb_trans_two_dtct => dbg_enb_trans_two_dtct,
sys_clkb => sys_clkb,
sys_clk => sys_clk,
sys_clk_in => sys_clk_in,
reset_in_n => reset_in_n
);
 
 
 
end arc_mem_interface_top;
/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_data_path_iobs_0.vhd
0,0 → 1,173
--*****************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.6.1
-- \ \ Application : MIG
-- / / Filename : DDR2_Ram_Core_parameters_0.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
-- Device : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Purpose : This module has the instantiations s3_dq_iob, s3_dqs_iob and
-- s3_dm_iob modules.
--*****************************************************************************
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
use work.DDR2_Ram_Core_parameters_0.all;
 
entity DDR2_Ram_Core_data_path_iobs_0 is
port(
clk : in std_logic;
clk90 : in std_logic;
dqs_reset : in std_logic;
dqs_enable : in std_logic;
ddr_dqs : inout std_logic_vector((DATA_STROBE_WIDTH -1) downto 0);
ddr_dqs_n : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
ddr_dq : inout std_logic_vector((DATA_WIDTH-1) downto 0);
write_data_falling : in std_logic_vector((DATA_WIDTH-1) downto 0);
write_data_rising : in std_logic_vector((DATA_WIDTH-1) downto 0);
write_en_val : in std_logic;
data_mask_f : in std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
data_mask_r : in std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
dqs_int_delay_in : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
ddr_dm : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
ddr_dq_val : out std_logic_vector((DATA_WIDTH-1) downto 0)
);
end DDR2_Ram_Core_data_path_iobs_0;
 
architecture arc of DDR2_Ram_Core_data_path_iobs_0 is
 
component DDR2_Ram_Core_s3_dqs_iob
port(
clk : in std_logic;
ddr_dqs_reset : in std_logic;
ddr_dqs_enable : in std_logic;
ddr_dqs : inout std_logic;
ddr_dqs_n : inout std_logic;
dqs : out std_logic
);
end component;
 
component DDR2_Ram_Core_s3_dq_iob
port (
ddr_dq_inout : inout std_logic; --Bi-directional SDRAM data bus
write_data_falling : in std_logic; --Transmit data, output on falling edge
write_data_rising : in std_logic; --Transmit data, output on rising edge
read_data_in : out std_logic; -- Received data
clk90 : in std_logic;
write_en_val : in std_logic
);
end component;
 
component DDR2_Ram_Core_s3_dm_iob
port (
ddr_dm : out std_logic;
mask_falling : in std_logic;
mask_rising : in std_logic;
clk90 : in std_logic
);
end component;
 
signal ddr_dq_in : std_logic_vector((DATA_WIDTH-1) downto 0);
 
begin
 
ddr_dq_val <= ddr_dq_in;
 
--***********************************************************************
-- DM IOB instantiations
--***********************************************************************
MASK_INST : if(MASK_ENABLE = 1) generate
begin
gen_dm: for dm_i in 0 to DATA_MASK_WIDTH-1 generate
s3_dm_iob_inst : DDR2_Ram_Core_s3_dm_iob
port map (
ddr_dm => ddr_dm(dm_i),
mask_falling => data_mask_f(dm_i),
mask_rising => data_mask_r(dm_i),
clk90 => clk90
);
end generate;
end generate MASK_INST;
 
--***********************************************************************
-- Read Data Capture Module Instantiations
--***********************************************************************
-- DQS IOB instantiations
--***********************************************************************
gen_dqs: for dqs_i in 0 to DATA_STROBE_WIDTH-1 generate
s3_dqs_iob_inst : DDR2_Ram_Core_s3_dqs_iob
port map (
clk => clk,
ddr_dqs_reset => dqs_reset,
ddr_dqs_enable => dqs_enable,
ddr_dqs => ddr_dqs(dqs_i),
ddr_dqs_n => ddr_dqs_n(dqs_i),
dqs => dqs_int_delay_in(dqs_i)
);
end generate;
 
 
 
--******************************************************************************
-- DDR Data bit instantiations
--******************************************************************************
 
gen_dq: for dq_i in 0 to DATA_WIDTH-1 generate
s3_dq_iob_inst : DDR2_Ram_Core_s3_dq_iob
port map (
ddr_dq_inout => ddr_dq(dq_i),
write_data_falling => write_data_falling(dq_i),
write_data_rising => write_data_rising(dq_i),
read_data_in => ddr_dq_in(dq_i),
clk90 => clk90,
write_en_val => write_en_val
);
end generate;
 
end arc;
/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_cal_top.vhd
0,0 → 1,134
--*****************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.6.1
-- \ \ Application : MIG
-- / / Filename : DDR2_Ram_Core_cal_to.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
-- Device : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Purpose : This module has the instantiations cal_ctl and tap_dly.
--*****************************************************************************
 
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use UNISIM.VCOMPONENTS.all;
 
entity DDR2_Ram_Core_cal_top is
port(
clk : in std_logic;
clk0dcmlock : in std_logic;
reset : in std_logic;
tapfordqs : out std_logic_vector(4 downto 0);
-- debug signals
dbg_phase_cnt : out std_logic_vector(4 downto 0);
dbg_cnt : out std_logic_vector(5 downto 0);
dbg_trans_onedtct : out std_logic;
dbg_trans_twodtct : out std_logic;
dbg_enb_trans_two_dtct : out std_logic
);
end DDR2_Ram_Core_cal_top;
 
architecture arc of DDR2_Ram_Core_cal_top is
 
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO : STRING;
 
ATTRIBUTE X_CORE_INFO of arc : ARCHITECTURE IS "mig_v3_61_ddr2_sp3, Coregen 12.4";
ATTRIBUTE CORE_GENERATION_INFO of arc : ARCHITECTURE IS "ddr2_sp3,mig_v3_61,{component_name=ddr2_sp3, data_width=16, memory_width=8, clk_width=1, bank_address=2, row_address=13, column_address=10, no_of_cs=1, cke_width=1, registered=0, data_mask=1, mask_enable=1, load_mode_register=0010100110010, ext_load_mode_register=0000000000000, language=VHDL, synthesis_tool=ISE, interface_type=DDR2_SDRAM, no_of_controllers=1}";
 
component DDR2_Ram_Core_cal_ctl
port (
clk : in std_logic;
reset : in std_logic;
flop2 : in std_logic_vector(31 downto 0);
tapfordqs : out std_logic_vector(4 downto 0);
dbg_phase_cnt : out std_logic_vector(4 downto 0);
dbg_cnt : out std_logic_vector(5 downto 0);
dbg_trans_onedtct : out std_logic;
dbg_trans_twodtct : out std_logic;
dbg_enb_trans_two_dtct : out std_logic
);
end component;
 
component DDR2_Ram_Core_tap_dly
port (
clk : in std_logic;
reset : in std_logic;
tapin : in std_logic;
flop2 : out std_logic_vector(31 downto 0)
);
end component;
 
signal fpga_rst : std_logic;
signal flop2_val : std_logic_vector(31 downto 0);
 
begin
 
fpga_rst <= (not reset) or (not clk0dcmlock);
 
cal_ctl0 : DDR2_Ram_Core_cal_ctl
port map(
clk => clk,
reset => fpga_rst,
flop2 => flop2_val,
tapfordqs => tapfordqs,
dbg_phase_cnt => dbg_phase_cnt,
dbg_cnt => dbg_cnt,
dbg_trans_onedtct => dbg_trans_onedtct,
dbg_trans_twodtct => dbg_trans_twodtct,
dbg_enb_trans_two_dtct => dbg_enb_trans_two_dtct
);
 
tap_dly0 : DDR2_Ram_Core_tap_dly
port map (
clk => clk,
reset => fpga_rst,
tapin => clk,
flop2 => flop2_val
);
 
end arc;
/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_top_0.vhd
0,0 → 1,379
--*****************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.6.1
-- \ \ Application : MIG
-- / / Filename : DDR2_Ram_Core_top_0.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
-- Device : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Purpose : This modules has the instantiations infrastructure, iobs,
-- controller and data_paths modules
--*****************************************************************************
 
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use work.DDR2_Ram_Core_parameters_0.all;
use UNISIM.VCOMPONENTS.all;
 
entity DDR2_Ram_Core_top_0 is
port(
wait_200us : in std_logic;
rst_dqs_div_in : in std_logic;
rst_dqs_div_out : out std_logic;
 
user_input_data : in std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
user_data_mask : in std_logic_vector(((DATA_MASK_WIDTH*2)-1) downto 0);
user_output_data : out std_logic_vector(((2*DATA_WIDTH)-1)
downto 0) := (others => 'Z');
user_data_valid : out std_logic;
user_input_address : in std_logic_vector(((ROW_ADDRESS +
COLUMN_ADDRESS + BANK_ADDRESS)-1) downto 0);
user_command_register : in std_logic_vector(2 downto 0);
burst_done : in std_logic;
auto_ref_req : out std_logic;
user_cmd_ack : out std_logic;
init_done : out std_logic;
ar_done : out std_logic;
ddr2_dqs : inout std_logic_vector((DATA_STROBE_WIDTH -1) downto 0);
ddr2_dqs_n : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
ddr2_dq : inout std_logic_vector((DATA_WIDTH-1) downto 0)
:= (others => 'Z');
ddr2_cke : out std_logic;
ddr2_cs_n : out std_logic;
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_dm : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
ddr2_ba : out std_logic_vector((BANK_ADDRESS-1) downto 0);
ddr2_a : out std_logic_vector((ROW_ADDRESS-1) downto 0);
ddr2_odt : out std_logic;
ddr2_ck : out std_logic_vector((CLK_WIDTH-1) downto 0);
ddr2_ck_n : out std_logic_vector((CLK_WIDTH-1) downto 0);
clk_tb : out std_logic;
clk90_tb : out std_logic;
sys_rst_tb : out std_logic;
sys_rst90_tb : out std_logic;
sys_rst180_tb : out std_logic;
clk_int : in std_logic;
clk90_int : in std_logic;
delay_sel_val : in std_logic_vector(4 downto 0);
sys_rst : in std_logic;
sys_rst90 : in std_logic;
sys_rst180 : in std_logic;
-- debug signals
dbg_delay_sel : out std_logic_vector(4 downto 0);
dbg_rst_calib : out std_logic;
vio_out_dqs : in std_logic_vector(4 downto 0);
vio_out_dqs_en : in std_logic;
vio_out_rst_dqs_div : in std_logic_vector(4 downto 0);
vio_out_rst_dqs_div_en : in std_logic
);
 
end DDR2_Ram_Core_top_0;
 
architecture arc of DDR2_Ram_Core_top_0 is
 
component DDR2_Ram_Core_controller_0
port(
auto_ref_req : out std_logic;
wait_200us : in std_logic;
clk : in std_logic;
rst0 : in std_logic;
rst180 : in std_logic;
address : in std_logic_vector(((ROW_ADDRESS + COLUMN_ADDRESS)-1)
downto 0);
bank_addr : in std_logic_vector((BANK_ADDRESS-1) downto 0);
command_register : in std_logic_vector(2 downto 0);
burst_done : in std_logic;
ddr_rasb_cntrl : out std_logic;
ddr_casb_cntrl : out std_logic;
ddr_web_cntrl : out std_logic;
ddr_ba_cntrl : out std_logic_vector((BANK_ADDRESS-1) downto 0);
ddr_address_cntrl : out std_logic_vector((ROW_ADDRESS-1) downto 0);
ddr_cke_cntrl : out std_logic;
ddr_csb_cntrl : out std_logic;
ddr_ODT_cntrl : out std_logic;
dqs_enable : out std_logic;
dqs_reset : out std_logic;
write_enable : out std_logic;
rst_calib : out std_logic;
rst_dqs_div_int : out std_logic;
cmd_ack : out std_logic;
init : out std_logic;
ar_done : out std_logic;
read_fifo_rden : out std_logic -- Added new signal
);
end component;
 
component DDR2_Ram_Core_data_path_0
port(
user_input_data : in std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
user_data_mask : in std_logic_vector(((2*DATA_MASK_WIDTH)-1) downto 0);
clk : in std_logic;
clk90 : in std_logic;
reset : in std_logic;
reset90 : in std_logic;
write_enable : in std_logic;
rst_dqs_div_in : in std_logic;
delay_sel : in std_logic_vector(4 downto 0);
dqs_int_delay_in : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
dq : in std_logic_vector((DATA_WIDTH-1) downto 0);
u_data_val : out std_logic;
user_output_data : out std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
write_en_val : out std_logic;
data_mask_f : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
data_mask_r : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
write_data_falling : out std_logic_vector((DATA_WIDTH-1) downto 0);
write_data_rising : out std_logic_vector((DATA_WIDTH-1) downto 0);
read_fifo_rden : in std_logic; -- Added new signal
-- debug singals
vio_out_dqs : in std_logic_vector(4 downto 0);
vio_out_dqs_en : in std_logic;
vio_out_rst_dqs_div : in std_logic_vector(4 downto 0);
vio_out_rst_dqs_div_en : in std_logic
 
);
end component;
 
component DDR2_Ram_Core_infrastructure
port(
clk_int : in std_logic;
rst_calib1 : in std_logic;
delay_sel_val : in std_logic_vector(4 downto 0);
delay_sel_val1_val : out std_logic_vector(4 downto 0);
-- debug signals
dbg_delay_sel : out std_logic_vector(4 downto 0);
dbg_rst_calib : out std_logic
);
end component;
component DDR2_Ram_Core_iobs_0
port(
clk : in std_logic;
clk90 : in std_logic;
ddr_rasb_cntrl : in std_logic;
ddr_casb_cntrl : in std_logic;
ddr_web_cntrl : in std_logic;
ddr_cke_cntrl : in std_logic;
ddr_csb_cntrl : in std_logic;
ddr_ODT_cntrl : in std_logic;
ddr_address_cntrl : in std_logic_vector((ROW_ADDRESS-1) downto 0);
ddr_ba_cntrl : in std_logic_vector((BANK_ADDRESS-1) downto 0);
rst_dqs_div_int : in std_logic;
dqs_reset : in std_logic;
dqs_enable : in std_logic;
ddr_dqs : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
ddr_dqs_n : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
ddr_dq : inout std_logic_vector((DATA_WIDTH-1) downto 0);
write_data_falling : in std_logic_vector((DATA_WIDTH-1) downto 0);
write_data_rising : in std_logic_vector((DATA_WIDTH-1) downto 0);
write_en_val : in std_logic;
data_mask_f : in std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
data_mask_r : in std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
ddr_odt : out std_logic;
ddr2_ck : out std_logic_vector((CLK_WIDTH-1) downto 0);
ddr2_ck_n : out std_logic_vector((CLK_WIDTH-1) downto 0);
ddr_rasb : out std_logic;
ddr_casb : out std_logic;
ddr_web : out std_logic;
ddr_ba : out std_logic_vector((BANK_ADDRESS-1) downto 0);
ddr_address : out std_logic_vector((ROW_ADDRESS-1) downto 0);
ddr_cke : out std_logic;
ddr_csb : out std_logic;
rst_dqs_div : out std_logic;
rst_dqs_div_in : in std_logic;
rst_dqs_div_out : out std_logic;
dqs_int_delay_in : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
ddr_dm : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
dq : out std_logic_vector((DATA_WIDTH-1) downto 0)
);
end component;
signal rst_calib : std_logic;
signal delay_sel : std_logic_vector(4 downto 0);
signal write_enable : std_logic;
signal dqs_div_rst : std_logic;
signal dqs_enable : std_logic;
signal dqs_reset : std_logic;
signal dqs_int_delay_in : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
signal dq : std_logic_vector((DATA_WIDTH-1) downto 0);
signal write_en_val : std_logic;
signal data_mask_f : std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
signal data_mask_r : std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
signal write_data_falling : std_logic_vector((DATA_WIDTH-1) downto 0);
signal write_data_rising : std_logic_vector((DATA_WIDTH-1) downto 0);
signal ddr_rasb_cntrl : std_logic;
signal ddr_casb_cntrl : std_logic;
signal ddr_web_cntrl : std_logic;
signal ddr_ba_cntrl : std_logic_vector((BANK_ADDRESS-1) downto 0);
signal ddr_address_cntrl : std_logic_vector((ROW_ADDRESS-1) downto 0);
signal ddr_cke_cntrl : std_logic;
signal ddr_csb_cntrl : std_logic;
signal ddr_odt_cntrl : std_logic;
signal rst_dqs_div_int : std_logic;
signal read_fifo_rden : std_logic;
begin
 
 
clk_tb <= clk_int after 1 ps;
clk90_tb <= clk90_int after 1 ps;
sys_rst_tb <= sys_rst;
sys_rst90_tb <= sys_rst90;
sys_rst180_tb <= sys_rst180;
 
controller0 : DDR2_Ram_Core_controller_0
port map (
auto_ref_req => auto_ref_req,
wait_200us => wait_200us,
clk => clk_int,
rst0 => sys_rst,
rst180 => sys_rst180,
address => user_input_address(((ROW_ADDRESS + COLUMN_ADDRESS +
BANK_ADDRESS)-1) downto BANK_ADDRESS),
bank_addr => user_input_address(BANK_ADDRESS-1 downto 0),
command_register => user_command_register,
burst_done => burst_done,
ddr_rasb_cntrl => ddr_rasb_cntrl,
ddr_casb_cntrl => ddr_casb_cntrl,
ddr_web_cntrl => ddr_web_cntrl,
ddr_ba_cntrl => ddr_ba_cntrl,
ddr_address_cntrl => ddr_address_cntrl,
ddr_cke_cntrl => ddr_cke_cntrl,
ddr_csb_cntrl => ddr_csb_cntrl,
ddr_odt_cntrl => ddr_odt_cntrl,
dqs_enable => dqs_enable,
dqs_reset => dqs_reset,
write_enable => write_enable,
rst_calib => rst_calib,
rst_dqs_div_int => rst_dqs_div_int,
cmd_ack => user_cmd_ack,
init => init_done,
ar_done => ar_done,
read_fifo_rden => read_fifo_rden -- Added new signal
);
 
data_path0 : DDR2_Ram_Core_data_path_0
port map (
user_input_data => user_input_data,
user_data_mask => user_data_mask,
clk => clk_int,
clk90 => clk90_int,
reset => sys_rst,
reset90 => sys_rst90,
write_enable => write_enable,
rst_dqs_div_in => dqs_div_rst,
delay_sel => delay_sel,
dqs_int_delay_in => dqs_int_delay_in,
dq => dq,
u_data_val => user_data_valid,
user_output_data => user_output_data,
write_en_val => write_en_val,
data_mask_f => data_mask_f,
data_mask_r => data_mask_r,
write_data_falling => write_data_falling,
write_data_rising => write_data_rising,
read_fifo_rden => read_fifo_rden, -- Added new signal
--debug signals
vio_out_dqs => vio_out_dqs,
vio_out_dqs_en => vio_out_dqs_en,
vio_out_rst_dqs_div => vio_out_rst_dqs_div,
vio_out_rst_dqs_div_en => vio_out_rst_dqs_div_en
);
 
infrastructure0 : DDR2_Ram_Core_infrastructure
port map (
clk_int => clk_int,
rst_calib1 => rst_calib,
delay_sel_val => delay_sel_val,
delay_sel_val1_val => delay_sel,
dbg_delay_sel => dbg_delay_sel,
dbg_rst_calib => dbg_rst_calib
);
 
iobs0 : DDR2_Ram_Core_iobs_0
port map (
clk => clk_int,
clk90 => clk90_int,
ddr_rasb_cntrl => ddr_rasb_cntrl,
ddr_casb_cntrl => ddr_casb_cntrl,
ddr_odt_cntrl => ddr_odt_cntrl,
ddr_web_cntrl => ddr_web_cntrl,
ddr_cke_cntrl => ddr_cke_cntrl,
ddr_csb_cntrl => ddr_csb_cntrl,
ddr_address_cntrl => ddr_address_cntrl,
ddr_ba_cntrl => ddr_ba_cntrl,
rst_dqs_div_int => rst_dqs_div_int,
dqs_reset => dqs_reset,
dqs_enable => dqs_enable,
ddr_dqs => ddr2_dqs,
ddr_dqs_n => ddr2_dqs_n,
ddr_dq => ddr2_dq,
write_data_falling => write_data_falling,
write_data_rising => write_data_rising,
write_en_val => write_en_val,
data_mask_f => data_mask_f,
data_mask_r => data_mask_r,
ddr_odt => ddr2_odt,
ddr2_ck => ddr2_ck,
ddr2_ck_n => ddr2_ck_n,
ddr_rasb => ddr2_ras_n,
ddr_casb => ddr2_cas_n,
ddr_web => ddr2_we_n,
ddr_ba => ddr2_ba,
ddr_address => ddr2_a,
ddr_cke => ddr2_cke,
ddr_csb => ddr2_cs_n,
rst_dqs_div => dqs_div_rst,
rst_dqs_div_in => rst_dqs_div_in,
rst_dqs_div_out => rst_dqs_div_out,
dqs_int_delay_in => dqs_int_delay_in,
ddr_dm => ddr2_dm,
dq => dq
);
 
end arc;
/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_parameters_0.vhd
0,0 → 1,94
--*****************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.6.1
-- \ \ Application : MIG
-- / / Filename : DDR2_Ram_Core_parameters_0.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
-- Device : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Purpose : This module has the parameters used in the design
--*****************************************************************************
 
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use UNISIM.VCOMPONENTS.all;
 
package DDR2_Ram_Core_parameters_0 is
 
-- The reset polarity is set to active low by default.
-- You can change this by editing the parameter RESET_ACTIVE_LOW.
-- Please do not change any of the other parameters directly by editing the RTL.
-- All other changes should be done through the GUI.
 
constant DATA_WIDTH : INTEGER := 16;
constant DATA_STROBE_WIDTH : INTEGER := 2;
constant DATA_MASK_WIDTH : INTEGER := 2;
constant CLK_WIDTH : INTEGER := 1;
constant CKE_WIDTH : INTEGER := 1;
constant ROW_ADDRESS : INTEGER := 13;
constant MEMORY_WIDTH : INTEGER := 8;
constant REGISTERED : INTEGER := 0;
constant DATABITSPERSTROBE : INTEGER := 8;
constant RESET_PORT : INTEGER := 0;
constant MASK_ENABLE : INTEGER := 1;
constant USE_DM_PORT : INTEGER := 1;
constant COLUMN_ADDRESS : INTEGER := 10;
constant BANK_ADDRESS : INTEGER := 2;
constant DEBUG_EN : INTEGER := 0;
constant CLK_TYPE : string := "SINGLE_ENDED";
constant LOAD_MODE_REGISTER : std_logic_vector(12 downto 0) := "0010100110010";
 
constant EXT_LOAD_MODE_REGISTER : std_logic_vector(12 downto 0) := "0000000000000";
 
constant RESET_ACTIVE_LOW : std_logic := '1';
constant RAS_COUNT_VALUE : std_logic_vector(4 downto 0) := "00101";
constant RP_COUNT_VALUE : std_logic_vector(2 downto 0) := "001";
constant RFC_COUNT_VALUE : std_logic_vector(7 downto 0) := "00001101";
constant TWR_COUNT_VALUE : std_logic_vector(2 downto 0) := "010";
constant MAX_REF_WIDTH : INTEGER := 10;
constant MAX_REF_CNT : std_logic_vector(9 downto 0) := "1111100111";
 
end DDR2_Ram_Core_parameters_0 ;
/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_data_read_0.vhd
0,0 → 1,247
--*****************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.6.1
-- \ \ Application : MIG
-- / / Filename : DDR2_Ram_Core_data_read_0.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
-- Device : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Purpose : ram8d modules are instantiated for Read data FIFOs. ram8d is
-- each 8 bits or 4 bits depending on number data bits per strobe.
-- Each strobe will have two instances, one for rising edge data
-- and one for falling edge data.
--*****************************************************************************
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use UNISIM.VCOMPONENTS.all;
use work.DDR2_Ram_Core_parameters_0.all;
 
entity DDR2_Ram_Core_data_read_0 is
port(
clk90 : in std_logic;
reset90 : in std_logic;
ddr_dq_in : in std_logic_vector((DATA_WIDTH-1) downto 0);
fifo_0_wr_en : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
fifo_1_wr_en : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
fifo_0_wr_addr : in std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
fifo_1_wr_addr : in std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
dqs_delayed_col0 : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
dqs_delayed_col1 : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
read_fifo_rden : in std_logic;
user_output_data : out std_logic_vector((2*DATA_WIDTH-1) downto 0);
u_data_val : out std_logic
);
end DDR2_Ram_Core_data_read_0;
 
architecture arc of DDR2_Ram_Core_data_read_0 is
 
component DDR2_Ram_Core_rd_gray_cntr
port (
clk90 : in std_logic;
reset90 : in std_logic;
cnt_en : in std_logic;
rgc_gcnt : out std_logic_vector(3 downto 0)
);
end component;
 
component DDR2_Ram_Core_ram8d_0 is
port (
DOUT : out std_logic_vector((DATABITSPERSTROBE -1) downto 0);
WADDR : in std_logic_vector(3 downto 0);
DIN : in std_logic_vector((DATABITSPERSTROBE -1) downto 0);
RADDR : in std_logic_vector(3 downto 0);
WCLK0 : in std_logic;
WCLK1 : in std_logic;
WE : in std_logic
);
end component;
 
signal fifo0_rd_addr : std_logic_vector(3 downto 0);
signal fifo1_rd_addr : std_logic_vector(3 downto 0);
 
signal first_sdr_data : std_logic_vector((2*DATA_WIDTH-1) downto 0);
signal reset90_r : std_logic;
signal fifo0_rd_addr_r : std_logic_vector((4*DATA_STROBE_WIDTH-1) downto 0);
signal fifo1_rd_addr_r : std_logic_vector((4*DATA_STROBE_WIDTH-1) downto 0);
signal fifo_0_data_out : std_logic_vector((DATA_WIDTH-1) downto 0);
signal fifo_1_data_out : std_logic_vector((DATA_WIDTH-1) downto 0);
signal fifo_0_data_out_r : std_logic_vector((DATA_WIDTH-1) downto 0);
signal fifo_1_data_out_r : std_logic_vector((DATA_WIDTH-1) downto 0);
signal dqs_delayed_col0_n : std_logic_vector((DATA_STROBE_WIDTH -1) downto 0);
signal dqs_delayed_col1_n : std_logic_vector((DATA_STROBE_WIDTH -1) downto 0);
 
signal read_fifo_rden_90r1 : std_logic;
signal read_fifo_rden_90r2 : std_logic;
signal read_fifo_rden_90r3 : std_logic;
signal read_fifo_rden_90r4 : std_logic;
signal read_fifo_rden_90r5 : std_logic;
signal read_fifo_rden_90r6 : std_logic;
 
attribute syn_preserve : boolean;
 
attribute syn_preserve of fifo0_rd_addr_r : signal is true;
attribute syn_preserve of fifo1_rd_addr_r : signal is true;
 
begin
 
process(clk90)
begin
if(clk90'event and clk90='1') then
reset90_r <= reset90;
end if;
end process;
 
gen_asgn : for asgn_i in 0 to DATA_STROBE_WIDTH-1 generate
dqs_delayed_col0_n(asgn_i) <= not dqs_delayed_col0(asgn_i);
dqs_delayed_col1_n(asgn_i) <= not dqs_delayed_col1(asgn_i);
end generate;
user_output_data <= first_sdr_data;
u_data_val <= read_fifo_rden_90r6;
 
-- Read fifo read enable signal phase is changed from 180 to 90 clock domain
 
process (clk90)
begin
if (rising_edge(clk90)) then
if reset90_r = '1' then
read_fifo_rden_90r1 <= '0';
read_fifo_rden_90r2 <= '0';
read_fifo_rden_90r3 <= '0';
read_fifo_rden_90r4 <= '0';
read_fifo_rden_90r5 <= '0';
read_fifo_rden_90r6<= '0';
else
read_fifo_rden_90r1 <= read_fifo_rden;
read_fifo_rden_90r2 <= read_fifo_rden_90r1;
read_fifo_rden_90r3 <= read_fifo_rden_90r2;
read_fifo_rden_90r4 <= read_fifo_rden_90r3;
read_fifo_rden_90r5 <= read_fifo_rden_90r4;
read_fifo_rden_90r6 <= read_fifo_rden_90r5;
end if;
end if;
end process;
 
 
process(clk90)
begin
if clk90'event and clk90 = '1' then
fifo_0_data_out_r <= fifo_0_data_out;
fifo_1_data_out_r <= fifo_1_data_out;
end if;
end process;
 
gen_addr : for addr_i in 0 to DATA_STROBE_WIDTH-1 generate
process(clk90)
begin
if clk90'event and clk90 = '1' then
fifo0_rd_addr_r((addr_i*4-1)+ 4 downto addr_i*4) <= fifo0_rd_addr;
fifo1_rd_addr_r((addr_i*4-1)+ 4 downto addr_i*4) <= fifo1_rd_addr;
end if;
end process;
end generate;
 
process(clk90)
begin
if clk90'event and clk90 = '1' then
if reset90_r = '1' then
first_sdr_data <= (others => '0');
elsif (read_fifo_rden_90r5 = '1') then
first_sdr_data <= (fifo_0_data_out_r & fifo_1_data_out_r);
else
first_sdr_data <= first_sdr_data;
end if;
end if;
end process;
 
------------------------------------------------------------------------------
-- fifo0_rd_addr and fifo1_rd_addr counters ( gray counters )
-------------------------------------------------------------------------------
 
fifo0_rd_addr_inst : DDR2_Ram_Core_rd_gray_cntr
port map (
clk90 => clk90,
reset90 => reset90,
cnt_en => read_fifo_rden_90r3,
rgc_gcnt => fifo0_rd_addr
);
fifo1_rd_addr_inst : DDR2_Ram_Core_rd_gray_cntr
port map (
clk90 => clk90,
reset90 => reset90,
cnt_en => read_fifo_rden_90r3,
rgc_gcnt => fifo1_rd_addr
);
 
-------------------------------------------------------------------------------
-- ram8d instantiations
-------------------------------------------------------------------------------
 
gen_strobe: for strobe_i in 0 to DATA_STROBE_WIDTH-1 generate
strobe : DDR2_Ram_Core_ram8d_0
Port Map (
dout => fifo_0_data_out((strobe_i*DATABITSPERSTROBE-1)+ DATABITSPERSTROBE downto strobe_i*DATABITSPERSTROBE),
waddr => fifo_0_wr_addr((strobe_i*4-1)+4 downto strobe_i*4),
din => ddr_dq_in((strobe_i*DATABITSPERSTROBE-1)+ DATABITSPERSTROBE downto strobe_i*DATABITSPERSTROBE),
raddr => fifo0_rd_addr_r((strobe_i*4-1)+4 downto strobe_i*4),
wclk0 => dqs_delayed_col0(strobe_i),
wclk1 => dqs_delayed_col1(strobe_i),
we => fifo_0_wr_en(strobe_i)
);
strobe_n : DDR2_Ram_Core_ram8d_0
Port Map (
dout => fifo_1_data_out((strobe_i*DATABITSPERSTROBE-1)+ DATABITSPERSTROBE downto strobe_i*DATABITSPERSTROBE),
waddr => fifo_1_wr_addr((strobe_i*4-1)+4 downto strobe_i*4),
din => ddr_dq_in((strobe_i*DATABITSPERSTROBE-1)+ DATABITSPERSTROBE downto strobe_i*DATABITSPERSTROBE),
raddr => fifo1_rd_addr_r((strobe_i*4-1)+4 downto strobe_i*4),
wclk0 => dqs_delayed_col0_n(strobe_i),
wclk1 => dqs_delayed_col1_n(strobe_i),
we => fifo_1_wr_en(strobe_i)
);
end generate;
 
end arc;
/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_dqs_delay_0.vhd
0,0 → 1,144
--*****************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.6.1
-- \ \ Application : MIG
-- / / Filename : DDR2_Ram_Core_dqs_delay_0.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
-- Device : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Purpose : This module generate the delay in the dqs signal.
--*****************************************************************************
 
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use UNISIM.VCOMPONENTS.all;
 
entity DDR2_Ram_Core_dqs_delay is
port (
clk_in : in std_logic;
sel_in : in std_logic_vector(4 downto 0);
clk_out : out std_logic
);
end DDR2_Ram_Core_dqs_delay;
 
architecture arc_dqs_delay of DDR2_Ram_Core_dqs_delay is
 
signal delay1 : std_logic;
signal delay2 : std_logic;
signal delay3 : std_logic;
signal delay4 : std_logic;
signal delay5 : std_logic;
signal high : std_logic;
 
attribute syn_preserve : boolean;
attribute syn_preserve of one : label is true;
attribute syn_preserve of two : label is true;
attribute syn_preserve of three : label is true;
attribute syn_preserve of four : label is true;
attribute syn_preserve of five : label is true;
attribute syn_preserve of six : label is true;
 
begin
 
high <= '1';
 
one : LUT4 generic map (INIT => x"f3c0")
port map (
I0 => high,
I1 => sel_in(4),
I2 => delay5,
I3 => clk_in,
O => clk_out
);
two : LUT4 generic map (INIT => x"ee22")
port map (
I0 => clk_in,
I1 => sel_in(2),
I2 => high,
I3 => delay3,
O => delay4
);
 
three : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => clk_in,
I1 => sel_in(0),
I2 => delay1,
I3 => high,
O => delay2
);
 
four : LUT4 generic map (INIT => x"ff00")
port map (
I0 => high,
I1 => high,
I2 => high,
I3 => clk_in,
O => delay1
);
 
five : LUT4 generic map (INIT => x"f3c0")
port map (
I0 => high,
I1 => sel_in(3),
I2 => delay4,
I3 => clk_in,
O => delay5
);
 
six : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => clk_in,
I1 => sel_in(1),
I2 => delay2,
I3 => high,
O => delay3
);
 
end arc_dqs_delay;
/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_s3_dqs_iob.vhd
0,0 → 1,148
--*****************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.6.1
-- \ \ Application : MIG
-- / / Filename : DDR2_Ram_Core_s3_dqs_iob.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
-- Device : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Purpose : This module instantiates DDR IOB output flip-flops, an
-- output buffer with registered tri-state, and an input buffer
-- for a single strobe/dqs bit. The DDR IOB output flip-flops
-- are used to forward strobe to memory during a write. During
-- a read, the output of the IBUF is routed to the internal
-- delay module, dqs_delay.
--*****************************************************************************
 
library ieee;
use ieee.std_logic_1164.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
 
entity DDR2_Ram_Core_s3_dqs_iob is
port(
clk : in std_logic;
ddr_dqs_reset : in std_logic;
ddr_dqs_enable : in std_logic;
ddr_dqs : inout std_logic;
ddr_dqs_n : inout std_logic;
dqs : out std_logic);
end DDR2_Ram_Core_s3_dqs_iob;
 
architecture arc of DDR2_Ram_Core_s3_dqs_iob is
 
 
signal dqs_q : std_logic;
signal ddr_dqs_enable1 : std_logic;
signal vcc : std_logic;
signal gnd : std_logic;
signal ddr_dqs_enable_b : std_logic;
signal data1 : std_logic;
signal clk180 : std_logic;
 
attribute IOB : string;
attribute syn_useioff : boolean;
attribute IOB of U1 : label is "FORCE";
attribute syn_useioff of U1 : label is true;
 
begin
 
--******************************************************************************
-- Output DDR generation. This includes instantiation of the output DDR flip flop.
-- Additionally, to keep synthesis tools from register sharing, manually
-- instantiate the output tri-state flip-flop.
--******************************************************************************
vcc <= '1';
gnd <= '0';
clk180 <= not clk;
ddr_dqs_enable_b <= not ddr_dqs_enable;
data1 <= '0' when ddr_dqs_reset = '1' else
'1';
 
U1 : FD
port map (
D => ddr_dqs_enable_b,
Q => ddr_dqs_enable1,
C => clk
);
 
 
U2 : FDDRRSE
port map (
Q => dqs_q,
C0 => clk,
C1 => clk180,
CE => vcc,
D0 => data1,
D1 => gnd,
R => gnd,
S => gnd
);
 
 
 
--***********************************************************************
-- IO buffer for dqs signal. Allows for distribution of dqs
-- to the data (DQ) loads.
--***********************************************************************
 
 
U3 : OBUFTDS port map (
I => dqs_q,
T => ddr_dqs_enable1,
O => ddr_dqs,
OB => ddr_dqs_n
);
 
U4 : IBUFDS port map(
I => ddr_dqs,
IB => ddr_dqs_n,
O => dqs
);
 
 
 
end arc;
/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_data_read_controller_0.vhd
0,0 → 1,274
--*****************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.6.1
-- \ \ Application : MIG
-- / / Filename : DDR2_Ram_Core_data_read_controller_0.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
-- Device : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Description : This module has instantiations fifo_0_wr_en, fifo_1_wr_en,
-- dqs_delay and wr_gray_cntr.
--*****************************************************************************
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use UNISIM.VCOMPONENTS.all;
use work.DDR2_Ram_Core_parameters_0.all;
 
entity DDR2_Ram_Core_data_read_controller_0 is
port(
clk : in std_logic;
reset : in std_logic;
rst_dqs_div_in : in std_logic;
delay_sel : in std_logic_vector(4 downto 0);
dqs_int_delay_in : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
fifo_0_wr_en_val : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
fifo_1_wr_en_val : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
fifo_0_wr_addr_val : out std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
fifo_1_wr_addr_val : out std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
dqs_delayed_col0_val : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
dqs_delayed_col1_val : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
-- debug signals
vio_out_dqs : in std_logic_vector(4 downto 0);
vio_out_dqs_en : in std_logic;
vio_out_rst_dqs_div : in std_logic_vector(4 downto 0);
vio_out_rst_dqs_div_en: in std_logic
);
 
end DDR2_Ram_Core_data_read_controller_0;
 
architecture arc of DDR2_Ram_Core_data_read_controller_0 is
 
component DDR2_Ram_Core_dqs_delay
port (
clk_in : in std_logic;
sel_in : in std_logic_vector(4 downto 0);
clk_out : out std_logic
);
end component;
 
-- wr_gray_cntr is a gray counter with an ASYNC reset for fifo wr_addr
component DDR2_Ram_Core_wr_gray_cntr
port (
clk : in std_logic;
reset : in std_logic;
cnt_en : in std_logic;
wgc_gcnt : out std_logic_vector(3 downto 0)
);
end component;
 
-- fifo_wr_en module generates fifo write enable signal
-- enable is derived from rst_dqs_div signal
component DDR2_Ram_Core_fifo_0_wr_en_0
port (
clk : in std_logic;
reset : in std_logic;
din : in std_logic;
rst_dqs_delay_n : out std_logic;
dout : out std_logic
);
end component;
component DDR2_Ram_Core_fifo_1_wr_en_0
port (
clk : in std_logic;
rst_dqs_delay_n : in std_logic;
reset : in std_logic;
din : in std_logic;
dout : out std_logic
);
end component;
 
 
signal dqs_delayed_col0 : std_logic_vector((data_strobe_width-1) downto 0);
signal dqs_delayed_col1 : std_logic_vector((data_strobe_width-1) downto 0);
signal fifo_0_wr_addr : std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
signal fifo_1_wr_addr : std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
 
-- FIFO WRITE ENABLE SIGNALS
signal fifo_0_wr_en : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
signal fifo_1_wr_en : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
 
signal rst_dqs_div : std_logic;
signal reset_r : std_logic;
signal rst_dqs_delay_0_n : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
signal dqs_delayed_col0_n : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
signal dqs_delayed_col1_n : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
signal delay_sel_rst_dqs_div : std_logic_vector(4 downto 0);
signal delay_sel_dqs : std_logic_vector(4 downto 0);
 
attribute syn_preserve : boolean;
attribute buffer_type : string;
attribute buffer_type of dqs_delayed_col0: signal is "none";
attribute buffer_type of dqs_delayed_col1: signal is "none";
 
begin
 
process(clk)
begin
if(clk'event and clk = '1') then
reset_r <= reset;
end if;
end process;
 
 
fifo_0_wr_addr_val <= fifo_0_wr_addr;
fifo_1_wr_addr_val <= fifo_1_wr_addr;
fifo_0_wr_en_val <= fifo_0_wr_en;
fifo_1_wr_en_val <= fifo_1_wr_en;
dqs_delayed_col0_val <= dqs_delayed_col0 ;
dqs_delayed_col1_val <= dqs_delayed_col1 ;
 
gen_asgn : for asgn_i in 0 to DATA_STROBE_WIDTH-1 generate
dqs_delayed_col0_n(asgn_i) <= not dqs_delayed_col0(asgn_i);
dqs_delayed_col1_n(asgn_i) <= not dqs_delayed_col1(asgn_i);
end generate;
 
 
debug_rst_dqs_div_ena : if (DEBUG_EN = 1) generate
delay_sel_rst_dqs_div <= vio_out_rst_dqs_div(4 downto 0) when (vio_out_rst_dqs_div_en = '1')
else delay_sel;
end generate;
 
debug_rst_dqs_div_dis : if (DEBUG_EN = 0) generate
delay_sel_rst_dqs_div <= delay_sel;
end generate;
 
 
-- delayed rst_dqs_div logic
 
rst_dqs_div_delayed : DDR2_Ram_Core_dqs_delay
port map (
clk_in => rst_dqs_div_in,
sel_in => delay_sel_rst_dqs_div,
clk_out => rst_dqs_div
);
 
 
debug_ena : if (DEBUG_EN = 1) generate
delay_sel_dqs <= vio_out_dqs(4 downto 0) when (vio_out_dqs_en = '1')
else delay_sel;
end generate;
 
debug_dis : if (DEBUG_EN = 0) generate
delay_sel_dqs <= delay_sel;
end generate;
 
 
--******************************************************************************
-- DQS Internal Delay Circuit implemented in LUTs
--******************************************************************************
gen_delay: for dly_i in 0 to DATA_STROBE_WIDTH-1 generate
attribute syn_preserve of dqs_delay_col0: label is true;
attribute syn_preserve of dqs_delay_col1: label is true;
begin
-- Internal Clock Delay circuit placed in the first
-- column (for falling edge data) adjacent to IOBs
dqs_delay_col0 : DDR2_Ram_Core_dqs_delay
port map (
clk_in => dqs_int_delay_in(dly_i),
sel_in => delay_sel_dqs,
clk_out => dqs_delayed_col0(dly_i)
);
-- Internal Clock Delay circuit placed in the second
--column (for rising edge data) adjacent to IOBs
dqs_delay_col1 : DDR2_Ram_Core_dqs_delay
port map (
clk_in => dqs_int_delay_in(dly_i),
sel_in => delay_sel_dqs,
clk_out => dqs_delayed_col1(dly_i)
);
end generate;
 
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
 
gen_wr_en: for wr_en_i in 0 to DATA_STROBE_WIDTH-1 generate
fifo_0_wr_en_inst: DDR2_Ram_Core_fifo_0_wr_en_0
port map (
clk => dqs_delayed_col1_n (wr_en_i),
reset => reset_r,
din => rst_dqs_div,
rst_dqs_delay_n => rst_dqs_delay_0_n(wr_en_i),
dout => fifo_0_wr_en(wr_en_i)
);
fifo_1_wr_en_inst: DDR2_Ram_Core_fifo_1_wr_en_0
port map (
clk => dqs_delayed_col0(wr_en_i),
rst_dqs_delay_n => rst_dqs_delay_0_n(wr_en_i),
reset => reset_r,
din => rst_dqs_div,
dout => fifo_1_wr_en(wr_en_i)
);
end generate;
 
-------------------------------------------------------------------------------
-- write pointer gray counter instances
-------------------------------------------------------------------------------
 
gen_wr_addr: for wr_addr_i in 0 to DATA_STROBE_WIDTH-1 generate
fifo_0_wr_addr_inst : DDR2_Ram_Core_wr_gray_cntr
port map (
clk => dqs_delayed_col1(wr_addr_i),
reset => reset_r,
cnt_en => fifo_0_wr_en(wr_addr_i),
wgc_gcnt => fifo_0_wr_addr((wr_addr_i*4-1)+4 downto wr_addr_i*4)
);
fifo_1_wr_addr_inst : DDR2_Ram_Core_wr_gray_cntr
port map (
clk => dqs_delayed_col0_n(wr_addr_i),
reset => reset_r,
cnt_en => fifo_1_wr_en(wr_addr_i),
wgc_gcnt => fifo_1_wr_addr((wr_addr_i*4-1)+4 downto wr_addr_i*4)
);
end generate;
 
end arc;
/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_ram8d_0.vhd
0,0 → 1,215
--*****************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.6.1
-- \ \ Application : MIG
-- / / Filename : DDR2_Ram_Core_ram8d_0.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
-- Device : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Purpose : This module instantiates RAM16X1 premitives. There will be 8 or 4 RAM16X1
-- instances depending on the number of data bits per strobe.
--*****************************************************************************
 
library IEEE;
library UNISIM;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use UNISIM.VCOMPONENTS.all;
use work.DDR2_Ram_Core_parameters_0.all;
 
entity DDR2_Ram_Core_ram8d_0 is
port (
dout : out std_logic_vector((DATABITSPERSTROBE -1) downto 0);
waddr : in std_logic_vector(3 downto 0);
din : in std_logic_vector((DATABITSPERSTROBE -1) downto 0);
raddr : in std_logic_vector(3 downto 0);
wclk0 : in std_logic;
wclk1 : in std_logic;
we : in std_logic
);
end DDR2_Ram_Core_ram8d_0;
 
architecture arc of DDR2_Ram_Core_ram8d_0 is
 
begin
 
fifo_bit0 : RAM16X1D
port map (
DPO => dout(0),
A0 => waddr(0),
A1 => waddr(1),
A2 => waddr(2),
A3 => waddr(3),
D => din(0),
DPRA0 => raddr(0),
DPRA1 => raddr(1),
DPRA2 => raddr(2),
DPRA3 => raddr(3),
WCLK => wclk1,
SPO => OPEN,
WE => we
);
 
fifo_bit1 : RAM16X1D
port map (
DPO => dout(1),
A0 => waddr(0),
A1 => waddr(1),
A2 => waddr(2),
A3 => waddr(3),
D => din(1),
DPRA0 => raddr(0),
DPRA1 => raddr(1),
DPRA2 => raddr(2),
DPRA3 => raddr(3),
WCLK => wclk0,
SPO => OPEN,
WE => we
);
 
fifo_bit2 : RAM16X1D
port map (
DPO => dout(2),
A0 => waddr(0),
A1 => waddr(1),
A2 => waddr(2),
A3 => waddr(3),
D => din(2),
DPRA0 => raddr(0),
DPRA1 => raddr(1),
DPRA2 => raddr(2),
DPRA3 => raddr(3),
WCLK => wclk1,
SPO => OPEN,
WE => we
);
 
fifo_bit3 : RAM16X1D
port map (
DPO => dout(3),
A0 => waddr(0),
A1 => waddr(1),
A2 => waddr(2),
A3 => waddr(3),
D => din(3),
DPRA0 => raddr(0),
DPRA1 => raddr(1),
DPRA2 => raddr(2),
DPRA3 => raddr(3),
WCLK => wclk0,
SPO => OPEN,
WE => we
);
 
fifo_bit4 : RAM16X1D
port map (
DPO => dout(4),
A0 => waddr(0),
A1 => waddr(1),
A2 => waddr(2),
A3 => waddr(3),
D => din(4),
DPRA0 => raddr(0),
DPRA1 => raddr(1),
DPRA2 => raddr(2),
DPRA3 => raddr(3),
WCLK => wclk1,
SPO => OPEN,
WE => we
);
 
fifo_bit5 : RAM16X1D
port map (
DPO => dout(5),
A0 => waddr(0),
A1 => waddr(1),
A2 => waddr(2),
A3 => waddr(3),
D => din(5),
DPRA0 => raddr(0),
DPRA1 => raddr(1),
DPRA2 => raddr(2),
DPRA3 => raddr(3),
WCLK => wclk0,
SPO => OPEN,
WE => we
);
 
fifo_bit6 : RAM16X1D
port map (
DPO => dout(6),
A0 => waddr(0),
A1 => waddr(1),
A2 => waddr(2),
A3 => waddr(3),
D => din(6),
DPRA0 => raddr(0),
DPRA1 => raddr(1),
DPRA2 => raddr(2),
DPRA3 => raddr(3),
WCLK => wclk1,
SPO => OPEN,
WE => we
);
 
fifo_bit7 : RAM16X1D
port map (
DPO => dout(7),
A0 => waddr(0),
A1 => waddr(1),
A2 => waddr(2),
A3 => waddr(3),
D => din(7),
DPRA0 => raddr(0),
DPRA1 => raddr(1),
DPRA2 => raddr(2),
DPRA3 => raddr(3),
WCLK => wclk0,
SPO => OPEN,
WE => we
);
 
end arc;
/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_tap_dly.vhd
0,0 → 1,386
--*****************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.6.1
-- \ \ Application : MIG
-- / / Filename : DDR2_Ram_Core_tap_dly.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
-- Device : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Purpose :This module generates a 32 bit tap delay register used by the
-- cal_ctl module to find out the phase transitions.
--*****************************************************************************
 
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use UNISIM.VCOMPONENTS.all;
 
 
entity DDR2_Ram_Core_tap_dly is
port (
clk : in std_logic;
reset : in std_logic;
tapin : in std_logic;
flop2 : out std_logic_vector(31 downto 0)
);
end DDR2_Ram_Core_tap_dly;
 
architecture arc_tap_dly of DDR2_Ram_Core_tap_dly is
 
signal tap : std_logic_vector(31 downto 0);
signal flop1 : std_logic_vector(31 downto 0);
signal high : std_logic;
signal low : std_logic;
signal flop2_xnor : std_logic_vector(30 downto 0);
signal reset_r : std_logic;
 
attribute syn_preserve : boolean;
 
attribute syn_preserve of tap : signal is true;
attribute syn_preserve of flop1 : signal is true;
 
 
begin
 
process(clk)
begin
if(clk'event and clk='1') then
reset_r <= reset;
end if;
end process;
 
high <= '1';
low <= '0';
 
l0 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tapin,
I2 => low,
I3 => high,
O => tap(0)
);
 
l1 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(0),
I2 => low,
I3 => high,
O => tap(1)
);
l2 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(1),
I2 => low,
I3 => high,
O => tap(2)
);
l3 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(2),
I2 => low,
I3 => high,
O => tap(3)
);
l4 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(3),
I2 => low,
I3 => high,
O => tap(4)
);
l5 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(4),
I2 => low,
I3 => high,
O => tap(5)
);
l6 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(5),
I2 => low,
I3 => high,
O => tap(6)
);
l7 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(6),
I2 => low,
I3 => high,
O => tap(7)
);
l8 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(7),
I2 => low,
I3 => high,
O => tap(8)
);
l9 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(8),
I2 => low,
I3 => high,
O => tap(9)
);
l10 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(9),
I2 => low,
I3 => high,
O => tap(10)
);
l11 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(10),
I2 => low,
I3 => high,
O => tap(11)
);
l12 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(11),
I2 => low,
I3 => high,
O => tap(12)
);
l13 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(12),
I2 => low,
I3 => high,
O => tap(13)
);
l14 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(13),
I2 => low,
I3 => high,
O => tap(14)
);
l15 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(14),
I2 => low,
I3 => high,
O => tap(15)
);
l16 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(15),
I2 => low,
I3 => high,
O => tap(16)
);
l17 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(16),
I2 => low,
I3 => high,
O => tap(17)
);
l18 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(17),
I2 => low,
I3 => high,
O => tap(18)
);
l19 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(18),
I2 => low,
I3 => high,
O => tap(19)
);
l20 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(19),
I2 => low,
I3 => high,
O => tap(20)
);
l21 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(20),
I2 => low,
I3 => high,
O => tap(21)
);
l22 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(21),
I2 => low,
I3 => high,
O => tap(22)
);
l23 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(22),
I2 => low,
I3 => high,
O => tap(23)
);
l24 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(23),
I2 => low,
I3 => high,
O => tap(24)
);
l25 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(24),
I2 => low,
I3 => high,
O => tap(25)
);
l26 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(25),
I2 => low,
I3 => high,
O => tap(26)
);
l27 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(26),
I2 => low,
I3 => high,
O => tap(27)
);
l28 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(27),
I2 => low,
I3 => high,
O => tap(28)
);
l29 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(28),
I2 => low,
I3 => high,
O => tap(29)
);
l30 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(29),
I2 => low,
I3 => high,
O => tap(30)
);
l31 : LUT4 generic map (INIT => x"e2e2")
port map (
I0 => high,
I1 => tap(30),
I2 => low,
I3 => high,
O => tap(31)
);
 
gen_tap1 : for tap1_i in 0 to 31 generate
r : FDR port map (
Q => flop1(tap1_i),
C => clk,
D => tap(tap1_i),
R => reset_r
);
end generate;
gen_asgn : for asgn_i in 0 to 30 generate
flop2_xnor(asgn_i) <= flop1(asgn_i) xnor flop1(asgn_i+1);
end generate;
 
gen_tap2 : for tap2_i in 0 to 30 generate
u : FDR port map (
Q => flop2(tap2_i),
C => clk,
D => flop2_xnor(tap2_i),
R => reset_r
);
end generate;
u31 : FDR
port map (
Q => flop2(31),
C => clk,
D => flop1(31),
R => reset_r
);
end arc_tap_dly;
/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_clk_dcm.vhd
0,0 → 1,127
--*****************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.6.1
-- \ \ Application : MIG
-- / / Filename : DDR2_Ram_Core_clk_dcm.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
--
-- Device : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Purpose : This module generates the system clock for controller block
-- This also generates the recapture clock, clock for the
-- Refresh counter and also for the data path
--*****************************************************************************
 
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use UNISIM.VCOMPONENTS.all;
entity DDR2_Ram_Core_clk_dcm is
port(
input_clk : in std_logic;
rst : in std_logic;
clk : out std_logic;
clk90 : out std_logic;
dcm_lock : out std_logic
);
end DDR2_Ram_Core_clk_dcm;
 
architecture arc of DDR2_Ram_Core_clk_dcm is
 
signal clk0dcm : std_logic;
signal clk90dcm : std_logic;
signal clk0_buf : std_logic;
signal clk90_buf : std_logic;
signal gnd : std_logic;
signal dcm1_lock : std_logic;
 
begin
 
gnd <= '0';
clk <= clk0_buf;
clk90 <= clk90_buf;
 
DCM_INST1 : DCM
generic map(
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => true
)
port map (
CLKIN => input_clk,
CLKFB => clk0_buf,
DSSEN => gnd,
PSINCDEC => gnd,
PSEN => gnd,
PSCLK => gnd,
RST => rst,
CLK0 => clk0dcm,
CLK90 => clk90dcm,
CLK180 => open,
CLK270 => open,
CLK2X => open,
CLK2X180 => open,
CLKDV => open,
CLKFX => open,
CLKFX180 => open,
LOCKED => dcm1_lock,
PSDONE => open,
STATUS => open
);
 
BUFG_CLK0 : BUFG
port map (
O => clk0_buf,
I => clk0dcm
);
 
BUFG_CLK90 : BUFG
port map (
O => clk90_buf,
I => clk90dcm
);
 
dcm_lock <= dcm1_lock;
 
end arc;
/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_s3_dm_iob.vhd
0,0 → 1,106
--*****************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.6.1
-- \ \ Application : MIG
-- / / Filename : DDR2_Ram_Core_s3_dm_iob.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
-- Device : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Purpose : This module instantiates DDR IOB output flip-flops, and an
-- output buffer for the data mask bits.
--*****************************************************************************
 
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use UNISIM.VCOMPONENTS.all;
 
entity DDR2_Ram_Core_s3_dm_iob is
port (
ddr_dm : out std_logic; --Data mask output
mask_falling : in std_logic; --Mask output on falling edge
mask_rising : in std_logic; --Mask output on rising edge
clk90 : in std_logic
);
end DDR2_Ram_Core_s3_dm_iob;
 
architecture arc of DDR2_Ram_Core_s3_dm_iob is
 
--***********************************************************************\
-- Internal signal declaration
--***********************************************************************/
 
signal mask_o : std_logic;
signal gnd : std_logic;
signal vcc : std_logic;
signal clk270 : std_logic;
begin
 
gnd <= '0';
vcc <= '1';
clk270 <= not clk90;
 
-- Data Mask Output during a write command
 
DDR_DM0_OUT : FDDRRSE
port map (
Q => mask_o,
C0 => clk270,
C1 => clk90,
CE => vcc,
D0 => mask_rising,
D1 => mask_falling,
R => gnd,
S => gnd
);
 
DM1_OBUF : OBUF
port map (
I => mask_o,
O => ddr_dm
);
end arc;
/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_wr_gray_cntr.vhd
0,0 → 1,139
--*****************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.6.1
-- \ \ Application : MIG
-- / / Filename : DDR2_Ram_Core_wr_gray_cntr.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
-- Device : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Purpose :
--*****************************************************************************
-- fifo_wr_addr gray counter with synchronous reset
-- Gray counter is used for FIFO address counter
 
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use UNISIM.VCOMPONENTS.all;
 
entity DDR2_Ram_Core_wr_gray_cntr is
port (
clk : in std_logic;
reset : in std_logic;
cnt_en : in std_logic;
wgc_gcnt : out std_logic_vector(3 downto 0)
);
end DDR2_Ram_Core_wr_gray_cntr;
 
architecture arc of DDR2_Ram_Core_wr_gray_cntr is
 
signal d_in : std_logic_vector(3 downto 0);
signal gc_int : std_logic_vector(3 downto 0);
 
begin
 
wgc_gcnt <= gc_int(3 downto 0);
 
process(gc_int)
begin
case gc_int is
when "0000" => d_in <= "0001"; --0 > 1
when "0001" => d_in <= "0011"; --1 > 3
when "0010" => d_in <= "0110"; --2 > 6
when "0011" => d_in <= "0010"; --3 > 2
when "0100" => d_in <= "1100"; --4 > c
when "0101" => d_in <= "0100"; --5 > 4
when "0110" => d_in <= "0111"; --6 > 7
when "0111" => d_in <= "0101"; --7 > 5
when "1000" => d_in <= "0000"; --8 > 0
when "1001" => d_in <= "1000"; --9 > 8
when "1010" => d_in <= "1011"; --a > b
when "1011" => d_in <= "1001"; --b > 9
when "1100" => d_in <= "1101"; --c > d
when "1101" => d_in <= "1111"; --d > f
when "1110" => d_in <= "1010"; --e > a
when "1111" => d_in <= "1110"; --f > e
when others => d_in <= "0001"; --0 > 1
end case;
end process;
 
bit0 : FDCE
port map (
Q => gc_int(0),
C => clk,
CE => cnt_en,
CLR => reset,
D => d_in(0)
);
 
bit1 : FDCE
port map (
Q => gc_int(1),
C => clk,
CE => cnt_en,
CLR => reset,
D => d_in(1)
);
bit2 : FDCE
port map (
Q => gc_int(2),
C => clk,
CE => cnt_en,
CLR => reset,
D => d_in(2)
);
 
bit3 : FDCE
port map (
Q => gc_int(3),
C => clk,
CE => cnt_en,
CLR => reset,
D => d_in(3)
);
 
end arc;
/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_cal_ctl.vhd
0,0 → 1,255
--*****************************************************************************
-- (c) Copyright 2005 - 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.6.1
-- \ \ Application : MIG
-- / / Filename : DDR2_Ram_Core_cal_ctl.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
-- Device : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Purpose : This module generates the select lines for the LUT delay
-- circuit that generate the required delay for the DQS with
-- respect to the DQ. It calculates the dealy of a LUT dynalically
-- by finding the number of LUTs in a clock phase.
--*****************************************************************************
 
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use UNISIM.VCOMPONENTS.all;
 
entity DDR2_Ram_Core_cal_ctl is
port (
clk : in std_logic;
reset : in std_logic;
flop2 : in std_logic_vector(31 downto 0);
tapfordqs : out std_logic_vector(4 downto 0);
-- debug signals
dbg_phase_cnt : out std_logic_vector(4 downto 0);
dbg_cnt : out std_logic_vector(5 downto 0);
dbg_trans_onedtct : out std_logic;
dbg_trans_twodtct : out std_logic;
dbg_enb_trans_two_dtct : out std_logic
);
end DDR2_Ram_Core_cal_ctl;
 
architecture arc_cal_ctl of DDR2_Ram_Core_cal_ctl is
 
signal cnt : std_logic_vector(5 downto 0);
signal cnt1 : std_logic_vector(5 downto 0);
signal trans_onedtct : std_logic;
signal trans_twodtct : std_logic;
signal phase_cnt : std_logic_vector(4 downto 0);
signal tap_dly_reg : std_logic_vector(31 downto 0);
signal enb_trans_two_dtct : std_logic;
signal tapfordqs_val : std_logic_vector(4 downto 0);
signal cnt_val : integer;
signal reset_r : std_logic;
 
constant tap1 : std_logic_vector(4 downto 0) := "01111";
constant tap2 : std_logic_vector(4 downto 0) := "10111";
constant tap3 : std_logic_vector(4 downto 0) := "11011";
constant tap4 : std_logic_vector(4 downto 0) := "11101";
constant tap5 : std_logic_vector(4 downto 0) := "11110";
constant tap6 : std_logic_vector(4 downto 0) := "11111";
constant default_tap : std_logic_vector(4 downto 0) := "11101";
 
attribute syn_keep : boolean;
attribute syn_keep of cnt : signal is true;
attribute syn_keep of cnt1 : signal is true;
attribute syn_keep of trans_onedtct : signal is true;
attribute syn_keep of trans_twodtct : signal is true;
attribute syn_keep of tap_dly_reg : signal is true;
attribute syn_keep of enb_trans_two_dtct : signal is true;
attribute syn_keep of phase_cnt : signal is true;
attribute syn_keep of tapfordqs_val : signal is true;
 
begin
 
dbg_phase_cnt <= phase_cnt;
dbg_cnt <= cnt1;
dbg_trans_onedtct <= trans_onedtct;
dbg_trans_twodtct <= trans_twodtct;
dbg_enb_trans_two_dtct <= enb_trans_two_dtct;
 
process(clk)
begin
if(clk'event and clk = '1') then
reset_r <= reset;
end if;
end process;
 
process(clk)
begin
if(clk'event and clk = '1') then
tapfordqs <= tapfordqs_val;
end if;
end process;
 
-----------For Successive Transition-------------------
 
process(clk)
begin
if (clk'event and clk = '1') then
if(reset_r = '1') then
enb_trans_two_dtct <= '0';
elsif(phase_cnt >= "00001") then
enb_trans_two_dtct <= '1';
else
enb_trans_two_dtct <= '0';
end if;
end if;
end process;
 
process (clk)
begin
if(clk'event and clk = '1') then
if(reset_r = '1') then
tap_dly_reg <= "00000000000000000000000000000000";
elsif(cnt(5) = '1') then
tap_dly_reg <= flop2;
else
tap_dly_reg <= tap_dly_reg;
end if;
end if;
end process;
 
--------Free Running Counter For Counting 32 States ----------------------
------- Two parallel counters are used to fix the timing ------------------
 
process (clk)
begin
if(clk'event and clk = '1') then
if(reset_r = '1' or cnt(5) = '1') then
cnt(5 downto 0) <= "000000";
else
cnt(5 downto 0) <= cnt(5 downto 0) + "000001";
end if;
end if;
end process;
 
 
process(clk)
begin
if(clk'event and clk = '1') then
if(reset_r = '1' or cnt1(5) = '1') then
cnt1(5 downto 0) <= "000000";
else
cnt1(5 downto 0) <= cnt1(5 downto 0) + "000001";
end if;
end if;
end process;
 
process(clk)
begin
if clk'event and clk = '1' then
if(reset_r = '1' or cnt(5) = '1') then
phase_cnt <= "00000";
elsif (trans_onedtct = '1' and trans_twodtct = '0') then
phase_cnt <= phase_cnt + "00001";
else
phase_cnt <= phase_cnt;
end if;
end if;
end process;
 
----------- Checking For The First Transition ------------------
 
process (clk)
begin
if clk'event and clk = '1' then
if (reset_r = '1' or cnt(5) = '1') then
trans_onedtct <= '0';
trans_twodtct <= '0';
elsif (cnt(4 downto 0) = "00000" and tap_dly_reg(0) = '1') then
trans_onedtct <= '1';
trans_twodtct <= '0';
elsif (tap_dly_reg(cnt_val) = '1' and trans_twodtct = '0') then
if(trans_onedtct = '1' and enb_trans_two_dtct = '1') then
trans_twodtct <= '1';
else
trans_onedtct <= '1';
end if;
end if;
end if;
end process;
 
cnt_val <= conv_integer(cnt(4 downto 0));
 
-- Tap values for Left/Right banks
process (clk)
begin
if clk'event and clk = '1' then
if(reset_r = '1') then
tapfordqs_val <= default_tap;
elsif(cnt1(4) = '1' and cnt1(3) = '1' and cnt1(2) = '1' and cnt1(1) = '1'
and cnt1(0) = '1') then
if ((trans_onedtct = '0') or (trans_twodtct = '0')
or (phase_cnt > "01100")) then
tapfordqs_val <= tap6;
elsif (phase_cnt > "01001") then
tapfordqs_val <= tap4;
elsif (phase_cnt > "00111") then
tapfordqs_val <= tap3;
elsif (phase_cnt > "00100") then
tapfordqs_val <= tap2;
else
tapfordqs_val <= tap1;
end if;
else
tapfordqs_val <= tapfordqs_val;
end if;
end if;
end process;
 
end arc_cal_ctl;
/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_s3_dq_iob.vhd
0,0 → 1,135
--*****************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.6.1
-- \ \ Application : MIG
-- / / Filename : DDR2_Ram_Core_s3_dq_iob.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
-- Device : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Purpose : This module instantiate DDR IOB output flip-flops, an
-- output buffer with registered tri-state, and an input buffer
-- for a single data/dq bit. The DDR IOB output flip-flops
-- are used to forward data to memory during a write.
--*****************************************************************************
 
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use UNISIM.VCOMPONENTS.all;
 
entity DDR2_Ram_Core_s3_dq_iob is
port (
ddr_dq_inout : inout std_logic; --Bi-directional SDRAM data bus
write_data_falling : in std_logic; --Transmit data, output on falling edge
write_data_rising : in std_logic; --Transmit data, output on rising edge
read_data_in : out std_logic; -- Received data
clk90 : in std_logic; --Clock 90
write_en_val : in std_logic
);
end DDR2_Ram_Core_s3_dq_iob;
 
architecture arc of DDR2_Ram_Core_s3_dq_iob is
 
--***********************************************************************\
-- Internal signal declaration
--***********************************************************************/
signal ddr_en : std_logic; -- Tri-state enable signal
signal ddr_dq_q : std_logic; -- Data output intermediate signal
signal gnd : std_logic;
signal clock_en : std_logic;
signal enable_b : std_logic;
signal clk270 : std_logic;
 
attribute iob : string;
attribute syn_useioff : boolean;
 
attribute iob of DQ_T : label is "FORCE";
attribute syn_useioff of DQ_T : label is true;
 
begin
clk270 <= not clk90;
gnd <= '0';
enable_b <= not write_en_val;
clock_en <= '1';
 
-- Transmission data path
 
DDR_OUT : FDDRRSE
port map (
Q => ddr_dq_q,
C0 => clk270,
C1 => clk90,
CE => clock_en,
D0 => write_data_rising,
D1 => write_data_falling,
R => gnd,
S => gnd
);
 
DQ_T : FD
port map (
D => enable_b,
C => clk270,
Q => ddr_en
);
 
DQ_OBUFT : OBUFT
port map (
I => ddr_dq_q,
T => ddr_en,
O => ddr_dq_inout
);
 
-- Receive data path
 
DQ_IBUF : IBUF
port map(
I => ddr_dq_inout,
O => read_data_in
);
 
end arc;
/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_data_write_0.vhd
0,0 → 1,196
--*****************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.6.1
-- \ \ Application : MIG
-- / / Filename : DDR2_Ram_Core_data_write0.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
-- Device : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Purpose : Data write operation performed through the pipelines in this
-- module.
--*****************************************************************************
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
use work.DDR2_Ram_Core_parameters_0.all;
 
entity DDR2_Ram_Core_data_write_0 is
port(
user_input_data : in std_logic_vector((2*DATA_WIDTH-1) downto 0);
user_data_mask : in std_logic_vector((2*DATA_MASK_WIDTH-1) downto 0);
clk90 : in std_logic;
write_enable : in std_logic;
write_en_val : out std_logic;
data_mask_f : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
data_mask_r : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
write_data_falling : out std_logic_vector((DATA_WIDTH-1) downto 0);
write_data_rising : out std_logic_vector((DATA_WIDTH-1) downto 0)
);
end DDR2_Ram_Core_data_write_0;
 
architecture arc of DDR2_Ram_Core_data_write_0 is
 
 
signal write_en_P1 : std_logic; -- write enable Pipeline stage
signal write_data0 : std_logic_vector((2*DATA_WIDTH-1) downto 0);
signal write_data1 : std_logic_vector((2*DATA_WIDTH-1) downto 0);
signal write_data2 : std_logic_vector((2*DATA_WIDTH-1) downto 0);
signal write_data3 : std_logic_vector((2*DATA_WIDTH-1) downto 0);
signal write_data4 : std_logic_vector((2*DATA_WIDTH-1) downto 0);
signal write_data_m0 : std_logic_vector ((2*DATA_MASK_WIDTH-1) downto 0);
signal write_data_m1 : std_logic_vector ((2*DATA_MASK_WIDTH-1) downto 0);
signal write_data_m2 : std_logic_vector ((2*DATA_MASK_WIDTH-1) downto 0);
signal write_data_m3 : std_logic_vector ((2*DATA_MASK_WIDTH-1) downto 0);
signal write_data_m4 : std_logic_vector ((2*DATA_MASK_WIDTH-1) downto 0);
 
signal write_data90 : std_logic_vector((DATA_WIDTH-1) downto 0);
signal write_data90_1 : std_logic_vector((DATA_WIDTH-1) downto 0);
signal write_data90_2 : std_logic_vector((DATA_WIDTH-1) downto 0);
signal write_data_m90 : std_logic_vector ((DATA_MASK_WIDTH-1) downto 0);
signal write_data_m90_1 : std_logic_vector ((DATA_MASK_WIDTH-1) downto 0);
signal write_data_m90_2 : std_logic_vector ((DATA_MASK_WIDTH-1) downto 0);
 
signal write_data270 : std_logic_vector((DATA_WIDTH-1) downto 0);
signal write_data270_1 : std_logic_vector((DATA_WIDTH-1) downto 0);
signal write_data270_2 : std_logic_vector((DATA_WIDTH-1) downto 0);
 
signal write_data_m270 : std_logic_vector ((DATA_MASK_WIDTH-1) downto 0);
signal write_data_m270_1 : std_logic_vector ((DATA_MASK_WIDTH-1) downto 0);
signal write_data_m270_2 : std_logic_vector ((DATA_MASK_WIDTH-1) downto 0);
 
 
attribute syn_preserve : boolean;
attribute syn_preserve of write_data0 : signal is true;
attribute syn_preserve of write_data1 : signal is true;
attribute syn_preserve of write_data2 : signal is true;
attribute syn_preserve of write_data3 : signal is true;
attribute syn_preserve of write_data4 : signal is true;
 
attribute syn_preserve of write_data_m0 : signal is true;
attribute syn_preserve of write_data_m1 : signal is true;
attribute syn_preserve of write_data_m2 : signal is true;
attribute syn_preserve of write_data_m3 : signal is true;
attribute syn_preserve of write_data_m4 : signal is true;
 
attribute syn_preserve of write_data90 : signal is true;
attribute syn_preserve of write_data90_1 : signal is true;
attribute syn_preserve of write_data90_2 : signal is true;
 
attribute syn_preserve of write_data270 : signal is true;
attribute syn_preserve of write_data270_1 : signal is true;
attribute syn_preserve of write_data270_2 : signal is true;
 
begin
 
write_data0 <= user_input_data;
write_data_m0 <= user_data_mask;
 
process(clk90)
begin
if clk90'event and clk90 = '1' then
write_data1 <= write_data0;
write_data_m1 <= write_data_m0;
write_data2 <= write_data1;
write_data_m2 <= write_data_m1;
write_data3 <= write_data2;
write_data_m3 <= write_data_m2;
write_data4 <= write_data3;
write_data_m4 <= write_data_m3;
end if;
end process;
 
process(clk90)
begin
if clk90'event and clk90 = '1' then
write_data90 <= write_data4((DATA_WIDTH-1) downto 0);
write_data_m90 <= write_data_m4((DATA_MASK_WIDTH-1) downto 0);
write_data90_1 <= write_data90;
write_data_m90_1 <= write_data_m90;
write_data90_2 <= write_data90_1;
write_data_m90_2 <= write_data_m90_1;
 
end if;
end process;
 
 
process(clk90)
begin
if clk90'event and clk90 = '0' then
write_data270 <= write_data4((DATA_WIDTH*2-1) downto DATA_WIDTH);
write_data_m270 <= write_data_m4((DATA_MASK_WIDTH*2-1) downto DATA_MASK_WIDTH);
write_data270_1 <= write_data270;
write_data270_2 <= write_data270_1;
write_data_m270_1 <= write_data_m270;
write_data_m270_2 <= write_data_m270_1;
 
end if;
end process;
 
write_data_rising <= write_data270_2;
write_data_falling <= write_data90_2;
data_mask_r <= write_data_m270_2;
data_mask_f <= write_data_m90_2;
 
-- write enable for data path
process(clk90)
begin
if clk90'event and clk90 = '1' then
write_en_P1 <= write_enable;
end if;
end process;
 
-- write enable for data path
process(clk90)
begin
if clk90'event and clk90 = '0' then
write_en_val <= write_en_P1;
end if;
end process;
 
end arc;
/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_controller_0.vhd
0,0 → 1,1380
--*****************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.6.1
-- \ \ Application : MIG
-- / / Filename : DDR2_Ram_Core_controller_0.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
-- Device : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Purpose : THis is main controller block. This includes the following
-- features:
-- - The controller state machine that controls the
-- initialization process upon power up, as well as the
-- read, write, and refresh commands.
-- - Accepts and decodes the user commands.
-- - Generates the address and Bank address and control signals
-- to the memory
-- - Generates control signals for other modules.
--*****************************************************************************
 
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use UNISIM.VCOMPONENTS.all;
use work.DDR2_Ram_Core_parameters_0.all;
 
entity DDR2_Ram_Core_controller_0 is
generic
(
COL_WIDTH : integer := COLUMN_ADDRESS;
ROW_WIDTH : integer := ROW_ADDRESS
);
port(
clk : in std_logic;
rst0 : in std_logic;
rst180 : in std_logic;
address : in std_logic_vector(((ROW_ADDRESS + COLUMN_ADDRESS)-1)
downto 0);
bank_addr : in std_logic_vector((BANK_ADDRESS-1) downto 0);
command_register : in std_logic_vector(2 downto 0);
burst_done : in std_logic;
ddr_rasb_cntrl : out std_logic;
ddr_casb_cntrl : out std_logic;
ddr_web_cntrl : out std_logic;
ddr_ba_cntrl : out std_logic_vector((BANK_ADDRESS-1) downto 0);
ddr_address_cntrl : out std_logic_vector((ROW_ADDRESS-1) downto 0);
ddr_cke_cntrl : out std_logic;
ddr_csb_cntrl : out std_logic;
ddr_odt_cntrl : out std_logic;
dqs_enable : out std_logic;
dqs_reset : out std_logic;
write_enable : out std_logic;
rst_calib : out std_logic;
rst_dqs_div_int : out std_logic;
cmd_ack : out std_logic;
init : out std_logic;
ar_done : out std_logic;
wait_200us : in std_logic;
auto_ref_req : out std_logic;
read_fifo_rden : out std_logic -- Read Enable signal for read fifo(to data_read)
);
end DDR2_Ram_Core_controller_0;
 
 
architecture arc of DDR2_Ram_Core_controller_0 is
 
type s_m is (IDLE, PRECHARGE, AUTO_REFRESH, ACTIVE,
FIRST_WRITE, WRITE_WAIT, BURST_WRITE,
PRECHARGE_AFTER_WRITE, PRECHARGE_AFTER_WRITE_2, READ_WAIT,
BURST_READ, ACTIVE_WAIT);
 
type s_m1 is (INIT_IDLE, INIT_PRECHARGE,
INIT_AUTO_REFRESH, INIT_LOAD_MODE_REG);
signal next_state, current_state : s_m;
signal init_next_state, init_current_state : s_m1;
 
signal ack_reg : std_logic;
signal ack_o : std_logic;
signal auto_ref : std_logic;
signal auto_ref1 : std_logic;
signal autoref_value : std_logic;
signal auto_ref_detect1 : std_logic;
signal autoref_count : std_logic_vector((MAX_REF_WIDTH-1) downto 0);
signal ar_done_p : std_logic;
signal auto_ref_issued : std_logic;
signal auto_ref_issued_p : std_logic;
signal ba_address_reg1 : std_logic_vector((BANK_ADDRESS-1) downto 0);
signal ba_address_reg2 : std_logic_vector((BANK_ADDRESS-1) downto 0);
signal burst_length : std_logic_vector(2 downto 0);
signal burst_cnt_max : std_logic_vector(2 downto 0);
signal cas_count : std_logic_vector(2 downto 0);
signal ras_count : std_logic_vector(4 downto 0);
signal column_address_reg : std_logic_vector((ROW_ADDRESS-1) downto 0);
signal ddr_rasb1 : std_logic;
signal ddr_casb1 : std_logic;
signal ddr_web1 : std_logic;
signal ddr_ba1 : std_logic_vector((BANK_ADDRESS-1) downto 0);
signal ddr_address1 : std_logic_vector((ROW_ADDRESS-1) downto 0);
signal dqs_enable_out : std_logic;
signal dqs_reset_out : std_logic;
signal dll_rst_count : std_logic_vector(7 downto 0);
signal init_count : std_logic_vector(3 downto 0);
signal init_done : std_logic;
signal init_done_r1 : std_logic;
signal init_done_dis : std_logic;
signal init_done_value : std_logic;
signal init_memory : std_logic;
signal init_mem : std_logic;
signal init_cmd_in : std_logic;
signal init_pre_count : std_logic_vector(6 downto 0);
signal ref_freq_cnt : std_logic_vector((MAX_REF_WIDTH-1) downto 0);
signal read_cmd_in : std_logic;
signal read_cmd1 : std_logic;
signal read_cmd2 : std_logic;
signal read_cmd3 : std_logic;
signal rcd_count : std_logic_vector(2 downto 0);
signal rp_cnt_value : std_logic_vector(2 downto 0);
signal rfc_count_reg : std_logic;
signal ar_done_reg : std_logic;
signal rdburst_end_1 : std_logic;
signal rdburst_end_2 : std_logic;
signal rdburst_end : std_logic;
signal rp_count : std_logic_vector(2 downto 0);
signal rfc_count : std_logic_vector(7 downto 0);
signal row_address_reg : std_logic_vector((ROW_ADDRESS-1) downto 0);
signal column_address1 : std_logic_vector((ROW_ADDRESS -1) downto 0);
signal rst_dqs_div_r : std_logic;
signal rst_dqs_div_r1 : std_logic;
signal wrburst_end_cnt : std_logic_vector(2 downto 0);
signal wrburst_end : std_logic;
signal wrburst_end_1 : std_logic;
signal wrburst_end_2 : std_logic;
signal wrburst_end_3 : std_logic;
signal wr_count : std_logic_vector(2 downto 0);
signal write_enable_out : std_logic;
signal write_cmd_in : std_logic;
signal write_cmd2 : std_logic;
signal write_cmd3 : std_logic;
signal write_cmd1 : std_logic;
signal go_to_active_value : std_logic;
signal go_to_active : std_logic;
signal dqs_div_cascount : std_logic_vector(2 downto 0);
signal dqs_div_rdburstcount : std_logic_vector(2 downto 0);
signal dqs_enable1 : std_logic;
signal dqs_enable2 : std_logic;
signal dqs_enable3 : std_logic;
signal dqs_reset1_clk0 : std_logic;
signal dqs_reset2_clk0 : std_logic;
signal dqs_reset3_clk0 : std_logic;
signal dqs_enable_int : std_logic;
signal dqs_reset_int : std_logic;
signal rst180_r : std_logic;
signal rst0_r : std_logic;
signal emr : std_logic_vector(ROW_ADDRESS - 1 downto 0);
signal lmr : std_logic_vector(ROW_ADDRESS - 1 downto 0);
signal lmr_dll_rst : std_logic_vector(ROW_ADDRESS - 1 downto 0);
signal lmr_dll_set : std_logic_vector(ROW_ADDRESS - 1 downto 0);
signal ddr_odt1 : std_logic;
signal ddr_odt2 : std_logic;
signal rst_dqs_div_int1 : std_logic;
signal accept_cmd_in : std_logic;
signal dqs_enable_i : std_logic;
signal auto_ref_wait : std_logic;
signal auto_ref_wait1 : std_logic;
signal auto_ref_wait2 : std_logic;
signal address_reg : std_logic_vector(((ROW_ADDRESS +
COLUMN_ADDRESS)-1) downto 0);
signal ddr_rasb2 : std_logic;
signal ddr_casb2 : std_logic;
signal ddr_web2 : std_logic;
signal count6 : std_logic_vector(7 downto 0);
signal clk180 : std_logic;
signal odt_deassert : std_logic;
 
constant addr_const1 : std_logic_vector(14 downto 0) := "000010000000000";
constant addr_const2 : std_logic_vector(14 downto 0) := "000001110000000"; --380
constant addr_const3 : std_logic_vector(14 downto 0) := "000110001111111"; --C7F
constant ba_const1 : std_logic_vector(2 downto 0) := "010";
constant ba_const2 : std_logic_vector(2 downto 0) := "011";
constant ba_const3 : std_logic_vector(2 downto 0) := "001";
 
attribute iob : string;
attribute syn_useioff : boolean;
attribute syn_preserve : boolean;
attribute syn_keep : boolean;
 
attribute iob of rst_iob_out : label is "FORCE";
attribute syn_useioff of rst_iob_out : label is true;
attribute syn_preserve of lmr_dll_rst : signal is true;
attribute syn_preserve of lmr_dll_set : signal is true;
attribute syn_preserve of ba_address_reg1 : signal is true;
attribute syn_preserve of ba_address_reg2 : signal is true;
attribute syn_preserve of column_address_reg : signal is true;
attribute syn_preserve of row_address_reg : signal is true;
 
begin
 
clk180 <= not clk;
emr <= EXT_LOAD_MODE_REGISTER;
lmr <= LOAD_MODE_REGISTER;
lmr_dll_rst <= lmr(ROW_ADDRESS - 1 downto 9) & '1' & lmr(7 downto 0);
lmr_dll_set <= lmr(ROW_ADDRESS - 1 downto 9) & '0' & lmr(7 downto 0);
 
 
-- Input : COMMAND REGISTER FORMAT
-- 000 - NOP
-- 010 - Initialize memory
-- 100 - Write Request
-- 110 - Read request
 
 
-- Input : Address format
-- row address = address((ROW_ADDRESS + COLUMN_ADDRESS) -1 downto COLUMN_ADDRESS)
-- column address = address(COLUMN_ADDRESS-1 downto 0)
 
ddr_csb_cntrl <= '0';
ddr_cke_cntrl <= not wait_200us;
init <= init_done;
ddr_rasb_cntrl <= ddr_rasb2;
ddr_casb_cntrl <= ddr_casb2;
ddr_web_cntrl <= ddr_web2;
rst_dqs_div_int <= rst_dqs_div_int1;
ddr_address_cntrl <= ddr_address1;
ddr_ba_cntrl <= ddr_ba1;
 
-- turn off auto-precharge when issuing read/write commands (A10 = 0)
-- mapping the column address for linear addressing.
gen_ddr_addr_col_0: if (COL_WIDTH = ROW_WIDTH-1) generate
column_address1 <= (address_reg(COL_WIDTH-1 downto 10) & '0' &
address_reg(9 downto 0));
end generate;
 
gen_ddr_addr_col_1: if ((COL_WIDTH > 10) and
not(COL_WIDTH = ROW_WIDTH-1)) generate
column_address1(ROW_WIDTH-1 downto COL_WIDTH+1) <= (others => '0');
column_address1(COL_WIDTH downto 0) <=
(address_reg(COL_WIDTH-1 downto 10) & '0' & address_reg(9 downto 0));
end generate;
 
gen_ddr_addr_col_2: if (not((COL_WIDTH > 10) or
(COL_WIDTH = ROW_WIDTH-1))) generate
column_address1(ROW_WIDTH-1 downto COL_WIDTH+1) <= (others => '0');
column_address1(COL_WIDTH downto 0) <=
('0' & address_reg(COL_WIDTH-1 downto 0));
end generate;
 
 
process(clk)
begin
if clk'event and clk = '0' then
rst180_r <= rst180;
end if;
end process;
 
process(clk)
begin
if clk'event and clk = '1' then
rst0_r <= rst0;
end if;
end process;
 
--******************************************************************************
-- Register user address
--******************************************************************************
 
process(clk)
begin
if clk'event and clk = '0' then
row_address_reg <= address_reg(((ROW_ADDRESS + COLUMN_ADDRESS)-1) downto
COLUMN_ADDRESS);
column_address_reg <= column_address1;
ba_address_reg1 <= bank_addr;
ba_address_reg2 <= ba_address_reg1;
address_reg <= address;
end if;
end process;
 
process(clk)
begin
if clk'event and clk = '0' then
if rst180_r = '1' then
burst_length <= "000";
else
burst_length <= lmr(2 downto 0);
end if;
end if;
end process;
 
process(clk)
begin
if (clk'event and clk = '0') then
if rst180_r = '1' then
accept_cmd_in <= '0';
elsif (current_state = IDLE and (rp_count = "000" and (rfc_count_reg and
not(auto_ref_wait) and
not(auto_ref_issued)) = '1')) then
accept_cmd_in <= '1';
else
accept_cmd_in <= '0';
end if;
end if;
end process;
--******************************************************************************
-- Commands from user.
--******************************************************************************
init_cmd_in <= '1' when (command_register = "010") else '0';
write_cmd_in <= '1' when (command_register = "100" and
accept_cmd_in = '1') else '0';
read_cmd_in <= '1' when (command_register = "110" and
accept_cmd_in = '1') else '0';
 
--******************************************************************************
-- write_cmd1 is asserted when user issued write command and the controller s/m
-- is in idle state and AUTO_REF is not asserted.
--******************************************************************************
process(clk)
begin
if clk'event and clk = '0' then
if rst180_r = '1' then
write_cmd1 <= '0';
write_cmd2 <= '0';
write_cmd3 <= '0';
else
if (accept_cmd_in = '1') then
write_cmd1 <= write_cmd_in;
end if;
write_cmd2 <= write_cmd1;
write_cmd3 <= write_cmd2;
end if;
end if;
end process;
 
--******************************************************************************
-- read_cmd1 is asserted when user issued read command and the controller s/m
-- is in idle state and AUTO_REF is not asserted.
--******************************************************************************
 
process(clk)
begin
if clk'event and clk = '0' then
if rst180_r = '1' then
read_cmd1 <= '0';
read_cmd2 <= '0';
read_cmd3 <= '0';
else
if (accept_cmd_in = '1') then
read_cmd1 <= read_cmd_in;
end if;
read_cmd2 <= read_cmd1;
read_cmd3 <= read_cmd2;
end if;
end if;
end process;
 
--******************************************************************************
-- ras_count- Active to Precharge time
-- Controller is giving tras violation when user issues a single read command for
-- BL=4 and tRAS is more then 42ns.It uses a fixed clk count of 7 clocks which is
-- 7*6(@166) = 42ns. Addded ras_count counter which will take care of tras timeout.
-- RAS_COUNT_VALUE parameter is used to load the counter and it depends on the
-- selected memory and frequency
--******************************************************************************
process(clk)
begin
if clk'event and clk = '0' then
if rst180_r = '1' then
ras_count <= "00000";
elsif(current_state = ACTIVE) then
ras_count <= RAS_COUNT_VALUE - '1';
elsif(ras_count /= "00000") then
ras_count <= ras_count - '1';
end if;
end if;
end process;
--******************************************************************************
-- rfc_count
-- An executable command can be issued only after Trfc period after a AUTOREFRESH
-- command is issued. rfc_count_value is set in the parameter file depending on
-- the memory device speed grade and the selected frequency.For example for 5B
-- speed grade, at 133Mhz, rfc_counter_value = 8'b00001001.
-- ( Trfc/clk_period= 75/7.5= 10)
--******************************************************************************
 
process(clk)
begin
if clk'event and clk = '0' then
if rst180_r = '1' then
rfc_count <= "00000000";
elsif(current_state = AUTO_REFRESH) then
rfc_count <= RFC_COUNT_VALUE;
elsif(rfc_count /= "00000000") then
rfc_count <= rfc_count - '1';
end if;
end if;
end process;
 
--******************************************************************************
-- rp_count
-- An executable command can be issued only after Trp period after a PRECHARGE
-- command is issued.
--******************************************************************************
 
process(clk)
begin
if clk'event and clk = '0' then
if rst180_r = '1' then
rp_count <= "000";
elsif(current_state = PRECHARGE) then
rp_count <= RP_COUNT_VALUE;
elsif(rp_count /= "000") then
rp_count <= rp_count - '1';
end if;
end if;
end process;
 
 
--******************************************************************************
-- rcd_count
-- ACTIVE to READ/WRITE delay - Minimum interval between ACTIVE and READ/WRITE command.
--******************************************************************************
 
process(clk)
begin
if (clk'event and clk = '0') then
if (rst180_r = '1') then
rcd_count <= "000";
elsif (current_state = ACTIVE) then
rcd_count <= "001";
elsif (rcd_count /= "000") then
rcd_count <= rcd_count - '1';
end if;
end if;
end process;
 
--******************************************************************************
-- WR Counter
-- a PRECHARGE command can be applied only after 2 cycles after a WRITE command
-- has finished executing
--******************************************************************************
process (clk)
begin
if clk'event and clk = '0' then
if rst180_r = '1' then
wr_count <= "000";
else
if (dqs_enable_int = '1') then
wr_count <= TWR_COUNT_VALUE;
elsif (wr_count /= "000") then
wr_count <= wr_count - "001";
end if;
end if;
end if;
end process;
 
--******************************************************************************
-- autoref_count - This counter is used to issue AUTO REFRESH command to
-- the memory for every 7.8125us.
-- (Auto Refresh Request is raised for every 7.7 us to allow for termination
-- of any ongoing bus transfer).For example at 166MHz frequency
-- autoref_count = refresh_time_period/clock_period = 7.7us/6.02ns = 1279
--******************************************************************************
ref_freq_cnt <= MAX_REF_CNT;
process(clk)
begin
if clk'event and clk = '0' then
if rst180_r = '1' then
autoref_value <= '0';
elsif (autoref_count = ref_freq_cnt) then
autoref_value <= '1';
else
autoref_value <= '0';
end if;
end if;
end process;
 
process(clk)
begin
if clk'event and clk = '0' then
if rst180_r = '1' then
autoref_count <= (others => '0');
elsif (autoref_value = '1') then
autoref_count <= (others => '0');
else
autoref_count <= autoref_count + '1';
end if;
end if;
end process;
 
process(clk)
begin
if clk'event and clk = '0' then
if rst180_r = '1' then
auto_ref_detect1 <= '0';
auto_ref1 <= '0';
else
auto_ref_detect1 <= autoref_value and init_done;
auto_ref1 <= auto_ref_detect1;
end if;
end if;
end process;
 
ar_done_p <= '1' when ar_done_reg = '1' else '0';
 
process(clk)
begin
if clk'event and clk = '0' then
if rst180_r = '1' then
auto_ref_wait <= '0';
ar_done <= '0';
auto_ref_issued <= '0';
else
if (auto_ref1 = '1' and auto_ref_wait = '0') then
auto_ref_wait <= '1';
elsif (auto_ref_issued = '1') then
auto_ref_wait <= '0';
else
auto_ref_wait <= auto_ref_wait;
end if;
ar_done <= ar_done_p;
auto_ref_issued <= auto_ref_issued_p;
end if;
end if;
end process;
 
process(clk)
begin
if clk'event and clk = '0' then
if rst180_r = '1' then
auto_ref_wait1 <= '0';
auto_ref_wait2 <= '0';
auto_ref <= '0';
else
if (auto_ref_issued_p = '1') then
auto_ref_wait1 <= '0';
auto_ref_wait2 <= '0';
auto_ref <= '0';
else
auto_ref_wait1 <= auto_ref_wait;
auto_ref_wait2 <= auto_ref_wait1;
auto_ref <= auto_ref_wait2;
end if;
end if;
end if;
end process;
 
auto_ref_req <= auto_ref_wait;
auto_ref_issued_p <= '1' when (current_state = AUTO_REFRESH) else '0';
 
--******************************************************************************
-- Common counter for the Initialization sequence
--******************************************************************************
process(clk)
begin
if (clk'event and clk = '0') then
if (rst180_r = '1') then
count6 <= "00000000";
elsif(init_current_state = INIT_AUTO_REFRESH or init_current_state
= INIT_PRECHARGE or init_current_state = INIT_LOAD_MODE_REG) then
count6 <= RFC_COUNT_VALUE;
elsif(count6 /= "00000000") then
count6 <= count6 - '1';
else
count6 <= "00000000";
end if;
end if;
end process;
 
--******************************************************************************
-- While doing consecutive READs or WRITEs, the burst_cnt_max value determines
-- when the next READ or WRITE command should be issued. burst_cnt_max shows the
-- number of clock cycles for each burst.
-- e.g burst_cnt_max = 2 for a burst length of 4
-- = 4 for a burst length of 8
--******************************************************************************
 
burst_cnt_max <= "010" when burst_length = "010" else
"100" when burst_length = "011" else
"000";
 
process(clk)
begin
if (clk'event and clk = '0') then
if (rst180_r = '1') then
cas_count <= "000";
elsif(current_state = BURST_READ) then
cas_count <= burst_cnt_max - '1';
elsif(cas_count /= "000") then
cas_count <= cas_count - '1';
end if;
end if;
end process;
 
 
process(clk)
begin
if (clk'event and clk = '0') then
if (rst180_r = '1') then
wrburst_end_cnt <= "000";
elsif ((current_state = FIRST_WRITE) or (current_state = BURST_WRITE)) then
wrburst_end_cnt <= burst_cnt_max;
elsif (wrburst_end_cnt /= "000") then
wrburst_end_cnt <= wrburst_end_cnt - '1';
end if;
end if;
end process;
 
process(clk)
begin
if clk'event and clk = '0' then
if rst180_r = '1' then
rdburst_end_1 <= '0';
else
if(burst_done = '1') then
rdburst_end_1 <= '1';
else
rdburst_end_1 <= '0';
end if;
rdburst_end_2 <= rdburst_end_1;
end if;
end if;
end process;
 
rdburst_end <= rdburst_end_1 or rdburst_end_2;
 
process(clk)
begin
if clk'event and clk = '0' then
if rst180_r = '1' then
wrburst_end_1 <= '0';
else
if (burst_done = '1') then
wrburst_end_1 <= '1';
else
wrburst_end_1 <= '0';
end if;
wrburst_end_2 <= wrburst_end_1;
wrburst_end_3 <= wrburst_end_2;
end if;
end if;
end process;
 
wrburst_end <= wrburst_end_1 or wrburst_end_2 or wrburst_end_3;
 
--******************************************************************************
-- dqs_enable and dqs_reset signals are used to generate DQS signal during write
-- data.
--******************************************************************************
dqs_enable_out <= '1' when ((current_state = FIRST_WRITE) or
(current_state = BURST_WRITE) or
(WRburst_end_cnt /= "000")) else '0';
dqs_reset_out <= '1' when current_state = FIRST_WRITE else '0';
dqs_enable <= dqs_enable_i;
dqs_enable_i <= dqs_enable2;
dqs_reset <= dqs_reset2_clk0;
 
process(clk)
begin
if clk'event and clk = '0' then
if rst180_r = '1' then
dqs_enable_int <= '0';
dqs_reset_int <= '0';
else
dqs_enable_int <= dqs_enable_out;
dqs_reset_int <= dqs_reset_out;
end if;
end if;
end process;
 
process(clk)
begin
if clk'event and clk = '1' then
if rst0_r = '1' then
dqs_enable1 <= '0';
dqs_enable2 <= '0';
dqs_enable3 <= '0';
dqs_reset1_clk0 <= '0';
dqs_reset2_clk0 <= '0';
dqs_reset3_clk0 <= '0';
else
dqs_enable1 <= dqs_enable_int;
dqs_enable2 <= dqs_enable1;
dqs_enable3 <= dqs_enable2;
dqs_reset1_clk0 <= dqs_reset_int;
dqs_reset2_clk0 <= dqs_reset1_clk0;
dqs_reset3_clk0 <= dqs_reset2_clk0;
end if;
end if;
end process;
 
--******************************************************************************
--Write Enable signal to the datapath
--******************************************************************************
 
write_enable_out <= '1' when (wrburst_end_cnt /= "000")else '0';
cmd_ack <= ack_reg;
ack_o <= '1' when ((write_cmd_in = '1') or (write_cmd1 = '1') or
(read_cmd_in = '1') or (read_cmd1 = '1')) else '0';
 
process(clk)
begin
if clk'event and clk = '0' then
if rst180_r = '1' then
write_enable <= '0';
else
write_enable <= write_enable_out;
end if;
end if;
end process;
 
 
ACK_REG_INST1 : FD
port map (
Q => ack_reg,
D => ack_o,
C => clk180
);
 
--******************************************************************************
-- init_done will be asserted when initialization sequence is complete
--******************************************************************************
 
process(clk)
begin
if clk'event and clk = '0' then
if rst180_r = '1' then
init_memory <= '0';
init_done <= '0';
init_done_r1 <= '0';
else
init_memory <= init_mem;
init_done_r1 <= init_done;
if ((init_done_value = '1')and (init_count = "1011")) then
init_done <= '1';
else
init_done <= '0';
end if;
end if;
end if;
end process;
 
init_done_dis <= '1' when ( init_done = '1' and init_done_r1 = '0') else
'0';
process(clk)
begin
if(clk'event and clk = '0') then
if rst180_r = '0' then
--synthesis translate_off
assert (init_done_dis = '0') report "INITIALIZATION_DONE" severity note;
--synthesis translate_on
end if;
end if;
end process;
 
process (clk)
begin
if clk'event and clk = '0' then
if init_cmd_in = '1' or rst180_r = '1' then
init_pre_count <= "1010000";
else
init_pre_count <= init_pre_count - "0000001";
end if;
end if;
end process;
 
process(clk)
begin
if clk'event and clk = '0' then
if rst180_r = '1' then
init_mem <= '0';
elsif (init_cmd_in = '1') then
init_mem <= '1';
elsif ((init_count = "1011") and (count6 = "00000000")) then
init_mem <= '0';
else
init_mem <= init_mem;
end if;
end if;
end process;
 
-- Counter for Memory Initialization sequence
 
 
process(clk)
begin
if(clk'event and clk = '0') then
if rst180_r = '1' then
init_count <= "0000";
elsif(((init_current_state = INIT_PRECHARGE) or
(init_current_state = INIT_LOAD_MODE_REG) or
(init_current_state = INIT_AUTO_REFRESH)) and init_memory = '1') then
init_count <= init_count + '1';
else
init_count <= init_count;
end if;
end if;
end process;
 
init_done_value <= '1' when ((init_count = "1011") and
(dll_rst_count = "00000001")) else '0';
 
-- Counter to count 200 clock cycles When DLL reset is issued during initialization.
 
process(clk)
begin
if(clk'event and clk = '0') then
if rst180_r = '1' then
dll_rst_count <= "00000000";
elsif(init_count = "0100") then
dll_rst_count <= "11001000";
elsif(dll_rst_count /= "00000001") then
dll_rst_count <= dll_rst_count - '1';
else
dll_rst_count <= dll_rst_count;
end if;
end if;
end process;
 
 
go_to_active_value <= '1' when ((write_cmd_in = '1') and (accept_cmd_in = '1'))
or ((read_cmd_in = '1') and (accept_cmd_in = '1'))
else '0';
 
process(clk)
begin
if clk'event and clk = '0' then
if rst180_r = '1' then
go_to_active <= '0';
else
go_to_active <= go_to_active_value;
end if;
end if;
end process;
 
--******************************************************************************
-- Register counter values
--******************************************************************************
process(clk)
begin
if clk'event and clk = '0' then
if rst180_r = '1' then
ar_done_reg <= '0';
rfc_count_reg <= '0';
else
if(rfc_count = "00000010") then
ar_done_reg <= '1';
else
ar_done_reg <= '0';
end if;
if(ar_done_reg = '1') then
rfc_count_reg <= '1';
elsif (init_done = '1' and init_mem = '0' and rfc_count = "00000000")
then
rfc_count_reg <= '1';
elsif (auto_ref_issued = '1') then
rfc_count_reg <= '0';
else
rfc_count_reg <= rfc_count_reg;
end if;
end if;
end if;
end process;
 
--******************************************************************************
-- Initialization state machine
--******************************************************************************
 
process(clk)
begin
if clk'event and clk = '0' then
if rst180_r = '1' then
init_current_state <= INIT_IDLE;
else
init_current_state <= init_next_state;
end if;
end if;
end process;
 
process (rst180_r, init_count, init_current_state, init_memory, count6,
init_pre_count)
begin
if rst180_r = '1' then
init_next_state <= INIT_IDLE;
else
case init_current_state is
when INIT_IDLE =>
if init_memory = '1' then
case init_count is
when "0000" =>
if(init_pre_count = "0000001") then
init_next_state <= INIT_PRECHARGE;
else
init_next_state <= INIT_IDLE;
end if;
when "0001" =>
if (count6 = "00000000") then
init_next_state <= INIT_LOAD_MODE_REG;
else
init_next_state <= INIT_IDLE;
end if;
when "0010" =>
-- for reseting DLL in Base Mode register
if (count6 = "00000000") then
init_next_state <= INIT_LOAD_MODE_REG;
else
init_next_state <= INIT_IDLE;
end if;
when "0011" =>
if (count6 = "00000000") then
init_next_state <= INIT_LOAD_MODE_REG; -- For EMR
else
init_next_state <= INIT_IDLE;
end if;
when "0100" =>
if (count6 = "00000000") then
init_next_state <= INIT_LOAD_MODE_REG; -- For EMR
else
init_next_state <= INIT_IDLE;
end if;
when "0101" =>
if (count6 = "00000000") then
init_next_state <= INIT_PRECHARGE;
else
init_next_state <= INIT_IDLE;
end if;
when "0110" =>
if (count6 = "00000000") then
init_next_state <= INIT_AUTO_REFRESH;
else
init_next_state <= INIT_IDLE;
end if;
when "0111" =>
if (count6 = "00000000") then
init_next_state <= INIT_AUTO_REFRESH;
else
init_next_state <= INIT_IDLE;
end if;
when "1000" =>
-- to deactivate the rst DLL bit in the LMR
if (count6 = "00000000") then
init_next_state <= INIT_LOAD_MODE_REG;
else
init_next_state <= INIT_IDLE;
end if;
when "1001" =>
-- to set OCD to default in EMR
if (count6 = "00000000") then
init_next_state <= INIT_LOAD_MODE_REG;
else
init_next_state <= INIT_IDLE;
end if;
when "1010" =>
if (count6 = "00000000") then
init_next_state <= INIT_LOAD_MODE_REG; -- OCD exit in EMR
else
init_next_state <= INIT_IDLE;
end if;
when "1011" =>
if (count6 = "00000000") then
init_next_state <= INIT_IDLE;
else
init_next_state <= init_current_state;
end if;
when others =>
init_next_state <= INIT_IDLE;
end case;
else
init_next_state <= INIT_IDLE;
end if;
when INIT_PRECHARGE =>
init_next_state <= INIT_IDLE;
when INIT_LOAD_MODE_REG =>
init_next_state <= INIT_IDLE;
when INIT_AUTO_REFRESH =>
init_next_state <= INIT_IDLE;
when others =>
init_next_state <= INIT_IDLE;
end case;
end if;
end process;
 
--******************************************************************************
-- MAIN state machine
--******************************************************************************
 
process(clk)
begin
if clk'event and clk = '0' then
if rst180_r = '1' then
current_state <= IDLE;
else
current_state <= next_state;
end if;
end if;
end process;
 
process (rst180_r, cas_count, wr_count,
go_to_active, write_cmd1, read_cmd3, current_state,
wrburst_end, wrburst_end_cnt,
rdburst_end, init_memory,rcd_count, ras_count,
auto_ref, rfc_count_reg, rp_count)
begin
if rst180_r = '1' then
next_state <= IDLE;
else
case current_state is
when IDLE =>
if (init_memory = '0') then
if(auto_ref = '1' and rfc_count_reg = '1' and rp_count = "000") then
next_state <= AUTO_REFRESH; -- normal Refresh in the IDLE state
elsif go_to_active = '1' then
next_state <= ACTIVE;
else
next_state <= IDLE;
end if;
else
next_state <= IDLE;
end if;
when PRECHARGE =>
next_state <= IDLE;
when AUTO_REFRESH =>
next_state <= IDLE;
when ACTIVE =>
next_state <= ACTIVE_WAIT;
when ACTIVE_WAIT =>
if (rcd_count = "000" and write_cmd1 = '1') then
next_state <= FIRST_WRITE;
elsif (rcd_count = "000" and read_cmd3 = '1') then
next_state <= BURST_READ;
else
next_state <= ACTIVE_WAIT;
end if;
when FIRST_WRITE =>
next_state <= WRITE_WAIT;
when WRITE_WAIT =>
case wrburst_end is
when '1' =>
next_state <= PRECHARGE_AFTER_WRITE;
when '0' =>
if wrburst_end_cnt = "010" then
next_state <= BURST_WRITE;
else
next_state <= WRITE_WAIT;
end if;
when others =>
next_state <= WRITE_WAIT;
end case;
when BURST_WRITE =>
next_state <= WRITE_WAIT;
when PRECHARGE_AFTER_WRITE =>
next_state <= PRECHARGE_AFTER_WRITE_2;
when PRECHARGE_AFTER_WRITE_2 =>
if(wr_count = "00" and ras_count = "00000") then
next_state <= PRECHARGE;
else
next_state <= PRECHARGE_AFTER_WRITE_2;
end if;
when READ_WAIT =>
case rdburst_end is
when '1' =>
next_state <= PRECHARGE_AFTER_WRITE;
when '0' =>
if cas_count = "001" then
next_state <= BURST_READ;
else
next_state <= READ_WAIT;
end if;
when others =>
next_state <= READ_WAIT;
end case;
 
when BURST_READ =>
next_state <= READ_WAIT;
 
when others =>
next_state <= IDLE;
end case;
end if;
end process;
 
process(clk)
begin
if clk'event and clk = '0' then
if rst180_r = '1' then
ddr_address1 <= (others => '0');
elsif (init_mem = '1') then
case (init_count) is
when "0000" | "0101" =>
ddr_address1 <= addr_const1((ROW_ADDRESS - 1) downto 0);
when "0001" =>
ddr_address1 <= (others => '0');
when "0010" =>
ddr_address1 <= (others => '0');
when "0011" =>
ddr_address1 <= emr;
when "0100" =>
ddr_address1 <= lmr_dll_rst;
when "1000" =>
ddr_address1 <= lmr_dll_set;
when "1001" =>
ddr_address1 <= emr or addr_const2((ROW_ADDRESS - 1) downto 0);
when "1010" =>
ddr_address1 <= emr and addr_const3((ROW_ADDRESS - 1) downto 0);
when others =>
ddr_address1 <= (others => '0');
end case;
elsif (current_state = PRECHARGE) then
ddr_address1 <= addr_const1((ROW_ADDRESS - 1) downto 0);
elsif (current_state = ACTIVE) then
ddr_address1 <= row_address_reg;
elsif (current_state = BURST_WRITE or current_state = FIRST_WRITE or
current_state = BURST_READ) then
ddr_address1 <= column_address_reg((ROW_ADDRESS - 1) downto 0);
else
ddr_address1 <= (others => '0');
end if;
end if;
end process;
 
process(clk)
begin
if clk'event and clk = '0' then
if rst180_r = '1' then
ddr_ba1 <= (others => '0');
elsif (init_mem = '1') then
case (init_count) is
when "0001" =>
ddr_ba1 <= ba_const1((BANK_ADDRESS -1) downto 0);
when "0010" =>
ddr_ba1 <= ba_const2((BANK_ADDRESS -1) downto 0);
when "0011" | "1001" | "1010" =>
ddr_ba1 <= ba_const3((BANK_ADDRESS -1) downto 0);
when others =>
ddr_ba1 <= (others => '0');
end case;
elsif (current_state = ACTIVE or current_state = FIRST_WRITE or
current_state = BURST_WRITE or current_state = BURST_READ) then
ddr_ba1 <= ba_address_reg2;
else
ddr_ba1 <= (others => '0');
end if;
end if;
end process;
 
process(clk)
begin
if clk'event and clk = '0' then
if rst180_r = '1' then
odt_deassert <= '0';
elsif(wrburst_end_3 = '1') then
odt_deassert <= '1';
elsif(write_cmd3 = '0') then
odt_deassert <= '0';
else
odt_deassert <= odt_deassert;
end if;
end if;
end process;
 
ddr_odt1 <= '1' when (write_cmd3 = '1' and (emr(6) = '1' or emr(2) = '1') and
odt_deassert = '0') else '0';
 
--******************************************************************************
-- Register CONTROL SIGNALS outputs
--******************************************************************************
process(clk)
begin
if clk'event and clk = '0' then
if rst180_r = '1' then
ddr_odt2 <= '0';
ddr_rasb2 <= '1';
ddr_casb2 <= '1';
ddr_web2 <= '1';
else
ddr_odt2 <= ddr_odt1;
ddr_rasb2 <= ddr_rasb1;
ddr_casb2 <= ddr_casb1;
ddr_web2 <= ddr_web1;
end if;
end if;
end process;
 
process(clk)
begin
if clk'event and clk = '0' then
if rst180_r = '1' then
ddr_odt_cntrl <= '0';
else
ddr_odt_cntrl <= ddr_odt2;
end if;
end if;
end process;
 
--******************************************************************************
-- control signals to the Memory
--******************************************************************************
 
ddr_rasb1 <= '0' when (current_state = ACTIVE or current_state = PRECHARGE or
current_state = AUTO_REFRESH or
init_current_state = INIT_PRECHARGE or
init_current_state = INIT_AUTO_REFRESH or
init_current_state = INIT_LOAD_MODE_REG) else '1';
 
ddr_casb1 <= '0' when (current_state = BURST_READ or
current_state = BURST_WRITE or
current_state = FIRST_WRITE or
current_state = AUTO_REFRESH or
init_current_state = INIT_AUTO_REFRESH or
init_current_state = INIT_LOAD_MODE_REG) else '1';
 
ddr_web1 <= '0' when (current_state = BURST_WRITE or
current_state = FIRST_WRITE or
current_state = PRECHARGE or
init_current_state = INIT_PRECHARGE or
init_current_state = INIT_LOAD_MODE_REG) else '1';
 
-------------------------------------------------------------------------------
 
process(clk)
begin
if(clk'event and clk = '0') then
if rst180_r = '1' then
dqs_div_cascount <= "000";
else
if(ddr_rasb2 = '1' and ddr_casb2 = '0' and ddr_web2 = '1') then
dqs_div_cascount <= burst_cnt_max;
else
if dqs_div_cascount /= "000" then
dqs_div_cascount <= dqs_div_cascount - "001";
else
dqs_div_cascount <= dqs_div_cascount;
end if;
end if;
end if;
end if;
end process;
 
process(clk)
begin
if(clk'event and clk = '0') then
if rst180_r = '1' then
dqs_div_rdburstcount <= "000";
else
if (dqs_div_cascount = "001" and burst_length = "010") then
dqs_div_rdburstcount <= "010";
elsif (dqs_div_cascount = "011" and burst_length = "011") then
dqs_div_rdburstcount <= "100";
else
if dqs_div_rdburstcount /= "000" then
dqs_div_rdburstcount <= dqs_div_rdburstcount - "001";
else
dqs_div_rdburstcount <= dqs_div_rdburstcount;
end if;
end if;
end if;
end if;
end process;
 
process(clk)
begin
if(clk'event and clk = '0') then
if rst180_r = '1' then
rst_dqs_div_r <= '0';
else
if (dqs_div_cascount = "001" and burst_length = "010")then
rst_dqs_div_r <= '1';
elsif (dqs_div_cascount = "011" and burst_length = "011")then
rst_dqs_div_r <= '1';
else
if (dqs_div_rdburstcount = "001" and dqs_div_cascount = "000") then
rst_dqs_div_r <= '0';
else
rst_dqs_div_r <= rst_dqs_div_r;
end if;
end if;
end if;
end if;
end process;
 
process(clk) -- For Reg dimm
begin
if(clk'event and clk = '0') then
rst_dqs_div_r1 <= rst_dqs_div_r;
end if;
end process;
 
process (clk)
begin
if (clk'event and clk = '0') then
if (dqs_div_cascount /= "000" or dqs_div_rdburstcount /= "000") then
rst_calib <= '1';
else
rst_calib <= '0';
end if;
end if;
end process;
 
rst_iob_out : FD
port map (
Q => rst_dqs_div_int1,
D => rst_dqs_div_r,
C => clk
);
 
--Read fifo read enable logic, this signal is same as rst_dqs_div_int signal for RDIMM
--and one clock ahead of rst_dqs_div_int for component or UDIMM OR SODIMM.
process(clk)
begin
if clk'event and clk = '0' then
read_fifo_rden <= rst_dqs_div_r1;
end if;
end process;
end arc;
/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_infrastructure_top.vhd
0,0 → 1,293
--*****************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.6.1
-- \ \ Application : MIG
-- / / Filename : DDR2_Ram_Core_infrastructure_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
-- Device : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Purpose : This module has instantiations clk_dcm,cal_top and generate
-- reset signals to the design
--*****************************************************************************
 
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use UNISIM.VCOMPONENTS.all;
use work.DDR2_Ram_Core_parameters_0.all;
 
entity DDR2_Ram_Core_infrastructure_top is
port(
reset_in_n : in std_logic;
sys_clk : in std_logic;
sys_clkb : in std_logic;
sys_clk_in : in std_logic;
delay_sel_val1_val : out std_logic_vector(4 downto 0);
sys_rst_val : out std_logic;
sys_rst90_val : out std_logic;
clk_int_val : out std_logic;
clk90_int_val : out std_logic;
sys_rst180_val : out std_logic;
wait_200us : out std_logic;
-- debug signals
dbg_phase_cnt : out std_logic_vector(4 downto 0);
dbg_cnt : out std_logic_vector(5 downto 0);
dbg_trans_onedtct : out std_logic;
dbg_trans_twodtct : out std_logic;
dbg_enb_trans_two_dtct : out std_logic
);
 
end DDR2_Ram_Core_infrastructure_top;
 
architecture arc of DDR2_Ram_Core_infrastructure_top is
 
component DDR2_Ram_Core_clk_dcm
port(
input_clk : in std_logic;
rst : in std_logic;
clk : out std_logic;
clk90 : out std_logic;
dcm_lock : out std_logic
);
end component;
 
component DDR2_Ram_Core_cal_top
port (
clk : in std_logic;
clk0dcmlock : in std_logic;
reset : in std_logic;
tapfordqs : out std_logic_vector(4 downto 0);
dbg_phase_cnt : out std_logic_vector(4 downto 0);
dbg_cnt : out std_logic_vector(5 downto 0);
dbg_trans_onedtct : out std_logic;
dbg_trans_twodtct : out std_logic;
dbg_enb_trans_two_dtct : out std_logic
);
end component;
 
signal user_rst : std_logic;
signal user_cal_rst : std_logic;
signal clk_int : std_logic;
signal clk90_int : std_logic;
signal dcm_lock : std_logic;
signal sys_rst_o : std_logic;
signal sys_rst_1 : std_logic := '1';
signal sys_rst : std_logic;
signal sys_rst90_o : std_logic;
signal sys_rst90_1 : std_logic := '1';
signal sys_rst90 : std_logic;
signal sys_rst180_o : std_logic;
signal sys_rst180_1 : std_logic := '1';
signal sys_rst180 : std_logic;
signal delay_sel_val1 : std_logic_vector(4 downto 0);
signal clk_int_val1 : std_logic;
signal clk_int_val2 : std_logic;
signal clk90_int_val1 : std_logic;
signal clk90_int_val2 : std_logic;
signal wait_200us_i : std_logic;
signal wait_200us_int : std_logic;
signal wait_clk90 : std_logic;
signal wait_clk270 : std_logic;
signal counter200 : std_logic_vector(15 downto 0);
signal sys_clk_ibuf : std_logic;
 
begin
 
DIFF_ENDED_CLKS_INST : if(CLK_TYPE = "DIFFERENTIAL") generate
begin
SYS_CLK_INST : IBUFGDS_LVDS_25
port map(
I => sys_clk,
IB => sys_clkb,
O => sys_clk_ibuf
);
end generate;
 
SINGLE_ENDED_CLKS_INST : if(CLK_TYPE = "SINGLE_ENDED") generate
begin
SYS_CLK_INST : IBUFG
port map(
I => sys_clk_in,
O => sys_clk_ibuf
);
end generate;
 
clk_int_val <= clk_int;
clk90_int_val <= clk90_int;
sys_rst_val <= sys_rst;
sys_rst90_val <= sys_rst90;
sys_rst180_val <= sys_rst180;
delay_sel_val1_val <= delay_sel_val1;
 
 
-- To remove delta delays in the clock signals observed during simulation
-- ,Following signals are used
 
clk_int_val1 <= clk_int;
clk90_int_val1 <= clk90_int;
clk_int_val2 <= clk_int_val1;
clk90_int_val2 <= clk90_int_val1;
user_rst <= not reset_in_n when RESET_ACTIVE_LOW = '1' else reset_in_n;
user_cal_rst <= reset_in_n when RESET_ACTIVE_LOW = '1' else not reset_in_n;
 
process(clk_int_val2)
begin
if clk_int_val2'event and clk_int_val2 = '1' then
if user_rst = '1' or dcm_lock = '0' then
wait_200us_i <= '1';
counter200 <= (others => '0');
else
if( counter200 < 33400) then
wait_200us_i <= '1';
counter200 <= counter200 + 1;
else
counter200 <= counter200;
wait_200us_i <= '0';
end if;
end if;
end if;
end process;
 
process(clk_int_val2)
begin
if clk_int_val2'event and clk_int_val2 = '1' then
wait_200us <= wait_200us_i;
end if;
end process;
 
process(clk_int_val2)
begin
if clk_int_val2'event and clk_int_val2 = '1' then
wait_200us_int <= wait_200us_i;
end if;
end process;
 
process(clk90_int_val2)
begin
if clk90_int_val2'event and clk90_int_val2 = '0' then
if user_rst = '1' or dcm_lock = '0' then
wait_clk270 <= '1';
else
wait_clk270 <= wait_200us_int;
end if;
end if;
end process;
 
process(clk90_int_val2)
begin
if clk90_int_val2'event and clk90_int_val2 = '1' then
wait_clk90 <= wait_clk270;
end if;
end process;
 
process(clk_int_val2)
begin
if clk_int_val2'event and clk_int_val2 = '1' then
if user_rst = '1' or dcm_lock = '0' or wait_200us_int = '1' then
sys_rst_o <= '1';
sys_rst_1 <= '1';
sys_rst <= '1';
else
sys_rst_o <= '0';
sys_rst_1 <= sys_rst_o;
sys_rst <= sys_rst_1;
end if;
end if;
end process;
 
process(clk90_int_val2)
begin
if clk90_int_val2'event and clk90_int_val2 = '1' then
if user_rst = '1' or dcm_lock = '0' or wait_clk90 = '1' then
sys_rst90_o <= '1';
sys_rst90_1 <= '1';
sys_rst90 <= '1';
else
sys_rst90_o <= '0';
sys_rst90_1 <= sys_rst90_o;
sys_rst90 <= sys_rst90_1;
end if;
end if;
end process;
 
process(clk_int_val2)
begin
if clk_int_val2'event and clk_int_val2 = '0' then
if user_rst = '1' or dcm_lock = '0' or wait_clk270 = '1' then
sys_rst180_o <= '1';
sys_rst180_1 <= '1';
sys_rst180 <= '1';
else
sys_rst180_o <= '0';
sys_rst180_1 <= sys_rst180_o;
sys_rst180 <= sys_rst180_1;
end if;
end if;
end process;
 
clk_dcm0 : DDR2_Ram_Core_clk_dcm
port map (
input_clk => sys_clk_ibuf,
rst => user_rst,
clk => clk_int,
clk90 => clk90_int,
dcm_lock => dcm_lock
);
 
cal_top0 : DDR2_Ram_Core_cal_top
port map (
clk => clk_int_val2,
clk0dcmlock => dcm_lock,
reset => user_cal_rst,
tapfordqs => delay_sel_val1,
dbg_phase_cnt => dbg_phase_cnt,
dbg_cnt => dbg_cnt,
dbg_trans_onedtct => dbg_trans_onedtct,
dbg_trans_twodtct => dbg_trans_twodtct,
dbg_enb_trans_two_dtct => dbg_enb_trans_two_dtct
);
 
end arc;
/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_data_path_0.vhd
0,0 → 1,210
--*****************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.6.1
-- \ \ Application : MIG
-- / / Filename : DDR2_Ram_Core_data_path_0.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
-- Device : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Purpose : This module has the write and read data paths for the
-- DDR2 memory interface. The write data along with write enable
-- signals are forwarded to the DDR IOB FFs. The read data is
-- captured in CLB FFs and finally input to FIFOs.
--*****************************************************************************
 
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use UNISIM.VCOMPONENTS.all;
use work.DDR2_Ram_Core_parameters_0.all;
 
entity DDR2_Ram_Core_data_path_0 is
port(
user_input_data : in std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
user_data_mask : in std_logic_vector((2*DATA_MASK_WIDTH-1) downto 0);
clk : in std_logic;
clk90 : in std_logic;
reset : in std_logic;
reset90 : in std_logic;
write_enable : in std_logic;
rst_dqs_div_in : in std_logic;
delay_sel : in std_logic_vector(4 downto 0);
dqs_int_delay_in : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
dq : in std_logic_vector((DATA_WIDTH-1) downto 0);
u_data_val : out std_logic;
user_output_data : out std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
write_en_val : out std_logic;
data_mask_f : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
data_mask_r : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
write_data_falling : out std_logic_vector((DATA_WIDTH-1) downto 0);
write_data_rising : out std_logic_vector((DATA_WIDTH-1) downto 0);
read_fifo_rden : in std_logic; -- Added new signal
-- debug signals
vio_out_dqs : in std_logic_vector(4 downto 0);
vio_out_dqs_en : in std_logic;
vio_out_rst_dqs_div : in std_logic_vector(4 downto 0);
vio_out_rst_dqs_div_en : in std_logic
);
end DDR2_Ram_Core_data_path_0;
 
architecture arc of DDR2_Ram_Core_data_path_0 is
 
component DDR2_Ram_Core_data_read_0
port(
clk90 : in std_logic;
reset90 : in std_logic;
ddr_dq_in : in std_logic_vector((DATA_WIDTH-1) downto 0);
fifo_0_wr_en : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
fifo_1_wr_en : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
fifo_0_wr_addr : in std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
fifo_1_wr_addr : in std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
dqs_delayed_col0 : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
dqs_delayed_col1 : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
read_fifo_rden : in std_logic;
user_output_data : out std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
u_data_val : out std_logic
 
);
end component;
 
component DDR2_Ram_Core_data_read_controller_0
port(
clk : in std_logic;
reset : in std_logic;
rst_dqs_div_in : in std_logic;
delay_sel : in std_logic_vector(4 downto 0);
dqs_int_delay_in : in std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
fifo_0_wr_en_val : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
fifo_1_wr_en_val : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
fifo_0_wr_addr_val : out std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
fifo_1_wr_addr_val : out std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
dqs_delayed_col0_val : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
dqs_delayed_col1_val : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
vio_out_dqs : in std_logic_vector(4 downto 0);
vio_out_dqs_en : in std_logic;
vio_out_rst_dqs_div : in std_logic_vector(4 downto 0);
vio_out_rst_dqs_div_en : in std_logic
);
end component;
 
component DDR2_Ram_Core_data_write_0
port(
user_input_data : in std_logic_vector(((2*DATA_WIDTH)-1) downto 0);
user_data_mask : in std_logic_vector((2*DATA_MASK_WIDTH-1) downto 0);
clk90 : in std_logic;
write_enable : in std_logic;
write_en_val : out std_logic;
data_mask_f : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
data_mask_r : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
write_data_falling : out std_logic_vector((DATA_WIDTH-1) downto 0);
write_data_rising : out std_logic_vector((DATA_WIDTH-1) downto 0)
);
end component;
 
 
signal fifo0_rd_addr : std_logic_vector(3 downto 0);
signal fifo1_rd_addr : std_logic_vector(3 downto 0);
signal read_valid_data_1 : std_logic;
signal fifo_0_wr_addr : std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
signal fifo_1_wr_addr : std_logic_vector((4*DATA_STROBE_WIDTH)-1 downto 0);
signal fifo_0_wr_en : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
signal fifo_1_wr_en : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
signal dqs_delayed_col0 : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
signal dqs_delayed_col1 : std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
 
begin
 
data_read0 : DDR2_Ram_Core_data_read_0
port map (
clk90 => clk90,
reset90 => reset90,
ddr_dq_in => dq,
fifo_0_wr_en => fifo_0_wr_en,
fifo_1_wr_en => fifo_1_wr_en,
fifo_0_wr_addr => fifo_0_wr_addr,
fifo_1_wr_addr => fifo_1_wr_addr,
dqs_delayed_col0 => dqs_delayed_col0,
dqs_delayed_col1 => dqs_delayed_col1,
read_fifo_rden => read_fifo_rden,
user_output_data => user_output_data,
u_data_val => u_data_val
);
 
data_read_controller0 : DDR2_Ram_Core_data_read_controller_0
port map (
clk => clk,
reset => reset,
rst_dqs_div_in => rst_dqs_div_in,
delay_sel => delay_sel,
dqs_int_delay_in => dqs_int_delay_in,
fifo_0_wr_en_val => fifo_0_wr_en,
fifo_1_wr_en_val => fifo_1_wr_en,
fifo_0_wr_addr_val => fifo_0_wr_addr,
fifo_1_wr_addr_val => fifo_1_wr_addr,
dqs_delayed_col0_val => dqs_delayed_col0,
dqs_delayed_col1_val => dqs_delayed_col1,
vio_out_dqs => vio_out_dqs,
vio_out_dqs_en => vio_out_dqs_en,
vio_out_rst_dqs_div => vio_out_rst_dqs_div,
vio_out_rst_dqs_div_en => vio_out_rst_dqs_div_en
);
 
data_write0 : DDR2_Ram_Core_data_write_0
port map (
user_input_data => user_input_data,
user_data_mask => user_data_mask,
clk90 => clk90,
write_enable => write_enable,
write_en_val => write_en_val,
write_data_falling => write_data_falling,
write_data_rising => write_data_rising,
data_mask_f => data_mask_f,
data_mask_r => data_mask_r
);
 
 
 
end arc;
/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_iobs_0.vhd
0,0 → 1,225
--*****************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.6.1
-- \ \ Application : MIG
-- / / Filename : DDR2_Ram_Core_iobs_0.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
-- Device : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Purpose : This module has the instantiations infrastructure_iobs,
-- data_path_iobs and controller_iobs modules.
--*****************************************************************************
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.DDR2_Ram_Core_parameters_0.all;
 
 
library UNISIM;
use UNISIM.VCOMPONENTS.all;
 
 
entity DDR2_Ram_Core_iobs_0 is
port(
clk : in std_logic;
clk90 : in std_logic;
ddr_rasb_cntrl : in std_logic;
ddr_casb_cntrl : in std_logic;
ddr_web_cntrl : in std_logic;
ddr_cke_cntrl : in std_logic;
ddr_csb_cntrl : in std_logic;
ddr_address_cntrl : in std_logic_vector((ROW_ADDRESS -1) downto 0);
ddr_ba_cntrl : in std_logic_vector((BANK_ADDRESS -1) downto 0);
ddr_odt_cntrl : in std_logic;
rst_dqs_div_int : in std_logic;
dqs_reset : in std_logic;
dqs_enable : in std_logic;
ddr_dqs : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
ddr_dqs_n : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
ddr_dq : inout std_logic_vector((DATA_WIDTH-1) downto 0);
write_data_falling : in std_logic_vector((DATA_WIDTH-1) downto 0);
write_data_rising : in std_logic_vector((DATA_WIDTH-1) downto 0);
write_en_val : in std_logic;
data_mask_f : in std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
data_mask_r : in std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
ddr_odt : out std_logic;
ddr2_ck : out std_logic_vector((CLK_WIDTH-1) downto 0);
ddr2_ck_n : out std_logic_vector((CLK_WIDTH-1) downto 0);
ddr_rasb : out std_logic;
ddr_casb : out std_logic;
ddr_web : out std_logic;
ddr_ba : out std_logic_vector((BANK_ADDRESS -1) downto 0);
ddr_address : out std_logic_vector((ROW_ADDRESS -1) downto 0);
ddr_cke : out std_logic;
ddr_csb : out std_logic;
rst_dqs_div : out std_logic;
rst_dqs_div_in : in std_logic;
rst_dqs_div_out : out std_logic;
dqs_int_delay_in : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
ddr_dm : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
dq : out std_logic_vector((DATA_WIDTH-1) downto 0)
);
end DDR2_Ram_Core_iobs_0;
 
 
architecture arc of DDR2_Ram_Core_iobs_0 is
 
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO : STRING;
 
ATTRIBUTE X_CORE_INFO of arc : ARCHITECTURE IS "mig_v3_61_ddr2_sp3, Coregen 12.4";
ATTRIBUTE CORE_GENERATION_INFO of arc : ARCHITECTURE IS "ddr2_sp3,mig_v3_61,{component_name=ddr2_sp3, data_width=16, memory_width=8, clk_width=1, bank_address=2, row_address=13, column_address=10, no_of_cs=1, cke_width=1, registered=0, data_mask=1, mask_enable=1, load_mode_register=0010100110010, ext_load_mode_register=0000000000000, language=VHDL, synthesis_tool=ISE, interface_type=DDR2_SDRAM, no_of_controllers=1}";
 
component DDR2_Ram_Core_infrastructure_iobs_0
port(
ddr2_ck : out std_logic_vector((CLK_WIDTH-1) downto 0);
ddr2_ck_n : out std_logic_vector((CLK_WIDTH-1) downto 0);
clk0 : in std_logic
);
end component;
 
component DDR2_Ram_Core_controller_iobs_0
port(
clk0 : in std_logic;
ddr_rasb_cntrl : in std_logic;
ddr_casb_cntrl : in std_logic;
ddr_web_cntrl : in std_logic;
ddr_cke_cntrl : in std_logic;
ddr_csb_cntrl : in std_logic;
ddr_address_cntrl : in std_logic_vector((ROW_ADDRESS -1) downto 0);
ddr_ba_cntrl : in std_logic_vector((BANK_ADDRESS -1) downto 0);
ddr_odt_cntrl : in std_logic;
rst_dqs_div_int : in std_logic;
ddr_rasb : out std_logic;
ddr_casb : out std_logic;
ddr_web : out std_logic;
ddr_ba : out std_logic_vector((BANK_ADDRESS -1) downto 0);
ddr_address : out std_logic_vector((ROW_ADDRESS -1) downto 0);
ddr_cke : out std_logic;
ddr_csb : out std_logic;
ddr_ODT : out std_logic;
rst_dqs_div : out std_logic;
rst_dqs_div_in : in std_logic;
rst_dqs_div_out : out std_logic
);
end component;
 
component DDR2_Ram_Core_data_path_iobs_0
port(
clk : in std_logic;
clk90 : in std_logic;
dqs_reset : in std_logic;
dqs_enable : in std_logic;
ddr_dq : inout std_logic_vector((DATA_WIDTH-1) downto 0);
ddr_dqs : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
ddr_dqs_n : inout std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
write_data_falling : in std_logic_vector((DATA_WIDTH-1) downto 0);
write_data_rising : in std_logic_vector((DATA_WIDTH-1) downto 0);
write_en_val : in std_logic;
data_mask_f : in std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
data_mask_r : in std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
dqs_int_delay_in : out std_logic_vector((DATA_STROBE_WIDTH-1) downto 0);
ddr_dm : out std_logic_vector((DATA_MASK_WIDTH-1) downto 0);
ddr_dq_val : out std_logic_vector((DATA_WIDTH-1) downto 0)
);
end component;
 
begin
 
infrastructure_iobs0 : DDR2_Ram_Core_infrastructure_iobs_0
port map (
clk0 => clk,
ddr2_ck => ddr2_ck,
ddr2_ck_n => ddr2_ck_n
);
 
controller_iobs0 : DDR2_Ram_Core_controller_iobs_0
port map (
clk0 => clk,
ddr_rasb_cntrl => ddr_rasb_cntrl,
ddr_casb_cntrl => ddr_casb_cntrl,
ddr_web_cntrl => ddr_web_cntrl,
ddr_cke_cntrl => ddr_cke_cntrl,
ddr_csb_cntrl => ddr_csb_cntrl,
ddr_odt_cntrl => ddr_odt_cntrl,
ddr_address_cntrl => ddr_address_cntrl((ROW_ADDRESS -1) downto 0),
ddr_ba_cntrl => ddr_ba_cntrl((BANK_ADDRESS -1) downto 0),
rst_dqs_div_int => rst_dqs_div_int,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_web => ddr_web,
ddr_ba => ddr_ba((BANK_ADDRESS -1) downto 0),
ddr_address => ddr_address((ROW_ADDRESS -1) downto 0),
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
ddr_odt => ddr_odt,
rst_dqs_div => rst_dqs_div,
rst_dqs_div_in => rst_dqs_div_in,
rst_dqs_div_out => rst_dqs_div_out
);
 
datapath_iobs0 : DDR2_Ram_Core_data_path_iobs_0
port map (
clk => clk,
clk90 => clk90,
dqs_reset => dqs_reset,
dqs_enable => dqs_enable,
ddr_dqs => ddr_dqs,
ddr_dqs_n => ddr_dqs_n,
ddr_dq => ddr_dq,
write_data_falling => write_data_falling,
write_data_rising => write_data_rising,
write_en_val => write_en_val,
data_mask_f => data_mask_f,
data_mask_r => data_mask_r,
dqs_int_delay_in => dqs_int_delay_in,
ddr_dm => ddr_dm,
ddr_dq_val => dq
);
 
end arc;
/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_infrastructure_iobs_0.vhd
0,0 → 1,125
--*****************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.6.1
-- \ \ Application : MIG
-- / / Filename : DDR2_Ram_Core_infrastructure_iobs_0.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
-- Device : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Purpose : This module has the FDDRRSE instantiations to the clocks.
--*****************************************************************************
 
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use UNISIM.VCOMPONENTS.all;
use work.DDR2_Ram_Core_parameters_0.all;
 
entity DDR2_Ram_Core_infrastructure_iobs_0 is
port(
ddr2_ck : out std_logic_vector((CLK_WIDTH-1) downto 0);
ddr2_ck_n : out std_logic_vector((CLK_WIDTH-1) downto 0);
clk0 : in std_logic
);
end DDR2_Ram_Core_infrastructure_iobs_0;
 
architecture arc of DDR2_Ram_Core_infrastructure_iobs_0 is
 
signal ddr2_clk_q : std_logic;
signal vcc : std_logic;
signal gnd : std_logic;
signal clk180 : std_logic;
 
---- **************************************************
---- iob attributes for instantiated FDDRRSE components
---- **************************************************
begin
 
gnd <= '0';
vcc <= '1';
clk180 <= not clk0;
--- ***********************************
---- This includes instantiation of the output DDR flip flop
---- for ddr clk's and dimm clk's
---- ***********************************************************
 
U_clk_i : FDDRRSE
port map (
Q => ddr2_clk_q,
C0 => clk0,
C1 => clk180,
CE => vcc,
D0 => vcc,
D1 => gnd,
R => gnd,
S => gnd
);
 
 
 
---- ******************************************
---- Ouput BUffers for ddr clk's and dimm clk's
---- ******************************************
 
r_inst : OBUFDS
port map (
I => ddr2_clk_q,
O => ddr2_ck(0),
OB => ddr2_ck_n(0)
);
 
 
 
end arc;
/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_fifo_0_wr_en_0.vhd
0,0 → 1,92
--*****************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.6.1
-- \ \ Application : MIG
-- / / Filename : DDR2_Ram_Core_fifo_0_wr_en_0.v
-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
-- Device : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Purpose : This module generate the write enable signal to the fifos,
-- which are driven by negedge of data strobe
--*****************************************************************************
 
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use UNISIM.VCOMPONENTS.all;
 
entity DDR2_Ram_Core_fifo_0_wr_en_0 is
port (
clk : in std_logic;
reset : in std_logic;
din : in std_logic;
rst_dqs_delay_n : out std_logic;
dout : out std_logic
);
 
end DDR2_Ram_Core_fifo_0_wr_en_0;
 
architecture arc of DDR2_Ram_Core_fifo_0_wr_en_0 is
 
signal din_delay : std_ulogic;
signal tie_high : std_ulogic;
begin
 
rst_dqs_delay_n <= not din_delay;
dout <= din or din_delay;
tie_high <= '1';
 
delay_ff : FDCE
port map (
Q => din_delay,
C => clk,
CE => tie_high,
CLR => reset,
D => din
);
 
end arc;
/ipcore_dir/DDR2_Ram_Core/user_design/rtl/DDR2_Ram_Core_fifo_1_wr_en_0.vhd
0,0 → 1,94
--*****************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2005, 2006, 2007 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.6.1
-- \ \ Application : MIG
-- / / Filename : DDR2_Ram_Core_fifo_0_wr_en_0.vhd
-- /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
-- \ \ / \ Date Created : Mon May 2 2005
-- \___\/\___\
-- Device : Spartan-3/3A/3A-DSP
-- Design Name : DDR2 SDRAM
-- Purpose : This module generate the write enable signal to the fifos,
-- which are driven by posedge of data strobe
--*****************************************************************************
 
library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use UNISIM.VCOMPONENTS.all;
 
entity DDR2_Ram_Core_fifo_1_wr_en_0 is
port (
clk : in std_logic;
rst_dqs_delay_n : in std_logic;
reset : in std_logic;
din : in std_logic;
dout : out std_logic
);
end DDR2_Ram_Core_fifo_1_wr_en_0;
 
architecture arc of DDR2_Ram_Core_fifo_1_wr_en_0 is
 
signal din_delay : std_ulogic;
signal tie_high : std_ulogic;
signal dout0 : std_ulogic;
signal rst_dqs_delay : std_logic;
 
begin
 
rst_dqs_delay <= not rst_dqs_delay_n;
dout0 <= din and rst_dqs_delay_n;
dout <= rst_dqs_delay or din_delay;
tie_high <= '1';
 
delay_ff_1 : FDCE
port map (
Q => din_delay,
C => clk,
CE => tie_high,
CLR => reset,
D => dout0
);
 
end arc;
/ipcore_dir/DDR2_Ram_Core/user_design/rtl
ipcore_dir/DDR2_Ram_Core/user_design/rtl Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: ipcore_dir/DDR2_Ram_Core/user_design/par/UB_DDR2_64bit_UCF.ucf =================================================================== --- ipcore_dir/DDR2_Ram_Core/user_design/par/UB_DDR2_64bit_UCF.ucf (nonexistent) +++ ipcore_dir/DDR2_Ram_Core/user_design/par/UB_DDR2_64bit_UCF.ucf (revision 2) @@ -0,0 +1,644 @@ +######################################### +# File : UB_DDR2_64bit_UCF.ucf +# Autor : UB +# +# Constraint-File fuer das externe DDR2-SDRAM +# auf dem Spartan-3A Board (MT47H32M16xx-3) +# +# Size = 64MByte +# +######################################### + +######################################### +# Port-Zuweisungen +######################################### +# +# ---------------------------------------------------- +# -- DDR2 SDRAM-Port-Pins +# ---------------------------------------------------- +# cntrl0_ddr2_a : out std_logic_vector(12 downto 0) := (others => '0'); +# cntrl0_ddr2_ba : out std_logic_vector(1 downto 0) := (others => '0'); +# cntrl0_ddr2_ck : out std_logic_vector(0 downto 0) := (others => '0'); +# cntrl0_ddr2_ck_n : out std_logic_vector(0 downto 0) := (others => '0'); +# cntrl0_ddr2_cke : out std_logic := '0'; +# cntrl0_ddr2_cs_n : out std_logic := '0'; +# cntrl0_ddr2_ras_n : out std_logic := '0'; +# cntrl0_ddr2_cas_n : out std_logic := '0'; +# cntrl0_ddr2_we_n : out std_logic := '0'; +# cntrl0_ddr2_odt : out std_logic := '0'; +# cntrl0_ddr2_dm : out std_logic_vector(1 downto 0) := (others => '0'); +# cntrl0_ddr2_dqs_n : inout std_logic_vector(1 downto 0) := (others => '0'); +# cntrl0_ddr2_dqs : inout std_logic_vector(1 downto 0) := (others => '0'); +# cntrl0_ddr2_dq : inout std_logic_vector(15 downto 0) := (others => '0'); +# cntrl0_rst_dqs_div_in : in std_logic; +# cntrl0_rst_dqs_div_out : out std_logic +# ---------------------------------------------------- +# +######################################### + +##################################################################################################################### +## Clock constraints +##################################################################################################################### +NET "INST_DDR2_RAM_CORE/infrastructure_top0/sys_clk_ibuf" TNM_NET = "SYS_CLK"; +TIMESPEC "TS_SYS_CLK" = PERIOD "SYS_CLK" 7.5187 ns HIGH 50 %; + +####################################################################################################################### +## Calibration Circuit Constraints +####################################################################################################################### +## Placement constraints for LUTS in tap delay ckt +####################################################################################################################### + + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l0" RLOC=X0Y6; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l0" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l1" RLOC=X0Y6; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l1" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l2" RLOC=X0Y7; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l2" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l3" RLOC=X0Y7; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l3" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l4" RLOC=X1Y6; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l4" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l5" RLOC=X1Y6; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l5" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l6" RLOC=X1Y7; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l6" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l7" RLOC=X1Y7; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l7" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l8" RLOC=X0Y4; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l8" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l9" RLOC=X0Y4; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l9" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l10" RLOC=X0Y5; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l10" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l11" RLOC=X0Y5; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l11" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l12" RLOC=X1Y4; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l12" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l13" RLOC=X1Y4; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l13" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l14" RLOC=X1Y5; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l14" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l15" RLOC=X1Y5; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l15" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l16" RLOC=X0Y2; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l16" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l17" RLOC=X0Y2; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l17" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l18" RLOC=X0Y3; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l18" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l19" RLOC=X0Y3; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l19" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l20" RLOC=X1Y2; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l20" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l21" RLOC=X1Y2; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l21" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l22" RLOC=X1Y3; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l22" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l23" RLOC=X1Y3; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l23" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l24" RLOC=X0Y0; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l24" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l25" RLOC=X0Y0; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l25" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l26" RLOC=X0Y1; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l26" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l27" RLOC=X0Y1; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l27" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l28" RLOC=X1Y0; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l28" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l29" RLOC=X1Y0; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l29" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l30" RLOC=X1Y1; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l30" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l31" RLOC=X1Y1; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l31" U_SET = delay_calibration_chain; + +####################################################################################################################### +# Placement constraints for first stage flops in tap delay ckt # +####################################################################################################################### + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[0].r" RLOC=X0Y6; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[0].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[1].r" RLOC=X0Y6; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[1].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[2].r" RLOC=X0Y7; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[2].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[3].r" RLOC=X0Y7; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[3].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[4].r" RLOC=X1Y6; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[4].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[5].r" RLOC=X1Y6; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[5].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[6].r" RLOC=X1Y7; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[6].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[7].r" RLOC=X1Y7; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[7].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[8].r" RLOC=X0Y4; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[8].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[9].r" RLOC=X0Y4; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[9].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[10].r" RLOC=X0Y5; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[10].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[11].r" RLOC=X0Y5; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[11].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[12].r" RLOC=X1Y4; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[12].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[13].r" RLOC=X1Y4; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[13].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[14].r" RLOC=X1Y5; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[14].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[15].r" RLOC=X1Y5; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[15].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[16].r" RLOC=X0Y2; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[16].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[17].r" RLOC=X0Y2; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[17].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[18].r" RLOC=X0Y3; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[18].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[19].r" RLOC=X0Y3; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[19].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[20].r" RLOC=X1Y2; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[20].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[21].r" RLOC=X1Y2; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[21].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[22].r" RLOC=X1Y3; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[22].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[23].r" RLOC=X1Y3; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[23].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[24].r" RLOC=X0Y0; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[24].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[25].r" RLOC=X0Y0; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[25].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[26].r" RLOC=X0Y1; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[26].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[27].r" RLOC=X0Y1; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[27].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[28].r" RLOC=X1Y0; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[28].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[29].r" RLOC=X1Y0; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[29].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[30].r" RLOC=X1Y1; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[30].r" U_SET = delay_calibration_chain; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[31].r" RLOC=X1Y1; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/gen_tap1[31].r" U_SET = delay_calibration_chain; + +####################################################################################################################### +## BEL constraints for LUTS in tap delay ckt +####################################################################################################################### + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l0" BEL= G; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l1" BEL= F; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l2" BEL= G; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l3" BEL= F; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l4" BEL= G; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l5" BEL= F; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l6" BEL= G; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l7" BEL= F; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l8" BEL= G; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l9" BEL= F; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l10" BEL= G; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l11" BEL= F; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l12" BEL= G; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l13" BEL= F; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l14" BEL= G; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l15" BEL= F; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l16" BEL= G; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l17" BEL= F; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l18" BEL= G; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l19" BEL= F; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l20" BEL= G; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l21" BEL= F; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l22" BEL= G; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l23" BEL= F; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l24" BEL= G; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l25" BEL= F; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l26" BEL= G; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l27" BEL= F; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l28" BEL= G; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l29" BEL= F; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l30" BEL= G; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l31" BEL= F; + +############################################################################################################## +## Area Group Constraint For tap_dly and cal_ctl module. +############################################################################################################## +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/l0" RLOC_ORIGIN=X28Y16; + +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/cal_ctl0/*" AREA_GROUP = cal_ctl; +INST "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/*" AREA_GROUP = cal_ctl; +AREA_GROUP "cal_ctl" RANGE = SLICE_X26Y8:SLICE_X37Y21; +AREA_GROUP "cal_ctl" GROUP = CLOSED; +################################################################################################################ +#**************************************************************************************************************# +# CONTROLLER 0 # +#**************************************************************************************************************# +################################################################################################################ +# I/O STANDARDS +################################################################################################################ +#NET "sys_clk_in" IOSTANDARD = LVCMOS33; +NET "cntrl0_ddr2_a[*]" IOSTANDARD = SSTL18_I; +NET "cntrl0_ddr2_ba[*]" IOSTANDARD = SSTL18_I; +NET "cntrl0_ddr2_ck[*]" IOSTANDARD = DIFF_SSTL18_I; +NET "cntrl0_ddr2_ck_n[*]" IOSTANDARD = DIFF_SSTL18_I; +NET "cntrl0_ddr2_cke" IOSTANDARD = SSTL18_I; +NET "cntrl0_ddr2_cs_n" IOSTANDARD = SSTL18_I; +NET "cntrl0_ddr2_ras_n" IOSTANDARD = SSTL18_I; +NET "cntrl0_ddr2_cas_n" IOSTANDARD = SSTL18_I; +NET "cntrl0_ddr2_we_n" IOSTANDARD = SSTL18_I; +NET "cntrl0_ddr2_odt" IOSTANDARD = SSTL18_I; +NET "cntrl0_ddr2_dm[*]" IOSTANDARD = SSTL18_I; +NET "cntrl0_rst_dqs_div_in" IOSTANDARD = SSTL18_I; +NET "cntrl0_rst_dqs_div_out" IOSTANDARD = SSTL18_I; +NET "cntrl0_ddr2_dq[*]" IOSTANDARD = SSTL18_I; +NET "cntrl0_ddr2_dqs[*]" IOSTANDARD = DIFF_SSTL18_I; +NET "cntrl0_ddr2_dqs_n[*]" IOSTANDARD = DIFF_SSTL18_I; + +#################################################################################################################### +# Banks 2 +# Pin Location Constraints for System clock signals +#################################################################################################################### +#NET "sys_clk_in" LOC = "V12"; # on board clock +#NET "sys_clk_in" LOC = "U12"; #external clock + +#################################################################################################################### +# Banks 3 +# Pin Location Constraints for Clock,Masks, Address, and Controls + #################################################################################################################### +NET "cntrl0_ddr2_ck[0]" LOC = "M1" ; +NET "cntrl0_ddr2_ck_n[0]" LOC = "M2" ; +NET "cntrl0_ddr2_dm[0]" LOC = "J3" ; +NET "cntrl0_ddr2_dm[1]" LOC = "E3" ; +NET "cntrl0_ddr2_a[0]" LOC = "R2" ; +NET "cntrl0_ddr2_a[1]" LOC = "T4" ; +NET "cntrl0_ddr2_a[2]" LOC = "R1" ; +NET "cntrl0_ddr2_a[3]" LOC = "U3" ; +NET "cntrl0_ddr2_a[4]" LOC = "U2" ; +NET "cntrl0_ddr2_a[5]" LOC = "U4" ; +NET "cntrl0_ddr2_a[6]" LOC = "U1" ; +NET "cntrl0_ddr2_a[7]" LOC = "Y1" ; +NET "cntrl0_ddr2_a[8]" LOC = "W1" ; +NET "cntrl0_ddr2_a[9]" LOC = "W2" ; +NET "cntrl0_ddr2_a[10]" LOC = "T3" ; +NET "cntrl0_ddr2_a[11]" LOC = "V1" ; +NET "cntrl0_ddr2_a[12]" LOC = "Y2" ; +NET "cntrl0_ddr2_ba[0]" LOC = "P3" ; +NET "cntrl0_ddr2_ba[1]" LOC = "R3" ; +NET "cntrl0_ddr2_cke" LOC = "N3" ; +NET "cntrl0_ddr2_cs_n" LOC = "M5" ; +NET "cntrl0_ddr2_ras_n" LOC = "M3" ; +NET "cntrl0_ddr2_cas_n" LOC = "M4" ; +NET "cntrl0_ddr2_we_n" LOC = "N4" ; +NET "cntrl0_ddr2_odt" LOC = "P1" ; + +#NET "reset_in_n" LOC = "T15" | IOSTANDARD = LVTTL | PULLDOWN ; +#NET "cntrl0_led_error_output1" LOC = "R20" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = QUIETIO | PULLDOWN ; +#NET "cntrl0_data_valid_out" LOC = "T19" | IOSTANDARD = LVTTL; +#NET "cntrl0_init_done" LOC = "V16" | IOSTANDARD = LVTTL; + + +############################################################################################################## +## MAXDELAY constraints +############################################################################################################## + +############################################################################################################## +## Constraint to have the tap delay inverter connection wire length to be the same and minimum to get +## accurate calibration of tap delays. The following constraints are independent of frequency. +############################################################################################################## +NET "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/tap[7]" MAXDELAY = 400ps; +NET "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/tap[15]" MAXDELAY = 400ps; +NET "INST_DDR2_RAM_CORE/infrastructure_top0/cal_top0/tap_dly0/tap[23]" MAXDELAY = 400ps; + +############################################################################################################## +## MAXDELAY constraint on inter LUT delay elements. This constraint is required to minimize the +## wire delays between the LUTs. +############################################################################################################## +NET "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay*dqs_delay_col*/delay*" MAXDELAY = 190 ps; +NET "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/delay*" MAXDELAY = 200 ps; + +############################################################################################################## +## Constraint from the dqs PAD to input of LUT delay element. +############################################################################################################## +NET "INST_DDR2_RAM_CORE/top_00/dqs_int_delay_in*" MAXDELAY = 580 ps; + +############################################################################################################## +## Constraint from rst_dqs_div_in PAD to input of LUT delay element. +############################################################################################################## +NET "INST_DDR2_RAM_CORE/top_00/dqs_div_rst" MAXDELAY = 460 ps; + +############################################################################################################## +## Following are the MAXDELAY constraints on delayed rst_dqs_div net and fifo write enable signals. +## These constraints are required since these paths are not covered by timing analysis. The requirement is total +## delay on delayed rst_dqs_div and fifo_wr_en nets should not exceed the clock period. +############################################################################################################## +NET "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/rst_dqs_div" MAXDELAY = 3007 ps; +NET "INST_DDR2_RAM_CORE/top_00/data_path0/fifo*_wr_en*" MAXDELAY = 3007 ps; + +############################################################################################################## +## The MAXDELAY value on fifo write address should be less than clock period. This constraint is +## required since this path is not covered by timing analysis. +############################################################################################################## +NET "INST_DDR2_RAM_CORE/top_00/data_path0/fifo*_wr_addr*" MAXDELAY = 6390 ps; + + + + + +############################################################################################################## +## constraints for bit cntrl0_ddr2_dq, 1, location in tile: 0 +############################################################################################################## +NET "cntrl0_ddr2_dq[1]" LOC = K5; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit1" LOC = SLICE_X0Y58; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit1" LOC = SLICE_X0Y59; +############################################################################################################## +## constraints for bit cntrl0_ddr2_dq, 0, location in tile: 0 +############################################################################################################## +NET "cntrl0_ddr2_dq[0]" LOC = H1; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit0" LOC = SLICE_X2Y62; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit0" LOC = SLICE_X2Y63; +############################################################################################################## +## constraints for bit cntrl0_ddr2_dq, 3, location in tile: 0 +############################################################################################################## +NET "cntrl0_ddr2_dq[3]" LOC = L3; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit3" LOC = SLICE_X2Y52; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit3" LOC = SLICE_X2Y53; +############################################################################################################## +## constraints for bit cntrl0_ddr2_dq, 2, location in tile: 0 +############################################################################################################## +NET "cntrl0_ddr2_dq[2]" LOC = K1; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit2" LOC = SLICE_X0Y50; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit2" LOC = SLICE_X0Y51; +############################################################################################################## +## constraints for bit cntrl0_ddr2_dqs, 0, location in tile: 0 +############################################################################################################## +NET "cntrl0_ddr2_dqs[0]" LOC = K3; +############################################################################################################## +## constraints for bit cntrl0_ddr2_dqs_n, 0, location in tile: 0 +############################################################################################################## +############################################################# +NET "cntrl0_ddr2_dqs_n[0]" LOC = K2; + +############################################################################################################## +## LUT location constraints for dqs_delayed_col0 +############################################################################################################## +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/one" LOC = SLICE_X2Y55; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/one" BEL = F; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/two" LOC = SLICE_X2Y55; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/two" BEL = G; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/three" LOC = SLICE_X2Y54; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/three" BEL = G; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/four" LOC = SLICE_X2Y54; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/four" BEL = F; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/five" LOC = SLICE_X3Y55; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/five" BEL = G; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/six" LOC = SLICE_X3Y54; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col0/six" BEL = G; + +############################################################################################################## +## LUT location constraints for dqs_delayed_col1 +############################################################################################################## +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/one" LOC = SLICE_X0Y55; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/one" BEL = F; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/two" LOC = SLICE_X0Y55; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/two" BEL = G; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/three" LOC = SLICE_X0Y54; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/three" BEL = G; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/four" LOC = SLICE_X0Y54; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/four" BEL = F; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/five" LOC = SLICE_X1Y55; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/five" BEL = G; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/six" LOC = SLICE_X1Y54; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[0].dqs_delay_col1/six" BEL = G; + +############################################################################################################## +## Slice location constraints for Fifo write address and write enable +############################################################################################################## +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit0" LOC = SLICE_X1Y50; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit1" LOC = SLICE_X1Y50; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit2" LOC = SLICE_X1Y49; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_0_wr_addr_inst/bit3" LOC = SLICE_X1Y49; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit0" LOC = SLICE_X3Y49; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit1" LOC = SLICE_X3Y49; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit2" LOC = SLICE_X3Y50; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[0].fifo_1_wr_addr_inst/bit3" LOC = SLICE_X3Y50; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_0_wr_en_inst/delay_ff" LOC = SLICE_X1Y53; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_en[0].fifo_1_wr_en_inst/delay_ff_1" LOC = SLICE_X3Y53; +############################################################################################################## +## constraints for bit cntrl0_ddr2_dq, 5, location in tile: 0 +############################################################################################################## +NET "cntrl0_ddr2_dq[5]" LOC = L1; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit5" LOC = SLICE_X2Y50; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit5" LOC = SLICE_X2Y51; +############################################################################################################## +## constraints for bit cntrl0_ddr2_dq, 4, location in tile: 0 +############################################################################################################## +NET "cntrl0_ddr2_dq[4]" LOC = L5; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit4" LOC = SLICE_X0Y52; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit4" LOC = SLICE_X0Y53; +############################################################################################################## +## constraints for bit cntrl0_ddr2_dq, 7, location in tile: 0 +############################################################################################################## +NET "cntrl0_ddr2_dq[7]" LOC = H2; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit7" LOC = SLICE_X0Y62; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit7" LOC = SLICE_X0Y63; +############################################################################################################## +## constraints for bit cntrl0_ddr2_dq, 6, location in tile: 0 +############################################################################################################## +NET "cntrl0_ddr2_dq[6]" LOC = K4; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe/fifo_bit6" LOC = SLICE_X2Y58; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[0].strobe_n/fifo_bit6" LOC = SLICE_X2Y59; + + +############################################################################################################## +## constraints for bit cntrl0_ddr2_dq, 9, location in tile: 0 +############################################################################################################## +NET "cntrl0_ddr2_dq[9]" LOC = G4; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit1" LOC = SLICE_X2Y78; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit1" LOC = SLICE_X2Y79; +############################################################################################################## +## constraints for bit cntrl0_ddr2_dq, 8, location in tile: 0 +############################################################################################################## +NET "cntrl0_ddr2_dq[8]" LOC = F2; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit0" LOC = SLICE_X0Y70; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit0" LOC = SLICE_X0Y71; +############################################################################################################## +## constraints for bit cntrl0_ddr2_dq, 11, location in tile: 0 +############################################################################################################## +NET "cntrl0_ddr2_dq[11]" LOC = H6; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit3" LOC = SLICE_X2Y76; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit3" LOC = SLICE_X2Y77; +############################################################################################################## +## constraints for bit cntrl0_ddr2_dq, 10, location in tile: 0 +############################################################################################################## +NET "cntrl0_ddr2_dq[10]" LOC = G1; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit2" LOC = SLICE_X2Y68; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit2" LOC = SLICE_X2Y69; +############################################################################################################## +## constraints for bit cntrl0_ddr2_dqs, 1, location in tile: 0 +############################################################################################################## +NET "cntrl0_ddr2_dqs[1]" LOC = K6; +############################################################################################################## +## constraints for bit cntrl0_ddr2_dqs_n, 1, location in tile: 0 +############################################################################################################## +############################################################# +NET "cntrl0_ddr2_dqs_n[1]" LOC = J5; + +############################################################################################################## +## LUT location constraints for dqs_delayed_col0 +############################################################################################################## +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/one" LOC = SLICE_X2Y75; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/one" BEL = F; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/two" LOC = SLICE_X2Y75; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/two" BEL = G; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/three" LOC = SLICE_X2Y74; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/three" BEL = G; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/four" LOC = SLICE_X2Y74; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/four" BEL = F; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/five" LOC = SLICE_X3Y75; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/five" BEL = G; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/six" LOC = SLICE_X3Y74; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col0/six" BEL = G; + +############################################################################################################## +## LUT location constraints for dqs_delayed_col1 +############################################################################################################## +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/one" LOC = SLICE_X0Y75; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/one" BEL = F; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/two" LOC = SLICE_X0Y75; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/two" BEL = G; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/three" LOC = SLICE_X0Y74; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/three" BEL = G; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/four" LOC = SLICE_X0Y74; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/four" BEL = F; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/five" LOC = SLICE_X1Y75; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/five" BEL = G; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/six" LOC = SLICE_X1Y74; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_delay[1].dqs_delay_col1/six" BEL = G; + +############################################################################################################## +## Slice location constraints for Fifo write address and write enable +############################################################################################################## +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit0" LOC = SLICE_X1Y69; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit1" LOC = SLICE_X1Y69; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit2" LOC = SLICE_X1Y70; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_0_wr_addr_inst/bit3" LOC = SLICE_X1Y70; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit0" LOC = SLICE_X3Y69; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit1" LOC = SLICE_X3Y69; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit2" LOC = SLICE_X3Y70; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_addr[1].fifo_1_wr_addr_inst/bit3" LOC = SLICE_X3Y70; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_en[1].fifo_0_wr_en_inst/delay_ff" LOC = SLICE_X1Y72; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/gen_wr_en[1].fifo_1_wr_en_inst/delay_ff_1" LOC = SLICE_X3Y72; +############################################################################################################## +## constraints for bit cntrl0_ddr2_dq, 13, location in tile: 0 +############################################################################################################## +NET "cntrl0_ddr2_dq[13]" LOC = F1; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit5" LOC = SLICE_X2Y70; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit5" LOC = SLICE_X2Y71; +############################################################################################################## +## constraints for bit cntrl0_ddr2_dq, 12, location in tile: 0 +############################################################################################################## +NET "cntrl0_ddr2_dq[12]" LOC = H5; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit4" LOC = SLICE_X0Y76; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit4" LOC = SLICE_X0Y77; +############################################################################################################## +## constraints for bit cntrl0_ddr2_dq, 15, location in tile: 0 +############################################################################################################## +NET "cntrl0_ddr2_dq[15]" LOC = F3; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit7" LOC = SLICE_X0Y78; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit7" LOC = SLICE_X0Y79; +############################################################################################################## +## constraints for bit cntrl0_ddr2_dq, 14, location in tile: 0 +############################################################################################################## +NET "cntrl0_ddr2_dq[14]" LOC = G3; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe/fifo_bit6" LOC = SLICE_X0Y68; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read0/gen_strobe[1].strobe_n/fifo_bit6" LOC = SLICE_X0Y69; + +############################################################################################################## +## constraints for bit cntrl0_rst_dqs_div_in, 1, location in tile: 1 +############################################################################################################## +NET "cntrl0_rst_dqs_div_in" LOC = H4; + +############################################################################################################## +## Slice location constraints for delayed rst_dqs_div signal +############################################################################################################## +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/one" LOC = SLICE_X0Y67; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/one" BEL = F; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/two" LOC = SLICE_X0Y66; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/two" BEL = F; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/three" LOC = SLICE_X0Y67; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/three" BEL = G; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/four" LOC = SLICE_X1Y66; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/four" BEL = F; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/five" LOC = SLICE_X1Y66; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/five" BEL = G; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/six" LOC = SLICE_X1Y67; +INST "INST_DDR2_RAM_CORE/top_00/data_path0/data_read_controller0/rst_dqs_div_delayed/six" BEL = G; + +############################################################################################################## +## constraints for bit cntrl0_rst_dqs_div_out, 1, location in tile: 0 +############################################################################################################## +NET "cntrl0_rst_dqs_div_out" LOC = H3; +################################################################################# +INST "INST_DDR2_RAM_CORE/top_00/controller0/rst_dqs_div_r" LOC = SLICE_X4Y66; Index: ipcore_dir/DDR2_Ram_Core/user_design/par =================================================================== --- ipcore_dir/DDR2_Ram_Core/user_design/par (nonexistent) +++ ipcore_dir/DDR2_Ram_Core/user_design/par (revision 2)
ipcore_dir/DDR2_Ram_Core/user_design/par Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: ipcore_dir/DDR2_Ram_Core/user_design =================================================================== --- ipcore_dir/DDR2_Ram_Core/user_design (nonexistent) +++ ipcore_dir/DDR2_Ram_Core/user_design (revision 2)
ipcore_dir/DDR2_Ram_Core/user_design Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: ipcore_dir/DDR2_Ram_Core =================================================================== --- ipcore_dir/DDR2_Ram_Core (nonexistent) +++ ipcore_dir/DDR2_Ram_Core (revision 2)
ipcore_dir/DDR2_Ram_Core Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: ipcore_dir =================================================================== --- ipcore_dir (nonexistent) +++ ipcore_dir (revision 2)
ipcore_dir Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: Prj_12_DDR2.xise =================================================================== --- Prj_12_DDR2.xise (nonexistent) +++ Prj_12_DDR2.xise (revision 2) @@ -0,0 +1,480 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: impact.xsl =================================================================== --- impact.xsl (nonexistent) +++ impact.xsl (revision 2) @@ -0,0 +1,55 @@ + + + + + + + Current iMPACT Usage Statistics. +

+ Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. + +

+

+ This page displays the current iMPACT device usage statistics that will be sent to Xilinx using WebTalk. + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + + + Index: DDR2_Read_VHDL.vhd =================================================================== --- DDR2_Read_VHDL.vhd (nonexistent) +++ DDR2_Read_VHDL.vhd (revision 2) @@ -0,0 +1,226 @@ +--------------------------------------------------------------------- +-- File : DDR2_Read_VHDL.vhd +-- Projekt : Prj_12_DDR2 +-- Zweck : DDR2-Read-Funktion +-- Datum : 19.08.2011 +-- Version : 2.0 +-- Plattform : XILINX Spartan-3A +-- FPGA : XC3S700A-FGG484 +-- Sprache : VHDL +-- ISE : ISE-Design-Suite V:13.1 +-- Autor : UB +-- Mail : Becker_U(at)gmx.de +--------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + -------------------------------------------- + -- Beschreibung : + -- + -- Die State-Machine liest + -- einen 64Bit Wert aus dem RAM + -- von 4 aufeinander folgenden 16bit-Zellen + -- + -- die Adresse wird + -- von der übergeordneten CONTROL-Unit + -- gehandelt + -- + -- solange die Read-Funktion läuft, + -- ist READ_BUSY=1 + -------------------------------------------- + +entity DDR2_Read_VHDL is + + -------------------------------------------- + -- Port Deklerationen + -------------------------------------------- + port ( + reset_in : in std_logic; + clk_in : in std_logic; + clk90_in : in std_logic; + r_command_register : out std_logic_vector(2 downto 0); + r_cmd_ack : in std_logic; + r_burst_done : out std_logic; + r_data_valid : in std_logic; + read_en : in std_logic; + read_busy : out std_logic; + output_data : in std_logic_vector(31 downto 0); + read_data : out std_logic_vector(63 downto 0) + ); + +end DDR2_Read_VHDL; + +architecture Verhalten of DDR2_Read_VHDL is + + -------------------------------------------- + -- Interne Signale + -------------------------------------------- + + signal v_data_lsb : std_logic_vector(31 downto 0):=(others => '0'); + signal v_data_msb : std_logic_vector(31 downto 0):=(others => '0'); + + constant CLK_ANZ : integer := 1; -- warte 2 Clockzyklen (1 bis 0 = 2) + signal v_counter : natural range 0 to CLK_ANZ := CLK_ANZ; + + type STATE_RA_TYPE is ( + RA_1_NOP, + RA_2_WAIT_4_ACK1, + RA_3_WAIT_CLK, + RA_4_SET_BURST, + RA_5_SET_NOP, + RA_6_WAIT_4_ACK0 + ); + signal STATE_RA : STATE_RA_TYPE := RA_1_NOP; + + type STATE_RB_TYPE is ( + RB_1_NOP, + RB_2_WAIT_4_VALID1, + RB_3_DATA_MSB, + RB_4_WAIT_4_ACK0 + ); + signal STATE_RB : STATE_RB_TYPE := RB_1_NOP; + +begin + + ----------------------------------------- + -- State-Machine RA : (Clock-0 Lo-Flanke) + -- 1. wartet auf das READ_EN=1 von der DDR2_Control + -- 2. sendet das READ-Kommando an das RAM + -- 3. wartet auf das ACK=1 vom RAM + -- 4. wartet 2 Clockzyklen + -- (solange dauert das lesen von 64Bit) + -- 5. legt das BURST_DONE-Signal für 2 Clockzyklen an + -- 6. wartet auf das ACK=0 vom RAM + -- 7. Sprung zu Punkt 1 + ----------------------------------------- + P_Read_RA : process(clk_in,reset_in) + begin + if reset_in = '1' then + r_burst_done <= '0'; + r_command_register <= "000"; + STATE_RA <= RA_1_NOP; + elsif falling_edge(clk_in) then + -- Default Stellungen + r_burst_done <= '0'; + r_command_register <= "000"; + -- State-Machine + case STATE_RA is + when RA_1_NOP => + -- warten auf read enable signal + v_counter <= CLK_ANZ; + if read_en = '1' then + -- read enable wurde erkannt + STATE_RA <= RA_2_WAIT_4_ACK1; + end if; + when RA_2_WAIT_4_ACK1 => + -- READ-CMD anlegen + -- warten auf ACK=1 signal + r_command_register <= "110"; + if r_cmd_ack = '1' then + -- ack-signal wurde erkannt + STATE_RA <= RA_3_WAIT_CLK; + end if; + when RA_3_WAIT_CLK => + -- warte ein paar Clockzyklen + r_command_register <= "110"; + if v_counter = 0 then + STATE_RA <= RA_4_SET_BURST; + else + v_counter <= v_counter - 1; + end if; + when RA_4_SET_BURST => + r_command_register <= "110"; + r_burst_done <= '1'; + STATE_RA <= RA_5_SET_NOP; + when RA_5_SET_NOP => + -- NOP-CMD anlegen + -- bei Burst_Done=Hi + r_burst_done <= '1'; + STATE_RA <= RA_6_WAIT_4_ACK0; + when RA_6_WAIT_4_ACK0 => + -- burst_done auf Lo + -- warten auf ACK=0 signal + if r_cmd_ack = '0' then + -- ack-signal wurde erkannt + STATE_RA <= RA_1_NOP; + end if; + when others => + NULL; + end case; + end if; + end process P_Read_RA; + + ----------------------------------------- + -- State-Machine RB : (Clock-90 Hi-Flanke) + -- 1. wartet bis State-Machine-RA das + -- READ-Kommando gesendet hat + -- 2. warte auf das DATA_VALID=1 vom RAM + -- 3. liest die LSB-Daten (32Bit) vom RAM + -- 4. wartet einen Clockzyklus + -- 5. liest die MSB-Daten (32Bit) vom RAM + -- 6. wartet auf das ACK=0 vom RAM + -- 7. Sprung zu Punkt 1 + ----------------------------------------- + P_Read_RB : process(clk90_in,reset_in) + begin + if reset_in = '1' then + -- reset button ist gedrueckt + v_data_lsb <= (others => '0'); + v_data_msb <= (others => '0'); + STATE_RB <= RB_1_NOP; + elsif rising_edge(clk90_in) then + case STATE_RB is + when RB_1_NOP => + -- warten bis Read enable + if STATE_RA = RA_2_WAIT_4_ACK1 then + -- ack-signal wurde erkannt + STATE_RB <= RB_2_WAIT_4_VALID1; + end if; + when RB_2_WAIT_4_VALID1 => + -- warte bis Daten Valid sind + if r_data_valid = '1' then + -- LSB Daten sind ok + v_data_lsb <= output_data; + STATE_RB <= RB_3_DATA_MSB; + else + v_data_lsb <= v_data_lsb; + end if; + when RB_3_DATA_MSB => + -- MSB Daten lesen + if r_data_valid = '1' then + -- MSB Daten sind ok + v_data_msb <= output_data; + else + v_data_msb <= v_data_msb; + end if; + STATE_RB <= RB_4_WAIT_4_ACK0; + when RB_4_WAIT_4_ACK0 => + -- warten auf ACK=0 vom RAM + if r_cmd_ack = '0' then + -- ack-signal wurde erkannt + STATE_RB <= RB_1_NOP; + end if; + when others => + NULL; + end case; + end if; + end process P_Read_RB; + + + ----------------------------------------- + -- Read-Busy erzeugen : + -- solange der Read-Prozess im Gange + -- ist READ_BUSY = 1 + ----------------------------------------- + read_busy <= '0' when STATE_RA=RA_1_NOP else '1'; + + ----------------------------------------- + -- Read-Data uebergeben : + -- 64Bit zusammengesetzt aus MSB & LSB + ----------------------------------------- + read_data <= v_data_msb & v_data_lsb; + +end Verhalten; + Index: webtalk_impact.xml =================================================================== --- webtalk_impact.xml (nonexistent) +++ webtalk_impact.xml (revision 2) @@ -0,0 +1,43 @@ + + + + +
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+
+ + + + + + + + + + + + + + + + + + + + + +
+ + Index: DDR2_liesmich.txt =================================================================== --- DDR2_liesmich.txt (nonexistent) +++ DDR2_liesmich.txt (revision 2) @@ -0,0 +1,245 @@ +============================================== +File : DDR2_liesmich.txt +Projekt : Prj_12_DDR2 +Zweck : DDR2-SDRAM auf dem Spartan-3A Board +DDR2-RAM : MT47H32M16 (64 MByte) +Datum: 19.08.2011 +Version : 7.0 +Plattform : XILINX Spartan-3A +FPGA : XC3S700A-FGG484 +Sprache : VHDL +ISE : ISE-Design-Suite V:13.1 +IP-Core : MIG V:3.6.1 +Autor : UB +Mail : Becker_U(at)gmx.de +============================================== + + + +Module : +================== + + ############### ######################### ################ + # # # # # # + # DDR2-RAM : #---------# TOP_Modul_VHDL #----# Buttons_VHDL # + # 512 MBit # # # # # + # # # # ################ + ############### # # + # # ################ + # # # # + # #----# Clock_VHDL # + # # # # + # # ################ + # # + ############### # # ##################### ################### + # # # # # # # # + # Eingabe : # # # # DDR2_Control_VHDL #----# DDR2_READ_VHDL # + # 4 Buttons #---------# # # # # # + # 4 Schalter # # #----# # ################### + # # # # # # + ############### # # # # ################### + # # # # # # + ################### # # # #----# DDR2_Write_VHDL # + # # # # # # # # + # Ausgabe : #-----# # # # ################### + # 8 LEDs (Data) # # # ##################### + # 1 LED (Status) # # # + ################### # # ####################### + # #----# # + ############### # # # DDR2_RAM_CORE.vhd # + # Clock : #---------# # # MIG 3.6.1 # + # 133 MHz # # # # (27 Dateien) # + # # # # # + UCF-File # + ############### ######################### ####################### + + + +Zweck : +======== + +> Dieses Projekt ist ein Beispiel wie ein DDR2-SDRAM auf einem Xilinx FPGA Board + eingebunden wird + + + +Hinweise zur DDR2-RAM-Einbindung : +=================================== + +> das ganze Projekt basiert auf der Einbindung der vom MIG + generierten Files für ein DDR2-SDRAM (MIG 3.6.1) + +> Hinweis zu den Einstellungen vom MIG : + - Typ = DDR2-SDRAM + - Frq = 133MHz + - Write Pipe Stages = 4 + - Memory Part = MT47H32M16XX-3 (für das Spartan-3A Board) + - Data Width = 16 + - Data-Mask = Ja + - SystemClock = Single-Ended + - Signale auf : Bank3 (komplett) , Bank2 (V12) + - Bank2 = System-Clock / Bank3 = Adrees-Control+Data+System-Control + - sonst alles auf "Default" + +> Hinweise zum DDR2_RAM_CORE : + + - es wurden nur die VHDL-Files + vom Ordner "User_Design/RTL" benutzt. + - alle anderen vom MIG generierten Files + sind für das Projekt nicht notwendig + +> Hinweis zum UCF-File für das DDR2-RAM : + + - ohne die Richtigen Settings im UCF-File, + kommt es zu Timing problemen beim lesen oder + schreiben + - das vom MIG generierte UCF muss auf die + Pinbelegung vom Spartan-3A Board angepasst + werden + - aus dem Grund habe ich das UCF-File + aus dem Xilinx-Example für Spartan-3A Boards + benutzt und für das Projekt angepasst + das DDR2-Example bekommt man durch einen Link + vom MIG -> "Xilinx Reference Boards" unter + "http://www.xilinx.com/products/boards/s3astarter/reference_designs.htm" + der Name ist "DDR2 MIG Reference Design" + + +Beschreibung der Funktion : +============================ + +> der Schalter-0 (SW0) dient als Reset-Schalter (High = Reset) + +> das "TOP_Modul" routet alle Signale zwischen den Modulen + +> die "Buttons_VHDL" dient nur zum entprellen der Tasten und zum erzeugen + eines "On-Click-Events" damit die Read/Write-Funktionen nur + einmal gestartet werden + +> das "DDR2_Control" enthaellt eine State-Machine mit folgenden Funktionen : + + 1. Initialisieren vom DDR2-RAM + 2. Beschreiben des DDR2-RAM mit 16 Datenwerten (mit je 64Bit breite) + 3. Auslesen des ersten Datenwertes + 4. Warten auf Tasteneingaben + + 5a. Bei Taste 1 (North) -> erhoehen des Adresszeigers (ROW) um 1 + 5b. Bei Taste 2 (South) -> veringern des Adresszeigers (ROW) um 1 + 5c. Bei Taste 3 (West) -> schreiben eines einzelnen (fixen) Datenwertes in die aktuelle Adresse + 5d. Bei Taste 4 (East) -> lesen eines einzelnen Datenwertes aus der aktuellen Adresse + +> das "DDR2_Control" uebernimmt auch die Aufbereitung fuer die Anzeige : + + - SW1 bis SW3 dient zum auswählen eines der 8 Bytewerten des 64Bit breiten Datenwortes + + SW3=0 + SW2=0 + SW1=0 -> Anzeige von Datenbits (D7...D0) + SW3=0 + SW2=0 + SW1=1 -> Anzeige von Datenbits (D15...D8) + SW3=0 + SW2=1 + SW1=0 -> Anzeige von Datenbits (D23...D16) + SW3=0 + SW2=1 + SW1=1 -> Anzeige von Datenbits (D31...D24) + SW3=1 + SW2=0 + SW1=0 -> Anzeige von Datenbits (D39...D32) + SW3=1 + SW2=0 + SW1=1 -> Anzeige von Datenbits (D47...D40) + SW3=1 + SW2=1 + SW1=0 -> Anzeige von Datenbits (D55...D48) + SW3=1 + SW2=1 + SW1=1 -> Anzeige von Datenbits (D63...D56) + + das ausgewählte Byte wird an den 8 LEDs angezeigt + +> das "DDR2_Read" enthaellt eine State-Machine um ein Datenwort (64Bit) + aus dem RAM zu lesen + +> das "DDR2_Write" enthaellt eine State-Machine um ein Datenwort (64Bit) + ins RAM zu schreiben + + +Ram Inhalt nach dem Initialisieren : +===================================== + +> nach der Init-Funktion stehen 16 Datenwerte (je 64Bit) im RAM + +ADR 0 = 0123456789ABCDEF +ADR 1 = 123456789ABCDEF0 +ADR 2 = 23456789ABCDEF01 +ADR 3 = 3456789ABCDEF012 +ADR 4 = 456789ABCDEF0123 +ADR 5 = 56789ABCDEF01234 +ADR 6 bis ADR 15 = 639CC6398C7318E7 + + +Ablauf : +========= + + +> nach dem Init und Schreiben von 16 Werten wird die Adr 0 ausgelesen + und an den LEDs ausgegeben + +> Mit dem Button North und South kann der ADR-Counter verändert werden + +> Button EAST liest das RAM an der aktuellen Adresse aus + +> Button WEST schreibt den 64Bit-Wert "31CE629DC43B8877" in die aktuelle Adresse + + + +Infos zum RAM : +================ + +> das DDR2-RAM auf dem Spartan-3A Board hat eine groesse von 512MBit (64MByte) + +> das RAM ist in 4 Bloecke (BANKs) unterteilt, + jeder Block ist in 8192 Reihen (ROWs) und 1024 Zeilen (COLs) aufgeteilt + eine einzelne Zelle ist 16bit breit + + das Ergibt 4x8192x1024x16bit = 512MBit + +> fuer die BANK_Adresse werden 2Bit benoetigt + fuer die ROW_Adresse werden 13Bit benoetigt + fuer die COL_Adresse werden 10Bit benoetigt + +> der Adresszeiger fuer eine einzelne Zelle setzt sich so zusammen : + + ADR = ROW & COL & BANK + + damit ist der Adresszeiger 13+10+2 = 25bit breit + + +Einschraenkungen in dem Projekt : +================================== + +> VORSICHT !! der BURST-MODE ist fest auf "4" eingestellt, + damit werden bei jedem Write Zyklus + 4 Zellen (also 4x16Bit=64Bit) beschrieben !! + +> damit keine Daten überschrieben werden, muss + der COL-Pointer immer in 4er Schritten erhöht/verringert werden + (0,4,8,12 usw) + + +Geschwindigkeit : +================== + +> bei einer Speedmessung (per VHDL-Code) wurde + die Anzahl der notwendigen Clockzyklen ermittelt + +> Read (von einem 64Bit Wert) = 22 Clockzyklen + (bei 133MHz -> 165 ns => 46 MByte/sec) + +> Write (von einem 64Bit Wert) = 25 Clockzyklen + (bei 133MHz -> 188 ns => 40 MByte/sec) + + +Hinweise : +=========== + +> das Projekt ist von "privat" und nicht fuer + kommerzielle Zwecke gedacht + +> das Projekt ist nicht frei von Fehlern + und ich kann daher keine Garantie + fuer eventuell auftretende Schaeden geben + +> das Projekt ist frei kopier- und verwendbar + +> bei gefundenen Fehlern bitte eine EMail an mich + + + +08.08.11 / UB + Index: DDR2_readme.txt =================================================================== --- DDR2_readme.txt (nonexistent) +++ DDR2_readme.txt (revision 2) @@ -0,0 +1,250 @@ +============================================== +Project : Prj_12_DDR2 +Purpose : DDR2-SDRAM at a Spartan-3A Board +DDR2-RAM : MT47H32M16 (64 MByte) +Date : 19.08.2011 +Version : 7.0 +Plattform : XILINX Spartan-3A +FPGA : XC3S700A-FGG484 +Language : VHDL +ISE : ISE-Design-Suite V:13.1 +IP-Core : MIG V:3.6.1 +Author : UB +Mail : Becker_U(at)gmx.de +============================================== + + +first word : +================ + +> sorry for my bad english :-) + + + +Moduls : +================== + + ############### ######################### ################ + # # # # # # + # DDR2-RAM : #---------# TOP_Modul_VHDL #----# Buttons_VHDL # + # 512 MBit # # # # # + # # # # ################ + ############### # # + # # ################ + # # # # + # #----# Clock_VHDL # + # # # # + # # ################ + # # + ############### # # ##################### ################### + # # # # # # # # + # Input : # # # # DDR2_Control_VHDL #----# DDR2_READ_VHDL # + # 4 buttons #---------# # # # # # + # 4 switches # # #----# # ################### + # # # # # # + ############### # # # # ################### + # # # # # # + ################### # # # #----# DDR2_Write_VHDL # + # # # # # # # # + # Output : #-----# # # # ################### + # 8 LEDs (Data) # # # ##################### + # 1 LED (Status) # # # + ################### # # ####################### + # #----# # + ############### # # # DDR2_RAM_CORE.vhd # + # Clock : #---------# # # MIG 3.6.1 # + # 133 MHz # # # # (27 files) # + # # # # # + UCF-File # + ############### ######################### ####################### + + + +purpose : +======== + +> this project is a simple example how to implement the DDR2-SDRAM on a Xilinx FPGA Board + (with the generated Code from the Xilinx MIG) + + + +hint for using the DDR2-RAM : +=================================== + +> the complete DDR2_RAM_Core Files in this project are + genaratet with the Xilinx MIG 3.6.1 tool + + +> MIG settings : + - Typ = DDR2-SDRAM + - Frq = 133MHz + - Write Pipe Stages = 4 + - Memory Part = MT47H32M16XX-3 (for the Spartan-3A Board) + - Data Width = 16 + - Data-Mask = Ja + - SystemClock = Single-Ended + - Signals at : Bank3 (complete) , Bank2 (V12) + - Bank2 = System-Clock / Bank3 = Adrees-Control+Data+System-Control + - all others : "Default" + +> Hint : DDR2_RAM_CORE : + + - only the VHDL-Files from path + "USer_Design/RTL" are used + - the oter files generated from MIG + are not necessary + +> HINT : DDR2 UCF-File : + + - the settings in the UCF-File are very important + for the correct timing and function of the RAM + - i have downloaded the original UCF-File + from Xilinx for the Spartan-3A Board + from these adress : + "http://www.xilinx.com/products/boards/s3astarter/reference_designs.htm" + - a few changes are required (e.g. for the path) + + +Function of the Project : +============================ + +> Switch-0 (SW0) is the Reset-Switch (High = Reset) + +> the "TOP_Modul" only routes the signals between the other Moduls + +> the "Buttons_VHDL" debounce the switches und buttons + and generate a "rising_edge" signal for the 4 Buttons + +> the "DDR2_Control" has a state machine with these steps : + + 1. Init the RAM + 2. Automatic Write Sequenz (writes 16 Datawords each 64Bit) + 3. Automatic Read Sequenz (reads the first Dataword with 64Bit from adress 0) + 4. Wait for a button signal + + 5a. Button-1 (north) -> increment ROW-Counter + 5b. Button-2 (south) -> decrement ROW-COunter + 5c. Button-3 (west) -> writes a single Datawort (64Bit) to the actual adress + 5d. Button-4 (east) -> reads a single Dataword (64Bit) from the actual adress + +> the "DDR2_Control" also selects one Byte (from the 64Bit Dataword) + + - SW1 to SW3 are the MUX-Select-Pins : + + SW3=0 + SW2=0 + SW1=0 -> shows the Databits (D7...D0) + SW3=0 + SW2=0 + SW1=1 -> shows the Databits (D15...D8) + SW3=0 + SW2=1 + SW1=0 -> shows the Databits (D23...D16) + SW3=0 + SW2=1 + SW1=1 -> shows the Databits (D31...D24) + SW3=1 + SW2=0 + SW1=0 -> shows the Databits (D39...D32) + SW3=1 + SW2=0 + SW1=1 -> shows the Databits (D47...D40) + SW3=1 + SW2=1 + SW1=0 -> shows the Databits (D55...D48) + SW3=1 + SW2=1 + SW1=1 -> shows the Databits (D63...D56) + + the selected Databits are shown on the 8 LEDs at the FPGA-Board + +> the "DDR2_Read" has a state machine to read one Dataword (64Bit) + from given adress + +> the "DDR2_Write" has a state machine to write one Dataword (64Bit) + to the given adress + + + +Ram Data content after the automatic write sequenz : +====================================================== + +> after the automtic write sequenz the content of the first 16 Datawords are : + +ADR 0 = 0123456789ABCDEF +ADR 1 = 123456789ABCDEF0 +ADR 2 = 23456789ABCDEF01 +ADR 3 = 3456789ABCDEF012 +ADR 4 = 456789ABCDEF0123 +ADR 5 = 56789ABCDEF01234 +ADR 6 to ADR 15 = 639CC6398C7318E7 + + + +Process after power on : +========================== + +> after the RAM-INIT and writing of 16 Datawords + the first RAM-Adress is reading and shown on the LEDs + +> the buttons "north" and "south" changes the actuall adress pointer + +> to read one adress use button "east" + +> to write the Dataword "31CE629DC43B8877" use button "west" + + + +RAM-Info : +================ + +> the size of the DDR2-RAM is 512MBit (64MByte) + +> it is splitted in 4 Blocks (Banks) + each Block has 8192 ROWs and 1024 COLs + + a single Datacell is 16bit wide + + 4x8192*1024*16bit = 512MBit + +> the Bank-Adress needs 2Bit + the ROW-Adress needs 13Bit + the COL-Adress needs 10Bit + +> the Adresspointer looks like : + + ADR = ROW & COL & BANK + + the complete ADR-Pointer needs 25Bit + + + +Restrictions in this project : +================================== + +> the "Burst-Mode" is fixed set to "4" + whis this setting the Dataword is 64Bit wide + +> each read process reads 64Bit and each write process + writes 64Bits + +> to avoid data fail the COL-Adress must increment + and decrement by the value of "4" + like (0,4,8,12...) + + + +Speed : +================== + +> a single read process (of 64Bit) needs 22 Clockcycles + (at 133MHz -> 165 ns => 46 MByte/sec) + +> a single write process (of 64Bit) needs 25 Clockcycles + (at 133MHz -> 188 ns => 40 MByte/sec) + + +last Hints : +============= + +> this project is "from private" + and not allowed for commercial use + +> this project is not free of bugs + and i can not give a guarantee + for any kind of error or damages + +> everyone is permitted to copy and modify + this files + +> please give me a notice if you found + some bugs + + + + +19.08.11 / UB + Index: Prj12_Impact_xdb/tmp =================================================================== --- Prj12_Impact_xdb/tmp (nonexistent) +++ Prj12_Impact_xdb/tmp (revision 2)
Prj12_Impact_xdb/tmp Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: Prj12_Impact_xdb =================================================================== --- Prj12_Impact_xdb (nonexistent) +++ Prj12_Impact_xdb (revision 2)
Prj12_Impact_xdb Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: Clock_VHDL.vhd =================================================================== --- Clock_VHDL.vhd (nonexistent) +++ Clock_VHDL.vhd (revision 2) @@ -0,0 +1,62 @@ +--------------------------------------------------------------------- +-- File : DDR2_Control_VHDL.vhd +-- Projekt : Prj_12_DDR2 +-- Zweck : DDR2-Verwaltung (Init,Read,Write) +-- Datum : 19.08.2011 +-- Version : 2.0 +-- Plattform : XILINX Spartan-3A +-- FPGA : XC3S700A-FGG484 +-- Sprache : VHDL +-- ISE : ISE-Design-Suite V:13.1 +-- Autor : UB +-- Mail : Becker_U(at)gmx.de +--------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Clock_VHDL is + -------------------------------------------- + -- Port Deklerationen + -------------------------------------------- + port ( + clk_in_133MHz : in std_logic; + clk_out_1Hz : out std_logic + ); + +end Clock_VHDL; + +architecture Verhalten of Clock_VHDL is + + -------------------------------------------- + -- Interne Signale + -------------------------------------------- + constant STATUS_LED_VORTEILER : integer := 66500000; -- 1Hz bei 133MHz Quarzclock + signal v_cnt1 : natural range 0 to STATUS_LED_VORTEILER := 0; + signal clk1Hz : std_logic := '0'; + + +begin + + ------------------------------------------------------- + -- erzeugen eines 1Hz Signales aus dem Eingangstakt + ------------------------------------------------------- + Timer2 : process (clk_in_133MHz) begin + if rising_edge(clk_in_133MHz) then + v_cnt1 <= v_cnt1 + 1; + if(v_cnt1 >= STATUS_LED_VORTEILER) then + -- wenn zeit abgelaufen, signal toggeln + v_cnt1 <= 0; + clk1Hz <= not clk1Hz; + end if; + end if; + end process Timer2; + + ------------------------------------------------------- + -- Uebergabe aller Signale + ------------------------------------------------------- + clk_out_1Hz<=clk1Hz; + + + +end Verhalten; + Index: DDR2_Control_VHDL.vhd =================================================================== --- DDR2_Control_VHDL.vhd (nonexistent) +++ DDR2_Control_VHDL.vhd (revision 2) @@ -0,0 +1,502 @@ +--------------------------------------------------------------------- +-- File : DDR2_Control_VHDL.vhd +-- Projekt : Prj_12_DDR2 +-- Zweck : DDR2-Verwaltung (Init,Read,Write) +-- Datum : 19.08.2011 +-- Version : 2.0 +-- Plattform : XILINX Spartan-3A +-- FPGA : XC3S700A-FGG484 +-- Sprache : VHDL +-- ISE : ISE-Design-Suite V:13.1 +-- Autor : UB +-- Mail : Becker_U(at)gmx.de +--------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + -------------------------------------------- + -- Beschreibung : + -- + -- das DDR2-RAM hat 512 MBit (64MByte) Speicherplatz + -- organisiert in 16Bit Woertern + -- + -- es werden immer Datenworte von 64Bit ausgelesen + -- oder geschrieben (weil der Burst-Mode auf 4 steht) + -- aus dem Grund ist der Daten-Vektor für Read/Write + -- 64Bit breit + -- + -- das RAM ist ein 4 Blöcke unterteilt (zu je 16Mbyte) + -- Bank "00" bis Bank "11" : 2Bit + -- + -- jeder Block ist in 8192 Reihen zu je 1024 Spalten organisiert + -- ROW "0000000000000" bis "1111111111111" : 13Bit + -- COL "0000000000" bis "1111111111" : 10Bit + -- + -- die übergebene Adresse an die FIFO Komponente + -- mit 25 Bit setzt sich dann so zusammen + -- + -- input_adress = ROW & COL & BANK + -- (25Bit) 13Bit 10Bit 2Bit + -- pro Adresse stehen 16bit Daten + -- + -- in diesem Demo-Programm wird nur Bank=0 + -- COL=0 und ROW= 0 bis 15 benutzt + --------------------------------------------- + -- + -- das CONTROL steuert die READ und WRITE funktion + -- je nachdem welcher Button gedrückt wurde + -- + -------------------------------------------- + -- Vorsicht !! zur Adressierung : + -- Der Burst-Mode steht FIX auf "4" + -- damit werden IMMER 4 (16bit) Zellen gelesen + -- und beschrieben (also imer 64Bit) + -- + -- wenn also das 64bit Wort "123456789ABCDEF0" in Adr 0 + -- geschrieben wird, sieht der Speicher danach so aus : + -- Row 0 Col 0 = "1234" + -- Row 0 Col 1 = "5678" + -- Row 0 Col 2 = "9ABC" + -- Row 0 Col 3 = "DEF0" + -- + -- Der Col-Counter muss also immer um 4 Adressen + -- incrementiert / decrementiert werden + -- + -- in der Demo hier wird nur der ROW-Counter verändert + -- + -------------------------------------------- + + + +entity DDR2_Control_VHDL is + + -------------------------------------------- + -- Port Deklerationen + -------------------------------------------- + port ( + reset_in : in std_logic; + clk_in : in std_logic; + clk90_in : in std_logic; + init_done : in std_logic; + command_register : out std_logic_vector(2 downto 0); + input_adress : out std_logic_vector(24 downto 0); + input_data : out std_logic_vector(31 downto 0); + output_data : in std_logic_vector(31 downto 0); + cmd_ack : in std_logic; + data_valid : in std_logic; + burst_done : out std_logic; + auto_ref_req : in std_logic; + debounce_in : in std_logic_vector(7 downto 0); + risingedge_in : in std_logic_vector(3 downto 0); + data_out : out std_logic_vector(7 downto 0) + ); + +end DDR2_Control_VHDL; + +architecture Verhalten of DDR2_Control_VHDL is + + -------------------------------------------- + -- Einbinden einer Componente + -- zum schreiben eines 64Bit Wertes + -------------------------------------------- + COMPONENT DDR2_Write_VHDL + PORT ( + reset_in : in std_logic; + clk_in : in std_logic; + clk90_in : in std_logic; + w_command_register : out std_logic_vector(2 downto 0); + w_cmd_ack : in std_logic; + w_burst_done : out std_logic; + write_en : in std_logic; + write_busy : out std_logic; + input_data : out std_logic_vector(31 downto 0); + write_data : in std_logic_vector(63 downto 0) + ); + END COMPONENT DDR2_Write_VHDL; + + -------------------------------------------- + -- Einbinden einer Componente + -- zum lesen eines 64Bit Wertes + -------------------------------------------- + COMPONENT DDR2_Read_VHDL + PORT ( + reset_in : in std_logic; + clk_in : in std_logic; + clk90_in : in std_logic; + r_command_register : out std_logic_vector(2 downto 0); + r_cmd_ack : in std_logic; + r_burst_done : out std_logic; + r_data_valid : in std_logic; + read_en : in std_logic; + read_busy : out std_logic; + output_data : in std_logic_vector(31 downto 0); + read_data : out std_logic_vector(63 downto 0) + ); + END COMPONENT DDR2_Read_VHDL; + + -------------------------------------------- + -- Interne Signale + -------------------------------------------- + + constant INIT_PAUSE : integer := 133000; -- pause 1ms (Wichtig !!) + signal v_counter : natural range 0 to INIT_PAUSE := INIT_PAUSE; + + -------------------------------------------- + -- 16 Konstante Werte erzeugen, die beim INIT + -- (Auto-Write) ins RAM geschrieben werden + -- ein Wert ist 64Bit = 8 Byte breit + -------------------------------------------- + constant MAX_ADR : integer := 15; -- 0 bis 15 = 16 Werte + type RAM_DATA_TYP is array (0 to MAX_ADR) of std_logic_vector(63 downto 0); + constant RAM_DATA : RAM_DATA_TYP := + ( + x"0123456789ABCDEF", x"123456789ABCDEF0", x"23456789ABCDEF01", x"3456789ABCDEF012", + x"456789ABCDEF0123", x"56789ABCDEF01234", others => (x"639CC6398C7318E7") + ); + signal v_array_pos : natural range 0 to MAX_ADR+1 := 0; + + -------------------------------------------- + -- Definition der ROW,COL,BANK adressen + -------------------------------------------- + signal v_ROW : std_logic_vector(12 downto 0):= (others => '0'); -- 13Bit + signal v_COL : std_logic_vector(9 downto 0):= (others => '0'); -- 10Bit + signal v_BANK : std_logic_vector(1 downto 0):= (others => '0'); -- 2Bit + + -- zwischenspeicher fuer daten + signal v_write_data : std_logic_vector(63 downto 0):= (others => '0'); + signal v_read_data : std_logic_vector(63 downto 0):= (others => '0'); + + -------------------------------------------- + -- Ein Konstanter Wert, der mit WRITE-Button + -- ins RAM geschrieben wird + -------------------------------------------- + constant CONST_DATA : std_logic_vector(63 downto 0):= x"31CE629DC43B8877"; + + -------------------------------------------- + -- State-Machine-Typen + -------------------------------------------- + type STATE_M_TYPE is ( + M1_START_UP, + M2_WAIT_4_DONE, + M3_AUTO_WRITE_START, + M4_AUTO_WRITE_INIT, + M5_AUTO_WRITING, + M6_AUTO_READ_INIT, + M7_AUTO_READING, + M8_NOP, + M9_WRITE_INIT, + M10_WRITING, + M11_READ_INIT, + M12_READING + ); + signal STATE_M : STATE_M_TYPE := M1_START_UP; + + -------------------------------------------- + -- sonstige Signale + -------------------------------------------- + signal v_write_en : std_logic:='0'; -- '1'=chip-select + signal v_read_en : std_logic:='0'; -- '1'=chip-select + signal v_write_busy : std_logic; -- '1'=belegt, '0'=frei + signal v_read_busy : std_logic; -- '1'=belegt, '0'=frei + signal v_main_command_register : std_logic_vector(2 downto 0):= (others => '0'); + signal v_write_command_register : std_logic_vector(2 downto 0):= (others => '0'); + signal v_read_command_register : std_logic_vector(2 downto 0):= (others => '0'); + signal v_write_burst_done : std_logic; + signal v_read_burst_done : std_logic; + +begin + + -------------------------------------------------- + -- Instantz einer Componente erzeugen und verbinden + -- zum schreiben eines 64Bit Wertes + -------------------------------------------------- + INST_DDR2_Write_VHDL : DDR2_Write_VHDL + PORT MAP ( + reset_in => reset_in, + clk_in => clk_in, + clk90_in => clk90_in, + w_command_register => v_write_command_register, + w_cmd_ack => cmd_ack, + w_burst_done => v_write_burst_done, + write_en => v_write_en, + write_busy => v_write_busy, + input_data => input_data, + write_data => v_write_data + ); + + -------------------------------------------------- + -- Instantz einer Componente erzeugen und verbinden + -- zum lesen eines 64Bit Wertes + -------------------------------------------------- + INST_DDR2_Read_VHDL : DDR2_Read_VHDL + PORT MAP ( + reset_in => reset_in, + clk_in => clk_in, + clk90_in => clk90_in, + r_command_register => v_read_command_register, + r_cmd_ack => cmd_ack, + r_burst_done => v_read_burst_done, + r_data_valid => data_valid, + read_en => v_read_en, + read_busy => v_read_busy, + output_data => output_data, + read_data => v_read_data + ); + + ----------------------------------------- + -- State-Machine : + -- 1. wartet nach Reset 1ms + -- 2. sendet das INIT-Kommando an das RAM + -- 3. Wartet auf das INIT_DONE vom RAM + -- 4. Schreiben von 16 Datenwerten ins RAM + -- 5. Auslesen von Adr0 + -- 6. Warte auf Tastendrück + -- + -- 7a. North/South = ändern der Adresse (ROW) + -- 7b. East = auslesen eines Wertes + -- 7c. West = schreiben eines Wertes + -- 8. Sprung zu Punkt 6 + ----------------------------------------- + P_State_Main : process(clk_in,reset_in) + begin + if reset_in = '1' then + -- reset button ist gedrueckt + STATE_M <= M1_START_UP; + v_write_en <= '0'; + v_read_en <= '0'; + v_main_command_register <= "000"; -- NOP + v_counter <= INIT_PAUSE; + v_ROW <= (others => '0'); + v_COL <= (others => '0'); + v_BANK <= (others => '0'); + v_array_pos <= 0; + elsif falling_edge(clk_in) then + case STATE_M is + ----------------------------------------------------- + -- INITIALISIERUNG vom RAM : WICHTIG !! : + -- nach dem Reset wird 1ms gewartet und danach + -- wird das INIT-Kommando an das RAM gesendet + -- und auf das Init-Done-Signal vom RAM gewartet + ----------------------------------------------------- + when M1_START_UP => + -- warte 1ms nach Reset bis RAM bereit + -- WICHTIG !! das steht so im Datasheet + if v_counter = 0 then + -- nach 1ms INIT-Kommando (für einen Clock) anlegen + STATE_M <= M2_WAIT_4_DONE; + v_main_command_register <= "010"; -- INIT-CMD + else + v_main_command_register <= "000"; -- NOP + v_counter <= v_counter - 1; + end if; + when M2_WAIT_4_DONE => + -- warte auf Init-Done-Signal vom RAM + v_main_command_register <= "000"; -- NOP + if (init_done = '1') then + -- das RAM ist jetzt bereit + STATE_M <= M3_AUTO_WRITE_START; + end if; + ----------------------------------------------------- + -- automatisches schreiben von ein paar Werten : + -- es werden 16 feste Datenwerte in die Adressen 0-15 + -- ins RAM geschrieben + ----------------------------------------------------- + when M3_AUTO_WRITE_START => + -- automatisches schreiben von daten ins RAM + if v_array_pos > MAX_ADR then + -- wenn alle adressen geschrieben sind + STATE_M <= M6_AUTO_READ_INIT; + v_ROW <= (others => '0'); + else + if v_write_busy = '0' and auto_ref_req = '0' then + -- wenn RAM nicht beschäftigt ist, starte das schreiben + STATE_M <= M4_AUTO_WRITE_INIT; + end if; + end if; + when M4_AUTO_WRITE_INIT => + -- warten bis zum schreiben bereit + if v_write_busy = '0' and v_write_en='0' then + -- daten zum schreiben freigeben + v_write_en <= '1'; + elsif v_write_busy = '1' and v_write_en='1' then + -- daten werden geschrieben + v_write_en <= '0'; + STATE_M <= M5_AUTO_WRITING; + end if; + when M5_AUTO_WRITING => + -- warte bis schreiben fertig + if v_write_busy = '0' then + -- naechste adresse beschreiben + v_array_pos <= v_array_pos +1; + v_ROW <= v_ROW +1; + STATE_M <= M3_AUTO_WRITE_START; + end if; + ----------------------------------------------------- + -- automatisches lesen von einem Wert : + -- es wird der Inhalt von Adr 0 vom RAM ausgelesen + ----------------------------------------------------- + when M6_AUTO_READ_INIT => + -- automatisches lesen vom RAM (ein wert) + -- warten bis zum lesen bereit + if v_read_busy = '0' and v_read_en='0' and auto_ref_req = '0' then + -- daten zum lesen freigeben + v_read_en <= '1'; + elsif v_read_busy = '1' and v_read_en='1' then + -- daten werden gelesen + v_read_en <= '0'; + STATE_M <= M7_AUTO_READING; + end if; + when M7_AUTO_READING => + -- warte bis lesen fertig + if v_read_busy = '0' then + STATE_M <= M8_NOP; + end if; + ----------------------------------------------------- + -- Dauerloop : warten auf User-Eingabe : + -- hier wird gewartet, bis einer der 4 Buttons + -- gedrückt wurde + ----------------------------------------------------- + when M8_NOP => + -- warte auf Taste fuer READ oder WRITE + v_write_en <= '0'; + v_read_en <= '0'; + if risingedge_in(3) = '1' and v_write_busy = '0' and auto_ref_req = '0' then + -- button = west + -- write starten (nur wenn nicht busy und kein refresh-zyklus) + STATE_M <= M9_WRITE_INIT; + elsif risingedge_in(0) = '1' and v_read_busy = '0' and auto_ref_req = '0' then + -- button = east + -- read starten (nur wenn nicht busy und kein refresh-zyklus) + STATE_M <= M11_READ_INIT; + end if; + -- warte auf Taste fuer Adr-Up oder Adr-Down + if risingedge_in(1)='1' and v_ROW < 255 then + -- button = north + v_ROW <= v_ROW + 1; + elsif risingedge_in(2)='1' and v_ROW > 0 then + -- button = south + v_ROW <= v_ROW - 1; + end if; + ----------------------------------------------------- + -- WRITE : schreiben eines Wertes ins RAM : + -- ein fester Datenwert wird in die aktuelle Adresse + -- ins RAM geschrieben + ----------------------------------------------------- + when M9_WRITE_INIT => + -- warten bis zum schreiben bereit + if v_write_busy = '0' and v_write_en='0' then + -- daten zum schreiben freigeben + v_write_en <= '1'; + elsif v_write_busy = '1' and v_write_en='1' then + -- daten werden geschrieben + v_write_en <= '0'; + STATE_M <= M10_WRITING; + end if; + when M10_WRITING => + -- warte bis schreiben fertig + if v_write_busy = '0' then + STATE_M <= M8_NOP; + end if; + ----------------------------------------------------- + -- READ : lesen eines Wertes vom RAM : + -- die aktuelle Adresse vom RAM wird ausgelesen + ----------------------------------------------------- + when M11_READ_INIT => + -- warten bis zum lesen bereit + if v_read_busy = '0' and v_read_en='0' then + -- daten zum lesen freigeben + v_read_en <= '1'; + elsif v_read_busy = '1' and v_read_en='1' then + -- daten werden gelesen + v_read_en <= '0'; + STATE_M <= M12_READING; + end if; + when M12_READING => + -- warte bis lesen fertig + if v_read_busy = '0' then + STATE_M <= M8_NOP; + end if; + when others => + NULL; + end case; + end if; + end process P_State_Main; + + ----------------------------------------- + -- Weiterleitung von Signalen + -- in Abhängigkeit von Read oder Write : + ----------------------------------------- + P_SIGNAL : process(clk_in) + begin + if falling_edge(clk_in) then + if STATE_M=M4_AUTO_WRITE_INIT or STATE_M=M5_AUTO_WRITING then + ----------------------------------------------------- + -- automatisches schreiben von ein paar Werten + ----------------------------------------------------- + v_write_data <= RAM_DATA(v_array_pos); + input_adress <= v_ROW & v_COL & v_BANK; + command_register <= v_write_command_register; + burst_done <= v_write_burst_done; + elsif STATE_M=M6_AUTO_READ_INIT or STATE_M=M7_AUTO_READING then + ----------------------------------------------------- + -- automatisches lesen von einem Wert + ----------------------------------------------------- + v_write_data <= (others => '0'); + input_adress <= v_ROW & v_COL & v_BANK; + command_register <= v_read_command_register; + burst_done <= v_read_burst_done; + elsif STATE_M=M9_WRITE_INIT or STATE_M=M10_WRITING then + ----------------------------------------------------- + -- WRITE : schreiben eines Wertes ins RAM + ----------------------------------------------------- + v_write_data <= CONST_DATA; + input_adress <= v_ROW & v_COL & v_BANK; + command_register <= v_write_command_register; + burst_done <= v_write_burst_done; + elsif STATE_M=M11_READ_INIT or STATE_M=M12_READING then + ----------------------------------------------------- + -- READ : lesen eines Wertes vom RAM + ----------------------------------------------------- + v_write_data <= (others => '0'); + input_adress <= v_ROW & v_COL & v_BANK; + command_register <= v_read_command_register; + burst_done <= v_read_burst_done; + else + ----------------------------------------------------- + -- Dauerloop oder INIT + ----------------------------------------------------- + v_write_data <= (others => '0'); + input_adress <= (others => '0'); + command_register <= v_main_command_register; + burst_done <= '0'; + end if; + end if; + end process P_SIGNAL; + + ----------------------------------------- + -- Ausgabe der gelesenen Daten + -- je nach Schalterstellung + ----------------------------------------- + P_DataOut : process(clk_in,reset_in) + begin + if reset_in = '1' then + -- reset button ist gedrueckt + data_out <= (others => '0'); + elsif falling_edge(clk_in) then + if debounce_in(7 downto 5)="000" then data_out <= v_read_data(7 downto 0); + elsif debounce_in(7 downto 5)="001" then data_out <= v_read_data(15 downto 8); + elsif debounce_in(7 downto 5)="010" then data_out <= v_read_data(23 downto 16); + elsif debounce_in(7 downto 5)="011" then data_out <= v_read_data(31 downto 24); + elsif debounce_in(7 downto 5)="100" then data_out <= v_read_data(39 downto 32); + elsif debounce_in(7 downto 5)="101" then data_out <= v_read_data(47 downto 40); + elsif debounce_in(7 downto 5)="110" then data_out <= v_read_data(55 downto 48); + elsif debounce_in(7 downto 5)="111" then data_out <= v_read_data(63 downto 56); + end if; + ------------------------------------------- + end if; + end process P_DataOut; + +end Verhalten; + Index: Top_Modul_VHDL_bitgen.xwbt =================================================================== --- Top_Modul_VHDL_bitgen.xwbt (nonexistent) +++ Top_Modul_VHDL_bitgen.xwbt (revision 2) @@ -0,0 +1,8 @@ +INTSTYLE=ise +INFILE=F:\Data_Temp_Ordner\Xilinx\Projekte\Test_Prj_VHDL\Prj_12_DDR2\Prj_12_DDR2\Top_Modul_VHDL.ncd +OUTFILE=F:\Data_Temp_Ordner\Xilinx\Projekte\Test_Prj_VHDL\Prj_12_DDR2\Prj_12_DDR2\Top_Modul_VHDL.bit +FAMILY=Spartan3A and Spartan3AN +PART=xc3s700a-4fg484 +WORKINGDIR=F:\Data_Temp_Ordner\Xilinx\Projekte\Test_Prj_VHDL\Prj_12_DDR2\Prj_12_DDR2 +LICENSE=WebPack +USER_INFO=205456775_0_0_536 Index: UB_Clock_UCF.ucf =================================================================== --- UB_Clock_UCF.ucf (nonexistent) +++ UB_Clock_UCF.ucf (revision 2) @@ -0,0 +1,31 @@ +######################################### +# File : UB_Clock_UCF.ucf +# Autor : UB +# +# Constraint-File fuer die externen Clock-Quellen +# auf dem Spartan-3A Board +# +# CLK_50MHZ_IN = 50 MHz +# CLK_AUX_IN = 133,33 MHz +# CLK_SMA_IN = nicht belegt +# +# +# unbenutzte Netze per '#' deaktivieren +# +######################################### + +#NET "CLK_50MHZ_IN" LOC = "E12"| IOSTANDARD = LVCMOS33 ; +NET "CLK_AUX_IN" LOC = "V12"| IOSTANDARD = LVCMOS33 ; +#NET "CLK_SMA_IN" LOC = "U12"| IOSTANDARD = LVCMOS33 ; + + +######################################### +# Port-Zuweisungen +######################################### +# +# +# CLK_50MHZ_IN : in std_logic; +# CLK_AUX_IN : in std_logic; +# CLK_SMA_IN : in std_logic; +# +######################################### \ No newline at end of file Index: Buttons_VHDL.vhd =================================================================== --- Buttons_VHDL.vhd (nonexistent) +++ Buttons_VHDL.vhd (revision 2) @@ -0,0 +1,138 @@ +--------------------------------------------------------------------- +-- File : Buttons_VHDL.vhd +-- Projekt : Prj_12_DDR2 +-- Zweck : Buttons und Schalter entprellen +-- Datum : 19.08.2011 +-- Version : 2.0 +-- Plattform : XILINX Spartan-3A +-- FPGA : XC3S700A-FGG484 +-- Sprache : VHDL +-- ISE : ISE-Design-Suite V:13.1 +-- Autor : UB +-- Mail : Becker_U(at)gmx.de +--------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + -------------------------------------------- + -- Beschreibung : + -- + -- hier werden die Buttons und Schalter + -- mit dem Clock syncronisiert + -- + -- weil die Taster prellen + -- werden sie mit einer Verzögerung eingelesen + -- sonst kommt es zu anzeigefehlern + -- + -- damit die Read/Write Funktionen + -- bei gedruecktem Button nicht + -- staendig aufgerufen werden, + -- wird aus allen 4 Buttons + -- ein OnClick-Eregnis gemacht + -------------------------------------------- + +entity Buttons_VHDL is + + -------------------------------------------- + -- Port Deklerationen + -------------------------------------------- + port ( + clk_in : in std_logic; + button_in : in std_logic_vector(3 downto 0); + switch_in : in std_logic_vector(3 downto 0); + debounce_out : out std_logic_vector(7 downto 0); + risingedge_out : out std_logic_vector(3 downto 0) + ); + +end Buttons_VHDL; + +architecture Verhalten of Buttons_VHDL is + + -------------------------------------------- + -- Interne Signale + -------------------------------------------- + signal v_debounce : std_logic_vector(7 downto 0) := (others => '0'); + signal v_btn_old : std_logic_vector(3 downto 0):= (others => '0'); + signal v_btn_tic : std_logic_vector(3 downto 0):= (others => '0'); + + -- verzoegerung für die tasten, weil sie prellen + constant BUTTON_SLEEP : integer := 6650000; -- Zeit = 50ms bei 133MHz Quarz + signal v_counter : natural range 0 to BUTTON_SLEEP := BUTTON_SLEEP; + +begin + + ----------------------------------------- + -- Einclocken von Asyncronen Signalen + ----------------------------------------- + P_ASYNC : process(clk_in) + begin + if falling_edge(clk_in) then + if v_counter = 0 then + -- wenn Verzögerungszeit um, die zustände der + -- buttons und schalter übergeben + v_counter <= BUTTON_SLEEP; + v_debounce(3 downto 0) <= button_in(3 downto 0); + v_debounce(7 downto 4) <= switch_in(3 downto 0); + else + v_counter <= v_counter -1; + end if; + end if; + end process P_ASYNC; + + -- übergabe der Signale------------------ + debounce_out <= v_debounce; + + ----------------------------------------- + -- Aus den Tastern jeweils ein + -- einzelnes 1Clock langes Signal machen, + -- bis der Taser wieder verlassen ist + -- damit die Funktionen (+/-, read,write) + -- nur einmal ausgeführt werden + ----------------------------------------- + P_Buttons : process(clk_in) + begin + if falling_edge(clk_in) then + -- TIC merker zurücksetzen + v_btn_tic(3 downto 0) <= "0000"; + + -- button east------------------------------- + if v_debounce(0)='1' and v_btn_old(0)='0' then + v_btn_old(0) <= '1'; + v_btn_tic(0) <= '1'; + elsif v_debounce(0)='0' and v_btn_old(0)='1' then + v_btn_old(0) <= '0'; + end if; + + -- button north----------------------------- + if v_debounce(1)='1' and v_btn_old(1)='0' then + v_btn_old(1) <= '1'; + v_btn_tic(1) <= '1'; + elsif v_debounce(1)='0' and v_btn_old(1)='1' then + v_btn_old(1) <= '0'; + end if; + + -- button south----------------------------- + if v_debounce(2)='1' and v_btn_old(2)='0' then + v_btn_old(2) <= '1'; + v_btn_tic(2) <= '1'; + elsif v_debounce(2)='0' and v_btn_old(2)='1' then + v_btn_old(2) <= '0'; + end if; + + -- button west------------------------------ + if v_debounce(3)='1' and v_btn_old(3)='0' then + v_btn_old(3) <= '1'; + v_btn_tic(3) <= '1'; + elsif v_debounce(3)='0' and v_btn_old(3)='1' then + v_btn_old(3) <= '0'; + end if; + end if; + end process P_Buttons; + + -- übergabe der Signale------------------ + risingedge_out <= v_btn_tic; + +end Verhalten; + Index: impact_impact.xwbt =================================================================== --- impact_impact.xwbt (nonexistent) +++ impact_impact.xwbt (revision 2) @@ -0,0 +1,8 @@ +INTSTYLE=impact +INFILE=F:\Data_Temp_Ordner\Xilinx\Projekte\Test_Prj_VHDL\Prj_12_DDR2\Prj_12_DDR2\impact.xsl +OUTFILE=F:\Data_Temp_Ordner\Xilinx\Projekte\Test_Prj_VHDL\Prj_12_DDR2\Prj_12_DDR2\impact.xsl +FAMILY=Multiple +PART=Multiple +WORKINGDIR=F:\Data_Temp_Ordner\Xilinx\Projekte\Test_Prj_VHDL\Prj_12_DDR2\Prj_12_DDR2 +LICENSE=iMPACT +USER_INFO=iMPACT Index: Prj_12_DDR2.gise =================================================================== --- Prj_12_DDR2.gise (nonexistent) +++ Prj_12_DDR2.gise (revision 2) @@ -0,0 +1,30 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + Index: Top_Modul_VHDL.vhd =================================================================== --- Top_Modul_VHDL.vhd (nonexistent) +++ Top_Modul_VHDL.vhd (revision 2) @@ -0,0 +1,280 @@ +--------------------------------------------------------------------- +-- File : Top_Modul_VHDL.vhd +-- Projekt : Prj_12_DDR2 +-- Zweck : DDR2-SDRAM am Spartan-3A Board +-- DDR2-RAM : MT47H32M16 (64 MByte) +-- Datum : 19.08.2011 +-- Version : 7.0 +-- Plattform : XILINX Spartan-3A +-- FPGA : XC3S700A-FGG484 +-- Sprache : VHDL +-- ISE : ISE-Design-Suite V:13.1 +-- IP-Core : MIG V:3.6.1 +-- Autor : UB +-- Mail : Becker_U(at)gmx.de +--------------------------------------------------------------------- +-- +-- Bitte auch die Hinweise in der "DDR2_liesmich.txt" beachten +-- +-- please have a look at the "DDR2_readme.txt" +-- and sorry for my bad english :-) +-- +--------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity Top_Modul_VHDL is + -------------------------------------------- + -- Port Deklerationen + -------------------------------------------- + port( + CLK_AUX_IN : in std_logic; + LED_OUT : out std_logic_vector(7 downto 0); + LED_YELLOW_OUT : out std_logic; + SW_IN : in std_logic_vector(3 downto 0); + BTN_IN : in std_logic_vector(3 downto 0); + ---------------------------------------------------- + -- DDR2 SDRAM-Port-Pins + ---------------------------------------------------- + cntrl0_ddr2_a : out std_logic_vector(12 downto 0) := (others => '0'); + cntrl0_ddr2_ba : out std_logic_vector(1 downto 0) := (others => '0'); + cntrl0_ddr2_ck : out std_logic_vector(0 downto 0) := (others => '0'); + cntrl0_ddr2_ck_n : out std_logic_vector(0 downto 0) := (others => '0'); + cntrl0_ddr2_cke : out std_logic := '0'; + cntrl0_ddr2_cs_n : out std_logic := '0'; + cntrl0_ddr2_ras_n : out std_logic := '0'; + cntrl0_ddr2_cas_n : out std_logic := '0'; + cntrl0_ddr2_we_n : out std_logic := '0'; + cntrl0_ddr2_odt : out std_logic := '0'; + cntrl0_ddr2_dm : out std_logic_vector(1 downto 0) := (others => '0'); + cntrl0_ddr2_dqs_n : inout std_logic_vector(1 downto 0) := (others => '0'); + cntrl0_ddr2_dqs : inout std_logic_vector(1 downto 0) := (others => '0'); + cntrl0_ddr2_dq : inout std_logic_vector(15 downto 0) := (others => '0'); + cntrl0_rst_dqs_div_in : in std_logic; + cntrl0_rst_dqs_div_out : out std_logic + ---------------------------------------------------- + ); + +end Top_Modul_VHDL; + +architecture Verhalten of Top_Modul_VHDL is + + -------------------------------------------- + -- Interne Signale + -------------------------------------------- + signal v_reset_n : std_logic; + signal v_reset_p : std_logic; + signal v_debounce : std_logic_vector(7 downto 0) := (others => '0'); + signal v_risingedge : std_logic_vector(3 downto 0) := (others => '0'); + + -- DDR2 SDRAM-Leitungen ----------------------------------------- + signal clk_tb : std_logic; + signal clk90_tb : std_logic; + signal burst_done : std_logic; + signal user_command_register : std_logic_vector(2 downto 0) := (others => '0'); + signal user_data_mask : std_logic_vector(3 downto 0):= (others => '0'); + signal user_input_data : std_logic_vector(31 downto 0); + signal user_input_address : std_logic_vector(24 downto 0); + signal v_init_done : std_logic; + signal ar_done : std_logic; + signal auto_ref_req : std_logic; + signal user_cmd_ack : std_logic; + signal user_data_valid : std_logic; + signal user_output_data : std_logic_vector(31 downto 0); + --------------------------------------------------------------------- + + -------------------------------------------- + -- Einbinden einer Componente + -- Clock_VHDL : für die Clockerzeugung + -------------------------------------------- + COMPONENT Clock_VHDL is + PORT ( + clk_in_133MHz : in std_logic; + clk_out_1Hz : out std_logic + ); + END COMPONENT Clock_VHDL; + + -------------------------------------------- + -- Einbinden einer Componente + -- Buttons_VHDL : für die Buttons und Schalter + -------------------------------------------- + COMPONENT Buttons_VHDL is + PORT ( + clk_in : in std_logic; + button_in : in std_logic_vector(3 downto 0); + switch_in : in std_logic_vector(3 downto 0); + debounce_out : out std_logic_vector(7 downto 0); + risingedge_out : out std_logic_vector(3 downto 0) + ); + END COMPONENT Buttons_VHDL; + + -------------------------------------------- + -- Einbinden einer Componente + -- VHDL um das DDR2 zu steuern + -------------------------------------------- + COMPONENT DDR2_Control_VHDL is + PORT ( + reset_in : in std_logic; + clk_in : in std_logic; + clk90_in : in std_logic; + init_done : in std_logic; + command_register : out std_logic_vector(2 downto 0); + input_adress : out std_logic_vector(24 downto 0); + input_data : out std_logic_vector(31 downto 0); + output_data : in std_logic_vector(31 downto 0); + cmd_ack : in std_logic; + data_valid : in std_logic; + burst_done : out std_logic; + auto_ref_req : in std_logic; + debounce_in : in std_logic_vector(7 downto 0); + risingedge_in : in std_logic_vector(3 downto 0); + data_out : out std_logic_vector(7 downto 0) + ); + END COMPONENT DDR2_Control_VHDL; + + -------------------------------------------- + -- Einbinden einer Componente + -- DDR2_RAM_Modul (vom MIG generiert) + -------------------------------------------- + COMPONENT DDR2_Ram_Core is + PORT ( + cntrl0_ddr2_dq : inout std_logic_vector(15 downto 0); + cntrl0_ddr2_a : out std_logic_vector(12 downto 0); + cntrl0_ddr2_ba : out std_logic_vector(1 downto 0); + cntrl0_ddr2_cke : out std_logic; + cntrl0_ddr2_cs_n : out std_logic; + cntrl0_ddr2_ras_n : out std_logic; + cntrl0_ddr2_cas_n : out std_logic; + cntrl0_ddr2_we_n : out std_logic; + cntrl0_ddr2_odt : out std_logic; + cntrl0_ddr2_dm : out std_logic_vector(1 downto 0); + cntrl0_rst_dqs_div_in : in std_logic; + cntrl0_rst_dqs_div_out : out std_logic; + sys_clk_in : in std_logic; + reset_in_n : in std_logic; + cntrl0_burst_done : in std_logic; + cntrl0_init_done : out std_logic; + cntrl0_ar_done : out std_logic; + cntrl0_user_data_valid : out std_logic; + cntrl0_auto_ref_req : out std_logic; + cntrl0_user_cmd_ack : out std_logic; + cntrl0_user_command_register : in std_logic_vector(2 downto 0); + cntrl0_clk_tb : out std_logic; + cntrl0_clk90_tb : out std_logic; + cntrl0_sys_rst_tb : out std_logic; + cntrl0_sys_rst90_tb : out std_logic; + cntrl0_sys_rst180_tb : out std_logic; + cntrl0_user_output_data : out std_logic_vector(31 downto 0); + cntrl0_user_input_data : in std_logic_vector(31 downto 0); + cntrl0_user_data_mask : in std_logic_vector(3 downto 0); + cntrl0_user_input_address : in std_logic_vector(24 downto 0); + cntrl0_ddr2_dqs : inout std_logic_vector(1 downto 0); + cntrl0_ddr2_dqs_n : inout std_logic_vector(1 downto 0); + cntrl0_ddr2_ck : out std_logic_vector(0 downto 0); + cntrl0_ddr2_ck_n : out std_logic_vector(0 downto 0) + ); + END COMPONENT DDR2_Ram_Core; + + +begin + + -------------------------------------------------- + -- Instantz einer Componente erzeugen und verbinden + -- Clock_VHDL : für die Clockerzeugung + -------------------------------------------------- + INST_Clock_VHDL : Clock_VHDL + PORT MAP ( + clk_in_133MHz => clk_tb, + clk_out_1Hz => LED_YELLOW_OUT + ); + + -------------------------------------------------- + -- Instantz einer Componente erzeugen und verbinden + -- VHDL um die Buttons/Schalter zu bearbeiten + -------------------------------------------------- + INST_Buttons_VHDL : Buttons_VHDL + PORT MAP ( + clk_in => clk_tb, + button_in => BTN_IN, + switch_in => SW_IN, + debounce_out => v_debounce, + risingedge_out => v_risingedge + ); + + -------------------------------------------------- + -- Instantz einer Componente erzeugen und verbinden + -- VHDL um das DDR2 zu steuern + -------------------------------------------------- + INST_DDR2_Control_VHDL : DDR2_Control_VHDL + PORT MAP ( + reset_in => v_reset_p, + clk_in => clk_tb, + clk90_in => clk90_tb, + init_done => v_init_done, + command_register => user_command_register, + input_adress => user_input_address, + input_data => user_input_data, + output_data => user_output_data, + cmd_ack => user_cmd_ack, + data_valid => user_data_valid, + burst_done => burst_done, + auto_ref_req => auto_ref_req, + debounce_in => v_debounce, + risingedge_in => v_risingedge, + data_out => LED_OUT + ); + + -------------------------------------------------- + -- Instantz einer Componente erzeugen und verbinden + -- DDR2_RAM_Modul (vom MIG generiert) + -------------------------------------------------- + INST_DDR2_RAM_CORE : DDR2_Ram_Core + PORT MAP ( + sys_clk_in => CLK_AUX_IN, + reset_in_n => v_reset_n, + cntrl0_burst_done => burst_done, + cntrl0_user_command_register => user_command_register, + cntrl0_user_data_mask => user_data_mask, + cntrl0_user_input_data => user_input_data, + cntrl0_user_input_address => user_input_address, + cntrl0_init_done => v_init_done, + cntrl0_ar_done => ar_done, + cntrl0_auto_ref_req => auto_ref_req, + cntrl0_user_cmd_ack => user_cmd_ack, + cntrl0_clk_tb => clk_tb, + cntrl0_clk90_tb => clk90_tb, + cntrl0_sys_rst_tb => open, + cntrl0_sys_rst90_tb => open, + cntrl0_sys_rst180_tb => open, + cntrl0_user_data_valid => user_data_valid, + cntrl0_user_output_data => user_output_data, + cntrl0_ddr2_ras_n => cntrl0_ddr2_ras_n, + cntrl0_ddr2_cas_n => cntrl0_ddr2_cas_n, + cntrl0_ddr2_we_n => cntrl0_ddr2_we_n, + cntrl0_ddr2_cs_n => cntrl0_ddr2_cs_n, + cntrl0_ddr2_cke => cntrl0_ddr2_cke, + cntrl0_ddr2_dm => cntrl0_ddr2_dm, + cntrl0_ddr2_ba => cntrl0_ddr2_ba, + cntrl0_ddr2_a => cntrl0_ddr2_a, + cntrl0_ddr2_ck => cntrl0_ddr2_ck, + cntrl0_ddr2_ck_n => cntrl0_ddr2_ck_n, + cntrl0_ddr2_dqs => cntrl0_ddr2_dqs, + cntrl0_ddr2_dqs_n => cntrl0_ddr2_dqs_n, + cntrl0_ddr2_dq => cntrl0_ddr2_dq, + cntrl0_ddr2_odt => cntrl0_ddr2_odt, + cntrl0_rst_dqs_div_in => cntrl0_rst_dqs_div_in, + cntrl0_rst_dqs_div_out => cntrl0_rst_dqs_div_out + ); + + + ----------------------------------------- + -- Reset-Signal aus einem Schalter generieren + ----------------------------------------- + v_reset_p <= SW_IN(0); + v_reset_n <= not v_reset_p; + + + +end Verhalten; + Index: Top_Modul_VHDL_guide.ncd =================================================================== --- Top_Modul_VHDL_guide.ncd (nonexistent) +++ Top_Modul_VHDL_guide.ncd (revision 2) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6 +###4324:XlxV32DM 3fb9 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f98eNrFm02O5KgSgC/TBzDY5qdSs59TtAQOkGYzvehlq+4+/EUAaZtypuvptdSVFoYgDMRHEMAPJqfpY17nxz/csY/pI/7y+PuLrWKJD59WKhEe5vB/+vODrVJ9MGHV41+2qumDC/v4UaQsAym/tdBRyp+/ZHgIrx9/ScXTw8+Zy5BBthlCNVPIITbMKtJDzLWFXPxPepdy/ZzVEl/ItSkutAulQtKsPNbEohact1qwkmkyQYyJWiyrKPJT+hbTdUhXWrXpNqarWK3e2nSI6SapQ1+zkToa1RGkjqm5ijq6qGOnVC2J10Udy5Oask2P6liW1HFtelTHzqn1fUkPdcdOefxkkuv0xuIbTm+YfXx+Wi2nD/axfYgP/6f0sYJHGQKwPf6ZxZx6OfRA6vXQhOE3ZIiiRGi3mKTaJJWSdMlt8q+dyi8rv7z8ZulRnfLAU0krBYTfpRuRZqURaZKOYRQoNuHgXPTR4JS55tg/ZawLt5csSLI6kmyuSZbxa9desiySxQIoWVoyqMWGRphM037WxPabbJuUWnnacpNNUDrEY612V2sYWFirO6h1nbBWrGokX8k9GyS1lz5or69go0awkddgkymR7AqQILLARswpA9QMCBuHWRXBBq0pPPSwMU3xYt0GrVsW625YYlpmaN5px0rhCqEGNqaFUAMb08PGokBH6lhUR5E6xAzbMkNzV0sXdewJhGwLIZ0GeUKH7NDRYsh2GJIMS6gOQxE2fAAbOIMNEuYMK2Qm/IGEoST2uAYbP4KNuAGblHIKm+UObLYRbPwQNlfMXsIAK+s0xAq1v9vDDIYwU3oEm/UN2JgRbOarsCH78UgQ3cPG1wwFNqHLSlaDsCFritNuB5utKV6se0Pr1nvYbB1s5qnVjpXCh7DZTmCz9bBBdEY9izqA6pg9bKCDzcxr6aIOnMAGethwRIc+hQ30sJmxhNnBZhnAxl2FDbk19oHcoaQ0Ux96NjTYlwdyh5LmxyGCEjZPEcTvIIiPEDTdQZAbIGhlLyGI2md7IBcoKbR9CyY/AhN/yd/BKrZpX6vvalV2BCb2Bpi2AZhWfxFMEk0/jJ9CG9uBKY2rkgHBxDHrRmBCy4tTdAcm1xQvJHBIArsHk+vBtLTasVL4EEzuBEyuBxNiNupZ1PGozrYHk+/BJGrpoo4/AZPvwbQgZuwpmHwPphVLbDswiQGY/L0l13u4GvpGCbFnYFrdHTAtAzCt2w0wqWkEpvkbFmLXcaXYAFd6u788gwGYVngDTG4EJnsVTOQEzEgb6ME01wwIpgWzOgITWl6czlswqakpnkmgJiQB7MAU37VgUq12rBQ+AlNKPwBTSq9gUoTZhdRhqI7bgSm+a8FkaumiDjsGU0pvwETfB2dgSiUaMJEK7hlMMYx1BiY3/T9jQWaEoFuxIDtC0K1YkBggSP/PYkFyBJtviAXNI9i8EwtaRrC5GguS6GcIgwSZ++WZqRkwFmQx60KxIIyTCvvkBYmmeHE7BFr3vPeCRB8L6rRjpfChFyROvCDRe0ESBVpSR6I6y94Lkn0sSNTSRR154gXJDjYUl1fzqRck+5A0YIllB5uAnw8Tut4ewIYRbJ4hYy95P/ol7+fQ61ED8wV3zXy3Sx6E+cKD0Af4q0ZtaiQG4IJRt8a8joxZvGrMjf0EyY31NYahOsNI20EhPX5hHL20YcFVW4AMpTEI1RoEjdgkqBnqFNwNCvUjVrY1ZMNZi+E05qhacySDyrWQvdDoz+loL5/Wx9b70GGUs+lgkPPQJ7zEHFaXf+X25QxrcaoBhWN2wYfU45atJnYR60fvQgNVPX6Vzvu0kJahJ3Mr3PDuQcH51Ao3nHufIuH82TT/DoKhiPf5X9V+cuNJthqFTwHIJ8N3RS5jKHKWVW3X9J8o/ZbF/WJCuq63YgUHm0SeKgCqYKUK/EsVgF527UO4kLya9eQPcFFbIoyieTeKLGm1sjiKWKnTDPwCeH0NAmbgFsDFJYjHLZM4xvM06XHLJCqcrd3Lwo7Ybo1Ve13WJ3FEhOYPhUPPxYef8c/nb7eUJX5Kz0LLLPf5G7B0NINcd5KP2XLd2UZ4ydU4HG52KFtXhYvs0DElWpMMPTkxQEuebND41cnVgbLyKjXz9NVQlY+DKLE3shQMq98dR9Wj5AlPP9Pfz9+zbeookud2o9+nzTOOQor4pLzEYHX6tPBBuf0imwP98uct2CplxzwNReyuMmd42sCKU0PEgkuw1Yerl7k1ofkKa+3jcH/pELsasbvusUs7DItssBvyyuuIdgNEmzuI9gNE31j8gBZHiEYErQcIOvaeWi7bEZe321yGPOufYXMZYrPd76o6gxk4WKDfoOLglA5cXCuFkSeIHivSAyMUIU3RW4lvPbLFMDRr2xPBLb6+KcBaEVhuLTLjB3QnU/LQTiBxBCuPSMEDQRnFKLwSOI/fBArf4RP02ogt9BVVr/KtGUUotxLIS4dTQrdOAy1RrCexCsUKIpRvG6lhn1cTylXtVJOngaJu+fbWgY6jn408Sf0y3fSebvPjK6fSvkA3uEw3PQ3odmPrHTQb0G25Qzczott8jW5PXieM6Ga+wet0I69Tf4PXuY3wya/h0/f4HBw8gvUNfA7OHcHFkwBecbRueLbuGa176xxJtWAJ9+Rq6XKAMNoA8oR8STxi5BVDud0JotaTAvSkXMuxbFooP9NVo8No8ARUtpMknz1RFP1nzUi9DdVT3ZwwY4Nkf9E9zQ6rq41Gn4ezg2jah4RXX3ej+agE7OLX0Gzl6C36uJqRJ+zr55eP7k6INS4+oIvvmgkmms2auKsOncp4YomrfgHf4/eCU/k1dv1V7ILmA5TyOyh1I+Kxt/y5+CDOiKfeJp6antGXrECcoU++jb5dTWCmEQOntxg4OA8F7A0GDo5DwXSNgaDRX9GcwEC2q4lbK3Kl2/P3SqC9+2eCFj/RJx52pERPz0xYj6F6ZPOuXcATmGI9KtAvy1WRcFwlftiJ+IFup8aD5A0efMGDnjr/E2vIZTh+PQGmRbQviI4iWkRzbCSOiDZ4XIxNyrafkNiaPqFlKwZRUxXYBcRWqC1K7ZZffloH8nTJbKGJTiLkDn3K60TDZbK9Hp0cnQJn03QDaaNT4N697x060N8Snmwg4JwceIfzdMLKV8iVj6uckcu9Qa7QzdfDh0e7gJJa63XKHe1sIOU8XKQcbh7A08lwwIPlQAfLAQ+WQ9n5aFeXsfu6+Jal8J1Fb0zgAtw5X0u1rKoxNzzvDmXjssTcojXnkqBb3uYBieomWqcciQa0W+gWBFGzVZLW6G6G5juwFALGs1bdhkvh4zCMh0fg05Ao1UEJEALdzclLYdzJBTrmDnjFB2iHxoFqa61TSDQ/e75Stq6B2feHAdFjs/L6Qtnq6ywcHFL32w0Ujs6oe3NjoZzPmpy5jfCG2+jcaHuGu/sodG60P8PP9mdegq0ewXZ7J9J4dH+PAGrfAKgcAFRfjDSS9xN7LXk/sXFb7weP1QMeq4dyCxAdqNUaYmW5UwgSl38gyykuoGPqIIlskmDhEBZPWx2ZtUW/7CHmPJ2HSPFQi/FQ4Um0RYrJDrmetYKj35YFd2tiUdUilXH7CA+cAN0HAEn0FVQ9bh/1NwoBLyMAXUYAvIwA5ZJUrAOjkU+XERxsqNnT5o1bmjekTHUnQ21hqWwO3MmNfUXcHWaXLzH7QjzSusuYHR3E9+oOZgfn8L24g1k7wqwdYrZj68FhuMrW7WW2VqQenDGoSLUvI7WSFEYkNZdIGo/+tyRVA5LKN0iqByRdL7qiiiNPLPFke+YJ2SbuwChV14EcX2IAT+kaY7MUY7MYY5OMYmzW01v0ciUnBGOIUdJOtDpeAie98iSwdZMA3lAAuqEAeEMByi2rmAv906cbCoD3NIFuKIBsWgBRiQGEbts4TAFTbbWOdYBXsoCuGgDegQK6kuUcBk/7K07ONQ3eTjrRGuZAIhlACXtM8i9DiC/u3PwH+CdDcQ==###3924:XlxV32DM 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f3ceNq9m0eO5TYTgC/jA4hBDO9h9j5FA0wCZuNZeDmYu5upilRiq6X+fwO2HxiKQayvAtmvtyWzI6/plf6dfv9FZqleRBj2/ovIaXoxLt+/aKCx9v3HesniD75uOr//IbOaXgt/pzL9IopM2F2/f9KQhKf/ZzG/YqMpFxChAwhe4g+6FiyrYEk1Sp4WlGzfP9lkYpdYp2jsYM37/YuppYgMwe/nGqpIQk0VyWSba4gSBc9Tq2J+ESFDnatXIDjsBS8oWKPgGQUvlwR7RXabYCfcBHWwCfO024Sl3wSvUh1bi4R9XdjBB5vZ0Qcrk0/y7F6eAnkUhfCBkH+DcGmdv3+knYxTff9IYlN9qgysVKYjEZf2/mDxIPz51+ftYqmcvdLBeZcWpbt5xeFyK+wdW8VzVmTHOcRKItlUZKSzET/Iu8wg/vhg0uXutA2SOlXRNDYQLImYHS0DZLUpTXJbkufOYWH+lT7w+4NIWlYl2pKxxuTNkK0PrqZuhle0TTgdlHcVEH995P8m0XNdcjw+ZcPioUl9p64cdjlP9I9VNp6Vl3qJl/9dv5ny7/JFqZTxUFGZvxpT9dga2R0yo9+pSPVFJhXZotjMkv5IslxF+yKei1hfRN/vOC9yDhju5vuEUXn8jWSBkuWRZHNRstjpBLKLu0bFiY7ZFYtsX2R7TVY2fYD5GA7cCRhFLmEPh53oJY/muiI35SLftwr9BOKBZzs7YZFxM0l2gmDbed9WYFva2iaVqrqRPlE6nz9y96JS8SeHWoK1oHBl62tlgUIqSqc9VcomFyplrdQGK2PR5JLWJEYw6/rhkuJTmYXRTlgCy0dUjSzIQkUceLKJVyqXL/0AqdySXK779sg3bXzfHtVYZ43Acp/KWZ4Q6ZaeSVf2jxb95nH3TdTv5UC/VTJH7I5+58ljkc1F/TGOSwcKbLSf7LV/BQRyBgQ2AoJ+AgQ+AoJ9AgS1U9UOCOpAVS8DYaO11u21Vq+xoUfYMENsbHBh97hYzcV/ThD5BYLYqwTRGlVQ9yoSZSioYMgO2ciCqs6xtlrIqHYMKtVarVfliRtRWZI68ias50M5DHUOQCEFFNJzLw1hoNroDJWbVzemfFIYqkrUKFH2e9EwonVfjjjquMZ6R0fr1TrTnhqTy6deDnAzHrTIOxJ5w17qgDgcibMljdmTRu1Jo5E0UeMkSR8usWEescE/YYMZabC7psF2r8F6rzUGtWatKstFVYlHEg+ROTmS8/rTLn37drS178u7w2iaHDhvBoxsM3NzPffp++RpkV4cniAy+6mfV9G7BTzTdMDIS0fbRaaDg+TRNf3J5hJARdd9ZMrM3iJFw4Jh16/kocOPfMDi5vuDiJjjl1ZdRCzz0T05g5TL+2dQ5jmf2CfK5/v2SWt6FGz/HSV7COXKP6H5rp8c9HZ0ddbK+TjupgrmzcSyirvhY34eJuvs9M3H8TdVDONvvoq/rw8gnRnE4Wy5FodvTJ+/7DxLb89jdsrFl4N2mcPSk6Cdcn4tatem4iTt/yqE1ZpAzbwOe9Fapi3trJF0usS16ZAXpOQWKUpNs602GGxNOrAdkFocnwbMcXyaUxfHKym6BnOoDeKPj/SfJLoG1kl/ywTyIHkCHpyAooK0TrMz6kXroXu2z6lJTgeU+dNCOkwW+JosKM0IRhpVRqnztg85Yqe646VFBqWH0Mdz0pZYUgPlw3SpATWz9mFwbTW3oGbfvifufKmMShaNygDDK41lVzBsu/TAmL3z1WxkbCsvc3qUWKCcPeE0HXGa3Oe0LA7qSVKUhWtJUbeG8zKCM30OZzeN4MwRzuI2nMMIzn4I524nZE6bnVKW3qCsGFF2ukZZJYClbgKtFE1lF1DZBSpnqIzaIJA2M9CGYLTjFdZKqKWQR2m8XCov0/CNl4WEGdgAsrByKnsmL5XJSURjMrqp6Vh3NJc50KuiwRa4tjxAMQUUr/MvRbGhe0UxhTmKimLpPLSiOEhoG1wNjlFt89cmzoi28ysT13F4AQ7n3h2HMdmUx0QzmCirB5SNrsxFyu48XP6ph6u/QFl3nbKDbA3tPKcblB1kayjzDyhbwpEzyrohZXu05mu0U7SSb0ArHaF1eu73ejpCq73k96bEUE9ZOaBsZ8KuU1YNKJu/1gXKlnOaccAQGhygoRAaS9eqQMMjlSWSCby0TeYHM725U5/pNUAZsnWXHdTQNX+kR8pxnAr4q0EhvyyMSFdXQcioPGJhFN34ioK1WeESwfAI3iaGg4LhaehPXQv6aY/+Au+6kXWTZW89mv1JEor9ob39iRDyaL4cmC/ejJvBWg21DFMKxo8oy7/sy+rjJPcYuOILwFXXgTuPgGufAFeMgKufAJePgGtu3PXrfDV1xl65fAN7+YC9Mjx3a4vzdsZefePuXwY9Yq+5wV4zYq+66uGCKxX3tLLENNDMUMmgUh96uALUfD7ycCGitmLn4SbBhTB87eFyYBQ4z0GfeLhJRMEcX3u4HvDLVx6uZ000wJu35YEdEWBHxMbDnbvu1VjB8oMBY+WxlcBBRNtguNaY2uZvPNzQdv7Ew801xXrwrYe7wNLF2sNNXvk5e+f/C3sDuc7ewK6zV47Y+yj1q0bsnZ+wV43Yq26xd5TvlQ7RSG6zd5TvlfYb2DvM98pb7B3lcNmdHK4bsZdfZS8GuIgG19groRKyhQGzhR0EMN3oNulGvDNNG9pnez1mexWiybTxAU28zW2NJoj9y9i9wwyPINK5XhFXwogSR1RtUUBcBcRVG+L23StxwaQEt3tOljesGASx9ntFk1N72xO/F/LUTqz9XnhSlslUjZpCkxcwwRwwwSzbVRobsVf877IL4Qs53HA9h5sDqlPgPsnh5pDsFLhPcrjWjIArLmcXDp5/dZT1zyl79GilUdY8zy5YN6LsfCe74N2IsjdyuDnKPKXs1RzuDE6sBeZEuZjDxWs0CZVuT9nMrXKpozaUhTcjaUN7ylrIo8bDXJlnXRsf7tREm9vmFq+b2Jqy8BZErh8GSAtcT2nMOqJpi6qUhXRHntfqEq3vXihrDFyF+T1l04aVyz61pqxqcmpvd0zZJKHcBqoNZTF0CEBqYxplMewIEBsY3SgrRzdl5jZlP3+lYL6QUvDXKWsHlKVPcrg5vXVGWfokh2vDiLL8OmX1iLL6G94umBFl1Te8XZhGlGU33i5IHwaUpTdyuH4ZUJZezeEa5J1FfEBq0C8QFlvftaqMgoufuDBglANGuXUOF57T5U5dDleDI231FpaQ3bVmk8O1kE5Og9Q7KEgn+wUBDVljNx3ncPOIxTSY7X2/aLPCJaLhkW1iOOg+h5u6FsqaFWUzxutG1k0OJ5TVQFlzmsP1wFF3lMMFK2Bso6wdUdY+eI/whRyu/QJww3Xg+hFwn+RwTRgB90kO19ERcOmtpwl2xF75Dex1I/bO38BePmIvuZVHmEbsvZPDJSP2qqvsRap6ZG+AEJfg/RnpWlXg4f3RhOwNwN6wYS/cZjm6Zi/cklm7ZS/kMK3bsNdBCjYNUqeCKViC7IUEruMn7LXIXrdlr2qzwiUie3WbGA56wF4L7HVr9rq2kXWTpxP2WmCvO2UvfCgTjtgLdDe+sXfJfyymXuEAve4UvbefgIXLjxNkzjufsvNJDtaJEeGmW4TzI8LxbyBcGBFOfMPjKzX6C9Xl+uMrOsLanfQoG2Ftvhq4W1BTfBvEmg6jY+ehkh4E7h4JEbZ3JJCsdGr9GFZ25TAq3OjTNqPNfc3UprOhINzFOLF+aAU3ROlPNSoDRVsK4Bh6p1YF7TXzuEaVB1SFNapCG6Siip6gygOqwiYYRxgFCOgN/n0A9+lCib/ES+9hpO2nf7l6/OcACTr2qsPGnTuHDnnwZyfck3N/jYT77tpcrlV3L/7/AwsgL0M=###3564:XlxV32DM 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dd4eNq1m0mO3DoShi/TB+BMKhPe9ykMUBwAb9oLLw3fvTkFB6XEUiWrHuDnBKkITvq/IIMy5so+/4e5Qg9sn//BXG4PrJALPyVCD8r25y+K9AM9Qp0iDyz2/fn8TZUPRc9/O3Mo/CDhD/obrVV8AhWPwpvm0oNLjl5cut4l5s6GX3j0yas5fv4mDqdn/4RnXWz/7w9mzCMUP38k8/jr3x8uZKkMvQxNPn/S0Ld/f5j1pdzi4Htzz/yE8smI5koueDHSMpXz1lI2Sk8ko+ioeeQSBSvFYkV4uFnFivQIcST3vtSGX3sqLLWx93Q3/dBIcElCR8KcWxpmhz/EQ/8tk6Ly2qkH2UyY3TSEOKUs/v0rDKCbbR0WMBSpvkjHoh31a0Kfz7gU/mUpNKsvh4pLQcqbYOMPNj7Ky5tAUH0RMKrm2/NXWclfxc3vOEWpIM4wOKavjgU4xmeO9T3H6RE6OpagBg+OpfMTNZg4c2ifCITOBGLvCcSPAvHkvkA8hTeTgEA8AYGkOUkCoYNA0qQlI1oFQqtALBjhYLRHgahUrvvyKpw8zaUH4AxX4dCupV44lnRWRTi0CKeTGynSEDSPFlVBeRAUzaONbxIPs8aCcLYT4dgPhbNdqcSL+yphE5WQFZXwiUro+yrhRL68wGFd/4tb5Oj6PY0cehQGnwnDvScM9QlhbPAOsSoMBcIgUOn4KAwGRry+yxAEOCkRIk5ZHzmIbC2VyBGfKALgncdBAKyzKgLgVQC073wvAAkCCC9lEQBvApCTyOHuCWCMHPurJkjWBLqvCTHRBF/RhJxoQqxEDnEdOQi7Fzn0a+Qwo0DUTCD+ra2VZ+9EDlEFwkAgFPAcejkIpL7rsgpEVYHAvivMXx85iOnLu8ghWg/AmajC6VsahNNbFeHIKhzeD+o0coRfRTiyCWebRA6/EDnkfZWoiUrkikq2iUrUQuSgH0cO+Vbk0NfCCB7eixz6ncihqjB0FUaNHHoURjXa6rusQRgUIgcdIweVraUSOWiLHL3HQQCqsyoC2KoAZN/588ghQQBbFYBx15FDow8FoF8jh3rVBMuawLc1YexEE3pBE8ZNNLEvRA6rJ5Fjuxc59tfIsQ0CsWYmEHxLIAYdBMLfiBzGVoFwEAirG3szHsp3MHIgkPhEEUg9seshclDTl7fIYXXrATgDteXFhZaGw7rtrLJwwiMgnK0f1HnkwEU4ySoJhxMcZk0F4dgT4eB3tlxJOHp7PdLrD470JBXho+KY8RMV2ZXIgiYq8isqigvFL1Rkmor45/ZfabKReT3f2+vzvXUvgq5aI+5E0OebtENXXtS331RffPYkfSbqs2RUKkjBoqpUSJ+FnzUD5WvtDjrmNZC4Isk9l7O+vNN31xRI0oG+eT3Q22Bko451goXry00s31L53pc3HjDVl3c8sG0k0Lit21Lc9Wzgge+sSiBFwINGEd/xICqeJsXrh39VvIrvYToPhr+lOVH+qWqxSDE9iEESBj/iK5Ti5UmOjtYXX/bx0u3XSqcrOTovrpVOycIeEvGzPSSEMnISyprUOwVxeZJEdNDBqlJlqpd0Gi4Lk738xkK60r+8HNHvST7HF7/tIKha7/w9v0yehfB+7+zzf+5kB/3hOVAgfJMRYQVez7o7rAA9S79yera0eczBH37Nuu4K/NX3lrOJkz9YqKK+uABRxj+i3/hAroUcvqSlFgmozXKnuTLO+DM5Sb9+pv9HDwh2KR4Ov3HOYAsD23Ume8TlRaPZqGzXmWzdA2vRuh6XPrQaxJx6xlq3a03uMwwIjZcSiJUWg7JLi4i3IecWszrLYAbAJR6AeQYcpI1yh9M1haSozVh4efOExR8/A8PydLU9EORd3V4vMrpOZt9IDDcanOsJMtuNxl1ksjkyWYprVxhkKxi0EwwuJJw4Nx8dpSc4uCCivyYiXyCiEtdEFAtE5P5LiXjYYQlEb++wBPK36YnVhJ78DXpuE3rKu/TcAEFKAJ62Rs8N8BZekVKrTujpgZ5KHOmJ4V7J20pPD9tKgWCH6E2tpXVbWXZqcb17tqblp9llIR33rfNg7drARrbyvQ1qZCvX0KIZ2Jo0R3M3oUXTJgTYattQB7b63ryw1QJbtxO2+sLWuCaNrRneFGaLQOPdhlOgCT3tR/T8IEk5B6mbgFStgNRPQKoXQCrIl4D0PDPJlbxmqlxhqrpmqlpgqhBfu8v0B6by+0zF93ekWE+Yur3B1H3C1P02UxWgRwEk9o6pEmrrhlC/MlXJylR1zVQ4jIu6p+yZ6ipTa8qtfdIiBqamT1podgmftIjWebBmbWAjUwVugxqZKhC0SMaPaAi06GqLpE0IMNW3oY5MdZ15YaoHKu6vTI2TnZmqRqba5qdY6wNT5YSp7qt3pByhCUjN+yDl6aB3BVK3AtLty3ekarum57ZCT31NT71CT/O9O1L5CXrS+/Q0E3raN+hpJ/T0t+kJmzClAQe2o+cGtRvUmhN6bpWe+oqevJzif6Q5O9Iz6hDoKSv/oGvCjPQsG7zoElhmWufBem8DO9BTtUEd6AnBIohsoOcGLaLaYjchpUWE21B7embIgHmiZ54NAh0+0nMDeuqRnr75KdbmQE87oaf/xh0pR5OvEBlaAenkK0S2kuEU/lt3pPs1U/cVppprppoFpkryvTtS9QmmsvtMdddMZe/kSP01U9ntHOlmADAVS75jagXTDrXuhKl7Zaq5ZiqtTGUnTCWVqer44Wlc756pkgBa4MPT9AR0HqxxG9iBqa4N6sBUyCsIPzK1woxUpvo2IcBU2oY6MpV05oWpFKjoT5i6A1NNz9QMbQqzRaDx/lqJXzN1Q5/ekX50tHeTHClbyZG6SY6UreRIifr6HCm/pqdduTWa5EjdAj3J/r303D5BT37/hklO6PlGjhSpCT1v50hVzYLCkRip7oapXtXU6xZ5kiPl9YbpOkfqao4U89fzvGs50u34dXJc756epF7n1Bwp2VvnwVq3gR3un0Qb1OH+qX7arF4/baa5m9CiahNSzvPOtqGO90+mM8/neQc5UqROcqQc7p/ESE/a/BRreaCnmdATr+xIP7pscpMcKVvJkbpJjpSt5EiJ+84dqZzkSP0KUyc5UowWoErx9x7z9SegKu5DdZtA9Y0kKdITqN5Okio42cpKCd1BtfIHkqRoO4FqTZLK6ySpa0lScQLVliStH+7Cx+lxvXuoUgxsqUlSilvn4bNf1AZ2gKptgzpAFfbnxI1QhSynq0lS4tqEAFR9G+oI1d68QBWSpEifQBWSpHJMkjrb/BTrbYQqJROokq+/tp8kSZlZuW2aJEnZSpKUsq/fkk6SpBiv8HOSJcVkhZ/qe/m5f4Kf8j4/9wk/30iTIjPh5+00qYKdn4Q0KTIdPyGjKCEriPYTftY0qdTXl0wtTSpPLplamrReE7V/w6BGftaPomqalKrWebAWbWAjPyltgxr5Cf8GKcps+FcT8L2Rr2lSytqEwCUTbkMdL5lQZ14umSBNiswJPyFNKsc0qfPNT7HeD/zcJvyk33pxn9Ok/wfrL/0k###3916:XlxV32DM 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f34eNq9m0mu3DgShi9TB+AsKhPe1ykMcBJQm/ail0bdvTlFkJSUTL3UcxdQToEUg8Hh/xQcHnmQ339RuegHVUY+/0OlJg9JniltfVBN0+NCyIOL9fkPC/RBHumXpd9f8SWSE6haQ3r414qNxwcR/+8MKzDMzgybS4Ylt/GBjYaX59/RsK/mt/JfwEpIwErs8x9OTCwd8zSLZa15Pn9xvVXriz26HapdysHioh1aDNGiEtnLauYXVUuobnsNht3R8AaGRTO8oeHtmmEeDv1hydX+iEO874+t7w+qSPKbjuYlFqfPX3XM0rtUH99V+C7r3pXExwc+vrrA9KAn00Pys+lR+ifZC0d7GuxxNCImRv5Llc5z6/ePNFqxD54/kt30Qsk1kGsh10OuZMkqL5lpdJ7ZSH76mf9NFigpFpI6oh/PH7nP0lPKJQJyGeTG3i+5krtaeRzvOGLPnzyOckoPpd5kMqnkWd4A56G0bw1Lkyj6tDCTc7pGYU5uEV+hRltrjDpL6RZqZFhj1yGlxqL/2tQk41hci5zBuuIpo/YGA4dZ6oyFk9afUQalO9PDT764bIc2O7W0zw8/ueLPf5MytjgZ9cM8tt91/KMkyuxgq0jq4kVdWZtp1le1maX8WtILQzyb7n6lToKH1IPPSDxxVDiiVNxBqZygVN1AqaDfgtKBn37CT3mHn2HCT3WDn0J8Kz8d2fHTf4Gf63V+bhN+yq/zM5PpFT+Xy/xEzACCKOn4CQiLk6TiYjvhp0d+htf8lMjP9YSfAvkJPJKC1crjePf8zMPPi8lKs/QGOA+leWvYyE9BWqN2/NygRjrwUyC4BNZIW4cAP2Vr6shP0RWv/JSVgNnhPT898DOM/OTNTuXnNvJT6Ak/5Tt+giDM+jyglL9D6TJBqb6DUj1BqbmDUvMno1JNJlRdblBV0wlV9R2q+j8blYYvUNVcpiplE6quH1CVT6hqr1J1BcRowATlHVUBM5pALjtSNX8lM1WjkZdU1UhVc0LVBamKcaWAgDmO90BVD3DRyDjfnIfSrjVsR9W1NWqkqtBQoxmpaqDGBWs0rUOAqro1daTq0hWvVNVAVX6kaursTNU0Jj1VZbNTS7MdVcOEqur7o9J1glJ3B6VmgtJwA6WSfHtUqtmEn+sdfvIJP80Nfkr+Z6NS9QV+suv8FBN++g/4KSf83C7zE0K/OFoVCLLxc6WQyyBXnPCTIT/5a34a5Cc74eeK/FRAQAmVx/Hu+SkxODNAM9k5D6W7hu34ubVG7fgZoEYy8FMSqHHFGknrEOCnaU0d+bl2xSs/DRBQnvCTAT/5yE/d7NTSYuSnjKPzWCJB/Qk/lwM/vyMata8Rqm7skUqp/mjQKCbQs3egJyfQc3egt76DnmIfhYvUXsWdpOo1wtQHG5N0eY2w3JprCBOgZwmaXDqEwepU48pVnSBMIMLkAWEOdG0RYRYxswAy1hFSa5cOTkEZ3Rwe0SRlc3ZEk4RGRl0MaFLABItoUq2hgCbbmlAIVNzZg0cAeOQIHtMqqeBRA3jMsuTATZ2AJ6S4jS1vV8FG90k6J619ks1J/VQ2BoGVfukOXGlyH3eYjEDp6TS5WZmMZlGvSSbW9XOUpc55GQ2Kdfk8HDQZ43IPSbDcYqwg52SMSbZPygOSTzcwyeUk3yfZHiRmOTm1IOhL25gg7MimgwN7Rm0XGRXlymrEkQYU5Ao7R55SyExrMpvkmtNJ6NNRxqVROR1WTqZu0KVCFjJdLOSTJk1O1326S+lrTpd9eqrc6JzO+nTUdhnd2hKo3NXKy6QCz7poo8xjKJW1nl6pWle0NjRLI2u55KZe4Nb1XZfkzZYi7zXHFerhjvJuYcUredupSmMS65NYTsoG48hnQl8UsJ4JWN0R8DoTsPhcwJ6+jXJ6z6cBjhvVGA5k6NTYDhu2cE2NexwExMEgVMa/IFQBsw23Vhhsf7gNNRGqtuJcielh69OTtizL6a5PR2G7sPbpnbBR8CtqK4CwafUsDU8nyDpaxeNSKL9RBbl2FgdB6q5UFeRaBdnJWHdf1NQ7DIQaJVCFWrfz0/DG73ickeqxHgWp3wrSHON8lj+XTB7VhgfEYhnUZmZq43fUZmdqu3E9wujT3ZNieRHNZ7JNdDZ89dxm3oXlvcvTuDyM37wcMl3ZWkiTBacYhqhsQSnVzORrJwEH69U8mfJszm/k2ezgiCX12fBNQv3B4tvUvdWUaTuLgwRMV6pKwKIE1pY5SkChBCRIwIAERPxY0ccaJRCOa904lu9iTnsp5nyxIt59xcTxK0bxKzZITNjJelnYG1GmsG4iG2s/l41wJwchGGXaLrKj88/ThShzWKULxyYfMWumH7Hdx8vuNvz2FftjeLvX43p9W5DZL2gXlpfWoXYt7pAx2FSyTdlwqitg5Zs6qvtICq37dPxICuX6dPxICjhEKelIiNL/1bUi9vxGFrvQAQrRPsoVcBOopGOUK2CnsaQjUcrsqi2ESihUYrvOGfbUrO1KlT213H+sj2NLp7U4Vth0vmAiM07OF4R49d08gMIiKA4r0u8Hhp8Bw98BRpgBY7sDDD5Zllp3otvuaGJPCYdiPSh0Rwsxo0X4v9JCuuu0kM5fpYVYUPGiV3y0AZK3vnIiuVApIh0KImAu3kZbUJh8EKx2fXoTuA3N2KBJx5sPoGQOSlamt9bkb31XqAoZbrqVIYWqqkUBFhfS90Wj1qL79Ea5RoX+Llz0LPSe4TJeLKG3AxRNE41MKCLfUWSPjtNTy68sk3uERFVvE144eoMXjkx44fgdXsgJLxy5xIs9JAYyqAkZHLtEhoqB6+viHhYDGcwXyBAuk0EjGdQrMmyofXMkgyOYCzcYhEaFyYEMaunTGxkcacZGMsjmA+hYoo5Vb60jw9YVKmRwBMmguqqqRYUWXd8XjQya9ekdGULfRY0Mi+k9a2TQqrfTyEAJNxkNcTKRAxtosLgqib+VBTJ85UbDy+O4FfbLLm94eze5/eC2z0Hh3eT2g/OfcyJ2r/vu6w+U5Gs66sVRIIHVDV/IcBQIw/b65E6T3RGe9/Rsr6BuP9DtZPvh/ekdu7ozbn1+eHF658KXT+98YK9P75y7dnoX4DJTspZP5dKJV4JJgCuieYTygVZqAZzrEfhzhJy9O7HjlUPe4bUCBkcAcRLViCONR0cH7+sxWJq/dXfPU6iZteJjxd0hXZZ/zePDVn6duby4VIyXd6Bd9XzCGfB8vENQxArlMwy9q3cIinPdUR52WjvCowSOFkuOjF6nf/ISE48EWD0S8O0DQSQfmquTS0zjKotDLzNoR1tuxRaW9VZsCz3BoTvB4LVrs/Z0A3N2USFOCnp1bzO+y69TdLKh4+wdik72c9x648zB88kuKA3XdkGH04Y4N/wMour7IBqrCseq8IYFkViVHG5YfMRrOeO1v8brYV3oA58w2HzAYDFhsL7IYInUEgGIhNe8QgcAD7l8x2Fes8sdimxnRDKBPwVInTpAVwBEHEJXNieAQvAXCtV0d2ciQmbrHNwDOUC1w6rTewbVWqyWt9YBjR3Q2O1obLvilcYOICgOFytK16WbFaWLG5cL8KulWp4Pu+AF3GhEBjDSI5wLQDjngHCHe4gcj5I4hVw7Ar4NYAQ89DKyPsuO5+12cx7Zhu9A+JvrulQadxnh0oTrCJ9ssbnlDsInO2xO3kH4MkO4+wzh23ER3hAuPkZ4I3e+RilfkZt/TO4G7HUGbHsJ2ONtYB/kBNjqA2CrCbDFxStvRAhE3rZHnpCAvOFGWsyA47Q0EANDvVdAIY84XACHslGYg+lliG570G0AOklG0PmuiorMAMhTFZlFMZm4496i9xqKB/RwBQ/hnpv3ofMDPkaSjB+joEjXe9hI+N4p2XVTzP0feX4coA==###3668:XlxV32DM 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e3ceNq9m0mu5DgOQC9TB9Bo2RHIfZ8iAY1AbToXuUzk3VsTKSls60eE43cVqsLQQFK0+URT/vcfzi83Khdx//ubSm1v5Mb+/MhXzLP7D2ddvKCl12Ovh15fe51NU/mfOiH1eZkvfvKFp+lEyjKCEhFuXPp7vJIkX/1M//v718QudaO3Nf7r//xDFYndq7v/Q6Vab9SH+79xYJQSfxdefpUtv1rF3zhwZTe6aH2PTYZ0TYbFJrq4NQ3/RRUTcKHThaELT/bR+B/5UxUumt+rFULdf8XVpKF/jbMhXohxqLz/N6oiN8uzvduNrpTg9O3+b3RUNrWK+RUHkdxAl81Xwc4kF4+CVRWsqEbJJKBkE1dKdL9Sc7//4msoIqOPk1o5yvRVJiWsyuSqGet7P4vyW+T9oovy1ejiyqyB7TUE1EBRg0QN4SUNzrmdWwxBt2wHbpFk5xbfu8X59LzwUSR42rKDWyj50S0sxid5617eCvIoChETIb/9AhGWXBptTVG0Qnj6RWMvhV4Fvc55CK/Ym3x3L2Ly5c/8/xSFYitCkk+jg2LoRU+m6bZrB8018onQnV3pBkWBMXBK39pZhX2i9CkQaqqy+DQnZRpgEW7p6b+XEbAkQEqos9OoGCxgE0uyFSfdeuNDVJebrn5GKmQBvqmpTFJnTEpCKpNYx6TfkQtLXWAiRMVeKDb+NWpLzNC35RZ2wGI0BRJT+S7zVRyByiRQ6bV2bfW3f271umcZz020b6K5iT0Sj5vMSaPWCbJYfCzfZlbywE7ygpKPQknoJyWLPVcUSpYgWQU/oaFNXiCmeJbU3YK4fsjWk0FtcqcVYcMkP9B6AJuAWrHJ3cGAHknVlp7YC1e7ncggOyVNOxHFsdt+7IJjWRubnuQaxumWpef3R55eg3zhNZDTowK9EIsbBEHyTrQ4YYPndtG329TOcjvr201qL3JI3474KU6vphUi5BGRCHES89ApqnKtc7vt25NyveV23bcn5XrN7axvRxyV56yuHJSLqrw83mBZotDPGMqpYw3drIyn4te0fm5s78xEHKYKL+KNv6nIC3vAi4CJzQMvABIP3Nj6pu2+Q8dxGhSNoDMYkCswYBMYiHAFBssMBnQKg10s2n0s6vuOC2bkwjpJQgR9IwmJAWZeiHT3QqRjxDCMZdciHeOGYq+BSGeAgbjeIUJVEwlBsmKEIh6WMUJF394itJFoGSIUGZTbuwhdmsWgfMEIZZ1lfYTmxxxm1QhlNUK7uKZdTpDusz7d0al1X+7o230SrJ/b3AVu7g+hvU1CW7groa1noW2uhHaYhLbwGNpeTvZ5fZ9E+RdbviaTLV/YAwPe3fIt2WPmkQnheSYI+jwTBIaJhqgXFJkgMBw2ZELY7f7RUYe7f24/2P1z+8Hun9sbWzRpptXwTiMed/9wsvuHk90/nOz+YWRLaCsHtgRki+4sG9iydbMqW/Ru98/O7Hd/e7r7U+vPdv+Dt4URIO8mAvG282eLHnHsQYFE4Ni1G6s2M6PQdoVCdkah9QKFNJ1RSL/6ttGj5uVcQ/NZrkFezzW6fT3KHmIPw8Ji7PHdvh6dc7iv5/aDfT23H+zrub3FnsYd2qByirFnO8uG2DPdrBp7Fvd13Tr7d/1F4Hu8qO/xZVbln8BeDr0G3vJtqrPctpgVULIL3MAwJ2hFrVKWnOYI+11/Wp4U6tlI1eskvRcbfT/69KrOo0+sF9J7XXK1k8qnYM9VPvVQ4qPreeFTaAhovrxb+HR0O697Cr2hAvZm3dMGf4SB/0QFrqoJ5R/f/PNFVaLPNMSztYN4e9h5uVRs5OV6qc7750m9VKz+uYKp1lDNjLcilw913o5zRVQD2dKDUDsZdBoXam2QrrVammSMxdIF6p7puYeUCQomNlQ8pbvUAbXcNF4mFablEWAdzHbN8qGiav3azB7qqdbXV7AULB1F9UZAI7wd5RGw5KKxxG5dTI/TgguYnnFa1svA4LHgmt2Z6q3Z6a3cqpXpBqRaah7Ql1KxVpxoVhSskIJyI5oZVTkbsicbwoTC4vRwaJpNvURhva4Tsq7uClm3GVkvvF05ckjWJyFynOJ0kGVkBtn1OmQZnUFWXYasI+J7IftCiScfpD0JZD0B8mrfALKZAVk/C+SamqXbVgFkGpA1dBLo1HsgMwJAZvQRyJIDw/AtVbKWw1noXRHXUNdyBHYDIoaDL4LYgde/PAJsh9m8rWvAtSOkLWrEdYDzKzLgugQkL2aCRtocArje2lJHXK/d9IrrDYhp9rhOzs64ZnTAdd4POHiLgXLMmBvPGak8Z3Q4rndEToAsXwby9gaQ9QzI2xUgmxmQ1RUgq88Cecx6GZsBefkAkPkMyPIDQNbfC2T3ApDF80C2MyCvbwDZzYC8PAtkyDMZB8S4BmQ49GcMOu0BkBkCmZ8D2SCQxQGQW8nRIVIhz413awCyBi4ZxKNutsPsra3rAchLW9QA5ISrqlGNQEYSatSomkMAyKYtdQSy7qZXIBtAqjsAMgMg8xHIW5NTZ9sTIDMAMn8AspkAef2/ZMh2BmR5BchuBmR+BcjuWzNkMQOy+ACQ5QzI/DqQKfleIPsXgCyfB7KfAVm8AeQwAzJ7FsiQFTIJiAkNyB46MQX1B0AWCGR5DmSHQJYHQLYIZPyEk4ByOpzOlNvPi8iKR0qa7TC7W9cDkG1b1AOQ4W2BuBHIDjRaBLJrDgEgu7bUEci2m16B7ACp4QDIAoAsRyCbJqfO9idAFgBkOQKZ0gmQ3ctA1m8A2c+AfKkYHCZAVheKwY7yzwLZjEBeZkBmHwCymgGZfgDI6nuB/MIJtFyeBnI+5T0F8hs15Hx6dAZk9WwN2VDAE+R8miKQDb7dL9BJDoC8IJDVOZDxs7rosz2QPQIZkUoFAFmNQF6AS/j5LO1sh9myrWsEMmVtUSOQKfiC8gHIOSB5MRM08uYQAHJoSx2B7LvpFcj1k9xi8COQFwCyGoHsmpw6m5wAeQEgqwHI1m8TIPtPlCzEV0BmEyCrSzVkPgPyhRqy9eY7SxZUz4BMPnBQZyZA3sL1gzr/2YO69JVQD2RJXgCyej5D5hMgq3dqyGIG5KdryIg9AzmfaBkyFGIp1gT4waGexkM9cw5kjkBWB0DGLyclAM56OPLz45GfR75xOPLzvtkOs11b18ORn26Lejjy20Dj8BcUJSB5MRM0muYQAHK31BHIrJtegcwhxxUHR34ajvzMCOTQ5NTZ/BjISUI5EzQPQJ4d6oULJYsvKCxmFL5UOJYzCl8oHNvwrSd51E4ovPkPUNjNKOw+8LnEZ07yRvTSF9C7Po9eOUPvO9XiZYbep6vFUDul+Lq9NPRCQhmflNopD9BrEb3uHL0S4boeoFdgL8XvJRh8bSHGry3w+E7i1xai2Q6zeVvXiN5A2qIe0BtA43B8V6KQFzNBI20OAfTKttQRvaKbXtErAZ7LAXotoNeN6OVNTp0tT9BrAb1uRG+Q539sS8g3/rGtXpcZfS9UiW1Q31k6oH7GSPsBRoYZI80HGGm+YqRQ/LmqwcN363J7lpR6UzP6vVOaXWf048/SD7+8ChDPa6Mf/C0rxcxOHdDPI/3Cjn74NdmCfGvfg61AGzPyTXftYBPM2Zq9D1RbmrEPHyVIkBdfjP8HBoM8yQ==###3760:XlxV32DM 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faceNqtW8uu5CgS/ZnezYanwZmaXykJMEi9mV7UslT/PgSPAOOETGdXl/peC0wA50ScAMxV+4Nvx/Mvqgh5cLE9/+abeJBH/K0D/P6HbsrDw++fVBh4Yr/+G5/2R2xinvBoHvAOvMAVxxfMI1p4/qBbCFClNhOrRKrSD+70s1iRisRHqI6PPDaAn9CAtc5UHKSAqi3bYkes4qlqS1Wlw/KSz4O12F5G23GWuUfoO9Ufnf00A3zV5RccvrANL9j4AreuH4XM1So9wShSL1yGfhYJEbmpVEVDZ79WbanK0VKlNhu7NvSZcUtoJTRt9wJ36vmDO/b8/dvGAhiWjv+OX39FgwDxxp/wCEQZVsnWDgqVfgj1/Ce2TqzDCOqDqg+6Pvj6kFzjP0BVLokkwwP0nlCN/5Nf2ToVwTz/R6Umj5D/86lfcCC918HwAGMoPcb5Jo+zVFh2NWeLOd6aCxId1unssBEjbA5P4tzcYXNVBsKVRkM0GpJ5ntNIAMP0avi4GKZqt2iZfWbZQBE/W/Yny9kcT0TYyogrc0/45yHyq6GAhjQO0RC0Ka4o/g1hXkxm16K9SUlIMalFaLNuxMjmJmlQYhyUJLQOyhyVkM8lyeoaRHG+VZJiLy8kKZYOkuSqJEU3K5IEVqokubkkRf5nkhR9rkgSdHiSJCsx4gNKUuyxSpJVnX1UnNAkyW74AhleGCQJRpElCYZ6kqSN9LM4SRIjnf1BkhgqzoGSFHFrknR0LwyS5O9KkvuTkhT+rCS5lSS5t5JkVpJk/oUk2ZUkmX8hSXZfSZK5IUnHSpLsV5LkF5IkySeS5FeS5O9LEkYKzBclyb+UJD9KkkdJcihJR5Mkv5AkO5ckg5LkR0nCRYjdmyQdKEm4EgH7VXHyq1mSXJMMM7wwSpJBSbKjJPW9DJJEO/uDJHFUnNAkyXWSFLoXzpKksivyCPZFfNhZdPxJWSwl+4t4qCFMo3uhz5lTDC8ijIqrptTAoEp8GBg4r2k87O/i4WdFBgCPo6qOp47R8XjlHeA4+1TYu6rqEtFY8Smy875poxTGL+SUF87XvAiy4mV3E2ld0UIWtHy8hMJpzWjh5gNaEG+Y5gnvgllijCBjQg6Mcb91FpAWUmgJivYdnFiRJOe8+O/CClWNlY4MSeUcu43az7HLnc+wo13qNhPssgUACEZVAILCE0Da1QUMvAWg9AAccwC2CQDbCgBzB4BVTNPwCQAHArA1AI4RAI8AbBcA/ByAfQKAWgGw3wFgleQZ+QQAjwCoBoAfAQgIgLoAEOYA6AkAegWAvgNAWAFAPwEgIAC6ARAGAA6CAOgRgCKGLwGwEwD2FQDqBgCp8ykA7AMAkoUMAJ46yayXPQAUAdgvANA5AGYCgFkBsN0BgK4A4J8AQBEA0wCgIwAMATAXANgcgGMCgF0BIO8AwFYAiE8AYAiAbQCwEQCOANgLAGIOgJsA4FYAiDsAiBUA8hMABALgGgBiBEAgAG4AQKl9vjoT71ZnbrU6O+6vzkhYrc72O4vmfbVo3u6tztywOsuYparQ1tP7ZXW2dxbq6owEXJ2JvoPzmpmLKSvMrVnh3i5Y0fdZ4d6ttjJ31sx86fD2DiswzTMrvMYCDLiywsXIyqE6C4UVaFFYYbbvYGBlHivMvGEl8BUr/j4rYbnBvBMrfBUrLNxiJU5zYKXGCgwYWbnEymE7C5WVIJCV0HcwsGLmrBzvWJErVsIXrGwrVswdVsxqf0nusSJHVgyysjVWzIUV11lAVrbKyrmDgRU7Z0W+Y0Wt8gr5ghW9YsXeYcWuWKH3WFEjKxZZ0Y0Ve2Hl6CwgKxpZoX0HAytuzop6x8ryLIZ+wYpZseLusLI6T+DsHivjWQx3yIpprLgLK76zgKwYZIX1HQyszE8umXjHyirb7+wLVpbZ/rjDyuqQg/N7rFyy/YGsdNn+uLASOgvICmZ7zvsOBlb8nBX9jpVjxQr/ghW/YsXfYWV18sLFPVaOkRWPrPjGir+sjHsLyIpHVkTfwcBKmLNC37ESVqyIL/Yrq9NkFe6wsjoO4vIeK2FkJeB+pZ0m83BhhXYWcL+Cp8lc9h0MZ/xkzsrbM366YkV+wQpb7SLJnTP+1RkVv7mLpOMZP0FWWDvjJxdWWGcBWWHIytZ3MLBC56ywd6ys9iv79gUrq/2KpndYWR2ccXWPlXG/Iiiy0vYrgl5Y4Z0FZAX3K1z1HfSs8PIRIRYjKbaQEvCKRGOCX87cuRMfXHVwr646lAtqJ2MSj67w0gY/XgGfR05PjTf8ZtF9h8QbTdz3sOf2EVoYRfoQzvOni4YrXqCDWefPv1BUvv4WKHJt/+2Xl2P5V5hS8hLU/Q+CysgCVPoOVL0A1XwAqi6gMlJB1QOo9QoQzLqAykgDdW+1Z1DNFFT/ElP7JzGlC0zJO0zNAlP7AaamYkorpmbElFbULGJKG6a21Z4xPeaOSl+C6v8kqGwOKgnvQD0WoLoPQD0qqKyCeoygsgqbR1BZA9W32vPND2Gnh/gsvDzEF5SuspG6k42WJwL+g2wkLH7spy3lDNt+bvG4mNLLIf7iCMy/S/TLrYr/ItGvtir6zhGYWh2ByZuJftyqKIOJvm1V1OUIzJvOAiZ63Koo3XfQJ3rnAaI4vMeOpOhCyhHDM13Kgd/ltp4KBVFScGDlapzMGMeHvZbstIS2TnqBfXXBuSNQW/cpEUlk7s8O4ffPQxRJhMFAMdyBiz/BdbeuJrYEkOJPqJGnGpJqSO/uuSYDq9MtuK1etstVLDViJFexVhWnFTUiX9DbFO0rDqg4YND1uD+Vx73BD/jRe05uEKBByLSmb47RwVusqUKrBTfm9Y6kKADtR+FoXFHzuDWqHOH6d0uCnjkyvb16U7LYqyM5yTkTJ4PZin0RXPUuYZpgvR8NBsuFLryECGWpFvxaxCrnt9Yujg5kmOOtwGovDhLojz8TZGQKmVtDRueQyfANZGQOmQzvIGs+QREygpBxdDEyQiZbu9eQ0QEynz4XuYd4BITswOtZcA+Z5ezOmS6x6/JvA+XxxRiWMYXuTyjSfZFORXtfZKEo/WFFLbIiFdG+iKci1hfRVMT7IvYEwI8CnmKJ0jifY7zKvBlV1x4B12SatKQAJKRbwWjbQHfE9kVpguk7NBa5Z5S0LFgApL127LBj3LXotqgU4JNmK3CGiy/5ahnmLc+W6x3qjbfvrM2wnydOENLaQwYPenCXHizBsbdM6kTtQpIRNEeuoIUraEcqOvoi3+H4kxJdlNKnD3QHrD/gJ3ycU7XGPaKN6N425U4pThUOKiAfBEL7cgvlkA188H25gfIkxlKiobieNuGZ30jpIBDSjws0H7wumTOtVQ5XX74eQiWvlUcZWwwW6Kt+aswVMDiTZklFXw6DMyoPTncVOg0ORrmdJMPXD6MxUKF7RvtRp8TDUjekmyo4G1QokASTrj7b6Mv+KgnWdpLwWgrMVQrsVQqyOpiLhtjsnIMkiKskvI5/k/KvfB3/SnSu7Bfxb6+u7K6uvF9d2fSSYNL6YSIJSrjvJSFTJF5LAuv+Fip8KAlVCUxa14jXShC3CgifN1clGDEriuCmsY4rOZMu4Xehrk1J/jCgLqK13vtyjOit/q1kLseINnWdBlykgE4vpMg0Sva9dwFtFGmtckDDO7mZ1qZW0qJC0eVj+R76cgx0rUVfjnG+SdeXY5ybuoJM5ToNmV/CPI2nhbnZQjfiPppDujG/xcWNvkZz9I8Wzee8zJ6fBOGLvByzdwzHdDABl9jE5c4HxCNm4aOLwhY5Yd8WkSPt95ETdjlPdUo2fQh8nurAiz/w9RepLvTuH1RJQzCoLp8FtfflLZ0p15ej8wet+nJ0/rCLWr5l508v5GxW/5AC6soiMpKWtzB4i0/kL8jFwJbaqa5d72hWxC3t44isUXL1NEk7T6t/N3bKH5ekYSbrx1nSGNaPn+SPwXXp65Ti+CKlyCbjRF9TyiWP2JfryHUecXIVDf77aLCSzJeWQnZ3o90pkQCB/wfURbzg###4080:XlxV32DM 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fd8eNq1W0my5CgSvUwfACTGH9b7PkWagQCz2nQuellWd29wJkdCRPyIn4sczBnkCr3nA+58Pf7aBfsiX/FfFdK/v6mQHgRUOJX+8481R5rC4x/y978ol+qLCkse/6VckS/J3SMJ9ReVnsf/SkK+dk7ijsTEJXFMbWlBeCSRRaKDgOjAszyIHBa5x+N30e6f/9k9KbX9/W/LyVdS8fEL/o4jTOeRpG7c4vFrtzvIKZYfSb6BfMdym+QU5ALLTZKTKDdHm8+/dhMeeYIKsMZiraSPWsmNpRGy9VXxZyIPmFOW7b4O7kVlY2C7DcuTykaDnGN5UtnkV1dYnlQ2ElTG+yhQOeku4hiVO+k6RxTERfJIm3GK5Dy+SvorPcSgNxE6DWzxKf9YSra0lfjav9TfBQAqoyJCxYv4RTeZQWYJ/rJb+tiWYhED0VZm73iIRhxQSdMv/bCUwzvTAZTxpQsUFXEVisx2+CRV095sXHY0LOu2ASVtgyOqYkRWyRSWxC9ZWKJ925quaKIaTcK2oIlf0WTNDUpIgSHogjgQR8Iw0lhACd2GkcaDOMKHkcaE8qZ5ZMtcyHMA1QUOdRhA/yt9uDQmZN00fUDAZNlE5GdKvBSjLLj05iaC7LiAbOMcgcxI9BNFQiWRwiILIo1FCkT4S0TGvQLYvQEWA7VgFwE2uHBBR8RrRocIHR0eI/eMDntBhz2uRlRfjahBQCk/5Q0JRBDvkyA4f88BERo/pdHf4kDxHscJ++UtEQf8VoCeNEEMCNV6Z3nDv98Uljf0h4Njecc+523AZejDDEB+/l3L2ID7YNtIwJY+HATLm6UP4HKbvFl6v0ksb5Y+qiXQgAK1XGFVOCRSa+CUTG+vIhTs1XBLhTglD2TAKwkuyGePi9VO/KihxO/kFIENXpGl9T6m1jtIuTDewnyAW/ghTjv7sjMVW9l5l810M/9S7BSkWDgF0fyNdPuVEJUFZ+gXj+BOBMGeQBVPEOCJKEwKhNYRMRCEMixvBAlEYnkjiA87ljeC5BcGuSz8SBMyP6TCWqEwKVS3kFblMCnNKQ5F1D0TbDK4YfMxjoEFPY4JDm85oH5P2x3xc4erJzEbQj0YB4R+Uz2MunoY/cR37FffQa++Y+u+Y0KbwO0Vpt2J8E4gcnUiF5tqrzZ1dBNcrdzE/gHdIPbmc7oJRhvdyIt0U+TMO25Wjoh1dyu+lbMUr3OTs8wpGF/2hoJRySFKEwcemHAQ5N1JNc6CHDupSs74CTMJ04xMwl1gvTAJueqrCgnZXpc1jxQxOHgqieXIUwUsx54KbwRkBiVPZE4P7mT2G8FKK5LIDL+lP5DOY1YCsaSJAHaTrAQHjNxPaD7S+8PEZeYCNwgJzlz+T1zlmn/YOqP9OizstHWHWHnJ7ZMUh7p73lISbnhbf9/n7tJB2HXrLmnPofyfyaGcbYkSdSNte3qVtJxmV3lgklzlgUlulQcac11lWfqIQFyYUPIqqgbdEHU9D31dpi5Myiv9VkiSMIe4WCBY5AqeJi5UzBt1LuL8Lo30I4KevoEamI1e8fsjArmdjwheSbO2WZoV00r7xrmAV8vIMrzPGa+WAaDviF4EgKs06Mb77KaGTGLE6u7wAMIqI3gAYbUerOWBhtX8ZiAvkR5MyIhTvI+dTwBYOwEoDiBvIAavCQsxghS8WzQus1wlfuG7/N9e83/1UsDGHt9D4fygSmlyH7JJYXtGvMr7j2sgop9Eb0qvTrqEex/SSq8OusTRX+m4N9LFIr+O7rm9VqKAMymFcM4Nx/IGcyEIljeUK+mwvIE8vyvIy0kXTACQZ0SWsQHk3LSnEBwsCX5geQuWlDRY3gx0Bk+VK3h6PStTmqGnj7aW3dvaQH7S1h5v2VqzAKakn9havQAmBCX3J7Bv21pk6/RoatkwgExtPffPA9jU7ngAmVpV5aaaWt1MLetj94etRzW1pplaJtHC0dSy+8gZrNP5WGiRGE9PjFZJrgK/st9YTE46vsxrSS6yiUqtTv8/CI3zT3ZzgLRtVekdQonvHCApiExuqwp0mcieD5Am6HW1PJbeYIh3vd7qiMS4FjXWzPIGa6UMljdUMz7Iu2lVsspLkgoTimnVWCsU6arKtrQqR7ppTl7W7WuLYcC+GhGwvNvXGsKoErkUXcYAGPbv8a+qhAMNBt7ocM8bQe548zRU+fnkUxm64BhzS449iUoQ3cy+oBsLn4QgYUE3erxPN7Mt6MZ6uO6PP5SANj7GVxz42HkXdUR87DwFeeOjbuAGeQ916ilTlnc+mrbPXviYJmQ+9nAqnPjYQp24qvBRhwsfDZ3z0dCBj4YiOfARdDnxMe2P+KgD0mDgI9DLRpz4Kx93+ZSPvXS4qBcuDnqn9ZEZGfV9aVAyNomnl6XBRT1wIKddkfODImD+2W/J6T8g5zVyROTkk1xqeag7q6vMmGjkyERlarJgzMg4heWIcQHLEeOqZ4zfojDONMZ5/PSBcaqvKowz1XH2zMNoXGjM36TJW0aCjIQeMpJuJPTIUI3kmaH2ytCkT2eoPg6kMWao9uKWoe54OdC0Nwn9WNA3P57jFwIbyINuCMwdyjv4CxHrMU3sz05jiGsN8/dc5u6DuNZAiWG/4bJm3+Ny0tTd+1fuejh7hD9+dqBrG0tSCjlUTR2Wd3pLi+Wd3q1di7mhY4y1fXzpGGP1SDYDP43RU4BrmO2rMr3TnLJMhjp4YHprarG80Vu1jjGQN3prOuzTO8bYgeTQMQa6j/QGfRC9a1kXNB5OIo58ZscmPTs0sJdLMPrxUuvB1bU6YWZFluIxAjqrCAvXOpyrObCMt8cXH1RFvWOr6or+vLoi7MJ/yq03I5DvNSPMyp7pbcZ88ijeLqmBW3Cqd8jy3mFwBCzvNZJ65Je+RK6RCFsPQxzBT0e0coL3VZlWaU5Zdqg6aDAdnMByKJDAM0c6wD6oVlkbD0DeqyO+mhvQYGhICPaWJptzr8Wp30gSJ51qz/p1Nvu8WEneKVbaVRSKtnyjWEn4oqdnY2/39DhrVkcy4QeKlJMmt7tOH9KKgoSf+gxCBZwd+gxCYFje2wyCwPLeZhA0lnci2iYv4StMyO0C4RjUGmqVri+rtUrCW62yVps2O9YqLZIDFa2d1CrTRqgJKFj0LMw5CWbzxjWRb+aGd0HllHBXdkkoStyeeHaXQrbXEsDOLymW/c78fX7lH/AuyyPu7SxPCrrwUpxNmpyWIeKMU5MsL73PQJ/8gmlEjCWkem6e5Y0m7bAjyxtN8vuAvJSQYAKgXYodPx2xRNbTnrQqsyTNKcs4qYNDHUnW3posb+SRAs9XoMJ2IQ/s37kj2IE0GFtr9H2FaXP6tuF/f8krPSupeqjVfbd5NCq96ovh8hNXo1dtK1x0j+D++A2ZoJtD0EObStDHMNDtvpHDQDf8OgwD6AaAbncDtKg3AHTvVKm1SRg+F6WqIZeuXgDQtesk1OOFvPAEuvtbJlJ+55LJJMVnTzHn38PcsgjPPsLcsgq/vxuFTDLpWb/xiDmEIDpiTg0DHXMIjPQOc6dbJ7rdOtHt1onut040QcNnzNUGKOkb5rYJ5s53TiBpuAkShPuJTmE7v3gy6f0Vi0MmKfXyAskrvb/Hs1sjwq0S30+674VctQPrz9uBvdou9LVkQt9IkWkPrzgdAceH1RsdwtWSfK2WhJpr5mW4xVbYvqq02Ip6dtsviYhjvCQisXxySUQMhzv9UokYDndCay8W5XAn637qvBVy3nkL7zLrvBWnWyU5cJgf6nr3jcj6acPWswLMs077K8sE86taTL/A5NT3rmnp1akuYpngZFWW+eCCYv4st2UZ/nbALlhYlWXQ1TbzE732k9g9vdopdt/qSMBuR9bbW1mOYneK5c3p5FdL8nQZNrEcJpTi5o6fjlgu6sFvWpVZLsp5alrG6jKPWd5i+ixvLJfj/MbyFp5neWN5RnCVJ5Zn3UeWgz6op1fWtgpQeUiU4TnzsMv+aDOZeaOZTK4qH1J8UMWUq0qFFPzPNJOJ6iDkWJMQ9SRSjjUJIQSWd0CLDct7MlqhmX64/wO4WlZM###3572:XlxV32DM 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f34eNq1W1mS4yoW3UwvgEkMdrytZAQIiOifro/6rKi9N4OAiwSkbOf7qXQdZHGFzrkTGKEHZe75X8rZAz3CX+nj31+YC5cAzK2MH/4azuOHeBn68x+8CfnAXPvn//Am0YMg94ygemAh40eB4p39zTvr8IF2dzbouPNGVb2z8+XOGwp3RPFrYUyS+AX/jJCBkH0+fx3z/v1tGY6z/PmHc/OIkz//iY+UPn2lf//+5jzaRuI1+hFu9vyiBgc8PBSHAzoOoPQFVXD5CFM98wXhQxyTbSw+dphGEJ1GfBkxbYTFEYHKiA3z2DCPTt/YJMT3iKts2AYHosU6P4mBeDRYi4TvAM8Gm8PgYINtSxReXF6h+OGLiv35N7yqZJ94kIf8c7wKaZ/5pRkVXoDY89s2CL4IGt+NwRDCCSIQIgmiHTt+xSWLH46pZ/zDuLJEoVf5J6IZ24x/e72zdi/zL0A7hFyCbDLlRM34UsIznghJygg5+BAWM+BMQTzyISwf5EnCK4EbrxLe+CvAzJkO8YLMX0GhVYC/B1HK1wA/MJHRsECah7oQhCABGKLF8VcCxhSadATApmdCmERcHEZg9/HCfHthXlYqmPLCyltq6x9vuPBtlO/v+7Zwa7NwbsnAw1Z0JdfV1t8YSZ3XPlndsSUgvI6ZzoERpbqRyoDwf3i/xIF8TfYJ+YW26SANSHE+6Y0A7xP+b7uR6n8wVd13wiRf8Q2nIbFBSyCtkIzs0OEV7VdaMRnWacsr39OryE6bJ2CaVnBIPpfkI6wnn3X7lSqVe6i5IYuu3KtuYK/O4uIh1BMyE0l28U3BDeXpMGbHdFS02RxYjRsERZJeZ/B1hq3OsHXUvz+DdQsFMEubAswtBVincpRKi5MjeXqKXgtIHLE8zg+lgMQOB6oSHCviiTdLQkhXZB0g4cForwMkcR1jfUAP3zNltr2L3EhYONC0k7leB6p03AbxpNM4XYndFIFVScE7P0eVUbyzgNdsrlwTPn3Ff4LUvI+rawLD7VVpdurAT0rrFKYSBPkfcpo7OQIb5wgrdRp5JXNRJ9eNa7udR4aTSjt16hq/K2R6wSJ29Q9VsGSbCPaOUBGdBylM+ESoNwRqxOXGLUQhNnBpt/KfHQ3zHxjLkCyERE3K6CRl74+4EA0FyY73FOJV4d4LiAOBl6AUp8gCN+IQkPcSDHb69l7XoZO8vedlKgnzde8ZxKvqvccQr6LPqqs40LwAeNY8GmkeVc0j2oVO7/00YyeWTVN2dpUjXaXsXWJ/zd6DXWLFXlLZK15mr1tk79wMJH9l70FVcyX0JHsf15gHoTNVRM9iR+ordjCV995CHLDbQByw20O8sZvDqQ92uxq+EOoM67J5CscgeZSNNuzhtbkLeTAW03RLPS9xQda4UILBHcq1KvHCs28igabbIhJYXWlhtkWepq+0UJUW10rOaITm3p9TUVjO3YveX6W3PpEPp7LKh74oH51KuYl8+N6aL7t4TT72sk7jIKCwz04srl0OAfFhO+1IdWgkWgu0I0vhnPGqHakZxKt2lJAQr9rR5EgJ48xJOumCJB1lSRvrhJPVQYrlICxIVeYJLARhQTIE8RoWpPIQb7ngtjk4UONCZnfBk8EIXcJCwmJUSI8FdZ18zj5M8qx/T9Z9BtgVVKsIwp7fKbuV/xeJ23kpxu3W+ob6XYnDVBCoPBkwVTl+O8fTGK1Uvr2d4umNr1TeuhD7Pq/BFpHxcAALlYsj04trl1UeH/ak8kOF0dpO5QTiVeWqlFYZrypv6k94U/lWRIOPZle6IKvcmTbWq9xX36OnKrcTNXc9WaB+24vZHWtDbfE+um+NNEnHkSjp9AydpKMI3TBUG36jMdLXZt9WcPKTCm6dMg4Er07KT6XwLLg7fi+471flm1sVn+qdAV45A/p2yNdYrZwBez/kM7pyBs1vGvsT9d4yY27RPyxj8Qtq5heC4Z1fQBAHfkFCfOAXEt78QlqyaEOYOeuP0aI/opIPoMU7qLN3UMU74Jl3CGQFOQDwWmjsNRIOvAaBOPAa+rB6K94smDDzGrh4DdV7DRdvYicJPv+226Mn4b/3FerqK8it8hJPdoTmfoGt/IJtzCY32j9mmAac6aw7Z4Dlwhm07s/rzoCIlTMg7zsDviifuW3NH4cXzsDdKp/taPOreQAsiwcgp9pZlY2GaC3wAKr0eDPePEBpyGa85f/YQhx4AFuEcpTO6YLOAxTVklP5nCVEiv3AAyhclc46DyApxKsHUMJDvHoA4DFY5wE2eJ9kNZbXIgDLQ/ukL+6dQqnTS4d7KvsrKYN8t+nLbm8ML/YDrVtlA6bFs92/lg2o1/u/eVFnba7tgyat9Ysmra4PKRF6t06fNWnlIbL4bH1jlhwhLhoHW1cYQ7y1rtAG8da6UrjNkDtX1h9EzgtaZ++3XerWShdhPWYQb81XJCDemq8IQ7zqy1oH8GtgLQYDTUkTTeIP8hCDeIrP3dZFvjyqihvl8zx0chhCukozdodm0e5FF2gDXSB9oz4EeeC6KJTbsfBxeuDWN7NBvPJKMwnxyitRuiQZr7ySZi943sfLFyRe5RU8xib90PS1Llua741hLD8ssuTKPU5pgb9pg25k0SPZ23a15h9XSn1ZhMUqE+Lv90gQXmVC6P0eCfGLTEiLVzuhUw10BVBO71OcFiX9QfhUAGlekg/fpz8W4q39qQzER+1P37c/SxqFcCklfG1/0jZ2SnxK6YPFufSpiQzpExwD8VbitFKJ9AkOBnhOcMQgwRFHgoPwqSUipl1OM9+80HfOiryRwZyES583axqKFwp27J6Czc0DJ5psC9li+34Bg/RCtkS/X8BQsupmjHpBnyRGZzH7STdjq2LWs70MSsZ7GZSM9zIoGYuZdkf6NFWl+68P0VDS1zK29FOQPnczRHEQ20zSgY6wa9F6mngs6YQ3SXOIZ1ezXSUdsSxpfdqQ5EfNYq4RWKt/s2b55mjiSbUqRalZTbKTduiJ/Os1iR4dSWnSc29HTIX3xdlGwwfnMJcnuyQt0iinQZpoDtrEKWFLr9Ay41UEudCn+U6JZumCTgQczgVFUMr2+A7h5p3QEG8SkAziTQJaQLwdgdxK2aQQntQV+jjP0TJPP92It+rtY4/fc/373Tr6TQLK6aol147Wuv3t85Jr9mO7SkQ/6c+vElHywZY8E4uI5uhgyQayurFDN4ldYcFKJ/6UiCpcEkUmxn04Jvo+HIN4i10SQbzFrnIEM858dOJF3aGjbeyUiJbYlCwfduA47XvwHuItQa2dOU7HHThO+wTVAjwnqHaQoNrSfT8nqHhaT3qzOCs/PEfzomiHWl0FLd1STcMW5+oXp2MyxcZSJKqWbtzfkWIMbKsuiNKvdkE03Ve9cD54/h8QntT1LMfei8pAfFDd0T4W1o0iuvcJYT2mYkpCuNfqzraxUypY0lHsT6JqIunjY00ROR63tfkkReSnFBEBPIvKD0TlS4p4atJ4NA2Vfv+Jsy0vdLXfb9v4VdQUP3B6bbWndQqgbhVAyQclIV8F0P2DkpCtOjl8edrl7U4OCKCuFn981smhrNN61RRl440syvq810AcaL12a3jROqtal23spPWiuGT5eBPbjwPo5ieb2L7fxN4gDgKoA3jWuhto3RWt81NazNLPguhDX8tB9Ho5+GZTfl4FErT4oRrYmRr9UO2bKhAKlKzCIH85DKYfF07lM6pdf2IzoFInTA/7IpWCCW9hsPwwLeNNGrUpmnCQW5YTaLg0E5nqS0JXslVMeoG00o/0ZzNq6Ue6naPsCgo+rvCiFV3Y0tOw5fyNZuWLv8C5d37rhV/pXnLJfZVLbstcctC2fPFHOaem5upUBt4/iGB2FcHUByXgqqlp236c9Z/8JPn/D3RSgg==###4024:XlxV32DM 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fa0eNrFWkuSJCcMvYwPQPKnK3yVieCTRHhjL2Y5MXc3f0Qm0FU93TNeuGskEgQ8PSEBfju4OR+Pfwhyb+jt8R+RPv79+V0d8Qf58bfGMjRy8vG3Dm3Sr2/p/z+/S4pDGxzahB+hh8c3Ykj8Vlgot1GOk1xCuYnyI41loFxHOQpyTY8iDyMHyx65QfgRvnG+6w4uzmCVwDpqvC6aZHnR0KiRpGi4Lfbq+IVUHsqjvVolew2UR3t1mreSUB7t1SLay2H7ZG8wIdt7CIL6ghJO83rGH9+IsI+fP43yLLTQb+TN/PjrECi0lu7x18HCsh1EhU1K6xr+ahH+BoXEYYJhClEkoUhGkUFAZGgSHVBEkghDEU4iAkVHEMUNT/g4RNqr+APHZX4YlRATv0A/iq08rMa/4XP0xoRIE1Bvhzj9o8yKmgg4DQcxCYMGitSjw9FoHEeg4yi+jMIPX0YhgrRBfOiR07xguZv/IhqSoM4ndMx5+MGGjgP4Sseumx8WsPTM0NV8i+7m+ySyUNQdrYnc4+ZzCbnk4mkdoXzwtI5oDj1NKgPlzdMOxhFUdFdLy1CGztCNDbKrJVw2s4CrNUeIIAAOwpmF8uYgSp5AHjr/FvHUvaOOPzhFHMIEgNmJU/ClU5jmFPGvKn/1O06C705Cm5PMPGPiENKKG6K6Q6izIcq7jUPYhqgKoxt2Lg7C725YHQTL7iD0GQeJfqHXfsG47G6N1n5REG/urjKd0OAMkjak6jG4SCgHwcVAOQguDsoB4lVFHK+I1w3xsuvG4FJDVdzlIYRQKO8hJIGhyXsIqaNnefMQObRfeAgfPORAeBM3uA7LzDLrvRs/qqtMXKT6xTYWBFPOO0037J+qY58+FQxuFDpgPgxn7q5WQX8g10DPBtDX5Xg/Ori0HWTuBdTRPh9z94I2iQ5qZwqPJ9MHig+SQsGuQSVzNsIUKhqCTypBZwnCrqAmfSWGoQCIg6R/eUK4Fix1TQNs+DcZNA2y4d8eaqagzSY21MaPHNSwYF38X8ZztE684Tc5wbOZ4PmC0ErXAKkdoHaHGPsJiJE3D+i8iXBDjEMbxFSGnCPH3pBDKkAkpMS+m1kBISWhokOKYTBKgZTskFKDDRBScKftcqftZadJ7DD0/6bbTp9lp/kZVgHLpzY6x+X5hqchRg+2quyHMPYeF5naxUWXsgsx9qdbf6btr2oIYnq5v9e86x+iCsmKowLKm/sE/G1AInQbz/QJBMlZyVpnJB3hDFI2P8wlDhQ2OQwSWwQ1MbZqowydDWfEiP4diMjEcChv8COGQXlDHzEUyhv4nG/wCpuWwed1Ax+B2hn4SP0yJlfR+gGFioBB1REUWGYQmtgxD3QjbnSD095NUXjJoo4lAFP3C8bhVCwYZ800El0oJwxh1lGK035W83JzVvOPScA6kDR12Y268o7uOjPyiz4HTdvj8G8N+kubnNuUXTZqGG5BMUaNm6v98JVEbXt52iwbGPm87a6SyzORWuTUQybxTI59rNMHPCbWKcoD5Ajk13lETHDqrupzc5bS08R6xT9hvRy+n+DOGiB9P/HIduKh51ORkVu3TuEx6vOR54s5PHdsk6sIO1mp53J4t85VTpiruFSoCvwTVy8Xy+JsB2/htZgVrYX5zEmhvLGnoB7Km29xPbRvnsVdldtSLEsNkltxzbpucCpumlV4LJYdjJS4HYEIUh3lB3k7OwpqobwXAwyC8nZuzPiu8mwwbtWydGgoK5oIPU0LpD0+EYkazg7VsfkHHXusHqxo/tnK2IGQWmdDscdWW0If9WBYL+hOnNdm4Wrh3y/HnOppZ1rURaRhTE6KfdtIM0/9Q9ApEIsTGQthtuA1WgK84hSDvHmFN6b3lECWGiSQ+RqK8ihDgtSjXthDAHJp0aDoCb05BwVIj5CEmml6lKyDVa+Ud86j1mGPz0D3WAvTTwP+UjCmj1fjmrJmUx9zPQ5Y+hlecSVuAx1FWbWOdli37ID7F4OdFGgT7A79Wjlu6BhvYp3TT8W6hQdeVq9ExCfCXlzGHPbivEeHreW6aDgIe7JGhSxvYc+fAsqbg0tBoLw5uKyOH0dODp4aJAeXgnbdWMaztXBt1Rj2ZD1KRpjCAp9AUH4v8GV55wPBoLyXwK0G8mhvNOF6R5RkMeqlWcGop+IOuYAsf09WrH231veZBPFysXzHCk5vTruMd1w79eWs4DW529LOwJQ050UDKzxfJPIab6pQlP56FSrlX6tbLdPrsJp9TfW+RNAA5biYmRvirAdu8JUbormAG3z12yzv3KAUlDdu8JUDsrwXFGp+GkfO9QR91uCvgG7gBl/LI9lywA2nbfYOJ+LslE3euMGroX3jhpNgKG/c4DTsJ9obTbhyQ5JFbkiz6lmwT4f82oCdpQGot/lULo/lNnUnj4SwgTRuTGGevlXenIo91bv7Yr+9L75593jsJXJ37HUfPvZ6uj32sqeOvYtL4lmtJU7kUmrhBeLRFHjurZcGWd7PvRR0laFE27kXD8MA6J+1Xhw3aSj+80HRD7eMOaCYn22JHENYui4Ifjg723IxqbetbnYvN1j3m6sxhKnHtnb3/sF2me+payzDm1ime5Zk/VM3wJeLMXsPb+4SBKFPbMuP/NfLjz49KVjFGtsjt8HPVR+fOIZeY01lbHIpUfqzMGo0EkSYkxxQ3iNMZfgs7xHGMigHbqYK59aKdWqQ/QCnGFAvx/ytat3cPeIFhhNLobyHk3rUzPIeTuoQWQ7CyQHkC98cC6ndncmljurTJ4vYEfbjQ4+TnrpU9on6lgHj/JwHRp64XeywvxA75C528G3s2Fbko8nXKNGigVxECTnCV/SuSpSot32+Y8StokTYmTFKKKiAUcICxQKJl/IeoRu82VcSHH3D29NnFY530HPPQU9PiRxAL6XRS+jpj0OP+R30yFPQe/esEqy/orDW1Zifo5D5AYXs7F1lFDLfUEjhMHMU4gsKJVRAFBqgmKMwWjCgUKQiM508rcFpq18+q8iPHKKv2bJnYg1MTtFzwLTvcSKl6zyYE7/Ig185O1C8O53gTzidpIi2vBsln3p0jweBsGYl3aX45hgVgMGouWO40TEqbZZnz7lBcQzWdWP+SiqpJ1PglQ7iNbwzMZ4gGJQ3l/GMA3mOD/SekEZZSkjpkJCeGME1CYeJYiw4VhyEqZQNsLcD396AYBYPFrgko1NXW73yfO2xyMW9Dny6+yuPoz66UP1VsGrvjUMW+AuvPA7Cyf2Zh2wjysm9K5O7hyqhR7x5+aL05L51//QlrIrZvH1R6tPfvoQR7+8J2+MXn//rB0B9vPcERt3ewuh6nxMnlx/DpFHLa5iD1ZfXCRNjg3goJ/VCqgiH9zIa9A0fzFg0KMCLGTkowJOZc1D09xT4rIOQEtVKm+ykpD3oiuox/8iul3WXSld70pNmDXITYtygaMlJe9RTFI1b2nuioujxGJ+DJpkeLRmugGkxLxFMnmP6FVcbcA0XFC5Qe9/znUsNB8kKUajHrKlH8T/DPAQdO+YhX8E8Zsc89CPMo3fMwz/APN7vmId9PvMQhH8b84TJFWKJo96ZJ2JibDAyTxbOmcf7BfN4v2Ae7xfM4/3IPP5s9KEr83jfmUcD9ZV5TNOZFfPEWU+ZJysmzJMVE+bJis48BCGoKcxjZsxjGvPo+gsNpxw+7CNkHj3MZGQet2Ee9qeYh2+YR/qvYB63Yx70EeaxO+bBrzMPQXTHPMdXMI/4XcwTJ9eIRUyZh18aXJlHrJgn9j1lnqyYME9WTJgnKzrzEEQafdjqvoh25rFAfWWexiLcrZmHr5iHr5iHr5iHX5iHQU1hHjdjHteYxzbmESPzDCsHmUfDQUbm8Zt0y5E/RT1mRz3mK6jHb6hH2o9Qz7mhHnl+hHrUhnqk+wrqsb+PelRnFjulHnNpcKUeu6YetaIetaIetaIedaGe9gk/G/WoTj0nUF+pp00tgG9JPWZFPWZFPWZFPeZCPRpqoun/A/TUark=###3592:XlxV32DM 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df0eNrFm9uS4ygShl9mHoCjADv6VSYCEIrYm52Luezod18OIkmQoLtc66q5GLtJChD+8/OfSKZ8Ox5cH89f/1LF9gd5iJ8/aG7cxDO9C/Ud8fnd31z52HuzPnZmqTMxD25oDDCdAwECrgbU89cvFwejMRQe8kHZz7+oIiROHZ5/Uan0g+36+Z/YM/ZIr7q8Kl9e7dluz3ZrzldbXh05X+n5ys5Xnl/ptuc//CdepKhv8p/GVdH0t2l88rMshW6ePv9LpY7NWuX1mQdVhj/PRUsZhybn1PEqy+u5VLLnCeKmln+bsiSqaF5C2geVmng/o4YZNcyoHcyYNmcTZcQy8j90UwFGJNcRDYxo24gBRjTrEUm47oqFEU3bFQkj2s/tCk1Nop/xOGc8yn8BprUUpnXtQmJLOD9eauqbvKKob2kJKDM80sxJ1nHW1Cd3MEftEDXRdzCxA/cU4qmRhOffSVkp5CwaO15tVL3j+W9IF/ApwPJf6C7gUoDmQOgCNgVIWl/ZxBxRJGft2afkL98ICqfPMi4vyrzEYOlRfBATeb4NXXVZurU5sHeBtHSb98GJLpCWbssu+C6Qlm5VWTre2nPpcSVX9KTGApx0jeUdpR16XLelCD0562GSDj1cLdDjju9BD/PHAj32eAN6hFqgJ8rs4+gR2wI9UeofRg/z+wI9jv7/0cN28lXoSRd3kiXNekVP0kTfoUdPabxFTxobo8eZLoDQc3QBhB7VBRp6mIfMjp93yd/c50QP31B4QA9XEFMz9KSr7tAjuwBCj+8CCD2iCzT0MB9wpKAnruSKntRYgJOuMb9Lu43Roz3eIIQe3U3So8fM0bP5byLPLlbkce8gj1mQx/pXyKMX5LHhBfLsbEEeu7+DPPLLyBMvDsAi78gTNdF3GMkjp+SJY9+TJwfuyJMDd+TJAUSeHZxL/LxP8qQ+lTwahUfyGIiZKXniVd+TJwfuyJMDd+TJAUSenePISR5zRx4D5NFAHtmRx+DPEZPHMDxJRx6xqLe0+SbyBL0gj3kHeeSq3DKvkEeuyi3zCnnCtiCPeQd5gvky8sSLq2AJ5o48URN9h4E8ufGePHHse/LkwB15cuCOPDmAyBMqCtLnfZInbEAeQVB4II8AaMlpuZWu+p48OXBHnhy4I08OIPIEhSOFPPKu3JJQbslabqXd7k56GN4gfNLTTd97Hr466WHfVW7JBXrcO056BF+VW6+c9Ai2KrfsK+UWX5VbbzjpYX77unKLA1n8dltuyaHDgJ7cOCm3+Kzc4rNyi8/KLT6UW3CSIRiUW7yZHhweTQ+HGJ+XW3JWbslZuSVn5ZYcyq0ucpoefmd6OJgeVtHjt77cYniDcLnVTdKjx83RY+x3lVtmVW69hTxuVW69RB67KrdeIc+uVuXWO8iz268rt1SrpuxtuWWGDmO5ZefllpqVW2pWbqlZuaWGcqud5Fgot1Qjj0XhkTwOYm5ebplZuWVm5ZaZlVtmKLc0jpzkcXfkcUAeC+WW7cstgTcIl1vdlfTkkSvTQ77L9NiV6eHvQI9cmR7xCnrEyvRsr5gevTI98h2mx32d6WnlVJz1zvTYocNoetzc9OiZ6dEz06NnpkcPpqcdFAswPbqhR6DwiB4o1aL4pqbHzkyPnZkeOzM9djA9BkdO9Mg79EhAjwDT43rTs+ENwqZH40l69Oxz9Cj3XaYnrEzPW8izr0zPS+TxK9PzCnl2vzI97yDPfnyd6fHN0xy3picMHUbTc8xNj5+ZHj8zPX5mevxgeppz8WB6fCOPR+GRPHCTPIpvanrCzPSEmekJM9MTBtOz48hJnv2OPDuQx4PpOXrTo/EGYdNj8SQ9eY7FGfN3lVuBr86Y33Jf/ViR56X76mFFnlfuqwe6Is877qsH8XVnzLQdIYvbM2Y+dBjPmMX8jJnOzpjp7IyZzs6Y6XDGDIfIIsAZM23kCSg8kgceqYnim54x89kZM5+dMfPZGTMfzpgZjpzkuXuaUMDThCLAGbPoyePxBmHyBDwJIo9j0aM+XFTXDtzZT+7QmNcDaGJAp6My656VOdCknxU/0GSelUTQZJ9zKC1gZPPOyi4H4gaWHNhcu9/lII+Fq1lXJ3f+WRMQmvIScy5CU15iTktoipdbMzTuGb/ebbbhXIsQbS3aw1rCnClw2Wnka6bbA0ZGh0MHjHz80cjWXY9sYu6UkSVpR2e+4YNMqQV78a/LN475zx9pU3LK/0gXkd9VBDh2nqWmRaBEd2zD7ZDnjhncDmluj9NfpBlypuQOOVEcsy3WZbhjvkaGmsYxUufxOL0dE7gdstsxjdshuVMOoXbIbXsE1J7Wm5ZQE5uTtnE5m/NVQTKn1Iw8esQLfLhralK78AA5vUC77FkzDZrEsyYdNNFnNQXQxJ9dSlLXp6Tj10dRICWlaGXCoa8pCZLCaaVW4t8/I/5wgUcT/9ZuXXt3FT9sR7jAw5MrPPYrPI7nJWGyHNWYJiCj7tlXx3bcDuljD4nbW/pwgtshfRwRbeYzfepTr45TvKoufY4a6Q4QfX1AvbSD6B23qD0O/ndSTlN8nR8JnRKTrjCW7w9/UTrzB3K9Mty43/67pTPC/ffVb/PiN4qnJA8uJpL3reo8xOJbyD1HoOIvqJYQcbqUXdt9RlBW7TBXskuIuknzxNBkyJA9XI03ZIjYm00+PpYhvfYp0bVCTJfWqT+K4OR0WguScwwEHAA9ByHQYFnQuUfhKwHLWqbCno+A300fKCL8qcQWAbnHiO0izcERa3DkVvJlic2pxX8rHJFxdel/OSK7hWtyurgsiPIjC/bQ10TZ3U2CdE6r0/nAf9ZLvyleXH0XSJAeL0sQlHeQlTFpJd9O5sYEy21MqYAVuIf2+YqLAM9POC0JcbaJogSQMquOSgApM6BZijIPAsq0tFsDViYWjJgKRiDB/HIqb3J0GHcWnuspLc3Kwo8nCL+j5tRNLIFq8u3ViauXR/O79ljw1K5c/aXCThu2zY0GIx40LT7oM9SmFz6DtqNaf3yYonOfgeVdH5hKl9ipe5O6Rro7D0U80A6i3+SB20HzmzC4HSSvNtVmzorPHbLi1SbxqpDeTT2kT0JADlxvHrcDnzfZtQOddT1yK+3A5qKv2n5L5rxe7LrTTZ2HjvKwN9kk/6Ag/lMDvqh2PXdzay2Cvfk6Xla7SPxe2Xnxynf1evHqt2OeVnzfXvfvnpOFOznkq+4k+feWPMXRxoosbVEpZdMl9R49nAmWloQ998FwO6SFp7X/+QPR0qF47nrOVWbBntuf30RlJbhkPWD+LgE8YbgdEsBTj9rz/MpeStDclkpQvx19MsRPYJoMjP2ZER8Oe1ayv/kpQpP9vv+Z7N2t7LVayd58QvZarmSvPyH7m9+EIVN+LGV/3QMkcK2qwLXsBd6EJLrnez1RuL0JnNV2fT6m5kV9ttftssV6gddnTMpKkMA92eo8uhe4xu1N4PWsyNefNaQhLwLX52+S8io7gS9o78gfCLz3Th/Rul1p3X1U69j6YNmblezdZ2SvV7K3n5G9Wcnef0L2BmSvR9mDvEwve4vbkexrexyJ/w9hdGPq###3912:XlxV32DM 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f30eNrFWlmO5CgQvcwcwBibJa2+SkmAQeqf6Y/5bNXdhzUISEMupeoeaTqzIkjA+L0Xiy3c8cNs8kaFOz7/06e8Lbf19w8jxI0wbo8PwlcVPap4ZPVs3mOW8ptN3eiijw+qRLRrbFfBzoN9xXYR1hdlfcLp4p00LUPZdsSdhC8flJvj81Pr09zITdy2m/r9D+GLHy3O4x+yc79jLY+ffpyfwn8qnj9F+tRL/iTxk7AzOn6F6yhfwkUe2mxhCur/X37nmZnf+79kF8ttO2Vczh8Dd/rIe9i0n3lRaYV45ccvf03h81MbEQxbO5/N89HzhPmEgfmsn4dtab40z69w7M3Ww8zqfmYHM5s6s4OZ3XMzb/ruDPQCZ6AuzmBfxmfwn1G23Fl9C8uEW6vSt4/4bwMZnaGkSbSf2B6g5LcSoGQKKAuUwoAMZV19HZThV7qHcvF4ADRQttiOoHwie4KyvoCyLlBWHZTtGMor6aHsHWIN91cfPaqLS69HATiYtuMB1u0M63yKdVjEHJewP2ewd1+BvZnB3n4F9ucM9mIKezgOC8dRTGY5rslwAhlMTwYA3dmQgSzYjshQxosCxjAgk+Gsvo4M8KuzJ4Mr61hMBm1XbEdkwOMTGc4LMpyFDKYhA1lImNd7b/aeDSwI+5ohv6ebdi30wBIVWSLviYPvlJLHfWSgep0QiOiWQC6Kxn5NoN0gAq3jYAGLxS3GGTtundikEJjCyYUp2DUbCCF5B5TvDRnKMY5JIZaOHadZ73gH7NgXCtd6LpOg0F1gSw2yiCzc8boaSpClcCJsxM8SsL9GRyFFcgBZvINiB7DF7gStEuEaRyS4LmRr9oAI4/eQcR5uvL8vAf/ZobEjbM7DK862YwcwKUMeHEAlW+JatPstfQTYVR7BtoE/fq618ex+x+GfuIptLkYs3rWKTLqwNXFbb/KOdNpdcO2SKuGT3iVViR5+iQt+VHQub6OzgpLeLVBBudYcyJyPQVmohhB5agfnZ3pAljsYNpHAoGkDhuRASC3wSQ6M1B07EFIlWj4jlVaksmZzGKkYLGYIFoPA8qndGTweQDdzr8KcP5GTzAS4qu0sYyHHFFh3AmzcfTJQBJhpBvffqqcymJkWN8KbzmqQhZgRsB8D2p1kAuhzqxdkXspB9HlMYF6FN1xXA3PnluIhDcr3VWEHoNyWXCTZAeR25dgOGE9XnJeOEI8DIsTdueFtIYC7s+iqRwAS3HRfwA5666zDdpBbZyyyX8pt3BfOVrgIa/u7e5G7CzukiTpGBWmTbrTox1y5wL+XFDVO4Xe11gxkmRBAX6Xw50U6XMV7Y4Dx7RmMf2rL9RjaTNeSwKixVuPEocMzRj+GNs0YCus3Mq0ZdgCAhSHYXgHMG3sVaZ6JcOacOw3Iya/Yq7NBsDCgw0vTPBHaNo6KVW2w4xKscQ8IrLskMcjTiyAfArDPrPlFlO8QOZToSXGZVh5UgMSWRgpl7sUCcL8qLQGXdn8Nl83Ebpzhbq4CVJ1j7c3AHGkvSi02ksqicFCpDtxLRVjEN52hv61hawii6QjAXhMJgFtyAEZ3YYs9YzQOiBjd5VJ9DUR3mTOctEVUINaiLrhiUbcLjDz/W1p/G7HqkZYQGQCn/DlfZBm+jPhaliFmZR7cEPpyq2SXclLpkdobUObLiYZ8UPSlExwyi7/PrHjPhsza3meW3GedFXIRpS6yGvegs4IYxQuj/BW1jNKywHLHzNmlwvZKHLkVO83ECQMycWj1dcTRxcNb4uzSFI9sKsjK3OiAhCbdbLBDlNi1wHYIErvE9rRhfteKibbI2nBZOF6oMMJ4EFx0YvwVPE5uOio+34R51MgcJEbkAXHVOiNurRCUeypB6lj6UrcmHe6QuDWjIi8T18yIK75AXDspR0htcCn7ckt0lL6d15xWC3C6q8R3BdSxOMOTpRZI9lqHc8GwA4mAwXYkAiXcSlM4ZUEEXPW1IqDKKmrpoyeQXa1YBWpcVysWAWkMtlcRUAu2VxFQBNnjhtVyLwJqKSLQ92Njzqw9os47FeBi1IZ9UQyeYz497pqyDxjvdy9mTYEaq2Oo/Brlu25sPLd9QHBW2wJLQ/Dn+125aBl11Bj5ckfNryDGWTDTlfL2Ncrn8G2GVM9NCBrqG3+Oiezxghu2Ww49Mb9TXLfVXl10AK2FWRsH8Nr/zcHDElHSmNxg0wy5u1YwhTZx3CyiN6rsqMA0tlw0jquSjwpMZP83x560Q79gz+VkDGROl1IT8VS2wpDdliGo87crN+Q7McsrRNczok+fs3RxnT6I65qMSb5TXSMTe43k5gHJ01kNg3h9DiL0q1FcqVkUr70cYV8N48pMwjitz0yNfO3ZTR+73SB2uxK7VffYH4dCg4P3rk5sr8F7JQI7avDWK7bX4K1KLq5UiYWmBG9lq68N3rrk9nHvOINXJeBr0iTqSmF7jdGQVGjSxGi9IHvalwNex7cL8tGlGK3aFwgcYzFRpxeUXf0xjigrjzefloqvhOtnWvnnLFE/K6/0LGqr483HqrLp7jMxYSIT77f3mZoQkZG32/vXwXXa6WeiC6xbacQzhZnojMB2YKIzO7YDEZ012F4b/UzWlVOjn6nS6GcM7wo3+vVZ2vBNquzMgu31AYDZsL0+ADAc22uERc8x1tETANa+hyYFHRfJZHuYH+vn8+OWg+rlNxb6sMkVG7OMwYMrzzL7Wh/rOjfuWaYxy6Qw42x55cugj/V8LiuFHifLKyeDsvj5BXisPIe5cn25z5B334mAICrLS0I/pOjejZA8h7GwH8RQWZ5MJDswVIoF24GhYs/zyPwqWxoQGSrFWn0NQ2WJ4BK/YLTF9XVZh2HuypIHJ3stc7nDduBu4hvYgbuCLcge9iuFuUuNZX7bKF1VTYylsGhAyIvjAJQWE0oCI62HEFmB6bZE2d2gxyflBaXRG6iR24XQr71M0de3a2xH8AZ1HmAJddzW5xSSAur2p196+EllfkmWk1IT0pXe9W+NKCu6C6buYvYo0E+43k8oYcKLZ4u7nE64xo5rdyYKJtzrmUDI3tWXzmSNrbGW+6aIi0v/WbiO+khT1+vwFluyIVm+qByoIZ+M1xYWPn7ERcOYNEDCgLMbENhEy3PMbFwsCAbVeG4U66mWjQOkhJZ2c3aAllAoXZOjFtdraanHu51K1zgm8ZOW12eiuy2uE++Sj7aaQqEmD1eNRIXqvXGAqlC9NQ6QFQrPU5Oj5gSrbDxx62EnTXa+5e2lqjteY/wWThu/cEPpik9IkvwKVvBQvEzy8Kw8eqI8hvwl5Ym/GSmPI9+hPHqmPOsbyqNmyrO9rjyxHhwqD/0G5dHrn1KeUPxmYfGLXiiPB0Q7oFOeaLxWnlDZXiqPcgPlUW6gPMq1ylPK+ni3s/LU4poShdy98mjw6aHyaDJQnrYlgJSn7Qkg5WmbAv7vBXuy8ugr5dGgPKooj1475dnwCTXK02y5VZ5zpjzL31IeNst59HcozzlRHmveUB4zUR5rX1eeCK+R8tjzO5SH/ynl8dcGwsIvlYd1A3rl4UPl8XNfK090XClPdFwpT3Qg5Sltw3i3s/LorSqPQe5eeU7wnWPlYSPlYSPlYSPlYZ3yNHNl5TmvlOcE5TGgPLxTHoZPqFEejpdplcfNqi39t5RHz5SHf4fyuJnyiDeUx86UR72hPHKmPPI7lMf8MeWRVVjMpfLobkCvPGasPHKkPHKkPHKkPLJTHgHyYUF5ZFUei9y98jjwubHy6JHy6JHy6JHy6E55FPZk5XFXyuNAeSwoj+mUpzm6RnnwHWyVZyWznIf+JeWJLe6h8tBvUB5KZsqzva48qQk3Up43+jyRAEPl+Y4+jyF/THksCIshV8rjAdEO6JQnGgfKY3vl+R+WaGfn###4028:XlxV32DM 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fa4eNrFW9my3CYQ/Zl8AKtAM+VfuVWsVXmJH/zo8r8HkGgaSTBb7KQqnrndGmiYPqcXGHJjP79RZsONE3f/4pbdf/3gVt8IUtisoEUROoXJCpIU6W+/azgnN67jfX8mvUtqzghS00WF+xdVzGw6CjradKLMt9T5XBqV+DSfMUUhO0U23axFITpFNt3oonCdIptu1GZ6xJpierZkN12xvDKxm8cXcd/XWN4xt8m+uHJlMdzgHVpp0jC9aSyeZtMkA37ZyPKu6pu4mZ9/UUWyEf7+F5VK35g197/T2OmB9GpUek0KzdI+pY3IIo1FOossQSLLi4hiEU0iuvj8yfv3vNX1Tbb9bqPIu87T/+TnZkUaWd3/SR8nNylVMW29URXifbdX2DQJMXgSm+clFovW+/172tU8SVo1z4sS/SxhnyX9s8/CFYFJQhpxEdtWbMN8z+5SBHU9eWB7HjjCwCsMLGHg+NzAIpz2JXl/3RdxsS+SnPYlnvfFo335QYnOSv7zW96hPPv9W15SefdV/v31I7AdGNkmBFBKFo4VANAodnzmoYqPlweKi0eGdB02N89k1RSEzMBknWfBMEsGCKwAmEWBP1AMSGNWjHHSllyAVcwEXP2ylMs8brjJG2WAklBR4pe0qUxt3yDT22uHmgqV/Lrur2Z7LXipIMmvbH/lnQNcIIWymJ9VnUs4uruE0hxcYuXgErK6RPWD/LqbSnyZYHeGvxNLbCYouvsg5Ys8OaHTMGNzQm1hRj127zKiOI+4wohLGzHAiOt0RBbJeVcMjCjbrgAEpfloV1jkJ8y7ivm4/RdgWkNhWtsWkiRh/3rpWt+YHZTS1ACWF5dnzuSfZs3PlAdWiCLJJ/oHSmByFPRZSAKAmVuDxt6iXKLt/BnSKa4CdCSDAB1JH6BDtS+vdw/QkUCAlhypDwFaCtDJYYBOq+4CtO8UVwG6KK4CdFGgAB0p1mwBOllyDtBZuAXovMYtQKfdRgF6UQveoBafF6XxJCg8p/UvY+pR5P9iHjVhHhV/B/OoGfOQd5hnmTEPe4d55Ix56O9gHv3nmEc2YtGXzKMODxyZR4+ZR46YR46YR46YR/bMExt9LMA8sjGPROoj8yygU2PmUSPmUSPmUSPmUQfm6SbZmUddMY8C5lmAeXTPPN1eY+bppu+ZR4+ZZ4n/F/O4GfPY38E864R50u6+wTx6wjwqvMM8ZsI8yv8O5vF/jnlMIxZ/yTzu8MCRefyYecyIecyIecyIecyBeVagDw3MYxrzKKQ+Mo8G3TpmHjdiHjdiHjdiHndgHos1O/OsV8yzAvNoYB7fM0+3QYh5NMGTYOYhJn+1NrmXP/ckjE8eJMMF40Ajwg56Ex0PgWo9ty3EuW3B520LXyKxHLQtXGOJwCZtC3fZtjjgElQGdzQoKewpBy0NLgctjbqTjzsQaQZ6ngF6G1wNehvPz+CjmPQ4bCtoIxn3OBw5b2K87nGUPduaHGVxXZcjeeGOj2wWgnygEcsB8R4qhTxWQU15YgMNMR5pe7wTS0DHe7ynz4U6m8Z4TwqLFYD3HT2gALwH6rEc4O4jR/IC9mzGsTuyCQvEy/pQ35EUioFnZKjPpHdf+Z8E6uQ+NzrANDXu3ezhAFmGRWwOWVOodADZjMXqbTacIfswaOYV23GPUYjWiNDuxSajLVFy0GQUArVh4otdRlO+STFAINEwsqNnBB5htyPR4e8kYCRaGja/yVu14TAvrYOhJXsYzaahiGyJxXJApyUBywGdJu4xP89QvLw8UJzckth0HTRTolM1tgemJb7Os2BcWmKwHGBpyYLlgMqMCyQHVJqIx8/2ZhOOoCyyjMmyKtSytHQpcOM3d4ZbAstjuI0i4glm9F5T91GwLEBAyLNmOfsvBEuFetnPIA8jzs9woT7BxTm8N1wsLcF29qnIdMKFv5/CezxDpTiiPwCE0uooGueylkosB+CY2D3fgEMXLAfgWMLbzDtwdAUOVdiqDji7W+fvGsHAxE6OYMCxHGBgjUTyNOlXdqeGgWoXcn1ZvqsEh5s9uz7jo+zxQwhcuLnWbObmrR/k3UtuLu2E/qmt3Te+qFfysDyuG5O/iM3JLXnbyZtHS7N/43la5J9yVVgO/ilrCbbJwT+ltVW+E3t5oPintGvTdf4J5WX+kpB/6lqubHLwz9U5LAf/3L7jKr/0z2JXy5a8oEiOMqS1HKu59AWEs996Oax21meqnZM3s/skhToR+oND21VOqp+FrK0R4CbVj3mm+kE4WHkcJ1jMEMBBfDG/WnkYA4wZCoWOeDGMrNKMw8iC0qu2TxeHuOE+ybROYaQD3eZ8KXHIe7dlXHmxXUDRcnfcbC0KKOvisBwAuzKB5QBYLVYsB8Cussr5dgi8PVAAu9aT3c0qBNiVqaqJfSam6+ly9kKUia1LJweIr/X4epMDxLXQWA4QX2unpsiLvcmEYyZWZDkTK6tC4Wgt3VF1Yzd9AWuFYH1d2PBzYSPOGdex1tlxKcjEkdf4viOLqSObqSNfleeHULE7tB+WDsCieYm9+4I7iIP7BixH7quxHLlvJ2/uC24t9gs75YHdfVdsFa7xIRyUj+FM3dGUqV9fwKFcPNHkeobbHxC442x860ZE1HmxT7WvEEs7RccszQN9vwx2auLdPJD3033H6bgRJaK42I6neLonY2f28jdv0UbGeUl9dh/2/CKbhLP1ILAcvNPVgjWPVLzTwW0yW7vb2yw4W6+98s0SXOYGXufp8iEbJJYDWTqKny/zK3oiyyLLZFms7MDgxmCQ8k+BwU/AEPRHYHAzMNhPwGBnYDCfgMFNwBDW/xwMDsBwuHhmIzhXVxrYKLEcgcFXt7YVDA7AYJvuAAZXNYd7ZzYC6HwHhnpSu8kRGAKSb2BwF2BwFQz2AAY+BoPVrxQEZnY18wEYxCwy0OfAcJHa23uHCz7DBf8EF2yGC/YJLvgsSLDncBEvaAKDgQMY2DEygNPzPjIoLEdgqM6rKjNzDmBgTXcAQ4Wc4sfIAE4v+sigsRyBQSL5BgZ+AQZewcD6O5ik3JS+Lo+ZXd45FDRQJh8q5zfOB+nL5w+UFKIZnRmyFgz8+tqZoT333df7o+NDPzk+ZD6OEPjK+aFn4/ND5sMIiq9M4fzs/KJNEdfXThD9g6MMysqZTDkD8+1Q0bPjoaKrx/7ZVFSGpL9Fp0HXquFWwqZpdwyIqxcZ8kz72Z3zcOYIlxM2Q7ozxwr53d7uzBF+lJBdtDt0dEunQaeOlSh2DbqUDfcMNk27Z0BqDN40m/me9/cM6pbuR4+edUePrOSb8Mx29JifQY213Wqf/CJeUId8SB3mfmwOH1jFPPgZxOA+wQVfvNZ3S0ulMwppcdOap34tcXJyd+aN9cAbcsIb4/LuJd4QE94Y13kv8UacnO+wVvBZ/fLNgwvemPboOiqRjUrEiUo0oCfiTkf6m3aaa5KJPcnA/aFNg0mmsYgAkoEOGHESqY8ks4JOHkmmEYanPck0wigaTDJLp8EkEzsNIhlPsGYnGXlFMhJIRgxJRgLJiP5+g1cpWVcpH7xo83GPbkt27b4Prhw5P2l/8/jB/QKnl0nOHD+4X+CEmuTMKAWI9oMbPi199rXLnZfUwcfVY81sEgKCIxLLW/pc24R5pC19FfUurvVL0/Xps6/JuD90rVHK6/fOcRm5uZ0jon22HC3t9+NsAuS4SSLe+8ne5WnQtC6MsybJ8lxd+Oh3ek6FWV3oP6kL/awudJ/UhWHWL1FTH7862bmsCwPUhcf7AK0ZEfomicZyVBfGWuHVJgUPUBf6pjvUhbW1ocKxSQL1Z+ybJCuWt7qw/jrX7acqZchzXRhqXegPTRI5BoORz+V0Tx2NTsGwzMAQXwVDhwA5Q8AnLK/EDAGfsDyXs84IebdjOASDBDCIY5MEnF72TRKD5QgMFTyqNim4BDCIpjuAocYMJY9NEnD6/rpLsFiOmiQKyTcwyAswyAoG0YPBkzEYqH2vY/hcm1DQGQKuTkzEv2AccVo=###3716:XlxV32DM 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e6ceNrFm9mu3KgWhl/mPADzsK28SiTAWOqbzkVfRnn3w2BgYRu2XZWdtNTp6gXF5PX9P+CKXf6hyHygj/9hrsgHFtYsMWRhyC7LD6q2EFp+WadQ+MDCv+hnqCFVqGH88m+ojD6o35YY1B9YKhc+ShSCzIcmRfxK+G9u5wcW0qcAFqvaW5bbueWttuxby1ttebvXMotjpl3LFu0tM89ry5stLXNUVqYsR1uD/5yJPdCf3+JixG6Wb3Hw6dP39Oev/+ymQx0S6oTOQwvLd2pxilsYNzGOYpsE7/HQUuhpyRXCh/Adt7WyOL/QiyQmlqxoL0kj2UtY6seUfvDev8njcjAe+zcy9U9APPWvSv9YUtQmHBY8zzd++E6lW379suHpfeAPFR6f+bkvoVqXfbEpCYsoXV5MI0FuGRvTzahcZBFMOxKLLIYhvLTH+iNOtHxID8o6qk7POUyuPOf14jkzeyLALedHHqYnZ2kv30l7MUt78UbaUzlLez9N+7oc/iwI63IJQ1iiAoM4wOBL0ochQRj8CuMNBqxKwos9GWOFHQbRynoYnCwl8gCDL0kfMgTC4D2MNxiwBvHUv5RnGGIswyB6GFYygWEbwmAqDDWklt/BBaMzLsg9Luw5EXTvDGSCyIbfQEThCSIbescZyAwR+rsRSYUJkTClg19UXSa9X3gYB35Bi/IXvY4VMiIrbmUHvygqn0bS+UVBMSRL5xcbjAO/YCCe/YJc+AXZEYmj7PxCjxEhaIiIPiNiz4iwF6zDzBCx9xC52Dy5DhGpZy6i33ERNXMR9Y6L6Bki7hYiDt13EV1dRB1dpKq17hFBMA5cpGyBZFHxWGF3EdXKDi5StD+NpHORgkJIlg4RCuPARSyIZxfRFy6ii4uog4uwMSKcPkHkwkXoCy7CZ4iglxE5uAibuQh9x0XozEXIOy7CZojgey6y3XcRVl2EHl2kqjWDiDiEYRy4CC9+UFQ8VthdhLayg4sU7U8jAYg4VFAMyQIQcYjCOHARAeLZRdiFi7DiIrRHxKCECPnQZ0SwC+vJ87OqqCQITpmfYSDnXRbtnnRjwZq4Avw6lxhtoqhxl0tlOJ/nlE0E8+uc4qKdWZ0Zn1kPueXOm5b16mQbnkecYJ9ZTJWSuFVeYwbREDfew7iLcZLqcxivmWiKWOZ4zURrZOs5ZUKqkDPRIDgqkIl7jpSv1dQIX+EgzsM34h8hZZSMC+SCDvhzyjDzZG+ez676JLTGnOT4Ou1YTbuSa136TbRYpUHyay3mGCiOe7ajd+dE0TVRoIg3xc4rOlBsQoquUrE9FGwl9FiwCSlWQCV7qNdK2AlbmFys3pitfWuzJ02/Th7q98pwlrO4YFm/4ww7yvKUQ9rGIQLKtHMwXilT0sN4pYwXYnK8UqaEKfG8E8kVEmVK6lbWUabkfjbIIwd6n599KnH7eE38hhEbjMfxBhBCfcVgvPqD4A7Gqz8oaUE8jVeakz+kWPSHNCvgD0rH7mTwB3VxyhBHX/hsc/TIInLfw+zFr2evFrPsRdPs/WS3ccskciLHh6IPJpHnnErEdfqmeEvfIvo5fpG+Kd7SV/PWc04HLUr6aglHdWkS6WsgP3LaDczA3jGDiQMcZf+o9VOBF2mnMBT4Zv9muyXwE1UHUp7XYyTlWNScxU+lXE+OpwSvb8BgJjCg7ZaUH/X7SrTj0uyirdUx61VJL9NtjSSD8Zb1eoPxmvWCd3GQ9UWYtSpZb2rW+1bWZb0QO6V55EC0wwmHlyIPVVswCuNVtaua5/hZtXO8qrbgK4jHAceaR9VOsaTauj/4ehW/HmIXu3qFj1C+eB9E+w0Wtj1/3m7jwy5nYIOlzvzNL4Hy9AYshMqVBf6QBa+2yTHUtft+vz27qdngNgYjtT/dOJEOhM3LUrLBxPaui9fE9sq3llKepAopT3zfC0hs73Y1j88IZGMYmIUFNR299SAeWv8en3dnDGkAIAU18WNjWPHju5fkEUdj+OxG/4FdaKHGdiFQS1fjHt/NDMXRaja58SdGvbzz12xy4U+MftkuNCdjuxAIXazT7fv+GyYSFyybSJxhbyJ8T8U4RLh1kl28mogmDsYra4ppGK+sab7bgS7vd1OFxJomayvrWNNkKyWH9wWKle8IBT1ESwzj1UMyUTVeqVXlXiHHK7RaSBBP42Xn9wspFj0kzQoCTMkEYPIEYLPc2ORdHB1O5wW2nI75n1y5asFmWNOXsbbLvQ2hZmxGuHiDcDojXL5OuBAzwsk9wrfhxnn3x3V4TQtgZxV2OoJd9OckSWC8wU67+hewi+6cpAUv2O7XuqlChp3iVtbDTmkpYUPYWQ87hfEGOyUwfgU762GH7WTY2QXsrMBOD7CLCezs8fv2HnY9PNH9hos8LdCMcH6PcDsz7oMOnAgXM8LZG4TzGeH8DcKnHs6mhL9/excXrGDNh1gfPJzBOMC6i19h3Xu4qOjygnX1cMpb2QHr4qRMDLFGPdYcxgHWAsavsEYd1uVAm+IZa3GBtShY8wPWk6v6VYwOgqPt9p23PhcW/RnA3M0AllOAP7+ACBipGZ/kDT7ljE/6xh7bz/gUj/i8eHN15cAjVFVFVQ63275HVcA4QFXB+NV22/fb7bqllmW77SuqupUdULWlRI1Q5a5HVcI4QNXA+AWq3PWoWhDPqKoLVFVBVXaoYopjXvjw2DGpsPodVrLy8MTIDilR/SvZR/A+OhXjwEe6/4ep6PCeinJtt4Oa1lTkt+H8h+o8JCzxnvuYkvOPJJwqPdYfSQBcuRpTlRo8/7bA6dogOWPK9bRBku7WD2tiaoPtqkDX+ydu3lqTICYnpXFFabb8j6/zaK+zbZtHiPhyU6fLB7NfSHGz53qaW+x4+ZY6jXVyBV0rkEOFCAt1uJbHIPJVJ6iFbQOhoFZ3BVUpqFVdQZUKWq6h9oKqFZiUC+H0tBN9uU7Gj2IKivtXG5m7XMZ7yaBWgFkDzaCWdwVVNKhlXUFVDWpdV1BlI/w/hiVp6HEkRTnSzQLbh5ekI88xfYqrDd7ZY0odXCGNQwlRuWSF3eQSuSuPmCiPQH9LeeRMeexXKI+cKM/qXlAeMVGe1b+gPHyiPOv6Fcqj/pjy8CYs6lJ55KHCUXnUWHn4SHn4SHn4SHl4rzymyYeoysOb8nBQfFQeUcvkWHnkSHnkSHnkSHnkQXm6TnblkVfKI6vyiKo86qA83Qp1yrPBbnrlURPl4dvfUh43Ux75FcqjZ8qjXlAeNVMe84LymJny6K9QnvWPKY9pwrJeKo87VDgqzzpWHjNSHjNSHjNSHnNQHl3lQ1XlMU15JCg+Ko+qZXqsPG6kPG6kPG6kPO6gPBaW7Mqjr5RHV+VRVXnWXnkYgisElYdh2A1UHpTuSwfK4/VfER6P2ER37BectVB61TTSHff8rIUkmuiOe3zW8ohMZMf9/qOWR/zPqE6cWdaU2OVJc2IudMUaApVjneDY1mynNwbGgdxoGAdqo2C8/c6g/Po9PeH8QwNUXyYiQUBpLzWovJhIyXaQGtkm2ymNgHEgNBzGgc4wGG+/Wig/mU/xJDJxDN2VDNsHlqUlTS5+igsMNEaVv7eSJt0URpW/N5N66PWF7b/AMSd5WemFrDyQjX2bgiSZsGb9c9bkhDW7fgFrF5uU7dThDcwqXeW3XHEuBZ96lgD4nE4Ksn2vw0fAOMCnZOL/AerPU9w=###3892:XlxV32DM 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f1ceNrFm1mS3CgQhi8zBwCJtSrmKo4ABBF+GT/40dF3HxaRJJLApV7siRh3O1Mllvr/j5TARD5WYp/fVkufbz9Xyx7ksfz615MUNylOYtwTUeKUyOWxqvAsV8Rf3n5SIhjKUiH98xuVi0k5uZKYW+snBUufVPmXb6t08RIVKGpT0xhf1PPtzQarYsI91sf26x8qSbyN2p7/UC7Vgwb+/B4/Hy+IP42MP2NCpdaNfqaQwiGbQ3q/2uCUSilLSspSlLIspxYcWnJoxaE1hqjYUnvPH1RSu/+ypGaelhKeZofH/8mvvfPCyOd/8fPkke6YgvpBZUiDy8NkNrZCcDetSQ0Ti0Muh/YpIBtOxSn4Eb+clKrzyPoOhL0DlOm9A6vk0H6Id8xfavxZbvMjfa05UMcab5yH2I8syqWOzMPIvKt35qSO7DgcR2A4MAz/PI0soJFF5SlftJPGmDoWhZf+fPsZ6LJnYifjPZKS16TksOK4S/ElXb9IHAdHBMJxHBwRrG4tZ0PkC7IhyoRDr7AdiLLVKlEWpV/G5HZkl0gdi0pOA2FdIvXM5BES2iVS16KuUiN8xZnYp29Jl82OtdtgwvhdOpnNxh7+wmwifg+8fP0D09mz6QyYrjdb7z8N/jv4jh5NdmFF5LuF9b7bLB/bji8biDPrdGQ7d7adPetUn3VqOge67dwXXx24UnAgga54NOMvONG5cwNg8XUZWPz1Bra8MLBrq3PCYTYdPVv9YHF78POF6zuL27KApEnM5v43jbY3uw1F1amb2NRuwfFmasdxvC1zbHdnaiGbOl9QTO1Ey3WmDq6iIPdwz7CcYbUd3pndbjjevO4IjjerO4nj4HTPOYpnCMUu7KsyrLw5lhbePKq28Abn0QXc7xfEX76lPyIU4sqeGvBRWXQBLPgdC5Hq39eMzfRTXdChIuG4+B5X3OrturbOjR3Sly07KUbVFSnKrUlRryBFflx1jisnKO57rEBKDyTdtR9nIaXWvkUFLYrqLhGgQTV2Vb6hP99Qww2bXRncUM9uuIXtPCUG7kfblID/ufnIlHhCTjhwlTeh/OdhFAYatW0UMeJryaTrL2Y3Pc8yScKOI0vNpqqRpN9MSeuaDn1a5yLW1YIyxYgHTqzWttuiomC1BseBH6vVOI7KZIXjwI8tuLrwxm+4ACRsrUymKHuoCwSHXOghslrZBosgslqB4wCR1XIcB4hAbV/iAJEteBRPfc596CjC9o5ljJTBlUqedJW852haoJKPcdzTEpc7X+SEL+av8MVnF4z44sIX8EWyGV/Ifb7IdcYXdpcvPo9tyJf1C/iy/Rm+pJFVgGxnviQtdOkDX7YBX9Jtr/hS4me+lPiZLyWOHsM1PGiv9THcNL4IlD3yBR4votiu+ZIGe8WXEj/zpcTPfCnxVqQQi+KFL5Jd8CUFC1/S4Apftp4vEk0L5otCLfR80RO+2L/DF0pnfLFfwRcx4Ytz7+ALn/DF+ft8CRO+uO3z+ZLfDvwRvkCBEps88yVqoUv3fMmxa76EAV/CgC9hwJfQ88UDJXjlS2h8USh75EsjkxjxJQ72ki85fsGXHL/gS443vlCC4jtfxBVfBPCF73yhS88XPF2YLwa10PPFjvkS6/i/wxcx44v8Cr6oGV/UO/giZ3wxt/mS36EN+aK/gC/yD/EljqwCRF7xRfTpA1/kiC+UXfOFsmu+UHbNF9q/X6HwYlLKnS+UNb4YlD3yBd6bSjXkixjwRQz4IgZ8ET1f8PU7X9QVXxTwRVa+yJ4veHoxXxxqoefLNuEL/Ut8sTO+rF/BFzPjC3sHX/SML+I+X/SML/wL+OL+FF80AMRd8cX26QNf3JAvesAXPeCLHvBF93xpFYqufNGNLw5lj3zZIGeGfLEDvtgBX+yAL7bni0HxnS/mii8G+KIrX1zPlw1NC+aLRy1gviwq3T1y66Evdn22CU8O/JhtgC7y/Laz7cSEVt0Hdd6JAXe03ZR4wzDe0FxFe4JS/uaOZpyQ5dTXts8RWqUQyHhLs9++qIta6nW3axEjVXSpWaRvumjdZUDh8e8U3a/IJV9T5FK+0NYc1vgiHeQ8Vmb81NZl2lbiqhnO4K3EVTLcE7SXSEkupK83ExdBP2kzUT9f2Mw/bRuy+bYhJUHM9g0NKGDTH943NM/5zn3szGTjcPFtrVXunTuHsYnJ1uHi2/EEFd65dxibkLPNQwQAPTHVYfLSZiLy2ZIpms+ZhLpPmMfWW44EeAcfJF5qomZ9l2lmJN50mWZGEmBvPsC7rdDOxXiF0ocFx8NiFA67hrt9Sq4raePfSZeBRSd+ZusyzdzEiy6DzgkEjjN799sG4rKhKd2XntCtOHHaV3xN2kQs13S7iLnXW1RAOOMgGvJ3ODDPYyF7caDghVM8p6M7y29ZYGcsaPtq1kxYYJ8jDaODA73rw8z1/FNc72euZ5/iej0+HcSXBharbp0OOiHTD0EQGgj8CQQLaL+rRaNfbJe5RoQ+IEJ2GYyIxgAPHms1qQ8ofUBEgKflEE6IaHa3PSKQ3W2PCAQPe0CE7jIYEQZn9u6HK0TA7mDwQ0QEQITvECGYHNehsVZtz7mVELdO7E08XlpmA69RfX62zFb7vf4FW8dFapyT8zPmizWqYHy8mrLgwFdme/epu+anjdHy7aWJKm5KI+vMVOZwSddwbJgyBRBvdpGK4wS4RTBW4/v2Vr4ga00w0XKdUQRTNSMPNoEzMCmV5Znv3NQpmG6fzeXt/mhUEuKxPORZkUQdlXg4qHZZedKDEqsA9Uwn7AM6sTOdwFOSImR8ZGs/n3W5eG1nneSJ1Ed1uJqxWB2SExwHdUjOcByJw7QWdnFYEIfGrZ8PINePoacUwdNE6ThD9vQN5wOPLz+b3D9CPAMSN+OnZYaOH/hw7/mje7Iogx9iT70fe5zN5CzfL2cuZnJuz2WWfCr2uKrY4+wgbF65w0VXJzS8cYGVLUDZXHTK5nA925XN6waW4LLleuxxWzOHN+KCV8dxg9d5IwKOwyovuEbx0r46HSPMsYxQzjoj2chfOjo6vLobT/uvnBc25/PCy/m8MEVF/8RsxtHZ2Xxz95DwKyeDLfahZZNSn3H68VLfskmlzzj5eKVvHJk93ouXzgbvZ/3tYYGpNX9zpl1V0WOauuLMNMTOmbYuRqlryJm2FiQlDsa0tbYocTCmqef5UgvZGPmCbAxbi57SOjKmrYtR6SEypl19bafbCrdswXEo2S3jOA5GtrXiKXEwsgkBxVN/UxeORs6xZOQ8qlYLWU7RBalOzxegMr0c5JPxu74o0519zeGjs/5X/tSETV4du+XuYoicp8L5jFxbAe3Nwj/d7/zmuC181txb+N7i0GdvotE2Wxv69MQ9spCqFVlqA9lALwuOgw1UlVUaY5ZVviDLCs58plxnAzj1mWa6s4Gqx+zT14tkrReD4yBrTVYUT+2nWx5lnWNJ1rmXaH0q2x8D1Vp/59+RmZf+sUpcfK60TGdaRmvNVMvm8sUylrWdyZrel7WZyXq5LWs6k7W1d2V9/TTSFE57ha8Kx0HhmtKq1b0CyhfsCt9a7qBwXzN2pHDaK3w1ON4UXg9GaAoKtxcKt1Xh5qBwNeGyee3F6j0uqxmXyWtattdc5jMBy/sCZjMBq/tcFjMu08/hsui53MWbagmwl1UuC1CtbLmDalXN8CGXVc9lj+OIyxLFi2r5hWp5VW3/3KDy+8iRavnLm8+XrJ3pE770a31einKbiNKE+6J0M1GS+1SdidLqqSinSqQHJTIcR/wEJbrKz6bE0HK9EusLaXXcAkP8PChR4Djip0TxosTtQolbVaI78NNMlLiOlHizLFivywLiZlL1L0l1VAvIGUrTPtL/CJlpxQ==###3664:XlxV32DM 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e38eNrFW1uS3KgS3cwsAMS7KmYrHQEIIvxz58OfDu/9AiqSRAhc7dZ4PtylSBCJ8pzDK7FQ5sFkfP5FFSEPxsPzG5P8QR7pV8f8+w+VKuSHn05HmR5Y+kd+/EWF0g8qbXz+jwpNHpuTz2xM7SkO7cVVe4bYoT1HXu0JF1/tURWgg4KkhsprqUxv6QVPntnkkCm9+fzn5e7nd819eth+/J3dpYrPD+ZoshtGsN1mO8l2Yg57/tzUyvOokB5SWwGV5Q95flC12VJia4lqJbz4d9WPf/m3uvjfsD37t6r4x/Wz/9zk4Z+q0ml2uEmRfR69TA8fTPnnzwRSyJ+rHvxhfryCpvfnK7yep1gpf+BhFYqZdTmMVmOTzSZHcGR5MVFsYinY+VMPcFM08oMzlIxcUYCtv8CWuzO2qdqArUPYJkaa0UsARrLKyPcZrlcM559neFgxfL+d4aFnOMd2xPC9clVXhgdguGtlJ4b7WmJmDE+gdwyX2I4YHpH9YLi5YLipDNcdw6PNoMvH9lADw1VEBJ9RN/9uuIimIip33VM42twOvyYDlUAuJd4hAzjIHxCHhhsrhKus0ES8xYr86/H37JgdlOgXPPmDci8ScPnvz+9HJEtJTAD5TJCt2BW2A6FCJdRhB0JFG5qHAmipUACN1mLviFAvqOtrCGGaapRB7ApimmT9jW3q+PBNH7/iCHLFHqN5GpkoNVmQYjJoRAui1L4bNaqLXwOcXGyjCxhHomsuYsedt118pxu1h07K9xRA/y5+O4RTJOkR41cZjv8R5Q2aQJJOPztqvuiwtNBgyl2QuI4ItU56+sh/sg+B/WdKfCTMjhLs/VWiXvDzBfzxq/CLFfz6Fvj5Cn5zM/yiwc8H+BkEmQ/wcygTC/gFwM+n8AuAn5/gx/57+LH3E/z7HH6/fRX+sIKf3AL/voKf3gx/aPDvA/wegrwP8O9QFhbwB4B/n8IfAP69h3+zyH8H/+aQ9xP8cg7/br8Kv1rBL2+BX67gVzfDrxr8coBfQJDlAL+EMrWAXwH8cgq/AvjlSf3Yf69+7P0Ef1zAr78IvyUL+EO4Bf64gD/Ee+G3pMEfB/gDBDkO8MdaVpqYwJ/KKvxxBn+u84I/ntTvkf9e/Tvy3sOv9QJ+81X4zQr+W9Rf9tBT+G9WvzUAv9Vn+LWCIOsz/CXKGzQxg99U+K2ewm8q/LlOB79A/nv4JfJ+Uv8Cfkm/Oviv4I/8FvWv4I/i5sG/wW8G+BXAbwb4FcBvFvAbgN9M4TcAvznDT5D/Hn6FvJ/UT+fw8/2r6t9W6ve3qJ+u1L/frP6tqZ8O6ofwl7Je/bAps9tC/Ruon07Vv4H66Qn+gPz38Efk/aR+O4ffuq+q363Uv92ifrtSP7tZ/a6p3w7qN6AxO6i/rcrdQv0O1G+n6negfnuCXyP/PfwGeT+pny32/f6r6ucr9d9y7GPZSv03H/tY3tTPBvXD4Yplg/phT275Qv0c1M+m6uegfnaCnyL/Pfwb8n6CXyz2/V899rFyBf8txz5WrOC/+djHyga/GOCHwxUrBvjbskwu4JcAv5jCLwF+cYKfIf89/Bx5x/CH3ZZTcfrgA/olTBX0C7APjEPQiwP7Lf7ugf33vaope+gifXQaSi5Pt3MRCmDgqLEWmhSAcmicIHnIIQD6d5Y+0OIl56nYICDkk5Qva4uOmJBkCOcj6KMTUNLRDULUnywHg+2NV8EI3JQmlVbMcfQCIlVkeRxKE9DDDTHdysf+Khs65JG2MQVKn0NK6cg2sVOi9HqEMke6qYR7ljEV22czpihNGlkYhdF44CY8eCOTJcblbstkqTanBj/PZLkw5jf35zmp9cp37dMsKMpzsXDKc9Gat0r9TW3kvBXLdkKxveW/aqrzsEP+KxKF7ZD/CnU/W+yZfhnV/AKjuEuY+0TWtlKYUdI01F3zYYekaZQM2UuOjYU+afry0+VKSxo+cf2hR/5bW3mPyF5OSE46sL+4FXAhCV5uBVB34ji9OH4Dju+qZT7ZyPFputOPzOhuCUS6ysK3EzlNtk+xNFMS849VhGiXhk8FBBc02jCL7Ig2gdW8bEmcZ77aPKeEyLA989Wajt99Ar7xu0/AHzBU++GYuswXozOT07L84ccl2KbHSefNWyQ9q/TIKvN8d6BdDKHKqgW9ZDvd9e7Tl07OpDMj6SwmndH7Yr0p4+RqyvvLTc38gtWeN1a7T4+9jdU7f1Eof083qBpVb4ow3906qWdLhx3YrnlEdsR2U88pDxdokDT1kDoDi3Rg6g7msIMONA/Y3i6iaIntoAMtN2QvF2H0PoypxdYWJ0YHZIfFSRpmSmRtGmvtxVjLB62Yt7RyMQLrUStsfrnlYiVCrwdnYufqkbqpx4qFeuxb6rkYsk03ZBM3X1hI3c7RIluQO06vyFytJjrex/CiXu4JXjI4i+1tyQBDcLGjJQPFdlADFQwX4MEfljHlXiKQnhJhcQGwPjVFcAHQPq2IFC5o4z/BLeHxX3syH/+JPI/7/8q64ep21riUvhj+tfeL4d+3Lb71N64utOerO4ju03cQvVysqWVLIMXPr1YuLoot19S6XgTLnUIq0NJgO6hA14zjYQcVaMOxvc0J9Q5QsSMRHDwsBacjKl0vFGW0kTyEk9gO6rBcYzuIQ0mO7W1O8A7Zy+VEz4c5odjwrVsXFroR0/XSvzMHfHJjuk3UtJgOhIlLNd08HWjPVhrzn9eYXkwvrl0CiuGt6eWT+9bQaayexudOYY1pju1NY02TutNY057uNOYNsmONOXjhdPvvCE8p6aYg7RW2t3VX02Q3ASFN2l5jAtkPjbELjbH+VqjgcrrAopEN4rKjuPQoLgPiqopaTEoT7Yz7XL1YSgVxcS5yoR038suM2rHALySYsK8mkV0vJ5HFzLGmcthfPMjuEZWDD9gOVA51rD3s7Z7x1rXTNsy7QHa8ZvKwk9bdhtlHbAfCBu+xvR2+tI23xoR9Ua8W4BXTsVy7PrbevH7r3PrVxPW5Nbe/f26917hrdzqUheNa7abn1tr1h7Ic2btzazaPgDNvReDVxCQC4YYIGHY+lma45DoChvUR2JC9iwBfcODNCPBVBNwdEeDnCHBcMokA7yPAkB1FgFKe30grpkeAEIQ6Nms2huB6AzEbis/jbxfCY/RNfSjTluti6GldJfh2u8u0QU/M1v/DoPqNmaMn6c34eqCkPtQiutUHyAqW+df2vbJXvYL/VCTsL3uFekNZfeD1QdQHOfbGDjzzcegNU+3QyDWeJUuoQTf1wb7OP2G2L5+cfebMYPKX6xwVIPOYkOorlI3sgfFRIVtJaClNVm5u8vby9jwc5eEeXMo65VBWLmGj+hTq+1Zf1Kko1Td9fQL1XavP4VCXlVu+rT6JUN+2+gz2+5Qw9PF4X0/J1pW0jT0ltCtpO3tKSFfSZqpDiFDSpqrU5Xbl1/c3Oo78GasvGYhVekISV1OJC/2HFO5WClf/lcL9SuHqTyt8Xylc3aRw3wS8XyrcnSoMCt8XCndN4R4U7ucKd03hHhTu5wp3TeEeFO7nCndN4R4U7ucKd1OFu6nC3VTh7qRwhUt6hXMU3l7hDhTuQOH+rHA9V/j2hxQeVgrX/5XC40rh+g8rfCcrhev3Ff5/+dhEXg==###3868:XlxV32DM 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f04eNrFm0uS5CgPgC8zB+Bp43TMVToCDETMZmbRy46++8/DCGEDlVmVf/Wm0yVhnvokAe7tQR77f3SlOj78/kmlWcIT+/U3pYd/BIXaw6Ml8VHnAhIKuEuBLRbghpUCSUrc/oMuViWdJkEn6stszw1xYndoctl/cMNT+c225SmUP2p5GcuzXH5ryxMob2p5EcvTXH5pyhMP5XUtz2N5EstTwtHgY6d/cK2zhjWaI2q2rKGNxkSNyhrSaHTUrEkjFNYoH6ZwpSZ1eV3Q9PIlDmY98sQfQcPLSxvMVXj6wVlo8rcJNccZOh784X79FQYcXlBu/4vKVYWh2v2fUDCawj+h0vyr1/P3lOvt/NX515Dzl56/7Pzl6TcufTEyEx9CH2wsGv8gv86Wl4Pu/1KpwsiOLXVnC93Z2H72UcpQIzlbJOb8PXtIbGogTFP+e8s9ict5PlBSHoqKsvKQehdnxkaRbnule70S0Cv9Ya9QbygvD6I8yPKw3HsTS4u2N/7WG74a6IwJjS2lauLKpG8TxMOQgWDeQzysVFvghjgfI55fToiHhk7Ec5NdxHN5CuWPWr6LeC5PoLyp5buIp/IZ8VRe1/JdxEP5AeJJ00U8abqIJw1GfMOaFnGBprdF3BbE40sbzFWLuB4iLsU3ES5mhOs/RbicEa6/m/BlRrh+E+GyArx0CReXAjfClwnhohIugXA5JlxUwiUQLseEi0q4BMLlmHBRCZdAuBwTLoaEiyHhYki4uBCusWYUxJcL4Q4IF0C4vBJuJkHcfBPi6wxx86cQVzPEzXcjvs0QN29CXFWCty7i66XADfFtgvhaEVeAuBojvlbEFSCuxoivFXEFiKsx4mtFXAHiaoz4OkR8HSK+DhFfL4gbrBkF8e2CuAfEV0BcXRE/xogr+k2I6xnix59C3MwQP74b8WOG+PEmxE0l+Ogiri8FbogfE8R1RdwA4maMuK6IG0DcjBHXFXEDiJsx4roibgBxM0ZcDxHXQ8T1EHF9QfzAmlEUP1rEDwKIa0DcXBG34zxdfxPhdka4/VOEuxnh9rsJ9zPC7ZsIR2dpvku4vRS4Ee4nhNtKuAPC3ZhwWwl3QLgbE24r4Q4Id2PCbSXcAeFuTLgdEm6HhNsh4fZCuMWaURD3F8IpEG6BcNcQrlZ3Am4BcFtiuNiuZAeFYsG4wkgK5CBSe+EdRGYv6INI78ULFFFYqeIQQMT34htAJPbiJkBE98ZjMFEekhUbpWIzsqEiTGemYklgZkY9LVgIUxiFRlKHE64gSoNP5ILo2AvEIAqDL16mzHNLqHaFUFb6whcPXXGV0LOa/+iSqqmjDhUrehtksM0ySA6DdBbYJ7dBuvsg/W2QB7kP0qJB/rTitOw42oR4AV3Ic58Zu5sxSUAv8sDyo4DrNoblpgAqpMRyDSBKLpAi88EibnnioU+rSxqR3+HlHYLZVUpjOZArNcFy4FYphuVArVo9koc+pT7Eh9D4ykntV6X2tzHJl68P9lhvRGrbCbEtTHy/RleMC8TVSolxKQ/oUyJXVgxIEX2nBCJZtXQr1pulV4MMEwb1LROD9Ps1SA5Mjp1HlLFZZEBWMCwHA9KrwXIwICsWJEf2AzYd5wktumUKy2HR8/IVeXXUIUqT1PbyoI/ltrLsWGI2dS5tyaqka7Krm68LdSbbW/p+hdIF/MrW+JVS8di/KNI6mp+hqbKRJGkhEN5haEejw5iBpScdDlBErVgjw0vxn6SRTX2KnBHr5zmL8FKc4TBvcYK9p4kc/lD3+bUUzW+JaS06oh+HuhFGn9OfYvnArVOmBtP/sVsPNbN7zR5qXiGlk1Czf6pmmxI63udT2KVGRTPm8wwF14BRuQz9V2fyEeco2cnfaVCN4XhfMA29Qph6L7AcMHWi5FuxquRTU4nkU72XSAlGqJOqvke79ll6Gu3zrL1aaras8jq2Ocq4SutEQ9Z4MzqiJ0Y28M+nWw4Vb2M/ykVog4eNCtceFsyuTy3Y3KGGrLHc68YeIJca/l4bjalp82EbTY3LeXpAUx1rnDohhlNnyRMz10yXkJPpkvzL0zWYIyHbOQIDzZruHAnZzpEQWIPnaPPpvjxMEb+n5/x+il5dk04Tw/v+g20O/Id4xn/8/pl7EjoZK27Yqg4+qhA1erFInqFJmw7rbAparBcI7fHMZsPsM/vopDnWuUmaI2qe7NVrm4EDp/lhP8jG3lUK0smm5taHXaqCIMsZti1lTKOopkU4xRqU1/iybY8TgzehEOazAhKbvGhFjhMb745xXiM+ldeUKvtxdYG0ZiXvS2tim21wcgfWdHOaqMKBokxSkteExpumqprOcCPQCyiwGGbDhOpgSuZOPn3LxvzD7Ifed+FsvuXW6fJfDCiT1fmat2y5K3iGL+NETIh64q6OFzMxneAaBBYpbSV6ey1fsvchORyJTQmdcWyNYRpWHK4xOPoYJrAc/IMpe5UsB/eg/YLkyDkY5nDTyPJ1ybHiSqO9cTRXJAd3YpjB8rpNKodgSR7zuNjUdW+cZGhvvKVvNuJp1XGHgo2h0Pv1SPoCh35hPzAnosadKxpyG59GyaXm3Y5P0DDjNG7bb6fbwXp724jCxcI8bFDcq+dOfIbFqmqa5V7eRkyx2Oi5wdbXzcSmypEKb7DYFMdywGIrO8ksBywUHGPxFotsftA0wkKJQqTcmqMk4bAccNnK0VCWAy4bNVgOuOiyR0nyiIsmrD0HrllYs3cJ0DiZLlB6kcQurwQSvX8Onw9Poq6opK9SRqigj6CceC2KmP1JatLtCx+c1m7ytdPaCIubnIm5+smHf8cWDowrNos5qPbuGg4qH67hgON6MAeuBIEwTy0HvIQBoVsOJJYjDhSWdzgQzVWnXtjJgdAnB6ELAw4obznwcRHCqj30jQNH3xM7egGja+BkZuDmOQN/ORakWDy0avuyVYvJSZJ0qrOlqlY9Pz6qpiqWvqmKpXXZK5JjU/XFAYfBX1w2mGR7+l9NmAxMlQxMlbQu2yN5MlVmbhlOkjXOek33yl1nbV9x1ma/Xr+3dvvUHdws1Rd+druG8pnXN9SXe3Fs1thJy1lqs34+tRF8YteeTO36gyu1Xh4TxtHmMeC/Q0f6xs9b4xdI3vjpFTeBjB8Zs8fGD9xlORi/KtcpWd4zft8Yv/BInv20vBt/lCHjP/fi/eMudqyT4y54tX9evvJXz7ua6w4zOvFKOrT/t2UblBXozMt7e2Zh960Lc+SJ8NMhu+X/M7sXer9V/2CLb+dbfFcTf/JU7Opwj70DPlsjy+yyhQ8OhZ65EjnGd+hyYRV49uW9jL3fobvOxUm+a1iutyXlkjJ0GN2iw/VElkPCh25RjvZ2ZcPyervCNJLjw8ISRc8+IU/ifTkubA8EHFzMtgcCmQOQg8dwC0fy6DFSW1eXkYX4upy66C76J+RGPhPoBL53McktDw9w5WedfzQPdLZDz5WMzaGVObTDcliZOMoqb25RSPpaYeAzpZr7TD3xmUtFWbmnnaYG/6cnTlO3TvPACuQ0nRt/C0G9/qSzrOnPIF2/3h04T8YuL9pPmSe9fNnlNSmOt8fEGDX/Qobt3WmBsQ3sGyzHcuQbHJJj32DPZY2zhL9zgwCaFdUDWInl1QM4j+TNBUP6KjKYc+9iX6vRZ6cvfobGp/dHPn2RNNqy6bUuhZ18JvPqZ2O+83EOSkWX57yR710n+QOuMEhjAMZieTUAjstjAzjOLDNOEcolHfNYDobhD4HlnZunrADDyMtf5M0nNZLn/xDLOnt6Zt37D7XYi1lV15ScmO2caF3U5f9zvOXd5JtB6ZEtu69+M4jyHWx7Hm69aJvIeCxPicz/APWAS2U=###3628:XlxV32DM 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f78eNq9W0my5CgSvUwdgEGACFldpcxAgFltuhe5TPt3bwbhOJLgR8SP7EXlj3KPYHjujk/w4Ivf/uVyeZBH/LuG9Pe/VCqfPnxZSrmJn3j8j/z+iwq1Pqg0YfsPFWskM7olon5Qtfr4UZFIXMJkxF+UsjQi+/13Hjsxtn+oYqbwLPBs4y2Jp5hLKzl4cYKtjJA+/cPVnn9P8dhx8shha+HgkQ+O2r7SFvPA4sEe4vexhdVtZbNr2gtTZS9sLX/VXvYUF1Y/pGm3hJa7ouUrWtQ3tCyg9R3++wR/Gt7Bfwck9gv+Dnhugr8D/PcT/njsHn888gn/MMRfiRfxDzP893fw9zP83Tv4e0DCX/APwAsT/APg70/447F7/PHIHf4so7c86GO54L+vcQ82bv4R/39lcUmWb4lEy/Yswyy6ZWHoIgzGSR4XQ2dJhW5Zt784jR9M0+GdVAwFiYMTgwcPaV5iy7xkxywX5z2QjltleQFpq2kF8atxq5YlDt9tx7GJQwtHdhyTOKSMZjAnAZe2mJALa9qgjMDJC3B5A2fFFR4r8L9UurXT5Djinke81d94hB1IcUU69a3jDpQuTpRX2maM+yLrgUWaM9HjvtK/X7/KtoDT6SBHLKR4QXNEF/EX6Z9Ep3iolVR99GJFP8DaSExacyQ+3AVUJtQVRW4U0gVjk5qYA3Cjj79Yk8y6XZSagVJjZT70+0ZSTc1dEPn06kSmDpGJvSl3ECAze1Hu/aLc6a/DX9FIySNMeWVioClcvq0ph4LEfcmx9UrPYF9OTIzWw76wsdYtIqMFdcw76/WRHEqUloTM2QeO6WDMgShMB1P2WXSV3gz516FzbXKk8n5f649EHMzFwYzJg3FMT4syaaxAF0xPizL5ABb1VCqMtKqoJl+/XGCIHldVFpE+YYMrRHTUE7tgDthc8lmCjR3q/ppDlXziUOMuXneokk0cKrFvOFRBq2uT7OxQBQMeHzvUyDscquxRpgseu3OoCx65D2jEMg4o1Yv4ixn+6zv4LzP89Tv4c0BiueC/AE9M8BeA/3LCH4/d449HPuEvh/hr+iL+aoa/fAd/OcNfvYO/ACTkBX8JPDXBXwH+8oQ/HrvHH4+M8Xd53Pt4cmUX2DvnWmCvI9xitEDAyJV6BiIU9TheD1vmeifjauZTOBhDOIMTC4HjaiCf6QBNcs46aY2JCmiuMcy+XGIWDTFLH6Pk8OUU2XSRjIFI5hyTp7/8QDWnvjgyJ3odxywp8qk66PdJzGKuvl1vl9i8RDZdJGNxJBOMvKwF4gyhmoUFfo0zRkETiiyCqSGokYcDjylMdOBVFQodooqgDaa3qEI7TIeoIhiB6CiqCHqtDjp+QqFD0KFjtNhB7x0DggcIQg4GBA+HpgGnTB/zhKyFGZpIfehrXofTk3NAPcr3gLRsg5D4ODUJ1ZPglPJqv1K/GZzGGcx1hgAzMDghRHdCvBD+7vRyTINaLjnmPdTSPpWzVlIEHimns+E4ghNk+Sj6O++tO5uiJA+NSavCaSshO2a0UHcBtaClDla+UYJKQini9ocdIQ54+jb7q6stDiOPj8NS1n0nRqTHd1pSeChmnaNzHdnd3LsOsz/lOo4R7l2HbXLT9FXfUR1emqL3HdVJFs6971gExonX6D3Tke9wud4X3cRjvSJAn8h2b7LcW/s9lW7YducpHL9xxOAo9hasB/VScnuf1LplUjCSDmZbCRm7Amxo59l8Z3u1sJOmRQ7A1ZCz0MHY3LJiOtia4wHRkQNwNUJNKKJj3rEV0+GUdzXXKPSWIfId0fsj3oxLd0zQYekJn9XHEPcnqaBwVstXTtKcVNfCWfo0MIvM686PVgcwp1ODc8xBNhOyE4ymdxPvR0WoRjO0lPvACswBxr8v8fCWhAV2tYKh6n8TGKEyXJwehw8rxfQWPawc00GtwiowHdQq1NAh07FaWZs06v4MisnunwhfT0cTPQUgN0eTtbO6m2+lfu/+eAxrBRsHC4K1tk+YFLiPA8ue4oemENYe+UaaDh1M1kpMh4PJ1rpIpqODydrKsF1Ny3KL6aBZ1ipMB82yRGA6aJatzi3TuwNL5JxpkBkR/4xq2e3e1X2rWuxWtW56GJPUSS9+kjm51g6yL2ZO+3bnG6dapwUZZ07StcpzTphfqNCG7a7Dck2tVK36p5Wg1GoRGtPBs6qaQhU6KPAiFKa33ovgAjGQBquaKSV5IA1ealuh0EGDl1oGKXTQYKUZpre8StTcPjM6FWaMDH0uDeEH/TJGZ/0yeu2XOfWJfhnqfTHa9csYNA0LB/fLXMfB/TKCObhfFin7uNOof4KcmyGn/h/IuR45uMhQOPfIuRNyO+Z0yIllUlESV5dsnnLJGs7NJ1KFeix+kzL4MAmWpG/BkteTE9I+5ZfNzakUF7BMCkq+tSyCeymLuBzGXTYRg9JD4ml+dBi2OLgwmo5A16kwUFZvAma0rD4IREfHYdlyZnShYoyZCWbAediC6cJowSLtRkIHYq0oZAY+EP2e0IkK+/DX81DJNxq2z/n14dmwbBdV5du8hytnAf7evPq+vp3mTl25d3xSMIM22/vdXB8mVVbpUcVXfl9lPRmHG0asLZtLG+xqJtC89aEry0Kz1/fNXmjq+lOztynsqdnLEB3bSj1/y5JuW72ysyK/G0wHIyqKD/RWrWUU01seLxdETzW5tIRzozfTWkLsnUB01OUtq7LR7PYbsxMvmN1zHmJigc+bmZy4Bh1afWd5ysyecw0ji5vdnyD2Axa3TnJCr6Y54TwRxGbFhma19nciKKY3M+ES0Tsz6abAZlKD8iROXJeAaxdS3t+IkLJvahhMR2bCEb2YCbsxEzYwk/4yhFd0XCFb9DMl5TrEfYVM0UGv4fuKslf1jIoz9GJUFHNuS2eJ1VWUd0TH3ciYjEaOirGjup4Uy/7GPTXcIM83vMSoQb60dvb+bq+HajLu9XDSSvpreK/ZkxIdU1vhmtY+TJq378PEwWvPO/O6TruCC8aajjvtmtZOexwBFz4Zlfg7uXGSv4NKoFTg+btufE2hy6+72xCrHos/Wu7PxG/UTPzsI+LfZ+LnnxW/UU38+1n8K1x50Jeb02u9dFqGGIjfwEULvY/En75ziH8/iX9F8/fix7OfxD+xfrP+VPx2Jn7yCfEbMxM//bD4LYjfmIv44XHBpaFBoW1RhhiJHx4unNoeWPy2iv/UAKECz9+LH89+Er8bi3+XPxW/G4ufBf8R8U+sn4XwYfG7Jv6r9cPbBnO1fnjdYCbvJgy8mzBj63cg/rP14/l78ePZT+IPY/FL9lPxh5n494+I38/E7z4s/tDE7y/ih6cV5vJsY4XHFWbybMPAsw3jh+IPIH5/Ej+evxc/nh2Lv4Tk9zkiM+Ia/PaN0puWy4s1Wqw+rVBY1CcQP75bIJy86fZfu6o3/RN8t4yosfZIbl6O3M/PKOIMenJlgbcLEsZ9ouDcHm0Qdb4k7ytHd3UTSjD9ekm+0Nt1NrK2GXL2lb+Qs69Q7w2V2ZEFhHprKC2jqzMahRmoRrJjemtK15tOmd7KjPjpCVHd0xNi8KLgicmXdV4Pa+bxi29eC3jRAMatROfNpOgoWuwU6OduFdgiqVF1HN1ra1c/X1bYm0uYBITn+uI4VZiB1JZielNbJjEdqa1DdHwLE6oPEW5c1IPHI5neqhVQxcj09n4DTK8wWrnCa0THhfGQS5Cjng35ExW52TUK+monp6x/pKBhee6W8GfKdYGKSf3a+GlTZ3bDwj3d36kdk7SUToXhYKKir1gLTMftHYMZTYcp/gHWYTirGevbO/XmR2EgJaaYjpSYdz9ox26tlmd6fxeIpveNt28cYxb6ziPHcv1k8Mhxoev7YePllaPla72JcqqwoTswdPTIMbGQp0HXWigOzaxleKj2yBFKcvkHKC6zNuaPDx1PBn0D6jLyTM9czaa3VztHbuh/fC9XLA==###4044:XlxV32DM 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fb4eNqtW0my3CgQvUwfgHmoCl/FESBQhDftRS8dvnszCEiE4Kt+1cKuH5kSifKRSQ7weFpr3QM9WPiH/vyDuVQPLIx8/ou5Qg/u3DMS9QPLnYU/JUIPyuzzF0UmvBJ/7fG7xd/fVO3x928YNzJ4N65FZVyP2riujMtRGTfwFIkv7M8iopLcs0irJJ9IrpvAf5iTSCF/fsSpBPbzJ7U0MGxP3yKdRDqnkG4jHafnEaSbSEeRbuHzan/+xJLoxCCF4Q4BJtI34yE9CjAqCdghPQoICMRxDKBnAdg+//61GFGUUMMP9ufQnspQqQcJwn5RojIuMuHyCwuXCL/DHBNybYwO+f1AKDx/IEQlr8DvYUDB8sBZz7+xkL6TEDSPKM4TTzIiI0w9/p94qONJn/RmIk92vCApaEJugUPtBhlRFeEDD03QuSY4AZrgHmqkUwRdKIL7ogghOkWU8SYKSd9K67Tp4lsp/FaMlIWcIP9n/O+kO9qrgW7xJfEgD3GhhrQgZJ7mXB3spBfqLhaIP/RidVEL36ta/A21xLnuc31bU9WNX1Q33Q57SRJ6dWf9JJ4Dy441KOjBi1DkESAo1HH4TMDjeKbBYzUF4hs6gcGA7IMhD9jcHLaNfBM2soBNfh82hxewqTdg26p68ACbqzyygI0U2MIIM9hIgS0+A2HjQHwHmwCyT7D5udOx6I7ToW7hdKx4Q5u+znrucyJv1FPlQO1IyAAuhzEyX7qEhskZCTbpsClFkoIkG0kWwa2cJBKGJPaMesO2KFAnBTIW9UcncQsDcQsa45Y6thnji+0JohjG3SClRTGs+ECskFlEMX6QsiEg5T9GD8cVxYHIg5WAIdNr5MH4Bugg8mBUH4ygHRBhMOMgvUYYGcNC7yMMbhK8+Are8PJXnqmLONix0R5jXnomzFmNONArrilIUmgIQdomGoSeQhBuOt7oVAoPmIjXHQPuyrwXpVDxINQy+A7wIELHKYSw8bEN2rW2KfFkQ7baUPzVkKUSCy47Y0bzoqN54UQiJ4sb4WumJ6kcQvtmetJW0zN+YXrb85w9VJau8XwlWWiVYlPzHY4gWSegbLeQvgxdrXBiGLnZu9QX2dB3s5beBTh2hMzx27rlKsSxDcW5gXRFCAXp1WkIYSG9Og1RbD3RgdMQ2kLRwBpEmVREPGdQJm4k2iNIrwmOZBukV/eTV3ulV/cjqQD0MKU0hfhHtMSSpiVaNcS/1if0w94W9vVx86VD7tM2Xb/pcc9oGU+NaIW5k/EEn7AdEMSBJ1ttZF1G94kB9lMho5gtTM+NLoFMXYIZt9XsCvS4+R4pe+8S2MolxF963p+XrgHNXUOc7C3XYEf70WPWby6yfiuSy524Buy377sGmZLaSUEjari6BjJ3DdHo565h8Hr+2kWEbzy5CFvsCMNKR3URmQ5ch4B04DoIpFfXgTn1gAF9h+RwTnAn5dSVd1DnPByB9CvngTrnIRmkA+eBAD05jzCHwXlEGnAeWkaVBIfy0IOV4TB4C2tO4Uy2msFU6MwessfRSo/2UHcqSavHUS9GPGVVamVGAXsVQGpIxV7JI+CyN2weAbMdLPuLCHhY6/u4oENyFrWUlvKP+Dnd0tbyiGjjPMBS1dJCel2qqoTGcaS0KtIDaVVo6Ruvc9damsLRsywzslKSmUZuHl0rDx6IGWZ6oAWIeckdg8MgcLdinkUifKeIV4a43tGYau5uf7mIpw6dRBkdJllo5Vxue5EFlLRbBehg1+NkUciU9EYmXUa4toCy/g19LY/m5PBScfjJN0YW+EZOMKA3/DmBz4Nv361c4I/u4S9X+MvP4C/P+EvImeAve/wFoAMdOLJNdSDMHRWUES5VEBLfqgKNX1SBo4cviSI6DWSZlXOpgcgCGnDUAjrUAOVTDWC031LBMcS1Cix+RwWH+40iehVQDjmdCsrmG1mdCgSgd9VrL+ch/WYXIT1maYOZxfTaThzAooDmS8UrDj0roEUe/DTGIKODVyzg9ffgFSt43zByR2VBRJzhFZAzgVdcNmkSHfo5hKeZDfYXRp5TnCGvMZO8ZpbPTJMY3AdtrbR4OFXE5i1RoZu+jZi3RE/JzDlzaRlL1s4kghN0e7kNdy6GBQl0kbnoFiRs/FbmMk1XHIzuWqYbv7CvwPGy7uLUQMKyo45eExa/U0ivUeCOGaTXKHBHpIlOUWB6IEWBWd91WnBlo7pLIQZTE4zKks+MmptgRLs3anISvlABRquswi0Sdb0KXxxqnletIsZWethmA37h32g/bL9Xgs1L21o5X2wMT13J7XwBNq1PYYMtYYOdhw22DxtsCRsTvYVU1dXYUzjBmJw3JRieupbWibjdflCr9sO2bD980XMQaNVzUMuew1eNhtI4EKhrNFgE6aDRsAN612iwpXGg+kbDDumg0SABHTYalBTzrV+K+w2iAxgl5UJ77gqYb3RsVPnOKA4oUpV6SKa3tFQKQG+KDLEPwWaqAMz3VexTXr20ZkpBscvfDH7yiDGOiX9N9v3E6+I6Bhkw+GF6GvyYWwlOGWES3bfdUb4Y+lh3IBgl9KEP05BzHfowfRn+JTpQgA2OEz9k8EdyBNeIb3TRgC9PhbFJbYnhVmtV2zeLS1bS1W6h398t8pEoGhy5PGqaP6LQft+o57LkqaFteTlQJdmsbBNZqWwT34ZbSzp0VR6IZZv0AOh8272JhccCyimT9CIo51ixzbHW5j2sr8p8DevtE1jvK6ztJ7EuRb4fUWiPtdBFuacTPFG7maPMFOujMpfevsT6qMzlBwDW5fhDogOsnWpCe6xXdu3fxNqvsPYfwFq5Fdbuo1j7gnUQesK6nMNMnA7rYtfp7QnW/sA6vH2NtT+wjg9ArHUT22FtmtAOa4kWWO/vYa3RAmuCPoH10q73T2KtUcV6sOviTNXZrmUJ/fX0XF5kHVhP7FqjgvXJrm0T22G9NaE91mSONaVvYk1WWJMPYK0XpQRG8EexJgVrfcrurcRFufiMdTkYrckc6+MsX3z7GuvjIF96AGLtmtgOa9+EQqx9islNwNqMWAtx5wDbRUXKjudw1N1jbudzOLkPT0/9xotsNH/K7ESO8Re96XuH4S6KV9t4OEfD9NWpRbWJO3+rTz5JwM5zceNcug7jXvb1OClYZ3II0ludiUhIr2kdRmqDjJrXOUUAHSTI4JyHFLD9jZHsGLXIVGtfmV5T6lrjyvSaUvuSUiZ6l1KnYHFSb7V4epRE3zpKYm8dNBursF+s6tWpEnUVEdWCrGp7mFOvLW99a3l3Z8+ycmdnz+p+SsX+4vkSlZbYzG5MCwUce6lKe9tY6vkSdW7Ci9JUj3MEZhRmBenVjFg5YJnprczEOaS36ohygA6sSJUj9eoc9CtVCjAxWmvmpdQG6dW6vCaQXq1LKQPp1bpUMV91RINpCuV0CUVtWt3RtLTB6bCl6Ivyo1wc3ro2s2lF8mxT5P5OwRfXvUCr8Oq618UBrSv7acbi5WovsOASGL1Xypzf/JpsAKXYH2cCVm47A5wZbQcox3wzvS7dun4yvS5dLxmgg6WbPz0xeLcQpYT0uhCBO+e9myeA3h3Rpo5NK4epcjotHJY3ry8fbJNDQ4ueqWs3XNji0gE7HYXcIadrCOd7G9dVYbevv40vvs2+XhOFdyP44uP46UYFg5yuR7HNexTCfrJH4VY9CvtWj4KuehTyrR5FufQgaN+jIJDeehQC0rseRb300F23ZBZDOuhRbIAOLY2xuaER4laHAyEafKEySpaNifVBOnC9g3cqa9dBeKeyUq5OdNiN0H5LORF92DF0JPaV0NHW0PGbCRFeB4WGL24hCAe62vLlC0CzBneX6Bi8iAQFqbdZhH8xEjRcLVaKArumfSmD6vvzGh/e1+DhzOVR9YwTuTpzmengeHBpEyYGMMG8nKoMGL/pKqO7WhDG8pBR902ld0hvARxDkF6tOS+PQo8BnMFjAGdwH8DpVBycrH9Mvzyislj0+vaiH2/jXC1/ukj5hW/dHzs/pPI/l9lXyg==###3648:XlxV32DM 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e28eNrFmkuO5CgQhi8zBzDmnam+Sktgg9SbmUUtW333AQxBgA2VWZmqXkyXJ4KX+eMDnMTtH8LVeiPCbvf7L7pst+UW/+7hL7jM/f4fVT66/lizyPBAw3/L71BCqlDCuPu/ofByW7W9R6O+UeHDk1xCUeZCi4IdLR/N/EeEdLk9GttjTXt2ye0Jp3N7RO6mNMiXOESDh+jS6C027fBCxbQt6EU+tIovsf7+EUcQCt5/UrsGu9Ie2220k2RX2G6ifQl2wplDDuXvP4lcdexh19kR5iy+cfKw6JHQlght7aEtY462duyIgzKpKWmxPQ7KqGT32B4HZWSwx/+t9jCmNIb4EDqRdKnjCsqESnK7//lj9R4n1QZ1t995rtV+z6pQE+ZT5gAxMv9V+a9G82xsnHqDBQpvF0x2wQKxZCLYRJJpxaY1mIjY1RE2YfrKQ+zxHsInengbjrKEzyYhfLYN4tGW8Ckx0wdKhqGBwLYQqFPQAgRirRC4RyCA9wsNiwkNXBF4HTehIcb55zREZhANpATSEvvcVYjV+C+OVdFwUkNSNJzUkBQdJ4IgR8OJwX0jThBzquVELNhROalQK8wJglq1nOAODk7UBSeq5cStQ0687jEBBvS9ENNi0cKjAJ5CzAkTBpjM2WBswsa+QDCFBk9s4NW/DyZ7DiYNxDSY6AkmVHwdE8Ynm8bm66axnDHpXyfjsjVjx0DoHogS+GEUDRAK2y+ASHa8cVDkwECk+IK+ERChTnEFcRERNcCT/QKIZEdAKGyvQKSYKfYDCH0BhG6AsIu4kVug+qbOG4cmYXrXvGEUMkZbwSCgk27Wksmyy9ha4smsT8aTJReB6qFhCvGk6qnGPxaplp6OSxCpzCto2T+2oKMItSR2Rn//iNOSYvNHfI8mVm06rUXFwjhQTNrFYDvEpPG5fGzpkD8WSPLbhEj2QVSa5FHF0y3gOWTyIGPIHC1D7HzE0IG6CYIQKzGmGI/xIG7rTZxial3XR1ZXez50rPer1TSEGLHt4sn4ej7nlsWTM1OFW55bPDd8kGBCjMODs7JCErU8d/ptj7qMZW5jdygKmGXYDlHABEd2tDAxmleZODtoNWGWYjusJoeGxX40RGxUd6csEUdu7LxiLFHdVTUrBl4WjtWgNHENrXGgkCbPQfux03xwj100PB19ggcxEP7s1YUCfKcc2Y8AV3EKyLLLtD+vN36O8GMO8qrZzsXFyhja8uPPMkrrXq/sY99loUV3btFDi/Uoqtwj0xtmaNkz6qntdvaOuTh8vl9D0szS7EuLSGoBTTJZ7IbartMcPR61jFcYvsVplWH+5Xn+CbmYf+6GMdkJwtPs8Ws9yEZGepQePt9Z+L6fe/DQwzLS5+EePnZGjnnnSa64wcROGyC4zVF/eJCkx+yupfaloDyrmGojObnHBbjLBcLDz/hPaCK8UO0Xy03K6YzXOJAZNz3BbXsON0cmuK3uC7i5ZYLb6r+CmyqBH9rucdPgI2Pcgi/jFlpocNsoarvBbROo5Qa3hP8At9D1S7h5NsONvgE3p2e4re/EzbOCm+vOc3zP8354MG5lcT1qX+PmWcbN6WvcYoGEWyyAcVOi9tvgpnTttsPNDnEjSj2JG53htn0Ft3WG2/4V3AwE/nrCzYKPTnCjgNs62t3cOtrdHO1wm+xuQr2Im5rhxt+Am5cz3NhbcSufT7HTDjdZolv2uJXdzasxbvmTJ9a+xk1l3GKBBjdT+21xs7XbDrd9srvZJ3HjM9zMV3BjM9zsV3CrSLATbjv4+AQ3Drix4e7Ghrsb73AzY9y0eRE3M8NNvgO36e4m3oqbAdxOuxtsJqfdDYAwY9xMwW20u5mCW7+7bbXfFre9dtuqvY3VXvyLam8ztfU71LYztdVb1d5AbdurDWuZ7dUGPbax2ltR2w7U3oratlPb1X5btX3tFqstlgnb5LWTq1iXidpmeV1tkX7JHqmt/RvVji9zqB07bdX2eXIPD1JblN8ij9qXakdXUjvWRmqL9INUKRDVTgWuPhST4+pDMVXFapPJwSkUeUntdC87VHt9g9rrjG1D3ql2eJms9tqxLQgvk9uxfczuWmpfqx0vrZPaq71WOxZIaq/2+jslOa6+U0S+EK9qT9gW/EW1Z/u2YW9Qm872bUPfqnbZt2OnndowubpXu7BNzVjtvG/H2tdq5307Fbg6JifH1TE5VW3UnuzbSr2o9mzfNuIdak/Z5m9VewO1T2zD5J7Y3opnG6u9FbVHbG9FbXt9SkuOq1Naqtqo7Sb7Nn1R7dkPvEa9Q+3ZD7xGvlVtB2rvvdowuXuvtiseN1bbFbX3gdquqL1fn9KS4+qUlqoitfdEx/WVknzwRslObpTs+sqN0lYugWx/o2Sxp7lRKtfte4vKTh2yoxslxnT6yiZhZk/xTv0snwRdfDIzuZJE9z7+wdwKdA9pyvVh6APfQ5Y5OOz1HpJpZK/3kPHCPr5lMN7s+cdFsz+TgmMhBefBy+I+Q418kqFmzyld9SJZoCwc8vRF8iltJUzMNkuRQJvQ9mzOjZ3k3HDJ61W1fvqqus8m2u+nPIeUIbD12Q0lW9I2mTgou4G3WQ8C21HWw4rs6L7bEoa7Rkuc8SUVxkqcbxMDE9nhhtySpjzckNsF22PCReyqz7dJNpRvc6wAg6VOP7bUudlSx76c8RJWJ19WJ9cvdQ57Bktdc69L7YbsaKlzMlKlw9auz0udVY+Ar+7Xiauf59zRlO6Al4mLBJJjhCPuTf3s9k9m3+n7Vb5qXQLIos4fmSippF5OOvFcdlyfE9tkkIZu4ZJDlaxmS4PHL7JxAKe+4JUdAKrzrnHUnLlFcexBrAZDjqE48whJssgdO4BJ5ym2A5OHcsWOs1YISRgHGG8Ows7BpdbFIeM6U3qU4dmHWEPuEWBhDKmKbeTdSMnAtyjvBdLgOB+lPJ+yNn9RnfPw5OLzA1nKQ3GRtTzk3SGMKvpMOypzNSoId24+HRUaDaHlgZUHXh7EeTTrCb7Nn0ejSD3E2Lq8BYsrs67Lg8lxzl2Os/TOsdP7j9RhLJMK7B4KLF2BFJBUMygQrYuDNZJQlUZeK6/3o6MIFHQpCluEpuxSVJ5A+a2W5wW5UN625Rcob2t5VkgM5VVTfvFQ3tTytAIKmQWxPM7ZrvkIhwcBCsk/hwcIRSlDhwcYzSSCp1IahyzQ9OKLHZoS3mippGGuwhOkZREih4xz+U2I0xni/m8hzmaI++9GnM8Q9+9CnFWC+SXitCtwQpxPEKcVcQaIszHitCLOAHE2RpxWxBkgzsaI04o4A8TZGHE6RJwOEadDxGmHeFOnRRxPb4u4BcQpIM56xNUYcfJNiIsJ4ih975sRlxPE8ai+B3E1QbyO5lXEZSVYXSIuugInxNUEcVERl4C4HCMuKuISEJdjxEVFXALicoy4qIhLQFyOERdDxMUQcTFEXHSIN62NdnHVIb4B4gIQlz3ienxSl9s3Ma5njJO/xbiZMU6+m3E7Y5y8i3FTEbaXjOuuwIlxO2FcV8YNMG7GjOvKuAHGzZhxXRk3wLgZM64r4wYYN2PG9ZBxPWRcDxnXHeNNP6Nt3HaM78C4BsZNz7gZb+P0mxDfZoivfwvxfYY4jOp/1IFHQw==###3536:XlxV32DM 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e04eNrFm8uO5CoShl9mHoC7cabOq7TEVTqb6UUtW/Xuw8UEgW3o6p5U1qbSIsKAf+IDTIX9gzye//Kdll+6Ud4uRLuQ7UK1C50vPi1lxKWr7Eh+/YfKTT+ocvH5Xyo1eTDvnrlwf/DNpquNkAeXNjWmWtUk5Iufqca9XZhS9QeVNrfGfv2TGrGP3Obzn9Je9qkOEhzMyWHPDtxycMilJDx/UOV1sZncsug3s2dtiBP/hCbV80eqpPrb0Z+Cv+v+Mvuz6r+N/gT8bfcX2Z9WfzH4kwj+pvvz7E+yPyUbevjc6R/cmGpRg8Vly14tcrDYbNHVIgaLyZatWMRwj45Jwo3a0uVtQ/KmMU03ba4Kn0eTt5t20Cpd/eAsNZlCh4rcz3TjI/w6YkOHZw0itaUgYbpG5ubqb1E0/x7lZj9+Tf215Pilxy87fo+ATiPfYiyP5TNHr08XdoxeCtHrj+il284gfGWqkRwtEnv8Hj0s1T1/JpVOTJHYwCHtAnBjV6ZyaJqxV+auVwJ6ZX7bq78nPK4I9y8iPHSA4y3h/uRwITwuCPed8ACEhznhvhMegPAwJ9x3wgMQHuaE+054AMLDnHA/JdxPCfdTwv2J8KG2kXCJ5B0JN0C4B8LDQLhnZQAeND10A9wfgGt3BRwBykqIQA049kyLPZFkarG3tdgTscfegeFPqrYwNPD54TmrD5ZbKAHTwqY2CZYtB1TqTn7mjZNuQmJ4FlF51u8QIIZtKgCz21cUaFXcKkBVBAXkHyoQg66dzi0MCtQmwXKrQDYhBbh1qBwpUKW5V2DnXwuBuAoB9dcC+D6a8RwCEVsmIRBvBSjlSABKuJzHgAtfkQDquA8C8fdBQIm2B+C5jUGFo9Vuu9Wh2PDEQLjAllEKtcDBflEKtZLCvUYKdZFCDbaZFOokhcQWJMUu3FQJ6lzb66QCzfIDmud52wMm/UQbmlbvoM52qCOjbTsHTSjIY9vOoVWZRuK8iQDT/oTdzeeH1qY+X24WrUJaOVwOa5DeNS6HFaj2upX39SeHjMwSpvB46KtQG78IZUGoUbuyNYSnEM/ZLhFcKJI1h99+hJ/MgcAnAvMNtmZRLwR2IDDWHITNzeRHkEMzabVrzajeTN+XknMzjjxnm0Fo1uPxTFuEvQVs6kDdcdS9EeFmsDjYBRHuB4uF/Q7hYbAY2NkQObRTR5zt1aTBpIYNDJHbYOkbmBokYBkCqA4rT6TxSwApeomf/Ro/9jm8MWi3CIDgvxYA5hoAbhgJpptCuUEsA9NysHQZ0F5YnziKIle8J4z2m0XInN+tTjjh16xRqRErDlhhjA7CoIjdklV7KO91VS6ArsFddb0TcxbxBoMWJbnMl8CZcn00y2vOhDMbr6Ppn5epM+ABjoQeG6bUA4RTiByXI5gUw4bOkhS4JoRSpMdCnKXFbw9SEGyAaTsGh8sh5GJ7D6nlEHB1yFr5EG50EW7GvijcxCrcbmOMLmJMRt7ZfWmMsUWMyTKBH61uX5rLb2JsmMPNsY3J7Q4TtQnYgELLRGyA0IqMonIUWT1I6RBZ9UmhvAcWlbj8JrDoGFg0ovJhOqc0TM+MZHzLmRENZHFmhGaqt54Z0UAXZ0a4V+84M6KBLc6Mem80JX9+aBTafjs/83EmlBuEQyMfwYGcHOqh0S7BgZ0PjXZyHNIcN7NnbageGh1NokMj7Ud/Cv6u+6NDo7KwI38C/rb7o0MjrQb/cmhU/U3374dGxHv08HjaJ94Nln5oRLwdLGjP5c1gQYdGNGDL/bFwlnc4NHLsODQqN+2g1XAsXOi/R5zq8CbG+Yrx+F2MixXj8d2MyxXj8VWMi46wvGWcnxwujMsF47wzLoBxMWecd8YFMC7mjPPOuADGxZxx3hkXwLiYM86njPMp43zKOD8xjkWeHAxneUfGOTDOgXFxZpwuGBdvYlyt/vdDvovxbfW/H/JuxvXqfz/kVYxvHWF9y7g6OVwY1wvGVWd8A8a3OeOqM74B49uccdUZ34Dxbc646oxvwPg2Z1xNGVdTxtWUcXVinGLLbB3Xp3/+SGBcAePbmXG2YNy9ifF9xTj9LsbNinH6bsbtinH6KsZNR9jeMr6fHC6M2wXje2fcAONmzvjeGTfAuJkzvnfGDTBu5ozvnXEDjJs54/uU8X3K+D5lfD8xzrBlto7bE+MKGN+BcXNmnM9TON61jLsV4uy7EPcrxNm7EQ8rxNmrEPed4HCLuDs5XBAPC8RdR9wD4n6OuOuIe0DczxF3HXEPiPs54q4j7gFxP0fcTRF3U8TdFHF3Qpxjy2wZDyfEN0DcAeL+jLhYLOPqTYzHFeP8mxiPZMU4fzPjka4Y5y9iPPYTtUhvGY8nhzPjpXTGeATGI2mM1ybvGY/AeCSN8ep/z3gExiNpjFf/e8YjMB5JY7z63zMep4zHKeNxyng8MS6wZbKMJ3lHxjUwHhvjkZwZl/NTdf8exCNbIS6+C3G+Qly8G3GxQly8CvF+oBbFHeKRnRwuiIs54vXmijgHxPkU8epPwd91/1vEqz8Bf9v9bxEv/gfiHBDnU8ST/wTxYrlFvFhuES8WjLjElskynuS9T7YuN+2g1Yj4Itn6Tat4lCvE5XchrlaIy3cjvq0Ql69CvJ+nxe0WcXlyuCC+LRCXHXEFiKs54rIjrgBxNUdcdsQVIK7miMuOuALE1RxxOUVcThGXU8TlCXGFLbNVfJtkW5ebdtAKI072HGnpsR7qgjiT5R9nB9ONdRmm6ZbiyHc76hziUUP6sYF0yx6OGlU8T7vUZJF/mRo95V/ufLAd+ZfilH+ZbEP+5S6wJUnwI/8plm2oT5NDxg9uh3tqzuZWklrKkKZQeshrKqKSX0lF1M9L+mZNODOnhMU+a7ZWJ/lm/awwhj9LONyvGUo1K83P0hI/Qgvq3ClESGjo1HLgIzQ8ajnQEdo8U8t73sdQ/5D3IVmci7+JL+eBXnJnb/KMuvgh7oukNO1AfGP/ONvzJrN2lUb0EfiREZg7hcV3Dpd38V3E5V18Z3B5n5gkwzdg9W16h6Az8UW4JGaxZWJW2yL0vCxr90W2a7A9908tsvDCMkPqvF34/LD2mANy8yjX1bZPaGo5JFBZbnE55E9ZS3E5pE9Zq1F5T5/6tF7YaU5qvH4Ugb6FOG68/xbCdKF0+Er2++dHrTB/tpAuTmntzHcT/til5QiXcvyxiyMl6Y/fJP3RncyXnUUy4GUXCUsTEqWE1SwjV+59hjRfy+pDqXvOXvkPbfXj/Lr6FRp+v/odi15q4GZ2h68ZeHuj48oO4/nlBtqqmnYO+VnKcvpPbnT84Me2+bhYUBRE17JOnR2X3WjbZ1J2eLmpUQDlML2EkqbKj/IUNqXKYftTF/KjqzniSn9Q6EUXkENayatDX9ej9f1Bhk9PWNn4qwdDeyP4FM3ebI1mWyL0KUqtU9xHB+em0+iG8Ph9WKSqyfwrF84R6PFPP3NhFD7co+yIiNLeuONi8H/hasNTA4P/J9Uqht1YmTZa9WUUSw3jdzE7qruP08fx3K1mvPtKBXI6gkb/7QjK1Qjq/2sE+WoE9xeNoOwjyC8jCB98Un4ZQfiIgP4PmOVCSA==###5936:XlxV32DM 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kQdF3vcPuIfwnOi1tUsb7InkQ6tCaGG6NLfeYusFfiHqF6JCLDdyxwU7LvQLC7+w1HIfWhVGSdBafgEW3SOMdbmXqBDeSe/vHgFKW4zCpu4TAVryoVUhtHDmaYuKMOgWLKyyMCqEd9IWHX+TtDr4/ci5WFTawp5DLBaVJsAfS3WETU+YfMA9fuL4cK3rIYv4oYVVLluraxm4VoRrRfX+oEKsstCjIjwq0u8yHDxTy31oYZXLwTPzEZb7RPidsmhRhfA7zTRY5UMW4wm47pMfWuFDq8I7E7QWC5xwTwGLQqM/OIGewokCJgqcKH9oVdBJ0FpGj7BrgdGLGj2rEEa/aM4Cc5LFDde6K7Xyh1bF1iRoLRYFE11goeeUuTAET5sbkXQrnfahVUEnQWtMJHN3b/9rvW8fiWm+sh5gvh52SV+Q6gf5GxqFonC+yIz60lO/d97w+huM/Oh5tz7a2jYc7xNtKJbIAI0/tFlvsOaly0KWyBHNu6fAK9PAe+6AHgstPX41GPiNXOD3g6FR76beTb2bejf1OvU69Tr1cNElkR/UTlSBll7ENZgIb62EV2jCWz7hLZ/gWm2h1Ze32MIrdaE1aEmh/UTt5y36TlSIKtDqy+sp8cpZOK9wXuG8/JaP98wLrb78klT4BaVwZ4RfLwq/qhTukfBjaOFXghNVoN03sG9gX35cLTf7cqflZt+bfbnn/J5xoUJUgXbfzr70A0s/tdwjyz3iZ5bCj1GFH4KKpe9a2srSVvwcU/iNjvCD0fFZP/pyvZbrtfRsy/VartfSxy3Xa7lefmom/KhJ+MGXOPq9o185+pVjBDj6laNfBc/Y8owtfqwePPUi9SL1+KF7iNTL1MvUy9TLXC/ntfx7A0sG/GRO+HGW8MO18TcP6Mu/abBkZcHq/wF8mUkQ###6084:XlxV32DM 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ff0eNqFW0uW7SgO3BJ/xOt19ALANsOa9ahO7b2dF8JGUXbeN8kTLxwSyCAJnNl7r+XoP/828fvPz2i6WfE///yVkk1/zB//9182ivkTc/jP/2zM/Y/7z3/Pn8cf5/72zldIvfiPTZi24vsTxvPAw1U+XYXLVSRX8XQVffXxkI9GwkfryuF+fmYJZjXt5lD4+Te9m3rG2Rz+ic/EA4+piJqKp6nIORU5p2J7+oxEwuenkf0z5BxDecKx7NvPz2NOjTGGZo0eKuNsdKgCQkXjYexK/yyMZML+ZO8KxeVPP59NP1Y8QlXUAku/L7Bm9ILaacEB43ng4aoqV/K7q0KuZM6KcZ/PAw9XTS2A8ryW7T7W4rlWtzWg3uhtIhPz82/6w+gFAbybZx7+wAOPqWxqKvl5Km5uK2NCUGuPdnydpv/1/Ive07bztO2Yhz9MRWeYfV0AUp8XQL/Xjl9fuDHPGM8DD1eHcrX97qqRqzNK4Qn3O4rhdtXXFyQ7ucqnq+zrJsdIItHZ1bQzNv+Gg9iqXM+h7nuPI7m4/oTZ35v/Q2z5zR8wPw8e+BMKZ1Qo2nMokhmmsnUjf5oxNLvb8ITh2tPQthkKtscY+i7O/Yadcf4JXyWNeB4P8AiFXRdgcr8nuzPFt9V0k1Cf8JWHJx6unHJlyJU/Xfl7rVcTR5RkRqFE/4TvKOmhdBpKV0Pxaihf2pVEsw4Stid8F8qBh6uwrrX0pV05a15Z8xTPIs6h8PNv+jr1jJH3mO/E66hFNRX/vG2wwzOGNtuTaJ8xXJs5NcYYCnCw5jDnv3Pox1iTZ2wWnMTUH+z7sM/P8/j4eYQ6wz89P0Kh+l05fs/bZ6GM64JJlLcT5e205m2n+t1in6N+dTbGRsqTiapPXBeMmXmY8RFHcsviwhP+5u/eCwPfp4jx/H2K0Hq2B36EQvXL0ikU6QxFOkvYfswXq0tUN7okuBkKN/vXQ1x7wmzvzX4weqrsD5ifv0I18Ziq6nfTl373MDojGXnGeN6oDKX63fSl393IVZtdOuOrZ1m7eKf63VR+T4ZOoqXkpU6gbQ6Fn3/TR9EHEmA0icxX4oHHVFS/m/LvrftpWudlo6eyz6nw82/6Rnm7Ud5mvhqainorqt/NX/rdc+2ozszTgcfTgcevBx6n+t38pd89RJs+o2SfcL+jaG9Xqt/N++/JolBey8ZlZRoHiJkczgNDecJs782+m/YZ38lJ8zwe4M9Uvepn80s/2+9OyKzb5KxO2xPG2tnnMZD16F+rHVNnjP447KOVZ3xVPxlTYX9Yy8D8/FUtZQ2F6mfjl362SRR9aoj5CV95duLhSvWz8UsTWchVllie8N1+xLvd8H59wTH+nmxEYlKdlAn6nmAOhZ9/05959niyh2QCzM+DBx5TCSpq3ESGcyrhjlqdQ8XaOruD8ITdbCp9nCmf8X3H1Z8whgo8hhpVsvrS5J2ttzqmFUpWhZJVWZOVT6qzsS/Jah6OJTp9f2pcopTr1tY1zB3NmO292d+Mi7/5A+bnrxPwxGOq+v72pYlrs988xOt7CNGu45xqngtis+MSkjHbe7PvKe96yrvM83iAx1RFrfUvTZw1sepzu84QnjKEVxlC9YvxSxPXjTZ9kGvgqxBPPFxVlYzKy+1JHLfOaDWvS0Y65jHmw/Qxh4rqVMxITozZ35t/Y57xdcwkHuMBrw73XvWzMT+v5R2Hc4nqW0KhvMo4Gura51tge2/2txd7mEqkqW6UtzeVtzd1SvjSJPp52L5PuPqUkOiUoO76vepH05cm0ZIrVCPG9wl4TfGH6uJfLkXFGzGffyNguFLgs46ZQ0FTGPBFhHAzpvzoD+/bE2Z/b/4RNca4EmG+Ea/OZl71y+lLE+nmVLcySkqaBxTGmJprz3i5ndl1Hp2hvJrSWcgZz7WbRE8V9pbbof3peaz1tJ7tglEL8EvhL7TgsG0Y39Vw2VbBqmponzu7bRZud816fDLjqKU5FH7+TX+feDXGJzjmK/HqRBycWkD9+Wvm8h1MfxCYh3XGcN1oqtDj62ObyY8xFpycBeMJpzj2lrvqhsZYUJEWWKQFxqFqFKqmQqXun+OXZHrm9aY7SV2tC1XrslbroPvtL8k0kCs/b+EZ3+1QvKthUPfD8eXE7U0fJ+c+XjACisJ6l5Co7l/rLPSM2d6b/U73x/B3iMb8PHjgMVXVr8eXZIm8n+daDPNUYvc5NMLL1ff2hJercL02jZ4KMNa69TrZXoWfxsfPX032fBX8/AhFVgvsS7LcaEGdnWh7wvelaVyiru5/k33OMNmOHWwpSoGqIeMuOk+XOVQkz2hGxmCMqMUW0xPm8byND8dkHg8yDDA/v1Tzpa4UtUDfTlkYqtd7hXumhlDM6l7mDQFjtvdqn6YOf5gKMD+PBa7ur0P9Y//s8e8xQzNnaLsNP1cJ5WcjnhtsXhBu49Bgxz3OIdvHUdzHq3TGjw1g0+xiPJJ9mw3cZ3whRnQpo5js3f6keRGfxqs9tk/aP0+XHz4Ovhl3rHw7O7tVn0xrK7+blla9SPMrX0yLq77IKD7gjfR5oB/8ZlBcB39GY55mx/YLMp7rpvQV72X43ecnDDf9XrhseWyZPf48nxHnicscn5HNrv6jGfEHf5afpOcXVXzPpkDFT2Tw5eLH8rnsy1HX+AU5RPFm8NBXqWkdXzd13BKcExm6rQ4/1qwYvCPeEe+JBy42z9+oyX78f/YrvnghXjQfSB9IH0gPbO34XHD2j5944PMBMPhMfCa+Ed+I34gHxvqrxsZRoEpfMfhGfCO+E9+JP0eSVh4YvJejjdRe+orv/aH5QLwQL8QX4oGRb7zx+4iPxuAD8YF4IV6IL8QX4rOUuvLAl33ihfiN+I34nXhg5OMg21zn49oXGHwkPhKfjOaBwRfSF9JX4ivxjey3y36eNyoj32N/AYNPxCfmhXjRfCV9JX0jvjFP9oFdKaNey3n2/eR1jcFvxG/E70bzwODN+d5XHhi8Jd4S74zmgbG+EG+sL+CrnhOfmBfiRfOV9JX0jfjGPNkHRn6YneGVn4DBO+Id80K8aD6RPpE+E5+ZJ/vA1/6f/d61/3GgwP4nfmdeiBfNn8FS+QMYvCPeMS/ET1yLoJ6GMT8JKwYfiA/ER6N5YPBCeiF9Ib4QX8k+8LV/TEpq/0y87J9E+0fzQrxoPpE+kT4Tn5kn+8DoD+76p/HFC/Gi+UD6QHohXpgn+0L2C+mBUR+2uV5RH4DBY72DB7540u+kt/hdNXzBnRg81jt44IsnvSP9We881T9P9c9T/dM86RvpO/GdeDPPA+CBL16InxjvJ175VeO7v9X8nf8nJn0ifSW+Et/IfiP7jfTtqu8z/kaO9f0A3++HeNF8I30jfSe+M0/2O9k/T1J95YGv/tGIqm/Ad3+qeSF+I34jficeGP3NmVfa2t8Agz+IP4h3pmwrD3yfzzTvicd8wWcanxAvxG/Eb/+an+Z3io+d9fiqj1Sf0S/c9ZF40jvSJ+IT8ZnsZ7KfSX/3D/j1tfE+7l9nG/jihXjR/EH6g/R4n9evx0188UK8aN6T3pM+iOj6M/GVn4zmge/8RTzpC/GF+Er2K9mvpAfG/c0hddYpjcF3o3ngiyd9J/3Pd7iVBwbvRfPA4APpA+kD6QPpI+mBa2njt/TmfU80ra744oV40XwlfSV9JT3wPf7N6fEPfI9f88AXT/pI+kT6RPpC+kL6SvpK+kr6SvpG+kZ6Ky2uPDD4n3vHlQe+eNI70nvSe9In0ifSZ9Jn0mfSZ9IL6cX8y34i+4nsJ7KfyH4i+5onvZB+I/1G+o30G+l30u+k30kPjP2BfIP9AQwe+QY88MWTvpMe+Qa8of2PfAMeGHwgfSB9IH0gfST9v/OPbDr/yKbzD/Gi+Ur6SvpK+kr6g/QH6Q/SH6TvpO+k76QHvu6X5te+bIpb8V2/bVa/3j7xZtO2ftIzkugTX67jPj7PP1XObcWblfyDT39z34/GBBj28SfSsA+82fjpww7j5wfa6FfsSt3mX9fMvk1jzK+bJOufeQFfvOS+1m9gfI86TD7Wes/8ed5uT/5arGGMy9l1vP8HPFBn1w==###4436:XlxV32DM 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1140eNqNW0u27SYOnRIfA+JlHDUAG3AzvWplZe6FLWTDvphbaeSs/RBCEvphuOU8N6uNqv8dlPx5/sR0anfh+r/9+s1BbYzP4xq3pIK6J+w3fVLmHrchqbOcJ9IjdoHnp4Z/zHc2XTjSefM/9E127oqxuWZecoYmBoyfgcePxhfHDzrKvW7IO+uT9T1uD3+t/4P+Y/14pHz9etHr5PlOpeNal1z95wn2eR/0Q5xOxm7Tt/21Kve/O8fr7qrQraZlu6L8SI84hBKv32qZcOuhMvXjxuVbn0Af46qNf6yP9IjPwPNlfasP09t3V4zFvl/jsv+4PtIjDuGwg3/kfbvXI/Gf3d37QGE57hWva+hW4xT/RXrE+uT5sr82x9CPhxCpX/9rXNZH/0N5ECM/xPFkLPJlFfz1K/bdIt12F3siPoix7J+u/j/6X7rjLygX2b/n4+IfqN+P/f7h/yM/xLtiucR/ndv2Pv7o3O54NWTNbH3MV4iRH+KDGBtOc6roWHr7ORXPC3trbjvguAk75722Lu4P0n/Nr3nBXPSB3B0PPlR7l5/6Isb1fvqHd6N/jPggxhK/PrMe55bsLX9NGBfeKO23fSEfkjqYnozl+B/rUSF163tWuul+q+zY3xX7H8RjVnviecbMxoPaM++TufXAfJYvu97/wOujP9VCcMudGv7SLytz+wHu9672W99M1nLdHv3Jk7vl9mxG9cW/yqNX/EnZm4+JbI/Lz1m/Ect4gHHBWG9qH3DH4UaHn9UTsZ/sD9bbUC3HcVnSan8VlWPF/1AsF/YjNX1x/DX+X/sbKNmVflVuM6unz/q0h5n8Z5N/I3XvG/ZjnnTifWL//JJP0x5n+VTskxSvj+OyfvXzfWa/oArXTyqZfzXnv4PrqiKdWb7WP0A9ufLb/xNfRmlajQfSy/hNpD3Hx9jvif/U/c8r+6D9pF7JuCNbVutLfsJ+o+aFne206dW4xB+OuzYu66N9z2ZfmY/98Ku/Pds+Df2UrG9pm/KX/RP7fq0v+4f9kthH4vNrvuQ37HfcM57zrB8U+xBx3v3av6uz6vOLzM8qhdV8iY/f7FfUllb22cn4Xj/p92Rc5mM/KvYT+b72R/L7l/6vfnP/2q4SsPDPV/95/qqnlH3Wz8t8ya+4v6K/VUyO+fWU/NrOq1gfZP8kv3/VBxnH/Cn5TfjjeUvWf+Wf53+pD1/1RfIn9jua7m17MPaDUp9rHaBZvyjj8Sr9i/HaNx2zfvDhf2lRvsdrYSqrcVsL12q8qPIL/7Ktxo+Gsb8x6mj1kvuzPcbC/nTQ6F+MZbw8/iXxx1jGjTK+Hxcs44mM68cF7zHffZCvfW9fXwTLuIZxwV/9nVWp9X/jeUsR3XFOVNSs31bkOa8TGd4HrhPXQYL52/tX4r8Qj9vAdV7Gg+K+BNf3xP8g/c8eWp1q/RyuZwPnYdk/pN+Daf0y15uf8vA+qxZnSP+zfxrp//33b+8P90f9sf/8rR3VX3/89V/twvnH/PWf+lv+aPOP1XbXaqfWQlo+ajI+G2ZWfmDl1qwMFdezSsRRwaxCz8qda1ZVDt2zMg0zKxpYxTUrR6cZFTzzyyoOrOxvCnIaEbw1zKz2ntWW16yu//GJXhTkDMasjoFV+E1BTo6CQ8PMKg2s9JpVLaK5Z+UU52VmlSurrbEqwMhXRt7ukrDOehS7A8hxQqsHQD3DOR7cGBHT/5ivD04YZNIMu5i4wihrV/wEI30tqKbHrGjpFNVqrelOPLOeLNonznZiBiySnYqPyjj/zEfk0mr9DIvkG42aIj/BSC+aCmZNz947PjMFJ+fSZgpWZLeHU1K9zQxwcpWTs7vY5CDWSXRwjbPokMCmQo9YdPSKJfniJxjpxSaCWRPda7Ktd7/6jev9OjXJED+StZVwfu34ItuUvQWxSO4INAV+gpFeNHXDnpleUz/XVDRRzY+9OjK38tyCIZaVdxol2UGSHTQR3MXF1ltSQRwhvYGdEHrW1PZ+fq79fGucHr9XtuO09TajtXdk2lTvt5VzmmHRyahN9TrJfMkFp9rsDIuNTaP/4icY6WVPBLOmrtd0/yXft5lifds0QyySEUgiWCQRjPSynmCJE0s2zfihfEjPmvZdzmbW3qFp07132IaZU+htloBTqJzCG1FVJv7oJhFk5/ipWTTaDHHVWc9wZ1MNNtVg06FGi3xf9PUMaWb0bAnqLVHW9aDASgVWcm0lpEcsmkfQFPkVsFQESwlmTWKnifmlG6h7UnrJgtriDL/5e8tDPWjzXetzNtr8FDfJM2iK/AQjvWiaB037Dnbz6zgIbU+euGgrMaejt5lZ28yAzTQ5PcOiYz1EDjrKfMmKRjE94rcm8vwvfoKR/q2hvaap1/SXbsGr7ewjxjTNED+Sqa30ksl8yWKe2JsQi+SHAk2Bn2CkF02PYU9z7x3xlxra9kSwb5g59f21+aXv8C1ipM9wYY4fHQh0avjRqWGxSY24EyJw2CMPEYv0pOb0rOnZa0rzevDk0/tVxev3u3J+ht987PYhH7f5kivkMvQHlpMB5AbEO1gK1xOM9G+H1+157s8H5pduwoElNnJlhp/8TqNkMl/iIhJbDrFIrtsefvETjPSiqWDWVPdxktdxsreZb+/JKzGnvj83v3QTrtlEugdn5/g5A4FOiOkDP91Ew2+NdcdYYxmjfF/0Ubk0o2dL2N4SZR1HB3CKLW4QiyQ1btKYFRlL/XDKlRkWywSIA8QSJ1/rCUb6t2/rfaI/f1i1toQnT33cZOXtDL/1wQ9fTWS+ZJCdvJriJnmSDPSBI/gMricY6Z++jHpL9OcTa9aWILBEIH/MsEimGz3OlwySiC2H+NFcgSUAR/AJXE8w0r8dam8J31tiW1siKR97bybFmiMO+ThaHMYZfjpKyBMZ9izDnuu2/qNpwxKdhDsB9OmDni3Rn7+sX1uiNE5RtbjUXs/w02mcrsywaI5VooAlCliiRleEaBs0SxCdSF/UnJ4tcZ2/tJKUCZYwm/3H2qvkFtrvG7WoNb/sc+2GitQ+w4EYx1wOfnE1Yt/ow3VzOcEbRX6JGFK6X0i19UlzUrZVJC6EfoqlnO0HK0s5hb45Qn44HojduLiNZljmO73F8RMhB3BxrYWQ9QBHx/xqm5hmWPgbbdOMP8qLWBMnLLkBRSz8Tz1i2V+xp2svmhCLfY/DDJ85QkvlKC/irFleaTYRSxo5yZYZFnsFMtsMoz7oT0bF1iynePsn+EsXPDTzpy7hh5k/dU3CsRp3LdjRn7pjQ1mNm3bIRH/pDvZ6NV7tec78oftcuq3G5UUf+kN3QeNX47HdGON+vWlcv8ek3N/CYf2y5kpV732L0vtwF6CYMeK3l9dxht/evhek/wLi14KkJshz8COdZlgW3ho9YuEnmAXpbwC/riXj48s8Mz6+xbZnTv0FIK1VqkE2nDhLu6VDLCqkthDi10S9IP33g30tSARBiEyc4edDd6NH/EYTYxak9LZ1a9sebWZ8Psn3nPrrs7RWKcONaGwqIH6/3TM94jeAGd+CFNWrFNYqab7HflQ62o0hc+pPr19X64/jtXu1+Hw76W6Xiuk5HWtOcufyunR351L62xuXf9GufY+Pz+mq+8JZtp7TueYkXzhfu3Vfw0r/yMLrX7RrX0Li0+l1X0ZKf/vgfwl1+V7w2q07B5T+iYX/xbGloMcn5NzbR5f+hYX/xZ9yOy+/dvOdZ/ap3f/iT3s79cSnCPn3+UHZu97e+33e3MuL0Ez57jeP9iXouP6yYoJNTO0vM5ge54f3L4XSDOeTXxQmKmWG93pA5D7qVKv1BCO9vDAUzKY4BlOE+dc0YR3bi55H9euPqCZYRCvyxxQwX1R312PDCRbRFY2qIj/BSP8+Ju5VTYOq23rXD1C1UC4zLKJZaqrB/P3xEjbND9xE39W4y4gN7DquJxjpxRRm2PU8mAJzDlVT0GuK0p4cxtxUV6w64rM9id2bwyJ+HBJ2dWv8ZT3BSP84cMMHHfwUUI9eJ/NPxU9VQ2SvQnrUD+nZVP0Ng3f4wTBWU8Xr7Jva5VqL7ZB0rzrivYmiXUlT3FTfrtewC+yaKRCfz2v40dQ1ADcISMY6tVfkeZvR/9AP6IWfau/2kJ5NeQ6mPOY3uRJgmtgUIorsuiyVmkMjPWIxjQdTID8NpvRgSt/nklMNVe2jJfH1LMNvoPnJoeDhCeKpB6vQOi2VprUYmDT7KmLZIFJFz/BTPEDr0J4ni9aCkf4pNjL/SYunnfFD+ZGeTWEGU7h1MdLtNeaTkdVpZ7gTXcOGmz6NacUOg1hUOdquIX5f/v8wlQZTdbtuB1U/vjlLxqp7NqiSgLVtqkgGq2elMMPID/GbZkZVESc1x2KKBKZAedNgiv4ewm/netdLe1/vcvu7CVKciQC/xYDpcb7scjXd/j9c4IX2###4520:XlxV32DM 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1190eNqFW1uy5aYOnRJvQ2ccdwAGzGf+8pXK3C+2JBvWwT5dqXStRgi9kAQbt6O1VHM7/9jY9tbxnnI6cY5Nn9iksp3YxY463lSJI0b6pvI+4v/++zuE5v+oP+7fv7WP6k9w5a9/tN/aH/PX//rfx59g/rXB7sJanf/vU30t9cRekWiIRbSoZtHu+b6oExvVwgqL6AVURX6CkV5ULZOqoatqRdVtA1V1V1XbPah8md3HZs6pgptq9WG1TVZLwMp3Vt7u2dNMB1ZJbIXbYUpd2iM9YtHSsdZv/AQjvVhFMKkSJ1XCtyoqKnM5ipc+1Lx0AFWEHrGIFuOsCvITjPSiimBSJXVV8u1gVEVbe3o42V1ma+befCaponKXmIB92wOFt95W2KS9ULiZi75qdf2xpbmTf4kc3kkFoptxVlVRiJF1UL7KmUC21w8M60nMGg6EH/oCNprksbz9EKeSj4t+q9d2QnnFW57XextXHHgor4z39fTXeI1HW8nz8D/c1/geD/M1XlUNX+NbrJ6iFfytZkzRuA8bK9f1vmp+M6emx/WfUkWHcv4do7r+VjFc/25iN+m5t4AesdPbPs5/4ycY6WPc8ohJkzxoUhxosnVNNrsL526pK/a6Kc9koPr/3LUyYB+3C2urthUWyTooKyySChZNtazP8gh2NfgTpzOPn756oS8v9GSJMvq0rYulcOoOuyQUTk18BFgkMUyP8w/xcSR6xLdlwOfITzDS35acfF5Hn+tvTRtzlmi0kXyIWCQLcZZM5h+a6RXRIxbJK/gc+QlGetFUMGl6jD7dv6PbKJ1GH/qo3QqLZHvUcfYBzbdps9c8pfUKi+QBoh9xBZ/jeoKR/rbE5PM2+tx8+zydtedK+uSjGntZXGCRTEWix/kSzb2S1xUWyQv4HPkJRnrRtAw+78E0+hyb3tg1jXYXnxqOXicZqr1gXjmfyn1gBfsQcQGfSrQOeaGs6G9NJbeD/G/8HNcWpCdL6bFpTnbdNDdeOkiZYqw4/IiVGY1+fG80BRutb5yywqJUb8WmwJf5kkKCoo2J+CmA2n9hBxtJsBhd8Js8gskSdrTE9m0Jq0yYUowyaYXvUq+MH1eW+ZJiukuPFRbNklj+BQc1a4rrCUZ6sVSYLOHGlKO+LXFwaZYUE7k0IxbJNijtMt+x5p5bEcSxbRQrUYcVFs08xISHmPAQEyiPYLLEeBDP6Tv5ds77WGADlx3Ed1lgH+J8SbY60m5CfGsGPkd+O8SIB5/P0R9GTfNaU9FEKw2N6rwSYix4O/hkB58otsRTRmbLasgzSL+90JOm4zVBdt8+3aOZmibH+xqxSGKZHudLhkvK6BV+ytJsCeQnGOnFknny6XiLUPy6oArnHI9j3Lf9GKtWWCRzTI/zZd92arPCIcu+pQKMWDSzEDOIE8QMyiMY6cVSaaqCaYyJsM54YokU2WfcapiNdwNikVyBJoD3F3zvDoiJfqCdcrtglO+N3nPtQXqyxD61Ftt3a+E4xbSnjKSH1XhCzfG7jEQO7KhI6Kb1scJyInVWuxUejDhtzIOVvsuOFHCgH4w+FfQIRkV+Ij/SkyWmE6r+tkSOdjq95GiOFb7Pyorocb6UjS3asMLB08br4eBWeEjWaYWH5J2+5BFMlhhPsHv9tkSClLTHI67w45OjTqcZni+a+0gpDHG0pHnhFIR4SLYQU/N6gpF+SM7D7phOuPbbEkFZO0WXsmGFRbKsrJnO3jxf2stdmbzCrpLmfV9vSyyaQUxkiIkMMYHyCCZLjCfc7H/JE6yJxEDh3YBYVu7ONXMjTPOlABdF9Ih9Is0ta474Pidyq/G2nmCkj89hbL8toacTsPou2JX3uWRIo01ZYZUCtTCKGmXEUrZc4wyK+D4Rz02WrC+W3zgGET/3Qdat8HM/ZJfr3ZZSo6X02Nr8sns2udVgH1dFtyCIt418XHnfIxbJGkR/g+hvEP0ltgS3mWm8zSxwK4P0Ij/SkyWmA7z5bl16NHKd5miu5vjCtWq7wrfmcMRokPEaZMweMw1iqI0xI/K90Se+tkZ6ssR5gO8NChcXvAjufcu/1p2/NEnL2ZtvR79nBWq4qkkrXHoevLKkf8O0xwUj/8r8SrJhjYnfOyb+gn/KT1lcJxdXuMRIObM5u8Q10qEkWr3CLqZrPWPtRr/ocEufjwvbKi1+PFZ484R71m8rjPr8sB/LWyzbA3BvWs2I799LOGOUStFyX08B3nmfm67vCou/arJ5+j1GMhTrW/jSBnFifSzzQyz892SOEbtEGVjnwIdAs8TSA2+Wes7N0y2XXDggPxyX3Z28WmKZ3/fyttJf7HnfswPeuIuofOeKWPjnxLfVzxFtX9obMOqDGOMVsawfE/eTsJ97L08XM9Gs92NvGLmCLfeLUYlvv61ZxqtKiTtlNcoj8TZ0TW0VL0M2tV/jkeXGeBkuK8LXuOdLRIyn4dolfY0bPshiPA133uVrvJ2N6iJehqvEfbQfjidFdRX9PVxh1KeujpegOrzcCfTWgJ5IRHnrQk8tjN/DF+4pdl/hpOnxQW/C2hc+9/7XuO8pcoVFXhwXfjIumExx3oJutynw/LpfLziU3WOllwbdbY7eSBGzHK+RhuOyWIhJfY1rRce+xO9Ujhb9OG5FmZfxozfZF5/a7Mn/vJ9c0Ssv71xSWtGLPjWmsqLv5iFjpt2t9MH5SE/GPi9igxhb//htR1/WPkOPucf+5wqBjaQ1zB3xxtrGjaRFLKHQtbnoj0yh2WK6LsStN/TbYklxhffoLy8ES/wQp1OP89+7ul84q3R8Yc3yIbbxeukyjJM+GkJbcPGK5qnt+KLv3dKSHu2P9sL5SC/r9eqQx+gQjP6Q8Tf/ID+Kpm2MpoC/YOQrmLTde6qt7IwwMgscPG/jGoQv3PIhPeLNm8zz0wrfzo2z8sK/1yF6pJXImIgf40meRH4cLHEOlg2cv0GeRX01OCuAvILJGXG4W9Uaz2q2lxT7lJTGcSOm2zhuEMvSlbMs4ifrxKG6pVEUdayveXtB5gJJCVawYUys9inE8J63XiHW9RK59pim/dbx/oU3cBHOLzHV0WVGRTfu1663X2GZ33WyKyz8cLzn0zatxxjlvfcryI/yCrb8SjPo3a/0lWqRdYwretT/N3rUh5yZJ2fi9f9xOdM9Qep4sazJuCZSckTsNnVwX7HEPZcZKiq7XuF7/0FylfU1J9eDnYv4Nj44s4Czcbxy8ZHxqhIUizkYBKO8d75gjPL1RENX05DMMbnL+r/Rv42LfOTsMiWB+J0EApv6TgrclRGr814/3nGDV5fa9cAxZ4+oKz2mbTGoMRD2ftpY4d4gV0rsaVvhnQNFp2RX2EXqgqTBRpzl7XSLmbCj7MMFokRHd3HauxV20V1/79XmFc7cBalmy4q/r4YCSvmwwq4Sv278ssLSZem85o/2Rlws2bMXk2OFxZ5Oi31mew2Fua7kqaKncnplDynEu7LH1/xG+/KHPE+hpjPE2zgnQY7WY8py+JNDubKcmUpxG0tIPznaFR5OW21s+TJ0TUWyyst45pKAuN4Hqnm8QJZ64x+yHAn2tMI7O/e8I11hWe+I+z6u137RF+kF/7DXczodnNUmZ7m3kiT1ztfEfXC73oVLJkD81NfY5r4JUj72GwrqN2DNp1nFxuj9OBy19zwftfe8kkfGBYszQt6PFb/C38ak5zuJiR7lQXq035u+ot8bfYYSWaF/eaO/nG3UVJLMd0myLIpgz5hY6Slu7FtfegedSno81btIGQRxh3wrwKd4wFG+psl7WOGnVMMmULCpIQ5FvsBHHe9TWI1La+FVzCs89JVqhZ+4m8fbj00/y4/yFtg3HuJIMOqD9ORMMznTvJ1jHd+nBT83uQEuBQIcqnFcQd+msM9Ss7EEP+NgLMbiDA0VA/lt4Eyhf9NPQV/5G31Us/NEvt/oyRl22KR9D6436dYr+fj8WPD0/NiMt6w2vj4SoqlGfnitbp8f+gPWzvEjHj8u7e4XkjM/xNY7eTG55HfEGcu44p/UZVzwGz8ZJ1P40aqbf3t5Rb9FPI+6zf7TqucdYmFW3v/oxs+aac9u3MRKN5s9W1JjcVAt0WscfKUuNNI3dohNOqi9jHTOeMM9zPL4jZZVhs6wmcOOu1vEme8GvHZpNR/1QRwifRJbtnp984bYxnJtG6v5Gz7g7yrVyqRMWuFSM915sj0QH57wEVu5jn+AK4VjT0bd7ufNciL9M3/nmlQmORrJhzj4Qr/gquNYYaMVP0UmfVE/XA/xzuvlTN/gIRb+NjIGfwvuuyav/Nn4eBqVO1b0/XBoR4z+er54pTT4Nq74C9Uf9pZvHvkT5bfxQx1tZc+HP33z+DaeFX3ziPZ6vqms4Wu8b34vX9huZps+oW7ra8XHNMRaPv7trNIKy8e/WcnnlTN+VBlFiZMomHicOV9g7IMWgS5BCnXsurQV3jRFsVFdhAUW0ZRYDfDjFcIk6ngDGsLLDeghH6l2Uf8Pm+fWbQ==###4428:XlxV32DM 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117ceNqdW0myJCkOvRKjI7LO0QdgXNauV2l19yZcyAeF4Fd2br69FJOEZie8Gv9KdOnzt0GuEnbauc/fA8ohYQDnn/iff/4+Qsm/1K/j99/ag/qlq/3rv9qH/sv89Z/xt/3Syv622h42Od1tb70nODdTQbXwwcqXJuGim//gAMWeu/ZuPrhDnqd7r8exj4jNHM9xnPtBzef6FVQYq/esTqaVrgMMegObJQxzftcyLhXPfyir8UBzvkJ6CshPUcchYc4vPx9fj2OSZ6lGlKeGVj44QvaSPIhe5/58PaIXdQ7/4pfoSllza0t5aUth2tJPZfE2FYvMR0jxFM7c3Ot0SLhl3FyrednQ0wdbZRDXKUxlsoRpPxhqssN0Ho6tQuVyvigJk3CtT03CVs3LiblL5y/Q4Txv1E3CtJ6pukj4Wl+bKu1Hl5UVKgOXJ9H7xHy9W1lQGbh8ia7hqQx1KIOdygAhcddhPsqQMi099Yxwm3qGS7XXUnm/VJoqTzhPFcel+mOpjv8aWw/GemCTVTl9yBYympLOcYuhfmTSo81dwoNDlO64s8//c1xBB9Q+e8gYpbvCZThivD3rnhjA6n9DP8CGJz7lVdXP8sqnXY8biGD6UyI9mrbDQ5PcS0IMD/uDHR6hqpySCOpADt44Qj9v6MjOSbhMCQ5LtiKuqJSNJMjxlODnJnZ4KPMWg3qvR/i6EfW8Ef3zjaTzRtTnRg7/voHD7XACOCXoh1JKOKh8niSEliVcI0av7toh4SPbhhJqTcJDMhXDuT5vQMDnDWVvtISdNueOHYzZYQUmSBjApCdGiZsh8Qwk8oO7H63db2tssNYmHx185hs4GsaGw2N8tQVde8BsLJapsgCoEnmq5HEypDXM7OyoKKBwunKIuM7IgzKqImZxBmrZ0UcegON0Ks/zmBkSwhTk6nxOnXrQOT90PlCH255PYV6y4m+suJ3fAfPGFb1A0RJ/oJDvqMyWv+E6pguQ6cOZq939JAhmyx9g4rqiHwpO/pKO7Xn+T+a4O/9YN6J8a9+dP6hadue3CjQaGurv8ENV6W95r+TvFbLJ11fTDjLAqb9HNOc5yD4iNH2mDnSeSaf9a2yU92dpPtFJXs3m0+F9DA/z6TOGd5LHN72kHd2qZCQ67R90Ptfn+xO96+kgl3QMWWs6nmPNX3TP83H5+Ojrc/63/FyX6LR+BFf36zuzW5/m8/slugafJTrdP61P9//tX7V72gvR6fwFtH7aw/d806X5RB/IPfW52qqfdG6v3/I90lM+FsIZWFQO5SlPOu+3/A+Q9I/k03XIT/l8yx/n0/m/9Qvnr/Rr+IUg3f9tn8jf5Q/Y+vlTSmz2D7r7/f7dPvfn9wPR6Kf8Sb4xQHiuR+f9ll8Lu/MHndze/pA/fj+jhDuw5EID0xoTCn7/fD2OyT+M+NIk+xspbXn6T84/v6/v++vt6V+5/1ezi7SyP+7vC85SwyoNxhfAOEb6zjC312/7/YpnWAJP/rg9cszzAT6f87uSH6337b+c2ul3ViHu9R/iU7+4/Li+rPSH9I3jUcTWp/7x/cm+V/fH5bGyL1rvm3/Sf1xfK1xfpZyxBYE4dn/qN8f8PCv9uu5rcb+PeMX8hzqe+sHzjQRY2HiN+SunD/s/6UM/rZTP0PyoQcx3aD5EEPMZml+jB4lO86t+0/n5m25pd/7x/2m3v47G7fYf+uV281vUx25+0zKd5qfo8m5+0jKd5g93st1faaSv7q/omHf3l2PMO/mDxvx4Jf8QZ5nA9LGBQrsCYyV7Gox1jEPhkOy5jgRpxg+0Z+YPwqfZeP51p71xfxQ+CdIZh48g+at7fdQ/7u9GgYLnHeMkf+nBZSy8wezqN+KfxyvqmwcoTqLbST8A66jV/KqKl+Ip0ZvC3iePx6PuOf0djJM+83GSL90PyZfnC31ICP9WLcX7PtevCvO4JR0A6wyWr1SVzvFUP3J6UAnze2U88vfOh+h8DnKQ8q1xL/FZn/J8LZxto896DesQlu8R3YAT80U/97cQk6TfpJ+kPyv99MoHST/91E+qz3k+WyHYJ/8r+4hgXvZH/NP+5tPSPzd+59u0f5+Y5+u0P9n3yn5u/XzXA2R/aVTgO/kUhXUQrzfs3L9DO+Ui1DP235zfQ/A7+6b9eT2VZv+jgMXeK8tHD/Dm2X9Yra8Bvyes1qf+18p/lLHjzj84FdvWP42EZzef+iPcvqghSfrF61EYbufZX1nZF/lvbt9kX9Qf5PZH9t8gFqlepha1A9t29AAYn3k9rmZg9Kph3cvq+QPwE9ehtJf4p/hI9vvVL5j2QfLn9AwuPeMDty+i0/orelQxS/2MPBvw1L9dnm/GrxX9jk9v+yL7o/7div7T+e75736NHXEd60UQ+z3EP9kX7xdd82d/lfebiD70OO7WJ/+y0o87vsn+rQL2rZf+f/afeb+M5EPn4/mXn/H9vl95PslndT7qn6/860/y1aoYHLe43xk/V+frVz787icSf+T/eT+S6GSfq/szCv32av5P+YkemrujDz2IEp3ynwxYX/B+K+Vv5L9W8yn/5P3cPj8S99nuXtEpvnC6n3Tan8vnzh+tkfrNlL8nZftuf8qvVvK/5SPvT/Ln/XCSz0o/aD7F75V+Faj4AWMhH4ofq/sj/eXyGX4z7OZT/vyT/KpyZScfis8rOs1f6dd9Pvl+yP5X/N/zZfnZTyq04Y/4599D7vqiJ+l7Cs2n+M3vl/in71O83r2flpQu1cv6eg9SulRvE93P/ITX60Q/VBTrfaIneqfF+gUXHRDzfsP9DsplqV9x0ef98H4H0Z3Sh9QvuejTPnm/5X7aY5zUr7noYNxuflDo31bzw9V/kM8PCh+rrM4P8zHLSn5u2sdKfg7c9v4OhfF9dX/HFf/f/S6iW2hJ6pfd50PM+223/PApGe/X3fLzUer33E+nsG+90v9hP1rqF170mf/zfuPFn4Kt/Yy0JO/sx8z8kfc7L/uc7w55v/R+Wlbsbn6CYnbzh18yO/7bzM9X/A8DrLv68X6fIH9fD2M5dGdyfUP16+r7O+Vn+KDEPp7weMPfs3nz+/NKklIzp7C14aufr6fwSBwDdqD6YSFJOHpsPboiYwv9fPVXO2QJ364ORYusuBcrac9KQ2GMu8AsNCk4JBy0wS6Gw62/8LiwMyp6KDLGB5IrfHvlJyt+sKINPfMJjBUT7W/rPs/cHODzyFTLuZqrKMhho4eEh6qeu+deZw2L81uN4W1j0J50Wv8RAzEH9K2eF4cu8TG/TJ+NF/eR5ytG3jZ8nqd5YDESfUQP9Na3svnTR835Th/5/dYYfWyZ54/eMR/oypNevX7b+IwRKdL+7xiUZgxazW8zxnlPPX5d3vtjTCK6VV6/YwD1KHD97ue3zStHwZhC8knq7SPjzDH4fV8+dsqzXvcDh6QPvuIzyQhwSOOpJzDoVhpP67majaRPfD8+nuTjFeoX1zfiX9FzbDaer8/Hf+v/W1/TtOYY4ZD0lfPLx/P9uD47mM+3a2iSPvP1+HiuH1zfyyVPeTznZzXeetMkfV/tx8cTndsTH8/thZ+X2ws/P7cH9KbH8KZu/0z1GNHhsOnhf7AGjxjDV1hNfRkRqkg4anz+CyCPJ7qdOQHH1PPldFqP6PCKHuEZCK2SWaVAaGZMjzPwkSpzXEGr2X8RsQdsN7c+TZdho5B1E/GXCBzT1dmZ/nB8/wyk3C/7K7xifpefzxOrZcb84T3PyvDQmK5wDNXMChO/3HNcQeGXjskaxyaq6RXw6BxTjpB8XmDU6hUuUzSBMkWGL1HBU1Txj62AMlHS+hUmrS70UJRh0loH8niij8xcS5i0nNNpPaITRn7Tywq8zCo1NdMMmLUeM6AlK2FShQOSl/Awt/mRYwYkhumq6/y9DscUACAWkPCd+WKChazmF6tulfm69GRVV9OfrHE8ItB8B4NH5zjOo+dKPz3ieOYeC3xnvk9Wyv/hq3H+7ZtlnHXX0yqUhLXuEev7WR8u6KSFHGeQ6dd68MbIb31d3aJoIS2FeXXKo1YaiFHCpJUFYpAwhdEyEkQJU5qVnYzvUv4ZZtuLlchYceZTs1xaSKxQBjWWihKGqVU2yvjKACpmbBzfGfXzqP2PtYy+WpFWrTD5Nmvn1TBMviuDPJ7oh8KvJBxfr0gYndaz11fcB79Nva6Gh8kwWA23llGVT76PqnqOL9+nZpXPsJ/FZwBKlt94aMypVUeRcVb4274WY5AwOZTqo5Xw3TDDYhJFoV+iaHst1TOvIq0cTBYJk1YO+1ng+ZvjBb57i8+jmj/W0jRZJa1cYfJtar5R5Jh8F+WVKzrlpRyTr+P0az14Y+T31Ytybq+llLfqK0JjHspx9KiVzWHyxjH9wrbM32ZyTBFY6/mMjuED8PdkI2FOEqaS8i7BOSZfWu+fmbZXL8vZVQo/v0jTi4OplcPNWwmP8+IXzJi8hCnCu5nXcUwRvtVSZfw/Nd7NGQ==###4648:XlxV32DM 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1194eNqFW1uyrSgSnRIPUbg9jh6AinzWX39V1NzbbeZCc23cdaoiTqwr5AvIF5zJnT9zjsvn9+LC9Pm9+zhf/+7a0s4ffAfGd59DfM5nvGa3fn5PJdbP7+y8H2HQa9nPv75P2ascFxs3+eCe3yE/8+fx2en44sJzvid9MZ/Hv82fX+bj+57PqT/k33MIv77DvsApu53ol8uOKV7/flz/f49n+f5t/G1fkb+o/pu363Nkn0b0efw///w153z8cX/a33/5k8ufJaz/+Z9PS/sT/vPf8/fxJ8T4d4wxxfVw8TLDWlt67r5FrZ3zdHGNzl/a5xJFC+eGmOm90Q9Kf6tinZC9sUbOwu8NNyfWqEp/Kt6crk2/7/q9VWv9TXfLobuhJGfmZ10Nps/j2T6sz5t+k5PTxvOZ35t+Lo/ntzzJLi6yGxh/2ePFPlhPtgd2HzCvB74D83rg+8bfs6UPPPlpktPi81NfYLYn5gPzfsP3QN42OOtdgdke+M72wXrgO3A/T9l6T2A+b3e0sPIdTr2Xfgfm9X+zVz+/Vbz/7vwxwszvbf9C/rfvsJ94o3Z6owhvtB7sjcLfMZyuKIvoZ2Can6oUVYUxVAO+WBX3YDW3iVilk9Xp9ZLb1o91i/rQmrbwwdW164fx5Nf583txxzbCOZeL3lLrEK+lHNfqutpGuLnSnlhU8UaVNLYapk7nkhnSmVhlYpWfrMLJalJWoWVitZ7Rwkd3M/PKrKayCPOaR9jnRYRrdR7h4GZ/yeTHeM/pwlva61P4zr+uk8w74ghD+YnsznhTzPzKxwznT3R7GOGYU35ipgd5N7Ou8WHsJb1t0bQm3WLpSTq5esi/r1XX/frN49/m76Q66CUVFZjHQ5XdqDKdqgSHPbo71iWfOyef/604EXsNl58B+dMzRcle5MSdfmeTw23Hv83fXLzimovlku/ItT7FL67uv/BM5pxdEP9V1l1OckgSj/REl+CN/OoH3zD8YHL7tSP3JW7yvU4ir+RPrm0XTorXsl365NPt/frunfjvN3zmK0P6LA/jUPZrp4d8qdPplTxtT7y76aK3RTl5+8nostMiHrLpejC+7SsedNHt2nT97+0Zp5/652mX+CbruC2S78C+SxZ7TKrfSa489cN8/s703uhPkga+ysf2YjznqUq8t/uP99vb/jv315UPxLxmOaUif9/vnd8Ygz/Lz/QYY/1A7w07tS/rx+vN/Hk9GMP+tz5j/MZ/VX+zaN7DeEtblPMkGQJjrB/yVKY/VaE35VBGmPV92z84f9spwcWvSR11RhT3C/f9r+eRz+c3PYubF32jZjiMu3/Jxz7yn1/8GOt+Ps/hMcLsz9/8+9rTHOtPzzCWnrj7E83Le7hTzP4EGSIw+4vqLGZ/0JQ/MMcT2Av4O16IfMB9vnZhqrOY40VT+YHx3WWJt/gOzPEC+gNzvEY6AMzxYnF7HsUPxAvwB779kyTzoA/M8aLrn4/NpjMSL1pPZ6KJxzOlO3NPd2y8wP4BZn8N+YHZH7d7/ZaRv73TcMHsL6Gf6/vL5jupZ5bRj/wd5L/nW3+F9QVmfwP97vWz/gT7G5j9AeYD83mF/sB7LlJBVB9H+4HjH49/m9/Pe5H8w2tfgM8T+y8ez/kpn6cv/0fjJV1Oj8w/Nq6Dc/gkyytIHbmZ1Gh24ksY1yaqo+XwhucsW4XxbapoTAH+U+nFcBphmGJ1dqlBrx/FHI2rwnhsFWAx1WyK3/hW/MrURYugO8uCKBa3Xvc/WS2m+J3fi1+ZjIoLTQJUWIwDit3lmMZYit2wSbHKeEuzuABX/Qg7LZa93/1T2UrKAvfiNVPxqpjp8XjtZZxH9si/+HX70Hgxdn4Ye67cmJ7PdZ3jimxscy08q4WqpN8wshNs4eKabC2i94V79BNVmB688Vf2Q1v4MFu4mK5XJVVj+LTge9dr1q7XptcFyUnDl/HdYLPXH8B3A1OwiLI+RQnc35lOUaZPjR5Wvam4fNbsQ5Paxy0jfPd2bS+UsSdRPYnqjaibEXUZi7qgwZMP7VIIy2k7lhGui7Ttd/VpjO9LIBI1k6j5KepufJQfLzBExV7cUl0V1xFGpPUZkdViRF5gEaUaUcKbu5SpjUiHF4zxwbA6jLvk9tV2uUt/M4OJI3pqqifjoBF+XdoxxOqeitfxhPcl6TwnHW3C3s+SEenufsVZMMtfa1V3KmGPMYw3a0bE9IBXvUdkvGWLmR7kAZbFMJ31afu9BaHKii2Xdcsx7smw3RcL7YvluS9W90xujjz27GcdrXnrZOqOQHUK46x1COquQ/tcTO+N/jm+jfDtue33THUQsKhqOvPHvyQnu7Ml0FmSthG+U2bBwsp05o/pLTmJmnyck6X/osnG0eI6wse2iPfRfgnjGgXHPM8jvLpZ6pmylBHeXNIkZjH1XlFjsLyMYZzY+x+WHk5POrPcEcZpAmZ6kAdYjB2fpym5cWf+TDqClg6S+idNdDTVZ+yztla9tK4Z17hpLItD3EWnfRQdqeKeqkxmi7bf92AhR30boaevhH2EDyei1SRVFuOe2ncfNsZ468A49Xze3Vd6azKxzY1PG6YmZ1llYpWJVTasZhPbwrhA61ZTVti7Z6RZRhhn78ye5hF2PfF3y1M00EciHZUe456IqypMD2cDeRljnJWNTFfJVNWYanmsSmz7OE9DpKgaZBH0b1NZXLK0Ic/KdIjvNpJd1Z1E3Y2o+SnqsY5FxbFuuMHRoJi0Y8t4dtKprGlaRhhB84xE2wijQwMsohZzbMPbXpephZqPO7HaidVuWK0msoS3PA6TZ2XWdMny6ZFHOC+7k92Zwwgjr3NNPDnjz6G4IkEa4zuvEtf9ip1glr/nbe5qvH7h3klzMr5HlmwjDejz9x55cvYjer0zp1gWw1Q9KYzzOJymM2i1p+ghT2WE79LB7hNPTUJgEcVUNUcdn5Z094/D0+dtWYIa44L7Wz/Gj6aRH+G7Xx/vV26rqXqO4+20FHWX+hStt4Itq5laq8DCylY9HITKyarcrG6ryHuI2yoWg/WRQ/uFN7IC6Puq9JymFox7y2mMUUOtZYyxt6PyZ4y9HmnVWN7NrFoz7x/Wt5R2U9+/+Qkt3lVe50x5hO/HHdP6C88OLfjuFas8AsIjE3lXxJjl+cYizxvevfRdi+4rxr1F/rUv6crA2SuHlfbt+ty3m3kPdfxLSgsfiZ6EV0fCGCls8G9YbovfMPprG90W9+rDWSyq2KrLj087ppZ+cScYsY8xxpvYuNmqy73FRkyG3dCaRyxknDa05iUWMj5jpDzm8es8wrlXWWMck/R3Wi7bCOP8elfqU3nInyoyV1knxjAeAsYd+8o6os/f79gomOlBHhOQtud7qTPk0mIs57ovdwGM5+N36x9ef4yb4n4B5+gCztkLNIxH1QW8Z1nq6qdlRI/l4/GtX8jJLQmPF1NMJul2v6u6Td8qB5DK2iomDEe6JutogWvUu7XeG7AYjsiTY/LkuIBFFVPV1en368bGpPMYd1b5ycpUddWNq7r7gZtMRSw9pS4jnOokd0xZFpDxUsOmjsjcaPdwg7eKPXmz+M6A9IUQ0fN+Wp/hjfHpO9dR+EtkqmRM9anqUvex25vju2OTfb5Q9Y8sFm0ceG0cTFl7Gl7aT4zvOs72xhifOb593pDDMuLHGM+Xkg9lhN/0Geg3j/RF7AXm8e3+Pv/WZ3rE7mwC3v77iGzZvjQ4SNSDRAEWVsUEvOP3EYHVm6az6HQxRrq5UPoJjBtHFAFMH0dicqGMMFSLOp7pIfxMzqavwAhHE2VcoNd65SBYTLU+j8jOptqvI3KuC1oXxcuLhfvOMoRn+nl0fyPp5u1vLM5Kr9W4jfCjw+lH9NFqQQ7HuCSp0w/tf3xh0ocxosaUZHEY9xcyfZ+yvL0jO7QXAjIw0+svbsxibeZSYn65blZRpjwZbzTr4yQ8ZjpUtBWXDPrHNV/4hR5j16OY5dcfF/XHUXb8/Xjr6bpt3b7+vpS4A2p/9zbE7X4H92BVjbfY/+3FBEIevPJaND0mDK98yN8GfeG7XWyFXZwVFrj4JTwvAWJeork0UH+UtPXE41c8OkpLGY0/nORwh5/baHzolxoiP49n+/B4MfZhrvjq2xXfnp+toaI9YngPxjBdonVPtO42O3hW7vP+8ngDXajV2afSuELrjklPE49/m3/nAmN8EL6v8Gp6Yh5/O8rHvdtu6ubafl+o31d8/RVqG+Fb9Scrb9LT/f2KTxw2rjbRON0XeUHyhTUaov/AGNEQdnzFJPx9hWflYdzXiYzBGE8M7+Ix1hF//o7off/Jg6V3v1543Ivt4bGuZx7x+8J8U1XR/8DtJGOwjvRaMpIo5rZxj8Zh598H2+vBThU3JihDLMZD3L23VizGBfr+bK3s9rawvLVWZGqhN9F3a8XizurZWtmTiR3ruJGKa3wkJ2vO0hho2usjnGLSOnBJI4xGyJ7zMcI5SyOlxsU8M7gbYlYexlAdz20vev8HH+7zWw==###4608:XlxV32DM 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11e8eNqFW0u25aoNnRJ/i8o4MgBjTDO9tN7K3IMtbRv08HnVuWuXQT+EkASntVb9dpr+L9vNtf4vEtkV9rT5Ebt8bBc2FI4LVzPj//3vP4mO9Mf88X/9x0Yyf7Zw/uu/Nm7tj/vXv/vf8493f3nvd0z1JpRraqxHvXA10azww9owK40fUcwoyjaIkmpdi9JMjddUS6FdUxPVcGGyIa3wnhl74+sKR6EHzKLQJIq2iuuiOL9jqjX+HEkHxSooVmFilTurIKxc3RWrrbPa/O4jG/gkfy+Ao7zfuPl9hbsdbLtl4/FgfQprTU9jiE4yXtOzNskq8HeNC81Y04M8NJliH30x+t8O0N3Y3b5U6616E9E1BuusViUrUfIkShkd4ExrUaIpOztAENbl5uwo5BXec8kXPiiUFQY9YBblmETZvnyRp2bZ3A9po1gZxcqMrOroiycpVrmzypcvFic7MLPvbewaLdAS+63ygmxhhcmk896BOecVRpxLJu+j6ElU1fJoDNUR9zQ94GJyWWHEVWBND/LMcfUcTLmFpky5+7+87SFnP2y5iTdZB2sOxptfYkTSHonvbbmZdrL3tluILbbEyvEAjc123sI7490SU73pxRrTGrM8X1jro/FjPHUyvPocNGI9/jH2dHK0YYv48/g6xPbjPqREpVz3wKbhbarxnvPJfsTjNY4mtxHfolQznRzH127lqacmbdb4YWVGVnY6OfRuTZ1VelkVYdVi3vioPuNIGt+rWGEjtoLGEC190HutdJYVfq12Lunhe5qs6gZVfQtK1dhVjX7fI4saycnGZ9KGvGff2u/AQ+S2+7se/zG/n+9hRa+JqMB6fHtWjTGr4qdwHtcO0h4HmVnbD/ywopFVmMK5PsSOOwYNzIpM9rKk/XBOK1yI7j1at+RW2MoB0GekFT5LOsaAqvGb2M4BWuNE+fyJDWOt3+PSoo/Gr0vy+OdAoFk+0NffnwODcGDM9Nrj4uNixSlwlLVfIIb13XP/dZlxMLybNMZ4YGaVpsCR1oEDU0/ZqEV2R6aTRtL4Hisfu7Hrt8IQjcyaHqzkzBwYgBEYnFKVlKo0qboNqqbqlKrUVSW/IzAkc1Y+RHdOMU3zKxxLJk6e3L2AGh/EOFU+tDWGajvxoav5w3S7mEZjqJ5VDAU9OBiwHg9TAbOp5ppHHyehmypcsYLP30h2H5MtZ+yxwkUKE2fX+NkbPUqs8LNXBLOoeRI1/46h3tgpnHfRaYUxHphZ7dNeCevyDKS80sIr0kZEQcSxYiWNP+kpvCtMxsYVf/0de0mP35XV98nqZSrP0m8H2eWQteK7ZJxd4R0OUUV1jUW0olQtStQyiTrVTHX7nYVVstt0vps1ju8qbi+rqWb6W4QRB4nPjuSp11F1Rwxr7Qo3i4hi8sga83Ekv9tuxo9vi6ia3uMQNDsA8OMg6ntUpoiTKc7JQT4iCDJ8RJASC7ZdWGFLOwdPu8YQLahVBIaowCxqG8szW9YJpSezsW8d6Sqzak/zWLQaVjhbk9hqp72wno/vpznir/HAejy+A9+qnGZSZf+tykm93upTz8KiexFdY7DOSpSsRNXfqxJVY/DX41kVO+XG4Suuc4QJ0gFEibhROFcY44GZ1VRRmH3d6sBUNBtxup3S59QYrJvqwmhczCwqMPgBu5wtb/vEmauZ8bZR4QokpdX44wmmXJ3r8S0iGEe/Gq/11+PZlH5qIW+/e2Ve9crQMtZ46I2dK9zeXtmwqmGK+/Efutnk29i9RsdQY/QoqozXGBENmEWZ8/m09mVMPaTdAdKnYnUqVufEKk2+TF9JLk/N6LTEg4OX4Ua5xjvRnSRufUlXmBr7UqFIo2igDyvuJvgVhmpBxmt68OVeNMYVxl54v8/0IA8wm2q+Y/C/M8ds5sK+SD6t8VBgupcVTauS1qvy5rfSU3gOcp9XmDxbKUuLWONUGFvscEUfmeZB7lxhqNZEFU0Pq9C/LDFWBVjTgzxtMtWcz9vfLe4kvo+IkJ/rlxk/LXHBzGqfVsV99WWfcCXMEOmLeK/GaHofWwgrnAw3vU2M8Rc+bWorvGfyHB63NCoH+RA+31uQGcM4PXCcIz0nTXhNX3+PhsI8fqYHeYDZ2FPFEPLvcBxFFSSAuIvSGKwrzetelSh1EuWYWsRh3fPYzOmfrOQu/NmMPZaUFa7tODh8ty+Mzs+d1muM7vlRefdp/OYHCDwzfvOFcTfVaTeZ31nUG+OENClWpFhNG/ecdpP52k2Y/EYhXtK3AzfjYSu7X9ggair67elCIIrOuBZu6BRELYUD7Xd2GiNfvWuMLsZh1/iNeltb4fhEwa390geYjT3ecqSj/V5XK9ejIN2zZbvCQzZtH1ZtrClcO39nxydIRXT8QlrhftwlPmv4hP/CzsjFoMJoDRx1m1JA8IcXIcPQ+PEimELRe+t9Miv81v9kVvTaewc7mHKqaY7jqyjmDuAm13jN7BxorJHdN+OD2GGD5Vs7jdHxc9KR1BgdQGAW1U2i1t8taEMujqS9YuUVKz+x8pODHWsHQ4uYiHtFJ8nNcFzj6vkiISLcKoxG/UmujaJVctJ6mPlpDNUKOfcLk9DT/IC9kgcYFwfAmt7T4qbRlGPN4xt9vZqQvq1xacxfoJrGYL3RvKqbEmWbRJlqnqP8fjbz5nHPg4xzhYcHGu953qY7jLZ/53HyvOcpoJj4lqXqUdjLCVys5HkKQ7iqhK1KWGAscTDzEgPr76/LcOR38vCGLJ+Mf/suMSxvfluNr/Kw5+icV+O1ffR4NvY2udi+djEUXHiYE7KU0YbzNo0f05EyJSlTjnlcG6sqd9BHt0u02OXcBulGu4TXKpffHFb1+K/5PQ/Iv+gB6/HPyy/BrMpV9USoUtq6c4znTMns50g6m5n0Ybgtqsd/zQ8y/+s7mVkV4Pa83Jq/a3mANb/3EdxoiqsqS8+q6hZSvXfzXSqc8rSHmYfKF2KJWHiNezpGcrFmVzhI+7rXzpz3KdzPW+5GSe9Y48NarrbkACix7qPfuMzyZll3/f3xI7PjEcWknx7/NR/0tTyJ5H7pOaBmecAva78WebBYwJrfs9iTX5dpMeM/heZdPPfIVYoZSQsVhvBBxmOTbtqz6ff3vkkn5fYPel/zd/FcLQ+MCazHD/zySt4hSNAveYHZ2GNd60pep5fD1CyPa/i+0cqTJ4Xbhjq1pBWGaPfFxgIjSACzqNNNWdnW8c74Q26e+OB94s8/4GgON1oJW6jJKlpT7Aprfl/8yz/wA9bj8R2YTXEOW8Tb+hXvolRAJ/G1HbIwXLsdErwj4Y0Fu+Amz0Pi81aWsR7/Nd/3yn7Ehznzir7+ji2gx4Me+isvfdYH98wog4C1vsg6gTMVThFs40VQ9sJi4+HG38Yr++jxX/af7sVbGxfT6Xhn7b2a3bXRYQf1Z6PXFle4H4ty58bcNX6fdViaO954xjLz07g2fptZhZ7GkMdGPkU0fqxBNo+nS1CrHZ7VlssMw9Z+LjPM/Jjp1Ye9AVjze7xF8NH9g5/nzN4M/k2ikcusvx6v7afHQ/7tkXfWBzcc74unebymr8df3tQVGbLC0Lb1tUHfsPt1bepo5ydptd3XsD2LSytsbcsX7omDvB+4fyzQ6/9dyhS+ju3f+Y21oq/Hf82PMl/Tq3L9u6vvUX0H1vIWmjGbamythPZ12yekoYoR0TurtMJgXYSVxhClTKK4IQZYil9PLSOFIq9jEh+4gXvVxkmtE/iAtk62QmRXbT4tcY1WOhBhhS1xOZgvJ77tO/PX/DSGfNd1zWp+rI7fUpPQV3gXebNnrOWpFOXSkPXX4wsFueYQfZS9IA/wl7zAvFjjhbWl8PvFhCF/i3z0E54TB9dWmKIrnCOxCTQOFDjdq86ucBHV9/aFWbVg2BSsShiiRTfuOqcKMRoOVEwqX4P4DRaLoL7Dil21NLJ2YmU9/ms+6Gt+XlYdWPPDqgFrepCHJlPEaQvSZ9khLlqVsM7MLq2/H4p5gAuq8V/zN2Vski0C4yRa09fjv+Q5lDE39X1TiwF+WIyktphTiwHMxr7ab9tjbF12tNvYfRP1/MpwwjQL7yR+fH1H/EJ82D7Gf81PH/OPGOtoTP29gB7Zc4W9dSKfPVb4IH5GZasNK4xzr/8/reTB4vT4GlcY8gJre2Gxn/NA8UNQA9br8Sy2Op+0cwKzM4yPrG1u63gaYhLSPRs6L9IpPrXHfZ4m+SFmz9bOy+/n8V/zjyubWtCLlNKI9XjwA2ZVaIynu13H037K1ucV/kA6Cauv75vhrAyiWWpuNf5rflGqJqVqUqpqfsCaHkxRJlOMP0xNX53Wt4OE33OhApRnXuo7Olh4MacxymdrQv1F7/1d4zz++XmwYFblai8WqFJ0/9oWf11MXO+4Pe735b2e/JbAFvkpocKQrtAsXTHOj9/7wehW309i7XumEOX3YBMOVPnCp3LlpvFb4fB7hVPusXudMf1Gwsq14tf3Tk0e1xU5c5z8lJIrTvRFNdb0vuijQtL6Z+IKLFu+ddJYy6Px+/SDb7Uw31n89LNKf4u9QfP/23orrOl90bc0e6teb2Btb1SwwFre9n9RjuzG###4664:XlxV32DM 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11c0eNqNm1uS7CgOQLfEG3FnHbMAHvZn/81XR+99sCU5jVJ2dkVH1D3NSxJCCEMFazZz/IAp+/zZYOV//vkrlez/mD/p779shPnbwH/+Z2Pe/7j//Hf+3v5U/7e33vg6zD6ORkCNbTHx6Msbs2scaPA+h7uzFcIwu4L9M/N4zNw+G1Pv7ZnleFzOLOV3JC/MLjSW8n7XX+V7as/yobHDNHa8jF2FsYv72xdfuekuVJ+Nzq6MxaGyGKoKU0vusDL3x6ZilvUvU4r282f1K8Fs6id5pX7c/ld9NGVcTLkJU+ZpyuxrjjZos+JoVp7K2/xPeJFa/6l9ovayv2mS/c5SHh7PCa9Ooj0zmiLdTdGyMEWapki+cte76NoKL5DlDVZTyPIEqyqyPwt6f5cpRPskyplR1TxVDayqNbqqHvbTUXxZY9G06rh37cH00+HYga11Gsv+nvrvQpUuVJHlUh5mVBVugTnuXai6nYE5+MqrZSpzCjNXST5dcjijMQufij2Vr7A1cuWTA2xneStuaOxgbGe76MoiPBtTyCO5w57OdgXlkSzlkf2ndqy2YwnYrDHrVwrK980ovyxne8Q5HDoB9if1zWbz6N8uafLu1H7KA9p4w2zkVC58JrvMyfbXEpbRzE+/9scejE2bqWfXzW7n77mIrMa1nCPvGVrSmFVlRlHqTZRYixAlTFGm17EVDISzzzhw6GxC0XizGOB7D6Axb6ebCU1j3r6ZUdS2iCoDX5yixo+ojkQNJJoz0Wo83RAdxsekcYp7JtX7IioIUYl/1UdV+l2VNnQHYN8axp1djrFHXCPkW4J5qAouapzNvt0ZRRmLKE2PsSzKTqL4uFGe5azKZMWedWbR5kL3b7yDc3duZlWF+Vd9VHVbHGjovs4RiH2dt4fdRq9xGBiRLPhle5jtzT2iMf+qj6Lui6hNd5BPsERRW8H8JEBIGl+btiFRBHN/zKcoUwDzJ5Moc/kKUaw7tyY4fKRgyDf53ILGqGfIi5DLme0ZNFiJHfDsEM7yELvRuADWd3vFhNWfU7lXA5Rr0wTEUjTuEGiCmtO4cv++Uqqzyr/HQis5d43jwBU+TB4qC3kl+4bsTC0aNxNxuZbeNZb2lPauBTeAKU/SmPVl/rI3RawMtWn2ahAwSzY1a/Jw+7mTh7fyAf1MGdDb7PQ2Wy53k3tj9NPd4HD+zbhzGoM9f5kN/PmPkt2mcQKPbmkcLpps0QzgPCXpp9mOCUBzjHMRRBsTug/Oj4lx07hCOc1hh87gAfc6k4PG3WB9aPncLasfDd0lFk0eydF3DLWQVG4k75F+aDwPqJg22NNMX9xJH4goX6BMytJym/Efd6mpucaNMiewzeP8YMc+Y5CS8yE5zV3r/D23kLN9xEw1ANqPeT9OtgqPQofOmYOc9s0Yh6spTdMnmrNbkwuOFw2OfzEcR+6pV8vn/BbKTIGWt+RB+m7T8Dgu2mN4bP+kDzPLv/fk7v6aM/Un9Hni2TJpzPrn2Bb7Z5Kfx2t7AZVpfp2l8EvlqbmB/oDjZfCbxp3sM3bfNOb13DOVi/7nJndqU3dc75KPXPL8H4P8R7Ccb+mfX/Hmgav1VWWSf8/ofzulTHV6xummfsN4QXaUzPNvO6VakkneaU7khvEjGfRTaa+v+Sk4H864oLG0h4xP0p8ly/UiWfrbk/+xvzuTLJ4t+qB5w+2q69w6JjUjGq+xofSg+xpxe6SToRmYqIn5kiztLfnLXoIT1R9QVXYGj212jKSxj7ifVOheYwtnOJ55cweNpT0le4PpySddW7nS9t4sstxPry9KFM/lfndLv5K23wxT8NgL2Wn7Cc/XVDur+8U8JaGcuC7l+rmOFLCN+/ri/YLL/Uy29f0Cxw9Tbm2/mKc09ANwSdsPPp+NYNfiPY8fpkZavObxK7SgxePrCAela/GU86NI8VjGKy4HwLgp440BOzBv2DoeeNd4kQAdIxsbtfX8+YIIQ1uPn3QS01FZfqWjgOmo9MerPWA6+lS+mXs66u6HnyK/QFp7Hn6yr8caQe/A3ZR5AO6+kptBjjFvGhdrEs5WxiOZRe0Cr2ZiS8nzU3knbeNwG66ubt7qS3amJ2GdpPUnebrMeRDvRWdpL6kv8+Fub/ULHz4Ee8BP9LKc+xtUziztyfpK+172pHLmJ3sxozcdt29weVN49Kabr0aMfYG+8LRNY1fcOXoCtK7kbg3FJrTeTdsktF3KoyiPoryZ1RrMV/9GWJP4M9ukH80GM5dX6o/LmaU+sv5T+S5Xi/laTZgLx0hf3sRqofpyfmT9p/bxR//Sfl/yLbEpLN6UpDeZ05uSr9y6it6NWa2xQbeLNMK3ZbnsT5YnESumteCt/Zd8wvsSr03Rn+RKsWZudCpf3kD6P5UX0l8ye6Ms5/4ubxb2bSJ2SPsasVrk/CQRW5if7MWM3hIXb3HSW+L0Fjf9pU4b4DXVwM9YORv87ETnSMlsvWjrMnon6XaanQJtaDyzsoGRGvMeyVIeyYXGn0FzsUaBL29a1moW3ihnS3In73xqn8XssP6y/lN7Ka9kS/1Jfa+dzUDQ5oPLAdadkJl3SlnO/V07pQHVnjdvU+11s0d4s1cW3mxFuV120nT/Pj6M/imfU+ICNtFlHt7oWrtrzDdmfGvAPFP5cL9BY/5VH0XNd1H7rn/K564biertTjuW3TS+hoJVFOZL1Pu9I8Aiin2/68l05ckHXQ+ua8wHFQi4sCXzLQMYb18ZVvbGh+X+nvhXfVS1LNdau35ZuF8O4hYHSRZVk3xdY+0+acyijHl2WkQDoQqsqjzVR1WWK9pmn+499+1+RcsvlPKVKq48j4/nsm7RN40/x0dP95h4Gz2Ph+N+sc38qz6qsl7h7u+qXNdaEe85E4kumb+UTituGlu6k/dlFS2ZVRXmX/VRleUKt8f3O/wOeK/JF+V8ZSuZh/pc4a7Mt9vLFS4sV7jdv4uykSgtDtpnXNGYh/5csa7MoixXrLBcsbYHq3DTQVeem9nwBYP1RWMemiOGZFaNGUVZrlCbfxdlZ1EAhy6FRBF8DQ1CFBCiwE2UYpYJKu9bAPsKX+9vZr0z592FXx5c/KM+imIXUfK7KOwrvWDXA7BryddQtNtIvkS970bFLRNU3t12zi1uPnFQuoETIpknhHcDyTzhy25R/CJKfhelkiiVHuBYGlryNTQIUUCIco/2JSwT9ONpSDW23uc+Aj5LkswTksGCxhxymVGUuIjS3kXpJEofHJ1xaMk8NJhVFGYWhRlFSfeXgA3e3/4cLyLu0ZVXhGSeEAsua8z9yfJ2ufXKcnxZH1XJy/tN+REI3HG/XV3kr9JWbKcuvLGnBzqfJM6We35Yyaqy/Gu8h/G70cf7LCvkp/HqNetrf9dGuQSre746d189y+emgTYiDtke7wu+OOfR8YCJIVryLWIYja8nfcQoark5qLcPz6jYAStsixWCwbu+z5M/ZFlfMr+rM0HnT6q89bfxmGV9zleZUdV6U9XZh3w0Dnwt04wlh0HzV3q4+bnOwQOPrP/UPlL7p/6qKI+inBlVueejM3rrqnBTe/kyvgTmY6PkPo/S52wUXzVm0Wb+at8Z803JLM+Sj5Z7Phos6C/k+RLM8eXvoMswek0sedALsg7DarzTJW+2NWkM9MikDZ1d6fzxod55mJr/TfkwK6MpxmKKqkdYNkXgdwwR7+mcwRfUklm1aft4V5U52E7p27AaDzJq3OumMau2mdreeMBPzhpfpoK7qe75ev56/ktew007vUQumHLNtYazKLkCnOGi5QIa+4gWtDOuvHGD7DUGurrrJalcDiXOBZtA4wER7oymuJ8X7AgPprhuKlqh2318JmzbpvG5u25HSkCvPgXH3dARyFuNj2+E+GgOb2El89c6O2PBG7sZWzRmfZhPU9T7eSW4rv/hEl9od9jpczUuqLmLeo17wdgSoQeNC7+8LrhwJDvo2G/Eh21fTA5fTPdvvJkeXhlW9qa7f1POq4QZTWkXU256LGJTbmTKVhz94dDuNM4RTQckiuRGprOlF40Dma7HDhqzasH09MYevng1Bayme6qPpnKLqR52MDbVPCZUevGNr4nL7jVm1Xe7ZY1Z9UypleRk0Ls2+jzyxBC70ZhVPTYUjdlUzGgKv5iivpuikCl4867kJZJ58y7kJZIdvdzwEb1EsqeF1unlkeRLNYqNN15VBWGKh/poivt5OH092hc71CArbuRoweLfxkgO9IkvNXwzLblEvEAvpkaN8wi084DVOHp8y55MShp/LlFS1JgfszCjKeLiFeE9r5nuRx90MY+ZHDXmPCbR1wvJnMewl0jeDHFsTmOe1WZafmV45wirlzHz1Mf7nzXVtJgqvWfDG5mq01PQGQSjxoYWRI46x9LpjIEmfOKdUz/B2SJnsaCSWVVl/lUfTZEXU5h3r7H0qoxVL/TlTjLHhqn4A1P220bVuNIaz6NuKheMCWAw8X9kWJkPAr/Ko2n16+BQYTGVe/ca/lPCxqYB+psjwZZM04rBC07BAS9c5qzhdwrJhUyz2eY13uLx+//SJ5zr###4572:XlxV32DM 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11c4eNqNm0GW7CgORbcExhjxax29ADAwrFmP6tTemwjpOY1Cjuya5LkFAegBQsj8MaIrecz/eqzh9Rdccn3/bVSSxdHVcud///37yCX/cX/CP3/7SO7P7s+//utjGn+2v/4z//Y/tP0TKJSD/Onmf5tz+fV3b35/M7lkMbnW311Fd5hcq3/x4fr7r+azsWlJTHtiT9QthunB0bhzIjrvUoB1uf49S1UWqfp3qXaRqos0zb1bGppjZslOat7iJNIlXw6LYfru8mkxTCHK7is7zatU4N/qs1R1ShUh1TiUVGlKlUIJ8aXHHCptb6mydwc3tUWL21xdVnmj7biXg1G+0Zbu5eCn/vH7SKO8ystD/affo32W4ryvmhGUFGFKEULB0NCVb9w00eYtvqQhJRUpqYR5KG0OJWEomdRQvA//BP+aGO/395xnV3g0woNKvbMuL1Ie29Z5O5fjW33NlWyuZJdf/dFe76zHi3Iw1Opze9/VAqP8oNzv5WCUR8rFqv+zEKhZ/c0fbYP9VbXq782xu6RcrfpaX10feiUqZNXvs9ZbT5erZY/uT9fn1dTnaqJrNemTw+9zNW3BhbJL78EVVkdap+mpLG6ZexsYvcweucKeVbWnuUp7e6vV5Mjtb1T4MIvRsbH8e6wej/4eyk/Hq+mpPLuP3aJXZzLtU+09tR+olG9cZXdpezHbWXaD1vtarQ8csFtU+dWelGe1G6EX7D0f9MDqHWq3Yz7we/CHvbQyr9axrFZ9ePvw9n05FOyVTdTe8obZM/llAkdjJSrftIymKGucqIdy8FWurHWf1i5qgq/ZcGo2nPZ9ajaFtT26PnzDlku3+sP4UF/rgdWc1NmA+rDnULsB9Z9+r/UjfZao3ap/r+trvuZDrQ+thx6/rv9ejdUtq7Ho1bi9V+OMJmPe9/deEc9+s5Zbfyivau91pc5QeyVKeXM7B9i5BIt1f0/96/40l4f+B3w5cX+ar5OJD6pPFl/W5kXA4p8QT53E8vvrJHfrSQ6+IgFVjvZ+QlDmj/nCbqZ1N+v5GJ+R0brb1fxqPcvd91U/V9suq+2oOgSNMwSNoVQ6Ik/FvKD4V9PM5Hx4sS7PdPBdK3myuGQKvJH88a09sK4/NdrvzKZs92i67sqUY5pyzF0jPx0ST7UZGPGJQafFgep7FvfK8Y7mGV69VW/D5oPce/k88e4dnx2I7xR3WplNDYup0b5uwlQvC3ybUQJvOCKTxbQ+6LD4lGvrCKlZnJKTY4L70wzTAmX/ld1vvEoFhlRglmqfUvlLq+I+LlnhtcRnLBrlPuQr39I7h5xuXuF2i+d+e3Oq4bD4oCC39W3chzfk9ynybT/LvW2O+d1/HXy6zsj9LV+a02DxRuO9Uo/IsauT9n3eeCWT51O18hX0k8N25zCPFY65e+dTkaf3TIP9pIyvpBjv/ff2xjmNzDHzeLrrb3YSu2veHdcfgf2rbh/2Hu44LEb/ezuqpd8p9tI8gSyOeQs8T6yn5ua4PuzRrO3V/WN8LhZvzc81nsTrRfNcJ+/5aXFPFmP+St2Dtb5Oz+MZbqsWYz2UsHWLT2k/Jl4fNfN6Tc53a73o/nV9Xa71+Fi/aj08MfTW+wnuwUl/mjEesN5Pw/G6j64ma790pHZkXvR+SW7IPuqNo7x1v6A8uL1b+yFK/7vjAETPB9EmN3JJcSk9plMf7KY53tD75eqfjmStZ/RfXN2t9Qx9hsuntR7h/6IL/e4fW2X7UU5TUWs9OfKNf9c526j8M7Kp86+5HjC/Xo6DROy/XeT1o8ejx6/r6/Wsx8PHTbzFU9uR1WmT58n8ukhS5HRDTbIl2KUV3oG3rcJDR9c4qTUHpPZC6jaLqQ+sx6P59AeHqHNOrPGi/KS0WXzQ0axytIdyMEt5LFImW8ogQ4UpLmM1p2WXIwg6vBfvw/HdB4t0lOiwWao/sB6P5st0YlP1eFHe3CoVGFLpcrR3SUl3KdMSL262lG3GWexwoqQGM38conhYfCRm2jkxrTnT+Y7aXWBHo3mXA/V84Di8HKSOTVJ8es+OY07uV6aV560i/j/lcDBglpIWKcN3KQ+RsssXlepjsHiTW8FI+2ExQu0y+OzXfDiJjVqoFiO2wNnxwY1NvKZAM6QhnxWvUtEq7VN9ljIvG7wpKes70eFDOassffkCmJDqPuXLn2JfaZMdHTj17sXbeN6imQ/saZy3eJMD+Uz8RVKzHs8HE58ccbRqsicO6OZl8xvvrg3LHpQ/8SGngi5He+71fe/GPBllmYyqJqO8J+N1S1LGVjGuVRZf8+sseq9UNRlJJqN7jtbmPX63OIr4M2YdJqvxaC4ynpRatfgSh0QcNV6UZ2czxNblV3sQm+5i17sTKcX+Bgon4hG4ZfavzY1ocZUh58qBmeYoAeY+bK7iFHLtZDE28SYpjidOjgM2zQjowCzF8g20VDtrAykQoxbPps9FsJkspleJxTUj1o7V5oK7UGLTNV+mkTKVlKl0N7Xdt1h69HfwZ/1s8nEjB/5YczaLu+Ml7du5BM67XDzg32YkFC2uEvgetVWb9/adD/rG2h7NP1uqnZY9KK/EDyM0YwvqcrT3s0XbbTL6Mhn1aTLgLzDzczfKIcFvLTS/roN8K5NgRybjkMmAfyuO29Psxb/FYLMej2YfeXF4GY/mKuImL5Ol+BKPWCxtD8pPt4oNhti6HO1dk0H3yRhLUOXsfGZyeZOXOJxAgv8jDq01n+IUCu2nxXAKIUVvMYKfUHeyuDjeJ1vbs8WnRyIH/ducaa8W44IMfkt1ukUqbx8dkCpjdcA/UqoWI1QIc3NaDNOJUyEffObQ5DZ0mizS+CjSaBbTi1ulAEMKMEvhly3s7VAcP8VQug/yXo271hzdwf9f0gCffHICP3GeRnOW9NHhgre4U3kHLilvJsfMHx+rYy+ty1vm9CnKNZOka8C6PYfPQcIs5bZEf+MhbeHKJplwPvi9fNcU066MjkgdZBXM9XJYvIm0lKQ9xbo/zTlypgzSXqaSMpWUVKSkEtb26Pq/9cdSLt9mCtkBDTYoyaOuXe7WeC+mGRtyXti6xZdvCluzuMmGK1mSvYqx4brjjxWaMbVgNnVfTM3fTcX7tSq+p0seWjPSBKHy0DTDtKOupoLhW2oU0zTDNFKmkjKV7qYueT36xddUx6lD+JbTcdeavSz4FGx2OcunEkmZKz5kQ+zDmxxCWVLcmrHA5+nqv5Vj1jVjA+lytIdyMEu55PXSeHory1I2kRK+o8gq0QzfsaXNWwzfQdXmLcmLKhmq5st0WRVP5buzGVLocrR3SbmsuiVvl8f3w35zHHfjcD84XfHB8B1dPqRo/vEdNqcWZGPxYawZvqXlYDI23JzibvHPiR1+nsWcS96t/BL37CIFQkJyR7AYV+S9xm4xTG/B5iPyEDviFMVVTB8+mAzTk1ulAEMKMEux5M2yf0rV4MdzO4279xmOO9cM71OCzfA+SZawZnifNDaTSyruvmU04zjd3XfOIuJTeacQLMbDF12O9lAOZrGXvBiN744/itTwTu31hs5geCcc35rhnWp94Ms09haP7L5zplVKXT6XRrAYUulytHdJSXcp16xXf8h6zeiPPzsmkTS9t3Tw6bTYk/yjh3oMkyXb1HPKFu/EzxJqpvKNfZZnGYpL7pLoy81ifCYFsxRr1ms8ZL1EilOkOFyS94RsuuZOkkAONgfJRrWAb1UrTz/OL/rkwY5mmObdaioYpoLZ1DXrFe0N1CWndI5T3vbsO8/mOSye9TUvvz893+ETfyr64IPidufueIOmV7LUaG8qxHF4K92qnxqHIWkvu1U/8T8+mquKHyvq+pCuySrR9VnKNWcVnhw/Xgr0tIq5uVVMMMQEX2KREkv4FHHQvq6v+9f1c90kNjqDWV8ccIjyjljVxykcaxlW/cT/5GGcvpj1r5cLEFvVZ7GXnFQ57JeR2KKBqjx4T/LIUv4Bg+JK5Z2ma9OTWxwlTXeMGizGlqvE4aJmPNoAv01pS86opO+ON4opqfHQM9Vgsgx9rzYj45iHzRj6Kf09svvgxVTwb/VZiiVnRPEp7YsAbo+nPMbhC5i89fhgbKlOp7cYWwx8yg2uBp73UCWWnqeXxaMxzwiELMZ4S2zlLg4Rv245M38jwuR9sBoPtjS2HFwAWOuj6+vx6Po8GUvWiZ79mWP/Udsq9nCr2GCIDb5eMokY2O+br93iy1+Eelo848cmOexuMQ6PlvoqJikxhbV9un7ykQNx+FdVX/en67PYa17qtJ0A3gzjfDvlOXQhzn5qdvJGuCbOiWs+qnzToWhylm+HlI5g8ZZH488UfKEDR8fPZn4rxyM3MEux5q3a95fiTu5eQZ5L78hmahbTfeXZ04yX4eeQ92aK535MfCrJ8xvFl2m0mg6+TKW7qUveKuVHfyff7JIk/Ld0yJsBMhnPjvAsXTOeIely/OMHR0e/8ynz1+Rzla4f5aLRK17IreP1mR//zbirWvUhDnIkun53ievnnKzxoJwyv3XX9fV4dH2ejDXzlZ4mw41D4v1VbDxs1yxi/w+WJodm###4752:XlxV32DM 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1278eNqNm0ua3agOgLfEG5FeRy/AGBj27I7y9d6bgyTbqOSTm0nlLzBIQgjxKOMNNDP/ZTP6mP+CSbC4mfj5eULqGnvj/een89lqPOutdkrW2YyUPz+SgcUOYsXfw7nq27R+dgNDY0NyMI8c1vfVQNfaCwb5bLlr9aU8sv6///6TSsu/zC//+x8bwfwKR/jrfzbm8cv99ff82X9l99tnfwwD4WPKqaxbTRQoi4FUE+yhpg83D0njWaksUWtuGsMcw8/Pg1SRHKzB38N3boCmlAxgxpPRFLCZIgpTpGmKdJvCsSkaqn6a4jUeUOOHa4WqcTG9LtPRqEquZJqT6ktm1dhrJLOqzKhqmaoGUtVBEarCVBX80abLrCYv0dMavUAOxE0fsCQyOdr1gTUoumTZnuQEebXfhs48YYC8QMrD5c7koHGC1LRybo/LmdFUx2aqLEx1+N/ezkhxDIvCTBfEaFBw9lnDv0djnWSsRMZhP5FcyDi3n+ws+5PMynko39nszFNIlkt9LuOCMDYIY4tybv8yNjyNXbcp6N78stjPFCkQly1DKfnD0cSkcYXTf9jWaDUOxi7VDq9zN35N9RbXevGDQ3Me/dn3b5yNCzhFHUY7cDRk7njyn+qjqc7NVP67qSqZ6rBoGm+i1xjINDUH0JhNU3zIGndjl01S81XjAG5xzKjSDyZVk8Hfv/FpyFSC2ZTMaKq2TeEmTHWuKez8MUP3Gu9oGiYOUJb9oXavcbarrzklmtWY64fRksaDpmqNZ9P4tJBxCp5O4zTnjlZe5oyi1bg8Weon61dKEJofan3vXaclqmv1a3ED/dZiQiXq8+DMn6tfWR8Hq2+DVcVg9TVYwR8JMB7afK7GI2VHZz1B4x4xbh0GUxHJnhabox4qz9XGYdzC+my8w+zGZu6V4vJMRrX6kdq/5BP1E8l/67fXl/rL+mDQuK6OqNXPEcsLOIuL3l6fB+ugwZL1L2cE4YzEb/bichzs8Qhitssg5mcQ81sQW6rXiCnWHOKusStY/5wm0TjP1O3JS5RupiiRRMk26vF0qrg+rRa9Yq6NOJXNgUsOhIpLT1mi2Laqjz4XE41le2/tz3E41fZtOJZKUJomjweTnyzba1TOLNvj/pjRVHaaKvGojfI2Ra+Peb0ucbn2MXMJjbnzmQIdgjdhmGX9Cvr3xWT3LGfm8rkLaM9yZlnODDOi4e8D+l37If9uPNJf1vcxBOw3e01eIPv4ObW0+rJ9WT/ESKGpeE1++b2sj4PtnoPdrRjsugbb+uM2PizPnMl9wUUBhZEcCyoDrIzgS1hAY3T6Psbd2BXk4GP/sv7b940H66X//MLcX36Rl8uZ3+Rl/iEPDQ4zDoZ/xMtskxiMMIPUY955ChIhBsxX5r5HY/arAb5rzKIdxgeNuT9mFDU81vFUZZCIU9T4Ce19WWcGVszboK2mZl5nNHalU+h2mIKL77m80S75rT6zrM/lzKhKfFq9nEIVN1Vxt9Ub+M0hPnmQxlyfGbtKj1XI9tfdpiNvnZ3ZvXGXv3ECtwsDQhghfJv5+eaNxLI99mbmV/mo/QBYPvdQSavPoaiZpNa/l4JUtPpv/bP8aOz8cFHbsn72ZahpB/5EV+RA4YLG1yogTHUKU8ryMXeVz3JmLu+CuVzKJ+s3yprGTAC1+miK59lXjl1PxFi0SqM4EzLaHfotps5MaQsMzH+qj6KUhyhp5BdRpidgjMMNamuNwj+mx5KP0nC0KP2UzO2FZ3raj2d62l7CLRs4moCxJcYVsTtgmJVcPo2suYAD8sbW6Mz9MaOodRMVdKt5+nRG6oHpKPrCINEkc9dz82A1ZlGYUZTPycTBJxNRZtJ2+I8s9mM4TD75SGyGXDIUbiUk12hoa4RHSpI5ua104M/MR1acDDPbmbt+rgiqoYNz2JnLh7HpWc7M7Ts6p+H2mfl7Zv6e+U7W7SafbJ/l4XIpH+vD7V9HdDDch7tNQ6t/AG42WsVzLNkfczG2aPK6MvynvWK81fTl+nwYI+3F33s6RJL25vIh9JXyvY13AORs0cFOQH85sDsj/U/Wd2ZuhT/2srFr8sj23uqzfaS+sj1ZPzZcTGPALbe055/qnxbls3xIJ8bzT/WlfNJfpL7S3zAatC0ayBhqP6dv7rO1jtRbN3GNJjPQKeobu+uUFDlSNJDttYLaSeb23pjbZ/bU/o/2yJv4NmTaaFk7FfyF5Lf2vIhmlm45pD7XbAAcHWmPazYBziapzzUbwYVv33P52/eyfZbvmp0goimkuEUj2KMx8xXNiGV7VzSEPRqwPFc0JZb6XNEYdHtc0Rx0e16rgWif5blWEyEf63OtRkL/CClr9pL+LeubT/6y6vPF4F5f+qesj7O1b7NVJl+2r7V7bkBqZW8lbSgW+Ji23hvFjkyxw+VQ8LIavz9hX+uALgzWyt8/SRHe/EJGhoDHkZJle2/tV4MbPykfc6ZY+sYcG0+yXjR4zDnMCIsb3jlJlv3xaMx964kXHChfL3jHL1naQ7KUR7IcL8n32pxUednbTmEvK9ZuI9YatjezF9E6i9zBi+jC/nAfXGL70p/utZGig/DHOzfZZ5sTuRPzj/Y4VxC5B8vjr4PU3R5e5H5SPy9yRy+iL7fH38v2T5G7SvmcyH2ZcbaPbbbLTYMza7a7mamXjta81irkey3d2QNaf/C1IeBop4jXgIfpeXknXd/9YO6Pb2IFO2rfVntqfFvXwlcGu8lnImZCmTKjEZx5ls+tXNT0eWNuj+0Rc/JaexwNEkUDzhXOcniNea0tdHkumb2/xqzy23gyS3kl32slZ9q7Ppd30ton7XF5N9BsFva+x4eixcv3XqzdPJ7X7ASenbs/XrP7yiV2/e5cQUQLkZs4ET1PkZucYu2/5aFoASJaiNzkp34iWojchNu7ooVo/xS5iZTPidyEeUWLYZ4vDmLR30fxp41NA2EdrPSRrMbGZ7y0o0c5kg+TOh494Cs7yfMnnehm942nWFHjRuf3zKiq3VQ9dFXZihkCRp3o6NCVvExw8+nE84z4lQOpLplFd/CdM+yqMrOqzKiq21St+jn9nczS8k6j6If1GvuRGwZcPzQuNIqdAuYPJtEt+Kax51sXYlTFb6qc+hUuO2jnfU8Ly8rjtEPjhO/1PoeUVuMCKHobJLpkHgXaV77xyaZ5Y9jZmt00b+WXqczTVGEzVfvu4GwqHuU0KEwL9j6fKPrAc1/BI2d66NKaxkBecNgOGl8OT28kJbOqzKhq3FTtuoPfu0l0cPaC88SbJ8nN4KHuqB3DneBgM+72ThRd8u3QuyrMt4M/VUmbKkO/sGBVrrBEowQjZI1npFyi8xstycHg9XfzLzw3kEvkhs99JPPzC54wzNOrxv9Tzs8/mNEU27vlZL478LUYUUQehhYjwScdGSSPeYDkZFA1znPemPNAyZdqZled+VLVPFXd7mYO83L9aAZd6lfc5uPd75xD+P5GMtdnxq6e74Jb1QMov0BOueLdHD++NnV7OdTnf3By4xYQ6FmC5Oxxi2cNSi5Z9ie50BTpVmfW/KSXSFLeDjvL+mwpZrTU82oo/XhTeF1v07Mdg3d93Rx0nW2Hxic9BoBog8ZmFLzuNE7laA683xnOaszyzKl033KN7eoIju9XR6wKXxUVcEVjviqqVF8yXx0xoyjndv394+rIr/vvcr82SQZXjtgcvTLpUeN8HQfhSiT5JOaEWTJvoELEDao3EZ+kRXw/m63Dds/iNT4CX77iM27JI+AFms3Nro2KYF8cvSY5T5UNX0VMeyjMCf60h6VDyc1+/HQoziRRZRrdAMehsbSHZAsJ9Rn0FEmyTfhXEfQ0SdqbNzCJ3gtLnr50PFnqe+1KiGV/cS4QT0ZvbI+J4ax7uxRPdFLFr6gSxnyK/ZIPEyls6vx4lfUQpT9FMfn7/fxpOh7e0YOzXHrR+DDoZdMe6KWC2Us+s+AW5flm0/fy9mYTH9IUg2/Za2zksM5qzA9x7HU3uDO3x/wRZa4ymyjj7alApacAHk9O8UnR5wFG1/gotTzzEcncHjOKYjdfedkxPlIZXKr4j4UA47Nk3uzOpPOF0XfemIPuoHj/xgZc1piDNDOq6jZV/VsWignsoFW1NZwGwdSucciYQPNjccmZVDsaJtCS7/dzvX3jE3bmvcKfynkuPPcWh9ne47n09jIs0b35MM/gY0Fnrs+MXYXtEVp/e/qXKO7hpyckfJxEM15yISvW1pPG15NU6EFjjjjMKOr+Xm58D1Zzh0Ohnt+etK7x9VjI7KIw368en6I8d0x+JF2UbI6GV2OONn/VUS5jNXYF06hMq41kbo8ZRfnsWDKJMmQWb+1KbebEmekxPSXnVAOXwhx90vi+KcA/V5Xf32ePWM639GEq9fy+z43D81a/FNhfkbSSvzG3J7nQTU0ctapM8nH/18NZWjmkPpJnhFr+0XJyGkt9JLP+YCBo9uTUglna83pCTyztyd8zS33bdR5VsyYPf8+MzrT9rWrrb4GHRYf9yp3uECXfD4iQsavyvCQCmQXZsh5wfDY7ni4hTMMrSzL0KOf6haUrS28K/q1Xw0P9gy4teuXnJxUHhi8t2mm0cjZkMOc2ELP98bw0KaUkrbyRPAXoUkWw7E+y1Fe2L/X9wWT9mRRUrb37uU4zmj5czn8ULe3BnIilPa8cmsuFfHcOjfLJ8eLvuf8f403lLL9k9jZZzu1xudSP5blz+vK44v0PME/5RA==###4852:XlxV32DM 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\ No newline at end of file Index: Top_Modul_VHDL_summary.html =================================================================== --- Top_Modul_VHDL_summary.html (nonexistent) +++ Top_Modul_VHDL_summary.html (revision 2) @@ -0,0 +1,78 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Top_Modul_VHDL Project Status
Project File:Prj_12_DDR2.xiseParser Errors:
Module Name:Top_Modul_VHDLImplementation State:New
Target Device:xc3s700a-4fg484
  • Errors:
 
Product Version:ISE 13.1
  • Warnings:
 
Design Goal:Balanced
  • Routing Results:
 + 
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: 
  • Final Timing Score:
  
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Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
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+ + +
Secondary Reports [-]
Report NameStatusGenerated
+ + +
Date Generated: 08/20/2011 - 10:35:35
+ \ No newline at end of file Index: _xmsgs =================================================================== --- _xmsgs (nonexistent) +++ _xmsgs (revision 2)
_xmsgs Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: DDR2_Write_VHDL.vhd =================================================================== --- DDR2_Write_VHDL.vhd (nonexistent) +++ DDR2_Write_VHDL.vhd (revision 2) @@ -0,0 +1,211 @@ +--------------------------------------------------------------------- +-- File : DDR2_Write_VHDL.vhd +-- Projekt : Prj_12_DDR2 +-- Zweck : DDR2-Write-Funktion +-- Datum : 19.08.2011 +-- Version : 2.0 +-- Plattform : XILINX Spartan-3A +-- FPGA : XC3S700A-FGG484 +-- Sprache : VHDL +-- ISE : ISE-Design-Suite V:13.1 +-- Autor : UB +-- Mail : Becker_U(at)gmx.de +--------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + + -------------------------------------------- + -- Beschreibung : + -- + -- Die State-Machine schreibt + -- einen 64Bit Wert ins RAM + -- in 4 aufeinander folgenden 16bit-Zellen + -- + -- die Adresse wird + -- von der übergeordneten CONTROL-Unit + -- gehandelt + -- + -- solange die Write-Funktion läuft, + -- ist WRITE_BUSY=1 + -------------------------------------------- + +entity DDR2_Write_VHDL is + + -------------------------------------------- + -- Port Deklerationen + -------------------------------------------- + port ( + reset_in : in std_logic; + clk_in : in std_logic; + clk90_in : in std_logic; + w_command_register : out std_logic_vector(2 downto 0); + w_cmd_ack : in std_logic; + w_burst_done : out std_logic; + write_en : in std_logic; + write_busy : out std_logic; + input_data : out std_logic_vector(31 downto 0); + write_data : in std_logic_vector(63 downto 0) + ); + +end DDR2_Write_VHDL; + +architecture Verhalten of DDR2_Write_VHDL is + + -------------------------------------------- + -- Interne Signale + -------------------------------------------- + + constant CLK_ANZ : integer := 2; -- warte 3 Clockzyklen (2 bis 0 = 3) + signal v_counter : natural range 0 to CLK_ANZ := CLK_ANZ; + + type STATE_WA_TYPE is ( + WA_1_NOP, + WA_2_WRITE_CMD, + WA_3_WAIT_4_ACK1, + WA_4_WAIT_3_CLK, + WA_5_BURST_HI, + WA_6_BURST_OK, + WA_7_WAIT_4_ACK0 + ); + signal STATE_WA : STATE_WA_TYPE := WA_1_NOP; + + type STATE_WB_TYPE is ( + WB_1_NOP, + WB_2_DATA_LSB, + WB_3_T1, + WB_4_T2, + WB_5_DATA_MSB + ); + signal STATE_WB : STATE_WB_TYPE := WB_1_NOP; + +begin + + ----------------------------------------- + -- State-Machine WA : (Clock-0 Lo-Flanke) + -- 1. wartet auf das WRITE_EN=1 von der DDR2_Control + -- 2. sendet das WRITE-Kommando an das RAM + -- 3. wartet auf das ACK=1 vom RAM + -- 4. wartet 3 Clockzyklen + -- (solange dauert das schreiben von 64Bit) + -- 5. legt das BURST_DONE-Signal für 2 Clockzyklen an + -- 6. wartet auf das ACK=0 vom RAM + -- 7. Sprung zu Punkt 1 + ----------------------------------------- + P_Write_WA : process(clk_in,reset_in) + begin + if reset_in = '1' then + -- reset button ist gedrueckt + STATE_WA <= WA_1_NOP; + w_command_register <= "000"; -- NOP + w_burst_done <= '0'; + elsif falling_edge(clk_in) then + case STATE_WA is + when WA_1_NOP => + -- warte auf write enable signal + w_command_register <= "000"; -- NOP + v_counter <= CLK_ANZ; + w_burst_done <= '0'; + if write_en = '1' then + STATE_WA <= WA_2_WRITE_CMD; + end if; + when WA_2_WRITE_CMD => + -- CMD anlegen + w_command_register <= "100"; -- WRITE-CMD + STATE_WA <= WA_3_WAIT_4_ACK1; + when WA_3_WAIT_4_ACK1 => + -- warten auf ACK=1 vom RAM + if w_cmd_ack = '1' then + STATE_WA <= WA_4_WAIT_3_CLK; + end if; + when WA_4_WAIT_3_CLK => + -- warte 3 Clockzyklen + if v_counter = 0 then + -- burst_done auf HI + w_burst_done <= '1'; + STATE_WA <= WA_5_BURST_HI; + else + w_burst_done <= '0'; + v_counter <= v_counter - 1; + end if; + when WA_5_BURST_HI => + -- NOP anlegen + w_command_register <= "000"; -- NOP + STATE_WA <= WA_6_BURST_OK; + when WA_6_BURST_OK => + -- burst_done auf Lo + w_burst_done <= '0'; + STATE_WA <= WA_7_WAIT_4_ACK0; + when WA_7_WAIT_4_ACK0 => + -- warten auf ACK=0 vom RAM + if w_cmd_ack = '0' then + STATE_WA <= WA_1_NOP; + end if; + when others => + NULL; + end case; + end if; + end process P_Write_WA; + + ----------------------------------------- + -- State-Machine WB : (Clock-90 Hi-Flanke) + -- 1. wartet bis State-Machine-WA das + -- WRITE-Kommando gesendet hat + -- 2. legt die LSB-Daten (32Bit) für das RAM an + -- 3. wartet auf das ACK=1 vom RAM + -- 4. wartet nochmal 2 Clockzyklen (WICHTIG !!) + -- 5. legt die MSB-Daten (32Bit) für das RAM an + -- 6. wartet bis State-Machine-WA das + -- BURST_DONE-Signal angelegt hat + -- 7. Sprung zu Punkt 1 + ----------------------------------------- + P_Write_WB : process(clk90_in,reset_in) + begin + if reset_in = '1' then + -- reset button ist gedrueckt + STATE_WB <= WB_1_NOP; + input_data <= (others => '0'); + elsif rising_edge(clk90_in) then + case STATE_WB is + when WB_1_NOP => + -- warte bis write start + input_data <= (others => '0'); + if STATE_WA = WA_2_WRITE_CMD then + STATE_WB <= WB_2_DATA_LSB; + end if; + when WB_2_DATA_LSB => + -- Daten (LSB) anlegen + -- und warten auf ACK + input_data <= write_data(31 downto 0); + if w_cmd_ack = '1' then + STATE_WB <= WB_3_T1; + end if; + when WB_3_T1 => + input_data <= write_data(31 downto 0); + STATE_WB <= WB_4_T2; + when WB_4_T2 => + input_data <= write_data(31 downto 0); + STATE_WB <= WB_5_DATA_MSB; + when WB_5_DATA_MSB => + -- Daten (MSB) anlegen + -- und warten bis Write fertig + input_data <= write_data(63 downto 32); + if STATE_WA = WA_5_BURST_HI then + STATE_WB <= WB_1_NOP; + end if; + when others => + NULL; + end case; + end if; + end process P_Write_WB; + + ----------------------------------------- + -- Write-Busy erzeugen : + -- solange der Write-Prozess im Gange + -- ist WRITE_BUSY = 1 + ----------------------------------------- + write_busy <= '0' when STATE_WA=WA_1_NOP else '1'; + +end Verhalten; + Index: iseconfig/Top_Modul_VHDL.xreport =================================================================== --- iseconfig/Top_Modul_VHDL.xreport (nonexistent) +++ iseconfig/Top_Modul_VHDL.xreport (revision 2) @@ -0,0 +1,217 @@ + + +
+ 2011-08-20T10:35:35 + Top_Modul_VHDL + 2011-08-20T10:30:12 + F:/Data_Temp_Ordner/Xilinx/Projekte/Test_Prj_VHDL/Prj_12_DDR2/Prj_12_DDR2/iseconfig/Top_Modul_VHDL.xreport + F:/Data_Temp_Ordner/Xilinx/Projekte/Test_Prj_VHDL/Prj_12_DDR2/Prj_12_DDR2\ + 2011-08-19T13:02:28 + false +
+ + + + + + + + + + + + + + + + + + + + + + + + Index: iseconfig/Prj_12_DDR2.projectmgr =================================================================== --- iseconfig/Prj_12_DDR2.projectmgr (nonexistent) +++ iseconfig/Prj_12_DDR2.projectmgr (revision 2) @@ -0,0 +1,92 @@ + + + + + + + + + 2 + /Top_Modul_VHDL - Verhalten F:|Data_Temp_Ordner|Xilinx|Projekte|Test_Prj_VHDL|Prj_12_DDR2|Prj_12_DDR2|Top_Modul_VHDL.vhd/INST_DDR2_RAM_CORE - DDR2_Ram_Core - arc_mem_interface_top + /Top_Modul_VHDL - Verhalten F:|Data_Temp_Ordner|Xilinx|Projekte|Test_Prj_VHDL|Prj_12_DDR2|Prj_12_DDR2|Top_Modul_VHDL.vhd/INST_DDR2_RAM_CORE - DDR2_Ram_Core - arc_mem_interface_top/infrastructure_top0 - DDR2_Ram_Core_infrastructure_top - arc + /Top_Modul_VHDL - Verhalten F:|Data_Temp_Ordner|Xilinx|Projekte|Test_Prj_VHDL|Prj_12_DDR2|Prj_12_DDR2|Top_Modul_VHDL.vhd/INST_DDR2_RAM_CORE - DDR2_Ram_Core - arc_mem_interface_top/top_00 - DDR2_Ram_Core_top_0 - arc + + + Prj_12_DDR2 + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000238000000020000000000000000000000000200000064ffffffff000000810000000300000002000002380000000100000003000000000000000100000003 + true + Prj_12_DDR2 + + + + 1 + Design Utilities + + + + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000001bd000000010000000100000000000000000000000064ffffffff000000810000000000000001000001bd0000000100000000 + false + + + + + 1 + + + 0 + 0 + 000000ff00000000000000010000000000000000010000000000000000000000000000000000000392000000040101000100000000000000000000000064ffffffff000000810000000000000004000000e60000000100000000000000240000000100000000000000660000000100000000000002220000000100000000 + false + Buttons_VHDL.vhd + + + + 1 + work + + + 0 + 0 + 000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000 + false + work + + + + 1 + Design Utilities + Implement Design + Synthesize - XST + User Constraints + + + + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000001bd000000010000000100000000000000000000000064ffffffff000000810000000000000001000001bd0000000100000000 + false + + + 000000ff00000000000000020000015d0000011c01000000050100000002 + Implementation + + + 1 + + + Edit Constraints (Text) + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000001bd000000010000000100000000000000000000000064ffffffff000000810000000000000001000001bd0000000100000000 + false + Edit Constraints (Text) + + Index: iseconfig =================================================================== --- iseconfig (nonexistent) +++ iseconfig (revision 2)
iseconfig Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: Prj12_Impact.ipf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: Prj12_Impact.ipf =================================================================== --- Prj12_Impact.ipf (nonexistent) +++ Prj12_Impact.ipf (revision 2)
Prj12_Impact.ipf Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: webtalk.log =================================================================== --- webtalk.log (nonexistent) +++ webtalk.log (revision 2) @@ -0,0 +1,9 @@ +Release 13.1 - WebTalk (O.40d) +Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. + +WebTalk Summary +---------------- +INFO:WebTalk:3 - WebTalk is disabled. + +INFO:WebTalk:9 - WebTalk Install setting is OFF. +INFO:WebTalk:6 - WebTalk User setting is ON. Index: UB_Y-Led_UCF.ucf =================================================================== --- UB_Y-Led_UCF.ucf (nonexistent) +++ UB_Y-Led_UCF.ucf (revision 2) @@ -0,0 +1,29 @@ +######################################### +# File : UB_Y-LED_UCF.ucf +# Autor : UB +# +# Constraint-File fuer die Gelbe LED +# (AWAKE) auf dem Spartan-3A Board +# +# +# LED leuchtet bei HI +# +# unbenutzte Netze per '#' deaktivieren +# +######################################### + +# um die LED zu nutzen, muss der Suspend-Mode +# ausgeschaltet werden + +CONFIG ENABLE_SUSPEND = NO ; +NET "LED_YELLOW_OUT" LOC = "AB15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; + + +######################################### +# Port-Zuweisungen +######################################### +# +# +# LED_YELLOW_OUT : out std_logic; +# +######################################### \ No newline at end of file Index: UB_Taster_BUS_UCF.ucf =================================================================== --- UB_Taster_BUS_UCF.ucf (nonexistent) +++ UB_Taster_BUS_UCF.ucf (revision 2) @@ -0,0 +1,28 @@ +######################################### +# File : UB_Taster_BUS_UCF.ucf +# Autor : UB +# +# Constraint-File fuer die 4 Buttons +# auf dem Spartan-3A Board +# +# als 4bit BUS +# +# Signal ist bei gedruecktem Taster = Hi +# +# unbenutzte Netze per '#' deaktivieren +# +######################################### + +NET "BTN_IN<0>" LOC = "T16" | IOSTANDARD = LVCMOS33 | PULLDOWN ; +NET "BTN_IN<1>" LOC = "T14" | IOSTANDARD = LVCMOS33 | PULLDOWN ; +NET "BTN_IN<2>" LOC = "T15" | IOSTANDARD = LVCMOS33 | PULLDOWN ; +NET "BTN_IN<3>" LOC = "U15" | IOSTANDARD = LVCMOS33 | PULLDOWN ; + +######################################### +# Port-Zuweisungen +######################################### +# +# +# BTN_IN : in std_logic_vector(3 downto 0); +# +######################################### \ No newline at end of file Index: UB_Led_BUS_UCF.ucf =================================================================== --- UB_Led_BUS_UCF.ucf (nonexistent) +++ UB_Led_BUS_UCF.ucf (revision 2) @@ -0,0 +1,33 @@ +######################################### +# File : UB_LED_BUS_UCF.ucf +# Autor : UB +# +# Constraint-File fuer die 8 LEDs +# auf dem Spartan-3A Board +# +# als 8bit BUS +# +# LED leuchtet bei HI +# +# unbenutzte Netze per '#' deaktivieren +# +######################################### + + +NET "LED_OUT<7>" LOC = "W21" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "LED_OUT<6>" LOC = "Y22" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "LED_OUT<5>" LOC = "V20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "LED_OUT<4>" LOC = "V19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "LED_OUT<3>" LOC = "U19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "LED_OUT<2>" LOC = "U20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "LED_OUT<1>" LOC = "T19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; +NET "LED_OUT<0>" LOC = "R20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; + +######################################### +# Port-Zuweisungen +######################################### +# +# +# LED_OUT : out std_logic_vector(7 downto 0); +# +######################################### \ No newline at end of file Index: UB_Schalter_BUS_UCF.ucf =================================================================== --- UB_Schalter_BUS_UCF.ucf (nonexistent) +++ UB_Schalter_BUS_UCF.ucf (revision 2) @@ -0,0 +1,29 @@ +######################################### +# File : UB_Schalter_UCF.ucf +# Autor : UB +# +# Constraint-File fuer die 4 Schalter +# auf dem Spartan-3A Board +# +# als 4bit BUS +# +# Signal ist Hi oder Lo je nach Position +# +# unbenutzte Netze per '#' deaktivieren +# +######################################### + +NET "SW_IN<0>" LOC = "V8" | IOSTANDARD = LVCMOS33 ; +NET "SW_IN<1>" LOC = "U10"| IOSTANDARD = LVCMOS33 ; +NET "SW_IN<2>" LOC = "U8" | IOSTANDARD = LVCMOS33 ; +NET "SW_IN<3>" LOC = "T9" | IOSTANDARD = LVCMOS33 ; + + +######################################### +# Port-Zuweisungen +######################################### +# +# +# SW_IN : in std_logic_vector(3 downto 0); +# +######################################### \ No newline at end of file

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