URL
https://opencores.org/ocsvn/dds_synthesizer/dds_synthesizer/trunk
Subversion Repositories dds_synthesizer
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- This comparison shows the changes necessary to convert path
/dds_synthesizer/trunk
- from Rev 5 to Rev 8
- ↔ Reverse comparison
Rev 5 → Rev 8
/vhdl/dds_synthesizer.vhd
65,15 → 65,15
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architecture dds_synthesizer_arch of dds_synthesizer is |
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signal ftw_accu : std_logic_vector(ftw_width-1 downto 0); |
signal phase : std_logic_vector(PHASE_WIDTH-1 downto 0); |
signal lut_in : std_logic_vector(PHASE_WIDTH-3 downto 0); |
signal lut_out : std_logic_vector(AMPL_WIDTH-1 downto 0); |
signal lut_out_delay : std_logic_vector(AMPL_WIDTH-1 downto 0); |
signal lut_out_inv_delay : std_logic_vector(AMPL_WIDTH-1 downto 0); |
signal quadrant_2_or_4 : std_logic; |
signal quadrant_3_or_4 : std_logic; |
signal quadrant_3_or_4_delay : std_logic; |
signal ftw_accu : std_logic_vector(ftw_width-1 downto 0); |
signal phase : std_logic_vector(PHASE_WIDTH-1 downto 0); |
signal lut_in : std_logic_vector(PHASE_WIDTH-3 downto 0); |
signal lut_out : std_logic_vector(AMPL_WIDTH-1 downto 0); |
signal lut_out_delay : std_logic_vector(AMPL_WIDTH-1 downto 0); |
signal lut_out_inv_delay : std_logic_vector(AMPL_WIDTH-1 downto 0); |
signal quadrant_2_or_4 : std_logic; |
signal quadrant_3_or_4 : std_logic; |
signal quadrant_3_or_4_delay : std_logic; |
signal quadrant_3_or_4_2delay : std_logic; |
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begin |
82,7 → 82,7
quadrant_3_or_4 <= phase(PHASE_WIDTH-1); |
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lut_in <= phase(PHASE_WIDTH-3 downto 0) when quadrant_2_or_4 = '0' else conv_std_logic_vector(2**(PHASE_WIDTH-2)-conv_integer(phase(PHASE_WIDTH-3 downto 0)), PHASE_WIDTH-2); |
ampl_o <= lut_out_delay when quadrant_3_or_4_2delay = '0' else lut_out_inv_delay; |
ampl_o <= lut_out_delay when quadrant_3_or_4_2delay = '0' else lut_out_inv_delay; |
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process (clk_i, rst_i) |
begin |
89,9 → 89,14
if rst_i = '1' then |
ftw_accu <= (others => '0'); |
phase <= (others => '0'); |
lut_out <= (others => '0'); |
lut_out_delay <= (others => '0'); |
lut_out_inv_delay <= (others => '0'); |
quadrant_3_or_4_delay <= '0'; |
quadrant_3_or_4_2delay <= '0'; |
elsif clk_i'event and clk_i = '1' then |
ftw_accu <= conv_std_logic_vector(conv_integer(ftw_accu) + conv_integer(ftw_i), ftw_width); |
phase <= conv_std_logic_vector(conv_integer(ftw_accu(ftw_width-1 downto ftw_width-PHASE_WIDTH)) + conv_integer(phase_i), PHASE_WIDTH); |
ftw_accu <= ftw_accu + ftw_i; |
phase <= ftw_accu(ftw_width-1 downto ftw_width-PHASE_WIDTH) + phase_i; |
if quadrant_2_or_4 = '1' and phase(PHASE_WIDTH - 3 downto 0) = conv_std_logic_vector (0, PHASE_WIDTH - 2) then |
lut_out <= conv_std_logic_vector(2**(AMPL_WIDTH - 1) - 1, AMPL_WIDTH); |
else |