URL
https://opencores.org/ocsvn/debouncer_vhdl/debouncer_vhdl/trunk
Subversion Repositories debouncer_vhdl
Compare Revisions
- This comparison shows the changes necessary to convert path
/debouncer_vhdl
- from Rev 8 to Rev 9
- ↔ Reverse comparison
Rev 8 → Rev 9
/trunk/bench/debounce_vhdl_bench.gise
108,19 → 108,13
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputChanged"/> |
<status xil_pn:value="OutputChanged"/> |
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/> |
<outfile xil_pn:name="debounce_atlys_top.lso"/> |
<outfile xil_pn:name="debounce_atlys_top.ngc"/> |
<outfile xil_pn:name="debounce_atlys_top.ngr"/> |
<outfile xil_pn:name="debounce_atlys_top.prj"/> |
<outfile xil_pn:name="debounce_atlys_top.stx"/> |
<status xil_pn:value="OutputRemoved"/> |
<outfile xil_pn:name="debounce_atlys_top.syr"/> |
<outfile xil_pn:name="debounce_atlys_top.xst"/> |
<outfile xil_pn:name="debounce_atlys_top_xst.xrpt"/> |
<outfile xil_pn:name="webtalk_pn.xml"/> |
<outfile xil_pn:name="xst"/> |
</transform> |
<transform xil_pn:end_ts="1313109084" xil_pn:in_ck="-7617925053698354275" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="3041675604745481488" xil_pn:start_ts="1313109084"> |
<status xil_pn:value="SuccessfullyRun"/> |
128,60 → 122,49
</transform> |
<transform xil_pn:end_ts="1313461517" xil_pn:in_ck="1959554578214568806" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7550009954124855948" xil_pn:start_ts="1313461512"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_ngo"/> |
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/> |
<outfile xil_pn:name="debounce_atlys_top.bld"/> |
<outfile xil_pn:name="debounce_atlys_top.ngd"/> |
<outfile xil_pn:name="debounce_atlys_top_ngdbuild.xrpt"/> |
<status xil_pn:value="NotReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputRemoved"/> |
<status xil_pn:value="OutputRemoved"/> |
</transform> |
<transform xil_pn:end_ts="1313461537" xil_pn:in_ck="1959554578214568807" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-1658770934691434356" xil_pn:start_ts="1313461517"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> |
<outfile xil_pn:name="debounce_atlys_top.pcf"/> |
<outfile xil_pn:name="debounce_atlys_top_map.map"/> |
<outfile xil_pn:name="debounce_atlys_top_map.mrp"/> |
<outfile xil_pn:name="debounce_atlys_top_map.ncd"/> |
<outfile xil_pn:name="debounce_atlys_top_map.ngm"/> |
<outfile xil_pn:name="debounce_atlys_top_map.psr"/> |
<outfile xil_pn:name="debounce_atlys_top_map.xrpt"/> |
<outfile xil_pn:name="debounce_atlys_top_summary.xml"/> |
<outfile xil_pn:name="debounce_atlys_top_usage.xml"/> |
<status xil_pn:value="NotReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputRemoved"/> |
<status xil_pn:value="OutputRemoved"/> |
</transform> |
<transform xil_pn:end_ts="1313461555" xil_pn:in_ck="-6999964895445881344" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="7846039340612803429" xil_pn:start_ts="1313461537"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="WarningsGenerated"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> |
<outfile xil_pn:name="debounce_atlys_top.ncd"/> |
<outfile xil_pn:name="debounce_atlys_top.pad"/> |
<outfile xil_pn:name="debounce_atlys_top.par"/> |
<outfile xil_pn:name="debounce_atlys_top.ptwx"/> |
<outfile xil_pn:name="debounce_atlys_top.unroutes"/> |
<outfile xil_pn:name="debounce_atlys_top.xpi"/> |
<outfile xil_pn:name="debounce_atlys_top_pad.csv"/> |
<outfile xil_pn:name="debounce_atlys_top_pad.txt"/> |
<outfile xil_pn:name="debounce_atlys_top_par.xrpt"/> |
<status xil_pn:value="NotReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputRemoved"/> |
<status xil_pn:value="OutputRemoved"/> |
</transform> |
<transform xil_pn:end_ts="1313461578" xil_pn:in_ck="-1280993813019831418" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="7135157351517842893" xil_pn:start_ts="1313461562"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/> |
<outfile xil_pn:name="debounce_atlys_top.bgn"/> |
<outfile xil_pn:name="debounce_atlys_top.bit"/> |
<outfile xil_pn:name="debounce_atlys_top.drc"/> |
<outfile xil_pn:name="debounce_atlys_top.ut"/> |
<outfile xil_pn:name="usage_statistics_webtalk.html"/> |
<outfile xil_pn:name="webtalk.log"/> |
<outfile xil_pn:name="webtalk_pn.xml"/> |
<status xil_pn:value="NotReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputRemoved"/> |
<status xil_pn:value="OutputRemoved"/> |
</transform> |
<transform xil_pn:end_ts="1313461555" xil_pn:in_ck="1959554578214568675" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1313461548"> |
<status xil_pn:value="SuccessfullyRun"/> |
<status xil_pn:value="ReadyToRun"/> |
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> |
<outfile xil_pn:name="debounce_atlys_top.twr"/> |
<outfile xil_pn:name="debounce_atlys_top.twx"/> |
<status xil_pn:value="NotReadyToRun"/> |
<status xil_pn:value="OutOfDateForInputs"/> |
<status xil_pn:value="OutOfDateForPredecessor"/> |
<status xil_pn:value="OutOfDateForOutputs"/> |
<status xil_pn:value="InputRemoved"/> |
<status xil_pn:value="OutputRemoved"/> |
</transform> |
</transforms> |
|
/trunk/bench/grp_debouncer.vhd
90,8 → 90,8
-- |
-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com |
-- |
-- Copyright (C) 2011 Authors |
-- -------------------------- |
-- Copyright (C) 2011 Jonny Doin |
-- ----------------------------- |
-- |
-- This source file may be used and distributed without restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains the original copyright notice and the associated |
106,7 → 106,7
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download |
-- it from http://www.opencores.org/lgpl.shtml |
-- it from http://www.gnu.org/licenses/lgpl.txt |
-- |
------------------------------ REVISION HISTORY ----------------------------------------------------------------------- |
-- |
/trunk/bench/debounce_atlys_top_summary.html
2,7 → 2,7
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> |
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> |
<TD ALIGN=CENTER COLSPAN='4'><B>debounce_atlys_top Project Status (08/15/2011 - 23:26:18)</B></TD></TR> |
<TD ALIGN=CENTER COLSPAN='4'><B>debounce_atlys_top Project Status</B></TD></TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> |
<TD>debounce_vhdl_bench.xise</TD> |
13,19 → 13,18
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> |
<TD>debounce_atlys_top</TD> |
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> |
<TD>Programming File Generated</TD> |
<TD>Synthesized</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> |
<TD>xc6slx45-2csg324</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> |
<TD> |
No Errors</TD> |
<TD> </TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.1</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> |
<TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/*.xmsgs?&DataKey=Warning'>3 Warnings (3 new)</A></TD> |
<TD> </TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> |
32,7 → 31,7
<TD>Balanced</TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD> |
<TD> |
<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.unroutes'>All Signals Completely Routed</A></TD> |
All Signals Completely Routed</TD> |
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD> |
43,12 → 42,9
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> |
<TD> |
<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_envsettings.html'> |
System Settings</A> |
</TD> |
<TD> </TD> |
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> |
<TD>0 <A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD> |
<TD>0 </TD> |
</TR> |
</TABLE> |
|
367,7 → 363,7
</TR> |
<TR ALIGN=LEFT> |
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD> |
<A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.unroutes'>All Signals Completely Routed</A></TD> |
All Signals Completely Routed</TD> |
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD> |
<TD COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD> |
</TR> |
385,22 → 381,20
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> |
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:25:02 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/xst.xmsgs?&DataKey=Warning'>2 Warnings (2 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.bld'>Translation Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:25:16 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:25:36 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/map.xmsgs?&DataKey=Info'>9 Infos (9 new)</A></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:25:47 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/par.xmsgs?&DataKey=Warning'>1 Warning (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/par.xmsgs?&DataKey=Info'>4 Infos (4 new)</A></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:25:02 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:25:36 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:25:47 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:25:54 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\_xmsgs/trce.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:26:11 2011</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Mon Aug 15 23:25:54 2011</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR> |
</TABLE> |
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> |
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> |
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\debounce_atlys_top_map.psr'>Physical Synthesis Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Mon Aug 15 23:25:35 2011</TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Mon Aug 15 23:26:12 2011</TD></TR> |
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/dropbox/Dropbox/VHDL_training/OpenCores/debouncer_vhdl/debouncer_vhdl/trunk/bench\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Mon Aug 15 23:26:18 2011</TD></TR> |
</TABLE> |
|
|
<br><center><b>Date Generated:</b> 08/15/2011 - 23:26:18</center> |
<br><center><b>Date Generated:</b> 08/30/2011 - 11:26:47</center> |
</BODY></HTML> |
/trunk/bench/debounce_vhdl_bench.xise
280,8 → 280,8
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="false" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> |
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testbench" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testbench/Inst_debounce_atlys_top/Inst_sw_debouncer" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.grp_debouncer" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="work.testbench" xil_pn:valueState="non-default"/> |
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="work.testbench" xil_pn:valueState="non-default"/> |
299,7 → 299,7
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> |
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.grp_debouncer" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.testbench" xil_pn:valueState="default"/> |
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.testbench" xil_pn:valueState="default"/> |
/trunk/rtl/readme.txt
26,13 → 26,17
|
VHDL simulation was done in ISIM, after Place & Route, with default constraints, for the slowest Spartan-6 device. |
|
|
SILICON VERIFICATION |
-------------------- |
|
Design verification in silicon was done in a Digilent Atlys board, and the verification project can be found at the \trunk\syn directory, with all the required files to replicate the verification tests, including pinlock constraints for the Atlys board. |
|
LICENSING |
--------- |
|
This work is licensed as a LGPL work. If you find this licensing too restrictive for hardware, or it is not adequate for you, please get in touch with me and we can arrange a more suitable open source hardware licensing. |
|
|
If you have any questions or usage issues with this core, please open a thread in OpenCores forum, and I will be pleased to answer. |
|
If you find a bug or a design fault in the models, or if you have an issue that you like to be addressed, please open a bug/issue in the OpenCores bugtracker for this project, at |
/trunk/rtl/grp_debouncer.vhd
90,8 → 90,8
-- |
-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gmail.com |
-- |
-- Copyright (C) 2011 Authors |
-- -------------------------- |
-- Copyright (C) 2011 Jonny Doin |
-- ----------------------------- |
-- |
-- This source file may be used and distributed without restriction provided that this copyright statement is not |
-- removed from the file and that any derivative work contains the original copyright notice and the associated |
106,7 → 106,7
-- details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download |
-- it from http://www.opencores.org/lgpl.shtml |
-- it from http://www.gnu.org/licenses/lgpl.txt |
-- |
------------------------------ REVISION HISTORY ----------------------------------------------------------------------- |
-- |
/trunk/license/lgpl.txt
0,0 → 1,165
GNU LESSER GENERAL PUBLIC LICENSE |
Version 3, 29 June 2007 |
|
Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/> |
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This version of the GNU Lesser General Public License incorporates |
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0. Additional Definitions. |
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As used herein, "this License" refers to version 3 of the GNU Lesser |
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1. Exception to Section 3 of the GNU GPL. |
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