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URL https://opencores.org/ocsvn/deslcore/deslcore/trunk

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Rev 1 → Rev 2

/trunk/rtl/des_round.vhd
0,0 → 1,69
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:52:29 02/20/2013
-- Design Name:
-- Module Name: des_round - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity des_round is
port(clk : in std_logic;
l_0 : in std_logic_vector(31 downto 0);
r_0 : in std_logic_vector(31 downto 0);
k_i : in std_logic_vector(47 downto 0);
l_1 : out std_logic_vector(31 downto 0);
r_1 : out std_logic_vector(31 downto 0));
end des_round;
 
architecture Behavioral of des_round is
 
component f_fun is
port(clk : in std_logic;
r_in : in std_logic_vector(31 downto 0);
k_in : in std_logic_vector(47 downto 0);
r_out : out std_logic_vector(31 downto 0));
end component;
 
component dsp_xor is
port (clk : in std_logic;
op_1 : in std_logic_vector(31 downto 0);
op_2 : in std_logic_vector(31 downto 0);
op_3 : out std_logic_vector(31 downto 0));
end component;
 
signal f_out_s : std_logic_vector(31 downto 0);
 
begin
 
F_FUN_0 : f_fun port map (clk, r_0, k_i, f_out_s);
 
l_1 <= r_0;
r_1 <= l_0 xor f_out_s;
 
-- DSP_XOR_0 : dsp_xor port map (clk, l_0, f_out_s, r_1);
 
end Behavioral;
 
/trunk/rtl/des_loop.vhd
0,0 → 1,101
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:30:59 02/20/2013
-- Design Name:
-- Module Name: des - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity des_loop is
port(clk : in std_logic;
rst : in std_logic;
mode : in std_logic; -- 0 encrypt, 1 decrypt
key_in : in std_logic_vector(55 downto 0);
blk_in : in std_logic_vector(63 downto 0);
blk_out : out std_logic_vector(63 downto 0));
end des_loop;
 
architecture Behavioral of des_loop is
 
signal after_ip_s : std_logic_vector(63 downto 0);
signal after_ip_minus_one_s : std_logic_vector(63 downto 0);
signal after_f_s : std_logic_vector(31 downto 0);
signal final_s : std_logic_vector(63 downto 0);
 
component des_round is
port(clk : in std_logic;
l_0 : in std_logic_vector(31 downto 0);
r_0 : in std_logic_vector(31 downto 0);
k_i : in std_logic_vector(47 downto 0);
l_1 : out std_logic_vector(31 downto 0);
r_1 : out std_logic_vector(31 downto 0));
end component;
 
component key_schedule is
port(clk : in std_logic;
rst : in std_logic;
mode : in std_logic; -- 0 encrypt, 1 decrypt
key : in std_logic_vector(55 downto 0);
key_out : out std_logic_vector(47 downto 0));
end component;
 
signal key_s : std_logic_vector(47 downto 0);
 
signal l_0_s : std_logic_vector(31 downto 0);
signal l_1_s : std_logic_vector(31 downto 0);
signal r_0_s : std_logic_vector(31 downto 0);
signal r_1_s : std_logic_vector(31 downto 0);
signal rst_s : std_logic;
begin
 
pr_rst_delay : process(clk, rst)
begin
if rising_edge(clk) then
rst_s <= rst;
end if;
end process;
 
pr_seq: process(clk, rst_s, blk_in)
begin
if rst_s = '1' then
l_0_s <= blk_in(63 downto 32);
r_0_s <= blk_in(31 downto 0);
elsif rising_edge(clk) then
l_0_s <= l_1_s;
r_0_s <= r_1_s;
end if;
end process;
 
DES_ROUND_0 : des_round port map (clk, l_0_s, r_0_s, key_s, l_1_s, r_1_s);
 
blk_out <= r_1_s & l_1_s;
 
KEY_SCHEDULE_0 : key_schedule port map (clk, rst, mode, key_in, key_s);
 
end Behavioral;
 
/trunk/rtl/key_schedule.vhd
0,0 → 1,119
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:18:16 02/20/2013
-- Design Name:
-- Module Name: key_schedule - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity key_schedule is
port(clk : in std_logic;
rst : in std_logic;
mode : in std_logic; -- 0 encrypt, 1 decrypt
key : in std_logic_vector(55 downto 0);
key_out : out std_logic_vector(47 downto 0));
end key_schedule;
 
architecture Behavioral of key_schedule is
signal init_key_s : std_logic_vector(55 downto 0);
signal c_0_s : std_logic_vector(27 downto 0);
signal d_0_s : std_logic_vector(27 downto 0);
signal shift_s : std_logic_vector(15 downto 0);
signal key_pre_s : std_logic_vector(55 downto 0);
signal key_pre_delay_s : std_logic_vector(55 downto 0);
begin
 
pr_seq: process(clk, rst, key, shift_s(15), mode)
begin
if rst = '1' then
c_0_s <= key(55 downto 28);
d_0_s <= key(27 downto 0);
elsif rising_edge(clk) then
if shift_s(15) = '0' then
if mode = '0' then
c_0_s <= c_0_s(26 downto 0) & c_0_s(27);
d_0_s <= d_0_s(26 downto 0) & d_0_s(27);
else
c_0_s <= c_0_s(0) & c_0_s(27 downto 1);
d_0_s <= d_0_s(0) & d_0_s(27 downto 1);
end if;
else
if mode = '0' then
c_0_s <= c_0_s(25 downto 0) & c_0_s(27 downto 26);
d_0_s <= d_0_s(25 downto 0) & d_0_s(27 downto 26);
else
c_0_s <= c_0_s(1 downto 0) & c_0_s(27 downto 2);
d_0_s <= d_0_s(1 downto 0) & d_0_s(27 downto 2);
end if;
end if;
end if;
end process;
 
pr_shr: process(clk, rst, mode)
begin
if rst = '1' then
if mode = '0' then
shift_s <= "0011111101111110";
else
shift_s <= "0111111011111100";
end if;
elsif rising_edge(clk) then
shift_s <= shift_s(14 downto 0) & shift_s(15);
end if;
end process;
 
-- XXX Podemos meter aqui un FF para retrasar la salida n ciclos.
 
key_pre_s <= c_0_s & d_0_s;
pr_delay: process(clk, mode, key_pre_s)
begin
if rising_edge(clk) then
if mode = '1' then
key_pre_delay_s <= key_pre_s;
end if;
end if;
end process;
 
key_out <= (key_pre_s (42) & key_pre_s (39) & key_pre_s (45) & key_pre_s (32) & key_pre_s (55) & key_pre_s (51) & key_pre_s (53) & key_pre_s (28) &
key_pre_s (41) & key_pre_s (50) & key_pre_s (35) & key_pre_s (46) & key_pre_s (33) & key_pre_s (37) & key_pre_s (44) & key_pre_s (52) &
key_pre_s (30) & key_pre_s (48) & key_pre_s (40) & key_pre_s (49) & key_pre_s (29) & key_pre_s (36) & key_pre_s (43) & key_pre_s (54) &
key_pre_s (15) & key_pre_s (4) & key_pre_s (25) & key_pre_s (19) & key_pre_s (9) & key_pre_s (1) & key_pre_s (26) & key_pre_s (16) &
key_pre_s (5) & key_pre_s (11) & key_pre_s (23) & key_pre_s (8) & key_pre_s (12) & key_pre_s (7) & key_pre_s (17) & key_pre_s (0) &
key_pre_s (22) & key_pre_s (3) & key_pre_s (10) & key_pre_s (14) & key_pre_s (6) & key_pre_s (20) & key_pre_s (27) & key_pre_s (24))
when mode = '0' else
(key_pre_delay_s (42) & key_pre_delay_s (39) & key_pre_delay_s (45) & key_pre_delay_s (32) & key_pre_delay_s (55) & key_pre_delay_s (51) & key_pre_delay_s (53) & key_pre_delay_s (28) &
key_pre_delay_s (41) & key_pre_delay_s (50) & key_pre_delay_s (35) & key_pre_delay_s (46) & key_pre_delay_s (33) & key_pre_delay_s (37) & key_pre_delay_s (44) & key_pre_delay_s (52) &
key_pre_delay_s (30) & key_pre_delay_s (48) & key_pre_delay_s (40) & key_pre_delay_s (49) & key_pre_delay_s (29) & key_pre_delay_s (36) & key_pre_delay_s (43) & key_pre_delay_s (54) &
key_pre_delay_s (15) & key_pre_delay_s (4) & key_pre_delay_s (25) & key_pre_delay_s (19) & key_pre_delay_s (9) & key_pre_delay_s (1) & key_pre_delay_s (26) & key_pre_delay_s (16) &
key_pre_delay_s (5) & key_pre_delay_s (11) & key_pre_delay_s (23) & key_pre_delay_s (8) & key_pre_delay_s (12) & key_pre_delay_s (7) & key_pre_delay_s (17) & key_pre_delay_s (0) &
key_pre_delay_s (22) & key_pre_delay_s (3) & key_pre_delay_s (10) & key_pre_delay_s (14) & key_pre_delay_s (6) & key_pre_delay_s (20) & key_pre_delay_s (27) & key_pre_delay_s (24));
 
end Behavioral;
 
/trunk/rtl/s_box_l_dual_dram.xco
0,0 → 1,73
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Thu Feb 21 13:31:40 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:dist_mem_gen:7.2
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc7a200t
SET devicefamily = artix7
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fbg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Distributed_Memory_Generator xilinx.com:ip:dist_mem_gen:7.2
# END Select
# BEGIN Parameters
CSET ce_overrides=ce_overrides_sync_controls
CSET coefficient_file=s_box_l.coe
CSET common_output_ce=false
CSET common_output_clk=false
CSET component_name=s_box_l_dual_dram
CSET data_width=4
CSET default_data=0
CSET default_data_radix=16
CSET depth=64
CSET dual_port_address=non_registered
CSET dual_port_output_clock_enable=false
CSET input_clock_enable=false
CSET input_options=non_registered
CSET memory_type=dual_port_ram
CSET output_options=non_registered
CSET pipeline_stages=0
CSET qualify_we_with_i_ce=false
CSET reset_qdpo=false
CSET reset_qsdpo=false
CSET reset_qspo=false
CSET simple_dual_port_address=non_registered
CSET simple_dual_port_output_clock_enable=false
CSET single_port_output_clock_enable=false
CSET sync_reset_qdpo=false
CSET sync_reset_qsdpo=false
CSET sync_reset_qspo=false
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-21T20:07:40Z
# END Extra information
GENERATE
# CRC: b69c73ff
/trunk/rtl/s_box_l.coe
0,0 → 1,66
memory_initialization_radix=10;
memory_initialization_vector=
14,
5,
5,
0,
7,
8,
2,
15,
11,
14,
8,
3,
1,
2,
15,
12,
0,
11,
10,
7,
9,
6,
4,
9,
6,
13,
13,
4,
12,
1,
3,
10,
4,
9,
9,
6,
2,
15,
14,
5,
8,
3,
7,
8,
13,
4,
0,
11,
10,
7,
12,
1,
15,
12,
1,
2,
5,
0,
11,
14,
3,
10,
6,
13;
/trunk/rtl/f_fun.vhd
0,0 → 1,165
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:16:46 02/19/2013
-- Design Name:
-- Module Name: f_fun - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity f_fun is
port(clk : in std_logic;
r_in : in std_logic_vector(31 downto 0);
k_in : in std_logic_vector(47 downto 0);
r_out : out std_logic_vector(31 downto 0));
end f_fun;
 
architecture Behavioral of f_fun is
 
component dsp_xor is
port (clk : in std_logic;
op_1 : in std_logic_vector(31 downto 0);
op_2 : in std_logic_vector(31 downto 0);
op_3 : out std_logic_vector(31 downto 0));
end component;
 
component dsp_xor_48 is
port (clk : in std_logic;
op_1 : in std_logic_vector(47 downto 0);
op_2 : in std_logic_vector(47 downto 0);
op_3 : out std_logic_vector(47 downto 0));
end component;
 
COMPONENT s_box_dram_1
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
 
COMPONENT s_box_dram_2
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT s_box_dram_3
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
 
COMPONENT s_box_dram_4
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
 
COMPONENT s_box_dram_5
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
COMPONENT s_box_dram_6
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
 
COMPONENT s_box_dram_7
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
 
COMPONENT s_box_dram_8
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
 
COMPONENT s_box_l_dual_dram
PORT (
a : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
dpra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
dpo : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END COMPONENT;
signal blk_exp_s : std_logic_vector(47 downto 0);
signal post_exp_key_add_s : std_logic_vector(47 downto 0);
signal post_s_box_s : std_logic_vector(31 downto 0);
begin
 
-- E
 
blk_exp_s <= r_in(0) & r_in(31) & r_in(30) & r_in(29) & r_in(28) & r_in(27) &
r_in(28) & r_in(27) & r_in(26) & r_in(25) & r_in(24) & r_in(23) &
r_in(24) & r_in(23) & r_in(22) & r_in(21) & r_in(20) & r_in(19) &
r_in(20) & r_in(19) & r_in(18) & r_in(17) & r_in(16) & r_in(15) &
r_in(16) & r_in(15) & r_in(14) & r_in(13) & r_in(12) & r_in(11) &
r_in(12) & r_in(11) & r_in(10) & r_in(9) & r_in(8) & r_in(7) &
r_in(8) & r_in(7) & r_in(6) & r_in(5) & r_in(4) & r_in(3) &
r_in(4) & r_in(3) & r_in(2) & r_in(1) & r_in(0) & r_in(31);
-- DSP_XOR_0 : dsp_xor_48 port map (clk, blk_exp_s, k_in, post_exp_key_add_s);
 
post_exp_key_add_s <= blk_exp_s xor k_in;
 
S_BOX_0 : s_box_l_dual_dram port map (post_exp_key_add_s(47 downto 42),
(others => '0'),
post_exp_key_add_s(41 downto 36),
clk,
'0',
post_s_box_s(31 downto 28),
post_s_box_s(27 downto 24));
 
S_BOX_1 : s_box_l_dual_dram port map (post_exp_key_add_s(35 downto 30),
(others => '0'),
post_exp_key_add_s(29 downto 24),
clk,
'0',
post_s_box_s(23 downto 20),
post_s_box_s(19 downto 16));
 
S_BOX_2 : s_box_l_dual_dram port map (post_exp_key_add_s(23 downto 18),
(others => '0'),
post_exp_key_add_s(17 downto 12),
clk,
'0',
post_s_box_s(15 downto 12),
post_s_box_s(11 downto 8));
 
S_BOX_3 : s_box_l_dual_dram port map (post_exp_key_add_s(11 downto 6),
(others => '0'),
post_exp_key_add_s(5 downto 0),
clk,
'0',
post_s_box_s(7 downto 4),
post_s_box_s(3 downto 0));
 
r_out <= post_s_box_s(16) & post_s_box_s(25) & post_s_box_s(12) & post_s_box_s(11) & post_s_box_s(3) & post_s_box_s(20) & post_s_box_s(4) & post_s_box_s(15) &
post_s_box_s(31) & post_s_box_s(17) & post_s_box_s(9) & post_s_box_s(6) & post_s_box_s(27) & post_s_box_s(14) & post_s_box_s(1) & post_s_box_s(22) &
post_s_box_s(30) & post_s_box_s(24) & post_s_box_s(8) & post_s_box_s(18) & post_s_box_s(0) & post_s_box_s(5) & post_s_box_s(29) & post_s_box_s(23) &
post_s_box_s(13) & post_s_box_s(19) & post_s_box_s(2) & post_s_box_s(26) & post_s_box_s(10) & post_s_box_s(21) & post_s_box_s(28) & post_s_box_s(7);
 
 
end Behavioral;
 
/trunk/tb/tb_des_loop.vhd
0,0 → 1,120
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:47:33 02/21/2013
-- Design Name:
-- Module Name: C:/Users/vmr/Desktop/crypto_ng/des/dram/desl/tb_des_loop.vhd
-- Project Name: desl
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: des_loop
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_des_loop IS
END tb_des_loop;
ARCHITECTURE behavior OF tb_des_loop IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT des_loop
PORT(
clk : IN std_logic;
rst : IN std_logic;
mode : IN std_logic;
key_in : IN std_logic_vector(55 downto 0);
blk_in : IN std_logic_vector(63 downto 0);
blk_out : OUT std_logic_vector(63 downto 0)
);
END COMPONENT;
 
--Inputs
signal clk : std_logic := '0';
signal rst : std_logic := '0';
signal mode : std_logic := '0';
signal key_in : std_logic_vector(55 downto 0) := (others => '0');
signal blk_in : std_logic_vector(63 downto 0) := (others => '0');
 
--Outputs
signal blk_out : std_logic_vector(63 downto 0);
 
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: des_loop PORT MAP (
clk => clk,
rst => rst,
mode => mode,
key_in => key_in,
blk_in => blk_in,
blk_out => blk_out
);
 
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
 
-- Stimulus process
stim_proc: process
begin
wait for clk_period/2 + clk_period;
mode <= '0';
blk_in <= X"4E45565251554954";
key_in <= "00000000111111110000000000101010010100000000000110010100";
rst <= '1';
wait for clk_period;
rst <= '0';
wait for clk_period*16;
assert blk_out = X"72c6e3c6d2168e78"
report "ENCRYPT ERROR" severity FAILURE;
wait for clk_period;
 
mode <= '1';
blk_in <= X"72c6e3c6d2168e78";
key_in <= "00000000111111110000000000101010010100000000000110010100";
rst <= '1';
wait for clk_period;
rst <= '0';
wait for clk_period*16;
 
assert blk_out = X"4E45565251554954"
report "DECRYPT ERROR" severity FAILURE;
 
wait;
end process;
 
END;

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