OpenCores
URL https://opencores.org/ocsvn/dmt_tx/dmt_tx/trunk

Subversion Repositories dmt_tx

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /dmt_tx
    from Rev 27 to Rev 28
    ↔ Reverse comparison
  •

Rev 27 → Rev 28

/trunk/myhdl/test/test_const_encoder.py
0,0 → 1,119
#!/usr/bin/env python
 
import unittest
 
import os
from myhdl import *
 
import random
 
from rtl.const_encoder import const_encoder
 
 
########################################################################
#
# Test cases
#
class TestConstEncoder(unittest.TestCase):
 
def test_const_encoder(self):
def bench(tc):
clk, reset, \
wen_i, data_valid_o \
= [Signal(bool(0)) for i in range(4)]
 
const_size_i = Signal(intbv(0)[4:])
data_i = Signal(intbv(0)[15:])
x_o, y_o = [Signal(intbv(0, min=-256, max=256)) for i in range(2)]
 
const_encoder_inst = const_encoder( clk, reset,
wen_i, const_size_i,
data_i,
data_valid_o, x_o, y_o)
@always(delay(10))
def clkgen():
clk.next = not clk
 
@instance
def stimulus():
 
yield clk.negedge
reset.next = 1
yield clk.negedge
reset.next = 0
 
size = 5
const_size_i.next = size
 
for i in range(2**size):
data_i.next = i
wen_i.next = 1
yield clk.negedge
wen_i.next = 0
 
@instance
def verify():
expb2XL = [1, 1, -1, -1]
expb2YL = [1, -1, 1, -1]
expb3XL = [1, 1, -1, -1, -3, 1, -1]
expb3YL = [1, -1, 1, -1, 1, 3, -3]
expb4XL = [1, 1, 3, 3, 1, 1, 3, 3, -3, -3, -1, -1, -3, -3, -1, -1]
expb4YL = [1, 3, 1, 3, -3, -1, -3, -1, 1, 3, 1, 3, -3, -1, -3, -1]
expb5XL = [1, 1, 3, 3, 1, 1, 3, 3, -3, -3, -1, -1, -3, -3, -1, -1,
5, 5, -5, -5, 1, 1, 3, 3, -3, -3, -1, -1, 5, 5, -5, -5]
expb5YL = [1, 3, 1, 3, -3, -1, -3, -1, 1, 3, 1, 3, -3, -1, -3, -1,
1, 3, 1, 3, 5, -5, 5, -5, 5, -5, 5, -5, -3, -1, -3, -1]
 
 
expXL = []
expYL = []
yield data_valid_o.posedge
 
if const_size_i == 2:
expXL = expb2XL
expYL = expb2YL
elif const_size_i == 4:
expXL = expb4XL
expYL = expb4YL
elif const_size_i == 5:
expXL = expb5XL
expYL = expb5YL
 
#print "expXL ", expXL
#print "expYL ", expYL
#print "at ", now()
 
 
for j, expX in enumerate(expXL):
 
yield clk.negedge
#print
#print "data_valid: %d x_o: %d y_o: %d at %d"%( data_valid_o,
# x_o, y_o,
# now())
#print "expecting x_o: %d y_o: %d"%(expX, expYL[j])
 
if expX != x_o:
tc.fail("%d != x_o: %d at %d"%(expX, x_o, now()))
if expYL[j] != y_o:
tc.fail("%d != y_o: %d at %d"%(expYL[j], y_o, now()))
raise StopSimulation
return instances()
 
#####################################
tb = bench(self)
#tb = traceSignals(bench)
sim = Simulation(tb)
sim.run()
 
 
trunk/myhdl/test/test_const_encoder.py Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/myhdl/rtl/const_encoder.py =================================================================== --- trunk/myhdl/rtl/const_encoder.py (nonexistent) +++ trunk/myhdl/rtl/const_encoder.py (revision 28) @@ -0,0 +1,139 @@ + +from myhdl import * + + +def const_encoder( clk, reset, wen_i, const_size_i, data_i, + data_valid_o, x_o, y_o): + '''Constellation encoder + + I/O pins: + ========= + clk : clock input + reset : reset input + + wen_i : write enable for the const_size_i and data_i + const_size_i : select the constellation size + data_i : data word to be encoded + data_valid_o : signal that the output data x_o and y_o are valid + after an applied wen_i + x_o : real part of the constellation point + y_o : imaginary part of the constellation point + + parameters: + =========== + + ''' + + din_reg = Signal(intbv(0)[15:]) + const_size_i_reg = Signal(intbv(0)[4:]) + dvalid_reg = Signal(intbv(0)[1:]) + + x,y = [Signal(intbv(0,min=-256,max=256)) for i in range(2)] + + XY = [0,0,0,0, 3,3,3,3, 12,12,12,12, 15,15,15,15, 4,4, 8,8, + 1,2,1,2, 13,14,13,14, 7,7,11,11] + + @always(clk.posedge, reset.posedge) + def reg_input(): + + if reset: + din_reg.next = 0 + const_size_i_reg.next = const_size_i + else: + + if wen_i: + #print "data_i: %d size: %d at %d"%(data_i, const_size_i, now()) + din_reg.next = data_i + const_size_i_reg.next = const_size_i + + + @always(clk.posedge, reset.posedge) + def reg_output(): + + if reset: + x_o.next = 0 + y_o.next = 0 + dvalid_reg.next = 0 + data_valid_o.next = 0 + else: + x_o.next = x + y_o.next = y + #print "x_o: %d y_o: %d at %d"%(x_o,y_o,now()) + + dvalid_reg.next[0] = wen_i + data_valid_o.next = dvalid_reg[0] + + + @always_comb + def const_enc(): + + if const_size_i_reg[0] == 0: # even constellation + + if const_size_i_reg == 2: + x.next = concat(din_reg[1], True).signed() + y.next = concat(din_reg[0], True).signed() + #x.next = concat(din_reg[1], True) + #y.next = concat(din_reg[0], True) + elif const_size_i_reg == 4: + x.next = concat(din_reg[3], din_reg[1], True).signed() + y.next = concat(din_reg[2], din_reg[0], True).signed() + #x.next = concat(din_reg[3], din_reg[1], True) + #y.next = concat(din_reg[2], din_reg[0], True) + + else: # odd constellation + + if const_size_i_reg == 3: + if din_reg == 4: + x.next = -3 + y.next = 1 + elif din_reg == 5: + x.next = 1 + y.next = 3 + elif din_reg == 6: + x.next = -1 + y.next = -3 + elif din_reg == 7: + x.next = 3 + y.next = -1 + else: + x.next = concat(din_reg[1], True).signed() + y.next = concat(din_reg[0], True).signed() + + else: + addr = concat( din_reg[const_size_i_reg-1], + din_reg[const_size_i_reg-2], + din_reg[const_size_i_reg-3], + din_reg[const_size_i_reg-4], + din_reg[const_size_i_reg-5]) + + xy = intbv(XY[int(addr)])[4:] + top2X = xy[4:2] + top2Y = xy[2:0] + + if const_size_i_reg == 5: + x.next = concat(top2X, din_reg[1], True).signed() + y.next = concat(top2Y, din_reg[0], True).signed() + + return instances() + + +######################################################################## +def convert(): + + clk, reset, \ + wen_i, data_valid_o \ + = [Signal(bool(0)) for i in range(4)] + + const_size_i = Signal(intbv(0)[4:]) + data_i = Signal(intbv(0)[15:]) + x_o, y_o = [Signal(intbv(0, min=-256, max=256)) for i in range(2)] + + toVerilog(const_encoder, + clk, reset, + wen_i, const_size_i, + data_i, + data_valid_o, x_o, y_o) + + +if __name__ == '__main__': + convert() Index: trunk/myhdl/adsl_main.py =================================================================== --- trunk/myhdl/adsl_main.py (revision 27) +++ trunk/myhdl/adsl_main.py (revision 28) @@ -12,10 +12,11 @@ import unittest -import test.test_flipSign, test.test_cmath +import test.test_flipSign, test.test_cmath, test.test_const_encoder mL = [test.test_flipSign] mL.append(test.test_cmath) +mL.append(test.test_const_encoder) tl = unittest.defaultTestLoader def suite():

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.