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/trunk/fpmult/fpmult.sdc
0,0 → 1,108
## Generated SDC file "fpmult.sdc"
 
## Copyright (C) 1991-2010 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
 
 
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 10.1 Build 153 11/29/2010 SJ Web Edition"
 
## DATE "Sun Jan 30 18:51:15 2011"
 
##
## DEVICE "EP2C20F484C7"
##
 
 
#**************************************************************
# Time Information
#**************************************************************
 
set_time_format -unit ns -decimal_places 3
 
 
 
#**************************************************************
# Create Clock
#**************************************************************
 
create_clock -name {altera_reserved_tck} -period 20.000 -waveform { 0.000 10.000 } [get_ports { altera_reserved_tck }]
 
 
#**************************************************************
# Create Generated Clock
#**************************************************************
 
 
 
#**************************************************************
# Set Clock Latency
#**************************************************************
 
 
 
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
 
 
 
#**************************************************************
# Set Input Delay
#**************************************************************
 
 
 
#**************************************************************
# Set Output Delay
#**************************************************************
 
 
 
#**************************************************************
# Set Clock Groups
#**************************************************************
 
set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
 
 
#**************************************************************
# Set False Path
#**************************************************************
 
 
 
#**************************************************************
# Set Multicycle Path
#**************************************************************
 
 
 
#**************************************************************
# Set Maximum Delay
#**************************************************************
 
 
 
#**************************************************************
# Set Minimum Delay
#**************************************************************
 
 
 
#**************************************************************
# Set Input Transition
#**************************************************************
 
/trunk/fpmult/src/fpmult_stage23.vhdl
0,0 → 1,58
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fp_generic.all;
use work.fpmult_stage23_comp.all;
 
entity fpmult_stage23 is
port(
clk:in std_logic;
d:in fpmult_stage23_in_type;
q:out fpmult_stage23_out_type
);
end;
 
architecture twoproc of fpmult_stage23 is
type reg_type is record
p_sign:fp_sign_type;
p_exp:fp_exp_type;
p_mantissa:unsigned(47 downto 0);
end record;
signal r,rin:reg_type;
begin
comb:process(d,r)
variable v:reg_type;
begin
-- sample register outputs
v:=r;
 
-- overload
v.p_sign:=d.p_sign;
v.p_exp:=d.p_exp;
v.p_mantissa:=(resize(fp_mantissa(d.a),48) sll 23) + d.p_mantissa;
 
-- Shift down if product >= 2.0
if(v.p_mantissa(47)='1')then
v.p_mantissa:=v.p_mantissa srl 1;
v.p_exp:=v.p_exp+1;
end if;
 
-- Round mantissa
if(v.p_mantissa(22)='1')then
v.p_mantissa:=v.p_mantissa+(to_unsigned(1,48) sll 23);
end if;
 
-- drive register inputs
rin<=v;
 
-- drive outputs
q.p<=std_logic_vector(r.p_sign&r.p_exp&r.p_mantissa(45 downto 23));
end process;
seq:process(clk,rin)
begin
if rising_edge(clk) then
r<=rin;
end if;
end process;
end;
/trunk/fpmult/src/fpmult.vhdl
55,11 → 55,7
 
stage0:fpmult_stage0 port map(clk,fpmult_stage0_in,fpmult_stage0_out);
 
fpmult_stageN_in_array(1).a<=fpmult_stage0_out.a;
fpmult_stageN_in_array(1).b<=fpmult_stage0_out.b;
fpmult_stageN_in_array(1).p_sign<=fpmult_stage0_out.p_sign;
fpmult_stageN_in_array(1).p_exp<=fpmult_stage0_out.p_exp;
fpmult_stageN_in_array(1).p_mantissa<=fpmult_stage0_out.p_mantissa;
fpmult_stageN_in_array(1)<=fpmult_stage0_out;
pipeline:for N in 22 downto 1 generate
stageN:fpmult_stageN generic map(N) port map(clk,fpmult_stageN_in_array(N),fpmult_stageN_out_array(N));
66,10 → 62,7
fpmult_stageN_in_array(N+1)<=fpmult_stageN_out_array(N);
end generate pipeline;
 
fpmult_stage23_in.a<=fpmult_stageN_out_array(22).a;
fpmult_stage23_in.p_sign<=fpmult_stageN_out_array(22).p_sign;
fpmult_stage23_in.p_exp<=fpmult_stageN_out_array(22).p_exp;
fpmult_stage23_in.p_mantissa<=fpmult_stageN_out_array(22).p_mantissa;
fpmult_stage23_in<=fpmult_stageN_out_array(22);
 
stage23:fpmult_stage23 port map(clk,fpmult_stage23_in,fpmult_stage23_out);
 
/trunk/fpmult/src/fpmult_stage23_comp.vhdl
0,0 → 1,22
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fp_generic.all;
use work.fpmult_generic.all;
use work.fpmult_stageN_comp.all;
 
package fpmult_stage23_comp is
alias fpmult_stage23_in_type is fpmult_stageN_out_type;
 
type fpmult_stage23_out_type is record
p:fp_type;
end record;
 
component fpmult_stage23 is
port(
clk:in std_logic;
d:in fpmult_stage23_in_type;
q:out fpmult_stage23_out_type
);
end component;
end package;

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