URL
https://opencores.org/ocsvn/ethmac/ethmac/trunk
Subversion Repositories ethmac
Compare Revisions
- This comparison shows the changes necessary to convert path
/ethmac
- from Rev 351 to Rev 352
- ↔ Reverse comparison
Rev 351 → Rev 352
/trunk/rtl/verilog/eth_spram_256x32.v
272,7 → 272,7
// read operation |
always@(posedge clk) |
if (ce) // && !we) |
raddr <= #1 addr; // read address needs to be registered to read clock |
raddr <= addr; // read address needs to be registered to read clock |
|
assign #1 q = rst ? {32{1'b0}} : {mem3[raddr], mem2[raddr], mem1[raddr], mem0[raddr]}; |
|
280,14 → 280,14
always@(posedge clk) |
begin |
if (ce && we[3]) |
mem3[addr] <= #1 di[31:24]; |
mem3[addr] <= di[31:24]; |
if (ce && we[2]) |
mem2[addr] <= #1 di[23:16]; |
mem2[addr] <= di[23:16]; |
if (ce && we[1]) |
mem1[addr] <= #1 di[15: 8]; |
mem1[addr] <= di[15: 8]; |
if (ce && we[0]) |
mem0[addr] <= #1 di[ 7: 0]; |
end |
mem0[addr] <= di[ 7: 0]; |
end |
|
// Task prints range of memory |
// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations. |
/trunk/rtl/verilog/eth_shiftreg.v
79,8 → 79,6
LatchByte, ShiftedBit, Prsd, LinkFail); |
|
|
parameter Tp=1; |
|
input Clk; // Input clock (Host clock) |
input Reset; // Reset signal |
input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls. |
108,9 → 106,9
begin |
if(Reset) |
begin |
ShiftReg[7:0] <= #Tp 8'h0; |
Prsd[15:0] <= #Tp 16'h0; |
LinkFail <= #Tp 1'b0; |
ShiftReg[7:0] <= 8'h0; |
Prsd[15:0] <= 16'h0; |
LinkFail <= 1'b0; |
end |
else |
begin |
119,25 → 117,25
if(|ByteSelect) |
begin |
case (ByteSelect[3:0]) // synopsys parallel_case full_case |
4'h1 : ShiftReg[7:0] <= #Tp {2'b01, ~WriteOp, WriteOp, Fiad[4:1]}; |
4'h2 : ShiftReg[7:0] <= #Tp {Fiad[0], Rgad[4:0], 2'b10}; |
4'h4 : ShiftReg[7:0] <= #Tp CtrlData[15:8]; |
4'h8 : ShiftReg[7:0] <= #Tp CtrlData[7:0]; |
4'h1 : ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp, Fiad[4:1]}; |
4'h2 : ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10}; |
4'h4 : ShiftReg[7:0] <= CtrlData[15:8]; |
4'h8 : ShiftReg[7:0] <= CtrlData[7:0]; |
endcase |
end |
else |
begin |
ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi}; |
ShiftReg[7:0] <= {ShiftReg[6:0], Mdi}; |
if(LatchByte[0]) |
begin |
Prsd[7:0] <= #Tp {ShiftReg[6:0], Mdi}; |
Prsd[7:0] <= {ShiftReg[6:0], Mdi}; |
if(Rgad == 5'h01) |
LinkFail <= #Tp ~ShiftReg[1]; // this is bit [2], because it is not shifted yet |
LinkFail <= ~ShiftReg[1]; // this is bit [2], because it is not shifted yet |
end |
else |
begin |
if(LatchByte[1]) |
Prsd[15:8] <= #Tp {ShiftReg[6:0], Mdi}; |
Prsd[15:8] <= {ShiftReg[6:0], Mdi}; |
end |
end |
end |
/trunk/rtl/verilog/eth_rxethmac.v
119,10 → 119,8
MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss, PassAll, ControlFrmAddressOK |
); |
|
parameter Tp = 1; |
|
|
|
input MRxClk; |
input MRxDV; |
input [3:0] MRxD; |
198,7 → 196,7
|
|
// Rx State Machine module |
eth_rxstatem #(.Tp(Tp)) |
eth_rxstatem |
rxstatem1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .ByteCntEq0(ByteCntEq0), |
.ByteCntGreat2(ByteCntGreat2), .Transmitting(Transmitting), .MRxDEq5(MRxDEq5), |
.MRxDEqD(MRxDEqD), .IFGCounterEq24(IFGCounterEq24), .ByteCntMaxFrame(ByteCntMaxFrame), |
208,7 → 206,7
|
|
// Rx Counters module |
eth_rxcounters #(.Tp(Tp)) |
eth_rxcounters |
rxcounters1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .StateIdle(StateIdle), |
.StateSFD(StateSFD), .StateData(StateData), .StateDrop(StateDrop), |
.StatePreamble(StatePreamble), .MRxDEqD(MRxDEqD), .DlyCrcEn(DlyCrcEn), |
223,7 → 221,7
|
// Rx Address Check |
|
eth_rxaddrcheck #(.Tp(Tp)) |
eth_rxaddrcheck |
rxaddrcheck1 |
(.MRxClk(MRxClk), .Reset( Reset), .RxData(RxData), |
.Broadcast (Broadcast), .r_Bro (r_Bro), .r_Pro(r_Pro), |
247,7 → 245,7
|
|
// Connecting module Crc |
eth_crc #(.Tp(Tp)) |
eth_crc |
crcrx (.Clk(MRxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc), |
.Crc(Crc), .CrcError(CrcError) |
); |
258,16 → 256,16
|
always @ (posedge MRxClk) |
begin |
CrcHashGood <= #Tp StateData[0] & ByteCntEq6; |
CrcHashGood <= StateData[0] & ByteCntEq6; |
end |
|
always @ (posedge MRxClk) |
begin |
if(Reset | StateIdle) |
CrcHash[5:0] <= #Tp 6'h0; |
CrcHash[5:0] <= 6'h0; |
else |
if(StateData[0] & ByteCntEq6) |
CrcHash[5:0] <= #Tp Crc[31:26]; |
CrcHash[5:0] <= Crc[31:26]; |
end |
|
|
276,23 → 274,23
begin |
if(Reset) |
begin |
RxData_d[7:0] <= #Tp 8'h0; |
DelayData <= #Tp 1'b0; |
LatchedByte[7:0] <= #Tp 8'h0; |
RxData[7:0] <= #Tp 8'h0; |
RxData_d[7:0] <= 8'h0; |
DelayData <= 1'b0; |
LatchedByte[7:0] <= 8'h0; |
RxData[7:0] <= 8'h0; |
end |
else |
begin |
LatchedByte[7:0] <= #Tp {MRxD[3:0], LatchedByte[7:4]}; // Latched byte |
DelayData <= #Tp StateData[0]; |
LatchedByte[7:0] <= {MRxD[3:0], LatchedByte[7:4]}; // Latched byte |
DelayData <= StateData[0]; |
|
if(GenerateRxValid) |
RxData_d[7:0] <= #Tp LatchedByte[7:0] & {8{|StateData}}; // Data goes through only in data state |
RxData_d[7:0] <= LatchedByte[7:0] & {8{|StateData}}; // Data goes through only in data state |
else |
if(~DelayData) |
RxData_d[7:0] <= #Tp 8'h0; // Delaying data to be valid for two cycles. Zero when not active. |
RxData_d[7:0] <= 8'h0; // Delaying data to be valid for two cycles. Zero when not active. |
|
RxData[7:0] <= #Tp RxData_d[7:0]; // Output data byte |
RxData[7:0] <= RxData_d[7:0]; // Output data byte |
end |
end |
|
301,17 → 299,17
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
Broadcast <= #Tp 1'b0; |
Broadcast <= 1'b0; |
else |
begin |
if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7) |
Broadcast <= #Tp 1'b0; |
Broadcast <= 1'b0; |
else |
if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1) |
Broadcast <= #Tp 1'b1; |
Broadcast <= 1'b1; |
else |
if(RxAbort | RxEndFrm) |
Broadcast <= #Tp 1'b0; |
Broadcast <= 1'b0; |
end |
end |
|
319,13 → 317,13
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
Multicast <= #Tp 1'b0; |
Multicast <= 1'b0; |
else |
begin |
if(StateData[0] & ByteCntEq1 & LatchedByte[0]) |
Multicast <= #Tp 1'b1; |
Multicast <= 1'b1; |
else if(RxAbort | RxEndFrm) |
Multicast <= #Tp 1'b0; |
Multicast <= 1'b0; |
end |
end |
|
336,13 → 334,13
begin |
if(Reset) |
begin |
RxValid_d <= #Tp 1'b0; |
RxValid <= #Tp 1'b0; |
RxValid_d <= 1'b0; |
RxValid <= 1'b0; |
end |
else |
begin |
RxValid_d <= #Tp GenerateRxValid; |
RxValid <= #Tp RxValid_d; |
RxValid_d <= GenerateRxValid; |
RxValid <= RxValid_d; |
end |
end |
|
353,13 → 351,13
begin |
if(Reset) |
begin |
RxStartFrm_d <= #Tp 1'b0; |
RxStartFrm <= #Tp 1'b0; |
RxStartFrm_d <= 1'b0; |
RxStartFrm <= 1'b0; |
end |
else |
begin |
RxStartFrm_d <= #Tp GenerateRxStartFrm; |
RxStartFrm <= #Tp RxStartFrm_d; |
RxStartFrm_d <= GenerateRxStartFrm; |
RxStartFrm <= RxStartFrm_d; |
end |
end |
|
372,13 → 370,13
begin |
if(Reset) |
begin |
RxEndFrm_d <= #Tp 1'b0; |
RxEndFrm <= #Tp 1'b0; |
RxEndFrm_d <= 1'b0; |
RxEndFrm <= 1'b0; |
end |
else |
begin |
RxEndFrm_d <= #Tp GenerateRxEndFrm; |
RxEndFrm <= #Tp RxEndFrm_d | DribbleRxEndFrm; |
RxEndFrm_d <= GenerateRxEndFrm; |
RxEndFrm <= RxEndFrm_d | DribbleRxEndFrm; |
end |
end |
|
/trunk/rtl/verilog/eth_rxcounters.v
89,8 → 89,6
ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, ByteCntOut |
); |
|
parameter Tp = 1; |
|
input MRxClk; |
input Reset; |
input MRxDV; |
146,14 → 144,14
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ByteCnt[15:0] <= #Tp 16'h0; |
ByteCnt[15:0] <= 16'h0; |
else |
begin |
if(ResetByteCounter) |
ByteCnt[15:0] <= #Tp 16'h0; |
ByteCnt[15:0] <= 16'h0; |
else |
if(IncrementByteCounter) |
ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1; |
ByteCnt[15:0] <= ByteCnt[15:0] + 1'b1; |
end |
end |
|
181,14 → 179,14
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
IFGCounter[4:0] <= #Tp 5'h0; |
IFGCounter[4:0] <= 5'h0; |
else |
begin |
if(ResetIFGCounter) |
IFGCounter[4:0] <= #Tp 5'h0; |
IFGCounter[4:0] <= 5'h0; |
else |
if(IncrementIFGCounter) |
IFGCounter[4:0] <= #Tp IFGCounter[4:0] + 1'b1; |
IFGCounter[4:0] <= IFGCounter[4:0] + 1'b1; |
end |
end |
|
200,17 → 198,17
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
DlyCrcCnt[3:0] <= #Tp 4'h0; |
DlyCrcCnt[3:0] <= 4'h0; |
else |
begin |
if(DlyCrcCnt[3:0] == 4'h9) |
DlyCrcCnt[3:0] <= #Tp 4'h0; |
DlyCrcCnt[3:0] <= 4'h0; |
else |
if(DlyCrcEn & StateSFD) |
DlyCrcCnt[3:0] <= #Tp 4'h1; |
DlyCrcCnt[3:0] <= 4'h1; |
else |
if(DlyCrcEn & (|DlyCrcCnt[3:0])) |
DlyCrcCnt[3:0] <= #Tp DlyCrcCnt[3:0] + 1'b1; |
DlyCrcCnt[3:0] <= DlyCrcCnt[3:0] + 1'b1; |
end |
end |
|
/trunk/rtl/verilog/eth_txethmac.v
103,9 → 103,7
|
); |
|
parameter Tp = 1; |
|
|
input MTxClk; // Transmit clock (from PHY) |
input Reset; // Reset |
input TxStartFrm; // Transmit packet start frame |
227,14 → 225,14
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
StopExcessiveDeferOccured <= #Tp 1'b0; |
StopExcessiveDeferOccured <= 1'b0; |
else |
begin |
if(~TxStartFrm) |
StopExcessiveDeferOccured <= #Tp 1'b0; |
StopExcessiveDeferOccured <= 1'b0; |
else |
if(ExcessiveDeferOccured) |
StopExcessiveDeferOccured <= #Tp 1'b1; |
StopExcessiveDeferOccured <= 1'b1; |
end |
end |
|
243,14 → 241,14
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
ColWindow <= #Tp 1'b1; |
ColWindow <= 1'b1; |
else |
begin |
if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0])) |
ColWindow <= #Tp 1'b0; |
ColWindow <= 1'b0; |
else |
if(StateIdle | StateIPG) |
ColWindow <= #Tp 1'b1; |
ColWindow <= 1'b1; |
end |
end |
|
259,14 → 257,14
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
StatusLatch <= #Tp 1'b0; |
StatusLatch <= 1'b0; |
else |
begin |
if(~TxStartFrm) |
StatusLatch <= #Tp 1'b0; |
StatusLatch <= 1'b0; |
else |
if(ExcessiveDeferOccured | StateIdle) |
StatusLatch <= #Tp 1'b1; |
StatusLatch <= 1'b1; |
end |
end |
|
275,9 → 273,9
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxUsedData <= #Tp 1'b0; |
TxUsedData <= 1'b0; |
else |
TxUsedData <= #Tp |StartData; |
TxUsedData <= |StartData; |
end |
|
|
285,14 → 283,14
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxDone <= #Tp 1'b0; |
TxDone <= 1'b0; |
else |
begin |
if(TxStartFrm & ~StatusLatch) |
TxDone <= #Tp 1'b0; |
TxDone <= 1'b0; |
else |
if(StartTxDone) |
TxDone <= #Tp 1'b1; |
TxDone <= 1'b1; |
end |
end |
|
301,14 → 299,14
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxRetry <= #Tp 1'b0; |
TxRetry <= 1'b0; |
else |
begin |
if(TxStartFrm & ~StatusLatch) |
TxRetry <= #Tp 1'b0; |
TxRetry <= 1'b0; |
else |
if(StartTxRetry) |
TxRetry <= #Tp 1'b1; |
TxRetry <= 1'b1; |
end |
end |
|
317,14 → 315,14
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxAbort <= #Tp 1'b0; |
TxAbort <= 1'b0; |
else |
begin |
if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured) |
TxAbort <= #Tp 1'b0; |
TxAbort <= 1'b0; |
else |
if(StartTxAbort) |
TxAbort <= #Tp 1'b1; |
TxAbort <= 1'b1; |
end |
end |
|
333,15 → 331,15
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
RetryCnt[3:0] <= #Tp 4'h0; |
RetryCnt[3:0] <= 4'h0; |
else |
begin |
if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun |
| StateJam & NibCntEq7 & (~ColWindow | RetryMax)) |
RetryCnt[3:0] <= #Tp 4'h0; |
RetryCnt[3:0] <= 4'h0; |
else |
if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt) |
RetryCnt[3:0] <= #Tp RetryCnt[3:0] + 1'b1; |
RetryCnt[3:0] <= RetryCnt[3:0] + 1'b1; |
end |
end |
|
379,9 → 377,9
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
MTxEn <= #Tp 1'b0; |
MTxEn <= 1'b0; |
else |
MTxEn <= #Tp StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam; |
MTxEn <= StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam; |
end |
|
|
389,9 → 387,9
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
MTxD[3:0] <= #Tp 4'h0; |
MTxD[3:0] <= 4'h0; |
else |
MTxD[3:0] <= #Tp MTxD_d[3:0]; |
MTxD[3:0] <= MTxD_d[3:0]; |
end |
|
|
399,9 → 397,9
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
MTxErr <= #Tp 1'b0; |
MTxErr <= 1'b0; |
else |
MTxErr <= #Tp TooBig | UnderRun; |
MTxErr <= TooBig | UnderRun; |
end |
|
|
409,9 → 407,9
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
WillTransmit <= #Tp 1'b0; |
WillTransmit <= 1'b0; |
else |
WillTransmit <= #Tp StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam; |
WillTransmit <= StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam; |
end |
|
|
423,20 → 421,19
begin |
if(Reset) |
begin |
PacketFinished <= #Tp 1'b0; |
PacketFinished_q <= #Tp 1'b0; |
PacketFinished <= 1'b0; |
PacketFinished_q <= 1'b0; |
end |
else |
begin |
PacketFinished <= #Tp PacketFinished_d; |
PacketFinished_q <= #Tp PacketFinished; |
PacketFinished <= PacketFinished_d; |
PacketFinished_q <= PacketFinished; |
end |
end |
|
|
// Connecting module Counters |
eth_txcounters #(.Tp(Tp)) |
txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData), |
eth_txcounters txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData), |
.StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff), |
.StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG), |
.StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk), |
449,8 → 446,7
|
|
// Connecting module StateM |
eth_txstatem #(.Tp(Tp)) |
txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense), |
eth_txstatem txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense), |
.NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD), |
.TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision), |
.UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7), |
479,15 → 475,13
|
|
// Connecting module Crc |
eth_crc #(.Tp(Tp)) |
txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc), |
eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc), |
.Crc(Crc), .CrcError(CrcError) |
); |
|
|
// Connecting module Random |
eth_random #(.Tp(Tp)) |
random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt), |
eth_random random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt), |
.NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt)); |
|
|
/trunk/rtl/verilog/eth_wishbone.v
308,7 → 308,6
); |
|
|
parameter Tp = 1; |
parameter TX_FIFO_DATA_WIDTH = `ETH_TX_FIFO_DATA_WIDTH; |
parameter TX_FIFO_DEPTH = `ETH_TX_FIFO_DEPTH; |
parameter TX_FIFO_CNT_WIDTH = `ETH_TX_FIFO_CNT_WIDTH; |
557,7 → 556,7
|
always @ (posedge WB_CLK_I) |
begin |
WB_ACK_O <=#Tp (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q; |
WB_ACK_O <= (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q; |
end |
|
assign WB_DAT_O = ram_do; |
581,13 → 580,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxEn_needed <=#Tp 1'b0; |
TxEn_needed <= 1'b0; |
else |
if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q) |
TxEn_needed <=#Tp 1'b1; |
TxEn_needed <= 1'b1; |
else |
if(TxPointerRead & TxEn & TxEn_q) |
TxEn_needed <=#Tp 1'b0; |
TxEn_needed <= 1'b0; |
end |
|
// Enabling access to the RAM for three devices. |
595,13 → 594,13
begin |
if(Reset) |
begin |
WbEn <=#Tp 1'b1; |
RxEn <=#Tp 1'b0; |
TxEn <=#Tp 1'b0; |
ram_addr <=#Tp 8'h0; |
ram_di <=#Tp 32'h0; |
BDRead <=#Tp 1'b0; |
BDWrite <=#Tp 1'b0; |
WbEn <= 1'b1; |
RxEn <= 1'b0; |
TxEn <= 1'b0; |
ram_addr <= 8'h0; |
ram_di <= 32'h0; |
BDRead <= 1'b0; |
BDWrite <= 1'b0; |
end |
else |
begin |
609,61 → 608,61
case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case |
5'b100_10, 5'b100_11 : |
begin |
WbEn <=#Tp 1'b0; |
RxEn <=#Tp 1'b1; // wb access stage and r_RxEn is enabled |
TxEn <=#Tp 1'b0; |
ram_addr <=#Tp {RxBDAddress, RxPointerRead}; |
ram_di <=#Tp RxBDDataIn; |
WbEn <= 1'b0; |
RxEn <= 1'b1; // wb access stage and r_RxEn is enabled |
TxEn <= 1'b0; |
ram_addr <= {RxBDAddress, RxPointerRead}; |
ram_di <= RxBDDataIn; |
end |
5'b100_01 : |
begin |
WbEn <=#Tp 1'b0; |
RxEn <=#Tp 1'b0; |
TxEn <=#Tp 1'b1; // wb access stage, r_RxEn is disabled but r_TxEn is enabled |
ram_addr <=#Tp {TxBDAddress, TxPointerRead}; |
ram_di <=#Tp TxBDDataIn; |
WbEn <= 1'b0; |
RxEn <= 1'b0; |
TxEn <= 1'b1; // wb access stage, r_RxEn is disabled but r_TxEn is enabled |
ram_addr <= {TxBDAddress, TxPointerRead}; |
ram_di <= TxBDDataIn; |
end |
5'b010_00, 5'b010_10 : |
begin |
WbEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is disabled |
RxEn <=#Tp 1'b0; |
TxEn <=#Tp 1'b0; |
ram_addr <=#Tp WB_ADR_I[9:2]; |
ram_di <=#Tp WB_DAT_I; |
BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}}; |
BDRead <=#Tp (|BDCs) & ~WB_WE_I; |
WbEn <= 1'b1; // RxEn access stage and r_TxEn is disabled |
RxEn <= 1'b0; |
TxEn <= 1'b0; |
ram_addr <= WB_ADR_I[9:2]; |
ram_di <= WB_DAT_I; |
BDWrite <= BDCs[3:0] & {4{WB_WE_I}}; |
BDRead <= (|BDCs) & ~WB_WE_I; |
end |
5'b010_01, 5'b010_11 : |
begin |
WbEn <=#Tp 1'b0; |
RxEn <=#Tp 1'b0; |
TxEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is enabled |
ram_addr <=#Tp {TxBDAddress, TxPointerRead}; |
ram_di <=#Tp TxBDDataIn; |
WbEn <= 1'b0; |
RxEn <= 1'b0; |
TxEn <= 1'b1; // RxEn access stage and r_TxEn is enabled |
ram_addr <= {TxBDAddress, TxPointerRead}; |
ram_di <= TxBDDataIn; |
end |
5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 : |
begin |
WbEn <=#Tp 1'b1; // TxEn access stage (we always go to wb access stage) |
RxEn <=#Tp 1'b0; |
TxEn <=#Tp 1'b0; |
ram_addr <=#Tp WB_ADR_I[9:2]; |
ram_di <=#Tp WB_DAT_I; |
BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}}; |
BDRead <=#Tp (|BDCs) & ~WB_WE_I; |
WbEn <= 1'b1; // TxEn access stage (we always go to wb access stage) |
RxEn <= 1'b0; |
TxEn <= 1'b0; |
ram_addr <= WB_ADR_I[9:2]; |
ram_di <= WB_DAT_I; |
BDWrite <= BDCs[3:0] & {4{WB_WE_I}}; |
BDRead <= (|BDCs) & ~WB_WE_I; |
end |
5'b100_00 : |
begin |
WbEn <=#Tp 1'b0; // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit |
WbEn <= 1'b0; // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit |
end |
5'b000_00 : |
begin |
WbEn <=#Tp 1'b1; // Idle state. We go to WbEn access stage. |
RxEn <=#Tp 1'b0; |
TxEn <=#Tp 1'b0; |
ram_addr <=#Tp WB_ADR_I[9:2]; |
ram_di <=#Tp WB_DAT_I; |
BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}}; |
BDRead <=#Tp (|BDCs) & ~WB_WE_I; |
WbEn <= 1'b1; // Idle state. We go to WbEn access stage. |
RxEn <= 1'b0; |
TxEn <= 1'b0; |
ram_addr <= WB_ADR_I[9:2]; |
ram_di <= WB_DAT_I; |
BDWrite <= BDCs[3:0] & {4{WB_WE_I}}; |
BDRead <= (|BDCs) & ~WB_WE_I; |
end |
endcase |
end |
675,19 → 674,19
begin |
if(Reset) |
begin |
WbEn_q <=#Tp 1'b0; |
RxEn_q <=#Tp 1'b0; |
TxEn_q <=#Tp 1'b0; |
r_TxEn_q <=#Tp 1'b0; |
r_RxEn_q <=#Tp 1'b0; |
WbEn_q <= 1'b0; |
RxEn_q <= 1'b0; |
TxEn_q <= 1'b0; |
r_TxEn_q <= 1'b0; |
r_RxEn_q <= 1'b0; |
end |
else |
begin |
WbEn_q <=#Tp WbEn; |
RxEn_q <=#Tp RxEn; |
TxEn_q <=#Tp TxEn; |
r_TxEn_q <=#Tp r_TxEn; |
r_RxEn_q <=#Tp r_RxEn; |
WbEn_q <= WbEn; |
RxEn_q <= RxEn; |
TxEn_q <= TxEn; |
r_TxEn_q <= r_TxEn; |
r_RxEn_q <= r_RxEn; |
end |
end |
|
695,13 → 694,13
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
Flop <=#Tp 1'b0; |
Flop <= 1'b0; |
else |
if(TxDone | TxAbort | TxRetry_q) |
Flop <=#Tp 1'b0; |
Flop <= 1'b0; |
else |
if(TxUsedData) |
Flop <=#Tp ~Flop; |
Flop <= ~Flop; |
end |
|
wire ResetTxBDReady; |
711,13 → 710,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxBDReady <=#Tp 1'b0; |
TxBDReady <= 1'b0; |
else |
if(TxEn & TxEn_q & TxBDRead) |
TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning. |
TxBDReady <= ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning. |
else // Only packets larger then 4 bytes are transmitted. |
if(ResetTxBDReady) |
TxBDReady <=#Tp 1'b0; |
TxBDReady <= 1'b0; |
end |
|
|
727,13 → 726,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxBDRead <=#Tp 1'b1; |
TxBDRead <= 1'b1; |
else |
if(StartTxBDRead) |
TxBDRead <=#Tp 1'b1; |
TxBDRead <= 1'b1; |
else |
if(TxBDReady) |
TxBDRead <=#Tp 1'b0; |
TxBDRead <= 1'b0; |
end |
|
|
744,13 → 743,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxPointerRead <=#Tp 1'b0; |
TxPointerRead <= 1'b0; |
else |
if(StartTxPointerRead) |
TxPointerRead <=#Tp 1'b1; |
TxPointerRead <= 1'b1; |
else |
if(TxEn_q) |
TxPointerRead <=#Tp 1'b0; |
TxPointerRead <= 1'b0; |
end |
|
|
763,13 → 762,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
BlockingTxStatusWrite <=#Tp 1'b0; |
BlockingTxStatusWrite <= 1'b0; |
else |
if(~TxDone_wb & ~TxAbort_wb) |
BlockingTxStatusWrite <=#Tp 1'b0; |
BlockingTxStatusWrite <= 1'b0; |
else |
if(TxStatusWrite) |
BlockingTxStatusWrite <=#Tp 1'b1; |
BlockingTxStatusWrite <= 1'b1; |
end |
|
|
781,9 → 780,9
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
BlockingTxStatusWrite_sync1 <=#Tp 1'b0; |
BlockingTxStatusWrite_sync1 <= 1'b0; |
else |
BlockingTxStatusWrite_sync1 <=#Tp BlockingTxStatusWrite; |
BlockingTxStatusWrite_sync1 <= BlockingTxStatusWrite; |
end |
|
// Synchronizing BlockingTxStatusWrite to MTxClk |
790,9 → 789,9
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
BlockingTxStatusWrite_sync2 <=#Tp 1'b0; |
BlockingTxStatusWrite_sync2 <= 1'b0; |
else |
BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1; |
BlockingTxStatusWrite_sync2 <= BlockingTxStatusWrite_sync1; |
end |
|
// Synchronizing BlockingTxStatusWrite to MTxClk |
799,9 → 798,9
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
BlockingTxStatusWrite_sync3 <=#Tp 1'b0; |
BlockingTxStatusWrite_sync3 <= 1'b0; |
else |
BlockingTxStatusWrite_sync3 <=#Tp BlockingTxStatusWrite_sync2; |
BlockingTxStatusWrite_sync3 <= BlockingTxStatusWrite_sync2; |
end |
|
assign RstDeferLatched = BlockingTxStatusWrite_sync2 & ~BlockingTxStatusWrite_sync3; |
810,13 → 809,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
BlockingTxBDRead <=#Tp 1'b0; |
BlockingTxBDRead <= 1'b0; |
else |
if(StartTxBDRead) |
BlockingTxBDRead <=#Tp 1'b1; |
BlockingTxBDRead <= 1'b1; |
else |
if(~StartTxBDRead & ~TxBDReady) |
BlockingTxBDRead <=#Tp 1'b0; |
BlockingTxBDRead <= 1'b0; |
end |
|
|
825,10 → 824,10
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxStatus <=#Tp 4'h0; |
TxStatus <= 4'h0; |
else |
if(TxEn & TxEn_q & TxBDRead) |
TxStatus <=#Tp ram_do[14:11]; |
TxStatus <= ram_do[14:11]; |
end |
|
reg ReadTxDataFromMemory; |
861,27 → 860,27
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxLength <=#Tp 16'h0; |
TxLength <= 16'h0; |
else |
if(TxEn & TxEn_q & TxBDRead) |
TxLength <=#Tp ram_do[31:16]; |
TxLength <= ram_do[31:16]; |
else |
if(MasterWbTX & m_wb_ack_i) |
begin |
if(TxLengthLt4) |
TxLength <=#Tp 16'h0; |
TxLength <= 16'h0; |
else |
if(TxPointerLSB_rst==2'h0) |
TxLength <=#Tp TxLength - 3'h4; // Length is subtracted at the data request |
TxLength <= TxLength - 3'h4; // Length is subtracted at the data request |
else |
if(TxPointerLSB_rst==2'h1) |
TxLength <=#Tp TxLength - 3'h3; // Length is subtracted at the data request |
TxLength <= TxLength - 3'h3; // Length is subtracted at the data request |
else |
if(TxPointerLSB_rst==2'h2) |
TxLength <=#Tp TxLength - 3'h2; // Length is subtracted at the data request |
TxLength <= TxLength - 3'h2; // Length is subtracted at the data request |
else |
if(TxPointerLSB_rst==2'h3) |
TxLength <=#Tp TxLength - 3'h1; // Length is subtracted at the data request |
TxLength <= TxLength - 3'h1; // Length is subtracted at the data request |
end |
end |
|
891,10 → 890,10
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
LatchedTxLength <=#Tp 16'h0; |
LatchedTxLength <= 16'h0; |
else |
if(TxEn & TxEn_q & TxBDRead) |
LatchedTxLength <=#Tp ram_do[31:16]; |
LatchedTxLength <= ram_do[31:16]; |
end |
|
assign TxLengthEq0 = TxLength == 0; |
909,13 → 908,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxPointerMSB <=#Tp 30'h0; |
TxPointerMSB <= 30'h0; |
else |
if(TxEn & TxEn_q & TxPointerRead) |
TxPointerMSB <=#Tp ram_do[31:2]; |
TxPointerMSB <= ram_do[31:2]; |
else |
if(IncrTxPointer & ~BlockingIncrementTxPointer) |
TxPointerMSB <=#Tp TxPointerMSB + 1'b1; // TxPointer is word-aligned |
TxPointerMSB <= TxPointerMSB + 1'b1; // TxPointer is word-aligned |
end |
|
|
926,10 → 925,10
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxPointerLSB[1:0] <=#Tp 0; |
TxPointerLSB[1:0] <= 0; |
else |
if(TxEn & TxEn_q & TxPointerRead) |
TxPointerLSB[1:0] <=#Tp ram_do[1:0]; |
TxPointerLSB[1:0] <= ram_do[1:0]; |
end |
|
|
940,13 → 939,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxPointerLSB_rst[1:0] <=#Tp 0; |
TxPointerLSB_rst[1:0] <= 0; |
else |
if(TxEn & TxEn_q & TxPointerRead) |
TxPointerLSB_rst[1:0] <=#Tp ram_do[1:0]; |
TxPointerLSB_rst[1:0] <= ram_do[1:0]; |
else |
if(MasterWbTX & m_wb_ack_i) // After first access pointer is word alligned |
TxPointerLSB_rst[1:0] <=#Tp 0; |
TxPointerLSB_rst[1:0] <= 0; |
end |
|
|
957,13 → 956,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
BlockingIncrementTxPointer <=#Tp 0; |
BlockingIncrementTxPointer <= 0; |
else |
if(MasterAccessFinished) |
BlockingIncrementTxPointer <=#Tp 0; |
BlockingIncrementTxPointer <= 0; |
else |
if(IncrTxPointer) |
BlockingIncrementTxPointer <=#Tp 1'b1; |
BlockingIncrementTxPointer <= 1'b1; |
end |
|
|
980,13 → 979,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromMemory <=#Tp 1'b0; |
ReadTxDataFromMemory <= 1'b0; |
else |
if(TxLengthEq0 | TxAbortPulse | TxRetryPulse) |
ReadTxDataFromMemory <=#Tp 1'b0; |
ReadTxDataFromMemory <= 1'b0; |
else |
if(SetReadTxDataFromMemory) |
ReadTxDataFromMemory <=#Tp 1'b1; |
ReadTxDataFromMemory <= 1'b1; |
end |
|
reg tx_burst_en; |
1001,13 → 1000,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
BlockReadTxDataFromMemory <=#Tp 1'b0; |
BlockReadTxDataFromMemory <= 1'b0; |
else |
if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (~cyc_cleared) & (!(TxAbortPacket_NotCleared | TxRetryPacket_NotCleared))) |
BlockReadTxDataFromMemory <=#Tp 1'b1; |
BlockReadTxDataFromMemory <= 1'b1; |
else |
if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket) |
BlockReadTxDataFromMemory <=#Tp 1'b0; |
BlockReadTxDataFromMemory <= 1'b0; |
end |
|
|
1026,20 → 1025,20
begin |
if(Reset) |
begin |
MasterWbTX <=#Tp 1'b0; |
MasterWbRX <=#Tp 1'b0; |
m_wb_adr_o <=#Tp 30'h0; |
m_wb_cyc_o <=#Tp 1'b0; |
m_wb_we_o <=#Tp 1'b0; |
m_wb_sel_o <=#Tp 4'h0; |
cyc_cleared<=#Tp 1'b0; |
tx_burst_cnt<=#Tp 0; |
rx_burst_cnt<=#Tp 0; |
IncrTxPointer<=#Tp 1'b0; |
tx_burst_en<=#Tp 1'b1; |
rx_burst_en<=#Tp 1'b0; |
MasterWbTX <= 1'b0; |
MasterWbRX <= 1'b0; |
m_wb_adr_o <= 30'h0; |
m_wb_cyc_o <= 1'b0; |
m_wb_we_o <= 1'b0; |
m_wb_sel_o <= 4'h0; |
cyc_cleared<= 1'b0; |
tx_burst_cnt<= 0; |
rx_burst_cnt<= 0; |
IncrTxPointer<= 1'b0; |
tx_burst_en<= 1'b1; |
rx_burst_en<= 1'b0; |
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o <=#Tp 3'b0; |
m_wb_cti_o <= 3'b0; |
`endif |
end |
else |
1051,30 → 1050,30
8'b10_10_01_10, // Clear (previously MR) and MRB needed |
8'b01_1x_01_1x : // Clear (previously MW) and MRB needed |
begin |
MasterWbTX <=#Tp 1'b1; // tx burst |
MasterWbRX <=#Tp 1'b0; |
m_wb_cyc_o <=#Tp 1'b1; |
m_wb_we_o <=#Tp 1'b0; |
m_wb_sel_o <=#Tp 4'hf; |
cyc_cleared<=#Tp 1'b0; |
IncrTxPointer<=#Tp 1'b1; |
tx_burst_cnt <=#Tp tx_burst_cnt+3'h1; |
MasterWbTX <= 1'b1; // tx burst |
MasterWbRX <= 1'b0; |
m_wb_cyc_o <= 1'b1; |
m_wb_we_o <= 1'b0; |
m_wb_sel_o <= 4'hf; |
cyc_cleared<= 1'b0; |
IncrTxPointer<= 1'b1; |
tx_burst_cnt <= tx_burst_cnt+3'h1; |
if(tx_burst_cnt==0) |
m_wb_adr_o <=#Tp TxPointerMSB; |
m_wb_adr_o <= TxPointerMSB; |
else |
m_wb_adr_o <=#Tp m_wb_adr_o+1'b1; |
m_wb_adr_o <= m_wb_adr_o+1'b1; |
|
if(tx_burst_cnt==(`ETH_BURST_LENGTH-1)) |
begin |
tx_burst_en<=#Tp 1'b0; |
tx_burst_en<= 1'b0; |
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o <=#Tp 3'b111; |
m_wb_cti_o <= 3'b111; |
`endif |
end |
else |
begin |
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o <=#Tp 3'b010; |
m_wb_cti_o <= 3'b010; |
`endif |
end |
end |
1083,77 → 1082,77
8'b01_01_01_01, // Clear (previously MW) and MWB needed |
8'b10_x1_01_x1 : // Clear (previously MR) and MWB needed |
begin |
MasterWbTX <=#Tp 1'b0; // rx burst |
MasterWbRX <=#Tp 1'b1; |
m_wb_cyc_o <=#Tp 1'b1; |
m_wb_we_o <=#Tp 1'b1; |
m_wb_sel_o <=#Tp RxByteSel; |
IncrTxPointer<=#Tp 1'b0; |
cyc_cleared<=#Tp 1'b0; |
rx_burst_cnt <=#Tp rx_burst_cnt+3'h1; |
MasterWbTX <= 1'b0; // rx burst |
MasterWbRX <= 1'b1; |
m_wb_cyc_o <= 1'b1; |
m_wb_we_o <= 1'b1; |
m_wb_sel_o <= RxByteSel; |
IncrTxPointer<= 1'b0; |
cyc_cleared<= 1'b0; |
rx_burst_cnt <= rx_burst_cnt+3'h1; |
|
if(rx_burst_cnt==0) |
m_wb_adr_o <=#Tp RxPointerMSB; |
m_wb_adr_o <= RxPointerMSB; |
else |
m_wb_adr_o <=#Tp m_wb_adr_o+1'b1; |
m_wb_adr_o <= m_wb_adr_o+1'b1; |
|
if(rx_burst_cnt==(`ETH_BURST_LENGTH-1)) |
begin |
rx_burst_en<=#Tp 1'b0; |
rx_burst_en<= 1'b0; |
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o <=#Tp 3'b111; |
m_wb_cti_o <= 3'b111; |
`endif |
end |
else |
begin |
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o <=#Tp 3'b010; |
m_wb_cti_o <= 3'b010; |
`endif |
end |
end |
8'b00_x1_00_x0 : // idle and MW is needed (data write to rx buffer) |
begin |
MasterWbTX <=#Tp 1'b0; |
MasterWbRX <=#Tp 1'b1; |
m_wb_adr_o <=#Tp RxPointerMSB; |
m_wb_cyc_o <=#Tp 1'b1; |
m_wb_we_o <=#Tp 1'b1; |
m_wb_sel_o <=#Tp RxByteSel; |
IncrTxPointer<=#Tp 1'b0; |
MasterWbTX <= 1'b0; |
MasterWbRX <= 1'b1; |
m_wb_adr_o <= RxPointerMSB; |
m_wb_cyc_o <= 1'b1; |
m_wb_we_o <= 1'b1; |
m_wb_sel_o <= RxByteSel; |
IncrTxPointer<= 1'b0; |
end |
8'b00_10_00_00 : // idle and MR is needed (data read from tx buffer) |
begin |
MasterWbTX <=#Tp 1'b1; |
MasterWbRX <=#Tp 1'b0; |
m_wb_adr_o <=#Tp TxPointerMSB; |
m_wb_cyc_o <=#Tp 1'b1; |
m_wb_we_o <=#Tp 1'b0; |
m_wb_sel_o <=#Tp 4'hf; |
IncrTxPointer<=#Tp 1'b1; |
MasterWbTX <= 1'b1; |
MasterWbRX <= 1'b0; |
m_wb_adr_o <= TxPointerMSB; |
m_wb_cyc_o <= 1'b1; |
m_wb_we_o <= 1'b0; |
m_wb_sel_o <= 4'hf; |
IncrTxPointer<= 1'b1; |
end |
8'b10_10_01_00, // MR and MR is needed (data read from tx buffer) |
8'b01_1x_01_0x : // MW and MR is needed (data read from tx buffer) |
begin |
MasterWbTX <=#Tp 1'b1; |
MasterWbRX <=#Tp 1'b0; |
m_wb_adr_o <=#Tp TxPointerMSB; |
m_wb_cyc_o <=#Tp 1'b1; |
m_wb_we_o <=#Tp 1'b0; |
m_wb_sel_o <=#Tp 4'hf; |
cyc_cleared<=#Tp 1'b0; |
IncrTxPointer<=#Tp 1'b1; |
MasterWbTX <= 1'b1; |
MasterWbRX <= 1'b0; |
m_wb_adr_o <= TxPointerMSB; |
m_wb_cyc_o <= 1'b1; |
m_wb_we_o <= 1'b0; |
m_wb_sel_o <= 4'hf; |
cyc_cleared<= 1'b0; |
IncrTxPointer<= 1'b1; |
end |
8'b01_01_01_00, // MW and MW needed (data write to rx buffer) |
8'b10_x1_01_x0 : // MR and MW is needed (data write to rx buffer) |
begin |
MasterWbTX <=#Tp 1'b0; |
MasterWbRX <=#Tp 1'b1; |
m_wb_adr_o <=#Tp RxPointerMSB; |
m_wb_cyc_o <=#Tp 1'b1; |
m_wb_we_o <=#Tp 1'b1; |
m_wb_sel_o <=#Tp RxByteSel; |
cyc_cleared<=#Tp 1'b0; |
IncrTxPointer<=#Tp 1'b0; |
MasterWbTX <= 1'b0; |
MasterWbRX <= 1'b1; |
m_wb_adr_o <= RxPointerMSB; |
m_wb_cyc_o <= 1'b1; |
m_wb_we_o <= 1'b1; |
m_wb_sel_o <= RxByteSel; |
cyc_cleared<= 1'b0; |
IncrTxPointer<= 1'b0; |
end |
8'b01_01_10_00, // MW and MW needed (cycle is cleared between previous and next access) |
8'b01_1x_10_x0, // MW and MW or MR or MRB needed (cycle is cleared between previous and next access) |
1160,43 → 1159,43
8'b10_10_10_00, // MR and MR needed (cycle is cleared between previous and next access) |
8'b10_x1_10_0x : // MR and MR or MW or MWB (cycle is cleared between previous and next access) |
begin |
m_wb_cyc_o <=#Tp 1'b0; // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started |
cyc_cleared<=#Tp 1'b1; |
IncrTxPointer<=#Tp 1'b0; |
tx_burst_cnt<=#Tp 0; |
tx_burst_en<=#Tp txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4)); |
rx_burst_cnt<=#Tp 0; |
rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used. |
m_wb_cyc_o <= 1'b0; // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started |
cyc_cleared<= 1'b1; |
IncrTxPointer<= 1'b0; |
tx_burst_cnt<= 0; |
tx_burst_en<= txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4)); |
rx_burst_cnt<= 0; |
rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used. |
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o <=#Tp 3'b0; |
m_wb_cti_o <= 3'b0; |
`endif |
end |
8'bxx_00_10_00, // whatever and no master read or write is needed (ack or err comes finishing previous access) |
8'bxx_00_01_00 : // Between cyc_cleared request was cleared |
begin |
MasterWbTX <=#Tp 1'b0; |
MasterWbRX <=#Tp 1'b0; |
m_wb_cyc_o <=#Tp 1'b0; |
cyc_cleared<=#Tp 1'b0; |
IncrTxPointer<=#Tp 1'b0; |
rx_burst_cnt<=#Tp 0; |
rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used. |
MasterWbTX <= 1'b0; |
MasterWbRX <= 1'b0; |
m_wb_cyc_o <= 1'b0; |
cyc_cleared<= 1'b0; |
IncrTxPointer<= 1'b0; |
rx_burst_cnt<= 0; |
rx_burst_en<= MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used. |
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o <=#Tp 3'b0; |
m_wb_cti_o <= 3'b0; |
`endif |
end |
8'b00_00_00_00: // whatever and no master read or write is needed (ack or err comes finishing previous access) |
begin |
tx_burst_cnt<=#Tp 0; |
tx_burst_en<=#Tp txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4)); |
tx_burst_cnt<= 0; |
tx_burst_en<= txfifo_cnt<(TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4)); |
end |
default: // Don't touch |
begin |
MasterWbTX <=#Tp MasterWbTX; |
MasterWbRX <=#Tp MasterWbRX; |
m_wb_cyc_o <=#Tp m_wb_cyc_o; |
m_wb_sel_o <=#Tp m_wb_sel_o; |
IncrTxPointer<=#Tp IncrTxPointer; |
MasterWbTX <= MasterWbTX; |
MasterWbRX <= MasterWbRX; |
m_wb_cyc_o <= m_wb_cyc_o; |
m_wb_sel_o <= m_wb_sel_o; |
IncrTxPointer<= IncrTxPointer; |
end |
endcase |
end |
1209,8 → 1208,7
|
eth_fifo #(.DATA_WIDTH(TX_FIFO_DATA_WIDTH), |
.DEPTH(TX_FIFO_DEPTH), |
.CNT_WIDTH(TX_FIFO_CNT_WIDTH), |
.Tp(Tp)) |
.CNT_WIDTH(TX_FIFO_CNT_WIDTH)) |
tx_fifo ( .data_in(m_wb_dat_i), .data_out(TxData_wb), |
.clk(WB_CLK_I), .reset(Reset), |
.write(MasterWbTX & m_wb_ack_i), .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty), |
1232,13 → 1230,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxStartFrm_wb <=#Tp 1'b0; |
TxStartFrm_wb <= 1'b0; |
else |
if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0)) |
TxStartFrm_wb <=#Tp 1'b1; |
TxStartFrm_wb <= 1'b1; |
else |
if(TxStartFrm_syncb2) |
TxStartFrm_wb <=#Tp 1'b0; |
TxStartFrm_wb <= 1'b0; |
end |
|
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked. |
1245,13 → 1243,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
StartOccured <=#Tp 1'b0; |
StartOccured <= 1'b0; |
else |
if(TxStartFrm_wb) |
StartOccured <=#Tp 1'b1; |
StartOccured <= 1'b1; |
else |
if(ResetTxBDReady) |
StartOccured <=#Tp 1'b0; |
StartOccured <= 1'b0; |
end |
|
// Synchronizing TxStartFrm_wb to MTxClk |
1258,45 → 1256,45
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxStartFrm_sync1 <=#Tp 1'b0; |
TxStartFrm_sync1 <= 1'b0; |
else |
TxStartFrm_sync1 <=#Tp TxStartFrm_wb; |
TxStartFrm_sync1 <= TxStartFrm_wb; |
end |
|
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxStartFrm_sync2 <=#Tp 1'b0; |
TxStartFrm_sync2 <= 1'b0; |
else |
TxStartFrm_sync2 <=#Tp TxStartFrm_sync1; |
TxStartFrm_sync2 <= TxStartFrm_sync1; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxStartFrm_syncb1 <=#Tp 1'b0; |
TxStartFrm_syncb1 <= 1'b0; |
else |
TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2; |
TxStartFrm_syncb1 <= TxStartFrm_sync2; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxStartFrm_syncb2 <=#Tp 1'b0; |
TxStartFrm_syncb2 <= 1'b0; |
else |
TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1; |
TxStartFrm_syncb2 <= TxStartFrm_syncb1; |
end |
|
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxStartFrm <=#Tp 1'b0; |
TxStartFrm <= 1'b0; |
else |
if(TxStartFrm_sync2) |
TxStartFrm <=#Tp 1'b1; |
TxStartFrm <= 1'b1; |
else |
if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q))) |
TxStartFrm <=#Tp 1'b0; |
TxStartFrm <= 1'b0; |
end |
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk |
|
1305,13 → 1303,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxEndFrm_wb <=#Tp 1'b0; |
TxEndFrm_wb <= 1'b0; |
else |
if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData) |
TxEndFrm_wb <=#Tp 1'b1; |
TxEndFrm_wb <= 1'b1; |
else |
if(TxRetryPulse | TxDonePulse | TxAbortPulse) |
TxEndFrm_wb <=#Tp 1'b0; |
TxEndFrm_wb <= 1'b0; |
end |
|
|
1324,20 → 1322,20
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
LatchValidBytes <=#Tp 1'b0; |
LatchValidBytes <= 1'b0; |
else |
if(TxLengthLt4 & TxBDReady) |
LatchValidBytes <=#Tp 1'b1; |
LatchValidBytes <= 1'b1; |
else |
LatchValidBytes <=#Tp 1'b0; |
LatchValidBytes <= 1'b0; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
LatchValidBytes_q <=#Tp 1'b0; |
LatchValidBytes_q <= 1'b0; |
else |
LatchValidBytes_q <=#Tp LatchValidBytes; |
LatchValidBytes_q <= LatchValidBytes; |
end |
|
|
1345,13 → 1343,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxValidBytesLatched <=#Tp 2'h0; |
TxValidBytesLatched <= 2'h0; |
else |
if(LatchValidBytes & ~LatchValidBytes_q) |
TxValidBytesLatched <=#Tp TxValidBytes; |
TxValidBytesLatched <= TxValidBytes; |
else |
if(TxRetryPulse | TxDonePulse | TxAbortPulse) |
TxValidBytesLatched <=#Tp 2'h0; |
TxValidBytesLatched <= 2'h0; |
end |
|
|
1375,11 → 1373,11
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxBDAddress <=#Tp 7'h0; |
TxBDAddress <= 7'h0; |
else if (r_TxEn & (~r_TxEn_q)) |
TxBDAddress <=#Tp 7'h0; |
TxBDAddress <= 7'h0; |
else if (TxStatusWrite) |
TxBDAddress <=#Tp TempTxBDAddress; |
TxBDAddress <= TempTxBDAddress; |
end |
|
|
1387,11 → 1385,11
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxBDAddress <=#Tp 7'h0; |
RxBDAddress <= 7'h0; |
else if(r_RxEn & (~r_RxEn_q)) |
RxBDAddress <=#Tp r_TxBDNum[6:0]; |
RxBDAddress <= r_TxBDNum[6:0]; |
else if(RxStatusWrite) |
RxBDAddress <=#Tp TempRxBDAddress; |
RxBDAddress <= TempRxBDAddress; |
end |
|
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost}; |
1412,15 → 1410,15
begin |
if(Reset) |
begin |
TxAbort_q <=#Tp 1'b0; |
TxRetry_q <=#Tp 1'b0; |
TxUsedData_q <=#Tp 1'b0; |
TxAbort_q <= 1'b0; |
TxRetry_q <= 1'b0; |
TxUsedData_q <= 1'b0; |
end |
else |
begin |
TxAbort_q <=#Tp TxAbort; |
TxRetry_q <=#Tp TxRetry; |
TxUsedData_q <=#Tp TxUsedData; |
TxAbort_q <= TxAbort; |
TxRetry_q <= TxRetry; |
TxUsedData_q <= TxUsedData; |
end |
end |
|
1429,15 → 1427,15
begin |
if(Reset) |
begin |
TxDone_wb_q <=#Tp 1'b0; |
TxAbort_wb_q <=#Tp 1'b0; |
TxRetry_wb_q <=#Tp 1'b0; |
TxDone_wb_q <= 1'b0; |
TxAbort_wb_q <= 1'b0; |
TxRetry_wb_q <= 1'b0; |
end |
else |
begin |
TxDone_wb_q <=#Tp TxDone_wb; |
TxAbort_wb_q <=#Tp TxAbort_wb; |
TxRetry_wb_q <=#Tp TxRetry_wb; |
TxDone_wb_q <= TxDone_wb; |
TxAbort_wb_q <= TxAbort_wb; |
TxRetry_wb_q <= TxRetry_wb; |
end |
end |
|
1446,13 → 1444,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxAbortPacket <=#Tp 1'b0; |
TxAbortPacket <= 1'b0; |
else |
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) | |
TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked)) |
TxAbortPacket <=#Tp 1'b1; |
TxAbortPacket <= 1'b1; |
else |
TxAbortPacket <=#Tp 1'b0; |
TxAbortPacket <= 1'b0; |
end |
|
|
1459,14 → 1457,14
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxAbortPacket_NotCleared <=#Tp 1'b0; |
TxAbortPacket_NotCleared <= 1'b0; |
else |
if(TxEn & TxEn_q & TxAbortPacket_NotCleared) |
TxAbortPacket_NotCleared <=#Tp 1'b0; |
TxAbortPacket_NotCleared <= 1'b0; |
else |
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) | |
TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked)) |
TxAbortPacket_NotCleared <=#Tp 1'b1; |
TxAbortPacket_NotCleared <= 1'b1; |
end |
|
|
1473,13 → 1471,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxAbortPacketBlocked <=#Tp 1'b0; |
TxAbortPacketBlocked <= 1'b0; |
else |
if(!TxAbort_wb & TxAbort_wb_q) |
TxAbortPacketBlocked <=#Tp 1'b0; |
TxAbortPacketBlocked <= 1'b0; |
else |
if(TxAbortPacket) |
TxAbortPacketBlocked <=#Tp 1'b1; |
TxAbortPacketBlocked <= 1'b1; |
end |
|
|
1487,13 → 1485,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxRetryPacket <=#Tp 1'b0; |
TxRetryPacket <= 1'b0; |
else |
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked | |
TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked) |
TxRetryPacket <=#Tp 1'b1; |
TxRetryPacket <= 1'b1; |
else |
TxRetryPacket <=#Tp 1'b0; |
TxRetryPacket <= 1'b0; |
end |
|
|
1500,14 → 1498,14
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxRetryPacket_NotCleared <=#Tp 1'b0; |
TxRetryPacket_NotCleared <= 1'b0; |
else |
if(StartTxBDRead) |
TxRetryPacket_NotCleared <=#Tp 1'b0; |
TxRetryPacket_NotCleared <= 1'b0; |
else |
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked | |
TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked) |
TxRetryPacket_NotCleared <=#Tp 1'b1; |
TxRetryPacket_NotCleared <= 1'b1; |
end |
|
|
1514,13 → 1512,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxRetryPacketBlocked <=#Tp 1'b0; |
TxRetryPacketBlocked <= 1'b0; |
else |
if(!TxRetry_wb & TxRetry_wb_q) |
TxRetryPacketBlocked <=#Tp 1'b0; |
TxRetryPacketBlocked <= 1'b0; |
else |
if(TxRetryPacket) |
TxRetryPacketBlocked <=#Tp 1'b1; |
TxRetryPacketBlocked <= 1'b1; |
end |
|
|
1528,13 → 1526,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxDonePacket <=#Tp 1'b0; |
TxDonePacket <= 1'b0; |
else |
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxDonePacketBlocked | |
TxDone_wb & !MasterWbTX & !TxDonePacketBlocked) |
TxDonePacket <=#Tp 1'b1; |
TxDonePacket <= 1'b1; |
else |
TxDonePacket <=#Tp 1'b0; |
TxDonePacket <= 1'b0; |
end |
|
|
1541,14 → 1539,14
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxDonePacket_NotCleared <=#Tp 1'b0; |
TxDonePacket_NotCleared <= 1'b0; |
else |
if(TxEn & TxEn_q & TxDonePacket_NotCleared) |
TxDonePacket_NotCleared <=#Tp 1'b0; |
TxDonePacket_NotCleared <= 1'b0; |
else |
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & (~TxDonePacketBlocked) | |
TxDone_wb & !MasterWbTX & (~TxDonePacketBlocked)) |
TxDonePacket_NotCleared <=#Tp 1'b1; |
TxDonePacket_NotCleared <= 1'b1; |
end |
|
|
1555,13 → 1553,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxDonePacketBlocked <=#Tp 1'b0; |
TxDonePacketBlocked <= 1'b0; |
else |
if(!TxDone_wb & TxDone_wb_q) |
TxDonePacketBlocked <=#Tp 1'b0; |
TxDonePacketBlocked <= 1'b0; |
else |
if(TxDonePacket) |
TxDonePacketBlocked <=#Tp 1'b1; |
TxDonePacketBlocked <= 1'b1; |
end |
|
|
1569,13 → 1567,13
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
LastWord <=#Tp 1'b0; |
LastWord <= 1'b0; |
else |
if((TxEndFrm | TxAbort | TxRetry) & Flop) |
LastWord <=#Tp 1'b0; |
LastWord <= 1'b0; |
else |
if(TxUsedData & Flop & TxByteCnt == 2'h3) |
LastWord <=#Tp TxEndFrm_wb; |
LastWord <= TxEndFrm_wb; |
end |
|
|
1583,19 → 1581,19
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxEndFrm <=#Tp 1'b0; |
TxEndFrm <= 1'b0; |
else |
if(Flop & TxEndFrm | TxAbort | TxRetry_q) |
TxEndFrm <=#Tp 1'b0; |
TxEndFrm <= 1'b0; |
else |
if(Flop & LastWord) |
begin |
case (TxValidBytesLatched) // synopsys parallel_case |
1 : TxEndFrm <=#Tp TxByteCnt == 2'h0; |
2 : TxEndFrm <=#Tp TxByteCnt == 2'h1; |
3 : TxEndFrm <=#Tp TxByteCnt == 2'h2; |
0 : TxEndFrm <=#Tp TxByteCnt == 2'h3; |
default : TxEndFrm <=#Tp 1'b0; |
1 : TxEndFrm <= TxByteCnt == 2'h0; |
2 : TxEndFrm <= TxByteCnt == 2'h1; |
3 : TxEndFrm <= TxByteCnt == 2'h2; |
0 : TxEndFrm <= TxByteCnt == 2'h3; |
default : TxEndFrm <= 1'b0; |
endcase |
end |
end |
1605,26 → 1603,26
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxData <=#Tp 0; |
TxData <= 0; |
else |
if(TxStartFrm_sync2 & ~TxStartFrm) |
case(TxPointerLSB) // synopsys parallel_case |
2'h0 : TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering |
2'h1 : TxData <=#Tp TxData_wb[23:16]; // Big Endian Byte Ordering |
2'h2 : TxData <=#Tp TxData_wb[15:08]; // Big Endian Byte Ordering |
2'h3 : TxData <=#Tp TxData_wb[07:00]; // Big Endian Byte Ordering |
2'h0 : TxData <= TxData_wb[31:24]; // Big Endian Byte Ordering |
2'h1 : TxData <= TxData_wb[23:16]; // Big Endian Byte Ordering |
2'h2 : TxData <= TxData_wb[15:08]; // Big Endian Byte Ordering |
2'h3 : TxData <= TxData_wb[07:00]; // Big Endian Byte Ordering |
endcase |
else |
if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3) |
TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering |
TxData <= TxData_wb[31:24]; // Big Endian Byte Ordering |
else |
if(TxUsedData & Flop) |
begin |
case(TxByteCnt) // synopsys parallel_case |
0 : TxData <=#Tp TxDataLatched[31:24]; // Big Endian Byte Ordering |
1 : TxData <=#Tp TxDataLatched[23:16]; |
2 : TxData <=#Tp TxDataLatched[15:8]; |
3 : TxData <=#Tp TxDataLatched[7:0]; |
0 : TxData <= TxDataLatched[31:24]; // Big Endian Byte Ordering |
1 : TxData <= TxDataLatched[23:16]; |
2 : TxData <= TxDataLatched[15:8]; |
3 : TxData <= TxDataLatched[7:0]; |
endcase |
end |
end |
1634,10 → 1632,10
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxDataLatched[31:0] <=#Tp 32'h0; |
TxDataLatched[31:0] <= 32'h0; |
else |
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0) |
TxDataLatched[31:0] <=#Tp TxData_wb[31:0]; |
TxDataLatched[31:0] <= TxData_wb[31:0]; |
end |
|
|
1645,13 → 1643,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxUnderRun_wb <=#Tp 1'b0; |
TxUnderRun_wb <= 1'b0; |
else |
if(TxAbortPulse) |
TxUnderRun_wb <=#Tp 1'b0; |
TxUnderRun_wb <= 1'b0; |
else |
if(TxBufferEmpty & ReadTxDataFromFifo_wb) |
TxUnderRun_wb <=#Tp 1'b1; |
TxUnderRun_wb <= 1'b1; |
end |
|
|
1661,13 → 1659,13
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxUnderRun_sync1 <=#Tp 1'b0; |
TxUnderRun_sync1 <= 1'b0; |
else |
if(TxUnderRun_wb) |
TxUnderRun_sync1 <=#Tp 1'b1; |
TxUnderRun_sync1 <= 1'b1; |
else |
if(BlockingTxStatusWrite_sync2) |
TxUnderRun_sync1 <=#Tp 1'b0; |
TxUnderRun_sync1 <= 1'b0; |
end |
|
// Tx under run |
1674,13 → 1672,13
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxUnderRun <=#Tp 1'b0; |
TxUnderRun <= 1'b0; |
else |
if(BlockingTxStatusWrite_sync2) |
TxUnderRun <=#Tp 1'b0; |
TxUnderRun <= 1'b0; |
else |
if(TxUnderRun_sync1) |
TxUnderRun <=#Tp 1'b1; |
TxUnderRun <= 1'b1; |
end |
|
|
1688,21 → 1686,21
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxByteCnt <=#Tp 2'h0; |
TxByteCnt <= 2'h0; |
else |
if(TxAbort_q | TxRetry_q) |
TxByteCnt <=#Tp 2'h0; |
TxByteCnt <= 2'h0; |
else |
if(TxStartFrm & ~TxUsedData) |
case(TxPointerLSB) // synopsys parallel_case |
2'h0 : TxByteCnt <=#Tp 2'h1; |
2'h1 : TxByteCnt <=#Tp 2'h2; |
2'h2 : TxByteCnt <=#Tp 2'h3; |
2'h3 : TxByteCnt <=#Tp 2'h0; |
2'h0 : TxByteCnt <= 2'h1; |
2'h1 : TxByteCnt <= 2'h2; |
2'h2 : TxByteCnt <= 2'h3; |
2'h3 : TxByteCnt <= 2'h0; |
endcase |
else |
if(TxUsedData & Flop) |
TxByteCnt <=#Tp TxByteCnt + 1'b1; |
TxByteCnt <= TxByteCnt + 1'b1; |
end |
|
|
1718,13 → 1716,13
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromFifo_tck <=#Tp 1'b0; |
ReadTxDataFromFifo_tck <= 1'b0; |
else |
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0) |
ReadTxDataFromFifo_tck <=#Tp 1'b1; |
ReadTxDataFromFifo_tck <= 1'b1; |
else |
if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3) |
ReadTxDataFromFifo_tck <=#Tp 1'b0; |
ReadTxDataFromFifo_tck <= 1'b0; |
end |
|
// Synchronizing TxStartFrm_wb to MTxClk |
1731,49 → 1729,49
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromFifo_sync1 <=#Tp 1'b0; |
ReadTxDataFromFifo_sync1 <= 1'b0; |
else |
ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck; |
ReadTxDataFromFifo_sync1 <= ReadTxDataFromFifo_tck; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromFifo_sync2 <=#Tp 1'b0; |
ReadTxDataFromFifo_sync2 <= 1'b0; |
else |
ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1; |
ReadTxDataFromFifo_sync2 <= ReadTxDataFromFifo_sync1; |
end |
|
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromFifo_syncb1 <=#Tp 1'b0; |
ReadTxDataFromFifo_syncb1 <= 1'b0; |
else |
ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2; |
ReadTxDataFromFifo_syncb1 <= ReadTxDataFromFifo_sync2; |
end |
|
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromFifo_syncb2 <=#Tp 1'b0; |
ReadTxDataFromFifo_syncb2 <= 1'b0; |
else |
ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1; |
ReadTxDataFromFifo_syncb2 <= ReadTxDataFromFifo_syncb1; |
end |
|
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromFifo_syncb3 <=#Tp 1'b0; |
ReadTxDataFromFifo_syncb3 <= 1'b0; |
else |
ReadTxDataFromFifo_syncb3 <=#Tp ReadTxDataFromFifo_syncb2; |
ReadTxDataFromFifo_syncb3 <= ReadTxDataFromFifo_syncb2; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromFifo_sync3 <=#Tp 1'b0; |
ReadTxDataFromFifo_sync3 <= 1'b0; |
else |
ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2; |
ReadTxDataFromFifo_sync3 <= ReadTxDataFromFifo_sync2; |
end |
|
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3; |
1784,17 → 1782,17
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxRetrySync1 <=#Tp 1'b0; |
TxRetrySync1 <= 1'b0; |
else |
TxRetrySync1 <=#Tp TxRetry; |
TxRetrySync1 <= TxRetry; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxRetry_wb <=#Tp 1'b0; |
TxRetry_wb <= 1'b0; |
else |
TxRetry_wb <=#Tp TxRetrySync1; |
TxRetry_wb <= TxRetrySync1; |
end |
|
|
1802,17 → 1800,17
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxDoneSync1 <=#Tp 1'b0; |
TxDoneSync1 <= 1'b0; |
else |
TxDoneSync1 <=#Tp TxDone; |
TxDoneSync1 <= TxDone; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxDone_wb <=#Tp 1'b0; |
TxDone_wb <= 1'b0; |
else |
TxDone_wb <=#Tp TxDoneSync1; |
TxDone_wb <= TxDoneSync1; |
end |
|
// Synchronizing TxAbort signal (synchronized to WISHBONE clock) |
1819,17 → 1817,17
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxAbortSync1 <=#Tp 1'b0; |
TxAbortSync1 <= 1'b0; |
else |
TxAbortSync1 <=#Tp TxAbort; |
TxAbortSync1 <= TxAbort; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxAbort_wb <=#Tp 1'b0; |
TxAbort_wb <= 1'b0; |
else |
TxAbort_wb <=#Tp TxAbortSync1; |
TxAbort_wb <= TxAbortSync1; |
end |
|
|
1846,13 → 1844,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxBDRead <=#Tp 1'b0; |
RxBDRead <= 1'b0; |
else |
if(StartRxBDRead & ~RxReady) |
RxBDRead <=#Tp 1'b1; |
RxBDRead <= 1'b1; |
else |
if(RxBDReady) |
RxBDRead <=#Tp 1'b0; |
RxBDRead <= 1'b0; |
end |
|
|
1863,13 → 1861,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxBDReady <=#Tp 1'b0; |
RxBDReady <= 1'b0; |
else |
if(RxPointerRead) |
RxBDReady <=#Tp 1'b0; |
RxBDReady <= 1'b0; |
else |
if(RxEn & RxEn_q & RxBDRead) |
RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning |
RxBDReady <= ram_do[15]; // RxBDReady is sampled only once at the beginning |
end |
|
// Latching Rx buffer descriptor status |
1877,10 → 1875,10
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxStatus <=#Tp 2'h0; |
RxStatus <= 2'h0; |
else |
if(RxEn & RxEn_q & RxBDRead) |
RxStatus <=#Tp ram_do[14:13]; |
RxStatus <= ram_do[14:13]; |
end |
|
|
1888,13 → 1886,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxReady <=#Tp 1'b0; |
RxReady <= 1'b0; |
else |
if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3 | ~r_RxEn & r_RxEn_q) |
RxReady <=#Tp 1'b0; |
RxReady <= 1'b0; |
else |
if(RxEn & RxEn_q & RxPointerRead) |
RxReady <=#Tp 1'b1; |
RxReady <= 1'b1; |
end |
|
|
1907,13 → 1905,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxPointerRead <=#Tp 1'b0; |
RxPointerRead <= 1'b0; |
else |
if(StartRxPointerRead) |
RxPointerRead <=#Tp 1'b1; |
RxPointerRead <= 1'b1; |
else |
if(RxEn & RxEn_q) |
RxPointerRead <=#Tp 1'b0; |
RxPointerRead <= 1'b0; |
end |
|
|
1921,13 → 1919,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxPointerMSB <=#Tp 30'h0; |
RxPointerMSB <= 30'h0; |
else |
if(RxEn & RxEn_q & RxPointerRead) |
RxPointerMSB <=#Tp ram_do[31:2]; |
RxPointerMSB <= ram_do[31:2]; |
else |
if(MasterWbRX & m_wb_ack_i) |
RxPointerMSB <=#Tp RxPointerMSB + 1'b1; // Word access (always word access. m_wb_sel_o are used for selecting bytes) |
RxPointerMSB <= RxPointerMSB + 1'b1; // Word access (always word access. m_wb_sel_o are used for selecting bytes) |
end |
|
|
1935,13 → 1933,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxPointerLSB_rst[1:0] <=#Tp 0; |
RxPointerLSB_rst[1:0] <= 0; |
else |
if(MasterWbRX & m_wb_ack_i) // After first write all RxByteSel are active |
RxPointerLSB_rst[1:0] <=#Tp 0; |
RxPointerLSB_rst[1:0] <= 0; |
else |
if(RxEn & RxEn_q & RxPointerRead) |
RxPointerLSB_rst[1:0] <=#Tp ram_do[1:0]; |
RxPointerLSB_rst[1:0] <= ram_do[1:0]; |
end |
|
|
1959,13 → 1957,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxEn_needed <=#Tp 1'b0; |
RxEn_needed <= 1'b0; |
else |
if(~RxReady & r_RxEn & WbEn & ~WbEn_q) |
RxEn_needed <=#Tp 1'b1; |
RxEn_needed <= 1'b1; |
else |
if(RxPointerRead & RxEn & RxEn_q) |
RxEn_needed <=#Tp 1'b0; |
RxEn_needed <= 1'b0; |
end |
|
|
1978,13 → 1976,13
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
LastByteIn <=#Tp 1'b0; |
LastByteIn <= 1'b0; |
else |
if(ShiftWillEnd & (&RxByteCnt) | RxAbort) |
LastByteIn <=#Tp 1'b0; |
LastByteIn <= 1'b0; |
else |
if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow) |
LastByteIn <=#Tp 1'b1; |
LastByteIn <= 1'b1; |
end |
|
reg ShiftEnded_rck; |
2001,13 → 1999,13
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ShiftWillEnd <=#Tp 1'b0; |
ShiftWillEnd <= 1'b0; |
else |
if(ShiftEnded_rck | RxAbort) |
ShiftWillEnd <=#Tp 1'b0; |
ShiftWillEnd <= 1'b0; |
else |
if(StartShiftWillEnd) |
ShiftWillEnd <=#Tp 1'b1; |
ShiftWillEnd <= 1'b1; |
end |
|
|
2016,21 → 2014,21
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxByteCnt <=#Tp 2'h0; |
RxByteCnt <= 2'h0; |
else |
if(ShiftEnded_rck | RxAbort) |
RxByteCnt <=#Tp 2'h0; |
RxByteCnt <= 2'h0; |
else |
if(RxValid & RxStartFrm & RxReady) |
case(RxPointerLSB_rst) // synopsys parallel_case |
2'h0 : RxByteCnt <=#Tp 2'h1; |
2'h1 : RxByteCnt <=#Tp 2'h2; |
2'h2 : RxByteCnt <=#Tp 2'h3; |
2'h3 : RxByteCnt <=#Tp 2'h0; |
2'h0 : RxByteCnt <= 2'h1; |
2'h1 : RxByteCnt <= 2'h2; |
2'h2 : RxByteCnt <= 2'h3; |
2'h3 : RxByteCnt <= 2'h0; |
endcase |
else |
if(RxValid & RxEnableWindow & RxReady | LastByteIn) |
RxByteCnt <=#Tp RxByteCnt + 1'b1; |
RxByteCnt <= RxByteCnt + 1'b1; |
end |
|
|
2038,18 → 2036,18
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxValidBytes <=#Tp 2'h1; |
RxValidBytes <= 2'h1; |
else |
if(RxValid & RxStartFrm) |
case(RxPointerLSB_rst) // synopsys parallel_case |
2'h0 : RxValidBytes <=#Tp 2'h1; |
2'h1 : RxValidBytes <=#Tp 2'h2; |
2'h2 : RxValidBytes <=#Tp 2'h3; |
2'h3 : RxValidBytes <=#Tp 2'h0; |
2'h0 : RxValidBytes <= 2'h1; |
2'h1 : RxValidBytes <= 2'h2; |
2'h2 : RxValidBytes <= 2'h3; |
2'h3 : RxValidBytes <= 2'h0; |
endcase |
else |
if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow) |
RxValidBytes <=#Tp RxValidBytes + 1'b1; |
RxValidBytes <= RxValidBytes + 1'b1; |
end |
|
|
2056,25 → 2054,25
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxDataLatched1 <=#Tp 24'h0; |
RxDataLatched1 <= 24'h0; |
else |
if(RxValid & RxReady & ~LastByteIn) |
if(RxStartFrm) |
begin |
case(RxPointerLSB_rst) // synopsys parallel_case |
2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering |
2'h1: RxDataLatched1[23:16] <=#Tp RxData; |
2'h2: RxDataLatched1[15:8] <=#Tp RxData; |
2'h3: RxDataLatched1 <=#Tp RxDataLatched1; |
2'h0: RxDataLatched1[31:24] <= RxData; // Big Endian Byte Ordering |
2'h1: RxDataLatched1[23:16] <= RxData; |
2'h2: RxDataLatched1[15:8] <= RxData; |
2'h3: RxDataLatched1 <= RxDataLatched1; |
endcase |
end |
else if (RxEnableWindow) |
begin |
case(RxByteCnt) // synopsys parallel_case |
2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering |
2'h1: RxDataLatched1[23:16] <=#Tp RxData; |
2'h2: RxDataLatched1[15:8] <=#Tp RxData; |
2'h3: RxDataLatched1 <=#Tp RxDataLatched1; |
2'h0: RxDataLatched1[31:24] <= RxData; // Big Endian Byte Ordering |
2'h1: RxDataLatched1[23:16] <= RxData; |
2'h2: RxDataLatched1[15:8] <= RxData; |
2'h3: RxDataLatched1 <= RxDataLatched1; |
endcase |
end |
end |
2085,17 → 2083,17
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxDataLatched2 <=#Tp 32'h0; |
RxDataLatched2 <= 32'h0; |
else |
if(SetWriteRxDataToFifo & ~ShiftWillEnd) |
RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering |
RxDataLatched2 <= {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering |
else |
if(SetWriteRxDataToFifo & ShiftWillEnd) |
case(RxValidBytes) // synopsys parallel_case |
0 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering |
1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0}; |
2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0}; |
3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], 8'h0}; |
0 : RxDataLatched2 <= {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering |
1 : RxDataLatched2 <= {RxDataLatched1[31:24], 24'h0}; |
2 : RxDataLatched2 <= {RxDataLatched1[31:16], 16'h0}; |
3 : RxDataLatched2 <= {RxDataLatched1[31:8], 8'h0}; |
endcase |
end |
|
2113,13 → 2111,13
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
WriteRxDataToFifo <=#Tp 1'b0; |
WriteRxDataToFifo <= 1'b0; |
else |
if(SetWriteRxDataToFifo & ~RxAbort) |
WriteRxDataToFifo <=#Tp 1'b1; |
WriteRxDataToFifo <= 1'b1; |
else |
if(WriteRxDataToFifoSync2 | RxAbort) |
WriteRxDataToFifo <=#Tp 1'b0; |
WriteRxDataToFifo <= 1'b0; |
end |
|
|
2127,28 → 2125,28
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
WriteRxDataToFifoSync1 <=#Tp 1'b0; |
WriteRxDataToFifoSync1 <= 1'b0; |
else |
if(WriteRxDataToFifo) |
WriteRxDataToFifoSync1 <=#Tp 1'b1; |
WriteRxDataToFifoSync1 <= 1'b1; |
else |
WriteRxDataToFifoSync1 <=#Tp 1'b0; |
WriteRxDataToFifoSync1 <= 1'b0; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
WriteRxDataToFifoSync2 <=#Tp 1'b0; |
WriteRxDataToFifoSync2 <= 1'b0; |
else |
WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1; |
WriteRxDataToFifoSync2 <= WriteRxDataToFifoSync1; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
WriteRxDataToFifoSync3 <=#Tp 1'b0; |
WriteRxDataToFifoSync3 <= 1'b0; |
else |
WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2; |
WriteRxDataToFifoSync3 <= WriteRxDataToFifoSync2; |
end |
|
wire WriteRxDataToFifo_wb; |
2164,13 → 2162,13
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
LatchedRxStartFrm <=#Tp 0; |
LatchedRxStartFrm <= 0; |
else |
if(RxStartFrm & ~SyncRxStartFrm_q) |
LatchedRxStartFrm <=#Tp 1; |
LatchedRxStartFrm <= 1; |
else |
if(SyncRxStartFrm_q) |
LatchedRxStartFrm <=#Tp 0; |
LatchedRxStartFrm <= 0; |
end |
|
|
2177,12 → 2175,12
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
SyncRxStartFrm <=#Tp 0; |
SyncRxStartFrm <= 0; |
else |
if(LatchedRxStartFrm) |
SyncRxStartFrm <=#Tp 1; |
SyncRxStartFrm <= 1; |
else |
SyncRxStartFrm <=#Tp 0; |
SyncRxStartFrm <= 0; |
end |
|
|
2189,17 → 2187,17
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
SyncRxStartFrm_q <=#Tp 0; |
SyncRxStartFrm_q <= 0; |
else |
SyncRxStartFrm_q <=#Tp SyncRxStartFrm; |
SyncRxStartFrm_q <= SyncRxStartFrm; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
SyncRxStartFrm_q2 <=#Tp 0; |
SyncRxStartFrm_q2 <= 0; |
else |
SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q; |
SyncRxStartFrm_q2 <= SyncRxStartFrm_q; |
end |
|
|
2207,8 → 2205,7
|
eth_fifo #(.DATA_WIDTH(RX_FIFO_DATA_WIDTH), |
.DEPTH(RX_FIFO_DEPTH), |
.CNT_WIDTH(RX_FIFO_CNT_WIDTH), |
.Tp(Tp)) |
.CNT_WIDTH(RX_FIFO_CNT_WIDTH)) |
rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o), |
.clk(WB_CLK_I), .reset(Reset), |
.write(WriteRxDataToFifo_wb & ~RxBufferFull), .read(MasterWbRX & m_wb_ack_i), |
2227,41 → 2224,41
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ShiftEnded_rck <=#Tp 1'b0; |
ShiftEnded_rck <= 1'b0; |
else |
if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd) |
ShiftEnded_rck <=#Tp 1'b1; |
ShiftEnded_rck <= 1'b1; |
else |
if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2) |
ShiftEnded_rck <=#Tp 1'b0; |
ShiftEnded_rck <= 1'b0; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ShiftEndedSync1 <=#Tp 1'b0; |
ShiftEndedSync1 <= 1'b0; |
else |
ShiftEndedSync1 <=#Tp ShiftEnded_rck; |
ShiftEndedSync1 <= ShiftEnded_rck; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ShiftEndedSync2 <=#Tp 1'b0; |
ShiftEndedSync2 <= 1'b0; |
else |
ShiftEndedSync2 <=#Tp ShiftEndedSync1; |
ShiftEndedSync2 <= ShiftEndedSync1; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ShiftEndedSync3 <=#Tp 1'b0; |
ShiftEndedSync3 <= 1'b0; |
else |
if(ShiftEndedSync1 & ~ShiftEndedSync2) |
ShiftEndedSync3 <=#Tp 1'b1; |
ShiftEndedSync3 <= 1'b1; |
else |
if(ShiftEnded) |
ShiftEndedSync3 <=#Tp 1'b0; |
ShiftEndedSync3 <= 1'b0; |
end |
|
// Generation of the end-of-frame signal |
2268,29 → 2265,29
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ShiftEnded <=#Tp 1'b0; |
ShiftEnded <= 1'b0; |
else |
if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded) |
ShiftEnded <=#Tp 1'b1; |
ShiftEnded <= 1'b1; |
else |
if(RxStatusWrite) |
ShiftEnded <=#Tp 1'b0; |
ShiftEnded <= 1'b0; |
end |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ShiftEndedSync_c1 <=#Tp 1'b0; |
ShiftEndedSync_c1 <= 1'b0; |
else |
ShiftEndedSync_c1 <=#Tp ShiftEndedSync2; |
ShiftEndedSync_c1 <= ShiftEndedSync2; |
end |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ShiftEndedSync_c2 <=#Tp 1'b0; |
ShiftEndedSync_c2 <= 1'b0; |
else |
ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1; |
ShiftEndedSync_c2 <= ShiftEndedSync_c1; |
end |
|
// Generation of the end-of-frame signal |
2297,13 → 2294,13
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxEnableWindow <=#Tp 1'b0; |
RxEnableWindow <= 1'b0; |
else |
if(RxStartFrm) |
RxEnableWindow <=#Tp 1'b1; |
RxEnableWindow <= 1'b1; |
else |
if(RxEndFrm | RxAbort) |
RxEnableWindow <=#Tp 1'b0; |
RxEnableWindow <= 1'b0; |
end |
|
|
2310,49 → 2307,49
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxAbortSync1 <=#Tp 1'b0; |
RxAbortSync1 <= 1'b0; |
else |
RxAbortSync1 <=#Tp RxAbortLatched; |
RxAbortSync1 <= RxAbortLatched; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxAbortSync2 <=#Tp 1'b0; |
RxAbortSync2 <= 1'b0; |
else |
RxAbortSync2 <=#Tp RxAbortSync1; |
RxAbortSync2 <= RxAbortSync1; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxAbortSync3 <=#Tp 1'b0; |
RxAbortSync3 <= 1'b0; |
else |
RxAbortSync3 <=#Tp RxAbortSync2; |
RxAbortSync3 <= RxAbortSync2; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxAbortSync4 <=#Tp 1'b0; |
RxAbortSync4 <= 1'b0; |
else |
RxAbortSync4 <=#Tp RxAbortSync3; |
RxAbortSync4 <= RxAbortSync3; |
end |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxAbortSyncb1 <=#Tp 1'b0; |
RxAbortSyncb1 <= 1'b0; |
else |
RxAbortSyncb1 <=#Tp RxAbortSync2; |
RxAbortSyncb1 <= RxAbortSync2; |
end |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxAbortSyncb2 <=#Tp 1'b0; |
RxAbortSyncb2 <= 1'b0; |
else |
RxAbortSyncb2 <=#Tp RxAbortSyncb1; |
RxAbortSyncb2 <= RxAbortSyncb1; |
end |
|
|
2359,13 → 2356,13
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxAbortLatched <=#Tp 1'b0; |
RxAbortLatched <= 1'b0; |
else |
if(RxAbortSyncb2) |
RxAbortLatched <=#Tp 1'b0; |
RxAbortLatched <= 1'b0; |
else |
if(RxAbort) |
RxAbortLatched <=#Tp 1'b1; |
RxAbortLatched <= 1'b1; |
end |
|
|
2372,10 → 2369,10
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
LatchedRxLength[15:0] <=#Tp 16'h0; |
LatchedRxLength[15:0] <= 16'h0; |
else |
if(LoadRxStatus) |
LatchedRxLength[15:0] <=#Tp RxLength[15:0]; |
LatchedRxLength[15:0] <= RxLength[15:0]; |
end |
|
|
2384,10 → 2381,10
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxStatusInLatched <=#Tp 'h0; |
RxStatusInLatched <= 'h0; |
else |
if(LoadRxStatus) |
RxStatusInLatched <=#Tp RxStatusIn; |
RxStatusInLatched <= RxStatusIn; |
end |
|
|
2395,13 → 2392,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxOverrun <=#Tp 1'b0; |
RxOverrun <= 1'b0; |
else |
if(RxStatusWrite) |
RxOverrun <=#Tp 1'b0; |
RxOverrun <= 1'b0; |
else |
if(RxBufferFull & WriteRxDataToFifo_wb) |
RxOverrun <=#Tp 1'b1; |
RxOverrun <= 1'b1; |
end |
|
|
2430,13 → 2427,13
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxStatusWriteLatched <=#Tp 1'b0; |
RxStatusWriteLatched <= 1'b0; |
else |
if(RxStatusWriteLatched_syncb2) |
RxStatusWriteLatched <=#Tp 1'b0; |
RxStatusWriteLatched <= 1'b0; |
else |
if(RxStatusWrite) |
RxStatusWriteLatched <=#Tp 1'b1; |
RxStatusWriteLatched <= 1'b1; |
end |
|
|
2444,13 → 2441,13
begin |
if(Reset) |
begin |
RxStatusWriteLatched_sync1 <=#Tp 1'b0; |
RxStatusWriteLatched_sync2 <=#Tp 1'b0; |
RxStatusWriteLatched_sync1 <= 1'b0; |
RxStatusWriteLatched_sync2 <= 1'b0; |
end |
else |
begin |
RxStatusWriteLatched_sync1 <=#Tp RxStatusWriteLatched; |
RxStatusWriteLatched_sync2 <=#Tp RxStatusWriteLatched_sync1; |
RxStatusWriteLatched_sync1 <= RxStatusWriteLatched; |
RxStatusWriteLatched_sync2 <= RxStatusWriteLatched_sync1; |
end |
end |
|
2459,13 → 2456,13
begin |
if(Reset) |
begin |
RxStatusWriteLatched_syncb1 <=#Tp 1'b0; |
RxStatusWriteLatched_syncb2 <=#Tp 1'b0; |
RxStatusWriteLatched_syncb1 <= 1'b0; |
RxStatusWriteLatched_syncb2 <= 1'b0; |
end |
else |
begin |
RxStatusWriteLatched_syncb1 <=#Tp RxStatusWriteLatched_sync2; |
RxStatusWriteLatched_syncb2 <=#Tp RxStatusWriteLatched_syncb1; |
RxStatusWriteLatched_syncb1 <= RxStatusWriteLatched_sync2; |
RxStatusWriteLatched_syncb2 <= RxStatusWriteLatched_syncb1; |
end |
end |
|
2475,12 → 2472,12
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxB_IRQ <=#Tp 1'b0; |
TxB_IRQ <= 1'b0; |
else |
if(TxStatusWrite & TxIRQEn) |
TxB_IRQ <=#Tp ~TxError; |
TxB_IRQ <= ~TxError; |
else |
TxB_IRQ <=#Tp 1'b0; |
TxB_IRQ <= 1'b0; |
end |
|
|
2488,12 → 2485,12
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxE_IRQ <=#Tp 1'b0; |
TxE_IRQ <= 1'b0; |
else |
if(TxStatusWrite & TxIRQEn) |
TxE_IRQ <=#Tp TxError; |
TxE_IRQ <= TxError; |
else |
TxE_IRQ <=#Tp 1'b0; |
TxE_IRQ <= 1'b0; |
end |
|
|
2501,12 → 2498,12
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxB_IRQ <=#Tp 1'b0; |
RxB_IRQ <= 1'b0; |
else |
if(RxStatusWrite & RxIRQEn & ReceivedPacketGood & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow))) |
RxB_IRQ <=#Tp (~RxError); |
RxB_IRQ <= (~RxError); |
else |
RxB_IRQ <=#Tp 1'b0; |
RxB_IRQ <= 1'b0; |
end |
|
|
2514,12 → 2511,12
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxE_IRQ <=#Tp 1'b0; |
RxE_IRQ <= 1'b0; |
else |
if(RxStatusWrite & RxIRQEn & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow))) |
RxE_IRQ <=#Tp RxError; |
RxE_IRQ <= RxError; |
else |
RxE_IRQ <=#Tp 1'b0; |
RxE_IRQ <= 1'b0; |
end |
|
|
2536,26 → 2533,26
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
Busy_IRQ_rck <=#Tp 1'b0; |
Busy_IRQ_rck <= 1'b0; |
else |
if(RxValid & RxStartFrm & ~RxReady) |
Busy_IRQ_rck <=#Tp 1'b1; |
Busy_IRQ_rck <= 1'b1; |
else |
if(Busy_IRQ_syncb2) |
Busy_IRQ_rck <=#Tp 1'b0; |
Busy_IRQ_rck <= 1'b0; |
end |
|
always @ (posedge WB_CLK_I) |
begin |
Busy_IRQ_sync1 <=#Tp Busy_IRQ_rck; |
Busy_IRQ_sync2 <=#Tp Busy_IRQ_sync1; |
Busy_IRQ_sync3 <=#Tp Busy_IRQ_sync2; |
Busy_IRQ_sync1 <= Busy_IRQ_rck; |
Busy_IRQ_sync2 <= Busy_IRQ_sync1; |
Busy_IRQ_sync3 <= Busy_IRQ_sync2; |
end |
|
always @ (posedge MRxClk) |
begin |
Busy_IRQ_syncb1 <=#Tp Busy_IRQ_sync2; |
Busy_IRQ_syncb2 <=#Tp Busy_IRQ_syncb1; |
Busy_IRQ_syncb1 <= Busy_IRQ_sync2; |
Busy_IRQ_syncb2 <= Busy_IRQ_syncb1; |
end |
|
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3; |
/trunk/rtl/verilog/eth_txcounters.v
92,8 → 92,6
ExcessiveDefer, NibCntEq7, NibCntEq15, MaxFrame, NibbleMinFl, DlyCrcCnt |
); |
|
parameter Tp = 1; |
|
input MTxClk; // Tx clock |
input Reset; // Reset |
input StatePreamble; // Preamble state |
152,14 → 150,14
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
NibCnt <= #Tp 16'h0; |
NibCnt <= 16'h0; |
else |
begin |
if(ResetNibCnt) |
NibCnt <= #Tp 16'h0; |
NibCnt <= 16'h0; |
else |
if(IncrementNibCnt) |
NibCnt <= #Tp NibCnt + 1'b1; |
NibCnt <= NibCnt + 1'b1; |
end |
end |
|
184,14 → 182,14
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
ByteCnt[15:0] <= #Tp 16'h0; |
ByteCnt[15:0] <= 16'h0; |
else |
begin |
if(ResetByteCnt) |
ByteCnt[15:0] <= #Tp 16'h0; |
ByteCnt[15:0] <= 16'h0; |
else |
if(IncrementByteCnt) |
ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1; |
ByteCnt[15:0] <= ByteCnt[15:0] + 1'b1; |
end |
end |
|
205,14 → 203,14
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
DlyCrcCnt <= #Tp 3'h0; |
DlyCrcCnt <= 3'h0; |
else |
begin |
if(StateData[1] & DlyCrcCnt == 3'h4 | StartJam | PacketFinished_q) |
DlyCrcCnt <= #Tp 3'h0; |
DlyCrcCnt <= 3'h0; |
else |
if(DlyCrcEn & (StateSFD | StateData[1] & (|DlyCrcCnt[2:0]))) |
DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1; |
DlyCrcCnt <= DlyCrcCnt + 1'b1; |
end |
end |
|
/trunk/rtl/verilog/eth_random.v
82,8 → 82,6
module eth_random (MTxClk, Reset, StateJam, StateJam_q, RetryCnt, NibCnt, ByteCnt, |
RandomEq0, RandomEqByteCnt); |
|
parameter Tp = 1; |
|
input MTxClk; |
input Reset; |
input StateJam; |
103,9 → 101,9
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
x[9:0] <= #Tp 0; |
x[9:0] <= 0; |
else |
x[9:0] <= #Tp {x[8:0], Feedback}; |
x[9:0] <= {x[8:0], Feedback}; |
end |
|
assign Feedback = ~(x[2] ^ x[9]); |
125,11 → 123,11
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
RandomLatched <= #Tp 10'h000; |
RandomLatched <= 10'h000; |
else |
begin |
if(StateJam & StateJam_q) |
RandomLatched <= #Tp Random; |
RandomLatched <= Random; |
end |
end |
|
/trunk/rtl/verilog/eth_cop.v
89,7 → 89,6
s2_wb_dat_o |
); |
|
parameter Tp=1; |
parameter ETH_BASE = 32'hd0000000; |
parameter ETH_WIDTH = 32'h800; |
parameter MEMORY_BASE = 32'h2000; |
166,20 → 165,20
begin |
if(wb_rst_i) |
begin |
m1_in_progress <=#Tp 0; |
m2_in_progress <=#Tp 0; |
s1_wb_adr_o <=#Tp 0; |
s1_wb_sel_o <=#Tp 0; |
s1_wb_we_o <=#Tp 0; |
s1_wb_dat_o <=#Tp 0; |
s1_wb_cyc_o <=#Tp 0; |
s1_wb_stb_o <=#Tp 0; |
s2_wb_adr_o <=#Tp 0; |
s2_wb_sel_o <=#Tp 0; |
s2_wb_we_o <=#Tp 0; |
s2_wb_dat_o <=#Tp 0; |
s2_wb_cyc_o <=#Tp 0; |
s2_wb_stb_o <=#Tp 0; |
m1_in_progress <= 0; |
m2_in_progress <= 0; |
s1_wb_adr_o <= 0; |
s1_wb_sel_o <= 0; |
s1_wb_we_o <= 0; |
s1_wb_dat_o <= 0; |
s1_wb_cyc_o <= 0; |
s1_wb_stb_o <= 0; |
s2_wb_adr_o <= 0; |
s2_wb_sel_o <= 0; |
s2_wb_we_o <= 0; |
s2_wb_dat_o <= 0; |
s2_wb_cyc_o <= 0; |
s2_wb_stb_o <= 0; |
end |
else |
begin |
186,24 → 185,24
case({m1_in_progress, m2_in_progress, m1_req, m2_req, m_wb_access_finished}) // synopsys_full_case synopsys_paralel_case |
5'b00_10_0, 5'b00_11_0 : |
begin |
m1_in_progress <=#Tp 1'b1; // idle: m1 or (m1 & m2) want access: m1 -> m |
m1_in_progress <= 1'b1; // idle: m1 or (m1 & m2) want access: m1 -> m |
if(m1_addressed_s1) |
begin |
s1_wb_adr_o <=#Tp m1_wb_adr_i; |
s1_wb_sel_o <=#Tp m1_wb_sel_i; |
s1_wb_we_o <=#Tp m1_wb_we_i; |
s1_wb_dat_o <=#Tp m1_wb_dat_i; |
s1_wb_cyc_o <=#Tp 1'b1; |
s1_wb_stb_o <=#Tp 1'b1; |
s1_wb_adr_o <= m1_wb_adr_i; |
s1_wb_sel_o <= m1_wb_sel_i; |
s1_wb_we_o <= m1_wb_we_i; |
s1_wb_dat_o <= m1_wb_dat_i; |
s1_wb_cyc_o <= 1'b1; |
s1_wb_stb_o <= 1'b1; |
end |
else if(m1_addressed_s2) |
begin |
s2_wb_adr_o <=#Tp m1_wb_adr_i; |
s2_wb_sel_o <=#Tp m1_wb_sel_i; |
s2_wb_we_o <=#Tp m1_wb_we_i; |
s2_wb_dat_o <=#Tp m1_wb_dat_i; |
s2_wb_cyc_o <=#Tp 1'b1; |
s2_wb_stb_o <=#Tp 1'b1; |
s2_wb_adr_o <= m1_wb_adr_i; |
s2_wb_sel_o <= m1_wb_sel_i; |
s2_wb_we_o <= m1_wb_we_i; |
s2_wb_dat_o <= m1_wb_dat_i; |
s2_wb_cyc_o <= 1'b1; |
s2_wb_stb_o <= 1'b1; |
end |
else |
$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time); |
210,24 → 209,24
end |
5'b00_01_0 : |
begin |
m2_in_progress <=#Tp 1'b1; // idle: m2 wants access: m2 -> m |
m2_in_progress <= 1'b1; // idle: m2 wants access: m2 -> m |
if(m2_addressed_s1) |
begin |
s1_wb_adr_o <=#Tp m2_wb_adr_i; |
s1_wb_sel_o <=#Tp m2_wb_sel_i; |
s1_wb_we_o <=#Tp m2_wb_we_i; |
s1_wb_dat_o <=#Tp m2_wb_dat_i; |
s1_wb_cyc_o <=#Tp 1'b1; |
s1_wb_stb_o <=#Tp 1'b1; |
s1_wb_adr_o <= m2_wb_adr_i; |
s1_wb_sel_o <= m2_wb_sel_i; |
s1_wb_we_o <= m2_wb_we_i; |
s1_wb_dat_o <= m2_wb_dat_i; |
s1_wb_cyc_o <= 1'b1; |
s1_wb_stb_o <= 1'b1; |
end |
else if(m2_addressed_s2) |
begin |
s2_wb_adr_o <=#Tp m2_wb_adr_i; |
s2_wb_sel_o <=#Tp m2_wb_sel_i; |
s2_wb_we_o <=#Tp m2_wb_we_i; |
s2_wb_dat_o <=#Tp m2_wb_dat_i; |
s2_wb_cyc_o <=#Tp 1'b1; |
s2_wb_stb_o <=#Tp 1'b1; |
s2_wb_adr_o <= m2_wb_adr_i; |
s2_wb_sel_o <= m2_wb_sel_i; |
s2_wb_we_o <= m2_wb_we_i; |
s2_wb_dat_o <= m2_wb_dat_i; |
s2_wb_cyc_o <= 1'b1; |
s2_wb_stb_o <= 1'b1; |
end |
else |
$display("(%t)(%m)WISHBONE ERROR: Unspecified address space accessed", $time); |
234,30 → 233,30
end |
5'b10_10_1, 5'b10_11_1 : |
begin |
m1_in_progress <=#Tp 1'b0; // m1 in progress. Cycle is finished. Send ack or err to m1. |
m1_in_progress <= 1'b0; // m1 in progress. Cycle is finished. Send ack or err to m1. |
if(m1_addressed_s1) |
begin |
s1_wb_cyc_o <=#Tp 1'b0; |
s1_wb_stb_o <=#Tp 1'b0; |
s1_wb_cyc_o <= 1'b0; |
s1_wb_stb_o <= 1'b0; |
end |
else if(m1_addressed_s2) |
begin |
s2_wb_cyc_o <=#Tp 1'b0; |
s2_wb_stb_o <=#Tp 1'b0; |
s2_wb_cyc_o <= 1'b0; |
s2_wb_stb_o <= 1'b0; |
end |
end |
5'b01_01_1, 5'b01_11_1 : |
begin |
m2_in_progress <=#Tp 1'b0; // m2 in progress. Cycle is finished. Send ack or err to m2. |
m2_in_progress <= 1'b0; // m2 in progress. Cycle is finished. Send ack or err to m2. |
if(m2_addressed_s1) |
begin |
s1_wb_cyc_o <=#Tp 1'b0; |
s1_wb_stb_o <=#Tp 1'b0; |
s1_wb_cyc_o <= 1'b0; |
s1_wb_stb_o <= 1'b0; |
end |
else if(m2_addressed_s2) |
begin |
s2_wb_cyc_o <=#Tp 1'b0; |
s2_wb_stb_o <=#Tp 1'b0; |
s2_wb_cyc_o <= 1'b0; |
s2_wb_stb_o <= 1'b0; |
end |
end |
endcase |
344,13 → 343,13
always @ (posedge wb_clk_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
cnt <=#Tp 0; |
cnt <= 0; |
else |
if(s1_wb_ack_i | s1_wb_err_i | s2_wb_ack_i | s2_wb_err_i) |
cnt <=#Tp 0; |
cnt <= 0; |
else |
if(s1_wb_cyc_o | s2_wb_cyc_o) |
cnt <=#Tp cnt+1; |
cnt <= cnt+1; |
end |
|
always @ (posedge wb_clk_i) |
/trunk/rtl/verilog/eth_rxaddrcheck.v
82,7 → 82,6
ControlFrmAddressOK |
); |
|
parameter Tp = 1; |
|
input MRxClk; |
input Reset; |
138,11 → 137,11
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxAbort <= #Tp 1'b0; |
RxAbort <= 1'b0; |
else if(RxAddressInvalid & ByteCntEq7 & RxCheckEn) |
RxAbort <= #Tp 1'b1; |
RxAbort <= 1'b1; |
else |
RxAbort <= #Tp 1'b0; |
RxAbort <= 1'b0; |
end |
|
|
150,11 → 149,11
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
AddressMiss <= #Tp 1'b0; |
AddressMiss <= 1'b0; |
else if(ByteCntEq0) |
AddressMiss <= #Tp 1'b0; |
AddressMiss <= 1'b0; |
else if(ByteCntEq7 & RxCheckEn) |
AddressMiss <= #Tp (~(UnicastOK | BroadcastOK | MulticastOK | (PassAll & ControlFrmAddressOK))); |
AddressMiss <= (~(UnicastOK | BroadcastOK | MulticastOK | (PassAll & ControlFrmAddressOK))); |
end |
|
|
162,11 → 161,11
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
MulticastOK <= #Tp 1'b0; |
MulticastOK <= 1'b0; |
else if(RxEndFrm | RxAbort) |
MulticastOK <= #Tp 1'b0; |
MulticastOK <= 1'b0; |
else if(CrcHashGood & Multicast) |
MulticastOK <= #Tp HashBit; |
MulticastOK <= HashBit; |
end |
|
|
175,28 → 174,28
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
UnicastOK <= #Tp 1'b0; |
UnicastOK <= 1'b0; |
else |
if(RxCheckEn & ByteCntEq2) |
UnicastOK <= #Tp RxData[7:0] == MAC[47:40]; |
UnicastOK <= RxData[7:0] == MAC[47:40]; |
else |
if(RxCheckEn & ByteCntEq3) |
UnicastOK <= #Tp ( RxData[7:0] == MAC[39:32]) & UnicastOK; |
UnicastOK <= ( RxData[7:0] == MAC[39:32]) & UnicastOK; |
else |
if(RxCheckEn & ByteCntEq4) |
UnicastOK <= #Tp ( RxData[7:0] == MAC[31:24]) & UnicastOK; |
UnicastOK <= ( RxData[7:0] == MAC[31:24]) & UnicastOK; |
else |
if(RxCheckEn & ByteCntEq5) |
UnicastOK <= #Tp ( RxData[7:0] == MAC[23:16]) & UnicastOK; |
UnicastOK <= ( RxData[7:0] == MAC[23:16]) & UnicastOK; |
else |
if(RxCheckEn & ByteCntEq6) |
UnicastOK <= #Tp ( RxData[7:0] == MAC[15:8]) & UnicastOK; |
UnicastOK <= ( RxData[7:0] == MAC[15:8]) & UnicastOK; |
else |
if(RxCheckEn & ByteCntEq7) |
UnicastOK <= #Tp ( RxData[7:0] == MAC[7:0]) & UnicastOK; |
UnicastOK <= ( RxData[7:0] == MAC[7:0]) & UnicastOK; |
else |
if(RxEndFrm | RxAbort) |
UnicastOK <= #Tp 1'b0; |
UnicastOK <= 1'b0; |
end |
|
assign IntHash = (CrcHash[5])? HASH1 : HASH0; |
/trunk/rtl/verilog/eth_fifo.v
65,8 → 65,6
parameter DEPTH = 8; |
parameter CNT_WIDTH = 4; |
|
parameter Tp = 1; |
|
input clk; |
input reset; |
input write; |
98,40 → 96,40
always @ (posedge clk or posedge reset) |
begin |
if(reset) |
cnt <=#Tp 0; |
cnt <= 0; |
else |
if(clear) |
cnt <=#Tp { {(CNT_WIDTH-1){1'b0}}, read^write}; |
cnt <= { {(CNT_WIDTH-1){1'b0}}, read^write}; |
else |
if(read ^ write) |
if(read) |
cnt <=#Tp cnt - 1'b1; |
cnt <= cnt - 1'b1; |
else |
cnt <=#Tp cnt + 1'b1; |
cnt <= cnt + 1'b1; |
end |
|
always @ (posedge clk or posedge reset) |
begin |
if(reset) |
read_pointer <=#Tp 0; |
read_pointer <= 0; |
else |
if(clear) |
read_pointer <=#Tp { {(CNT_WIDTH-2){1'b0}}, read}; |
read_pointer <= { {(CNT_WIDTH-2){1'b0}}, read}; |
else |
if(read & ~empty) |
read_pointer <=#Tp read_pointer + 1'b1; |
read_pointer <= read_pointer + 1'b1; |
end |
|
always @ (posedge clk or posedge reset) |
begin |
if(reset) |
write_pointer <=#Tp 0; |
write_pointer <= 0; |
else |
if(clear) |
write_pointer <=#Tp { {(CNT_WIDTH-2){1'b0}}, write}; |
write_pointer <= { {(CNT_WIDTH-2){1'b0}}, write}; |
else |
if(write & ~full) |
write_pointer <=#Tp write_pointer + 1'b1; |
write_pointer <= write_pointer + 1'b1; |
end |
|
assign empty = ~(|cnt); |
165,10 → 163,10
always @ (posedge clk) |
begin |
if(write & clear) |
fifo[0] <=#Tp data_in; |
fifo[0] <= data_in; |
else |
if(write & ~full) |
fifo[write_pointer] <=#Tp data_in; |
fifo[write_pointer] <= data_in; |
end |
|
|
175,9 → 173,9
always @ (posedge clk) |
begin |
if(clear) |
data_out <=#Tp fifo[0]; |
data_out <= fifo[0]; |
else |
data_out <=#Tp fifo[read_pointer]; |
data_out <= fifo[read_pointer]; |
end |
`endif // !ETH_ALTERA_ALTSYNCRAM |
`endif // !ETH_FIFO_XILINX |
/trunk/rtl/verilog/eth_receivecontrol.v
84,9 → 84,7
RxStatusWriteLatched_sync2, r_PassAll, SetPauseTimer |
); |
|
parameter Tp = 1; |
|
|
input MTxClk; |
input MRxClk; |
input TxReset; |
165,28 → 163,28
always @ (posedge MRxClk or posedge RxReset) |
begin |
if(RxReset) |
AddressOK <= #Tp 1'b0; |
AddressOK <= 1'b0; |
else |
if(DetectionWindow & ByteCntEq0) |
AddressOK <= #Tp RxData[7:0] == ReservedMulticast[47:40] | RxData[7:0] == MAC[47:40]; |
AddressOK <= RxData[7:0] == ReservedMulticast[47:40] | RxData[7:0] == MAC[47:40]; |
else |
if(DetectionWindow & ByteCntEq1) |
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[39:32] | RxData[7:0] == MAC[39:32]) & AddressOK; |
AddressOK <= (RxData[7:0] == ReservedMulticast[39:32] | RxData[7:0] == MAC[39:32]) & AddressOK; |
else |
if(DetectionWindow & ByteCntEq2) |
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[31:24] | RxData[7:0] == MAC[31:24]) & AddressOK; |
AddressOK <= (RxData[7:0] == ReservedMulticast[31:24] | RxData[7:0] == MAC[31:24]) & AddressOK; |
else |
if(DetectionWindow & ByteCntEq3) |
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[23:16] | RxData[7:0] == MAC[23:16]) & AddressOK; |
AddressOK <= (RxData[7:0] == ReservedMulticast[23:16] | RxData[7:0] == MAC[23:16]) & AddressOK; |
else |
if(DetectionWindow & ByteCntEq4) |
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[15:8] | RxData[7:0] == MAC[15:8]) & AddressOK; |
AddressOK <= (RxData[7:0] == ReservedMulticast[15:8] | RxData[7:0] == MAC[15:8]) & AddressOK; |
else |
if(DetectionWindow & ByteCntEq5) |
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[7:0] | RxData[7:0] == MAC[7:0]) & AddressOK; |
AddressOK <= (RxData[7:0] == ReservedMulticast[7:0] | RxData[7:0] == MAC[7:0]) & AddressOK; |
else |
if(ReceiveEnd) |
AddressOK <= #Tp 1'b0; |
AddressOK <= 1'b0; |
end |
|
|
195,16 → 193,16
always @ (posedge MRxClk or posedge RxReset ) |
begin |
if(RxReset) |
TypeLengthOK <= #Tp 1'b0; |
TypeLengthOK <= 1'b0; |
else |
if(DetectionWindow & ByteCntEq12) |
TypeLengthOK <= #Tp ByteCntEq12 & (RxData[7:0] == TypeLength[15:8]); |
TypeLengthOK <= ByteCntEq12 & (RxData[7:0] == TypeLength[15:8]); |
else |
if(DetectionWindow & ByteCntEq13) |
TypeLengthOK <= #Tp ByteCntEq13 & (RxData[7:0] == TypeLength[7:0]) & TypeLengthOK; |
TypeLengthOK <= ByteCntEq13 & (RxData[7:0] == TypeLength[7:0]) & TypeLengthOK; |
else |
if(ReceiveEnd) |
TypeLengthOK <= #Tp 1'b0; |
TypeLengthOK <= 1'b0; |
end |
|
|
213,17 → 211,17
always @ (posedge MRxClk or posedge RxReset ) |
begin |
if(RxReset) |
OpCodeOK <= #Tp 1'b0; |
OpCodeOK <= 1'b0; |
else |
if(ByteCntEq16) |
OpCodeOK <= #Tp 1'b0; |
OpCodeOK <= 1'b0; |
else |
begin |
if(DetectionWindow & ByteCntEq14) |
OpCodeOK <= #Tp ByteCntEq14 & RxData[7:0] == 8'h00; |
OpCodeOK <= ByteCntEq14 & RxData[7:0] == 8'h00; |
|
if(DetectionWindow & ByteCntEq15) |
OpCodeOK <= #Tp ByteCntEq15 & RxData[7:0] == 8'h01 & OpCodeOK; |
OpCodeOK <= ByteCntEq15 & RxData[7:0] == 8'h01 & OpCodeOK; |
end |
end |
|
232,13 → 230,13
always @ (posedge MRxClk or posedge RxReset ) |
begin |
if(RxReset) |
ReceivedPauseFrmWAddr <= #Tp 1'b0; |
ReceivedPauseFrmWAddr <= 1'b0; |
else |
if(ReceiveEnd) |
ReceivedPauseFrmWAddr <= #Tp 1'b0; |
ReceivedPauseFrmWAddr <= 1'b0; |
else |
if(ByteCntEq16 & TypeLengthOK & OpCodeOK & AddressOK) |
ReceivedPauseFrmWAddr <= #Tp 1'b1; |
ReceivedPauseFrmWAddr <= 1'b1; |
end |
|
|
247,16 → 245,16
always @ (posedge MRxClk or posedge RxReset ) |
begin |
if(RxReset) |
AssembledTimerValue[15:0] <= #Tp 16'h0; |
AssembledTimerValue[15:0] <= 16'h0; |
else |
if(RxStartFrm) |
AssembledTimerValue[15:0] <= #Tp 16'h0; |
AssembledTimerValue[15:0] <= 16'h0; |
else |
begin |
if(DetectionWindow & ByteCntEq16) |
AssembledTimerValue[15:8] <= #Tp RxData[7:0]; |
AssembledTimerValue[15:8] <= RxData[7:0]; |
if(DetectionWindow & ByteCntEq17) |
AssembledTimerValue[7:0] <= #Tp RxData[7:0]; |
AssembledTimerValue[7:0] <= RxData[7:0]; |
end |
end |
|
265,13 → 263,13
always @ (posedge MRxClk or posedge RxReset ) |
begin |
if(RxReset) |
DetectionWindow <= #Tp 1'b1; |
DetectionWindow <= 1'b1; |
else |
if(ByteCntEq18) |
DetectionWindow <= #Tp 1'b0; |
DetectionWindow <= 1'b0; |
else |
if(ReceiveEnd) |
DetectionWindow <= #Tp 1'b1; |
DetectionWindow <= 1'b1; |
end |
|
|
280,13 → 278,13
always @ (posedge MRxClk or posedge RxReset ) |
begin |
if(RxReset) |
LatchedTimerValue[15:0] <= #Tp 16'h0; |
LatchedTimerValue[15:0] <= 16'h0; |
else |
if(DetectionWindow & ReceivedPauseFrmWAddr & ByteCntEq18) |
LatchedTimerValue[15:0] <= #Tp AssembledTimerValue[15:0]; |
LatchedTimerValue[15:0] <= AssembledTimerValue[15:0]; |
else |
if(ReceiveEnd) |
LatchedTimerValue[15:0] <= #Tp 16'h0; |
LatchedTimerValue[15:0] <= 16'h0; |
end |
|
|
295,13 → 293,13
always @ (posedge MRxClk or posedge RxReset) |
begin |
if(RxReset) |
DlyCrcCnt <= #Tp 3'h0; |
DlyCrcCnt <= 3'h0; |
else |
if(RxValid & RxEndFrm) |
DlyCrcCnt <= #Tp 3'h0; |
DlyCrcCnt <= 3'h0; |
else |
if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2]) |
DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1; |
DlyCrcCnt <= DlyCrcCnt + 1'b1; |
end |
|
|
313,13 → 311,13
always @ (posedge MRxClk or posedge RxReset) |
begin |
if(RxReset) |
ByteCnt[4:0] <= #Tp 5'h0; |
ByteCnt[4:0] <= 5'h0; |
else |
if(ResetByteCnt) |
ByteCnt[4:0] <= #Tp 5'h0; |
ByteCnt[4:0] <= 5'h0; |
else |
if(IncrementByteCnt) |
ByteCnt[4:0] <= #Tp ByteCnt[4:0] + 1'b1; |
ByteCnt[4:0] <= ByteCnt[4:0] + 1'b1; |
end |
|
|
346,13 → 344,13
always @ (posedge MRxClk or posedge RxReset) |
begin |
if(RxReset) |
PauseTimer[15:0] <= #Tp 16'h0; |
PauseTimer[15:0] <= 16'h0; |
else |
if(SetPauseTimer) |
PauseTimer[15:0] <= #Tp LatchedTimerValue[15:0]; |
PauseTimer[15:0] <= LatchedTimerValue[15:0]; |
else |
if(DecrementPauseTimer) |
PauseTimer[15:0] <= #Tp PauseTimer[15:0] - 1'b1; |
PauseTimer[15:0] <= PauseTimer[15:0] - 1'b1; |
end |
|
assign PauseTimerEq0 = ~(|PauseTimer[15:0]); |
364,13 → 362,13
begin |
if(TxReset) |
begin |
PauseTimerEq0_sync1 <= #Tp 1'b1; |
PauseTimerEq0_sync2 <= #Tp 1'b1; |
PauseTimerEq0_sync1 <= 1'b1; |
PauseTimerEq0_sync2 <= 1'b1; |
end |
else |
begin |
PauseTimerEq0_sync1 <= #Tp PauseTimerEq0; |
PauseTimerEq0_sync2 <= #Tp PauseTimerEq0_sync1; |
PauseTimerEq0_sync1 <= PauseTimerEq0; |
PauseTimerEq0_sync2 <= PauseTimerEq0_sync1; |
end |
end |
|
379,10 → 377,10
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
Pause <= #Tp 1'b0; |
Pause <= 1'b0; |
else |
if((TxDoneIn | TxAbortIn | ~TxUsedDataOutDetected) & ~TxStartFrmOut) |
Pause <= #Tp RxFlow & ~PauseTimerEq0_sync2; |
Pause <= RxFlow & ~PauseTimerEq0_sync2; |
end |
|
|
390,12 → 388,12
always @ (posedge MRxClk or posedge RxReset) |
begin |
if(RxReset) |
Divider2 <= #Tp 1'b0; |
Divider2 <= 1'b0; |
else |
if(|PauseTimer[15:0] & RxFlow) |
Divider2 <= #Tp ~Divider2; |
Divider2 <= ~Divider2; |
else |
Divider2 <= #Tp 1'b0; |
Divider2 <= 1'b0; |
end |
|
|
407,13 → 405,13
always @ (posedge MRxClk or posedge RxReset) |
begin |
if(RxReset) |
SlotTimer[5:0] <= #Tp 6'h0; |
SlotTimer[5:0] <= 6'h0; |
else |
if(ResetSlotTimer) |
SlotTimer[5:0] <= #Tp 6'h0; |
SlotTimer[5:0] <= 6'h0; |
else |
if(IncrementSlotTimer) |
SlotTimer[5:0] <= #Tp SlotTimer[5:0] + 1'b1; |
SlotTimer[5:0] <= SlotTimer[5:0] + 1'b1; |
end |
|
|
425,13 → 423,13
always @ (posedge MRxClk or posedge RxReset) |
begin |
if(RxReset) |
ReceivedPauseFrm <=#Tp 1'b0; |
ReceivedPauseFrm <= 1'b0; |
else |
if(RxStatusWriteLatched_sync2 & r_PassAll | ReceivedPauseFrm & (~r_PassAll)) |
ReceivedPauseFrm <=#Tp 1'b0; |
ReceivedPauseFrm <= 1'b0; |
else |
if(ByteCntEq16 & TypeLengthOK & OpCodeOK) |
ReceivedPauseFrm <=#Tp 1'b1; |
ReceivedPauseFrm <= 1'b1; |
end |
|
|
/trunk/rtl/verilog/eth_register.v
94,13 → 94,13
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
DataOut<=#1 RESET_VALUE; |
DataOut<= RESET_VALUE; |
else |
if(SyncReset) |
DataOut<=#1 RESET_VALUE; |
DataOut<= RESET_VALUE; |
else |
if(Write) // write |
DataOut<=#1 DataIn; |
DataOut<= DataIn; |
end |
|
|
/trunk/rtl/verilog/eth_clockgen.v
70,8 → 70,6
|
module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc); |
|
parameter Tp=1; |
|
input Clk; // Input clock (Host clock) |
input Reset; // Reset signal |
input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0]) |
96,15 → 94,15
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
Counter[7:0] <= #Tp 8'h1; |
Counter[7:0] <= 8'h1; |
else |
begin |
if(CountEq0) |
begin |
Counter[7:0] <= #Tp CounterPreset[7:0]; |
Counter[7:0] <= CounterPreset[7:0]; |
end |
else |
Counter[7:0] <= #Tp Counter - 8'h1; |
Counter[7:0] <= Counter - 8'h1; |
end |
end |
|
113,11 → 111,11
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
Mdc <= #Tp 1'b0; |
Mdc <= 1'b0; |
else |
begin |
if(CountEq0) |
Mdc <= #Tp ~Mdc; |
Mdc <= ~Mdc; |
end |
end |
|
/trunk/rtl/verilog/eth_miim.v
135,9 → 135,7
output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register |
output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data |
|
parameter Tp = 1; |
|
|
reg Nvalid; |
reg EndBusy_d; // Pre-end Busy signal |
reg EndBusy; // End Busy signal (stops the operation in progress) |
198,13 → 196,13
begin |
if(Reset) |
begin |
EndBusy_d <= #Tp 1'b0; |
EndBusy <= #Tp 1'b0; |
EndBusy_d <= 1'b0; |
EndBusy <= 1'b0; |
end |
else |
begin |
EndBusy_d <= #Tp ~InProgress_q2 & InProgress_q3; |
EndBusy <= #Tp EndBusy_d; |
EndBusy_d <= ~InProgress_q2 & InProgress_q3; |
EndBusy <= EndBusy_d; |
end |
end |
|
213,12 → 211,12
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
UpdateMIIRX_DATAReg <= #Tp 0; |
UpdateMIIRX_DATAReg <= 0; |
else |
if(EndBusy & ~WCtrlDataStart_q) |
UpdateMIIRX_DATAReg <= #Tp 1; |
UpdateMIIRX_DATAReg <= 1; |
else |
UpdateMIIRX_DATAReg <= #Tp 0; |
UpdateMIIRX_DATAReg <= 0; |
end |
|
|
228,32 → 226,32
begin |
if(Reset) |
begin |
WCtrlData_q1 <= #Tp 1'b0; |
WCtrlData_q2 <= #Tp 1'b0; |
WCtrlData_q3 <= #Tp 1'b0; |
WCtrlData_q1 <= 1'b0; |
WCtrlData_q2 <= 1'b0; |
WCtrlData_q3 <= 1'b0; |
|
RStat_q1 <= #Tp 1'b0; |
RStat_q2 <= #Tp 1'b0; |
RStat_q3 <= #Tp 1'b0; |
RStat_q1 <= 1'b0; |
RStat_q2 <= 1'b0; |
RStat_q3 <= 1'b0; |
|
ScanStat_q1 <= #Tp 1'b0; |
ScanStat_q2 <= #Tp 1'b0; |
SyncStatMdcEn <= #Tp 1'b0; |
ScanStat_q1 <= 1'b0; |
ScanStat_q2 <= 1'b0; |
SyncStatMdcEn <= 1'b0; |
end |
else |
begin |
WCtrlData_q1 <= #Tp WCtrlData; |
WCtrlData_q2 <= #Tp WCtrlData_q1; |
WCtrlData_q3 <= #Tp WCtrlData_q2; |
WCtrlData_q1 <= WCtrlData; |
WCtrlData_q2 <= WCtrlData_q1; |
WCtrlData_q3 <= WCtrlData_q2; |
|
RStat_q1 <= #Tp RStat; |
RStat_q2 <= #Tp RStat_q1; |
RStat_q3 <= #Tp RStat_q2; |
RStat_q1 <= RStat; |
RStat_q2 <= RStat_q1; |
RStat_q3 <= RStat_q2; |
|
ScanStat_q1 <= #Tp ScanStat; |
ScanStat_q2 <= #Tp ScanStat_q1; |
ScanStat_q1 <= ScanStat; |
ScanStat_q2 <= ScanStat_q1; |
if(MdcEn) |
SyncStatMdcEn <= #Tp ScanStat_q2; |
SyncStatMdcEn <= ScanStat_q2; |
end |
end |
|
263,24 → 261,24
begin |
if(Reset) |
begin |
WCtrlDataStart <= #Tp 1'b0; |
WCtrlDataStart_q <= #Tp 1'b0; |
RStatStart <= #Tp 1'b0; |
WCtrlDataStart <= 1'b0; |
WCtrlDataStart_q <= 1'b0; |
RStatStart <= 1'b0; |
end |
else |
begin |
if(EndBusy) |
begin |
WCtrlDataStart <= #Tp 1'b0; |
RStatStart <= #Tp 1'b0; |
WCtrlDataStart <= 1'b0; |
RStatStart <= 1'b0; |
end |
else |
begin |
if(WCtrlData_q2 & ~WCtrlData_q3) |
WCtrlDataStart <= #Tp 1'b1; |
WCtrlDataStart <= 1'b1; |
if(RStat_q2 & ~RStat_q3) |
RStatStart <= #Tp 1'b1; |
WCtrlDataStart_q <= #Tp WCtrlDataStart; |
RStatStart <= 1'b1; |
WCtrlDataStart_q <= WCtrlDataStart; |
end |
end |
end |
290,17 → 288,17
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
Nvalid <= #Tp 1'b0; |
Nvalid <= 1'b0; |
else |
begin |
if(~InProgress_q2 & InProgress_q3) |
begin |
Nvalid <= #Tp 1'b0; |
Nvalid <= 1'b0; |
end |
else |
begin |
if(ScanStat_q2 & ~SyncStatMdcEn) |
Nvalid <= #Tp 1'b1; |
Nvalid <= 1'b1; |
end |
end |
end |
310,40 → 308,40
begin |
if(Reset) |
begin |
WCtrlDataStart_q1 <= #Tp 1'b0; |
WCtrlDataStart_q2 <= #Tp 1'b0; |
WCtrlDataStart_q1 <= 1'b0; |
WCtrlDataStart_q2 <= 1'b0; |
|
RStatStart_q1 <= #Tp 1'b0; |
RStatStart_q2 <= #Tp 1'b0; |
RStatStart_q1 <= 1'b0; |
RStatStart_q2 <= 1'b0; |
|
InProgress_q1 <= #Tp 1'b0; |
InProgress_q2 <= #Tp 1'b0; |
InProgress_q3 <= #Tp 1'b0; |
InProgress_q1 <= 1'b0; |
InProgress_q2 <= 1'b0; |
InProgress_q3 <= 1'b0; |
|
LatchByte0_d <= #Tp 1'b0; |
LatchByte1_d <= #Tp 1'b0; |
LatchByte0_d <= 1'b0; |
LatchByte1_d <= 1'b0; |
|
LatchByte <= #Tp 2'b00; |
LatchByte <= 2'b00; |
end |
else |
begin |
if(MdcEn) |
begin |
WCtrlDataStart_q1 <= #Tp WCtrlDataStart; |
WCtrlDataStart_q2 <= #Tp WCtrlDataStart_q1; |
WCtrlDataStart_q1 <= WCtrlDataStart; |
WCtrlDataStart_q2 <= WCtrlDataStart_q1; |
|
RStatStart_q1 <= #Tp RStatStart; |
RStatStart_q2 <= #Tp RStatStart_q1; |
RStatStart_q1 <= RStatStart; |
RStatStart_q2 <= RStatStart_q1; |
|
LatchByte[0] <= #Tp LatchByte0_d; |
LatchByte[1] <= #Tp LatchByte1_d; |
LatchByte[0] <= LatchByte0_d; |
LatchByte[1] <= LatchByte1_d; |
|
LatchByte0_d <= #Tp LatchByte0_d2; |
LatchByte1_d <= #Tp LatchByte1_d2; |
LatchByte0_d <= LatchByte0_d2; |
LatchByte1_d <= LatchByte1_d2; |
|
InProgress_q1 <= #Tp InProgress; |
InProgress_q2 <= #Tp InProgress_q1; |
InProgress_q3 <= #Tp InProgress_q2; |
InProgress_q1 <= InProgress; |
InProgress_q2 <= InProgress_q1; |
InProgress_q3 <= InProgress_q2; |
end |
end |
end |
365,8 → 363,8
begin |
if(Reset) |
begin |
InProgress <= #Tp 1'b0; |
WriteOp <= #Tp 1'b0; |
InProgress <= 1'b0; |
WriteOp <= 1'b0; |
end |
else |
begin |
375,15 → 373,15
if(StartOp) |
begin |
if(~InProgress) |
WriteOp <= #Tp WriteDataOp; |
InProgress <= #Tp 1'b1; |
WriteOp <= WriteDataOp; |
InProgress <= 1'b1; |
end |
else |
begin |
if(EndOp) |
begin |
InProgress <= #Tp 1'b0; |
WriteOp <= #Tp 1'b0; |
InProgress <= 1'b0; |
WriteOp <= 1'b0; |
end |
end |
end |
396,7 → 394,7
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
BitCounter[6:0] <= #Tp 7'h0; |
BitCounter[6:0] <= 7'h0; |
else |
begin |
if(MdcEn) |
404,12 → 402,12
if(InProgress) |
begin |
if(NoPre & ( BitCounter == 7'h0 )) |
BitCounter[6:0] <= #Tp 7'h21; |
BitCounter[6:0] <= 7'h21; |
else |
BitCounter[6:0] <= #Tp BitCounter[6:0] + 1'b1; |
BitCounter[6:0] <= BitCounter[6:0] + 1'b1; |
end |
else |
BitCounter[6:0] <= #Tp 7'h0; |
BitCounter[6:0] <= 7'h0; |
end |
end |
end |
430,20 → 428,17
|
|
// Connecting the Clock Generator Module |
eth_clockgen #(.Tp(Tp)) |
clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc) |
eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc) |
); |
|
// Connecting the Shift Register Module |
eth_shiftreg #(.Tp(Tp)) |
shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad), |
eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad), |
.CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte), |
.ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail) |
); |
|
// Connecting the Output Control Module |
eth_outputcontrol #(.Tp(Tp)) |
outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress), |
eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress), |
.ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre), |
.Mdo(Mdo), .MdoEn(MdoEn) |
); |
/trunk/rtl/verilog/eth_outputcontrol.v
70,8 → 70,6
|
module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn); |
|
parameter Tp = 1; |
|
input Clk; // Host Clock |
input Reset; // General Reset |
input WriteOp; // Write Operation Latch (When asserted, write operation is in progress) |
106,17 → 104,17
begin |
if(Reset) |
begin |
MdoEn_2d <= #Tp 1'b0; |
MdoEn_d <= #Tp 1'b0; |
MdoEn <= #Tp 1'b0; |
MdoEn_2d <= 1'b0; |
MdoEn_d <= 1'b0; |
MdoEn <= 1'b0; |
end |
else |
begin |
if(MdcEn_n) |
begin |
MdoEn_2d <= #Tp SerialEn | InProgress & BitCounter<32; |
MdoEn_d <= #Tp MdoEn_2d; |
MdoEn <= #Tp MdoEn_d; |
MdoEn_2d <= SerialEn | InProgress & BitCounter<32; |
MdoEn_d <= MdoEn_2d; |
MdoEn <= MdoEn_d; |
end |
end |
end |
127,17 → 125,17
begin |
if(Reset) |
begin |
Mdo_2d <= #Tp 1'b0; |
Mdo_d <= #Tp 1'b0; |
Mdo <= #Tp 1'b0; |
Mdo_2d <= 1'b0; |
Mdo_d <= 1'b0; |
Mdo <= 1'b0; |
end |
else |
begin |
if(MdcEn_n) |
begin |
Mdo_2d <= #Tp ~SerialEn & BitCounter<32; |
Mdo_d <= #Tp ShiftedBit | Mdo_2d; |
Mdo <= #Tp Mdo_d; |
Mdo_2d <= ~SerialEn & BitCounter<32; |
Mdo_d <= ShiftedBit | Mdo_2d; |
Mdo <= Mdo_d; |
end |
end |
end |
/trunk/rtl/verilog/eth_maccontrol.v
94,9 → 94,7
); |
|
|
parameter Tp = 1; |
|
|
input MTxClk; // Transmit clock (from PHY) |
input MRxClk; // Receive clock (from PHY) |
input TxReset; // Transmit reset |
157,13 → 155,13
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
TxUsedDataOutDetected <= #Tp 1'b0; |
TxUsedDataOutDetected <= 1'b0; |
else |
if(TxDoneIn | TxAbortIn) |
TxUsedDataOutDetected <= #Tp 1'b0; |
TxUsedDataOutDetected <= 1'b0; |
else |
if(TxUsedDataOut) |
TxUsedDataOutDetected <= #Tp 1'b1; |
TxUsedDataOutDetected <= 1'b1; |
end |
|
|
172,13 → 170,13
begin |
if(TxReset) |
begin |
TxAbortInLatched <= #Tp 1'b0; |
TxDoneInLatched <= #Tp 1'b0; |
TxAbortInLatched <= 1'b0; |
TxDoneInLatched <= 1'b0; |
end |
else |
begin |
TxAbortInLatched <= #Tp TxAbortIn; |
TxDoneInLatched <= #Tp TxDoneIn; |
TxAbortInLatched <= TxAbortIn; |
TxDoneInLatched <= TxDoneIn; |
end |
end |
|
188,13 → 186,13
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
MuxedAbort <= #Tp 1'b0; |
MuxedAbort <= 1'b0; |
else |
if(TxStartFrmIn) |
MuxedAbort <= #Tp 1'b0; |
MuxedAbort <= 1'b0; |
else |
if(TxAbortIn & ~TxAbortInLatched & TxUsedDataOutDetected) |
MuxedAbort <= #Tp 1'b1; |
MuxedAbort <= 1'b1; |
end |
|
|
202,13 → 200,13
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
MuxedDone <= #Tp 1'b0; |
MuxedDone <= 1'b0; |
else |
if(TxStartFrmIn) |
MuxedDone <= #Tp 1'b0; |
MuxedDone <= 1'b0; |
else |
if(TxDoneIn & (~TxDoneInLatched) & TxUsedDataOutDetected) |
MuxedDone <= #Tp 1'b1; |
MuxedDone <= 1'b1; |
end |
|
|
245,8 → 243,7
|
|
// Connecting receivecontrol module |
eth_receivecontrol #(.Tp(Tp)) |
receivecontrol1 |
eth_receivecontrol receivecontrol1 |
( |
.MTxClk(MTxClk), .MRxClk(MRxClk), .TxReset(TxReset), .RxReset(RxReset), .RxData(RxData), |
.RxValid(RxValid), .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm), .RxFlow(RxFlow), |
258,8 → 255,7
); |
|
|
eth_transmitcontrol #(.Tp(Tp)) |
transmitcontrol1 |
eth_transmitcontrol transmitcontrol1 |
( |
.MTxClk(MTxClk), .TxReset(TxReset), .TxUsedDataIn(TxUsedDataIn), .TxUsedDataOut(TxUsedDataOut), |
.TxDoneIn(TxDoneIn), .TxAbortIn(TxAbortIn), .TxStartFrmIn(TxStartFrmIn), .TPauseRq(TPauseRq), |
/trunk/rtl/verilog/eth_top.v
278,7 → 278,6
); |
|
|
parameter Tp = 1; |
parameter TX_FIFO_DATA_WIDTH = `ETH_TX_FIFO_DATA_WIDTH; |
parameter TX_FIFO_DEPTH = `ETH_TX_FIFO_DEPTH; |
parameter TX_FIFO_CNT_WIDTH = `ETH_TX_FIFO_CNT_WIDTH; |
389,8 → 388,7
|
|
// Connecting Miim module |
eth_miim #(.Tp(Tp)) |
miim1 |
eth_miim miim1 |
( |
.Clk(wb_clk_i), .Reset(wb_rst_i), .Divider(r_ClkDiv), |
.NoPre(r_MiiNoPre), .CtrlData(r_CtrlData), .Rgad(r_RGAD), |
534,15 → 532,15
begin |
if(wb_rst_i) |
begin |
temp_wb_ack_o_reg <=#Tp 1'b0; |
temp_wb_dat_o_reg <=#Tp 32'h0; |
temp_wb_err_o_reg <=#Tp 1'b0; |
temp_wb_ack_o_reg <= 1'b0; |
temp_wb_dat_o_reg <= 32'h0; |
temp_wb_err_o_reg <= 1'b0; |
end |
else |
begin |
temp_wb_ack_o_reg <=#Tp temp_wb_ack_o & ~temp_wb_ack_o_reg; |
temp_wb_dat_o_reg <=#Tp temp_wb_dat_o; |
temp_wb_err_o_reg <=#Tp temp_wb_err_o & ~temp_wb_err_o_reg; |
temp_wb_ack_o_reg <= temp_wb_ack_o & ~temp_wb_ack_o_reg; |
temp_wb_dat_o_reg <= temp_wb_dat_o; |
temp_wb_err_o_reg <= temp_wb_err_o & ~temp_wb_err_o_reg; |
end |
end |
`endif |
549,8 → 547,7
|
|
// Connecting Ethernet registers |
eth_registers #(.Tp(Tp)) |
ethreg1 |
eth_registers ethreg1 |
( |
.DataIn(wb_dat_i), .Address(wb_adr_i[9:2]), .Rw(wb_we_i), |
.Cs(RegCs), .Clk(wb_clk_i), .Reset(wb_rst_i), |
607,8 → 604,7
wire [1:0] StateData; |
|
// Connecting MACControl |
eth_maccontrol #(.Tp(Tp)) |
maccontrol1 |
eth_maccontrol maccontrol1 |
( |
.MTxClk(mtx_clk_pad_i), .TPauseRq(TPauseRq), |
.TxPauseTV(r_TxPauseTV), .TxDataIn(TxData), |
661,8 → 657,7
|
|
// Connecting TxEthMAC |
eth_txethmac #(.Tp(Tp)) |
txethmac1 |
eth_txethmac txethmac1 |
( |
.MTxClk(mtx_clk_pad_i), .Reset(wb_rst_i), .CarrierSense(TxCarrierSense), |
.Collision(Collision), .TxData(TxDataOut), .TxStartFrm(TxStartFrmOut), |
696,8 → 691,7
|
|
// Connecting RxEthMAC |
eth_rxethmac #(.Tp(Tp)) |
rxethmac1 |
eth_rxethmac rxethmac1 |
( |
.MRxClk(mrx_clk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb), |
.Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn), |
718,13 → 712,13
begin |
if(wb_rst_i) |
begin |
CarrierSense_Tx1 <= #Tp 1'b0; |
CarrierSense_Tx2 <= #Tp 1'b0; |
CarrierSense_Tx1 <= 1'b0; |
CarrierSense_Tx2 <= 1'b0; |
end |
else |
begin |
CarrierSense_Tx1 <= #Tp mcrs_pad_i; |
CarrierSense_Tx2 <= #Tp CarrierSense_Tx1; |
CarrierSense_Tx1 <= mcrs_pad_i; |
CarrierSense_Tx2 <= CarrierSense_Tx1; |
end |
end |
|
736,17 → 730,17
begin |
if(wb_rst_i) |
begin |
Collision_Tx1 <= #Tp 1'b0; |
Collision_Tx2 <= #Tp 1'b0; |
Collision_Tx1 <= 1'b0; |
Collision_Tx2 <= 1'b0; |
end |
else |
begin |
Collision_Tx1 <= #Tp mcoll_pad_i; |
Collision_Tx1 <= mcoll_pad_i; |
if(ResetCollision) |
Collision_Tx2 <= #Tp 1'b0; |
Collision_Tx2 <= 1'b0; |
else |
if(Collision_Tx1) |
Collision_Tx2 <= #Tp 1'b1; |
Collision_Tx2 <= 1'b1; |
end |
end |
|
759,8 → 753,8
// Delayed WillTransmit |
always @ (posedge mrx_clk_pad_i) |
begin |
WillTransmit_q <= #Tp WillTransmit; |
WillTransmit_q2 <= #Tp WillTransmit_q; |
WillTransmit_q <= WillTransmit; |
WillTransmit_q2 <= WillTransmit_q; |
end |
|
|
772,10 → 766,10
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
RxEnSync <= #Tp 1'b0; |
RxEnSync <= 1'b0; |
else |
if(~mrxdv_pad_i) |
RxEnSync <= #Tp r_RxEn; |
RxEnSync <= r_RxEn; |
end |
|
|
786,7 → 780,7
if(wb_rst_i) |
WillSendControlFrame_sync1 <= 1'b0; |
else |
WillSendControlFrame_sync1 <=#Tp WillSendControlFrame; |
WillSendControlFrame_sync1 <= WillSendControlFrame; |
end |
|
always @ (posedge wb_clk_i or posedge wb_rst_i) |
794,7 → 788,7
if(wb_rst_i) |
WillSendControlFrame_sync2 <= 1'b0; |
else |
WillSendControlFrame_sync2 <=#Tp WillSendControlFrame_sync1; |
WillSendControlFrame_sync2 <= WillSendControlFrame_sync1; |
end |
|
always @ (posedge wb_clk_i or posedge wb_rst_i) |
802,7 → 796,7
if(wb_rst_i) |
WillSendControlFrame_sync3 <= 1'b0; |
else |
WillSendControlFrame_sync3 <=#Tp WillSendControlFrame_sync2; |
WillSendControlFrame_sync3 <= WillSendControlFrame_sync2; |
end |
|
always @ (posedge wb_clk_i or posedge wb_rst_i) |
810,7 → 804,7
if(wb_rst_i) |
RstTxPauseRq <= 1'b0; |
else |
RstTxPauseRq <=#Tp WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3; |
RstTxPauseRq <= WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3; |
end |
|
|
821,15 → 815,15
begin |
if(wb_rst_i) |
begin |
TxPauseRq_sync1 <= #Tp 1'b0; |
TxPauseRq_sync2 <= #Tp 1'b0; |
TxPauseRq_sync3 <= #Tp 1'b0; |
TxPauseRq_sync1 <= 1'b0; |
TxPauseRq_sync2 <= 1'b0; |
TxPauseRq_sync3 <= 1'b0; |
end |
else |
begin |
TxPauseRq_sync1 <= #Tp (r_TxPauseRq & r_TxFlow); |
TxPauseRq_sync2 <= #Tp TxPauseRq_sync1; |
TxPauseRq_sync3 <= #Tp TxPauseRq_sync2; |
TxPauseRq_sync1 <= (r_TxPauseRq & r_TxFlow); |
TxPauseRq_sync2 <= TxPauseRq_sync1; |
TxPauseRq_sync3 <= TxPauseRq_sync2; |
end |
end |
|
837,9 → 831,9
always @ (posedge mtx_clk_pad_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
TPauseRq <= #Tp 1'b0; |
TPauseRq <= 1'b0; |
else |
TPauseRq <= #Tp TxPauseRq_sync2 & (~TxPauseRq_sync3); |
TPauseRq <= TxPauseRq_sync2 & (~TxPauseRq_sync3); |
end |
|
|
854,11 → 848,11
always @ (posedge mrx_clk_pad_i or posedge wb_rst_i) |
begin |
if(wb_rst_i) |
RxAbort_latch <= #Tp 1'b0; |
RxAbort_latch <= 1'b0; |
else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll))) |
RxAbort_latch <= #Tp 1'b1; |
RxAbort_latch <= 1'b1; |
else if(RxAbortRst) |
RxAbort_latch <= #Tp 1'b0; |
RxAbort_latch <= 1'b0; |
end |
|
always @ (posedge wb_clk_i or posedge wb_rst_i) |
865,14 → 859,14
begin |
if(wb_rst_i) |
begin |
RxAbort_sync1 <= #Tp 1'b0; |
RxAbort_wb <= #Tp 1'b0; |
RxAbort_wb <= #Tp 1'b0; |
RxAbort_sync1 <= 1'b0; |
RxAbort_wb <= 1'b0; |
RxAbort_wb <= 1'b0; |
end |
else |
begin |
RxAbort_sync1 <= #Tp RxAbort_latch; |
RxAbort_wb <= #Tp RxAbort_sync1; |
RxAbort_sync1 <= RxAbort_latch; |
RxAbort_wb <= RxAbort_sync1; |
end |
end |
|
880,13 → 874,13
begin |
if(wb_rst_i) |
begin |
RxAbortRst_sync1 <= #Tp 1'b0; |
RxAbortRst <= #Tp 1'b0; |
RxAbortRst_sync1 <= 1'b0; |
RxAbortRst <= 1'b0; |
end |
else |
begin |
RxAbortRst_sync1 <= #Tp RxAbort_wb; |
RxAbortRst <= #Tp RxAbortRst_sync1; |
RxAbortRst_sync1 <= RxAbort_wb; |
RxAbortRst <= RxAbortRst_sync1; |
end |
end |
|
893,8 → 887,7
|
|
// Connecting Wishbone module |
eth_wishbone #(.Tp(Tp), |
.TX_FIFO_DATA_WIDTH(TX_FIFO_DATA_WIDTH), |
eth_wishbone #(.TX_FIFO_DATA_WIDTH(TX_FIFO_DATA_WIDTH), |
.TX_FIFO_DEPTH (TX_FIFO_DEPTH), |
.TX_FIFO_CNT_WIDTH (TX_FIFO_CNT_WIDTH), |
.RX_FIFO_DATA_WIDTH(RX_FIFO_DATA_WIDTH), |
959,8 → 952,7
assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0}; |
|
// Connecting MacStatus module |
eth_macstatus #(.Tp(Tp)) |
macstatus1 |
eth_macstatus macstatus1 |
( |
.MRxClk(mrx_clk_pad_i), .Reset(wb_rst_i), |
.ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK), |
/trunk/rtl/verilog/eth_transmitcontrol.v
88,9 → 88,7
ControlData, WillSendControlFrame, BlockTxDone |
); |
|
parameter Tp = 1; |
|
|
input MTxClk; |
input TxReset; |
input TxUsedDataIn; |
139,13 → 137,13
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
WillSendControlFrame <= #Tp 1'b0; |
WillSendControlFrame <= 1'b0; |
else |
if(TxCtrlEndFrm & CtrlMux) |
WillSendControlFrame <= #Tp 1'b0; |
WillSendControlFrame <= 1'b0; |
else |
if(TPauseRq & TxFlow) |
WillSendControlFrame <= #Tp 1'b1; |
WillSendControlFrame <= 1'b1; |
end |
|
|
153,13 → 151,13
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
TxCtrlStartFrm <= #Tp 1'b0; |
TxCtrlStartFrm <= 1'b0; |
else |
if(TxUsedDataIn_q & CtrlMux) |
TxCtrlStartFrm <= #Tp 1'b0; |
TxCtrlStartFrm <= 1'b0; |
else |
if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn | TxAbortIn | TxStartFrmIn | (~TxUsedDataOutDetected))) |
TxCtrlStartFrm <= #Tp 1'b1; |
TxCtrlStartFrm <= 1'b1; |
end |
|
|
168,12 → 166,12
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
TxCtrlEndFrm <= #Tp 1'b0; |
TxCtrlEndFrm <= 1'b0; |
else |
if(ControlEnd | ControlEnd_q) |
TxCtrlEndFrm <= #Tp 1'b1; |
TxCtrlEndFrm <= 1'b1; |
else |
TxCtrlEndFrm <= #Tp 1'b0; |
TxCtrlEndFrm <= 1'b0; |
end |
|
|
182,13 → 180,13
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
CtrlMux <= #Tp 1'b0; |
CtrlMux <= 1'b0; |
else |
if(WillSendControlFrame & ~TxUsedDataOut) |
CtrlMux <= #Tp 1'b1; |
CtrlMux <= 1'b1; |
else |
if(TxDoneIn) |
CtrlMux <= #Tp 1'b0; |
CtrlMux <= 1'b0; |
end |
|
|
197,13 → 195,13
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
SendingCtrlFrm <= #Tp 1'b0; |
SendingCtrlFrm <= 1'b0; |
else |
if(WillSendControlFrame & TxCtrlStartFrm) |
SendingCtrlFrm <= #Tp 1'b1; |
SendingCtrlFrm <= 1'b1; |
else |
if(TxDoneIn) |
SendingCtrlFrm <= #Tp 1'b0; |
SendingCtrlFrm <= 1'b0; |
end |
|
|
210,9 → 208,9
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
TxUsedDataIn_q <= #Tp 1'b0; |
TxUsedDataIn_q <= 1'b0; |
else |
TxUsedDataIn_q <= #Tp TxUsedDataIn; |
TxUsedDataIn_q <= TxUsedDataIn; |
end |
|
|
222,20 → 220,20
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
BlockTxDone <= #Tp 1'b0; |
BlockTxDone <= 1'b0; |
else |
if(TxCtrlStartFrm) |
BlockTxDone <= #Tp 1'b1; |
BlockTxDone <= 1'b1; |
else |
if(TxStartFrmIn) |
BlockTxDone <= #Tp 1'b0; |
BlockTxDone <= 1'b0; |
end |
|
|
always @ (posedge MTxClk) |
begin |
ControlEnd_q <= #Tp ControlEnd; |
TxCtrlStartFrm_q <= #Tp TxCtrlStartFrm; |
ControlEnd_q <= ControlEnd; |
TxCtrlStartFrm_q <= TxCtrlStartFrm; |
end |
|
|
246,13 → 244,13
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
DlyCrcCnt <= #Tp 4'h0; |
DlyCrcCnt <= 4'h0; |
else |
if(ResetByteCnt) |
DlyCrcCnt <= #Tp 4'h0; |
DlyCrcCnt <= 4'h0; |
else |
if(IncrementDlyCrcCnt) |
DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1; |
DlyCrcCnt <= DlyCrcCnt + 1'b1; |
end |
|
|
265,16 → 263,16
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
ByteCnt <= #Tp 6'h0; |
ByteCnt <= 6'h0; |
else |
if(ResetByteCnt) |
ByteCnt <= #Tp 6'h0; |
ByteCnt <= 6'h0; |
else |
if(IncrementByteCntBy2 & EnableCnt) |
ByteCnt <= #Tp (ByteCnt[5:0] ) + 2'h2; |
ByteCnt <= (ByteCnt[5:0] ) + 2'h2; |
else |
if(IncrementByteCnt & EnableCnt) |
ByteCnt <= #Tp (ByteCnt[5:0] ) + 1'b1; |
ByteCnt <= (ByteCnt[5:0] ) + 1'b1; |
end |
|
|
315,10 → 313,10
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
ControlData[7:0] <= #Tp 8'h0; |
ControlData[7:0] <= 8'h0; |
else |
if(~ByteCnt[0]) |
ControlData[7:0] <= #Tp MuxedCtrlData[7:0]; |
ControlData[7:0] <= MuxedCtrlData[7:0]; |
end |
|
|
/trunk/rtl/verilog/eth_macstatus.v
126,9 → 126,7
|
|
|
parameter Tp = 1; |
|
|
input MRxClk; |
input Reset; |
input RxCrcError; |
205,13 → 203,13
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
LatchedCrcError <=#Tp 1'b0; |
LatchedCrcError <= 1'b0; |
else |
if(RxStateSFD) |
LatchedCrcError <=#Tp 1'b0; |
LatchedCrcError <= 1'b0; |
else |
if(RxStateData[0]) |
LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0; |
LatchedCrcError <= RxCrcError & ~RxByteCntEq0; |
end |
|
|
219,12 → 217,12
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
LatchedMRxErr <=#Tp 1'b0; |
LatchedMRxErr <= 1'b0; |
else |
if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting)) |
LatchedMRxErr <=#Tp 1'b1; |
LatchedMRxErr <= 1'b1; |
else |
LatchedMRxErr <=#Tp 1'b0; |
LatchedMRxErr <= 1'b0; |
end |
|
|
249,9 → 247,9
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
LoadRxStatus <=#Tp 1'b0; |
LoadRxStatus <= 1'b0; |
else |
LoadRxStatus <=#Tp TakeSample; |
LoadRxStatus <= TakeSample; |
end |
|
|
260,9 → 258,9
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ReceiveEnd <=#Tp 1'b0; |
ReceiveEnd <= 1'b0; |
else |
ReceiveEnd <=#Tp LoadRxStatus; |
ReceiveEnd <= LoadRxStatus; |
end |
|
|
274,13 → 272,13
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
InvalidSymbol <=#Tp 1'b0; |
InvalidSymbol <= 1'b0; |
else |
if(LoadRxStatus & ~SetInvalidSymbol) |
InvalidSymbol <=#Tp 1'b0; |
InvalidSymbol <= 1'b0; |
else |
if(SetInvalidSymbol) |
InvalidSymbol <=#Tp 1'b1; |
InvalidSymbol <= 1'b1; |
end |
|
|
292,13 → 290,13
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxLateCollision <=#Tp 1'b0; |
RxLateCollision <= 1'b0; |
else |
if(LoadRxStatus) |
RxLateCollision <=#Tp 1'b0; |
RxLateCollision <= 1'b0; |
else |
if(Collision & (~r_FullD) & (~RxColWindow | r_RecSmall)) |
RxLateCollision <=#Tp 1'b1; |
RxLateCollision <= 1'b1; |
end |
|
// Collision Window |
305,13 → 303,13
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxColWindow <=#Tp 1'b1; |
RxColWindow <= 1'b1; |
else |
if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1]) |
RxColWindow <=#Tp 1'b0; |
RxColWindow <= 1'b0; |
else |
if(RxStateIdle) |
RxColWindow <=#Tp 1'b1; |
RxColWindow <= 1'b1; |
end |
|
|
320,13 → 318,13
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ShortFrame <=#Tp 1'b0; |
ShortFrame <= 1'b0; |
else |
if(LoadRxStatus) |
ShortFrame <=#Tp 1'b0; |
ShortFrame <= 1'b0; |
else |
if(TakeSample) |
ShortFrame <=#Tp RxByteCnt[15:0] < r_MinFL[15:0]; |
ShortFrame <= RxByteCnt[15:0] < r_MinFL[15:0]; |
end |
|
|
335,13 → 333,13
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
DribbleNibble <=#Tp 1'b0; |
DribbleNibble <= 1'b0; |
else |
if(RxStateSFD) |
DribbleNibble <=#Tp 1'b0; |
DribbleNibble <= 1'b0; |
else |
if(~MRxDV & RxStateData[1]) |
DribbleNibble <=#Tp 1'b1; |
DribbleNibble <= 1'b1; |
end |
|
|
349,13 → 347,13
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ReceivedPacketTooBig <=#Tp 1'b0; |
ReceivedPacketTooBig <= 1'b0; |
else |
if(LoadRxStatus) |
ReceivedPacketTooBig <=#Tp 1'b0; |
ReceivedPacketTooBig <= 1'b0; |
else |
if(TakeSample) |
ReceivedPacketTooBig <=#Tp ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0]; |
ReceivedPacketTooBig <= ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0]; |
end |
|
|
364,10 → 362,10
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
RetryCntLatched <=#Tp 4'h0; |
RetryCntLatched <= 4'h0; |
else |
if(StartTxDone | StartTxAbort) |
RetryCntLatched <=#Tp RetryCnt; |
RetryCntLatched <= RetryCnt; |
end |
|
|
375,10 → 373,10
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
RetryLimit <=#Tp 1'h0; |
RetryLimit <= 1'h0; |
else |
if(StartTxDone | StartTxAbort) |
RetryLimit <=#Tp MaxCollisionOccured; |
RetryLimit <= MaxCollisionOccured; |
end |
|
|
386,10 → 384,10
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
LateCollLatched <=#Tp 1'b0; |
LateCollLatched <= 1'b0; |
else |
if(StartTxDone | StartTxAbort) |
LateCollLatched <=#Tp LateCollision; |
LateCollLatched <= LateCollision; |
end |
|
|
398,13 → 396,13
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
DeferLatched <=#Tp 1'b0; |
DeferLatched <= 1'b0; |
else |
if(DeferIndication) |
DeferLatched <=#Tp 1'b1; |
DeferLatched <= 1'b1; |
else |
if(RstDeferLatched) |
DeferLatched <=#Tp 1'b0; |
DeferLatched <= 1'b0; |
end |
|
|
412,13 → 410,13
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
CarrierSenseLost <=#Tp 1'b0; |
CarrierSenseLost <= 1'b0; |
else |
if((StatePreamble | (|StateData)) & ~CarrierSense & ~Loopback & ~Collision & ~r_FullD) |
CarrierSenseLost <=#Tp 1'b1; |
CarrierSenseLost <= 1'b1; |
else |
if(TxStartFrm) |
CarrierSenseLost <=#Tp 1'b0; |
CarrierSenseLost <= 1'b0; |
end |
|
|
/trunk/rtl/verilog/eth_registers.v
181,8 → 181,6
StartTxDone, TxClk, RxClk, SetPauseTimer |
); |
|
parameter Tp = 1; |
|
input [31:0] DataIn; |
input [7:0] Address; |
|
948,13 → 946,13
always @ (posedge TxClk or posedge Reset) |
begin |
if(Reset) |
SetTxCIrq_txclk <=#Tp 1'b0; |
SetTxCIrq_txclk <= 1'b0; |
else |
if(TxCtrlEndFrm & StartTxDone & r_TxFlow) |
SetTxCIrq_txclk <=#Tp 1'b1; |
SetTxCIrq_txclk <= 1'b1; |
else |
if(ResetTxCIrq_sync2) |
SetTxCIrq_txclk <=#Tp 1'b0; |
SetTxCIrq_txclk <= 1'b0; |
end |
|
|
961,49 → 959,49
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
SetTxCIrq_sync1 <=#Tp 1'b0; |
SetTxCIrq_sync1 <= 1'b0; |
else |
SetTxCIrq_sync1 <=#Tp SetTxCIrq_txclk; |
SetTxCIrq_sync1 <= SetTxCIrq_txclk; |
end |
|
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
SetTxCIrq_sync2 <=#Tp 1'b0; |
SetTxCIrq_sync2 <= 1'b0; |
else |
SetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1; |
SetTxCIrq_sync2 <= SetTxCIrq_sync1; |
end |
|
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
SetTxCIrq_sync3 <=#Tp 1'b0; |
SetTxCIrq_sync3 <= 1'b0; |
else |
SetTxCIrq_sync3 <=#Tp SetTxCIrq_sync2; |
SetTxCIrq_sync3 <= SetTxCIrq_sync2; |
end |
|
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
SetTxCIrq <=#Tp 1'b0; |
SetTxCIrq <= 1'b0; |
else |
SetTxCIrq <=#Tp SetTxCIrq_sync2 & ~SetTxCIrq_sync3; |
SetTxCIrq <= SetTxCIrq_sync2 & ~SetTxCIrq_sync3; |
end |
|
always @ (posedge TxClk or posedge Reset) |
begin |
if(Reset) |
ResetTxCIrq_sync1 <=#Tp 1'b0; |
ResetTxCIrq_sync1 <= 1'b0; |
else |
ResetTxCIrq_sync1 <=#Tp SetTxCIrq_sync2; |
ResetTxCIrq_sync1 <= SetTxCIrq_sync2; |
end |
|
always @ (posedge TxClk or posedge Reset) |
begin |
if(Reset) |
ResetTxCIrq_sync2 <=#Tp 1'b0; |
ResetTxCIrq_sync2 <= 1'b0; |
else |
ResetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1; |
ResetTxCIrq_sync2 <= SetTxCIrq_sync1; |
end |
|
|
1011,13 → 1009,13
always @ (posedge RxClk or posedge Reset) |
begin |
if(Reset) |
SetRxCIrq_rxclk <=#Tp 1'b0; |
SetRxCIrq_rxclk <= 1'b0; |
else |
if(SetPauseTimer & r_RxFlow) |
SetRxCIrq_rxclk <=#Tp 1'b1; |
SetRxCIrq_rxclk <= 1'b1; |
else |
if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3)) |
SetRxCIrq_rxclk <=#Tp 1'b0; |
SetRxCIrq_rxclk <= 1'b0; |
end |
|
|
1024,57 → 1022,57
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
SetRxCIrq_sync1 <=#Tp 1'b0; |
SetRxCIrq_sync1 <= 1'b0; |
else |
SetRxCIrq_sync1 <=#Tp SetRxCIrq_rxclk; |
SetRxCIrq_sync1 <= SetRxCIrq_rxclk; |
end |
|
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
SetRxCIrq_sync2 <=#Tp 1'b0; |
SetRxCIrq_sync2 <= 1'b0; |
else |
SetRxCIrq_sync2 <=#Tp SetRxCIrq_sync1; |
SetRxCIrq_sync2 <= SetRxCIrq_sync1; |
end |
|
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
SetRxCIrq_sync3 <=#Tp 1'b0; |
SetRxCIrq_sync3 <= 1'b0; |
else |
SetRxCIrq_sync3 <=#Tp SetRxCIrq_sync2; |
SetRxCIrq_sync3 <= SetRxCIrq_sync2; |
end |
|
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
SetRxCIrq <=#Tp 1'b0; |
SetRxCIrq <= 1'b0; |
else |
SetRxCIrq <=#Tp SetRxCIrq_sync2 & ~SetRxCIrq_sync3; |
SetRxCIrq <= SetRxCIrq_sync2 & ~SetRxCIrq_sync3; |
end |
|
always @ (posedge RxClk or posedge Reset) |
begin |
if(Reset) |
ResetRxCIrq_sync1 <=#Tp 1'b0; |
ResetRxCIrq_sync1 <= 1'b0; |
else |
ResetRxCIrq_sync1 <=#Tp SetRxCIrq_sync2; |
ResetRxCIrq_sync1 <= SetRxCIrq_sync2; |
end |
|
always @ (posedge RxClk or posedge Reset) |
begin |
if(Reset) |
ResetRxCIrq_sync2 <=#Tp 1'b0; |
ResetRxCIrq_sync2 <= 1'b0; |
else |
ResetRxCIrq_sync2 <=#Tp ResetRxCIrq_sync1; |
ResetRxCIrq_sync2 <= ResetRxCIrq_sync1; |
end |
|
always @ (posedge RxClk or posedge Reset) |
begin |
if(Reset) |
ResetRxCIrq_sync3 <=#Tp 1'b0; |
ResetRxCIrq_sync3 <= 1'b0; |
else |
ResetRxCIrq_sync3 <=#Tp ResetRxCIrq_sync2; |
ResetRxCIrq_sync3 <= ResetRxCIrq_sync2; |
end |
|
|
1086,10 → 1084,10
irq_txb <= 1'b0; |
else |
if(TxB_IRQ) |
irq_txb <= #Tp 1'b1; |
irq_txb <= 1'b1; |
else |
if(INT_SOURCE_Wr[0] & DataIn[0]) |
irq_txb <= #Tp 1'b0; |
irq_txb <= 1'b0; |
end |
|
always @ (posedge Clk or posedge Reset) |
1098,10 → 1096,10
irq_txe <= 1'b0; |
else |
if(TxE_IRQ) |
irq_txe <= #Tp 1'b1; |
irq_txe <= 1'b1; |
else |
if(INT_SOURCE_Wr[0] & DataIn[1]) |
irq_txe <= #Tp 1'b0; |
irq_txe <= 1'b0; |
end |
|
always @ (posedge Clk or posedge Reset) |
1110,10 → 1108,10
irq_rxb <= 1'b0; |
else |
if(RxB_IRQ) |
irq_rxb <= #Tp 1'b1; |
irq_rxb <= 1'b1; |
else |
if(INT_SOURCE_Wr[0] & DataIn[2]) |
irq_rxb <= #Tp 1'b0; |
irq_rxb <= 1'b0; |
end |
|
always @ (posedge Clk or posedge Reset) |
1122,10 → 1120,10
irq_rxe <= 1'b0; |
else |
if(RxE_IRQ) |
irq_rxe <= #Tp 1'b1; |
irq_rxe <= 1'b1; |
else |
if(INT_SOURCE_Wr[0] & DataIn[3]) |
irq_rxe <= #Tp 1'b0; |
irq_rxe <= 1'b0; |
end |
|
always @ (posedge Clk or posedge Reset) |
1134,10 → 1132,10
irq_busy <= 1'b0; |
else |
if(Busy_IRQ) |
irq_busy <= #Tp 1'b1; |
irq_busy <= 1'b1; |
else |
if(INT_SOURCE_Wr[0] & DataIn[4]) |
irq_busy <= #Tp 1'b0; |
irq_busy <= 1'b0; |
end |
|
always @ (posedge Clk or posedge Reset) |
1146,10 → 1144,10
irq_txc <= 1'b0; |
else |
if(SetTxCIrq) |
irq_txc <= #Tp 1'b1; |
irq_txc <= 1'b1; |
else |
if(INT_SOURCE_Wr[0] & DataIn[5]) |
irq_txc <= #Tp 1'b0; |
irq_txc <= 1'b0; |
end |
|
always @ (posedge Clk or posedge Reset) |
1158,10 → 1156,10
irq_rxc <= 1'b0; |
else |
if(SetRxCIrq) |
irq_rxc <= #Tp 1'b1; |
irq_rxc <= 1'b1; |
else |
if(INT_SOURCE_Wr[0] & DataIn[6]) |
irq_rxc <= #Tp 1'b0; |
irq_rxc <= 1'b0; |
end |
|
// Generating interrupt signal |
/trunk/rtl/verilog/eth_crc.v
79,8 → 79,6
module eth_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError); |
|
|
parameter Tp = 1; |
|
input Clk; |
input Reset; |
input [3:0] Data; |
132,12 → 130,12
always @ (posedge Clk or posedge Reset) |
begin |
if (Reset) |
Crc <= #1 32'hffffffff; |
Crc <= 32'hffffffff; |
else |
if(Initialize) |
Crc <= #Tp 32'hffffffff; |
Crc <= 32'hffffffff; |
else |
Crc <= #Tp CrcNext; |
Crc <= CrcNext; |
end |
|
assign CrcError = Crc[31:0] != 32'hc704dd7b; // CRC not equal to magic number |
/trunk/rtl/verilog/eth_rxstatem.v
90,8 → 90,6
StateDrop |
); |
|
parameter Tp = 1; |
|
input MRxClk; |
input Reset; |
input MRxDV; |
144,50 → 142,50
begin |
if(Reset) |
begin |
StateIdle <= #Tp 1'b0; |
StateDrop <= #Tp 1'b1; |
StatePreamble <= #Tp 1'b0; |
StateSFD <= #Tp 1'b0; |
StateData0 <= #Tp 1'b0; |
StateData1 <= #Tp 1'b0; |
StateIdle <= 1'b0; |
StateDrop <= 1'b1; |
StatePreamble <= 1'b0; |
StateSFD <= 1'b0; |
StateData0 <= 1'b0; |
StateData1 <= 1'b0; |
end |
else |
begin |
if(StartPreamble | StartSFD | StartDrop) |
StateIdle <= #Tp 1'b0; |
StateIdle <= 1'b0; |
else |
if(StartIdle) |
StateIdle <= #Tp 1'b1; |
StateIdle <= 1'b1; |
|
if(StartIdle) |
StateDrop <= #Tp 1'b0; |
StateDrop <= 1'b0; |
else |
if(StartDrop) |
StateDrop <= #Tp 1'b1; |
StateDrop <= 1'b1; |
|
if(StartSFD | StartIdle | StartDrop) |
StatePreamble <= #Tp 1'b0; |
StatePreamble <= 1'b0; |
else |
if(StartPreamble) |
StatePreamble <= #Tp 1'b1; |
StatePreamble <= 1'b1; |
|
if(StartPreamble | StartIdle | StartData0 | StartDrop) |
StateSFD <= #Tp 1'b0; |
StateSFD <= 1'b0; |
else |
if(StartSFD) |
StateSFD <= #Tp 1'b1; |
StateSFD <= 1'b1; |
|
if(StartIdle | StartData1 | StartDrop) |
StateData0 <= #Tp 1'b0; |
StateData0 <= 1'b0; |
else |
if(StartData0) |
StateData0 <= #Tp 1'b1; |
StateData0 <= 1'b1; |
|
if(StartIdle | StartData0 | StartDrop) |
StateData1 <= #Tp 1'b0; |
StateData1 <= 1'b0; |
else |
if(StartData1) |
StateData1 <= #Tp 1'b1; |
StateData1 <= 1'b1; |
end |
end |
|
/trunk/rtl/verilog/eth_txstatem.v
96,8 → 96,6
StartBackoff, StartDefer, DeferIndication, StartPreamble, StartData, StartIPG |
); |
|
parameter Tp = 1; |
|
input MTxClk; |
input Reset; |
input ExcessiveDefer; |
197,69 → 195,69
begin |
if(Reset) |
begin |
StateIPG <= #Tp 1'b0; |
StateIdle <= #Tp 1'b0; |
StatePreamble <= #Tp 1'b0; |
StateData[1:0] <= #Tp 2'b0; |
StatePAD <= #Tp 1'b0; |
StateFCS <= #Tp 1'b0; |
StateJam <= #Tp 1'b0; |
StateJam_q <= #Tp 1'b0; |
StateBackOff <= #Tp 1'b0; |
StateDefer <= #Tp 1'b1; |
StateIPG <= 1'b0; |
StateIdle <= 1'b0; |
StatePreamble <= 1'b0; |
StateData[1:0] <= 2'b0; |
StatePAD <= 1'b0; |
StateFCS <= 1'b0; |
StateJam <= 1'b0; |
StateJam_q <= 1'b0; |
StateBackOff <= 1'b0; |
StateDefer <= 1'b1; |
end |
else |
begin |
StateData[1:0] <= #Tp StartData[1:0]; |
StateJam_q <= #Tp StateJam; |
StateData[1:0] <= StartData[1:0]; |
StateJam_q <= StateJam; |
|
if(StartDefer | StartIdle) |
StateIPG <= #Tp 1'b0; |
StateIPG <= 1'b0; |
else |
if(StartIPG) |
StateIPG <= #Tp 1'b1; |
StateIPG <= 1'b1; |
|
if(StartDefer | StartPreamble) |
StateIdle <= #Tp 1'b0; |
StateIdle <= 1'b0; |
else |
if(StartIdle) |
StateIdle <= #Tp 1'b1; |
StateIdle <= 1'b1; |
|
if(StartData[0] | StartJam) |
StatePreamble <= #Tp 1'b0; |
StatePreamble <= 1'b0; |
else |
if(StartPreamble) |
StatePreamble <= #Tp 1'b1; |
StatePreamble <= 1'b1; |
|
if(StartFCS | StartJam) |
StatePAD <= #Tp 1'b0; |
StatePAD <= 1'b0; |
else |
if(StartPAD) |
StatePAD <= #Tp 1'b1; |
StatePAD <= 1'b1; |
|
if(StartJam | StartDefer) |
StateFCS <= #Tp 1'b0; |
StateFCS <= 1'b0; |
else |
if(StartFCS) |
StateFCS <= #Tp 1'b1; |
StateFCS <= 1'b1; |
|
if(StartBackoff | StartDefer) |
StateJam <= #Tp 1'b0; |
StateJam <= 1'b0; |
else |
if(StartJam) |
StateJam <= #Tp 1'b1; |
StateJam <= 1'b1; |
|
if(StartDefer) |
StateBackOff <= #Tp 1'b0; |
StateBackOff <= 1'b0; |
else |
if(StartBackoff) |
StateBackOff <= #Tp 1'b1; |
StateBackOff <= 1'b1; |
|
if(StartIPG) |
StateDefer <= #Tp 1'b0; |
StateDefer <= 1'b0; |
else |
if(StartDefer) |
StateDefer <= #Tp 1'b1; |
StateDefer <= 1'b1; |
end |
end |
|
268,14 → 266,14
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
Rule1 <= #Tp 1'b0; |
Rule1 <= 1'b0; |
else |
begin |
if(StateIdle | StateBackOff) |
Rule1 <= #Tp 1'b0; |
Rule1 <= 1'b0; |
else |
if(StatePreamble | FullD) |
Rule1 <= #Tp 1'b1; |
Rule1 <= 1'b1; |
end |
end |
|