URL
https://opencores.org/ocsvn/fifo_srl_uni/fifo_srl_uni/trunk
Subversion Repositories fifo_srl_uni
Compare Revisions
- This comparison shows the changes necessary to convert path
/fifo_srl_uni
- from Rev 3 to Rev 4
- ↔ Reverse comparison
Rev 3 → Rev 4
/work/_info
File deleted
/work/fifo_srl_uni/fifo_srl_uni_rtl.psm
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work/fifo_srl_uni/fifo_srl_uni_rtl.psm
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Index: work/fifo_srl_uni/fifo_srl_uni_rtl.dat
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Index: work/fifo_srl_uni/fifo_srl_uni_rtl.dat
===================================================================
--- work/fifo_srl_uni/fifo_srl_uni_rtl.dat (revision 3)
+++ work/fifo_srl_uni/fifo_srl_uni_rtl.dat (nonexistent)
work/fifo_srl_uni/fifo_srl_uni_rtl.dat
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Index: work/fifo_srl_uni/fifo_srl_uni_rtl.dbs
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Index: work/fifo_srl_uni/fifo_srl_uni_rtl.dbs
===================================================================
--- work/fifo_srl_uni/fifo_srl_uni_rtl.dbs (revision 3)
+++ work/fifo_srl_uni/fifo_srl_uni_rtl.dbs (nonexistent)
work/fifo_srl_uni/fifo_srl_uni_rtl.dbs
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Index: work/fifo_srl_uni/_primary.dat
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Index: work/fifo_srl_uni/_primary.dat
===================================================================
--- work/fifo_srl_uni/_primary.dat (revision 3)
+++ work/fifo_srl_uni/_primary.dat (nonexistent)
work/fifo_srl_uni/_primary.dat
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Index: work/fifo_srl_uni/_primary.dbs
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Index: work/fifo_srl_uni/_primary.dbs
===================================================================
--- work/fifo_srl_uni/_primary.dbs (revision 3)
+++ work/fifo_srl_uni/_primary.dbs (nonexistent)
work/fifo_srl_uni/_primary.dbs
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Index: work/_vmake
===================================================================
--- work/_vmake (revision 3)
+++ work/_vmake (nonexistent)
@@ -1,3 +0,0 @@
-m255
-K3
-cModel Technology
Index: work/tb_fifo_srl_uni_1/testbench.dbs
===================================================================
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Index: work/tb_fifo_srl_uni_1/testbench.dbs
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--- work/tb_fifo_srl_uni_1/testbench.dbs (revision 3)
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work/tb_fifo_srl_uni_1/testbench.dbs
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Index: work/tb_fifo_srl_uni_1/testbench.dat
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Index: work/tb_fifo_srl_uni_1/testbench.dat
===================================================================
--- work/tb_fifo_srl_uni_1/testbench.dat (revision 3)
+++ work/tb_fifo_srl_uni_1/testbench.dat (nonexistent)
work/tb_fifo_srl_uni_1/testbench.dat
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Index: work/tb_fifo_srl_uni_1/_primary.dat
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Index: work/tb_fifo_srl_uni_1/_primary.dat
===================================================================
--- work/tb_fifo_srl_uni_1/_primary.dat (revision 3)
+++ work/tb_fifo_srl_uni_1/_primary.dat (nonexistent)
work/tb_fifo_srl_uni_1/_primary.dat
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Index: work/tb_fifo_srl_uni_1/_primary.dbs
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Index: work/tb_fifo_srl_uni_1/_primary.dbs
===================================================================
--- work/tb_fifo_srl_uni_1/_primary.dbs (revision 3)
+++ work/tb_fifo_srl_uni_1/_primary.dbs (nonexistent)
work/tb_fifo_srl_uni_1/_primary.dbs
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Index: work/tb_fifo_srl_uni_1/testbench.psm
===================================================================
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Index: work/tb_fifo_srl_uni_1/testbench.psm
===================================================================
--- work/tb_fifo_srl_uni_1/testbench.psm (revision 3)
+++ work/tb_fifo_srl_uni_1/testbench.psm (nonexistent)
work/tb_fifo_srl_uni_1/testbench.psm
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Index: transcript
===================================================================
--- transcript (revision 3)
+++ transcript (nonexistent)
@@ -1,425 +0,0 @@
-# Reading C:/Modeltech_xe_starter/tcl/vsim/pref.tcl
-# OpenFile C:/emacs-22.3/projekty/fifo_srl/src/tb_fifo_srl_uni_1.vhd
-vlib work
-vcom -reportprogress 300 -work work C:/emacs-22.3/projekty/fifo_srl/src/fifo_srl_uni.vhd
-# Model Technology ModelSim XE III vcom 6.4b Compiler 2008.11 Nov 15 2008
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package std_logic_arith
-# -- Loading package std_logic_unsigned
-# -- Loading package vcomponents
-# -- Compiling entity fifo_srl_uni
-# -- Compiling architecture fifo_srl_uni_rtl of fifo_srl_uni
-vcom -reportprogress 300 -work work C:/emacs-22.3/projekty/fifo_srl/src/tb_fifo_srl_uni_1.vhd
-# Model Technology ModelSim XE III vcom 6.4b Compiler 2008.11 Nov 15 2008
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package std_logic_arith
-# -- Loading package std_logic_unsigned
-# -- Loading package numeric_std
-# -- Compiling entity tb_fifo_srl_uni_1
-# -- Compiling architecture testbench of tb_fifo_srl_uni_1
-vsim -voptargs=+acc work.tb_fifo_srl_uni_1
-# vsim -voptargs=+acc work.tb_fifo_srl_uni_1
-# Loading std.standard
-# Loading ieee.std_logic_1164(body)
-# Loading ieee.std_logic_arith(body)
-# Loading ieee.std_logic_unsigned(body)
-# Loading ieee.numeric_std(body)
-# Loading work.tb_fifo_srl_uni_1(testbench)
-# Loading unisim.vcomponents
-# Loading work.fifo_srl_uni(fifo_srl_uni_rtl)
-# Loading std.textio(body)
-# Loading ieee.vital_timing(body)
-# Loading ieee.vital_primitives(body)
-# Loading unisim.vpkg(body)
-# Loading unisim.srlc16e(srlc16e_v)
-add wave sim:/tb_fifo_srl_uni_1/uut/*
-run 100 ns
-quit -sim
-vcom -work work -O0 C:/emacs-22.3/projekty/fifo_srl/src/fifo_srl_uni.vhd
-# Model Technology ModelSim XE III vcom 6.4b Compiler 2008.11 Nov 15 2008
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package std_logic_arith
-# -- Loading package std_logic_unsigned
-# -- Loading package vcomponents
-# -- Compiling entity fifo_srl_uni
-# -- Compiling architecture fifo_srl_uni_rtl of fifo_srl_uni
-# ** Error: C:/emacs-22.3/projekty/fifo_srl/src/fifo_srl_uni.vhd(129): Illegal target for signal assignment.
-# ** Error: C:/emacs-22.3/projekty/fifo_srl/src/fifo_srl_uni.vhd(129): (vcom-1136) Unknown identifier "ce_master".
-# ** Error: C:/emacs-22.3/projekty/fifo_srl/src/fifo_srl_uni.vhd(192): VHDL Compiler exiting
-# C:/Modeltech_xe_starter/win32xoem/vcom failed.
-vcom -work work -O0 C:/emacs-22.3/projekty/fifo_srl/src/fifo_srl_uni.vhd
-# Model Technology ModelSim XE III vcom 6.4b Compiler 2008.11 Nov 15 2008
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package std_logic_arith
-# -- Loading package std_logic_unsigned
-# -- Loading package vcomponents
-# -- Compiling entity fifo_srl_uni
-# -- Compiling architecture fifo_srl_uni_rtl of fifo_srl_uni
-vsim -voptargs=+acc work.tb_fifo_srl_uni_1
-# vsim -voptargs=+acc work.tb_fifo_srl_uni_1
-# Loading std.standard
-# Loading ieee.std_logic_1164(body)
-# Loading ieee.std_logic_arith(body)
-# Loading ieee.std_logic_unsigned(body)
-# Loading ieee.numeric_std(body)
-# Loading work.tb_fifo_srl_uni_1(testbench)
-# Loading unisim.vcomponents
-# Loading work.fifo_srl_uni(fifo_srl_uni_rtl)
-# Loading std.textio(body)
-# Loading ieee.vital_timing(body)
-# Loading ieee.vital_primitives(body)
-# Loading unisim.vpkg(body)
-# Loading unisim.srlc16e(srlc16e_v)
-run 100 ns
-quit -sim
-vcom -work work -O0 C:/emacs-22.3/projekty/fifo_srl/src/fifo_srl_uni.vhd
-# Model Technology ModelSim XE III vcom 6.4b Compiler 2008.11 Nov 15 2008
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package std_logic_arith
-# -- Loading package std_logic_unsigned
-# -- Loading package vcomponents
-# -- Compiling entity fifo_srl_uni
-# -- Compiling architecture fifo_srl_uni_rtl of fifo_srl_uni
-vsim -voptargs=+acc work.tb_fifo_srl_uni_1
-# vsim -voptargs=+acc work.tb_fifo_srl_uni_1
-# Loading std.standard
-# Loading ieee.std_logic_1164(body)
-# Loading ieee.std_logic_arith(body)
-# Loading ieee.std_logic_unsigned(body)
-# Loading ieee.numeric_std(body)
-# Loading work.tb_fifo_srl_uni_1(testbench)
-# Loading unisim.vcomponents
-# Loading work.fifo_srl_uni(fifo_srl_uni_rtl)
-# Loading std.textio(body)
-# Loading ieee.vital_timing(body)
-# Loading ieee.vital_primitives(body)
-# Loading unisim.vpkg(body)
-# Loading unisim.srlc16e(srlc16e_v)
-run 100 ns
-quit -sim
-vcom -work work -O0 C:/emacs-22.3/projekty/fifo_srl/src/fifo_srl_uni.vhd
-# Model Technology ModelSim XE III vcom 6.4b Compiler 2008.11 Nov 15 2008
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package std_logic_arith
-# -- Loading package std_logic_unsigned
-# -- Loading package vcomponents
-# -- Compiling entity fifo_srl_uni
-# -- Compiling architecture fifo_srl_uni_rtl of fifo_srl_uni
-vsim -voptargs=+acc work.tb_fifo_srl_uni_1
-# vsim -voptargs=+acc work.tb_fifo_srl_uni_1
-# Loading std.standard
-# Loading ieee.std_logic_1164(body)
-# Loading ieee.std_logic_arith(body)
-# Loading ieee.std_logic_unsigned(body)
-# Loading ieee.numeric_std(body)
-# Loading work.tb_fifo_srl_uni_1(testbench)
-# Loading unisim.vcomponents
-# Loading work.fifo_srl_uni(fifo_srl_uni_rtl)
-# Loading std.textio(body)
-# Loading ieee.vital_timing(body)
-# Loading ieee.vital_primitives(body)
-# Loading unisim.vpkg(body)
-# Loading unisim.srlc16e(srlc16e_v)
-run 100 ns
-quit -sim
-vcom -work work -O0 C:/emacs-22.3/projekty/fifo_srl/src/fifo_srl_uni.vhd
-# Model Technology ModelSim XE III vcom 6.4b Compiler 2008.11 Nov 15 2008
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package std_logic_arith
-# -- Loading package std_logic_unsigned
-# -- Loading package vcomponents
-# -- Compiling entity fifo_srl_uni
-# -- Compiling architecture fifo_srl_uni_rtl of fifo_srl_uni
-# ** Error: C:/emacs-22.3/projekty/fifo_srl/src/fifo_srl_uni.vhd(183): (vcom-1136) Unknown identifier "zeros".
-# ** Error: C:/emacs-22.3/projekty/fifo_srl/src/fifo_srl_uni.vhd(183): Type error resolving infix expression "=" as type std.standard.boolean.
-# ** Error: C:/emacs-22.3/projekty/fifo_srl/src/fifo_srl_uni.vhd(208): VHDL Compiler exiting
-# C:/Modeltech_xe_starter/win32xoem/vcom failed.
-vsim -voptargs=+acc work.fifo_srl_uni
-# vsim -voptargs=+acc work.fifo_srl_uni
-# Loading std.standard
-# Loading ieee.std_logic_1164(body)
-# Loading ieee.std_logic_arith(body)
-# Loading ieee.std_logic_unsigned(body)
-# Loading unisim.vcomponents
-# Loading work.fifo_srl_uni(fifo_srl_uni_rtl)
-# Loading std.textio(body)
-# Loading ieee.vital_timing(body)
-# Loading ieee.vital_primitives(body)
-# Loading unisim.vpkg(body)
-# Loading unisim.srlc16e(srlc16e_v)
-quit -sim
-vcom -work work -O0 C:/emacs-22.3/projekty/fifo_srl/src/fifo_srl_uni.vhd
-# Model Technology ModelSim XE III vcom 6.4b Compiler 2008.11 Nov 15 2008
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package std_logic_arith
-# -- Loading package std_logic_unsigned
-# -- Loading package vcomponents
-# -- Compiling entity fifo_srl_uni
-# -- Compiling architecture fifo_srl_uni_rtl of fifo_srl_uni
-vsim -voptargs=+acc work.tb_fifo_srl_uni_1
-# vsim -voptargs=+acc work.tb_fifo_srl_uni_1
-# Loading std.standard
-# Loading ieee.std_logic_1164(body)
-# Loading ieee.std_logic_arith(body)
-# Loading ieee.std_logic_unsigned(body)
-# Loading ieee.numeric_std(body)
-# Loading work.tb_fifo_srl_uni_1(testbench)
-# Loading unisim.vcomponents
-# Loading work.fifo_srl_uni(fifo_srl_uni_rtl)
-# Loading std.textio(body)
-# Loading ieee.vital_timing(body)
-# Loading ieee.vital_primitives(body)
-# Loading unisim.vpkg(body)
-# Loading unisim.srlc16e(srlc16e_v)
-run 100 ns
-restart
-run 100 ns
-quit -sim
-vcom -work work -O0 C:/emacs-22.3/projekty/fifo_srl/src/fifo_srl_uni.vhd
-# Model Technology ModelSim XE III vcom 6.4b Compiler 2008.11 Nov 15 2008
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package std_logic_arith
-# -- Loading package std_logic_unsigned
-# -- Loading package vcomponents
-# -- Compiling entity fifo_srl_uni
-# -- Compiling architecture fifo_srl_uni_rtl of fifo_srl_uni
-vsim -voptargs=+acc work.tb_fifo_srl_uni_1
-# vsim -voptargs=+acc work.tb_fifo_srl_uni_1
-# Loading std.standard
-# Loading ieee.std_logic_1164(body)
-# Loading ieee.std_logic_arith(body)
-# Loading ieee.std_logic_unsigned(body)
-# Loading ieee.numeric_std(body)
-# Loading work.tb_fifo_srl_uni_1(testbench)
-# Loading unisim.vcomponents
-# Loading work.fifo_srl_uni(fifo_srl_uni_rtl)
-# Loading std.textio(body)
-# Loading ieee.vital_timing(body)
-# Loading ieee.vital_primitives(body)
-# Loading unisim.vpkg(body)
-# Loading unisim.srlc16e(srlc16e_v)
-run 100 ns
-# Can't move the Now cursor.
-# Can't move the Now cursor.
-# Can't move the Now cursor.
-# Can't move the Now cursor.
-# Can't move the Now cursor.
-# Can't move the Now cursor.
-# Can't move the Now cursor.
-# Can't move the Now cursor.
-# Can't move the Now cursor.
-# Can't move the Now cursor.
-# WARNING: No extended dataflow License exists
-quit -sim
-vcom -work work -O0 C:/emacs-22.3/projekty/fifo_srl/src/tb_fifo_srl_uni_1.vhd
-# Model Technology ModelSim XE III vcom 6.4b Compiler 2008.11 Nov 15 2008
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package std_logic_arith
-# -- Loading package std_logic_unsigned
-# -- Loading package numeric_std
-# -- Compiling entity tb_fifo_srl_uni_1
-# -- Compiling architecture testbench of tb_fifo_srl_uni_1
-vsim -voptargs=+acc work.tb_fifo_srl_uni_1
-# vsim -voptargs=+acc work.tb_fifo_srl_uni_1
-# Loading std.standard
-# Loading ieee.std_logic_1164(body)
-# Loading ieee.std_logic_arith(body)
-# Loading ieee.std_logic_unsigned(body)
-# Loading ieee.numeric_std(body)
-# Loading work.tb_fifo_srl_uni_1(testbench)
-# Loading unisim.vcomponents
-# Loading work.fifo_srl_uni(fifo_srl_uni_rtl)
-# Loading std.textio(body)
-# Loading ieee.vital_timing(body)
-# Loading ieee.vital_primitives(body)
-# Loading unisim.vpkg(body)
-# Loading unisim.srlc16e(srlc16e_v)
-run 100 ns
-vcom -work work -O0 C:/emacs-22.3/projekty/fifo_srl/src/fifo_srl_uni.vhd
-# Model Technology ModelSim XE III vcom 6.4b Compiler 2008.11 Nov 15 2008
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package std_logic_arith
-# -- Loading package std_logic_unsigned
-# -- Loading package vcomponents
-# -- Compiling entity fifo_srl_uni
-# -- Compiling architecture fifo_srl_uni_rtl of fifo_srl_uni
-vsim -voptargs=+acc work.tb_fifo_srl_uni_1
-# vsim -voptargs=+acc work.tb_fifo_srl_uni_1
-# Loading std.standard
-# Loading ieee.std_logic_1164(body)
-# Loading ieee.std_logic_arith(body)
-# Loading ieee.std_logic_unsigned(body)
-# Loading ieee.numeric_std(body)
-# Loading work.tb_fifo_srl_uni_1(testbench)
-# Loading unisim.vcomponents
-# Loading work.fifo_srl_uni(fifo_srl_uni_rtl)
-# Loading std.textio(body)
-# Loading ieee.vital_timing(body)
-# Loading ieee.vital_primitives(body)
-# Loading unisim.vpkg(body)
-# Loading unisim.srlc16e(srlc16e_v)
-run 100 ns
-# ** Fatal: (vsim-3734) Index value -1 is out of range 0 to 2.
-# Time: 0 ps Iteration: 0 Process: /tb_fifo_srl_uni_1/uut/line__156 File: C:/emacs-22.3/projekty/fifo_srl/src/fifo_srl_uni.vhd
-# Fatal error in Architecture fifo_srl_uni_rtl at C:/emacs-22.3/projekty/fifo_srl/src/fifo_srl_uni.vhd line 156
-#
-# HDL call sequence:
-# Stopped at C:/emacs-22.3/projekty/fifo_srl/src/fifo_srl_uni.vhd 156 Architecture fifo_srl_uni_rtl
-#
-quit -sim
-vcom -work work -O0 C:/emacs-22.3/projekty/fifo_srl/src/fifo_srl_uni.vhd
-# Model Technology ModelSim XE III vcom 6.4b Compiler 2008.11 Nov 15 2008
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package std_logic_arith
-# -- Loading package std_logic_unsigned
-# -- Loading package vcomponents
-# -- Compiling entity fifo_srl_uni
-# -- Compiling architecture fifo_srl_uni_rtl of fifo_srl_uni
-vcom -work work -O0 C:/emacs-22.3/projekty/fifo_srl/src/tb_fifo_srl_uni_1.vhd
-# Model Technology ModelSim XE III vcom 6.4b Compiler 2008.11 Nov 15 2008
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package std_logic_arith
-# -- Loading package std_logic_unsigned
-# -- Loading package numeric_std
-# -- Compiling entity tb_fifo_srl_uni_1
-# -- Compiling architecture testbench of tb_fifo_srl_uni_1
-vsim -voptargs=+acc work.tb_fifo_srl_uni_1
-# vsim -voptargs=+acc work.tb_fifo_srl_uni_1
-# Loading std.standard
-# Loading ieee.std_logic_1164(body)
-# Loading ieee.std_logic_arith(body)
-# Loading ieee.std_logic_unsigned(body)
-# Loading ieee.numeric_std(body)
-# Loading work.tb_fifo_srl_uni_1(testbench)
-# Loading unisim.vcomponents
-# Loading work.fifo_srl_uni(fifo_srl_uni_rtl)
-# Loading std.textio(body)
-# Loading ieee.vital_timing(body)
-# Loading ieee.vital_primitives(body)
-# Loading unisim.vpkg(body)
-# Loading unisim.srlc16e(srlc16e_v)
-add wave sim:/tb_fifo_srl_uni_1/*
-run 100 ns
-# ** Fatal: (vsim-3734) Index value -1 is out of range 0 to 2.
-# Time: 0 ps Iteration: 0 Process: /tb_fifo_srl_uni_1/uut/line__156 File: C:/emacs-22.3/projekty/fifo_srl/src/fifo_srl_uni.vhd
-# Fatal error in Architecture fifo_srl_uni_rtl at C:/emacs-22.3/projekty/fifo_srl/src/fifo_srl_uni.vhd line 156
-#
-# HDL call sequence:
-# Stopped at C:/emacs-22.3/projekty/fifo_srl/src/fifo_srl_uni.vhd 156 Architecture fifo_srl_uni_rtl
-#
-quit -sim
-vcom -work work -O0 C:/emacs-22.3/projekty/fifo_srl/src/fifo_srl_uni.vhd
-# Model Technology ModelSim XE III vcom 6.4b Compiler 2008.11 Nov 15 2008
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package std_logic_arith
-# -- Loading package std_logic_unsigned
-# -- Loading package vcomponents
-# -- Compiling entity fifo_srl_uni
-# -- Compiling architecture fifo_srl_uni_rtl of fifo_srl_uni
-vsim -voptargs=+acc work.tb_fifo_srl_uni_1
-# vsim -voptargs=+acc work.tb_fifo_srl_uni_1
-# Loading std.standard
-# Loading ieee.std_logic_1164(body)
-# Loading ieee.std_logic_arith(body)
-# Loading ieee.std_logic_unsigned(body)
-# Loading ieee.numeric_std(body)
-# Loading work.tb_fifo_srl_uni_1(testbench)
-# Loading unisim.vcomponents
-# Loading work.fifo_srl_uni(fifo_srl_uni_rtl)
-# Loading std.textio(body)
-# Loading ieee.vital_timing(body)
-# Loading ieee.vital_primitives(body)
-# Loading unisim.vpkg(body)
-# Loading unisim.srlc16e(srlc16e_v)
-run 100 ns
-# ** Fatal: (vsim-3734) Index value -1 is out of range 0 to 2.
-# Time: 0 ps Iteration: 0 Process: /tb_fifo_srl_uni_1/uut/line__156 File: C:/emacs-22.3/projekty/fifo_srl/src/fifo_srl_uni.vhd
-# Fatal error in Architecture fifo_srl_uni_rtl at C:/emacs-22.3/projekty/fifo_srl/src/fifo_srl_uni.vhd line 156
-#
-# HDL call sequence:
-# Stopped at C:/emacs-22.3/projekty/fifo_srl/src/fifo_srl_uni.vhd 156 Architecture fifo_srl_uni_rtl
-#
-quit -sim
-vcom -work work -O0 C:/emacs-22.3/projekty/fifo_srl/src/fifo_srl_uni.vhd
-# Model Technology ModelSim XE III vcom 6.4b Compiler 2008.11 Nov 15 2008
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package std_logic_arith
-# -- Loading package std_logic_unsigned
-# -- Loading package vcomponents
-# -- Compiling entity fifo_srl_uni
-# -- Compiling architecture fifo_srl_uni_rtl of fifo_srl_uni
-vcom -work work -O0 C:/emacs-22.3/projekty/fifo_srl/src/tb_fifo_srl_uni_1.vhd
-# Model Technology ModelSim XE III vcom 6.4b Compiler 2008.11 Nov 15 2008
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package std_logic_arith
-# -- Loading package std_logic_unsigned
-# -- Loading package numeric_std
-# -- Compiling entity tb_fifo_srl_uni_1
-# -- Compiling architecture testbench of tb_fifo_srl_uni_1
-vsim -voptargs=+acc work.tb_fifo_srl_uni_1
-# vsim -voptargs=+acc work.tb_fifo_srl_uni_1
-# Loading std.standard
-# Loading ieee.std_logic_1164(body)
-# Loading ieee.std_logic_arith(body)
-# Loading ieee.std_logic_unsigned(body)
-# Loading ieee.numeric_std(body)
-# Loading work.tb_fifo_srl_uni_1(testbench)
-# Loading unisim.vcomponents
-# Loading work.fifo_srl_uni(fifo_srl_uni_rtl)
-# Loading std.textio(body)
-# Loading ieee.vital_timing(body)
-# Loading ieee.vital_primitives(body)
-# Loading unisim.vpkg(body)
-# Loading unisim.srlc16e(srlc16e_v)
-run 100 ns
-quit -sim
-vcom -work work -O0 C:/emacs-22.3/projekty/fifo_srl/src/fifo_srl_uni.vhd
-# Model Technology ModelSim XE III vcom 6.4b Compiler 2008.11 Nov 15 2008
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package std_logic_arith
-# -- Loading package std_logic_unsigned
-# -- Loading package vcomponents
-# -- Compiling entity fifo_srl_uni
-# -- Compiling architecture fifo_srl_uni_rtl of fifo_srl_uni
-vcom -work work -O0 C:/emacs-22.3/projekty/fifo_srl/src/tb_fifo_srl_uni_1.vhd
-# Model Technology ModelSim XE III vcom 6.4b Compiler 2008.11 Nov 15 2008
-# -- Loading package standard
-# -- Loading package std_logic_1164
-# -- Loading package std_logic_arith
-# -- Loading package std_logic_unsigned
-# -- Loading package numeric_std
-# -- Compiling entity tb_fifo_srl_uni_1
-# -- Compiling architecture testbench of tb_fifo_srl_uni_1
-vsim -voptargs=+acc work.tb_fifo_srl_uni_1
-# vsim -voptargs=+acc work.tb_fifo_srl_uni_1
-# Loading std.standard
-# Loading ieee.std_logic_1164(body)
-# Loading ieee.std_logic_arith(body)
-# Loading ieee.std_logic_unsigned(body)
-# Loading ieee.numeric_std(body)
-# Loading work.tb_fifo_srl_uni_1(testbench)
-# Loading unisim.vcomponents
-# Loading work.fifo_srl_uni(fifo_srl_uni_rtl)
-# Loading std.textio(body)
-# Loading ieee.vital_timing(body)
-# Loading ieee.vital_primitives(body)
-# Loading unisim.vpkg(body)
-# Loading unisim.srlc16e(srlc16e_v)
-run 100 ns
Index: tb_fifo_srl_uni_1.vhd
===================================================================
--- tb_fifo_srl_uni_1.vhd (revision 3)
+++ tb_fifo_srl_uni_1.vhd (nonexistent)
@@ -1,201 +0,0 @@
--------------------------------------------------------------------------------
--- Title : Testbench for fifo_srl_uni.vhd
--- Project :
--------------------------------------------------------------------------------
--- File : tb_fifo_srl_uni_1.vhd
--- Author : Tomasz Turek
--- Company : SzuWar INC
--- Created : 09:45:13 16-03-2010
--- Last update: 11:28:50 18-03-2010
--- Platform : Xilinx ISE 10.1.03
--- Standard : VHDL'93
--------------------------------------------------------------------------------
--- Description:
--------------------------------------------------------------------------------
--- Copyright (c) 2010 SzuWar INC
--------------------------------------------------------------------------------
--- Revisions :
--- Date Version Author Description
--- 09:45:13 16-03-2010 1.0 szuwarek Created
--------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use ieee.numeric_std.all;
-
-
-entity tb_fifo_srl_uni_1 is
-
-end entity tb_fifo_srl_uni_1;
-
-architecture testbench of tb_fifo_srl_uni_1 is
-
--------------------------------------------------------------------------------
--- Unit Under Test --
--------------------------------------------------------------------------------
- component fifo_srl_uni is
-
- generic (
- iDataWidth : integer range 1 to 32 := 17;
- ififoWidth : integer range 1 to 1023 := 33;
- iInputReg : integer range 0 to 2 := 0;
- iOutputReg : integer range 0 to 3 := 2;
- iFullFlagOfSet : integer range 0 to 1021 := 2;
- iEmptyFlagOfSet : integer range 0 to 1021 := 5;
- iSizeDelayCounter : integer range 5 to 11 := 6
- );
-
- port (
- CLK_I : in std_logic;
- DATA_I : in std_logic_vector(iDataWidth - 1 downto 0);
- DATA_O : out std_logic_vector(iDataWidth - 1 downto 0);
- WRITE_ENABLE_I : in std_logic;
- READ_ENABLE_I : in std_logic;
- READ_VALID_O : out std_logic;
- FIFO_COUNT_O : out std_logic_vector(iSizeDelayCounter - 1 downto 0);
- FULL_FLAG_O : out std_logic;
- EMPTY_FLAG_O : out std_logic
- );
-
- end component fifo_srl_uni;
-
--------------------------------------------------------------------------------
--- constants --
--------------------------------------------------------------------------------
- constant iDataWidth : integer := 16;
- constant ififoWidth : integer := 4;
- constant iInputReg : integer := 0;
- constant iOutputReg : integer := 1;
- constant iFullFlagOfSet : integer := 1;
- constant iEmptyFlagOfSet : integer := 1;
- constant iSizeDelayCounter : integer := 6;
-
- constant iWriteDataCounter : integer := 12;
- constant iReadDataCounter : integer := 6;
-
--------------------------------------------------------------------------------
--- signals --
--------------------------------------------------------------------------------
- -- IN --
- signal CLK_I : std_logic := '0';
- signal WRITE_ENABLE_I : std_logic := '0';
- signal READ_ENABLE_I : std_logic := '0';
- signal DATA_I : std_logic_vector(iDataWidth - 1 downto 0) := (others => '0');
-
- -- OUT --
- signal DATA_O : std_logic_vector(iDataWidth - 1 downto 0);
- signal READ_VALID_O : std_logic;
- signal FULL_FLAG_O : std_logic;
- signal EMPTY_FLAG_O : std_logic;
- signal FIFO_COUNT_O : std_logic_vector(iSizeDelayCounter - 1 downto 0);
-
- -- others --
- signal v_count : std_logic_vector(15 downto 0) := x"0000";
- signal i_count_write : integer range 0 to ififoWidth := 0;
-
-begin -- architecture testbench
-
-
- UUT: fifo_srl_uni
-
- generic map (
- iDataWidth => iDataWidth,
- ififoWidth => ififoWidth,
- iInputReg => iInputReg,
- iOutputReg => iOutputReg,
- iFullFlagOfSet => iFullFlagOfSet,
- iEmptyFlagOfSet => iEmptyFlagOfSet,
- iSizeDelayCounter => iSizeDelayCounter
- )
-
- port map(
- CLK_I => CLK_I,
- DATA_I => DATA_I,
- DATA_O => DATA_O,
- WRITE_ENABLE_I => WRITE_ENABLE_I,
- READ_ENABLE_I => READ_ENABLE_I,
- READ_VALID_O => READ_VALID_O,
- FIFO_COUNT_O => FIFO_COUNT_O,
- FULL_FLAG_O => FULL_FLAG_O,
- EMPTY_FLAG_O => EMPTY_FLAG_O
- );
-
- StimulationProcess : process
-
- begin
-
- for i in 0 to 1000000 loop
-
- CLK_I <= not CLK_I;
-
- wait for 5 ns;
-
- end loop;
-
- wait;
-
- end process StimulationProcess;
-
- T0: process (CLK_I) is
- begin -- process T0
-
- if rising_edge(CLK_I) then
-
- case v_count is
-
- when x"0003" =>
-
- DATA_I <= x"0010";
- WRITE_ENABLE_I <= '1';
- READ_ENABLE_I <= '0';
- v_count <= v_count + 1;
-
- when x"0004" =>
-
- DATA_I <= x"0200";
- WRITE_ENABLE_I <= '1';
- READ_ENABLE_I <= '0';
- v_count <= v_count + 1;
-
- when x"0005" =>
-
- DATA_I <= x"0100";
- WRITE_ENABLE_I <= '1';
- READ_ENABLE_I <= '0';
- v_count <= v_count + 1;
-
- when x"0006" =>
-
- DATA_I <= x"0000";
- WRITE_ENABLE_I <= '0';
- READ_ENABLE_I <= '0';
- v_count <= v_count + 1;
-
- when x"0007" =>
-
- DATA_I <= x"0000";
- WRITE_ENABLE_I <= '0';
- READ_ENABLE_I <= '1';
- v_count <= v_count + 1;
-
- when x"0008" =>
-
- DATA_I <= x"0000";
- WRITE_ENABLE_I <= '0';
- READ_ENABLE_I <= '0';
- v_count <= v_count + 1;
-
- when others =>
-
- WRITE_ENABLE_I <= WRITE_ENABLE_I;
- READ_ENABLE_I <= READ_ENABLE_I;
- v_count <= v_count + 1;
-
- end case;
-
- end if;
-
- end process T0;
-
-end architecture testbench;
Index: fifo_srl_uni.vhd
===================================================================
--- fifo_srl_uni.vhd (revision 3)
+++ fifo_srl_uni.vhd (nonexistent)
@@ -1,339 +0,0 @@
--------------------------------------------------------------------------------
--- Title : Parametrilayze based on SRL16 shift register FIFO
--- Project :
--------------------------------------------------------------------------------
--- File : fifo_srl_uni.vhd
--- Author : Tomasz Turek
--- Company : SzuWar INC
--- Created : 13:27:31 14-03-2010
--- Last update: 12:03:49 18-03-2010
--- Platform : Xilinx ISE 10.1.03
--- Standard : VHDL'93
--------------------------------------------------------------------------------
--- Description:
--------------------------------------------------------------------------------
--- Copyright (c) 2010 SzuWar INC
--------------------------------------------------------------------------------
--- Revisions :
--- Date Version Author Description
--- 13:27:31 14-03-2010 1.0 szuwarek Created
--------------------------------------------------------------------------------
-
-
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-use ieee.std_logic_arith.all;
-use IEEE.STD_LOGIC_UNSIGNED.all;
---use ieee.numeric_std.all;
-
-Library UNISIM;
-use UNISIM.vcomponents.all;
-
-entity fifo_srl_uni is
-
- generic (
- iDataWidth : integer range 1 to 32 := 17;
- ififoWidth : integer range 1 to 1023 := 32;
- iInputReg : integer range 0 to 2 := 0;
- iOutputReg : integer range 0 to 3 := 2;
- iFullFlagOfSet : integer range 0 to 1021 := 2;
- iEmptyFlagOfSet : integer range 0 to 1021 := 5;
- iSizeDelayCounter : integer range 5 to 11 := 6
- );
-
- port (
- CLK_I : in std_logic;
- DATA_I : in std_logic_vector(iDataWidth - 1 downto 0);
- DATA_O : out std_logic_vector(iDataWidth - 1 downto 0);
- WRITE_ENABLE_I : in std_logic;
- READ_ENABLE_I : in std_logic;
- READ_VALID_O : out std_logic;
- FIFO_COUNT_O : out std_logic_vector(iSizeDelayCounter - 1 downto 0);
- FULL_FLAG_O : out std_logic;
- EMPTY_FLAG_O : out std_logic
- );
-
-end entity fifo_srl_uni;
-
-architecture fifo_srl_uni_rtl of fifo_srl_uni is
-
-
--------------------------------------------------------------------------------
--- functions --
--------------------------------------------------------------------------------
- function f_srl_count (constant c_fifo_size : integer) return integer is
-
- variable i_temp : integer;
- variable i_count : integer;
-
- begin -- function f_srl_count
-
- i_temp := c_fifo_size;
- i_count := 0;
-
- for i in 0 to 64 loop
-
- if i_temp < 1 then
-
- if i_count = 0 then
-
- i_count := i;
-
- else
-
- i_count := i_count;
-
- end if;
-
- else
-
- i_temp := i_temp - 16;
-
- end if;
-
- end loop; -- i
-
- return i_count;
-
- end function f_srl_count;
-
--------------------------------------------------------------------------------
--- constants --
--------------------------------------------------------------------------------
- constant c_srl_count : integer range 0 to 64 := f_srl_count(ififoWidth);
-
--------------------------------------------------------------------------------
--- types --
--------------------------------------------------------------------------------
- type type_in_reg is array (0 to iInputReg - 1) of std_logic_vector(iDataWidth - 1 downto 0);
- type type_out_reg is array (0 to iOutputReg) of std_logic_vector(iDataWidth - 1 downto 0);
- type type_data_path is array (0 to c_srl_count - 1) of std_logic_vector(iDataWidth - 1 downto 0);
- type type_srl_path is array (0 to c_srl_count) of std_logic_vector(iDataWidth - 1 downto 0);
-
--------------------------------------------------------------------------------
--- signals --
--------------------------------------------------------------------------------
- signal v_delay_counter : std_logic_vector(iSizeDelayCounter - 1 downto 0) := (others => '0');
- signal v_size_counter : std_logic_vector(iSizeDelayCounter - 1 downto 0) := (others => '0');
- signal v_zeros : std_logic_vector(iSizeDelayCounter - 1 downto 0) := (others => '0');
- signal v_ones : std_logic_vector(iSizeDelayCounter - 1 downto 0) := (others => '0');
- signal v_WRITE_ENABLE : std_logic_vector(iInputReg downto 0);
- signal v_READ_ENABLE : std_logic_vector(iOutputReg downto 0);
- signal i_size_counter : integer range 0 to 1023 := 0;
- signal i_srl_select : integer range 0 to 64 := 0;
- signal i_temp : integer range 0 to 64;
- signal t_mux_in : type_data_path;
- signal t_srl_in : type_srl_path;
- signal t_mux_out : type_out_reg;
- signal t_reg_in : type_in_reg;
- signal one_delay : std_logic := '0';
- signal dupa : std_logic := '0';
-
-begin -- architecture fifo_srl_uni_r
-
-
- v_zeros <= (others => '0');
- v_ones <= (others => '1');
-
- GR0: if iInputReg = 0 generate
-
- t_srl_in(0) <= DATA_I;
- v_WRITE_ENABLE(0) <= WRITE_ENABLE_I;
-
- end generate GR0;
-
- GR1: if iInputReg = 1 generate
-
- t_srl_in(0) <= t_reg_in(0);
- v_WRITE_ENABLE(1) <= WRITE_ENABLE_I;
-
- P1: process (CLK_I) is
- begin -- process P1
-
- if rising_edge(CLK_I) then
-
- t_reg_in(0) <= DATA_I;
- v_WRITE_ENABLE(0) <= v_WRITE_ENABLE(1);
-
- end if;
-
- end process P1;
-
- end generate GR1;
-
- GR2: if iInputReg = 2 generate
-
- t_srl_in(0) <= t_reg_in(0);
- v_WRITE_ENABLE(2) <= WRITE_ENABLE_I;
-
- P1: process (CLK_I) is
- begin -- process P1
-
- if rising_edge(CLK_I) then
-
- t_reg_in(1) <= DATA_I;
- t_reg_in(0) <= t_reg_in(1);
- v_WRITE_ENABLE(1 downto 0) <= v_WRITE_ENABLE(2 downto 1);
-
- end if;
-
- end process P1;
-
- end generate GR2;
-
- G1: for i in 0 to c_srl_count - 1 generate
-
- G0: for j in 0 to iDataWidth - 1 generate
-
- SRLC16_inst : SRLC16E
- port map
- (
- Q => t_mux_in(i)(j), -- SRL data output
- Q15 => t_srl_in(i+1)(j), -- Carry output (connect to next SRL)
- A0 => v_delay_counter(0), -- Select[0] input
- A1 => v_delay_counter(1), -- Select[1] input
- A2 => v_delay_counter(2), -- Select[2] input
- A3 => v_delay_counter(3), -- Select[3] input
- CE => v_WRITE_ENABLE(0), -- Clock enable input
- CLK => CLK_I, -- Clock input
- D => t_srl_in(i)(j) -- SRL data input
- );
-
- end generate G0;
-
- end generate G1;
-
- i_srl_select <= conv_integer((v_delay_counter(iSizeDelayCounter - 1 downto 4)));
- i_size_counter <= conv_integer(v_size_counter);
-
- P0: process (CLK_I) is
- begin -- process P0
-
- if rising_edge(CLK_I) then
-
- if (v_WRITE_ENABLE(0) = '1') and (READ_ENABLE_I = '0') and (v_size_counter /= v_ones) then
-
- if one_delay = '1' then
-
- v_delay_counter <= v_delay_counter + 1;
- one_delay <= '1';
-
- else
-
- one_delay <= '1';
- v_delay_counter <= v_delay_counter;
-
- end if;
-
- v_size_counter <= v_size_counter + 1;
-
- elsif (v_WRITE_ENABLE(0) = '0') and (READ_ENABLE_I = '1') and (v_size_counter /= v_zeros) then
-
- if v_delay_counter = v_zeros then
-
- one_delay <= '0';
-
- else
-
- one_delay <= '1';
- v_delay_counter <= v_delay_counter - 1;
-
- end if;
-
- v_size_counter <= v_size_counter - 1;
-
- else
-
- v_delay_counter <= v_delay_counter;
- v_size_counter <= v_size_counter;
- one_delay <= one_delay;
-
- end if;
-
- end if;
-
- end process P0;
-
- t_mux_out(0) <= t_mux_in(i_srl_select);
- READ_VALID_O <= v_READ_ENABLE(0);
- FIFO_COUNT_O <= v_size_counter;
-
- GM0: if iOutputReg = 0 generate
-
- DATA_O <= t_mux_out(0);
- v_READ_ENABLE(0) <= READ_ENABLE_I;
-
- end generate GM0;
-
-
- GM1: if iOutputReg = 1 generate
-
- DATA_O <= t_mux_out(1);
- v_READ_ENABLE(1) <= READ_ENABLE_I;
-
- P2: process (CLK_I) is
- begin -- process P2
-
- if rising_edge(CLK_I) then
-
- v_READ_ENABLE(0) <= v_READ_ENABLE(1);
- t_mux_out(1) <= t_mux_out(0);
-
- end if;
-
- end process P2;
-
- end generate GM1;
-
- GM2: if iOutputReg > 1 generate
-
- DATA_O <= t_mux_out(iOutputReg);
- v_READ_ENABLE(iOutputReg) <= READ_ENABLE_I;
-
- P2: process (CLK_I) is
- begin -- process P2
-
- if rising_edge(CLK_I) then
-
- v_READ_ENABLE(iOutputReg - 1 downto 0) <= v_READ_ENABLE(iOutputReg downto 1);
- t_mux_out(1 to iOutputReg) <= t_mux_out(0 to iOutputReg - 1);
-
- end if;
-
- end process P2;
-
- end generate GM2;
-
- PF: process (CLK_I) is
- begin -- process PF
-
- if rising_edge(CLK_I) then
-
- if i_size_counter >= ififoWidth - iFullFlagOfSet then
-
- FULL_FLAG_O <= '1';
-
- else
-
- FULL_FLAG_O <= '0';
-
- end if;
-
- if i_size_counter < iEmptyFlagOfSet then
-
- EMPTY_FLAG_O <= '1';
-
- else
-
- EMPTY_FLAG_O <= '0';
-
- end if;
-
- end if;
-
- end process PF;
-
-
-
-end architecture fifo_srl_uni_rtl;
-
Index: vsim.wlf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: vsim.wlf
===================================================================
--- vsim.wlf (revision 3)
+++ vsim.wlf (nonexistent)
vsim.wlf
Property changes :
Deleted: svn:mime-type
## -1 +0,0 ##
-application/octet-stream
\ No newline at end of property