URL
https://opencores.org/ocsvn/fir_wishbone/fir_wishbone/trunk
Subversion Repositories fir_wishbone
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/fir_wishbone
- from Rev 7 to Rev 8
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Rev 7 → Rev 8
/trunk/workspaces/synthesis/quartus/fir.qsf
45,11 → 45,12
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files |
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)" |
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation |
set_global_assignment -name VHDL_FILE "../../../design/quartus-synthesis/fir.vhdl" |
set_global_assignment -name VHDL_FILE "../../../design/quartus-synthesis/tb_fir.vhdl" |
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top |
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top |
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top |
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008 |
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF |
set_global_assignment -name VHDL_FILE "../../../design/quartus-synthesis/fir.vhdl" |
set_global_assignment -name VHDL_FILE "../../../design/quartus-synthesis/tb_fir.vhdl" |
set_global_assignment -name VHDL_FILE ../../../tester/stp.vhd |
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |