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    from Rev 77 to Rev 78
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Rev 77 → Rev 78

/trunk/rtl/verilog2/BCDAdd8NClk.sv
73,7 → 73,7
reg [N-1:0] c [0:2];
wire [N*8-1:0] o1 [0:2];
reg [N*8-1:0] o2 [0:2];
wire [N:0] d [0:2];
wire [N-1:0] d [0:2];
 
genvar g,k;
generate begin : gBCDadd
/trunk/rtl/verilog2/BCDSubtract.sv
0,0 → 1,106
module BCDSubtract(clk, a, b, o, co);
parameter N=25;
input clk;
input [N*4-1:0] a;
input [N*4-1:0] b;
output reg [N*4-1:0] o;
output reg co;
 
wire [(N+1)*4-1:0] bc;
wire [(N+1)*4-1:0] o1, o2, o3;
wire c;
 
BCDNinesComplementN #(N+1) u1 (.i({4'h0,b}), .o(bc));
BCDAdd8NClk #(.N(N/2+1)) u2 (.clk(clk), .a({8'h00,a}), .b(bc), .o(o1), .ci(1'b0), .co(c));
BCDNinesComplementN #(N) u3 (.i(o1), .o(o2));
BCDAdd8NClk #(.N(N/2+1)) u4 (.clk(clk), .a(o1), .b({{N*8{1'b0}},1'b1}), .o(o3), .ci(1'b0), .co());
 
always_ff @(posedge clk)
if (c)
o <= o3;
else
o <= o2;
always_ff @(posedge clk)
co <= c;
 
endmodule
 
module BCDNinesComplement(i, o);
input [3:0] i;
output reg [3:0] o;
 
always_comb
case(i)
4'd0: o = 4'd9;
4'd1: o = 4'd8;
4'd2: o = 4'd7;
4'd3: o = 4'd6;
4'd4: o = 4'd5;
4'd5: o = 4'd4;
4'd6: o = 4'd3;
4'd7: o = 4'd2;
4'd8: o = 4'd1;
4'd9: o = 4'd0;
4'd10: o = 4'd9;
4'd11: o = 4'd8;
4'd12: o = 4'd7;
4'd13: o = 4'd6;
4'd14: o = 4'd5;
4'd15: o = 4'd4;
endcase
 
endmodule
 
module BCDNinesComplementN(i, o);
parameter N=25;
input [N*4-1:0] i;
output [N*4-1:0] o;
 
genvar g;
generate begin : gNC
for (g = 0; g < N; g = g + 1)
BCDNinesComplement utc1 (i[g*4+3:g*4],o[g*4+3:g*4]);
end
endgenerate
 
endmodule
 
module BCDTensComplement(i, o);
input [3:0] i;
output reg [3:0] o;
 
always_comb
case(i)
4'd0: o = 4'd0;
4'd1: o = 4'd9;
4'd2: o = 4'd8;
4'd3: o = 4'd7;
4'd4: o = 4'd6;
4'd5: o = 4'd5;
4'd6: o = 4'd4;
4'd7: o = 4'd3;
4'd8: o = 4'd2;
4'd9: o = 4'd1;
4'd10: o = 4'd0;
4'd11: o = 4'd9;
4'd12: o = 4'd8;
4'd13: o = 4'd7;
4'd14: o = 4'd6;
4'd15: o = 4'd5;
endcase
 
endmodule
 
module BCDTensComplementN(i, o);
parameter N=25;
input [N*4-1:0] i;
output [N*4-1:0] o;
 
genvar g;
generate begin : gTC
for (g = 0; g < N; g = g + 1)
BCDTensComplement utc1 (i[g*4+3:g*4],o[g*4+3:g*4]);
end
endgenerate
 
endmodule
/trunk/rtl/verilog2/DFPAddsub96.sv
76,6 → 76,15
wire [(N+1)*4-1:0] odd10;
wire odd10c;
 
BCDSubtract #(N+2) ubcdsubn1
(
.clk(clk),
.a({8'h00,oaa10}),
.b({8'h00,obb10}),
.o(odd10),
.co(odd10c)
);
/*
BCDSub8NClk #(.N((N+2)/2)) ubcdsdn1
(
.clk(clk),
85,7 → 94,7
.ci(1'b0),
.co(odd10c)
);
 
*/
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Clock #1
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
121,7 → 130,6
reg [N*4-1:0] siga2, sigb2;
reg sigeq, siga_gt_sigb;
reg expeq;
reg sxo2;
 
always_ff @(posedge clk)
if (ce) realOp2 = op1 ^ au.sign ^ bu.sign;
159,7 → 167,6
//
reg [11:0] xa3, xb3;
reg resZero3;
wire xaInf3, xbInf3;
reg xa_gt_xb3;
reg a_gt_b3;
reg op3;
186,8 → 193,8
ft_delay #(.WID(1), .DEP(2)) udly3c (.clk(clk), .ce(ce), .i(au.sign), .o(sa3));
ft_delay #(.WID(1), .DEP(2)) udly3d (.clk(clk), .ce(ce), .i(bu.sign), .o(sb3));
ft_delay #(.WID(3), .DEP(3)) udly3e (.clk(clk), .ce(ce), .i(rm), .o(rm3));
ft_delay #(.WID(1), .DEP(2)) udly3f (.clk(clk), .ce(ce), .i(aInf), .o(aInf3));
ft_delay #(.WID(1), .DEP(2)) udly3g (.clk(clk), .ce(ce), .i(bInf), .o(bInf3));
ft_delay #(.WID(1), .DEP(3)) udly3f (.clk(clk), .ce(ce), .i(au.infinity), .o(aInf3));
ft_delay #(.WID(1), .DEP(3)) udly3g (.clk(clk), .ce(ce), .i(bu.infinity), .o(bInf3));
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Clock #4
355,9 → 362,7
reg nan12;
reg qnan12;
reg infinity12;
wire sxo11;
wire so11;
ft_delay #(.WID(1), .DEP(9)) udly12a (.clk(clk), .ce(ce), .i(sxo2), .o(sxo11));
ft_delay #(.WID(1), .DEP(7)) udly12b (.clk(clk), .ce(ce), .i(so4), .o(so11));
 
always_ff @(posedge clk)
388,9 → 393,6
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
// Clock #13
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
wire so; // sign output
wire [13:0] xo; // de normalized exponent output
wire [(N+1)*4*2-1:0] mo; // mantissa output
 
ft_delay #(.WID(1), .DEP(1)) u13c (.clk(clk), .ce(ce), .i(nan12), .o(o.nan) );
ft_delay #(.WID(1), .DEP(1)) u13d (.clk(clk), .ce(ce), .i(qnan12), .o(o.qnan) );
/trunk/rtl/verilog2/DFPNormalize96.sv
275,14 → 275,14
reg St6,St7;
ft_delay #(.WID(1),.DEP(1)) u71 (.clk(clk), .ce(ce), .i(rightOrLeft6), .o(rightOrLeft7));
 
wire [11:0] xo7d = xo6 - lshiftAmt6;
 
always_ff @(posedge clk)
if (ce)
xo7 <= zeroMan6 ? xo6 :
xInf6 ? xo6 : // an infinite exponent is either a NaN or infinity; no need to change
rightOrLeft6 ? 1'd0 : // on a right shift, the exponent was negative, it's being made to zero
xo7d; // on a left shift, the exponent can't be decremented below zero
casez({zeroMan6,xInf6,rightOrLeft6})
3'b1??: xo7 <= xo6;
3'b01?: xo7 <= xo6; // an infinite exponent is either a NaN or infinity; no need to change
3'b001: xo7 <= 'd0; // on a right shift, the exponent was negative, it's being made to zero
default: xo7 <= xo6 - lshiftAmt6[7:2]; // lshiftAmt6 is a multiple of four (whole digit)
endcase
 
always_ff @(posedge clk)
if (ce) mo7r <= mo6 >> rshiftAmt6;
/trunk/rtl/verilog2/DFPRound96.sv
153,7 → 153,7
delay3 #(1) u23 (.clk(clk), .ce(ce), .i(i.snan), .o(snano));
delay2 #(1) u24 (.clk(clk), .ce(ce), .i(i.infinity), .o(infinity2));
delay3 #(1) u25 (.clk(clk), .ce(ce), .i(i.sign), .o(so));
delay1 #(12) u26 (.clk(clk), .ce(ce), .i(xo2[13:0]), .o(xo));
delay1 #(12) u26 (.clk(clk), .ce(ce), .i(xo2[11:0]), .o(xo));
delay1 #(1) u27 (.clk(clk), .ce(ce), .i(infinity2 | (rnd2 && xo2[11:0]==12'hBFF)), .o(infinity));
`endif
 
/trunk/rtl/verilog2/DFPScaleb96.sv
0,0 → 1,134
// ============================================================================
// __
// \\__/ o\ (C) 2019-2022 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// DFPScaleb96.sv
// - floating point Scaleb()
//
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// ============================================================================
 
import DFPPkg::*;
 
module DFPScaleb96(clk, ce, a, b, o);
localparam N=25;
input clk;
input ce;
input DFP96 a;
input [31:0] b;
output DFP96 o;
 
wire [4:0] cmp_o;
wire nana, nanb;
wire xza, mza;
 
wire [11:0] infXp = 12'hBFF; // infinite / NaN - all ones
wire [11:0] bias = 12'h5FF;
wire xinfa;
wire anan;
reg anan1;
wire sa;
reg sa1, sa2;
wire [N*4-1:0] ma;
reg [13:0] xa1a, xa1b, xa2;
reg [N*4-1:0] ma1, ma2;
wire bs = b[31];
reg bs1;
 
DFP96U au, bu;
DFPUnpack96 u01 (a, au);
 
// ----------------------------------------------------------------------------
// Clock cycle 1
// ----------------------------------------------------------------------------
always @(posedge clk)
if (ce) xa1a <= au.exp;
always @(posedge clk)
if (ce) xa1b <= au.exp + b;
always @(posedge clk)
if (ce) bs1 <= bs;
always @(posedge clk)
if (ce) anan1 <= au.nan;
always @(posedge clk)
if (ce) sa1 <= au.sign;
always @(posedge clk)
if (ce) ma1 <= au.sig;
 
// ----------------------------------------------------------------------------
// Clock cycle 2
// ----------------------------------------------------------------------------
reg nan2;
reg qnan2;
reg snan2;
reg infinity2;
 
always @(posedge clk)
if (ce) sa2 <= sa1;
always @(posedge clk)
if (ce) nan2 <= anan1;
always @(posedge clk)
if (ce) qnan2 <= anan1 && ma1[N*4-1:N*4-4]==4'h1;
always @(posedge clk)
if (ce) snan2 <= anan1 && ma1[N*4-1:N*4-4]==4'h0;
always @(posedge clk)
if (ce) begin
if (anan1) begin
xa2 <= xa1a;
ma2 <= ma1;
end
// Underflow? -> limit exponent to zero
else if (bs1 & xa1b[13]) begin
xa2 <= 'd0;
ma2 <= ma1;
end
// overflow ? -> set value to infinity
else if (~bs1 & xa1b[12]) begin
xa2 <= infXp;
ma2 <= 'd0;
infinity2 <= 1'b1;
end
else begin
xa2 <= xa1b;
ma2 <= ma1;
end
end
 
assign bu.nan = nan2;
assign bu.snan = snan2;
assign bu.qnan = qnan2;
assign bu.infinity = infinity2;
assign bu.sign = sa2;
assign bu.exp = xa2;
assign bu.sig = ma2;
 
DFPPack96 u02 (bu, o);
 
endmodule
/trunk/rtl/verilog2/DFPSqrt96.sv
40,14 → 40,9
// ============================================================================
 
import DFPPkg::*;
import fp::*;
 
module DFPSqrt96(rst, clk, ce, ld, a, o, done, sqrinf, sqrneg);
parameter N=25;
localparam pShiftAmt =
FPWID==80 ? 48 :
FPWID==64 ? 36 :
FPWID==32 ? 7 : (FMSB+1-16);
input rst;
input clk;
input ce;
63,6 → 58,7
reg inf;
reg overflow;
reg underflow;
wire sign = 1'b0;
 
wire so;
wire [13:0] xo;
/trunk/test_bench/DFPAddsub96_tb.v
80,7 → 80,7
end
endgenerate
 
reg [7:0] count;
reg [15:0] count;
always @(posedge clk)
if (rst) begin
adr <= 0;
93,7 → 93,7
$fwrite(outfile, " rm ------- A ------ ------- B ------ ------ sum ----- -- SIM Sum --\n");
end
count <= count + 1;
if (count > 35)
if (count > 50)
count <= 1'd1;
if (count==2) begin
a <= a1;
104,21 → 104,26
//ad <= memd[adr][63: 0];
//bd <= memd[adr][127:64];
end
if (adr==1 && count==2) begin
a <= 96'h25ff00000000000000000000; // 1
b <= 96'h25ff00000000000000000000; // 1
//-0 543771554911558566002677 581816070341546924523033 543771554911558566002677
 
if (adr==3 && count==2) begin
a <= 96'h543771554911558566002677;
b <= 96'h543716070341546924523033;
//a <= 96'h25ff00000000000000000000; // 1
//b <= 96'h25ff00000000000000000000; // 1
end
if (adr==2 && count==2) begin
a <= 96'h260000000000000000000000; // 10
b <= 96'h260000000000000000000000; // 10
b <= 96'h25ff00000000000000000000; // 1
end
if (adr==3 && count==2) begin
if (adr==1 && count==2) begin
a <= 96'h260100000000000000000000; // 100
b <= 96'h260100000000000000000000; // 100
b <= 96'h25ff00000000000000000000; // 1
end
if (adr==4 && count==2) begin
a <= 96'h260200000000000000000000; // 1000
b <= 96'h260200000000000000000000; // 1000
b <= 96'h25ff00000000000000000000; // 1
end
if (adr==5 && count==2) begin
a <= 96'h26064D2E7030000000000000; // 12345678
132,8 → 137,8
a <= 96'h440040000000000000000000;
b <= 96'h440040000000000000000000;
end
if (count==35) begin
if (adr[11]) begin
if (count==50) begin
if (~adr[11]) begin
$fwrite(outfile, "%c%h\t%h\t%h\t%h\n", "-",rm, a, b, o);
end
else begin
147,7 → 152,7
DFPAddsub96nr u6 (
.clk(clk),
.ce(1'b1),
.op(adr[11]),
.op(~adr[11]),
.a(a),
.b(b),
.o(o),
/trunk/test_bench/DFPScaleb96_tb.v
0,0 → 1,162
`timescale 1ns / 1ps
// ============================================================================
// __
// \\__/ o\ (C) 2006-2022 Robert Finch, Waterloo
// \ __ / All rights reserved.
// \/_// robfinch<remove>@finitron.ca
// ||
//
// DFPScaleb96_tb.v
// - decimal floating point addsub test bench
//
// BSD 3-Clause License
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice, this
// list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// ============================================================================
 
module DFPScaleb96_tb();
reg rst;
reg clk;
reg [15:0] adr;
reg [95:0] a;
reg [31:0] b;
wire [95:0] o;
reg [95:0] ad,bd;
reg [95:0] od;
reg [3:0] rm;
 
integer n;
reg [95:0] a1;
reg [31:0] b1;
wire [63:0] doubleA = {a[31], a[30], {3{~a[30]}}, a[29:23], a[22:0], {29{1'b0}}};
wire [63:0] doubleB = {b[31], b[30], {3{~b[30]}}, b[29:23], b[22:0], {29{1'b0}}};
 
integer outfile;
 
initial begin
rst = 1'b0;
clk = 1'b0;
adr = 0;
a = $urandom(1);
b = 1;
#20 rst = 1;
#50 rst = 0;
#10000000 $fclose(outfile);
#10 $finish;
end
 
always #5
clk = ~clk;
 
genvar g;
generate begin : gRand
for (g = 0; g < 96; g = g + 4) begin
always @(posedge clk) begin
a1[g+3:g] <= $urandom() % 10;
end
end
always @(posedge clk)
b1 <= $urandom();
end
endgenerate
 
reg [7:0] count;
always @(posedge clk)
if (rst) begin
adr <= 0;
count <= 0;
end
else
begin
if (adr==0) begin
outfile = $fopen("f:/cores2022/Float/dfpu/test_bench/DFPScaleb96_tvo.txt", "wb");
$fwrite(outfile, " rm ------- A ------ ------- B ------ ------ sum ----- -- SIM Sum --\n");
end
count <= count + 1;
if (count > 35)
count <= 1'd1;
if (count==2) begin
a <= a1;
b <= b1;
a[95:92] <= 4'h5;
rm <= adr[14:12];
//ad <= memd[adr][63: 0];
//bd <= memd[adr][127:64];
end
//-0 543771554911558566002677 581816070341546924523033 543771554911558566002677
 
if (adr==3 && count==2) begin
a <= 96'h543771554911558566002677;
b <= 32'h0;
//a <= 96'h25ff00000000000000000000; // 1
//b <= 96'h25ff00000000000000000000; // 1
end
if (adr==2 && count==2) begin
a <= 96'h260000000000000000000000; // 10
b <= 32'h1; // 10
end
if (adr==1 && count==2) begin
a <= 96'h260100000000000000000000; // 100
b <= 32'h2; // 100
end
if (adr==4 && count==2) begin
a <= 96'h260200000000000000000000; // 1000
b <= 32'h3; // 1000
end
if (adr==5 && count==2) begin
a <= 96'h26064D2E7030000000000000; // 12345678
b <= 32'h1; // 10
end
if (adr==6 && count==2) begin
a <= 96'h440000000000000000000000;
b <= 32'h4;
end
if (adr==7 && count==2) begin
a <= 96'h440040000000000000000000;
b <= 32'h5;
end
if (count==35) begin
if (adr[11]) begin
$fwrite(outfile, "%c%h\t%h\t%h\t%h\n", "-",rm, a, b, o);
end
else begin
$fwrite(outfile, "%c%h\t%h\t%h\t%h\n", "+",rm, a, b, o);
end
adr <= adr + 1;
end
end
 
//fpMulnr #(64) u1 (clk, 1'b1, a, b, o, rm);//, sign_exe, inf, overflow, underflow);
DFPScaleb96 u6 (
.clk(clk),
.ce(1'b1),
.a(a),
.b(b),
.o(o)
);
 
endmodule
/trunk/test_bench/i2df128_tb.sv
81,7 → 81,7
else
begin
if (adr==0) begin
outfile = $fopen("d:/cores2022/rf6809/rtl/dfpu/test_bench/i2df128_tvo.txt", "wb");
outfile = $fopen("f:/cores2022/float/dfpu/test_bench/i2df128_tvo.txt", "wb");
$fwrite(outfile, "s ------ bin ------ ------ flt ------ \n");
end
count <= count + 1;
100,6 → 100,9
bin <= 128'd1000;
end
if (adr==5) begin
bin <= 128'd1000000;
end
if (adr==6) begin
bin <= 128'd12345678;
end
if (count==140) begin

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