URL
https://opencores.org/ocsvn/ft816float/ft816float/trunk
Subversion Repositories ft816float
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/ft816float
- from Rev 82 to Rev 83
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Rev 82 → Rev 83
/trunk/rtl/verilog2/dfdiv.v
File deleted
/trunk/rtl/verilog2/BCDSubtract.sv
45,14 → 45,14
output reg [N*4-1:0] o; |
output reg sgn; |
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wire [(N+1)*4-1:0] bc; |
wire [(N+1)*4-1:0] o1, o2, o3; |
wire [(N)*4-1:0] bc; |
wire [(N)*4-1:0] o1, o2, o3; |
wire c; |
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BCDNinesComplementN #(N+1) u1 (.i({4'h0,b}), .o(bc)); |
BCDAddNClk #(.N(N+1)) u2 (.clk(clk), .a({8'h00,a}), .b(bc), .o(o1), .ci(1'b0), .co(c)); |
BCDNinesComplementN #(N) u1 (.i({4'h0,b}), .o(bc)); |
BCDAddNClk #(.N(N)) u2 (.clk(clk), .a({8'h00,a}), .b(bc), .o(o1), .ci(1'b0), .co(c)); |
BCDNinesComplementN #(N) u3 (.i(o1), .o(o2)); |
BCDAddNClk #(.N(N+1)) u4 (.clk(clk), .a(o1), .b('d0), .o(o3), .ci(c), .co()); |
BCDAddNClk #(.N(N)) u4 (.clk(clk), .a(o1), .b('d0), .o(o3), .ci(c), .co()); |
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always_ff @(posedge clk) |
if (c) |
60,7 → 60,7
else |
o <= o2; |
always_ff @(posedge clk) |
sgn <= ~c; |
sgn <= |o ? ~c : 1'b0; |
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endmodule |
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