OpenCores
URL https://opencores.org/ocsvn/funbase_ip_library/funbase_ip_library/trunk

Subversion Repositories funbase_ip_library

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  • This comparison shows the changes necessary to convert path
    /funbase_ip_library/trunk
    from Rev 159 to Rev 160
    Reverse comparison

Rev 159 → Rev 160

/TUT/ip.hwp.interface/udp_ip/1.0/ip-xact/udp_ip_dm9000a.1.0.xml
768,9 → 768,6
<spirit:left>47</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
<spirit:driver>
<spirit:defaultValue>0</spirit:defaultValue>
</spirit:driver>
</spirit:wire>
<spirit:vendorExtensions/>
</spirit:port>
/TUT/ip.hwp.interface/hibi_udp/1.0/hibi_udp.1.0.xml
10,10 → 10,37
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
<spirit:name>hibi_slave</spirit:name>
<spirit:name>clk_udp</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.busdef" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.absDef" spirit:version="1.0"/>
<spirit:slave/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>clk_udp</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>hibi_master</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="hibi_ip_r4.busdef" spirit:version="3.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="hibi_ip_r4.absdef" spirit:version="3.0"/>
<spirit:slave/>
<spirit:master/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
25,7 → 52,7
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_av_in</spirit:name>
<spirit:name>hibi_av_out</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
41,7 → 68,7
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_comm_in</spirit:name>
<spirit:name>hibi_comm_out</spirit:name>
<spirit:vector>
<spirit:left>4</spirit:left>
<spirit:right>0</spirit:right>
57,7 → 84,7
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_data_in</spirit:name>
<spirit:name>hibi_data_out</spirit:name>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
66,7 → 93,7
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>EMPTY</spirit:name>
<spirit:name>RE</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
73,7 → 100,7
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_empty_in</spirit:name>
<spirit:name>hibi_re_out</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
82,7 → 109,7
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>FULL</spirit:name>
<spirit:name>WE</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
89,7 → 116,7
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_full_in</spirit:name>
<spirit:name>hibi_we_out</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
101,10 → 128,10
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>hibi_master</spirit:name>
<spirit:name>hibi_slave</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="hibi_ip_r4.busdef" spirit:version="3.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.communication" spirit:name="hibi_ip_r4.absdef" spirit:version="3.0"/>
<spirit:master/>
<spirit:slave/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
116,7 → 143,7
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_av_out</spirit:name>
<spirit:name>hibi_av_in</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
132,7 → 159,7
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_comm_out</spirit:name>
<spirit:name>hibi_comm_in</spirit:name>
<spirit:vector>
<spirit:left>4</spirit:left>
<spirit:right>0</spirit:right>
148,7 → 175,7
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_data_out</spirit:name>
<spirit:name>hibi_data_in</spirit:name>
<spirit:vector>
<spirit:left>31</spirit:left>
<spirit:right>0</spirit:right>
157,7 → 184,7
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>RE</spirit:name>
<spirit:name>EMPTY</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
164,7 → 191,7
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_re_out</spirit:name>
<spirit:name>hibi_empty_in</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
173,7 → 200,7
</spirit:portMap>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>WE</spirit:name>
<spirit:name>FULL</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
180,7 → 207,7
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>hibi_we_out</spirit:name>
<spirit:name>hibi_full_in</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
192,7 → 219,7
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>clk_udp</spirit:name>
<spirit:name>clk</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.busdef" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.absDef" spirit:version="1.0"/>
<spirit:slave/>
207,7 → 234,7
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>clk_udp</spirit:name>
<spirit:name>clk</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
384,33 → 411,6
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
<spirit:busInterface>
<spirit:name>clk</spirit:name>
<spirit:busType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.busdef" spirit:version="1.0"/>
<spirit:abstractionType spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="clock.absDef" spirit:version="1.0"/>
<spirit:slave/>
<spirit:connectionRequired>false</spirit:connectionRequired>
<spirit:portMaps>
<spirit:portMap>
<spirit:logicalPort>
<spirit:name>CLK</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:logicalPort>
<spirit:physicalPort>
<spirit:name>clk</spirit:name>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>0</spirit:right>
</spirit:vector>
</spirit:physicalPort>
</spirit:portMap>
</spirit:portMaps>
<spirit:bitsInLau>8</spirit:bitsInLau>
<spirit:endianness>little</spirit:endianness>
</spirit:busInterface>
</spirit:busInterfaces>
<spirit:model>
<spirit:views>
418,7 → 418,19
<spirit:name>structural</spirit:name>
<spirit:envIdentifier>::</spirit:envIdentifier>
<spirit:hierarchyRef spirit:vendor="TUT" spirit:library="ip.hwp.interface" spirit:name="hibi_udp.designcfg" spirit:version="1.0"/>
<spirit:vendorExtensions>
<kactus2:topLevelViewRef>structural_vhd</kactus2:topLevelViewRef>
</spirit:vendorExtensions>
</spirit:view>
<spirit:view>
<spirit:name>structural_vhd</spirit:name>
<spirit:envIdentifier>VHDL:Kactus2:</spirit:envIdentifier>
<spirit:language spirit:strict="false">vhdl</spirit:language>
<spirit:modelName>hibi_udp(structural)</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>structural_vhdlSource</spirit:localName>
</spirit:fileSetRef>
</spirit:view>
</spirit:views>
<spirit:ports>
<spirit:port>
435,6 → 447,7
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>structural</spirit:viewNameRef>
<spirit:viewNameRef>structural_vhd</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
454,6 → 467,7
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>structural</spirit:viewNameRef>
<spirit:viewNameRef>structural_vhd</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
473,6 → 487,7
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>structural</spirit:viewNameRef>
<spirit:viewNameRef>structural_vhd</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
492,6 → 507,7
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>structural</spirit:viewNameRef>
<spirit:viewNameRef>structural_vhd</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
511,6 → 527,7
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>structural</spirit:viewNameRef>
<spirit:viewNameRef>structural_vhd</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
530,6 → 547,7
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>structural</spirit:viewNameRef>
<spirit:viewNameRef>structural_vhd</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
549,6 → 567,7
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>structural</spirit:viewNameRef>
<spirit:viewNameRef>structural_vhd</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
568,6 → 587,7
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>structural</spirit:viewNameRef>
<spirit:viewNameRef>structural_vhd</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
587,6 → 607,7
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>structural</spirit:viewNameRef>
<spirit:viewNameRef>structural_vhd</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
606,6 → 627,7
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>structural</spirit:viewNameRef>
<spirit:viewNameRef>structural_vhd</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
625,6 → 647,7
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>structural</spirit:viewNameRef>
<spirit:viewNameRef>structural_vhd</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
644,6 → 667,7
<spirit:typeDefinition>IEEE.std_logic_1164.all</spirit:typeDefinition>
<spirit:viewNameRef>rtl</spirit:viewNameRef>
<spirit:viewNameRef>structural</spirit:viewNameRef>
<spirit:viewNameRef>structural_vhd</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
750,6 → 774,41
</spirit:port>
</spirit:ports>
</spirit:model>
<spirit:fileSets>
<spirit:fileSet>
<spirit:name>structural_vhdlSource</spirit:name>
<spirit:group>sourceFiles</spirit:group>
<spirit:file>
<spirit:name>vhd/hibi_udp.vhd</spirit:name>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:isIncludeFile spirit:externalDeclarations="false">true</spirit:isIncludeFile>
<spirit:logicalName spirit:default="false">work</spirit:logicalName>
<spirit:buildCommand>
<spirit:command>vcom</spirit:command>
<spirit:flags>-quiet -check_synthesis -work work</spirit:flags>
<spirit:replaceDefaultFlags>true</spirit:replaceDefaultFlags>
</spirit:buildCommand>
</spirit:file>
<spirit:defaultFileBuilder>
<spirit:fileType>vhdlSource</spirit:fileType>
<spirit:command>vcom</spirit:command>
<spirit:flags>-quiet -check_synthesis -work work</spirit:flags>
<spirit:replaceDefaultFlags>true</spirit:replaceDefaultFlags>
</spirit:defaultFileBuilder>
<spirit:defaultFileBuilder>
<spirit:fileType>vhdlSource-87</spirit:fileType>
<spirit:command>vcom</spirit:command>
<spirit:flags>-quiet -check_synthesis -work work</spirit:flags>
<spirit:replaceDefaultFlags>true</spirit:replaceDefaultFlags>
</spirit:defaultFileBuilder>
<spirit:defaultFileBuilder>
<spirit:fileType>vhdlSource-93</spirit:fileType>
<spirit:command>vcom</spirit:command>
<spirit:flags>-quiet -check_synthesis -work work</spirit:flags>
<spirit:replaceDefaultFlags>true</spirit:replaceDefaultFlags>
</spirit:defaultFileBuilder>
</spirit:fileSet>
</spirit:fileSets>
<spirit:vendorExtensions>
<kactus2:extensions>
<kactus2:kts_attributes>
/TUT/ip.hwp.interface/hibi_udp/1.0/vhd/hibi_udp.vhd
0,0 → 1,294
-- ***************************************************
-- File: hibi_udp.vhd
-- Creation date: 12.02.2013
-- Creation time: 10:37:46
-- Description:
-- Created by: matilail
-- This file was generated with Kactus2 vhdl generator.
-- ***************************************************
library IEEE;
library udp2hibi;
library work;
use IEEE.std_logic_1164.all;
use udp2hibi.all;
use work.all;
 
entity hibi_udp is
 
port (
 
-- Interface: clk
clk : in std_logic;
 
-- Interface: clk_udp
clk_udp : in std_logic;
 
-- Interface: DM9000A
eth_interrupt_in : in std_logic;
eth_chip_sel_out : out std_logic;
eth_clk_out : out std_logic;
eth_cmd_out : out std_logic;
eth_read_out : out std_logic;
eth_reset_out : out std_logic;
eth_write_out : out std_logic;
eth_data_inout : inout std_logic_vector(15 downto 0);
 
-- Interface: hibi_master
hibi_av_out : out std_logic;
hibi_comm_out : out std_logic_vector(4 downto 0);
hibi_data_out : out std_logic_vector(31 downto 0);
hibi_re_out : out std_logic;
hibi_we_out : out std_logic;
 
-- Interface: hibi_slave
hibi_av_in : in std_logic;
hibi_comm_in : in std_logic_vector(4 downto 0);
hibi_data_in : in std_logic_vector(31 downto 0);
hibi_empty_in : in std_logic;
hibi_full_in : in std_logic;
 
-- Interface: rst_n
rst_n : in std_logic
);
 
end hibi_udp;
 
 
architecture structural of hibi_udp is
 
signal udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxdest_port_out : std_logic_vector(15 downto 0);
signal udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxlink_up_out : std_logic;
signal udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxnew_rx_out : std_logic;
signal udp2hibi_0_udp_ip_tx_to_udp_ip_dm9000a_0_app_txnew_tx_in : std_logic;
signal udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxrx_data_out : std_logic_vector(15 downto 0);
signal udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxrx_data_valid_out : std_logic;
signal udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxrx_erroneous_out : std_logic;
signal udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxrx_len_out : std_logic_vector(10 downto 0);
signal udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxrx_re_in : std_logic;
signal udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxsource_addr_out : std_logic_vector(31 downto 0);
signal udp2hibi_0_udp_ip_tx_to_udp_ip_dm9000a_0_app_txsource_port_in : std_logic_vector(15 downto 0);
signal udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxsource_port_out : std_logic_vector(15 downto 0);
signal udp2hibi_0_udp_ip_tx_to_udp_ip_dm9000a_0_app_txtarget_addr_in : std_logic_vector(31 downto 0);
signal udp2hibi_0_udp_ip_tx_to_udp_ip_dm9000a_0_app_txtarget_port_in : std_logic_vector(15 downto 0);
signal udp2hibi_0_udp_ip_tx_to_udp_ip_dm9000a_0_app_txtx_data_in : std_logic_vector(15 downto 0);
signal udp2hibi_0_udp_ip_tx_to_udp_ip_dm9000a_0_app_txtx_data_valid_in : std_logic;
signal udp2hibi_0_udp_ip_tx_to_udp_ip_dm9000a_0_app_txtx_len_in : std_logic_vector(10 downto 0);
signal udp2hibi_0_udp_ip_tx_to_udp_ip_dm9000a_0_app_txtx_re_out : std_logic;
 
-- - Interface between a UDP/IP block and the HIBI bus.
-- - Capable of handling one transmission and one incoming packet at a time
-- - UDP2HIBI uses HIBI addresses to separate transfers from different agents
-- - So all agents must use different addresses when sending to UDP2HIBI
--
component udp2hibi
generic (
ack_fifo_depth_g : integer := 4;
frequency_g : integer := 50000000;
hibi_addr_width_g : integer := 32;
hibi_comm_width_g : integer := 5;
hibi_data_width_g : integer := 32;
hibi_tx_fifo_depth_g : integer := 10;
receiver_table_size_g : integer := 4;
rx_multiclk_fifo_depth_g : integer := 10;
tx_multiclk_fifo_depth_g : integer := 10
 
);
port (
 
-- Interface: clk
-- clock input
clk : in std_logic;
 
-- Interface: clk_udp
-- clock udp input (25MHz)
clk_udp : in std_logic;
 
-- Interface: hibi_master
-- HIBI master interface
hibi_av_out : out std_logic;
hibi_comm_out : out std_logic_vector(4 downto 0);
hibi_data_out : out std_logic_vector(31 downto 0);
hibi_re_out : out std_logic;
hibi_we_out : out std_logic;
 
-- Interface: hibi_slave
-- HIBI slave interface
hibi_av_in : in std_logic;
hibi_comm_in : in std_logic_vector(4 downto 0);
hibi_data_in : in std_logic_vector(31 downto 0);
hibi_empty_in : in std_logic;
hibi_full_in : in std_logic;
 
-- Interface: rst_n
-- active low reset
rst_n : in std_logic;
 
-- Interface: udp_ip_rx
-- udp_ip_rx
dest_port_in : in std_logic_vector(15 downto 0);
eth_link_up_in : in std_logic;
new_rx_in : in std_logic;
rx_data_in : in std_logic_vector(15 downto 0);
rx_data_valid_in : in std_logic;
rx_erroneous_in : in std_logic;
rx_len_in : in std_logic_vector(10 downto 0);
source_ip_in : in std_logic_vector(31 downto 0);
source_port_in : in std_logic_vector(15 downto 0);
rx_re_out : out std_logic;
 
-- Interface: udp_ip_tx
-- udp_ip_tx
tx_re_in : in std_logic;
dest_ip_out : out std_logic_vector(31 downto 0);
dest_port_out : out std_logic_vector(15 downto 0);
new_tx_out : out std_logic;
source_port_out : out std_logic_vector(15 downto 0);
tx_data_out : out std_logic_vector(15 downto 0);
tx_data_valid_out : out std_logic;
tx_len_out : out std_logic_vector(10 downto 0)
 
);
end component;
 
-- DM9000A controller and UDP/IP.
component udp_ip_dm9000a
generic (
disable_arp_g : integer := 0;
disable_rx_g : integer := 0
 
);
port (
 
-- Interface: app_rx
-- Application receive operations
rx_re_in : in std_logic;
dest_port_out : out std_logic_vector(15 downto 0);
new_rx_out : out std_logic;
rx_data_out : out std_logic_vector(15 downto 0);
rx_data_valid_out : out std_logic;
rx_erroneous_out : out std_logic;
-- rx_error_out : out std_logic;
rx_len_out : out std_logic_vector(10 downto 0);
source_addr_out : out std_logic_vector(31 downto 0);
source_port_out : out std_logic_vector(15 downto 0);
 
-- Interface: app_tx
-- Application transmit operations
new_tx_in : in std_logic;
-- no_arp_target_MAC_in : in std_logic_vector(47 downto 0);
source_port_in : in std_logic_vector(15 downto 0);
target_addr_in : in std_logic_vector(31 downto 0);
target_port_in : in std_logic_vector(15 downto 0);
tx_data_in : in std_logic_vector(15 downto 0);
tx_data_valid_in : in std_logic;
tx_len_in : in std_logic_vector(10 downto 0);
tx_re_out : out std_logic;
 
-- Interface: clk
-- Clock 25 MHz in.
clk : in std_logic;
 
-- Interface: DM9000A
-- Connection to the DM9000A chip via IO pins.
eth_interrupt_in : in std_logic;
eth_chip_sel_out : out std_logic;
eth_clk_out : out std_logic;
eth_cmd_out : out std_logic;
eth_read_out : out std_logic;
eth_reset_out : out std_logic;
eth_write_out : out std_logic;
eth_data_inout : inout std_logic_vector(15 downto 0);
 
-- Interface: rst_n
-- Asynchronous reset active-low.
rst_n : in std_logic;
 
-- There ports are contained in many interfaces
-- fatal_error_out : out std_logic;
link_up_out : out std_logic
 
);
end component;
 
-- You can write vhdl code after this tag and it is saved through the generator.
-- ##KACTUS2_BLACK_BOX_DECLARATIONS_BEGIN##
-- ##KACTUS2_BLACK_BOX_DECLARATIONS_END##
-- Stop writing your code after this tag.
 
 
begin
 
-- You can write vhdl code after this tag and it is saved through the generator.
-- ##KACTUS2_BLACK_BOX_ASSIGNMENTS_BEGIN##
-- ##KACTUS2_BLACK_BOX_ASSIGNMENTS_END##
-- Stop writing your code after this tag.
 
udp2hibi_0 : udp2hibi
port map (
clk => clk,
clk_udp => clk_udp,
dest_ip_out(31 downto 0) => udp2hibi_0_udp_ip_tx_to_udp_ip_dm9000a_0_app_txtarget_addr_in(31 downto 0),
dest_port_in(15 downto 0) => udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxdest_port_out(15 downto 0),
dest_port_out(15 downto 0) => udp2hibi_0_udp_ip_tx_to_udp_ip_dm9000a_0_app_txtarget_port_in(15 downto 0),
eth_link_up_in => udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxlink_up_out,
hibi_av_in => hibi_av_in,
hibi_av_out => hibi_av_out,
hibi_comm_in(4 downto 0) => hibi_comm_in(4 downto 0),
hibi_comm_out(4 downto 0) => hibi_comm_out(4 downto 0),
hibi_data_in(31 downto 0) => hibi_data_in(31 downto 0),
hibi_data_out(31 downto 0) => hibi_data_out(31 downto 0),
hibi_empty_in => hibi_empty_in,
hibi_full_in => hibi_full_in,
hibi_re_out => hibi_re_out,
hibi_we_out => hibi_we_out,
new_rx_in => udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxnew_rx_out,
new_tx_out => udp2hibi_0_udp_ip_tx_to_udp_ip_dm9000a_0_app_txnew_tx_in,
rst_n => rst_n,
rx_data_in(15 downto 0) => udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxrx_data_out(15 downto 0),
rx_data_valid_in => udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxrx_data_valid_out,
rx_erroneous_in => udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxrx_erroneous_out,
rx_len_in(10 downto 0) => udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxrx_len_out(10 downto 0),
rx_re_out => udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxrx_re_in,
source_ip_in(31 downto 0) => udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxsource_addr_out(31 downto 0),
source_port_in(15 downto 0) => udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxsource_port_out(15 downto 0),
source_port_out(15 downto 0) => udp2hibi_0_udp_ip_tx_to_udp_ip_dm9000a_0_app_txsource_port_in(15 downto 0),
tx_data_out(15 downto 0) => udp2hibi_0_udp_ip_tx_to_udp_ip_dm9000a_0_app_txtx_data_in(15 downto 0),
tx_data_valid_out => udp2hibi_0_udp_ip_tx_to_udp_ip_dm9000a_0_app_txtx_data_valid_in,
tx_len_out(10 downto 0) => udp2hibi_0_udp_ip_tx_to_udp_ip_dm9000a_0_app_txtx_len_in(10 downto 0),
tx_re_in => udp2hibi_0_udp_ip_tx_to_udp_ip_dm9000a_0_app_txtx_re_out
);
 
udp_ip_dm9000a_0 : udp_ip_dm9000a
port map (
clk => clk,
dest_port_out(15 downto 0) => udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxdest_port_out(15 downto 0),
eth_chip_sel_out => eth_chip_sel_out,
eth_clk_out => eth_clk_out,
eth_cmd_out => eth_cmd_out,
eth_data_inout(15 downto 0) => eth_data_inout(15 downto 0),
eth_interrupt_in => eth_interrupt_in,
eth_read_out => eth_read_out,
eth_reset_out => eth_reset_out,
eth_write_out => eth_write_out,
link_up_out => udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxlink_up_out,
new_rx_out => udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxnew_rx_out,
new_tx_in => udp2hibi_0_udp_ip_tx_to_udp_ip_dm9000a_0_app_txnew_tx_in,
rst_n => rst_n,
rx_data_out(15 downto 0) => udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxrx_data_out(15 downto 0),
rx_data_valid_out => udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxrx_data_valid_out,
rx_erroneous_out => udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxrx_erroneous_out,
rx_len_out(10 downto 0) => udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxrx_len_out(10 downto 0),
rx_re_in => udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxrx_re_in,
source_addr_out(31 downto 0) => udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxsource_addr_out(31 downto 0),
source_port_in(15 downto 0) => udp2hibi_0_udp_ip_tx_to_udp_ip_dm9000a_0_app_txsource_port_in(15 downto 0),
source_port_out(15 downto 0) => udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rxsource_port_out(15 downto 0),
target_addr_in(31 downto 0) => udp2hibi_0_udp_ip_tx_to_udp_ip_dm9000a_0_app_txtarget_addr_in(31 downto 0),
target_port_in(15 downto 0) => udp2hibi_0_udp_ip_tx_to_udp_ip_dm9000a_0_app_txtarget_port_in(15 downto 0),
tx_data_in(15 downto 0) => udp2hibi_0_udp_ip_tx_to_udp_ip_dm9000a_0_app_txtx_data_in(15 downto 0),
tx_data_valid_in => udp2hibi_0_udp_ip_tx_to_udp_ip_dm9000a_0_app_txtx_data_valid_in,
tx_len_in(10 downto 0) => udp2hibi_0_udp_ip_tx_to_udp_ip_dm9000a_0_app_txtx_len_in(10 downto 0),
tx_re_out => udp2hibi_0_udp_ip_tx_to_udp_ip_dm9000a_0_app_txtx_re_out
);
 
end structural;
 
/TUT/ip.hwp.interface/hibi_udp/1.0/hibi_udp.design.1.0.xml
76,106 → 76,106
</spirit:componentInstances>
<spirit:interconnections>
<spirit:interconnection>
<spirit:name>udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rx</spirit:name>
<spirit:name>udp2hibi_0_udp_ip_tx_to_udp_ip_dm9000a_0_app_tx</spirit:name>
<spirit:displayName></spirit:displayName>
<spirit:description></spirit:description>
<spirit:activeInterface spirit:componentRef="udp_ip_dm9000a_0" spirit:busRef="app_rx"/>
<spirit:activeInterface spirit:componentRef="udp2hibi_0" spirit:busRef="udp_ip_rx"/>
<spirit:activeInterface spirit:componentRef="udp2hibi_0" spirit:busRef="udp_ip_tx"/>
<spirit:activeInterface spirit:componentRef="udp_ip_dm9000a_0" spirit:busRef="app_tx"/>
</spirit:interconnection>
<spirit:interconnection>
<spirit:name>udp2hibi_0_udp_ip_tx_to_udp_ip_dm9000a_0_app_tx</spirit:name>
<spirit:name>udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rx</spirit:name>
<spirit:displayName></spirit:displayName>
<spirit:description></spirit:description>
<spirit:activeInterface spirit:componentRef="udp2hibi_0" spirit:busRef="udp_ip_tx"/>
<spirit:activeInterface spirit:componentRef="udp_ip_dm9000a_0" spirit:busRef="app_tx"/>
<spirit:activeInterface spirit:componentRef="udp_ip_dm9000a_0" spirit:busRef="app_rx"/>
<spirit:activeInterface spirit:componentRef="udp2hibi_0" spirit:busRef="udp_ip_rx"/>
</spirit:interconnection>
</spirit:interconnections>
<spirit:hierConnections>
<spirit:hierConnection spirit:interfaceRef="rst_n">
<spirit:interface spirit:componentRef="udp2hibi_0" spirit:busRef="rst_n"/>
<spirit:hierConnection spirit:interfaceRef="clk_udp">
<spirit:interface spirit:componentRef="udp2hibi_0" spirit:busRef="clk_udp"/>
<spirit:vendorExtensions>
<kactus2:position x="90" y="130"/>
<kactus2:direction x="1" y="0"/>
<kactus2:route kactus2:offPage="true">
<kactus2:position x="400" y="180"/>
<kactus2:position x="90" y="130"/>
<kactus2:position x="700" y="100"/>
<kactus2:direction x="-1" y="0"/>
<kactus2:route kactus2:offPage="false">
<kactus2:position x="590" y="100"/>
<kactus2:position x="700" y="100"/>
</kactus2:route>
</spirit:vendorExtensions>
</spirit:hierConnection>
<spirit:hierConnection spirit:interfaceRef="rst_n">
<spirit:interface spirit:componentRef="udp_ip_dm9000a_0" spirit:busRef="rst_n"/>
<spirit:hierConnection spirit:interfaceRef="hibi_master">
<spirit:interface spirit:componentRef="udp2hibi_0" spirit:busRef="hibi_master"/>
<spirit:vendorExtensions>
<kactus2:position x="90" y="130"/>
<kactus2:direction x="1" y="0"/>
<kactus2:route kactus2:offPage="true">
<kactus2:position x="140" y="120"/>
<kactus2:position x="90" y="130"/>
<kactus2:position x="700" y="150"/>
<kactus2:direction x="-1" y="0"/>
<kactus2:route kactus2:offPage="false">
<kactus2:position x="590" y="150"/>
<kactus2:position x="700" y="150"/>
</kactus2:route>
</spirit:vendorExtensions>
</spirit:hierConnection>
<spirit:hierConnection spirit:interfaceRef="DM9000A">
<spirit:interface spirit:componentRef="udp_ip_dm9000a_0" spirit:busRef="DM9000A"/>
<spirit:hierConnection spirit:interfaceRef="hibi_slave">
<spirit:interface spirit:componentRef="udp2hibi_0" spirit:busRef="hibi_slave"/>
<spirit:vendorExtensions>
<kactus2:position x="60" y="170"/>
<kactus2:direction x="1" y="0"/>
<kactus2:position x="700" y="190"/>
<kactus2:direction x="-1" y="0"/>
<kactus2:route kactus2:offPage="false">
<kactus2:position x="170" y="170"/>
<kactus2:position x="60" y="170"/>
<kactus2:position x="590" y="190"/>
<kactus2:position x="700" y="190"/>
</kactus2:route>
</spirit:vendorExtensions>
</spirit:hierConnection>
<spirit:hierConnection spirit:interfaceRef="clk">
<spirit:interface spirit:componentRef="udp2hibi_0" spirit:busRef="clk"/>
<spirit:interface spirit:componentRef="udp_ip_dm9000a_0" spirit:busRef="clk"/>
<spirit:vendorExtensions>
<kactus2:position x="90" y="100"/>
<kactus2:direction x="1" y="0"/>
<kactus2:route kactus2:offPage="true">
<kactus2:position x="400" y="160"/>
<kactus2:position x="140" y="100"/>
<kactus2:position x="90" y="100"/>
</kactus2:route>
</spirit:vendorExtensions>
</spirit:hierConnection>
<spirit:hierConnection spirit:interfaceRef="clk">
<spirit:interface spirit:componentRef="udp_ip_dm9000a_0" spirit:busRef="clk"/>
<spirit:interface spirit:componentRef="udp2hibi_0" spirit:busRef="clk"/>
<spirit:vendorExtensions>
<kactus2:position x="90" y="100"/>
<kactus2:direction x="1" y="0"/>
<kactus2:route kactus2:offPage="true">
<kactus2:position x="140" y="100"/>
<kactus2:position x="400" y="160"/>
<kactus2:position x="90" y="100"/>
</kactus2:route>
</spirit:vendorExtensions>
</spirit:hierConnection>
<spirit:hierConnection spirit:interfaceRef="hibi_slave">
<spirit:interface spirit:componentRef="udp2hibi_0" spirit:busRef="hibi_slave"/>
<spirit:hierConnection spirit:interfaceRef="DM9000A">
<spirit:interface spirit:componentRef="udp_ip_dm9000a_0" spirit:busRef="DM9000A"/>
<spirit:vendorExtensions>
<kactus2:position x="700" y="190"/>
<kactus2:direction x="-1" y="0"/>
<kactus2:position x="60" y="170"/>
<kactus2:direction x="1" y="0"/>
<kactus2:route kactus2:offPage="false">
<kactus2:position x="590" y="190"/>
<kactus2:position x="700" y="190"/>
<kactus2:position x="170" y="170"/>
<kactus2:position x="60" y="170"/>
</kactus2:route>
</spirit:vendorExtensions>
</spirit:hierConnection>
<spirit:hierConnection spirit:interfaceRef="hibi_master">
<spirit:interface spirit:componentRef="udp2hibi_0" spirit:busRef="hibi_master"/>
<spirit:hierConnection spirit:interfaceRef="rst_n">
<spirit:interface spirit:componentRef="udp_ip_dm9000a_0" spirit:busRef="rst_n"/>
<spirit:vendorExtensions>
<kactus2:position x="700" y="150"/>
<kactus2:direction x="-1" y="0"/>
<kactus2:route kactus2:offPage="false">
<kactus2:position x="590" y="150"/>
<kactus2:position x="700" y="150"/>
<kactus2:position x="90" y="130"/>
<kactus2:direction x="1" y="0"/>
<kactus2:route kactus2:offPage="true">
<kactus2:position x="140" y="120"/>
<kactus2:position x="90" y="130"/>
</kactus2:route>
</spirit:vendorExtensions>
</spirit:hierConnection>
<spirit:hierConnection spirit:interfaceRef="clk_udp">
<spirit:interface spirit:componentRef="udp2hibi_0" spirit:busRef="clk_udp"/>
<spirit:hierConnection spirit:interfaceRef="rst_n">
<spirit:interface spirit:componentRef="udp2hibi_0" spirit:busRef="rst_n"/>
<spirit:vendorExtensions>
<kactus2:position x="700" y="100"/>
<kactus2:direction x="-1" y="0"/>
<kactus2:route kactus2:offPage="false">
<kactus2:position x="590" y="100"/>
<kactus2:position x="700" y="100"/>
<kactus2:position x="90" y="130"/>
<kactus2:direction x="1" y="0"/>
<kactus2:route kactus2:offPage="true">
<kactus2:position x="400" y="180"/>
<kactus2:position x="90" y="130"/>
</kactus2:route>
</spirit:vendorExtensions>
</spirit:hierConnection>
188,14 → 188,15
<kactus2:column name="IO" contentType="0" allowedItems="1" minWidth="119" width="119"/>
</kactus2:columnLayout>
<kactus2:routes>
<kactus2:route kactus2:connRef="udp2hibi_0_udp_ip_tx_to_udp_ip_dm9000a_0_app_tx" kactus2:offPage="false">
<kactus2:position x="430" y="100"/>
<kactus2:position x="330" y="100"/>
</kactus2:route>
<kactus2:route kactus2:connRef="udp_ip_dm9000a_0_app_rx_to_udp2hibi_0_udp_ip_rx" kactus2:offPage="false">
<kactus2:position x="330" y="130"/>
<kactus2:position x="430" y="130"/>
</kactus2:route>
<kactus2:route kactus2:connRef="udp2hibi_0_udp_ip_tx_to_udp_ip_dm9000a_0_app_tx" kactus2:offPage="false">
<kactus2:position x="430" y="100"/>
<kactus2:position x="330" y="100"/>
</kactus2:route>
</kactus2:routes>
<kactus2:adHocVisibilities/>
</spirit:vendorExtensions>
</spirit:design>

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