OpenCores
URL https://opencores.org/ocsvn/gecko3/gecko3/trunk

Subversion Repositories gecko3

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /gecko3/trunk
    from Rev 17 to Rev 18
    ↔ Reverse comparison
  •

Rev 17 → Rev 18

/GECKO3COM/gecko3com-ip/core/usb_tmc_ip_chipscope.cdc File deleted
/GECKO3COM/gecko3com-ip/core/fifo_dualclock.vhd
85,10 → 85,10
almost_full : OUT std_logic;
dout : OUT std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
empty : OUT std_logic;
full : OUT std_logic;
PROG_EMPTY_THRESH : IN std_logic;
PROG_EMPTY_THRESH_ASSERT : IN std_logic;
PROG_EMPTY_THRESH_NEGATE : IN std_logic);
full : OUT std_logic);
--PROG_EMPTY_THRESH : IN std_logic;
--PROG_EMPTY_THRESH_ASSERT : IN std_logic;
--PROG_EMPTY_THRESH_NEGATE : IN std_logic);
end component;
attribute box_type of coregenerator_fifo_dualclock : component is "black_box";
110,10 → 110,10
almost_full => o_almost_full,
dout => o_dout,
empty => o_empty,
full => o_full,
PROG_EMPTY_THRESH => '0',
PROG_EMPTY_THRESH_ASSERT => '0',
PROG_EMPTY_THRESH_NEGATE => '0'
full => o_full
--PROG_EMPTY_THRESH => '0',
--PROG_EMPTY_THRESH_ASSERT => '0',
--PROG_EMPTY_THRESH_NEGATE => '0'
);
 
end wrapper;
end wrapper;
/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple_prototype.ise Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/GECKO3COM/gecko3com-ip/core/gpif_com_test_tb.vhd
0,0 → 1,160
-- GECKO3COM IP Core
--
-- Copyright (C) 2009 by
-- ___ ___ _ _
-- ( _ \ ( __)( ) ( )
-- | (_) )| ( | |_| | Bern University of Applied Sciences
-- | _ < | _) | _ | School of Engineering and
-- | (_) )| | | | | | Information Technology
-- (____/ (_) (_) (_)
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- URL to the project description:
-- http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
--------------------------------------------------------------------------------
--
-- Author: Andreas Habegger, Christoph Zimmermann
-- Date of creation: 23. December 2009
-- Description:
-- F
--
-- Tool versions: 11.1
-- Dependencies:
--
--------------------------------------------------------------------------------
 
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
 
library XilinxCoreLib;
 
library work;
use work.GECKO3COM_defines.all;
 
entity gpif_com_test_tb is
end gpif_com_test_tb;
 
architecture simulation of gpif_com_test_tb is
 
-- components
 
component gpif_com_test
port (
i_nReset : in std_logic;
i_IFCLK : in std_logic;
i_SYSCLK : in std_logic;
i_WRU : in std_logic;
i_RDYU : in std_logic;
o_WRX : out std_logic;
o_RDYX : out std_logic;
b_gpif_bus : inout std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
o_LEDrx : out std_logic;
o_LEDtx : out std_logic;
o_LEDrun : out std_logic;
o_dummy : out std_logic);
end component;
 
 
 
-- simulation types
type TsimSend is (finish, sending, waiting);
-- simulation constants
 
--constant TIME_BASE : time := 1 ns;
 
constant CLK_PERIOD : time := 20 ns;
 
constant DATA_BUS_SIZE : integer := SIZE_DBUS_GPIF;
constant WORD_VALUE1 : std_logic_vector(DATA_BUS_SIZE-1 downto 0) := x"FF00";
constant WORD_VALUE2 : std_logic_vector(DATA_BUS_SIZE-1 downto 0) := x"B030";
constant WORD_VALUE3 : std_logic_vector(DATA_BUS_SIZE-1 downto 0) := x"50A0";
-- signals
 
signal sim_clk : std_logic;
signal sim_rst : std_logic;
 
signal s_LEDrun, s_LEDtx, s_LEDrx, s_dummy : std_logic;
signal sim_1 : boolean := false;
signal send_data : TsimSend := finish;
 
 
signal s_WRU : std_logic;
signal s_RDYU : std_logic;
 
signal s_WRX : std_logic;
signal s_RDYX : std_logic;
 
 
signal s_data_bus : std_logic_vector(DATA_BUS_SIZE-1 downto 0);
 
 
begin -- simulation
 
-------------------------------------------------------------------------------
-- Design maps
-------------------------------------------------------------------------------
 
DUT : gpif_com_test
port map (
i_nReset => sim_rst,
i_IFCLK => sim_clk,
i_SYSCLK => sim_clk,
i_WRU => s_WRU,
i_RDYU => s_RDYU,
o_WRX => s_WRX,
o_RDYX => s_RDYX,
b_gpif_bus => s_data_bus,
o_LEDrx => s_LEDrx,
o_LEDtx => s_LEDtx,
o_LEDrun => s_LEDrun,
o_dummy => s_dummy);
 
 
-------------------------------------------------------------------------------
-- CLK process
-------------------------------------------------------------------------------
clk_process: process
begin
sim_clk<='0';
wait for CLK_PERIOD/2;
sim_clk<='1';
wait for CLK_PERIOD/2;
if sim_1 then
wait;
end if;
end process;
rst_process: process
begin
sim_rst<='0';
wait for CLK_PERIOD;
sim_rst<='1';
wait;
end process;
 
end simulation;
/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple.xise
15,47 → 15,50
<version xil_pn:ise_version="11.1" xil_pn:schema_version="2"/>
 
<files>
<file xil_pn:name="USB_TMC_cmp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<file xil_pn:name="GECKO3COM_loopback.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="USB_TMC_IP_loopback.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="GECKO3COM_defines.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="gpif_com.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="coregenerator_fifo_dualclock.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="USB_TMC_IP.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="fifo_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="USB_TMC_IP_Defs.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="gpif_com.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="USB_TMC_IP_tb.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="gpif_com_test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostMapSimulation"/>
<association xil_pn:name="PostTranslateSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="fifo_X2U_2C_1024B.xco" xil_pn:type="FILE_COREGEN">
<file xil_pn:name="gpif_com_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="fifo_U2X_2C_1024B.xco" xil_pn:type="FILE_COREGEN">
<file xil_pn:name="message_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="USB_TMC_IP.ucf" xil_pn:type="FILE_UCF">
<file xil_pn:name="gpif_com_test_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostMapSimulation"/>
<association xil_pn:name="PostTranslateSimulation"/>
</file>
<file xil_pn:name="GECKO3main_v1.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="fifo_X2U_2C_1024B.ise" xil_pn:type="FILE_COREGENISE">
<file xil_pn:name="gecko3com_test_chipscope.cdc" xil_pn:type="FILE_CDC">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="fifo_U2X_2C_1024B.ise" xil_pn:type="FILE_COREGENISE">
<file xil_pn:name="coregenerator_fifo_dualclock.ise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation"/>
</file>
</files>
62,43 → 65,50
 
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false"/>
<property xil_pn:name="Command line syntax" xil_pn:value="emacsclient +$2 $1"/>
<property xil_pn:name="Compiled Library Directory" xil_pn:value="lib"/>
<property xil_pn:name="Constraints Entry" xil_pn:value="Constraints Editor"/>
<property xil_pn:name="Device" xil_pn:value="xc3s4000"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3"/>
<property xil_pn:name="Editor" xil_pn:value="Custom"/>
<property xil_pn:name="Fitter Report Format" xil_pn:value="HTML"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|USB_TMC_IP|top_core"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/USB_TMC_IP"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|gpif_com_test|loopback"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/gpif_com_test"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="Soft"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="true"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|gpif_com_test_tb|simulation"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="usb_tmc_com"/>
<property xil_pn:name="PROP_mapSmartGuideFileName" xil_pn:value=""/>
<property xil_pn:name="PROP_parSmartGuideFileName" xil_pn:value=""/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs"/>
<property xil_pn:name="Package" xil_pn:value="fg676"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="false"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="false"/>
<property xil_pn:name="Report Type" xil_pn:value="Error Report"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Error Report"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="Yes"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="Architecture|gpif_com_test_tb|simulation"/>
<property xil_pn:name="Simulation Resolution" xil_pn:value="1 ns"/>
<property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="2000ns"/>
<property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE VHDL"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)"/>
<property xil_pn:name="Simulator Path" xil_pn:value="/opt/mentorGraphics/modeltech/bin/"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL"/>
<property xil_pn:name="Verbose Property Persistence" xil_pn:value="false"/>
<property xil_pn:name="iMPACT Project File" xil_pn:value=""/>
<property xil_pn:name="iMPACT Project File" xil_pn:value="GECKO3COM.ipf"/>
</properties>
 
<bindings>
<binding xil_pn:location="/USB_TMC_IP" xil_pn:name="USB_TMC_IP.ucf"/>
<binding xil_pn:location="/gpif_com_test" xil_pn:name="GECKO3main_v1.ucf"/>
<binding xil_pn:location="/gpif_com_test" xil_pn:name="gecko3com_test_chipscope.cdc"/>
</bindings>
 
<libraries/>
 
<partitions>
<partition xil_pn:name="/USB_TMC_IP"/>
<partition xil_pn:name="/gpif_com_test"/>
</partitions>
 
</project>
/GECKO3COM/gecko3com-ip/core/gpif_com_test_tb.wcfg
0,0 → 1,105
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="/home/chrigi/bfh-work/GECKO3COM/gecko3com-ip/core/gpif_com_test_tb_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="gecko3com_defines" />
<top_module name="glbl" />
<top_module name="gpif_com_test_tb" />
<top_module name="numeric_std" />
<top_module name="std_logic_1164" />
<top_module name="std_logic_arith" />
<top_module name="std_logic_unsigned" />
<top_module name="usb_tmc_cmp" />
<top_module name="vcomponents" />
<top_module name="vcomponents" />
</top_modules>
</db_ref>
</db_ref_list>
<wvobject fp_name="/gpif_com_test_tb/sim_clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sim_clk</obj_property>
<obj_property name="ObjectShortName">sim_clk</obj_property>
</wvobject>
<wvobject fp_name="/gpif_com_test_tb/sim_rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">sim_rst</obj_property>
<obj_property name="ObjectShortName">sim_rst</obj_property>
</wvobject>
<wvobject fp_name="/gpif_com_test_tb/s_ledrun" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">s_ledrun</obj_property>
<obj_property name="ObjectShortName">s_ledrun</obj_property>
</wvobject>
<wvobject fp_name="/gpif_com_test_tb/s_ledtx" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">s_ledtx</obj_property>
<obj_property name="ObjectShortName">s_ledtx</obj_property>
</wvobject>
<wvobject fp_name="/gpif_com_test_tb/s_ledrx" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">s_ledrx</obj_property>
<obj_property name="ObjectShortName">s_ledrx</obj_property>
</wvobject>
<wvobject fp_name="/gpif_com_test_tb/s_dummy" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">s_dummy</obj_property>
<obj_property name="ObjectShortName">s_dummy</obj_property>
</wvobject>
<wvobject fp_name="/gpif_com_test_tb/sim_1" type="other" db_ref_id="1">
<obj_property name="ElementShortName">sim_1</obj_property>
<obj_property name="ObjectShortName">sim_1</obj_property>
</wvobject>
<wvobject fp_name="/gpif_com_test_tb/send_data" type="other" db_ref_id="1">
<obj_property name="ElementShortName">send_data</obj_property>
<obj_property name="ObjectShortName">send_data</obj_property>
</wvobject>
<wvobject fp_name="/gpif_com_test_tb/s_wru" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">s_wru</obj_property>
<obj_property name="ObjectShortName">s_wru</obj_property>
</wvobject>
<wvobject fp_name="/gpif_com_test_tb/s_rdyu" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">s_rdyu</obj_property>
<obj_property name="ObjectShortName">s_rdyu</obj_property>
</wvobject>
<wvobject fp_name="/gpif_com_test_tb/s_wrx" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">s_wrx</obj_property>
<obj_property name="ObjectShortName">s_wrx</obj_property>
</wvobject>
<wvobject fp_name="/gpif_com_test_tb/s_rdyx" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">s_rdyx</obj_property>
<obj_property name="ObjectShortName">s_rdyx</obj_property>
</wvobject>
<wvobject fp_name="/gpif_com_test_tb/s_data_bus" type="array" db_ref_id="1">
<obj_property name="ElementShortName">s_data_bus[15:0]</obj_property>
<obj_property name="ObjectShortName">s_data_bus[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/gpif_com_test_tb/clk_period" type="other" db_ref_id="1">
<obj_property name="ElementShortName">clk_period</obj_property>
<obj_property name="ObjectShortName">clk_period</obj_property>
</wvobject>
<wvobject fp_name="/gpif_com_test_tb/data_bus_size" type="other" db_ref_id="1">
<obj_property name="ElementShortName">data_bus_size</obj_property>
<obj_property name="ObjectShortName">data_bus_size</obj_property>
</wvobject>
<wvobject fp_name="/gpif_com_test_tb/word_value1" type="array" db_ref_id="1">
<obj_property name="ElementShortName">word_value1[15:0]</obj_property>
<obj_property name="ObjectShortName">word_value1[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/gpif_com_test_tb/word_value2" type="array" db_ref_id="1">
<obj_property name="ElementShortName">word_value2[15:0]</obj_property>
<obj_property name="ObjectShortName">word_value2[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/gpif_com_test_tb/word_value3" type="array" db_ref_id="1">
<obj_property name="ElementShortName">word_value3[15:0]</obj_property>
<obj_property name="ObjectShortName">word_value3[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/gpif_com_test_tb/DUT/s_tx_data" type="array" db_ref_id="1">
<obj_property name="ElementShortName">s_tx_data[15:0]</obj_property>
<obj_property name="ObjectShortName">s_tx_data[15:0]</obj_property>
</wvobject>
<wvobject fp_name="/gpif_com_test_tb/DUT/s_rom_adress" type="array" db_ref_id="1">
<obj_property name="ElementShortName">s_rom_adress[4:0]</obj_property>
<obj_property name="ObjectShortName">s_rom_adress[4:0]</obj_property>
</wvobject>
<wvobject fp_name="/gpif_com_test_tb/DUT/s_wr_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">s_wr_en</obj_property>
<obj_property name="ObjectShortName">s_wr_en</obj_property>
</wvobject>
</wave_config>
/GECKO3COM/gecko3com-ip/core/gecko3com_test_chipscope.cdc
0,0 → 1,86
#ChipScope Core Inserter Project File Version 3.0
#Wed Jan 13 10:18:17 CET 2010
Project.device.designInputFile=/home/chrigi/bfh-work/GECKO3COM/gecko3com-ip/core/gpif_com_test_cs.ngc
Project.device.designOutputFile=/home/chrigi/bfh-work/GECKO3COM/gecko3com-ip/core/gpif_com_test_cs.ngc
Project.device.deviceFamily=6
Project.device.enableRPMs=true
Project.device.outputDirectory=/home/chrigi/bfh-work/GECKO3COM/gecko3com-ip/core/_ngo
Project.device.useSRL16=true
Project.filter.dimension=1
Project.filter<0>=
Project.icon.boundaryScanChain=1
Project.icon.disableBUFGInsertion=false
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=1
Project.unit<0>.clockChannel=i_SYSCLK_BUFGP
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataChannel<0>=o_WRX_OBUF
Project.unit<0>.dataChannel<10>=GPIF_INTERFACE s_dbus_out<8>
Project.unit<0>.dataChannel<11>=GPIF_INTERFACE s_dbus_out<9>
Project.unit<0>.dataChannel<12>=GPIF_INTERFACE s_dbus_out<10>
Project.unit<0>.dataChannel<13>=GPIF_INTERFACE s_dbus_out<11>
Project.unit<0>.dataChannel<14>=GPIF_INTERFACE s_dbus_out<12>
Project.unit<0>.dataChannel<15>=GPIF_INTERFACE s_dbus_out<13>
Project.unit<0>.dataChannel<16>=GPIF_INTERFACE s_dbus_out<14>
Project.unit<0>.dataChannel<17>=GPIF_INTERFACE s_dbus_out<15>
Project.unit<0>.dataChannel<18>=GPIF_INTERFACE s_dbus_trans_dir
Project.unit<0>.dataChannel<19>=GPIF_INTERFACE o_RX
Project.unit<0>.dataChannel<1>=i_RDYU_IBUF
Project.unit<0>.dataChannel<20>=GPIF_INTERFACE o_TX
Project.unit<0>.dataChannel<21>=GPIF_INTERFACE s_U2X_AM_FULL
Project.unit<0>.dataChannel<22>=GPIF_INTERFACE s_U2X_WR_EN
Project.unit<0>.dataChannel<23>=GPIF_INTERFACE s_U2X_FULL
Project.unit<0>.dataChannel<24>=GPIF_INTERFACE o_RDYX
Project.unit<0>.dataChannel<25>=s_RX_DATA<0>
Project.unit<0>.dataChannel<26>=s_RX_DATA<1>
Project.unit<0>.dataChannel<27>=s_RX_DATA<2>
Project.unit<0>.dataChannel<28>=s_RX_DATA<3>
Project.unit<0>.dataChannel<29>=s_RX_DATA<4>
Project.unit<0>.dataChannel<2>=GPIF_INTERFACE s_dbus_out<0>
Project.unit<0>.dataChannel<30>=s_RX_DATA<5>
Project.unit<0>.dataChannel<31>=s_RX_DATA<6>
Project.unit<0>.dataChannel<32>=s_RX_DATA<7>
Project.unit<0>.dataChannel<33>=s_RX_DATA<8>
Project.unit<0>.dataChannel<34>=s_RX_DATA<9>
Project.unit<0>.dataChannel<35>=s_RX_DATA<10>
Project.unit<0>.dataChannel<36>=s_RX_DATA<11>
Project.unit<0>.dataChannel<37>=s_RX_DATA<12>
Project.unit<0>.dataChannel<38>=s_RX_DATA<13>
Project.unit<0>.dataChannel<39>=s_RX_DATA<14>
Project.unit<0>.dataChannel<3>=GPIF_INTERFACE s_dbus_out<1>
Project.unit<0>.dataChannel<40>=s_RX_DATA<15>
Project.unit<0>.dataChannel<41>=s_EMPTY
Project.unit<0>.dataChannel<42>=i_WRU_IBUF
Project.unit<0>.dataChannel<43>=o_WRX_OBUF
Project.unit<0>.dataChannel<44>=s_RD_EN
Project.unit<0>.dataChannel<4>=GPIF_INTERFACE s_dbus_out<2>
Project.unit<0>.dataChannel<5>=GPIF_INTERFACE s_dbus_out<3>
Project.unit<0>.dataChannel<6>=GPIF_INTERFACE s_dbus_out<4>
Project.unit<0>.dataChannel<7>=GPIF_INTERFACE s_dbus_out<5>
Project.unit<0>.dataChannel<8>=GPIF_INTERFACE s_dbus_out<6>
Project.unit<0>.dataChannel<9>=GPIF_INTERFACE s_dbus_out<7>
Project.unit<0>.dataDepth=512
Project.unit<0>.dataEqualsTrigger=false
Project.unit<0>.dataPortWidth=45
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=true
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerChannel<0><0>=i_WRU_IBUF
Project.unit<0>.triggerChannel<0><1>=o_WRX_OBUF
Project.unit<0>.triggerChannel<0><2>=o_RDYX_OBUF
Project.unit<0>.triggerChannel<0><3>=i_RDYU_IBUF
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=1
Project.unit<0>.triggerMatchCountWidth<0><0>=0
Project.unit<0>.triggerMatchType<0><0>=1
Project.unit<0>.triggerPortCount=1
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortWidth<0>=4
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=1
Project.unit<0>.type=ilapro
/GECKO3COM/gecko3com-ip/core/GECKO3main_v1.ucf
55,22 → 55,22
net "o_RDYX" loc = "AD14";
 
# connection of data bus signals
net "b_dbus<0>" loc = "AA12";
net "b_dbus<1>" loc = "AB12";
net "b_dbus<2>" loc = "AB13";
net "b_dbus<3>" loc = "AC13";
net "b_dbus<4>" loc = "AA14";
net "b_dbus<5>" loc = "Y14";
net "b_dbus<6>" loc = "W14";
net "b_dbus<7>" loc = "Y15";
net "b_dbus<8>" loc = "Y9";
net "b_dbus<9>" loc = "Y10";
net "b_dbus<10>" loc = "Y11";
net "b_dbus<11>" loc = "W11";
net "b_dbus<12>" loc = "Y12";
net "b_dbus<13>" loc = "W12";
net "b_dbus<14>" loc = "Y13";
net "b_dbus<15>" loc = "W13";
net "b_gpif_bus<0>" loc = "AA12";
net "b_gpif_bus<1>" loc = "AB12";
net "b_gpif_bus<2>" loc = "AB13";
net "b_gpif_bus<3>" loc = "AC13";
net "b_gpif_bus<4>" loc = "AA14";
net "b_gpif_bus<5>" loc = "Y14";
net "b_gpif_bus<6>" loc = "W14";
net "b_gpif_bus<7>" loc = "Y15";
net "b_gpif_bus<8>" loc = "Y9";
net "b_gpif_bus<9>" loc = "Y10";
net "b_gpif_bus<10>" loc = "Y11";
net "b_gpif_bus<11>" loc = "W11";
net "b_gpif_bus<12>" loc = "Y12";
net "b_gpif_bus<13>" loc = "W12";
net "b_gpif_bus<14>" loc = "Y13";
net "b_gpif_bus<15>" loc = "W13";
 
 
# switches
85,5 → 85,6
net "o_LEDtx" loc = "g9";
net "o_LEDrun"loc = "f10";
 
# dummy output, only needed for the gpif_com_test
net "o_dummy" loc = "AF19";
 
 
/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple.ise Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/GECKO3COM/gecko3com-ip/core/gpif_com_fsm.vhd
22,24 → 22,24
--
-- URL to the project description:
-- http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Author: Andreas Habegger, Christoph Zimmermann
-- Date of creation: 8. April 2009
-- Description:
-- FSM that controls the interface between the EZ-USB (and it's internal GPIF,
-- General Purpose Interface) and our FPGA. The interface is synchronous, where
-- the GPIF provides the clock. This FSM is synchronous to the GPIF clock, also
-- this side of the FIFO's.
-- FSM that controls the interface between the EZ-USB (and it's internal
-- GPIF, General Purpose Interface) and our FPGA. The interface is
-- synchronous, where the GPIF provides the clock. This FSM is synchronous
-- to the GPIF clock, also this side of the FIFO's.
--
-- You can find more detailed information how the interface works in the ../Doc
-- folder.
-- You can find more detailed information how the interface works in the
-- ../Doc folder.
--
-- Target Devices: Xilinx Spartan3 FPGA's (usage of BlockRam in the Datapath)
-- Tool versions: 11.1
-- Target Devices: general
-- Tool versions: Xilinx ISE 11.1, XST
-- Dependencies:
--
----------------------------------------------------------------------------------
-------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
50,24 → 50,31
 
entity gpif_com_fsm is
port (
i_nReset,
i_IFCLK, -- GPIF CLK (GPIF is Master and provides the clock)
i_WRU, -- write from GPIF
i_RDYU : in std_logic; -- GPIF is ready
i_U2X_FULL,
i_U2X_AM_FULL, -- signals for IN FIFO
i_X2U_AM_EMPTY,
i_X2U_EMPTY : in std_logic; -- signals for OUT FIFO
o_bus_trans_dir : out std_logic;
o_U2X_WR_EN, -- signals for IN FIFO
o_X2U_RD_EN, -- signals for OUT FIFO
o_FIFOrst,
o_WRX, -- To write to GPIF
o_RDYX : out std_logic; -- Core is ready
o_ABORT : out std_logic; -- abort condition detected. we have to flush the data
o_RX,
o_TX : out std_logic --
);
i_nReset : in std_logic;
i_IFCLK : in std_logic; -- GPIF CLK (GPIF is Master and provides the clock)
i_WRU : in std_logic; -- write from GPIF
i_RDYU : in std_logic; -- GPIF is ready
i_U2X_FULL : in std_logic;
i_U2X_AM_FULL : in std_logic; -- signals for IN FIFO
i_X2U_AM_EMPTY : in std_logic;
i_X2U_EMPTY : in std_logic; -- signals for OUT FIFO
o_bus_trans_dir : out std_logic;
o_U2X_WR_EN : out std_logic; -- signals for IN FIFO
o_X2U_RD_EN : out std_logic; -- signals for OUT FIFO
o_FIFOrst : out std_logic;
o_WRX : out std_logic; -- To write to GPIF
o_RDYX : out std_logic; -- Core is ready
o_ABORT : out std_logic; -- abort condition detected. we have to flush the data
o_RX : out std_logic;
o_TX : out std_logic --
);
 
-- XST specific synthesize attributes
attribute safe_implementation: string;
attribute safe_recovery_state: string;
 
attribute safe_implementation of gpif_com_fsm : entity is "yes";
 
end gpif_com_fsm;
 
 
74,260 → 81,286
 
architecture fsm of gpif_com_fsm is
 
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- FSM
-----------------------------------------------------------------------------
 
type t_busAccess is (readFromGPIF, writeToGPIF);
type t_busAccess is (readFromGPIF, writeToGPIF);
signal s_bus_trans_dir : t_busAccess;
 
type t_fsmState is (rst, idle, -- controll states
inRQ, inACK, inTrans, throt, endInTrans, -- in com states
outRQ, outTrans, endOutTrans); -- out com states
type t_fsmState is (rst, idle, -- controll states
inRQ, inACK, inTrans, inThrot,
inThrotEnd, endInTrans, -- in com states
outRQ, outTrans, outWait, endOutTrans); -- out com states
 
 
signal pr_state, nx_state : t_fsmState;
-- XST specific synthesize attributes
attribute safe_recovery_state of pr_state : signal is "idle";
attribute safe_recovery_state of nx_state : signal is "idle";
 
 
-- interconection signals
signal s_FIFOrst, s_RDYX, s_WRX, s_ABORT : std_logic;
 
signal s_FIFOrst,
s_RDYX,
s_WRX : std_logic;
 
-- USB to Xilinx (U2X)
-- USB to Xilinx (U2X)
signal s_U2X_WR_EN : std_logic;
 
-- Xilinx to USB (X2U)
signal s_X2U_RD_EN : std_logic;
-- Xilinx to USB (X2U)
signal s_X2U_RD_EN : std_logic;
begin
 
o_FIFOrst <= s_FIFOrst;
o_X2U_RD_EN <= s_X2U_RD_EN;
o_WRX <= s_WRX;
o_RDYX <= s_RDYX;
o_U2X_WR_EN <= s_U2X_WR_EN;
o_FIFOrst <= s_FIFOrst;
o_X2U_RD_EN <= s_X2U_RD_EN;
o_WRX <= s_WRX;
o_RDYX <= s_RDYX;
o_U2X_WR_EN <= s_U2X_WR_EN;
o_bus_trans_dir <= '1' when s_bus_trans_dir = writeToGPIF else '0';
o_ABORT <= s_ABORT;
 
 
-----------------------------------------------------------------------------
-- FSM GPIF
-----------------------------------------------------------------------------
 
-- state reg
-- state reg
action : process(i_IFCLK, i_nReset)
variable v_setup : integer range 0 to 15;
begin
variable v_setup : integer range 0 to 15;
begin
 
if i_nReset = '0' then
pr_state <= rst;
v_setup := 0;
elsif rising_edge(i_IFCLK) then
if v_setup < SETUP_TIME then
v_setup := v_setup + 1;
elsif nx_state = rst then
v_setup := 0;
pr_state <= nx_state;
else
pr_state <= nx_state;
end if;
end if;
end process action;
if i_nReset = '0' then
pr_state <= rst;
elsif rising_edge(i_IFCLK) then
pr_state <= nx_state;
end if;
end process action;
 
 
-- comb logic
transaction : process(pr_state, i_WRU, i_RDYU, i_U2X_AM_FULL, i_X2U_EMPTY)
begin -- process transaction
-- default signal values to avoid latches:
s_FIFOrst <= '0';
s_bus_trans_dir <= readFromGPIF;
s_U2X_WR_EN <= '0';
s_X2U_RD_EN <= '0';
nx_state <= idle;
s_WRX <= '0';
s_RDYX <= '0';
o_LEDrun <= '1';
o_LEDrx <= '0';
o_LEDtx <= '0';
case pr_state is
-- controll
-- comb logic
transaction : process(pr_state, i_WRU, i_RDYU, i_U2X_AM_FULL, i_X2U_EMPTY)
begin -- process transaction
 
when rst =>
-- output signal values:
s_FIFOrst <= '1';
s_WRX <= '0';
s_RDYX <= '0';
s_U2X_WR_EN <= '0';
s_X2U_RD_EN <= '0';
s_bus_trans_dir <= readFromGPIF;
-- state decisions
nx_state <= idle;
o_LEDrun <= '0';
-- default signal values to avoid latches:
s_FIFOrst <= '0';
s_bus_trans_dir <= readFromGPIF;
s_U2X_WR_EN <= '0';
s_X2U_RD_EN <= '0';
nx_state <= idle;
s_WRX <= '0';
s_RDYX <= '0';
s_ABORT <= '0';
o_RX <= '0';
o_TX <= '0';
 
case pr_state is
-- controll
 
when rst =>
-- output signal values:
s_FIFOrst <= '1';
s_WRX <= '0';
s_RDYX <= '0';
s_U2X_WR_EN <= '0';
s_X2U_RD_EN <= '0';
s_ABORT <= '1';
o_RX <= '0';
o_TX <= '0';
 
s_bus_trans_dir <= readFromGPIF;
 
-- state decisions
if i_WRU = '1' and i_RDYU = '1' then
nx_state <= rst;
else
nx_state <= idle;
end if;
when idle =>
-- output signal values:
s_FIFOrst <= '0';
s_WRX <= '0';
s_RDYX <= '0';
s_U2X_WR_EN <= '0';
s_X2U_RD_EN <= '0';
s_bus_trans_dir <= readFromGPIF;
-- state decisions
if i_WRU = '1' and i_RDYU = '1' then
nx_state <= rst;
elsif i_WRU = '1' and i_RDYU = '0' then
nx_state <= inRQ;
elsif i_WRU = '0' and i_X2U_EMPTY = '0' then
nx_state <= outRQ;
else
nx_state <= idle;
end if;
when idle =>
-- output signal values:
s_FIFOrst <= '0';
s_WRX <= '0';
s_RDYX <= '0';
s_U2X_WR_EN <= '0';
s_X2U_RD_EN <= '0';
s_bus_trans_dir <= readFromGPIF;
 
-- state decisions
if i_WRU = '1' and i_RDYU = '1' then
nx_state <= rst;
elsif i_WRU = '1' and i_RDYU = '0' then
nx_state <= inRQ;
elsif i_WRU = '0' and i_X2U_EMPTY = '0' then
nx_state <= outRQ;
else
nx_state <= idle;
end if;
 
-- in trans
when inRQ =>
-- output signal values:
s_WRX <= '0';
s_RDYX <= '0';
-- state decisions
if i_WRU = '1' and i_RDYU = '1' then
nx_state <= rst;
elsif i_U2X_AM_FULL = '0' then
nx_state <= inACK;
s_RDYX <= '1';
else
nx_state <= idle;
end if;
when inRQ =>
-- output signal values:
s_WRX <= '0';
s_RDYX <= '0';
-- state decisions
if i_WRU = '1' and i_RDYU = '1' then
nx_state <= rst;
elsif i_U2X_FULL = '0' then
nx_state <= inACK;
else
nx_state <= idle;
end if;
 
when inACK =>
-- output signal values:
s_WRX <= '0';
s_RDYX <= '0';
s_U2X_WR_EN <= '0';
-- state decisions
if i_WRU = '1' and i_RDYU = '1' then
nx_state <= rst;
elsif i_WRU = '1' then
nx_state <= inTrans;
s_U2X_WR_EN <= '1';
s_RDYX <= '1';
else
nx_state <= endInTrans;
end if;
when inACK =>
-- output signal values:
s_WRX <= '0';
s_RDYX <= '1';
s_U2X_WR_EN <= '1';
o_RX <= '1';
 
when inTrans =>
-- output signal values:
s_WRX <= '0';
s_RDYX <= '0';
o_LEDrx <= '1';
-- state decisions
if i_WRU = '1' and i_RDYU = '1' then
nx_state <= rst;
elsif i_WRU = '1' then
nx_state <= inTrans;
--nx_state <= inDummy;
else
nx_state <= endInTrans;
end if;
when inTrans =>
-- output signal values:
s_WRX <= '0';
s_RDYX <= '1';
s_U2X_WR_EN <= '1';
o_RX <= '1';
 
-- state decisions
if i_WRU = '1' and i_RDYU = '1' then
nx_state <= rst;
elsif i_WRU = '0' then
nx_state <= endInTrans;
s_RDYX <= '1';
s_U2X_WR_EN <= '1';
elsif i_U2X_AM_FULL = '1' then
nx_state <= throt;
s_U2X_WR_EN <= '1';
else
nx_state <= inTrans;
s_RDYX <= '1';
s_U2X_WR_EN <= '1';
end if;
-- state decisions
if i_WRU = '1' and i_RDYU = '1' then
nx_state <= rst;
elsif i_WRU = '0' then
nx_state <= endInTrans;
elsif i_U2X_FULL = '1' then
nx_state <= inThrot;
else
nx_state <= inTrans;
end if;
 
when throt =>
-- output signal values:
s_WRX <= '0';
s_RDYX <= '0';
s_U2X_WR_EN <= '0';
-- state decisions
if i_WRU = '1' and i_RDYU = '1' then
nx_state <= rst;
elsif i_U2X_AM_FULL = '0' then
nx_state <= inACK;
s_RDYX <= '1';
s_U2X_WR_EN <= '1';
elsif i_WRU = '0' then
nx_state <= endInTrans;
else
nx_state <= throt;
end if;
when endInTrans =>
-- output signal values:
s_WRX <= '0';
s_RDYX <= '0';
s_U2X_WR_EN <= '1';
-- state decisions
nx_state <= idle;
when inThrot =>
-- output signal values:
s_WRX <= '0';
s_RDYX <= '0';
s_U2X_WR_EN <= '0';
o_RX <= '1';
 
-- state decisions
if i_WRU = '1' and i_RDYU = '1' then
nx_state <= rst;
elsif i_U2X_FULL = '0' then
--nx_state <= inThrotEnd;
nx_state <= inACK;
elsif i_WRU = '0' then
nx_state <= endInTrans;
else
nx_state <= inThrot;
end if;
 
--when inThrotEnd =>
-- -- this is a one clock delay to help the fx2 to see the RDYX signal.
-- -- output signal values:
-- s_WRX <= '0';
-- s_RDYX <= '1';
-- s_U2X_WR_EN <= '0';
-- o_RX <= '1';
 
-- -- state decisions
-- nx_state <= inACK;
when endInTrans =>
-- output signal values:
s_WRX <= '0';
s_RDYX <= '0';
s_U2X_WR_EN <= '1';
 
-- state decisions
nx_state <= idle;
 
 
-- out trans
when outRQ =>
-- output signal values:
s_WRX <= '1';
s_RDYX <= '0';
-- state decisions
if i_WRU = '1' and i_RDYU = '1' then
nx_state <= rst;
s_WRX <= '0';
elsif i_WRU = '1' and i_RDYU = '0' then
nx_state <= inRQ;
elsif i_WRU = '0' and i_RDYU = '0' then -- vervollständigt, wenn ez-usb noch beschäfigt mit altem transfer
s_X2U_RD_EN <= '1';
nx_state <= outTrans;
when outRQ =>
-- output signal values:
s_WRX <= '1';
s_RDYX <= '0';
 
-- state decisions
if i_WRU = '1' and i_RDYU = '1' then
nx_state <= rst;
elsif i_WRU = '1' and i_RDYU = '0' then
nx_state <= inRQ;
elsif i_WRU = '0' and i_RDYU = '0' then -- vervollständigt, wenn ez-usb noch beschäfigt mit altem transfer
--s_X2U_RD_EN <= '1';
nx_state <= outTrans;
-- s_bus_trans_dir <= writeToGPIF;
else
nx_state <= outRQ;
end if;
else
nx_state <= outRQ;
end if;
 
 
when outTrans =>
-- output signal values:
s_WRX <= '1';
s_RDYX <= '0';
s_X2U_RD_EN <= '1';
s_bus_trans_dir <= writeToGPIF;
o_LEDtx <= '1';
-- state decisions
if i_WRU = '1' and i_RDYU = '1' then
nx_state <= rst;
s_WRX <= '0';
s_X2U_RD_EN <= '0';
s_bus_trans_dir <= readFromGPIF;
elsif i_X2U_EMPTY = '1' then
nx_state <= endOutTrans;
elsif i_WRU = '0' and i_RDYU = '1' then
nx_state <= outTrans;
else
s_X2U_RD_EN <= '0'; -- to realise a wait case
nx_state <= outTrans;
end if;
when endOutTrans =>
-- output signal values:
s_RDYX <= '0';
s_WRX <= '1'; -- nötig um letzte 16bit an ez-usb zu schreiben
s_X2U_RD_EN <= '1'; -- nötig da empyte flag schon beim ersten fifo zugriff auftaucht, zweite 16bit müssen noch gelesen werden
s_bus_trans_dir <= writeToGPIF;
-- state decisions
nx_state <= idle;
when outTrans =>
-- output signal values:
s_WRX <= '1';
s_RDYX <= '0';
s_X2U_RD_EN <= '1';
s_bus_trans_dir <= writeToGPIF;
o_TX <= '1';
-- state decisions
if i_WRU = '1' and i_RDYU = '1' then
nx_state <= rst;
elsif i_X2U_EMPTY = '1' then
nx_state <= endOutTrans;
elsif i_WRU = '0' and i_RDYU = '1' then
nx_state <= outTrans;
else
--s_X2U_RD_EN <= '0'; -- to realise a wait case
nx_state <= outWait;
end if;
 
when outWait =>
-- output signal values:
s_WRX <= '1';
s_RDYX <= '0';
s_X2U_RD_EN <= '0';
o_TX <= '1';
s_bus_trans_dir <= writeToGPIF;
 
-- state decisions
if i_WRU = '1' and i_RDYU = '1' then
nx_state <= rst;
elsif i_WRU = '0' and i_RDYU = '1' then
nx_state <= outTrans;
else
nx_state <= outWait;
end if;
when endOutTrans =>
-- output signal values:
s_RDYX <= '0';
s_WRX <= '1'; -- nötig um letzte 16bit an ez-usb zu schreiben
s_X2U_RD_EN <= '1'; -- nötig da empyte flag schon beim ersten fifo zugriff auftaucht, zweite 16bit müssen noch gelesen werden
s_bus_trans_dir <= writeToGPIF;
-- state decisions
nx_state <= idle;
-- error case
when others =>
nx_state <= idle;
end case;
end process transaction;
when others =>
nx_state <= idle;
end case;
end com_core;
end process transaction;
end fsm;
/GECKO3COM/gecko3com-ip/core/USB_TMC_cmp.vhd
30,7 → 30,7
library XilinxCoreLib;
 
library work;
use work.USB_TMC_IP_Defs.all;
use work.GECKO3COM_defines.all;
 
 
package USB_TMC_cmp is
/GECKO3COM/gecko3com-ip/core/chipscope-analyzer.cpj
1,5 → 1,5
#ChipScope Pro Analyzer Project File, Version 3.0
#Tue Dec 15 22:42:10 CET 2009
#Wed Jan 13 21:31:08 CET 2010
deviceChain.deviceName0=XC3S1500
deviceChain.iRLength0=6
deviceChain.name0=MyDevice0
6,10 → 6,10
deviceIds=01434093
import.certifyIdx=-1
import.dir=/home/chrigi/bfh-work/GECKO3COM/gecko3com-ip/core/
import.filename=usb_tmc_ip_chipscope.cdc
import.filename=gecko3com_test_chipscope.cdc
import.unitDeviceIdx=0
mdiAreaHeight=0.7781007751937985
mdiAreaHeightLast=0.42054263565891475
mdiAreaHeight=0.6934826883910387
mdiAreaHeightLast=0.7281059063136456
mdiCount=2
mdiDevice0=0
mdiDevice1=0
17,24 → 17,24
mdiType1=0
mdiUnit0=0
mdiUnit1=0
navigatorHeight=0.13275193798449614
navigatorHeightLast=0.17151162790697674
navigatorWidth=0.1368483412322275
navigatorWidthLast=0.12085308056872038
navigatorHeight=0.18635437881873726
navigatorHeightLast=0.18635437881873726
navigatorWidth=0.22322775263951736
navigatorWidthLast=0.14630467571644043
unit.-1.-1.username=
unit.0.0.0.HEIGHT0=0.40875
unit.0.0.0.HEIGHT0=0.460177
unit.0.0.0.TriggerRow0=1
unit.0.0.0.TriggerRow1=1
unit.0.0.0.TriggerRow2=1
unit.0.0.0.WIDTH0=0.46276966
unit.0.0.0.WIDTH0=1.0574257
unit.0.0.0.X0=0.0
unit.0.0.0.Y0=0.0
unit.0.0.1.HEIGHT1=0.69125
unit.0.0.1.WIDTH1=0.86290884
unit.0.0.1.X1=0.047320805
unit.0.0.1.Y1=0.25125
unit.0.0.MFBitsA0=X1
unit.0.0.MFBitsB0=00
unit.0.0.0.Y0=0.0044247787
unit.0.0.1.HEIGHT1=0.6902655
unit.0.0.1.WIDTH1=1.0574257
unit.0.0.1.X1=0.0
unit.0.0.1.Y1=0.3038348
unit.0.0.MFBitsA0=1XXX
unit.0.0.MFBitsB0=0000
unit.0.0.MFCompareA0=0
unit.0.0.MFCompareB0=999
unit.0.0.MFCount=1
56,14 → 56,12
unit.0.0.TCOutputHigh0=1
unit.0.0.TCOutputMode0=0
unit.0.0.browser_tree_state<Data\ Port>=1
unit.0.0.browser_tree_state<Trigger\ Ports>=1
unit.0.0.browser_tree_state<TriggerPort0>=1
unit.0.0.coretype=ILA
unit.0.0.eventCount0=1
unit.0.0.port.-1.b.0.alias=/s_dbus_out
unit.0.0.port.-1.b.0.channellist=0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
unit.0.0.port.-1.b.0.alias=/GPIF_INTERFACE/s_dbus_out
unit.0.0.port.-1.b.0.channellist=2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
unit.0.0.port.-1.b.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.b.0.name=/s_dbus_out
unit.0.0.port.-1.b.0.name=/GPIF_INTERFACE/s_dbus_out
unit.0.0.port.-1.b.0.orderindex=-1
unit.0.0.port.-1.b.0.radix=Hex
unit.0.0.port.-1.b.0.signedOffset=0.0
74,10 → 72,10
unit.0.0.port.-1.b.0.unsignedPrecision=0
unit.0.0.port.-1.b.0.unsignedScaleFactor=1.0
unit.0.0.port.-1.b.0.visible=1
unit.0.0.port.-1.b.1.alias=/s_opb_in
unit.0.0.port.-1.b.1.channellist=26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
unit.0.0.port.-1.b.1.alias=/s_RX_DATA
unit.0.0.port.-1.b.1.channellist=25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
unit.0.0.port.-1.b.1.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.b.1.name=/s_opb_in
unit.0.0.port.-1.b.1.name=/s_RX_DATA
unit.0.0.port.-1.b.1.orderindex=-1
unit.0.0.port.-1.b.1.radix=Hex
unit.0.0.port.-1.b.1.signedOffset=0.0
89,219 → 87,234
unit.0.0.port.-1.b.1.unsignedScaleFactor=1.0
unit.0.0.port.-1.b.1.visible=1
unit.0.0.port.-1.buscount=2
unit.0.0.port.-1.channelcount=42
unit.0.0.port.-1.channelcount=45
unit.0.0.port.-1.s.0.alias=
unit.0.0.port.-1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.0.name=/s_dbus_out<0>
unit.0.0.port.-1.s.0.name=/o_WRX_OBUF
unit.0.0.port.-1.s.0.orderindex=-1
unit.0.0.port.-1.s.0.visible=0
unit.0.0.port.-1.s.0.visible=1
unit.0.0.port.-1.s.1.alias=
unit.0.0.port.-1.s.1.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.1.name=/s_dbus_out<1>
unit.0.0.port.-1.s.1.name=/i_RDYU_IBUF
unit.0.0.port.-1.s.1.orderindex=-1
unit.0.0.port.-1.s.1.visible=0
unit.0.0.port.-1.s.1.visible=1
unit.0.0.port.-1.s.10.alias=
unit.0.0.port.-1.s.10.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.10.name=/s_dbus_out<10>
unit.0.0.port.-1.s.10.name=/GPIF_INTERFACE/s_dbus_out<8>
unit.0.0.port.-1.s.10.orderindex=-1
unit.0.0.port.-1.s.10.visible=0
unit.0.0.port.-1.s.11.alias=
unit.0.0.port.-1.s.11.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.11.name=/s_dbus_out<11>
unit.0.0.port.-1.s.11.name=/GPIF_INTERFACE/s_dbus_out<9>
unit.0.0.port.-1.s.11.orderindex=-1
unit.0.0.port.-1.s.11.visible=0
unit.0.0.port.-1.s.12.alias=
unit.0.0.port.-1.s.12.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.12.name=/s_dbus_out<12>
unit.0.0.port.-1.s.12.name=/GPIF_INTERFACE/s_dbus_out<10>
unit.0.0.port.-1.s.12.orderindex=-1
unit.0.0.port.-1.s.12.visible=0
unit.0.0.port.-1.s.13.alias=
unit.0.0.port.-1.s.13.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.13.name=/s_dbus_out<13>
unit.0.0.port.-1.s.13.name=/GPIF_INTERFACE/s_dbus_out<11>
unit.0.0.port.-1.s.13.orderindex=-1
unit.0.0.port.-1.s.13.visible=0
unit.0.0.port.-1.s.14.alias=
unit.0.0.port.-1.s.14.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.14.name=/s_dbus_out<14>
unit.0.0.port.-1.s.14.name=/GPIF_INTERFACE/s_dbus_out<12>
unit.0.0.port.-1.s.14.orderindex=-1
unit.0.0.port.-1.s.14.visible=0
unit.0.0.port.-1.s.15.alias=
unit.0.0.port.-1.s.15.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.15.name=/s_dbus_out<15>
unit.0.0.port.-1.s.15.name=/GPIF_INTERFACE/s_dbus_out<13>
unit.0.0.port.-1.s.15.orderindex=-1
unit.0.0.port.-1.s.15.visible=0
unit.0.0.port.-1.s.16.alias=
unit.0.0.port.-1.s.16.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.16.name=/o_RDYX_OBUF
unit.0.0.port.-1.s.16.name=/GPIF_INTERFACE/s_dbus_out<14>
unit.0.0.port.-1.s.16.orderindex=-1
unit.0.0.port.-1.s.16.visible=1
unit.0.0.port.-1.s.16.visible=0
unit.0.0.port.-1.s.17.alias=
unit.0.0.port.-1.s.17.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.17.name=/o_WRX_OBUF
unit.0.0.port.-1.s.17.name=/GPIF_INTERFACE/s_dbus_out<15>
unit.0.0.port.-1.s.17.orderindex=-1
unit.0.0.port.-1.s.17.visible=1
unit.0.0.port.-1.s.17.visible=0
unit.0.0.port.-1.s.18.alias=
unit.0.0.port.-1.s.18.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.18.name=/i_RDYU_IBUF
unit.0.0.port.-1.s.18.name=/GPIF_INTERFACE/s_dbus_trans_dir
unit.0.0.port.-1.s.18.orderindex=-1
unit.0.0.port.-1.s.18.visible=1
unit.0.0.port.-1.s.19.alias=
unit.0.0.port.-1.s.19.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.19.name=/i_WRU_IBUF
unit.0.0.port.-1.s.19.name=/GPIF_INTERFACE/o_RX
unit.0.0.port.-1.s.19.orderindex=-1
unit.0.0.port.-1.s.19.visible=1
unit.0.0.port.-1.s.2.alias=
unit.0.0.port.-1.s.2.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.2.name=/s_dbus_out<2>
unit.0.0.port.-1.s.2.name=/GPIF_INTERFACE/s_dbus_out<0>
unit.0.0.port.-1.s.2.orderindex=-1
unit.0.0.port.-1.s.2.visible=0
unit.0.0.port.-1.s.20.alias=
unit.0.0.port.-1.s.20.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.20.name=/s_dbus_trans_dir_inv
unit.0.0.port.-1.s.20.name=/GPIF_INTERFACE/o_TX
unit.0.0.port.-1.s.20.orderindex=-1
unit.0.0.port.-1.s.20.visible=1
unit.0.0.port.-1.s.21.alias=
unit.0.0.port.-1.s.21.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.21.name=/s_U2X_WR_EN
unit.0.0.port.-1.s.21.name=/GPIF_INTERFACE/s_U2X_AM_FULL
unit.0.0.port.-1.s.21.orderindex=-1
unit.0.0.port.-1.s.21.visible=1
unit.0.0.port.-1.s.22.alias=
unit.0.0.port.-1.s.22.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.22.name=/s_X2U_RD_EN
unit.0.0.port.-1.s.22.name=/GPIF_INTERFACE/s_U2X_WR_EN
unit.0.0.port.-1.s.22.orderindex=-1
unit.0.0.port.-1.s.22.visible=1
unit.0.0.port.-1.s.23.alias=
unit.0.0.port.-1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.23.name=/s_X2U_EMPTY
unit.0.0.port.-1.s.23.name=/GPIF_INTERFACE/s_U2X_FULL
unit.0.0.port.-1.s.23.orderindex=-1
unit.0.0.port.-1.s.23.visible=1
unit.0.0.port.-1.s.24.alias=
unit.0.0.port.-1.s.24.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.24.name=/s_U2X_AM_FULL
unit.0.0.port.-1.s.24.name=/GPIF_INTERFACE/o_RDYX
unit.0.0.port.-1.s.24.orderindex=-1
unit.0.0.port.-1.s.24.visible=1
unit.0.0.port.-1.s.25.alias=
unit.0.0.port.-1.s.25.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.25.name=/s_U2X_AM_EMPTY
unit.0.0.port.-1.s.25.name=/s_RX_DATA<0>
unit.0.0.port.-1.s.25.orderindex=-1
unit.0.0.port.-1.s.25.visible=1
unit.0.0.port.-1.s.25.visible=0
unit.0.0.port.-1.s.26.alias=
unit.0.0.port.-1.s.26.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.26.name=/s_opb_in<0>
unit.0.0.port.-1.s.26.name=/s_RX_DATA<1>
unit.0.0.port.-1.s.26.orderindex=-1
unit.0.0.port.-1.s.26.visible=0
unit.0.0.port.-1.s.27.alias=
unit.0.0.port.-1.s.27.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.27.name=/s_opb_in<1>
unit.0.0.port.-1.s.27.name=/s_RX_DATA<2>
unit.0.0.port.-1.s.27.orderindex=-1
unit.0.0.port.-1.s.27.visible=0
unit.0.0.port.-1.s.28.alias=
unit.0.0.port.-1.s.28.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.28.name=/s_opb_in<2>
unit.0.0.port.-1.s.28.name=/s_RX_DATA<3>
unit.0.0.port.-1.s.28.orderindex=-1
unit.0.0.port.-1.s.28.visible=0
unit.0.0.port.-1.s.29.alias=
unit.0.0.port.-1.s.29.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.29.name=/s_opb_in<3>
unit.0.0.port.-1.s.29.name=/s_RX_DATA<4>
unit.0.0.port.-1.s.29.orderindex=-1
unit.0.0.port.-1.s.29.visible=0
unit.0.0.port.-1.s.3.alias=
unit.0.0.port.-1.s.3.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.3.name=/s_dbus_out<3>
unit.0.0.port.-1.s.3.name=/GPIF_INTERFACE/s_dbus_out<1>
unit.0.0.port.-1.s.3.orderindex=-1
unit.0.0.port.-1.s.3.visible=0
unit.0.0.port.-1.s.30.alias=
unit.0.0.port.-1.s.30.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.30.name=/s_opb_in<4>
unit.0.0.port.-1.s.30.name=/s_RX_DATA<5>
unit.0.0.port.-1.s.30.orderindex=-1
unit.0.0.port.-1.s.30.visible=0
unit.0.0.port.-1.s.31.alias=
unit.0.0.port.-1.s.31.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.31.name=/s_opb_in<5>
unit.0.0.port.-1.s.31.name=/s_RX_DATA<6>
unit.0.0.port.-1.s.31.orderindex=-1
unit.0.0.port.-1.s.31.visible=0
unit.0.0.port.-1.s.32.alias=
unit.0.0.port.-1.s.32.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.32.name=/s_opb_in<6>
unit.0.0.port.-1.s.32.name=/s_RX_DATA<7>
unit.0.0.port.-1.s.32.orderindex=-1
unit.0.0.port.-1.s.32.visible=0
unit.0.0.port.-1.s.33.alias=
unit.0.0.port.-1.s.33.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.33.name=/s_opb_in<7>
unit.0.0.port.-1.s.33.name=/s_RX_DATA<8>
unit.0.0.port.-1.s.33.orderindex=-1
unit.0.0.port.-1.s.33.visible=0
unit.0.0.port.-1.s.34.alias=
unit.0.0.port.-1.s.34.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.34.name=/s_opb_in<8>
unit.0.0.port.-1.s.34.name=/s_RX_DATA<9>
unit.0.0.port.-1.s.34.orderindex=-1
unit.0.0.port.-1.s.34.visible=0
unit.0.0.port.-1.s.35.alias=
unit.0.0.port.-1.s.35.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.35.name=/s_opb_in<9>
unit.0.0.port.-1.s.35.name=/s_RX_DATA<10>
unit.0.0.port.-1.s.35.orderindex=-1
unit.0.0.port.-1.s.35.visible=0
unit.0.0.port.-1.s.36.alias=
unit.0.0.port.-1.s.36.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.36.name=/s_opb_in<10>
unit.0.0.port.-1.s.36.name=/s_RX_DATA<11>
unit.0.0.port.-1.s.36.orderindex=-1
unit.0.0.port.-1.s.36.visible=0
unit.0.0.port.-1.s.37.alias=
unit.0.0.port.-1.s.37.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.37.name=/s_opb_in<11>
unit.0.0.port.-1.s.37.name=/s_RX_DATA<12>
unit.0.0.port.-1.s.37.orderindex=-1
unit.0.0.port.-1.s.37.visible=0
unit.0.0.port.-1.s.38.alias=
unit.0.0.port.-1.s.38.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.38.name=/s_opb_in<12>
unit.0.0.port.-1.s.38.name=/s_RX_DATA<13>
unit.0.0.port.-1.s.38.orderindex=-1
unit.0.0.port.-1.s.38.visible=0
unit.0.0.port.-1.s.39.alias=
unit.0.0.port.-1.s.39.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.39.name=/s_opb_in<13>
unit.0.0.port.-1.s.39.name=/s_RX_DATA<14>
unit.0.0.port.-1.s.39.orderindex=-1
unit.0.0.port.-1.s.39.visible=0
unit.0.0.port.-1.s.4.alias=
unit.0.0.port.-1.s.4.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.4.name=/s_dbus_out<4>
unit.0.0.port.-1.s.4.name=/GPIF_INTERFACE/s_dbus_out<2>
unit.0.0.port.-1.s.4.orderindex=-1
unit.0.0.port.-1.s.4.visible=0
unit.0.0.port.-1.s.40.alias=
unit.0.0.port.-1.s.40.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.40.name=/s_opb_in<14>
unit.0.0.port.-1.s.40.name=/s_RX_DATA<15>
unit.0.0.port.-1.s.40.orderindex=-1
unit.0.0.port.-1.s.40.visible=0
unit.0.0.port.-1.s.41.alias=
unit.0.0.port.-1.s.41.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.41.name=/s_opb_in<15>
unit.0.0.port.-1.s.41.name=/s_EMPTY
unit.0.0.port.-1.s.41.orderindex=-1
unit.0.0.port.-1.s.41.visible=0
unit.0.0.port.-1.s.41.visible=1
unit.0.0.port.-1.s.42.alias=
unit.0.0.port.-1.s.42.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.42.name=/i_WRU_IBUF
unit.0.0.port.-1.s.42.orderindex=-1
unit.0.0.port.-1.s.42.visible=1
unit.0.0.port.-1.s.43.alias=
unit.0.0.port.-1.s.43.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.43.name=DataPort[43]
unit.0.0.port.-1.s.43.orderindex=-1
unit.0.0.port.-1.s.43.visible=1
unit.0.0.port.-1.s.44.alias=
unit.0.0.port.-1.s.44.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.44.name=/s_RD_EN
unit.0.0.port.-1.s.44.orderindex=-1
unit.0.0.port.-1.s.44.visible=1
unit.0.0.port.-1.s.5.alias=
unit.0.0.port.-1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.5.name=/s_dbus_out<5>
unit.0.0.port.-1.s.5.name=/GPIF_INTERFACE/s_dbus_out<3>
unit.0.0.port.-1.s.5.orderindex=-1
unit.0.0.port.-1.s.5.visible=0
unit.0.0.port.-1.s.6.alias=
unit.0.0.port.-1.s.6.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.6.name=/s_dbus_out<6>
unit.0.0.port.-1.s.6.name=/GPIF_INTERFACE/s_dbus_out<4>
unit.0.0.port.-1.s.6.orderindex=-1
unit.0.0.port.-1.s.6.visible=0
unit.0.0.port.-1.s.7.alias=
unit.0.0.port.-1.s.7.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.7.name=/s_dbus_out<7>
unit.0.0.port.-1.s.7.name=/GPIF_INTERFACE/s_dbus_out<5>
unit.0.0.port.-1.s.7.orderindex=-1
unit.0.0.port.-1.s.7.visible=0
unit.0.0.port.-1.s.8.alias=
unit.0.0.port.-1.s.8.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.8.name=/s_dbus_out<8>
unit.0.0.port.-1.s.8.name=/GPIF_INTERFACE/s_dbus_out<6>
unit.0.0.port.-1.s.8.orderindex=-1
unit.0.0.port.-1.s.8.visible=0
unit.0.0.port.-1.s.9.alias=
unit.0.0.port.-1.s.9.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.9.name=/s_dbus_out<9>
unit.0.0.port.-1.s.9.name=/GPIF_INTERFACE/s_dbus_out<7>
unit.0.0.port.-1.s.9.orderindex=-1
unit.0.0.port.-1.s.9.visible=0
unit.0.0.port.0.b.0.alias=
unit.0.0.port.0.b.0.channellist=0 1
unit.0.0.port.0.b.0.channellist=0 1 2 3
unit.0.0.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.b.0.name=TriggerPort0
unit.0.0.port.0.b.0.orderindex=-1
314,106 → 327,204
unit.0.0.port.0.b.0.unsignedScaleFactor=1.0
unit.0.0.port.0.b.0.visible=1
unit.0.0.port.0.buscount=1
unit.0.0.port.0.channelcount=2
unit.0.0.port.0.channelcount=4
unit.0.0.port.0.s.0.alias=
unit.0.0.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.0.name=/i_RDYU_IBUF
unit.0.0.port.0.s.0.name=/i_WRU_IBUF
unit.0.0.port.0.s.0.orderindex=-1
unit.0.0.port.0.s.0.visible=1
unit.0.0.port.0.s.1.alias=
unit.0.0.port.0.s.1.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.1.name=/o_RDYX_OBUF
unit.0.0.port.0.s.1.name=/o_WRX_OBUF
unit.0.0.port.0.s.1.orderindex=-1
unit.0.0.port.0.s.1.visible=1
unit.0.0.port.0.s.2.alias=
unit.0.0.port.0.s.2.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.2.name=/o_RDYX_OBUF
unit.0.0.port.0.s.2.orderindex=-1
unit.0.0.port.0.s.2.visible=1
unit.0.0.port.0.s.3.alias=
unit.0.0.port.0.s.3.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.0.s.3.name=/i_RDYU_IBUF
unit.0.0.port.0.s.3.orderindex=-1
unit.0.0.port.0.s.3.visible=1
unit.0.0.portcount=1
unit.0.0.samplesPerTrigger=1
unit.0.0.triggerCapture=1
unit.0.0.triggerNSamplesTS=0
unit.0.0.triggerPosition=0
unit.0.0.triggerPosition=32
unit.0.0.triggerWindowCount=1
unit.0.0.triggerWindowDepth=512
unit.0.0.triggerWindowTS=0
unit.0.0.username=MyILA0
unit.0.0.waveform.count=12
unit.0.0.waveform.posn.0.channel=2147483646
unit.0.0.waveform.posn.0.name=/s_opb_in
unit.0.0.waveform.posn.0.radix=1
unit.0.0.waveform.posn.0.type=bus
unit.0.0.waveform.posn.1.channel=2147483646
unit.0.0.waveform.posn.1.name=/s_dbus_out
unit.0.0.waveform.posn.1.radix=1
unit.0.0.waveform.posn.1.type=bus
unit.0.0.waveform.posn.10.channel=24
unit.0.0.waveform.posn.10.name=/s_U2X_AM_FULL
unit.0.0.waveform.count=15
unit.0.0.waveform.posn.0.channel=0
unit.0.0.waveform.posn.0.name=/o_WRX_OBUF
unit.0.0.waveform.posn.0.type=signal
unit.0.0.waveform.posn.1.channel=0
unit.0.0.waveform.posn.1.name=/o_WRX_OBUF
unit.0.0.waveform.posn.1.type=signal
unit.0.0.waveform.posn.10.channel=22
unit.0.0.waveform.posn.10.name=/GPIF_INTERFACE/s_U2X_WR_EN
unit.0.0.waveform.posn.10.type=signal
unit.0.0.waveform.posn.11.channel=25
unit.0.0.waveform.posn.11.name=/s_U2X_AM_EMPTY
unit.0.0.waveform.posn.11.channel=23
unit.0.0.waveform.posn.11.name=/GPIF_INTERFACE/s_U2X_FULL
unit.0.0.waveform.posn.11.radix=1
unit.0.0.waveform.posn.11.type=signal
unit.0.0.waveform.posn.12.channel=2147483646
unit.0.0.waveform.posn.12.name=/s_opb_in
unit.0.0.waveform.posn.12.name=/s_RX_DATA
unit.0.0.waveform.posn.12.radix=1
unit.0.0.waveform.posn.12.type=bus
unit.0.0.waveform.posn.13.channel=25
unit.0.0.waveform.posn.13.name=/s_U2X_AM_EMPTY
unit.0.0.waveform.posn.13.channel=41
unit.0.0.waveform.posn.13.name=/s_EMPTY
unit.0.0.waveform.posn.13.radix=1
unit.0.0.waveform.posn.13.type=signal
unit.0.0.waveform.posn.14.channel=25
unit.0.0.waveform.posn.14.name=/s_U2X_AM_EMPTY
unit.0.0.waveform.posn.14.channel=44
unit.0.0.waveform.posn.14.name=/s_RD_EN
unit.0.0.waveform.posn.14.radix=1
unit.0.0.waveform.posn.14.type=signal
unit.0.0.waveform.posn.15.channel=25
unit.0.0.waveform.posn.15.name=/s_U2X_AM_EMPTY
unit.0.0.waveform.posn.15.type=signal
unit.0.0.waveform.posn.16.channel=25
unit.0.0.waveform.posn.16.name=/s_U2X_AM_EMPTY
unit.0.0.waveform.posn.15.channel=2147483646
unit.0.0.waveform.posn.15.name=/GPIF_INTERFACE/s_dbus_out
unit.0.0.waveform.posn.15.radix=1
unit.0.0.waveform.posn.15.type=bus
unit.0.0.waveform.posn.16.channel=44
unit.0.0.waveform.posn.16.name=/s_RD_EN
unit.0.0.waveform.posn.16.radix=1
unit.0.0.waveform.posn.16.type=signal
unit.0.0.waveform.posn.17.channel=25
unit.0.0.waveform.posn.17.name=/s_U2X_AM_EMPTY
unit.0.0.waveform.posn.17.channel=44
unit.0.0.waveform.posn.17.name=/s_RD_EN
unit.0.0.waveform.posn.17.radix=1
unit.0.0.waveform.posn.17.type=signal
unit.0.0.waveform.posn.18.channel=25
unit.0.0.waveform.posn.18.name=/s_U2X_AM_EMPTY
unit.0.0.waveform.posn.18.channel=44
unit.0.0.waveform.posn.18.name=/s_RD_EN
unit.0.0.waveform.posn.18.radix=1
unit.0.0.waveform.posn.18.type=signal
unit.0.0.waveform.posn.19.channel=25
unit.0.0.waveform.posn.19.name=/s_U2X_AM_EMPTY
unit.0.0.waveform.posn.19.channel=44
unit.0.0.waveform.posn.19.name=/s_RD_EN
unit.0.0.waveform.posn.19.radix=1
unit.0.0.waveform.posn.19.type=signal
unit.0.0.waveform.posn.2.channel=16
unit.0.0.waveform.posn.2.name=/o_RDYX_OBUF
unit.0.0.waveform.posn.2.channel=24
unit.0.0.waveform.posn.2.name=/GPIF_INTERFACE/o_RDYX
unit.0.0.waveform.posn.2.type=signal
unit.0.0.waveform.posn.20.channel=25
unit.0.0.waveform.posn.20.name=/s_U2X_AM_EMPTY
unit.0.0.waveform.posn.20.channel=44
unit.0.0.waveform.posn.20.name=/s_RD_EN
unit.0.0.waveform.posn.20.radix=1
unit.0.0.waveform.posn.20.type=signal
unit.0.0.waveform.posn.21.channel=25
unit.0.0.waveform.posn.21.name=/s_U2X_AM_EMPTY
unit.0.0.waveform.posn.21.channel=44
unit.0.0.waveform.posn.21.name=/s_RD_EN
unit.0.0.waveform.posn.21.radix=1
unit.0.0.waveform.posn.21.type=signal
unit.0.0.waveform.posn.22.channel=25
unit.0.0.waveform.posn.22.name=/s_U2X_AM_EMPTY
unit.0.0.waveform.posn.22.channel=44
unit.0.0.waveform.posn.22.name=/s_RD_EN
unit.0.0.waveform.posn.22.radix=1
unit.0.0.waveform.posn.22.type=signal
unit.0.0.waveform.posn.23.channel=25
unit.0.0.waveform.posn.23.name=/s_U2X_AM_EMPTY
unit.0.0.waveform.posn.23.channel=44
unit.0.0.waveform.posn.23.name=/s_RD_EN
unit.0.0.waveform.posn.23.radix=1
unit.0.0.waveform.posn.23.type=signal
unit.0.0.waveform.posn.24.channel=25
unit.0.0.waveform.posn.24.name=/s_U2X_AM_EMPTY
unit.0.0.waveform.posn.24.channel=44
unit.0.0.waveform.posn.24.name=/s_RD_EN
unit.0.0.waveform.posn.24.radix=1
unit.0.0.waveform.posn.24.type=signal
unit.0.0.waveform.posn.25.channel=25
unit.0.0.waveform.posn.25.name=/s_U2X_AM_EMPTY
unit.0.0.waveform.posn.25.channel=44
unit.0.0.waveform.posn.25.name=/s_RD_EN
unit.0.0.waveform.posn.25.radix=1
unit.0.0.waveform.posn.25.type=signal
unit.0.0.waveform.posn.3.channel=17
unit.0.0.waveform.posn.3.name=/o_WRX_OBUF
unit.0.0.waveform.posn.26.channel=44
unit.0.0.waveform.posn.26.name=/s_RD_EN
unit.0.0.waveform.posn.26.radix=1
unit.0.0.waveform.posn.26.type=signal
unit.0.0.waveform.posn.27.channel=44
unit.0.0.waveform.posn.27.name=/s_RD_EN
unit.0.0.waveform.posn.27.radix=1
unit.0.0.waveform.posn.27.type=signal
unit.0.0.waveform.posn.28.channel=44
unit.0.0.waveform.posn.28.name=/s_RD_EN
unit.0.0.waveform.posn.28.radix=1
unit.0.0.waveform.posn.28.type=signal
unit.0.0.waveform.posn.29.channel=44
unit.0.0.waveform.posn.29.name=/s_RD_EN
unit.0.0.waveform.posn.29.radix=1
unit.0.0.waveform.posn.29.type=signal
unit.0.0.waveform.posn.3.channel=1
unit.0.0.waveform.posn.3.name=/i_RDYU_IBUF
unit.0.0.waveform.posn.3.type=signal
unit.0.0.waveform.posn.4.channel=18
unit.0.0.waveform.posn.4.name=/i_RDYU_IBUF
unit.0.0.waveform.posn.30.channel=44
unit.0.0.waveform.posn.30.name=/s_RD_EN
unit.0.0.waveform.posn.30.radix=1
unit.0.0.waveform.posn.30.type=signal
unit.0.0.waveform.posn.31.channel=44
unit.0.0.waveform.posn.31.name=/s_RD_EN
unit.0.0.waveform.posn.31.radix=1
unit.0.0.waveform.posn.31.type=signal
unit.0.0.waveform.posn.32.channel=44
unit.0.0.waveform.posn.32.name=/s_RD_EN
unit.0.0.waveform.posn.32.radix=1
unit.0.0.waveform.posn.32.type=signal
unit.0.0.waveform.posn.33.channel=44
unit.0.0.waveform.posn.33.name=/s_RD_EN
unit.0.0.waveform.posn.33.radix=1
unit.0.0.waveform.posn.33.type=signal
unit.0.0.waveform.posn.34.channel=44
unit.0.0.waveform.posn.34.name=/s_RD_EN
unit.0.0.waveform.posn.34.radix=1
unit.0.0.waveform.posn.34.type=signal
unit.0.0.waveform.posn.35.channel=44
unit.0.0.waveform.posn.35.name=/s_RD_EN
unit.0.0.waveform.posn.35.radix=1
unit.0.0.waveform.posn.35.type=signal
unit.0.0.waveform.posn.36.channel=44
unit.0.0.waveform.posn.36.name=/s_RD_EN
unit.0.0.waveform.posn.36.radix=1
unit.0.0.waveform.posn.36.type=signal
unit.0.0.waveform.posn.37.channel=44
unit.0.0.waveform.posn.37.name=/s_RD_EN
unit.0.0.waveform.posn.37.radix=1
unit.0.0.waveform.posn.37.type=signal
unit.0.0.waveform.posn.38.channel=44
unit.0.0.waveform.posn.38.name=/s_RD_EN
unit.0.0.waveform.posn.38.radix=1
unit.0.0.waveform.posn.38.type=signal
unit.0.0.waveform.posn.39.channel=44
unit.0.0.waveform.posn.39.name=/s_RD_EN
unit.0.0.waveform.posn.39.radix=1
unit.0.0.waveform.posn.39.type=signal
unit.0.0.waveform.posn.4.channel=42
unit.0.0.waveform.posn.4.name=/i_WRU_IBUF
unit.0.0.waveform.posn.4.type=signal
unit.0.0.waveform.posn.5.channel=19
unit.0.0.waveform.posn.5.name=/i_WRU_IBUF
unit.0.0.waveform.posn.5.type=signal
unit.0.0.waveform.posn.6.channel=20
unit.0.0.waveform.posn.6.name=/s_dbus_trans_dir_inv
unit.0.0.waveform.posn.40.channel=44
unit.0.0.waveform.posn.40.name=/s_RD_EN
unit.0.0.waveform.posn.40.radix=1
unit.0.0.waveform.posn.40.type=signal
unit.0.0.waveform.posn.41.channel=44
unit.0.0.waveform.posn.41.name=/s_RD_EN
unit.0.0.waveform.posn.41.radix=1
unit.0.0.waveform.posn.41.type=signal
unit.0.0.waveform.posn.42.channel=44
unit.0.0.waveform.posn.42.name=/s_RD_EN
unit.0.0.waveform.posn.42.type=signal
unit.0.0.waveform.posn.43.channel=44
unit.0.0.waveform.posn.43.name=/s_RD_EN
unit.0.0.waveform.posn.43.type=signal
unit.0.0.waveform.posn.44.channel=44
unit.0.0.waveform.posn.44.name=/s_RD_EN
unit.0.0.waveform.posn.44.type=signal
unit.0.0.waveform.posn.45.channel=44
unit.0.0.waveform.posn.45.name=/s_RD_EN
unit.0.0.waveform.posn.45.type=signal
unit.0.0.waveform.posn.5.channel=2147483646
unit.0.0.waveform.posn.5.name=/GPIF_INTERFACE/s_dbus_out
unit.0.0.waveform.posn.5.radix=1
unit.0.0.waveform.posn.5.type=bus
unit.0.0.waveform.posn.6.channel=18
unit.0.0.waveform.posn.6.name=/GPIF_INTERFACE/s_dbus_trans_dir
unit.0.0.waveform.posn.6.type=signal
unit.0.0.waveform.posn.7.channel=21
unit.0.0.waveform.posn.7.name=/s_U2X_WR_EN
unit.0.0.waveform.posn.7.channel=19
unit.0.0.waveform.posn.7.name=/GPIF_INTERFACE/o_RX
unit.0.0.waveform.posn.7.type=signal
unit.0.0.waveform.posn.8.channel=22
unit.0.0.waveform.posn.8.name=/s_X2U_RD_EN
unit.0.0.waveform.posn.8.channel=20
unit.0.0.waveform.posn.8.name=/GPIF_INTERFACE/o_TX
unit.0.0.waveform.posn.8.type=signal
unit.0.0.waveform.posn.9.channel=23
unit.0.0.waveform.posn.9.name=/s_X2U_EMPTY
unit.0.0.waveform.posn.9.channel=21
unit.0.0.waveform.posn.9.name=/GPIF_INTERFACE/s_U2X_AM_FULL
unit.0.0.waveform.posn.9.type=signal
/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple_prototype.xise
15,12 → 15,7
<version xil_pn:ise_version="11.1" xil_pn:schema_version="2"/>
 
<files>
<file xil_pn:name="USB_TMC_cmp.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="GECKO3COM_loopback.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="GECKO3COM_defines.vhd" xil_pn:type="FILE_VHDL">
27,12 → 22,6
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="USB_TMC_IP_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostMapSimulation"/>
<association xil_pn:name="PostTranslateSimulation"/>
</file>
<file xil_pn:name="coregenerator_fifo_dualclock.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
53,9 → 42,22
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="gpif_com_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="message_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="gpif_com_test_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation"/>
<association xil_pn:name="PostRouteSimulation"/>
<association xil_pn:name="PostMapSimulation"/>
<association xil_pn:name="PostTranslateSimulation"/>
</file>
<file xil_pn:name="gecko3com_test_chipscope.cdc" xil_pn:type="FILE_CDC">
<association xil_pn:name="Implementation"/>
</file>
<file xil_pn:name="coregenerator_fifo_dualclock.ise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation"/>
</file>
63,28 → 65,33
 
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false"/>
<property xil_pn:name="Command line syntax" xil_pn:value="emacsclient +$2 $1"/>
<property xil_pn:name="Compiled Library Directory" xil_pn:value="lib"/>
<property xil_pn:name="Constraints Entry" xil_pn:value="Constraints Editor"/>
<property xil_pn:name="Device" xil_pn:value="xc3s1500"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan3"/>
<property xil_pn:name="Editor" xil_pn:value="Custom"/>
<property xil_pn:name="Fitter Report Format" xil_pn:value="HTML"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|gpif_com_test|loopback"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/gpif_com_test"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="Soft"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="true"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|gpif_com_test_tb|simulation"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="usb_tmc_com"/>
<property xil_pn:name="PROP_mapSmartGuideFileName" xil_pn:value=""/>
<property xil_pn:name="PROP_parSmartGuideFileName" xil_pn:value=""/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs"/>
<property xil_pn:name="Package" xil_pn:value="fg676"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="false"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="false"/>
<property xil_pn:name="Report Type" xil_pn:value="Error Report"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Error Report"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="Architecture|USB_TMC_IP_tb|simulation"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="Yes"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="Architecture|gpif_com_test_tb|simulation"/>
<property xil_pn:name="Simulation Resolution" xil_pn:value="1 ns"/>
<property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="2000ns"/>
<property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE VHDL"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)"/>
<property xil_pn:name="Simulator Path" xil_pn:value="/opt/mentorGraphics/modeltech/bin/"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-4"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)"/>
95,6 → 102,7
 
<bindings>
<binding xil_pn:location="/gpif_com_test" xil_pn:name="GECKO3main_prototype.ucf"/>
<binding xil_pn:location="/gpif_com_test" xil_pn:name="gecko3com_test_chipscope.cdc"/>
</bindings>
 
<libraries/>
/GECKO3COM/gecko3com-ip/core/message_rom.vhd
0,0 → 1,52
-- This file was generated with hex2rom written by Daniel Wallner
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
 
entity message_rom is
port(
A : in std_logic_vector(4 downto 0);
D : out std_logic_vector(15 downto 0)
);
end message_rom;
 
architecture rtl of message_rom is
subtype ROM_WORD is std_logic_vector(15 downto 0);
type ROM_TABLE is array(0 to 31) of ROM_WORD;
signal ROM: ROM_TABLE := ROM_TABLE'(
"0000001000000010", -- 0x0000
"0000000011111101", -- 0x0002
"0000000000100000", -- 0x0004
"0000000000000000", -- 0x0006
"0000000000000001", -- 0x0008
"0000000000000000", -- 0x000A
"0110100101001101", -- 0x000C
"0111001001100011", -- 0x000E
"0100110001101111", -- 0x0010
"0110001001100001", -- 0x0012
"0100001000100000", -- 0x0014
"0100100001000110", -- 0x0016
"0101010000101101", -- 0x0018
"0010110001001001", -- 0x001A
"0100010101000111", -- 0x001C
"0100101101000011", -- 0x001E
"0011001101001111", -- 0x0020
"0100111101000011", -- 0x0022
"0010110001001101", -- 0x0024
"0011100100110001", -- 0x0026
"0011000000101100", -- 0x0028
"0011001100101110", -- 0x002A
"0000000000001010", -- 0x002C
"----------------", -- 0x002E
"----------------", -- 0x0030
"----------------", -- 0x0032
"----------------", -- 0x0034
"----------------", -- 0x0036
"----------------", -- 0x0038
"----------------", -- 0x003A
"----------------", -- 0x003C
"----------------"); -- 0x003E
begin
D <= ROM(to_integer(unsigned(A)));
end;
/GECKO3COM/gecko3com-ip/core/GECKO3main_prototype.ucf
39,6 → 39,8
net "i_nReset" loc = "AE24";
 
net "i_SYSCLK" loc = "AF14";
#net "i_SYSCLK" loc = "AA11"; # IFCLK, to test as a synchronus system
#net "i_SYSCLK" CLOCK_DEDICATED_ROUTE = FALSE; # also needed when IFCLK used as SYSCLK
net "i_SYSCLK" tnm_net = "SYSCLK";
timespec "TS_SYSCLK" = period "SYSCLK" 20.0 ns HIGH 50%; # 50 MHz system clock
 
54,22 → 56,22
net "o_RDYX" loc = "AD14";
 
# connection of data bus signals
net "b_dbus<0>" loc = "AA12";
net "b_dbus<1>" loc = "AB12";
net "b_dbus<2>" loc = "AB13";
net "b_dbus<3>" loc = "AC13";
net "b_dbus<4>" loc = "AA14";
net "b_dbus<5>" loc = "Y14";
net "b_dbus<6>" loc = "W14";
net "b_dbus<7>" loc = "Y15";
net "b_dbus<8>" loc = "AE7";
net "b_dbus<9>" loc = "Y13";
net "b_dbus<10>" loc = "W13";
net "b_dbus<11>" loc = "AF7";
net "b_dbus<12>" loc = "AF13";
net "b_dbus<13>" loc = "AD12";
net "b_dbus<14>" loc = "Y12";
net "b_dbus<15>" loc = "W12";
net "b_gpif_bus<0>" loc = "AA12";
net "b_gpif_bus<1>" loc = "AB12";
net "b_gpif_bus<2>" loc = "AB13";
net "b_gpif_bus<3>" loc = "AC13";
net "b_gpif_bus<4>" loc = "AA14";
net "b_gpif_bus<5>" loc = "Y14";
net "b_gpif_bus<6>" loc = "W14";
net "b_gpif_bus<7>" loc = "Y15";
net "b_gpif_bus<8>" loc = "AE7";
net "b_gpif_bus<9>" loc = "Y13";
net "b_gpif_bus<10>" loc = "W13";
net "b_gpif_bus<11>" loc = "AF7";
net "b_gpif_bus<12>" loc = "AF13";
net "b_gpif_bus<13>" loc = "AD12";
net "b_gpif_bus<14>" loc = "Y12";
net "b_gpif_bus<15>" loc = "W12";
 
 
# switches
84,5 → 86,8
net "o_LEDtx" loc = "F7"; # LED1, red
net "o_LEDrun"loc = "D7"; # LED2, green
 
# dummy output, only needed for the gpif_com_test
net "o_dummy" loc = "AF16";
 
 
 
/GECKO3COM/gecko3com-ip/core/GECKO3COM.ipf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/GECKO3COM/gecko3com-ip/core/usbtmc_idn_response_pkt.bin Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/GECKO3COM/gecko3com-ip/core/usbtmc_idn_response_pkt.bin
GECKO3COM/gecko3com-ip/core/usbtmc_idn_response_pkt.bin Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: GECKO3COM/gecko3com-ip/core/coregenerator_fifo_dualclock.ise =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: GECKO3COM/gecko3com-ip/core/gpif_com_test.vhd =================================================================== --- GECKO3COM/gecko3com-ip/core/gpif_com_test.vhd (revision 17) +++ GECKO3COM/gecko3com-ip/core/gpif_com_test.vhd (revision 18) @@ -22,13 +22,13 @@ -- -- URL to the project description: -- http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start ----------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- -- -- Author: Christoph Zimmermann -- Date of creation: 8. April 2009 -- Description: --- First test scenario for the GECKO3com IP core. --- This module (to be implemented as top module) is used to test the +-- First test scenario for the GECKO3com IP core. +-- This module (to be implemented as top module) is used to test the -- low-level communication between the GPIF from the EZ-USB and the FPGA. -- For this, it instantiates the the gpif_com module, reads all the -- received data from the FIFO (and puts them to nowhere) and writes a pre @@ -38,14 +38,16 @@ -- ROM content in this file (don't forget to adjust the the transfer size -- field AND the counter limit). -- --- Target Devices: Xilinx Spartan3 FPGA's (usage of BlockRam in the Datapath) --- Tool versions: 11.1 +-- Target Devices: Xilinx Spartan3 FPGA's (usage of BlockRam in the +-- Datapath) +-- Tool versions: 11.1 -- Dependencies: -- ----------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; library work; use work.GECKO3COM_defines.all; @@ -52,191 +54,184 @@ entity gpif_com_test is port ( - i_nReset, - i_IFCLK, -- GPIF CLK (GPIF is Master and provides the clock) - i_SYSCLK, -- FPGA System CLK - i_WRU, -- write from GPIF - i_RDYU : in std_logic; -- GPIF is ready - o_WRX, -- To write to GPIF - o_RDYX : out std_logic; -- IP Core is ready - o_LEDrx, -- controll LED rx - o_LEDtx : out std_logic; -- controll LED tx - o_LEDrun : out std_logic; -- controll LED running signalisation - b_gpif_bus : inout std_logic_vector(SIZE_DBUS_GPIF-1 downto 0)); -- bidirect data bus - ); + i_nReset : in std_logic; + i_IFCLK : in std_logic; -- GPIF CLK (GPIF is Master and provides the clock) + i_SYSCLK : in std_logic; -- FPGA System CLK + i_WRU : in std_logic; -- write from GPIF + i_RDYU : in std_logic; -- GPIF is ready + o_WRX : out std_logic; -- To write to GPIF + o_RDYX : out std_logic; -- IP Core is ready + b_gpif_bus : inout std_logic_vector(SIZE_DBUS_GPIF-1 downto 0); -- bidirect data bus + o_LEDrx : out std_logic; -- controll LED rx + o_LEDtx : out std_logic; -- controll LED tx + o_LEDrun : out std_logic; -- controll LED running signalisation + o_dummy : out std_logic -- dummy output for RX data consumer + ); end gpif_com_test; -architecture loopback of gpif_com_test is +architecture behaviour of gpif_com_test is - - type t_fsmLoop is (rst, idle, writeRQ, writeIn, writeEnd); - - signal pr_stateLoop, nx_stateLoop : t_fsmLoop; - - signal i_U2X_AM_EMPTY, - i_U2X_EMPTY, - i_X2U_AM_FULL, - i_X2U_FULL : in std_logic; - signal i_U2X_DATA : in std_logic_vector(SIZE_DBUS_FPGA-1 downto 0); - signal o_U2X_RD_EN, - o_X2U_WR_EN : out std_logic; - signal o_X2U_DATA : out std_logic_vector(SIZE_DBUS_FPGA-1 downto 0) ----------------------------------------------------------------------------- -- controll bus ----------------------------------------------------------------------------- - signal s_U2X_RD_EN, - s_X2U_WR_EN : std_logic; + signal s_EMPTY, s_FULL : std_logic; + signal s_RX_DATA : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0); + signal s_RD_EN, s_WR_EN : std_logic; + signal s_TX_DATA : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0); + signal s_RDYX : std_logic; + + signal s_ABORT, s_ABORT_TMP : std_logic; + signal s_RX_DATA_TMP : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0); + signal s_EMPTY_TMP, s_FULL_TMP : std_logic; - --------------------------------------------------------------------------------- + signal s_rom_adress : std_logic_vector(4 downto 0); + + + ----------------------------------------------------------------------------- -- COMPONENTS - --------------------------------------------------------------------------------- - + ----------------------------------------------------------------------------- + component gpif_com - port ( - i_nReset, - i_IFCLK, -- GPIF CLK (GPIF is Master and provides the clock) - i_SYSCLK, -- FPGA System CLK - i_WRU, -- write from GPIF - i_RDYU : in std_logic; -- GPIF is ready - o_WRX, -- To write to GPIF - o_RDYX : out std_logic; -- IP Core is ready - o_ABORT : out std_logic; -- Abort detected, you have to flush the data - o_RX, -- controll LED rx - o_TX : out std_logic; -- controll LED tx - b_gpif_bus : inout std_logic_vector(SIZE_DBUS_GPIF-1 downto 0)); -- bidirect data bus - end USB_TMC_IP; - -begin + port ( + i_nReset : in std_logic; + i_SYSCLK : in std_logic; + o_ABORT : out std_logic; + o_RX : out std_logic; + o_TX : out std_logic; + i_RD_EN : in std_logic; + o_EMPTY : out std_logic; + o_RX_DATA : out std_logic_vector(SIZE_DBUS_GPIF-1 downto 0); + i_WR_EN : in std_logic; + o_FULL : out std_logic; + i_TX_DATA : in std_logic_vector(SIZE_DBUS_GPIF-1 downto 0); + i_IFCLK : in std_logic; + i_WRU : in std_logic; + i_RDYU : in std_logic; + o_WRX : out std_logic; + o_RDYX : out std_logic; + b_gpif_bus : inout std_logic_vector(SIZE_DBUS_GPIF-1 downto 0)); + end component; - o_U2X_RD_EN <= s_U2X_RD_EN; - o_X2U_WR_EN <= s_X2U_WR_EN; - - o_LEDrun <= '1'; - - - GPIF_INTERFACE : gpif_com - port map ( - i_nReset => i_nReset, - i_IFCLK => i_IFCLK, -- GPIF CLK (GPIF is Master and provides the clock) - i_SYSCLK => i_SYSCLK, -- FPGA System CLK - i_WRU => i_WRU, -- write from GPIF - i_RDYU => i_RDYU, -- GPIF is ready - o_WRX => o_WRX, -- To write to GPIF - o_RDYX => o_RDYX, -- IP Core is ready - o_ABORT => o_ABORT, -- Abort detected, you have to flush the data - o_LEDrx => o_LEDrx, -- controll LED rx - o_LEDtx => o_LEDtx, -- controll LED tx - o_LEDrun => o_LEDrun, -- controll LED running signalisation - b_gpif_bus => b_gpif_buf - ); + component message_rom + port ( + A : in std_logic_vector(4 downto 0); + D : out std_logic_vector(15 downto 0)); + end component; - --------------------------------------------------------------------------- - -- FPGA CLK DOMAIN -> opb site - --------------------------------------------------------------------------- +begin -- behaviour - bus_loop_Dmap : process (i_SYSCLK) + GPIF_INTERFACE: gpif_com + port map ( + i_nReset => i_nReset, + i_SYSCLK => i_SYSCLK, + o_ABORT => s_ABORT, + o_RX => o_LEDrx, + o_TX => o_LEDtx, + i_RD_EN => s_RD_EN, + o_EMPTY => s_EMPTY, + o_RX_DATA => s_RX_DATA, + i_WR_EN => s_WR_EN, + o_FULL => s_FULL, + i_TX_DATA => s_TX_DATA, + --i_IFCLK => i_SYSCLK, + i_IFCLK => i_IFCLK, + i_WRU => i_WRU, + i_RDYU => i_RDYU, + o_WRX => o_WRX, + o_RDYX => o_RDYX, + b_gpif_bus => b_gpif_bus); - begin -- process bus_access - if rising_edge(i_SYSCLK) then - o_X2U_DATA <= i_U2X_DATA; - end if; - end process bus_loop_Dmap; + + o_LEDrun <= '1'; - ----------------------------------------------------------------------------- - -- FSM Loop + ----------------------------------------------------------------------------- + -- RX DATA CONSUMER WITH THROTLING + ----------------------------------------------------------------------------- - -- state reg - actionLoop : process(i_SYSCLK, i_nReset) - begin + -- purpose: activates the read enable signal of the receive FIFO as slow as + -- you want. + -- type : sequential + -- inputs : i_SYSCLK + -- outputs: s_RX_DATA_TMP + rx_throtling: process (i_SYSCLK, i_nReset) + variable v_rx_throtle_count : std_logic_vector(6 downto 0); -- counter variable + begin + if i_nReset = '0' then + v_rx_throtle_count := (others => '0'); + s_RD_EN <= '0'; + elsif i_SYSCLK = '1' and i_SYSCLK'event then + if v_rx_throtle_count >= 63 then + s_RD_EN <= '1'; + v_rx_throtle_count := (others => '0'); + else + v_rx_throtle_count := v_rx_throtle_count + 1; + s_RD_EN <= '0'; + end if; + end if; + end process rx_throtling; - if i_nReset = '0' then - pr_stateLoop <= rst; + -- purpose: reads the receive data from the GPIF interface + -- type : sequential + -- inputs : i_SYSCLK + -- outputs: s_RX_DATA_TMP + rx_consumer: process (i_SYSCLK) + begin -- process rx_consumer + if i_SYSCLK = '1' and i_SYSCLK'event then + s_RX_DATA_TMP <= s_RX_DATA; + s_EMPTY_TMP <= s_EMPTY; + s_FULL_TMP <= s_FULL; + s_ABORT_TMP <= s_ABORT; + end if; + end process rx_consumer; - elsif rising_edge(i_SYSCLK) then - pr_stateLoop <= nx_stateLoop; + -- dummy logic to "use" these signals and avoid that they are removed by + -- the optimizer + process(s_RX_DATA_TMP, s_EMPTY_TMP, s_FULL_TMP, s_ABORT_TMP, s_RDYX) + variable result : std_logic := '0'; + begin + result := '0'; + for i in s_RX_DATA_TMP'range loop + result := result or s_RX_DATA_TMP(i); + end loop; + o_dummy <= result or s_EMPTY_TMP or s_FULL_TMP or s_ABORT_TMP; + end process; + ----------------------------------------------------------------------------- + -- RESPONSE MESSAGE GENERATOR + ----------------------------------------------------------------------------- + + message_rom_1: message_rom + port map ( + A => s_rom_adress, + D => s_TX_DATA); + + -- purpose: counts up the rom adress lines to read out the response message + -- type : sequential + -- inputs : i_SYSCLK + -- outputs: s_RX_DATA_TMP + rom_adress_counter: process (i_SYSCLK, i_nReset) + begin + if i_nReset = '0' then + s_rom_adress <= (others => '0'); + --DEBUG s_WR_EN <= '1'; + s_WR_EN <= '0'; + elsif i_SYSCLK = '1' and i_SYSCLK'event then + if s_rom_adress = 24 then + s_rom_adress <= s_rom_adress; + s_WR_EN <= '0'; + else + s_rom_adress <= s_rom_adress + 1; + --DEBUG s_WR_EN <= '1'; + s_WR_EN <= '0'; end if; - end process actionLoop; - - - -- comb logic - loopTrans : process(pr_stateLoop, i_U2X_AM_EMPTY, i_U2X_EMPTY, i_X2U_AM_FULL ) - begin -- process transaction - - -- default signal sets to avoid latches - s_X2U_WR_EN <= '0'; - s_U2X_RD_EN <= '0'; - - case pr_stateLoop is - -- controll - - when rst => - s_X2U_WR_EN <= '0'; - s_U2X_RD_EN <= '0'; - nx_stateLoop <= idle; - - when idle => - -- when the input fifo has data (is not empty) and the output fifo is not full: - if i_U2X_AM_EMPTY = '0' and i_X2U_AM_FULL = '0' then - nx_stateLoop <= writeRQ; - s_U2X_RD_EN <= '1'; - else - nx_stateLoop <= idle; - end if; - - when writeRQ => - -- enable read from input fifo. wait one cycle untill the data is available to be written - s_U2X_RD_EN <= '1'; - s_X2U_WR_EN <= '0'; - nx_stateLoop <= writeIn; - - when writeIn => - - if i_U2X_EMPTY = '1' and i_X2U_AM_FULL = '0' then - -- input fifo is empty, end the transfer - nx_stateLoop <= writeEnd; - s_U2X_RD_EN <= '1'; -- i guess that this should be '0' here. zac1 - s_X2U_WR_EN <= '1'; - - elsif i_U2X_EMPTY = '0' and i_X2U_AM_FULL = '1' then - -- output data is full, still data in the input fifo - nx_stateLoop <= writeEnd; - s_U2X_RD_EN <= '0'; - s_X2U_WR_EN <= '1'; - - elsif i_U2X_EMPTY = '1' and i_X2U_AM_FULL = '1' then - -- input fifo empty and output fifo full - nx_stateLoop <= writeEnd; --idle; - s_U2X_RD_EN <= '0'; - s_X2U_WR_EN <= '1'; ---s_X2U_WR_EN <= '0'; - - else - -- input fifo has data, output fifo has free space - nx_stateLoop <= writeIn; - s_X2U_WR_EN <= '1'; - s_U2X_RD_EN <= '1'; - end if; - - - when writeEnd => - -- copy the last data from the register to the output fifo - nx_stateLoop <= idle; - s_U2X_RD_EN <= '0'; - s_X2U_WR_EN <= '1'; - - - -- error case - when others => - nx_stateLoop <= idle; - end case; - - end process loopTrans; - -end loopback; + end if; + end process rom_adress_counter; + +end behaviour;
/GECKO3COM/gecko3com-ip/core/gpif_com.vhd
22,20 → 22,23
--
-- URL to the project description:
-- http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
--
-- Author: Andreas Habegger, Christoph Zimmermann
-- Date of creation: 8. April 2009
-- Description:
-- GECKO3COM defines the communication between the GECKO3main and a USB Master e.g. a computer.
-- This file is the top module, it instantiates all required submodules and connects them
-- together.
-- GECKO3COM defines the communication between the GECKO3main and a USB
-- Master e.g. a computer.
--
-- Target Devices: Xilinx Spartan3 FPGA's (usage of BlockRam in the Datapath)
-- Tool versions: 11.1
-- This file is the top module, it instantiates all required submodules and
-- connects them together.
--
-- Target Devices: Xilinx Spartan3 FPGA's
-- (usage of BlockRam in the Datapath)
-- Tool versions: 11.1
-- Dependencies:
--
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
43,22 → 46,30
 
library work;
use work.GECKO3COM_defines.all;
use work.USB_TMC_cmp.all;
 
 
entity gpif_com is
port (
i_nReset,
i_IFCLK, -- GPIF CLK (GPIF is Master and provides the clock)
i_SYSCLK, -- FPGA System CLK
i_WRU, -- write from GPIF
i_RDYU : in std_logic; -- GPIF is ready
o_WRX, -- To write to GPIF
o_RDYX : out std_logic; -- IP Core is ready
o_ABORT : out std_logic; -- Abort detected, you have to flush the data
o_RX, -- controll LED rx
o_TX : out std_logic; -- controll LED tx
b_gpif_bus : inout std_logic_vector(SIZE_DBUS_GPIF-1 downto 0)); -- bidirect data bus
-- interface signals to higher level
i_nReset : in std_logic; -- asynchronous active low reset
i_SYSCLK : in std_logic; -- FPGA System CLK
o_ABORT : out std_logic; -- Abort detected, you have to flush the data
o_RX : out std_logic; -- controll LED rx
o_TX : out std_logic; -- controll LED tx
i_RD_EN : in std_logic; -- read enable
o_EMPTY : out std_logic; -- receive fifo empty
o_RX_DATA : out std_logic_vector(SIZE_DBUS_GPIF-1 downto 0); -- receive data
i_WR_EN : in std_logic; -- write enable
o_FULL : out std_logic; -- send fifo full
i_TX_DATA : in std_logic_vector(SIZE_DBUS_GPIF-1 downto 0); -- send data
 
-- GPIF connections, to be connected to FPGA pins
i_IFCLK : in std_logic; -- GPIF CLK (GPIF is Master and provides the clock)
i_WRU : in std_logic; -- write from GPIF
i_RDYU : in std_logic; -- GPIF is ready
o_WRX : out std_logic; -- To write to GPIF
o_RDYX : out std_logic; -- IP Core is ready
b_gpif_bus : inout std_logic_vector(SIZE_DBUS_GPIF-1 downto 0)); -- bidirect data bus
end gpif_com;
 
 
67,41 → 78,39
-- interconection signals
 
signal s_FIFOrst : std_logic;
signal s_FIFOrst, s_WRX, s_RDYX : std_logic;
signal s_ABORT_FSM, s_ABORT_TMP : std_logic;
signal s_RX_FSM, s_RX_TMP : std_logic;
signal s_TX_FSM, s_TX_TMP : std_logic;
-- USB to Xilinx (U2X)
-- USB to Xilinx (U2X)
signal s_U2X_WR_EN,
s_U2X_RD_EN,
s_U2X_FULL,
s_U2X_AM_FULL,
s_U2X_EMPTY,
s_U2X_AM_EMPTY : std_logic;
 
-- Xilinx to USB (X2U)
s_U2X_RD_EN,
s_U2X_FULL,
s_U2X_AM_FULL,
s_U2X_EMPTY,
s_U2X_AM_EMPTY : std_logic;
signal s_U2X_DATA : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
-- Xilinx to USB (X2U)
signal s_X2U_WR_EN,
s_X2U_RD_EN,
s_X2U_FULL,
s_X2U_AM_FULL,
s_X2U_EMPTY,
s_X2U_AM_EMPTY : std_logic;
 
-------------------------------------------------------------------------------
s_X2U_RD_EN,
s_X2U_FULL,
s_X2U_AM_FULL,
s_X2U_EMPTY,
s_X2U_AM_EMPTY : std_logic;
signal s_X2U_DATA : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
-----------------------------------------------------------------------------
-- data bus
-------------------------------------------------------------------------------
-----------------------------------------------------------------------------
 
-- data signals
signal s_dbus_trans_dir : std_logic;
signal s_dbus_in : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
signal s_dbus_out : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
signal s_opb_in : std_logic_vector(SIZE_DBUS_FPGA-1 downto 0);
signal s_opb_out : std_logic_vector(SIZE_DBUS_FPGA-1 downto 0);
signal s_dbus_in : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
signal s_dbus_out : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
 
-----------------------------------------------------------------------------
-- COMPONENTS
-----------------------------------------------------------------------------
108,41 → 117,41
 
-- FSM GPIF
component gpif_com_fsm
port (
i_nReset,
i_IFCLK, -- GPIF CLK (is Master)
i_WRU, -- write from GPIF
i_RDYU : in std_logic; -- GPIF is ready
i_U2X_FULL,
i_U2X_AM_FULL, -- signals for IN FIFO
i_X2U_AM_EMPTY,
i_X2U_EMPTY : in std_logic; -- signals for OUT FIFO
o_bus_trans_dir : out std_logic;
o_U2X_WR_EN, -- signals for IN FIFO
o_X2U_RD_EN, -- signals for OUT FIFO
o_FIFOrst,
o_WRX, -- To write to GPIF
o_RDYX : out std_logic; -- Core is ready
o_ABORT : out std_logic; -- abort condition detected. we have to flush the data
o_RX,
o_TX : out std_logic --
);
port (
i_nReset,
i_IFCLK, -- GPIF CLK (is Master)
i_WRU, -- write from GPIF
i_RDYU : in std_logic; -- GPIF is ready
i_U2X_FULL,
i_U2X_AM_FULL, -- signals for IN FIFO
i_X2U_AM_EMPTY,
i_X2U_EMPTY : in std_logic; -- signals for OUT FIFO
o_bus_trans_dir : out std_logic;
o_U2X_WR_EN, -- signals for IN FIFO
o_X2U_RD_EN, -- signals for OUT FIFO
o_FIFOrst,
o_WRX, -- To write to GPIF
o_RDYX : out std_logic; -- Core is ready
o_ABORT : out std_logic; -- abort condition detected. we have to flush the data
o_RX,
o_TX : out std_logic --
);
end component;
 
-- FIFO dualclock to cross the clock domain between the GPIF and the FPGA
component fifo_dualclock
port (
i_din : IN std_logic_VECTOR(SIZE_DBUS_GPIF-1 downto 0);
i_rd_clk : IN std_logic;
i_rd_en : IN std_logic;
i_rst : IN std_logic;
i_wr_clk : IN std_logic;
i_wr_en : IN std_logic;
o_almost_empty : OUT std_logic;
o_almost_full : OUT std_logic;
o_dout : OUT std_logic_VECTOR(SIZE_DBUS_GPIF-1 downto 0);
o_empty : OUT std_logic;
o_full : OUT std_logic);
port (
i_din : IN std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
i_rd_clk : IN std_logic;
i_rd_en : IN std_logic;
i_rst : IN std_logic;
i_wr_clk : IN std_logic;
i_wr_en : IN std_logic;
o_almost_empty : OUT std_logic;
o_almost_full : OUT std_logic;
o_dout : OUT std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
o_empty : OUT std_logic;
o_full : OUT std_logic);
end component;
 
153,96 → 162,109
-----------------------------------------------------------------------------
 
F_IN : fifo_dualclock
port map (
i_din => s_dbus_in,
i_rd_clk => i_SYSCLK,
i_rd_en => s_U2X_RD_EN,
i_rst => s_FIFOrst,
i_wr_clk => i_IFCLK ,
i_wr_en => s_U2X_WR_EN,
o_almost_empty => s_U2X_AM_EMPTY,
o_almost_full => s_U2X_AM_FULL,
o_dout => s_opb_in,
o_empty => s_U2X_EMPTY,
o_full => s_U2X_FULL
);
port map (
i_din => s_dbus_in,
i_rd_clk => i_SYSCLK,
i_rd_en => s_U2X_RD_EN,
i_rst => s_FIFOrst,
i_wr_clk => i_IFCLK ,
i_wr_en => s_U2X_WR_EN,
o_almost_empty => s_U2X_AM_EMPTY,
o_almost_full => s_U2X_AM_FULL,
o_dout => s_U2X_DATA,
o_empty => s_U2X_EMPTY,
o_full => s_U2X_FULL
);
 
 
F_OUT : fifo_dualclock
port map (
i_din => s_opb_out,
i_rd_clk => i_IFCLK,
i_rd_en => s_X2U_RD_EN,
i_rst => s_FIFOrst,
i_wr_clk => i_SYSCLK,
i_wr_en => s_X2U_WR_EN,
o_almost_empty => s_X2U_AM_EMPTY,
o_almost_full => s_X2U_AM_FULL,
o_dout => s_dbus_out,
o_empty => s_X2U_EMPTY,
o_full => s_X2U_FULL
);
port map (
i_din => s_X2U_DATA,
i_rd_clk => i_IFCLK,
i_rd_en => s_X2U_RD_EN,
i_rst => s_FIFOrst,
i_wr_clk => i_SYSCLK,
i_wr_en => s_X2U_WR_EN,
o_almost_empty => s_X2U_AM_EMPTY,
o_almost_full => s_X2U_AM_FULL,
o_dout => s_dbus_out,
o_empty => s_X2U_EMPTY,
o_full => s_X2U_FULL
);
 
 
FSM_GPIF : gpif_com_fsm
port map (
i_nReset => i_nReset,
i_IFCLK => i_IFCLK,
i_WRU => i_WRU,
i_RDYU => i_RDYU,
i_U2X_FULL => s_U2X_FULL,
i_U2X_AM_FULL => s_U2X_AM_FULL,
i_X2U_AM_EMPTY => s_X2U_AM_EMPTY,
i_X2U_EMPTY => s_X2U_EMPTY,
o_U2X_WR_EN => s_U2X_WR_EN,
o_X2U_RD_EN => s_X2U_RD_EN,
o_FIFOrst => s_FIFOrst,
o_bus_trans_dir => s_dbus_trans_dir,
o_WRX => o_WRX,
o_RDYX => o_RDYX,
o_ABORT => s_ABORT_FSM,
o_RX => o_RX,
o_TX => o_TX,
);
port map (
i_nReset => i_nReset,
i_IFCLK => i_IFCLK,
i_WRU => i_WRU,
i_RDYU => i_RDYU,
i_U2X_FULL => s_U2X_FULL,
i_U2X_AM_FULL => s_U2X_AM_FULL,
i_X2U_AM_EMPTY => s_X2U_AM_EMPTY,
i_X2U_EMPTY => s_X2U_EMPTY,
o_U2X_WR_EN => s_U2X_WR_EN,
o_X2U_RD_EN => s_X2U_RD_EN,
o_FIFOrst => s_FIFOrst,
o_bus_trans_dir => s_dbus_trans_dir,
o_WRX => s_WRX,
o_RDYX => s_RDYX,
o_ABORT => s_ABORT_FSM,
o_RX => s_RX_FSM,
o_TX => s_TX_FSM
);
 
 
s_U2X_RD_EN <= i_RD_EN;
o_EMPTY <= s_U2X_EMPTY;
o_RX_DATA <= s_U2X_DATA;
 
s_X2U_WR_EN <= i_WR_EN;
o_FULL <= s_X2U_FULL;
s_X2U_DATA <= i_TX_DATA;
 
o_WRX <= s_WRX;
o_RDYX <= s_RDYX;
 
-- Double buffer the ABORT, RX and TX signal to avoid metastability
double_buf_sig : process (i_SYSCLK, i_nReset)
begin
if i_nReset = '0' then
o_ABORT <= '0';
o_ABORT <= '0';
s_ABORT_TMP <= '0';
s_TX_FSM <= '0';
s_TX_TMP <= '0';
s_RX_FSM <= '0';
s_TX_TMP <= '0';
elsif rising_edge(i_SYSCLK)
o_ABORT <= s_ABORT_TMP;
o_TX <= '0';
s_TX_TMP <= '0';
o_RX <= '0';
s_RX_TMP <= '0';
elsif rising_edge(i_SYSCLK) then
o_ABORT <= s_ABORT_TMP;
s_ABORT_TMP <= s_ABORT_FSM;
o_TX <= s_TX_TMP;
s_TX_TMP <= s_TX_FSM;
o_RX <= s_RX_TMP;
s_RX_TMP <= s_RX_FSM;
o_TX <= s_TX_TMP;
s_TX_TMP <= s_TX_FSM;
o_RX <= s_RX_TMP;
s_RX_TMP <= s_RX_FSM;
end if;
end process double_buf_sig;
 
-----------------------------------------------------------------------------
-- Data bus access
-----------------------------------------------------------------------------
 
-- purpose: to handle the access on the bidirectional bus
-- type : combinational
-- inputs : s_bus_trans_dir
-- outputs:
-----------------------------------------------------------------------------
-- Data bus access
-----------------------------------------------------------------------------
 
-- purpose: to handle the access on the bidirectional bus
-- type : combinational
-- inputs : s_bus_trans_dir
-- outputs:
bus_access : process (s_dbus_trans_dir, s_dbus_out)
begin -- process bus_access
if s_dbus_trans_dir = '1' then
b_gpifbus <= s_dbus_out;
b_gpif_bus <= s_dbus_out;
else
b_gpifbus <= (others => 'Z');
b_gpif_bus <= (others => 'Z');
end if;
end process bus_access;
s_dbus_in <= b_gpifbus;
 
s_dbus_in <= b_gpif_bus;
 
end structure;
/GECKO3COM/gecko3com-fw/firmware/src/gecko3com_main.c
848,6 → 848,13
}
} /* end of IN Transfer clause */
 
/* if(!(EP2468STAT & bmEP2EMPTY) && flLOCAL == GECKO3COM_REMOTE) { */
/* flGPIF &= ~bmGPIF_PENDING_DATA; */
/* OUTPKTEND = USB_TMC_EP_OUT; */
/* gpif_trigger_write(); */
/* EP2FIFOCFG |= bmAUTOOUT; */
/* } */
 
/* if the LED flag is set to off, disable the external LED */
if(flLED == LEDS_OFF) {
set_led_ext(LEDS_OFF);
/GECKO3COM/gecko3com-fw/firmware/src/gecko3com_gpif.c
92,10 → 92,14
 
clear_fifo_gpif_irq();
 
/* check if there is data available for an OUT transfer */
//if((flGPIF & bmGPIF_PENDING_DATA) == bmGPIF_PENDING_DATA) {
if(!(EP2468STAT & bmEP2EMPTY)) {
//EA = 0; /* disable all interrupts */
 
/* check if there is data available for an OUT transfer */
if((flGPIF & bmGPIF_PENDING_DATA) == bmGPIF_PENDING_DATA) {
//if(!(EP2468STAT & bmEP2EMPTY)) {
flGPIF &= ~bmGPIF_PENDING_DATA;
GPIFABORT = 0xFF;
SYNCDELAY;
gpif_trigger_write();
}
else {
102,7 → 106,8
INPKTEND = USB_TMC_EP_IN;
gpif_trigger_read();
}
 
//EA = 1; /* global interrupt enable */
ISR_DEBUG_PORT &= ~bmGPIF_DONE;
}
 
118,16 → 123,16
clear_fifo_gpif_irq();
 
/* check if there is a active IN transfer */
/*if((GPIFIDLECTL & bmBIT3) == bmBIT3) {
if((GPIFIDLECTL & bmBIT3) == bmBIT3) {
flGPIF |= bmGPIF_PENDING_DATA;
}
else*/ {
EA = 0; /* disable all interrupts */
else {
//EA = 0; /* disable all interrupts */
GPIFABORT = 0xFF;
SYNCDELAY;
EA = 1; /* global interrupt enable */
 
gpif_trigger_write();
//EA = 1; /* global interrupt enable */
}
 
ISR_DEBUG_PORT &= ~bmFIFO_PF;
150,9 → 155,6
/*FIXME only here for testing */
//EP6AUTOINLENH = (20) >> 8; SYNCDELAY; /* this is the length for high speed */
//EP6AUTOINLENL = (20) & 0xff; SYNCDELAY;
//REVCTL = 0; /* set it back to 0 */
//SYNCDELAY;
 
/* enable autoout and autoin feature of the endpoints */
EP2FIFOCFG |= bmAUTOOUT;
161,15 → 163,16
SYNCDELAY;
 
/* set endpoint 2 fifo (out) programmable flag to "higher or equal 3"
* we use the programmable flag as interrupt source to detect if data for the FPGA
* is available and as GPIF flag to stop the flowstate, for this the flag has to change
* one cycle before the FIFO is completly empty, else we transfer one word too much */
* we use the programmable flag as interrupt source to detect if data for the
* FPGA is available and as GPIF flag to stop the flowstate, for this the
* flag has to change one cycle before the FIFO is completly empty, else we
* transfer one word too much */
EP2FIFOPFH = bmDECIS;
EP2FIFOPFL = 3;
EP2FIFOPFL = 1;
SYNCDELAY;
 
EP2GPIFFLGSEL = bmFLAG_PROGRAMMABLE;
// EP2GPIFFLGSEL = bmFLAG_EMPTY;
//EP2GPIFFLGSEL = bmFLAG_PROGRAMMABLE;
EP2GPIFFLGSEL = bmFLAG_EMPTY;
SYNCDELAY;
EP6GPIFFLGSEL = bmFLAG_FULL;
SYNCDELAY;
212,7 → 215,6
to signal the firmware that the GPIF is done */
hook_fgv(FGV_GPIFWF,(unsigned short) isr_gpif_done);
hook_fgv(FGV_EP2PF,(unsigned short) isr_endpoint_out_data);
hook_fgv(FGV_EP2PF,(unsigned short) isr_endpoint_out_data);
 
EP2FIFOIE = bmFIFO_PF;
GPIFIE = bmGPIFWF;
283,9 → 285,6
flGPIF = 0; /* unset all internal GPIF flags */
 
 
REVCTL = bmDYN_OUT | bmENH_PKT; /* restore the setting */
SYNCDELAY;
 
#ifdef GECKO3MAIN
//EP2FIFOCFG &= ~bmOEP;
EP2FIFOCFG &= ~bmAUTOOUT; /* disable AutoOUT feature */
298,5 → 297,5
EA = 1; /* global interrupt enable */
 
 
print_info("gpif deactivated\n");
//print_info("gpif deactivated\n");
}
/GECKO3COM/gecko3com-fw/firmware/gpif-design/gecko3main_fifo_transfer.gpf Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/GECKO3COM/gecko3com-fw/firmware/gpif-design/gecko3main_gpif.c
24,8 → 24,8
// CTL 0 = RDYU CMOS
// CTL 1 = WRU CMOS
// CTL 2 = RDYU CMOS
// CTL 3 = intern CMOS
// CTL 4 = unused CMOS
// CTL 3 = X2U_ex CMOS
// CTL 4 = U2X_th CMOS
// CTL 5 = unused CMOS
// GPIF Rdy Inputs
60,9 → 60,9
// RDYU 0 0 0 0 0 0 0 0
// WRU 0 0 0 0 0 0 0 0
// RDYU 0 1 1 1 1 1 1 0
// intern 0 0 0 0 0 0 0 0
// X2U_ex 0 0 0 0 0 0 0 0
// U2X_th 0 0 0 0 0 0 0 0
// unused 0 0 0 0 0 0 0 0
// unused 0 0 0 0 0 0 0 0
//
// END DO NOT EDIT
// DO NOT EDIT ...
87,9 → 87,9
// RDYU 0 0 0 0 0 0 0 0
// WRU 0 1 1 1 1 1 1 0
// RDYU 0 0 0 1 1 1 1 0
// intern 0 0 0 0 0 0 0 0
// X2U_ex 0 0 0 0 0 0 0 0
// U2X_th 0 0 0 0 0 0 0 0
// unused 0 0 0 0 0 0 0 0
// unused 0 0 0 0 0 0 0 0
//
// END DO NOT EDIT
// DO NOT EDIT ...
114,9 → 114,9
// RDYU 0 0 0 0 0 0 0 0
// WRU 0 0 0 0 0 0 0 0
// RDYU 0 0 1 1 1 0 0 0
// intern 0 1 1 1 1 0 0 0
// X2U_ex 0 1 1 1 1 0 0 0
// U2X_th 0 0 0 0 0 0 0 0
// unused 0 0 0 0 0 0 0 0
// unused 0 0 0 0 0 0 0 0
//
// END DO NOT EDIT
// DO NOT EDIT ...
128,22 → 128,22
//
// AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
// DataMode NO Data NO Data NO Data Activate Activate Activate NO Data
// NextData SameData SameData SameData SameData SameData NextData SameData
// NextData SameData SameData SameData SameData NextData NextData SameData
// Int Trig No Int No Int No Int No Int No Int Trig Int No Int
// IF/Wait IF Wait 1 IF IF IF IF IF
// Term A WRX WRX RDYX FIFOFlag RDYX WRX
// LFunc AND AND AND AND AND AND
// Term B WRX WRX RDYX FIFOFlag RDYX WRX
// Branch1 ThenIdle Then 2 Then 4 Then 4 ThenIdle ThenIdle
// Branch0 Else 1 Else 3 Else 3 Else 5 ElseIdle ElseIdle
// Re-Exec No No No Yes No No
// IF/Wait IF Wait 1 IF Wait 1 IF IF IF
// Term A WRX WRX FIFOFlag RDYX WRX
// LFunc AND AND AND AND AND
// Term B WRX WRX FIFOFlag RDYX WRX
// Branch1 ThenIdle Then 2 Then 5 Then 5 ThenIdle
// Branch0 Else 1 Else 3 Else 4 ElseIdle ElseIdle
// Re-Exec No No Yes No No
// Sngl/CRC Default Default Default Default Default Default Default
// RDYU 0 0 0 0 0 0 0 0
// WRU 0 1 1 1 1 0 0 0
// RDYU 0 0 0 0 0 0 0 0
// intern 0 0 0 0 0 0 0 0
// X2U_ex 0 0 0 0 0 0 0 0
// U2X_th 0 0 0 0 0 0 0 0
// unused 0 0 0 0 0 0 0 0
// unused 0 0 0 0 0 0 0 0
//
// END DO NOT EDIT
174,10 → 174,10
/* Output*/ 0x00, 0x08, 0x0C, 0x0C, 0x0C, 0x00, 0x00, 0x00,
/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
// Wave 3
/* LenBr */ 0x39, 0x01, 0x13, 0x23, 0xA5, 0x3F, 0x3F, 0x07,
/* Opcode*/ 0x01, 0x00, 0x01, 0x03, 0x03, 0x17, 0x01, 0x00,
/* LenBr */ 0x39, 0x01, 0x13, 0x01, 0xAC, 0x2F, 0x3F, 0x07,
/* Opcode*/ 0x01, 0x00, 0x01, 0x02, 0x07, 0x17, 0x01, 0x00,
/* Output*/ 0x00, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00, 0x00,
/* LFun */ 0x00, 0x00, 0x00, 0x09, 0x36, 0x09, 0x00, 0x3F,
/* LFun */ 0x00, 0x00, 0x00, 0x00, 0x36, 0x09, 0x00, 0x3F,
};
// END DO NOT EDIT
187,7 → 187,7
/* Wave 0 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
/* Wave 1 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
/* Wave 2 FlowStates */ 0x83,0x36,0x04,0x00,0x03,0x23,0x03,0x02,0x00,
/* Wave 3 FlowStates */ 0x84,0x09,0x02,0x02,0x02,0x23,0x03,0x02,0x00,
/* Wave 3 FlowStates */ 0x84,0x09,0x02,0x02,0x04,0x23,0x03,0x02,0x00,
};
// END DO NOT EDIT
/GECKO3COM/gecko3com-fw/gecko3com.iic Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.