URL
https://opencores.org/ocsvn/gecko3/gecko3/trunk
Subversion Repositories gecko3
Compare Revisions
- This comparison shows the changes necessary to convert path
/gecko3/trunk
- from Rev 19 to Rev 20
- ↔ Reverse comparison
Rev 19 → Rev 20
/GECKO3COM/gecko3com-ip/AUTHORS
0,0 → 1,4
Andreas Habegger <hga3@bfh.ch> |
Christoph Zimmermann <zac1@bfh.ch> |
|
|
/GECKO3COM/gecko3com-ip/ChangeLog
0,0 → 1,63
------------------------------------------------------------------------ |
r18 | zac1 | 2010-01-15 11:36:10 +0100 (Fri, 15 Jan 2010) | 6 lines |
|
I achieved now stable OUT transfers (from the PC to the FPGA) with working throtling (when the FPGA consumes data slower than the host delivers). |
The basics needed for this are implemented in the FPGA like handshaking with the FX2 and clock domain transistion from the Interface clock to the user defined system clock. |
|
in the gpif_com_test.vhd is a message rom, containing a prepared answer message to generate an IN transfer. this is needed for the next step. |
|
|
------------------------------------------------------------------------ |
r14 | zac1 | 2009-12-18 14:59:32 +0100 (Fri, 18 Dec 2009) | 14 lines |
|
reorganising and renaming the stuff in these project. |
|
the core will get the name "GECKO3COM_" followed by the type "simple", "plb" or "opb" |
to follow the naming in the GECKO3 wiki and to show the IP core interface. |
|
duplicated fifo corecenerator files are merged together including a wrapper to easily supress synthesizer warnings |
from unavailable, unused and unconnected pins. |
|
the project is now organised in a way how the IP core and it's parts are beeing used. this means that the |
low-level gpif access module is instantiated by the higher level modules and not the other way around. |
this will make more sense when more parts of this IP core are finished (planning is finished, they have |
to be implemented and tested now). |
|
|
------------------------------------------------------------------------ |
r12 | zac1 | 2009-12-03 12:14:30 +0100 (Thu, 03 Dec 2009) | 4 lines |
|
this is the version 0.4 of the GECKO3com IP core. |
|
This is the last version from Andreas Habegger, the maintainer for this core is now Christoph Zimmermann |
|
------------------------------------------------------------------------ |
r11 | zac1 | 2009-12-03 12:03:25 +0100 (Thu, 03 Dec 2009) | 4 lines |
|
initial add of the version 0.3 of the GECKO3com IP core. originaly developped by Andreas Habegger. |
|
this commit is just for backup and to make the project progress visible because version 0.4 is also ready and will be commited in the next step. |
|
------------------------------------------------------------------------ |
|
|
# |
# Copyright 2008 MicroLab (Berne University of Applied Science) |
# |
# This file is part of GECKO3COM |
# |
# GECKO3COM; you can redistribute it and/or modify |
# it under the terms of the GNU General Public License as published by |
# the Free Software Foundation; either version 3, or (at your option) |
# any later version. |
# |
# GECKO3COM is distributed in the hope that it will be useful, |
# but WITHOUT ANY WARRANTY; without even the implied warranty of |
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
# GNU General Public License for more details. |
# |
# You should have received a copy of the GNU General Public License |
# along with GNU Radio; see the file COPYING. If not, write to |
# the Free Software Foundation, Inc., 51 Franklin Street, |
# Boston, MA 02110-1301, USA. |
# |
/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple_prototype.ise
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
/GECKO3COM/gecko3com-ip/core/gecko3com_test_chipscope.cdc
1,5 → 1,5
#ChipScope Core Inserter Project File Version 3.0 |
#Wed Jan 13 10:18:17 CET 2010 |
#Tue Jan 26 16:27:50 CET 2010 |
Project.device.designInputFile=/home/chrigi/bfh-work/GECKO3COM/gecko3com-ip/core/gpif_com_test_cs.ngc |
Project.device.designOutputFile=/home/chrigi/bfh-work/GECKO3COM/gecko3com-ip/core/gpif_com_test_cs.ngc |
Project.device.deviceFamily=6 |
15,7 → 15,7
Project.icon.triggerInPinName= |
Project.icon.triggerOutPinName= |
Project.unit.dimension=1 |
Project.unit<0>.clockChannel=i_SYSCLK_BUFGP |
Project.unit<0>.clockChannel=i_IFCLK_BUFGP |
Project.unit<0>.clockEdge=Rising |
Project.unit<0>.dataChannel<0>=o_WRX_OBUF |
Project.unit<0>.dataChannel<10>=GPIF_INTERFACE s_dbus_out<8> |
32,7 → 32,7
Project.unit<0>.dataChannel<20>=GPIF_INTERFACE o_TX |
Project.unit<0>.dataChannel<21>=GPIF_INTERFACE s_U2X_AM_FULL |
Project.unit<0>.dataChannel<22>=GPIF_INTERFACE s_U2X_WR_EN |
Project.unit<0>.dataChannel<23>=GPIF_INTERFACE s_U2X_FULL |
Project.unit<0>.dataChannel<23>=GPIF_INTERFACE s_X2U_EMPTY |
Project.unit<0>.dataChannel<24>=GPIF_INTERFACE o_RDYX |
Project.unit<0>.dataChannel<25>=s_RX_DATA<0> |
Project.unit<0>.dataChannel<26>=s_RX_DATA<1> |
54,8 → 54,10
Project.unit<0>.dataChannel<40>=s_RX_DATA<15> |
Project.unit<0>.dataChannel<41>=s_EMPTY |
Project.unit<0>.dataChannel<42>=i_WRU_IBUF |
Project.unit<0>.dataChannel<43>=o_WRX_OBUF |
Project.unit<0>.dataChannel<43>=GPIF_INTERFACE s_X2U_RD_EN |
Project.unit<0>.dataChannel<44>=s_RD_EN |
Project.unit<0>.dataChannel<45>=GPIF_INTERFACE i_EOM |
Project.unit<0>.dataChannel<46>=GPIF_INTERFACE s_X2U_FULL_IFCLK |
Project.unit<0>.dataChannel<4>=GPIF_INTERFACE s_dbus_out<2> |
Project.unit<0>.dataChannel<5>=GPIF_INTERFACE s_dbus_out<3> |
Project.unit<0>.dataChannel<6>=GPIF_INTERFACE s_dbus_out<4> |
64,7 → 66,7
Project.unit<0>.dataChannel<9>=GPIF_INTERFACE s_dbus_out<7> |
Project.unit<0>.dataDepth=512 |
Project.unit<0>.dataEqualsTrigger=false |
Project.unit<0>.dataPortWidth=45 |
Project.unit<0>.dataPortWidth=47 |
Project.unit<0>.enableGaps=false |
Project.unit<0>.enableStorageQualification=true |
Project.unit<0>.enableTimestamps=false |
74,6 → 76,9
Project.unit<0>.triggerChannel<0><1>=o_WRX_OBUF |
Project.unit<0>.triggerChannel<0><2>=o_RDYX_OBUF |
Project.unit<0>.triggerChannel<0><3>=i_RDYU_IBUF |
Project.unit<0>.triggerChannel<0><4>=GPIF_INTERFACE F_IN o_full |
Project.unit<0>.triggerChannel<0><5>=GPIF_INTERFACE F_OUT o_empty |
Project.unit<0>.triggerChannel<0><6>=GPIF_INTERFACE i_EOM |
Project.unit<0>.triggerConditionCountWidth=0 |
Project.unit<0>.triggerMatchCount<0>=1 |
Project.unit<0>.triggerMatchCountWidth<0><0>=0 |
80,7 → 85,7
Project.unit<0>.triggerMatchType<0><0>=1 |
Project.unit<0>.triggerPortCount=1 |
Project.unit<0>.triggerPortIsData<0>=true |
Project.unit<0>.triggerPortWidth<0>=4 |
Project.unit<0>.triggerPortWidth<0>=7 |
Project.unit<0>.triggerSequencerLevels=16 |
Project.unit<0>.triggerSequencerType=1 |
Project.unit<0>.type=ilapro |
/GECKO3COM/gecko3com-ip/core/gpif_com_fsm.vhd
50,23 → 50,25
|
entity gpif_com_fsm is |
port ( |
i_nReset : in std_logic; |
i_IFCLK : in std_logic; -- GPIF CLK (GPIF is Master and provides the clock) |
i_WRU : in std_logic; -- write from GPIF |
i_RDYU : in std_logic; -- GPIF is ready |
i_U2X_FULL : in std_logic; |
i_U2X_AM_FULL : in std_logic; -- signals for IN FIFO |
i_X2U_AM_EMPTY : in std_logic; |
i_X2U_EMPTY : in std_logic; -- signals for OUT FIFO |
o_bus_trans_dir : out std_logic; |
o_U2X_WR_EN : out std_logic; -- signals for IN FIFO |
o_X2U_RD_EN : out std_logic; -- signals for OUT FIFO |
o_FIFOrst : out std_logic; |
o_WRX : out std_logic; -- To write to GPIF |
o_RDYX : out std_logic; -- Core is ready |
o_ABORT : out std_logic; -- abort condition detected. we have to flush the data |
o_RX : out std_logic; |
o_TX : out std_logic -- |
i_nReset : in std_logic; |
i_IFCLK : in std_logic; -- GPIF CLK (GPIF is Master and provides the clock) |
i_WRU : in std_logic; -- write from GPIF |
i_RDYU : in std_logic; -- GPIF is ready |
i_EOM : in std_logic; -- all data for X2U transfer is in FIFO |
i_U2X_FULL : in std_logic; |
i_U2X_AM_FULL : in std_logic; -- signals for IN FIFO |
i_X2U_FULL_IFCLK : in std_logic; |
i_X2U_AM_EMPTY : in std_logic; |
i_X2U_EMPTY : in std_logic; -- signals for OUT FIFO |
o_bus_trans_dir : out std_logic; |
o_U2X_WR_EN : out std_logic; -- signals for IN FIFO |
o_X2U_RD_EN : out std_logic; -- signals for OUT FIFO |
o_FIFOrst : out std_logic; |
o_WRX : out std_logic; -- To write to GPIF |
o_RDYX : out std_logic; -- Core is ready |
o_ABORT : out std_logic; -- abort condition detected. we have to flush the data |
o_RX : out std_logic; |
o_TX : out std_logic -- |
); |
|
end gpif_com_fsm; |
90,8 → 92,10
|
type t_fsmState is (rst, idle, -- controll states |
inRQ, inACK, inWait, inTrans, inThrot, |
inThrotBreak,inThrotBreak2, inThrotEnd, endInTrans, -- in com states |
outRQ, outTrans, outWait, endOutTrans); -- out com states |
inThrotBreak,inThrotBreak2, inThrotEnd, |
endInTrans, -- in com states |
outRQ, outTrans, outACK, outUSBwait, outFIFOwait, |
endOutTrans); -- out com states |
|
|
|
99,6 → 103,7
-- XST specific synthesize attributes |
attribute safe_recovery_state of pr_state : signal is "idle"; |
attribute safe_implementation of pr_state : signal is "yes"; |
|
|
|
|
142,8 → 147,8
|
|
-- comb logic |
transaction : process(pr_state, i_WRU, i_RDYU, i_U2X_FULL, |
i_U2X_AM_FULL, i_X2U_EMPTY) |
transaction : process(pr_state, i_WRU, i_RDYU, i_U2X_FULL, i_U2X_AM_FULL, |
i_X2U_EMPTY, i_X2U_FULL_IFCLK, i_EOM) |
begin -- process transaction |
|
-- default signal values to avoid latches: |
171,7 → 176,6
s_ABORT <= '1'; |
o_RX <= '0'; |
o_TX <= '0'; |
|
s_bus_trans_dir <= readFromGPIF; |
|
-- state decisions |
195,12 → 199,14
nx_state <= rst; |
elsif i_WRU = '1' and i_RDYU = '0' then |
nx_state <= inRQ; |
elsif i_WRU = '0' and i_X2U_EMPTY = '0' then |
elsif i_WRU = '0' and |
(i_X2U_FULL_IFCLK = '1' or i_EOM = '1') and i_X2U_EMPTY = '0' then |
nx_state <= outRQ; |
else |
nx_state <= idle; |
end if; |
|
----------------------------------------------------------------------- |
-- in trans |
when inRQ => |
-- output signal values: |
257,7 → 263,7
nx_state <= rst; |
elsif i_WRU = '0' then |
nx_state <= endInTrans; |
elsif i_U2X_FULL = '1' then |
elsif i_U2X_AM_FULL = '1' then |
nx_state <= inThrot; |
else |
nx_state <= inTrans; |
273,9 → 279,9
-- state decisions |
if i_WRU = '1' and i_RDYU = '1' then |
nx_state <= rst; |
elsif i_U2X_FULL = '0' then |
elsif i_U2X_AM_FULL = '0' then |
nx_state <= inThrotBreak; |
--nx_state <= inACK; |
--nx_state <= inThrotEnd; |
elsif i_WRU = '0' then |
nx_state <= endInTrans; |
else |
329,12 → 335,13
-- state decisions |
nx_state <= idle; |
|
|
----------------------------------------------------------------------- |
-- out trans |
when outRQ => |
-- output signal values: |
s_WRX <= '1'; |
s_RDYX <= '0'; |
s_WRX <= '1'; |
s_RDYX <= '0'; |
s_X2U_RD_EN <= '0'; |
|
-- state decisions |
if i_WRU = '1' and i_RDYU = '1' then |
341,36 → 348,48
nx_state <= rst; |
elsif i_WRU = '1' and i_RDYU = '0' then |
nx_state <= inRQ; |
elsif i_WRU = '0' and i_RDYU = '0' then -- vervollständigt, wenn ez-usb noch beschäfigt mit altem transfer |
--s_X2U_RD_EN <= '1'; |
nx_state <= outTrans; |
-- s_bus_trans_dir <= writeToGPIF; |
else |
nx_state <= outRQ; |
nx_state <= outACK; |
end if; |
|
when outACK => |
-- output signal values: |
s_WRX <= '1'; |
s_RDYX <= '0'; |
s_X2U_RD_EN <= '1'; |
o_TX <= '1'; |
|
-- state decisions |
if i_WRU = '1' and i_RDYU = '1' then |
nx_state <= rst; |
elsif i_WRU = '0' and i_RDYU = '1' then |
nx_state <= outTrans; |
else |
nx_state <= outUSBwait; |
end if; |
|
when outTrans => |
-- output signal values: |
s_WRX <= '1'; |
s_RDYX <= '0'; |
s_X2U_RD_EN <= '1'; |
o_TX <= '1'; |
s_bus_trans_dir <= writeToGPIF; |
o_TX <= '1'; |
|
-- state decisions |
if i_WRU = '1' and i_RDYU = '1' then |
nx_state <= rst; |
elsif i_X2U_EMPTY = '1' then |
elsif i_X2U_EMPTY = '1' and i_EOM = '1' then |
nx_state <= endOutTrans; |
elsif i_X2U_EMPTY = '1' and i_EOM = '0' then |
nx_state <= outFIFOwait; |
elsif i_WRU = '0' and i_RDYU = '1' then |
nx_state <= outTrans; |
else |
--s_X2U_RD_EN <= '0'; -- to realise a wait case |
nx_state <= outWait; |
nx_state <= outUSBwait; |
end if; |
|
when outWait => |
when outUSBwait => |
-- output signal values: |
s_WRX <= '1'; |
s_RDYX <= '0'; |
384,18 → 403,41
elsif i_WRU = '0' and i_RDYU = '1' then |
nx_state <= outTrans; |
else |
nx_state <= outWait; |
nx_state <= outUSBwait; |
end if; |
|
when outFIFOwait => |
-- output signal values: |
s_WRX <= '1'; |
s_RDYX <= '1'; |
s_X2U_RD_EN <= '0'; |
o_TX <= '1'; |
s_bus_trans_dir <= writeToGPIF; |
|
-- state decisions |
if i_WRU = '1' and i_RDYU = '1' then |
nx_state <= rst; |
elsif i_X2U_EMPTY = '1' and i_EOM = '1' then |
nx_state <= endOutTrans; |
elsif i_X2U_EMPTY = '0' and i_EOM = '0' then |
nx_state <= outTrans; |
else |
nx_state <= outFIFOwait; |
end if; |
|
when endOutTrans => |
-- output signal values: |
s_RDYX <= '0'; |
s_WRX <= '1'; -- nötig um letzte 16bit an ez-usb zu schreiben |
s_X2U_RD_EN <= '1'; -- nötig da empyte flag schon beim ersten fifo zugriff auftaucht, zweite 16bit müssen noch gelesen werden |
s_WRX <= '0'; |
s_X2U_RD_EN <= '0'; |
s_bus_trans_dir <= writeToGPIF; |
|
-- state decisions |
nx_state <= idle; |
if i_RDYU = '0' then |
nx_state <= idle; |
else |
nx_state <= endOutTrans; |
end if; |
|
-- error case |
when others => |
/GECKO3COM/gecko3com-ip/core/chipscope-analyzer.cpj
1,5 → 1,5
#ChipScope Pro Analyzer Project File, Version 3.0 |
#Sat Jan 16 00:54:10 CET 2010 |
#Tue Jan 26 21:37:40 CET 2010 |
deviceChain.deviceName0=XC3S1500 |
deviceChain.iRLength0=6 |
deviceChain.name0=MyDevice0 |
17,24 → 17,24
mdiType1=0 |
mdiUnit0=0 |
mdiUnit1=0 |
navigatorHeight=0.18635437881873726 |
navigatorHeight=0.3289205702647658 |
navigatorHeightLast=0.18635437881873726 |
navigatorWidth=0.22322775263951736 |
navigatorWidthLast=0.14630467571644043 |
navigatorWidth=0.2030178326474623 |
navigatorWidthLast=0.13305898491083676 |
unit.-1.-1.username= |
unit.0.0.0.HEIGHT0=0.460177 |
unit.0.0.0.TriggerRow0=1 |
unit.0.0.0.TriggerRow1=1 |
unit.0.0.0.TriggerRow2=1 |
unit.0.0.0.WIDTH0=1.0574257 |
unit.0.0.0.WIDTH0=0.9352014 |
unit.0.0.0.X0=0.0 |
unit.0.0.0.Y0=0.0044247787 |
unit.0.0.1.HEIGHT1=0.6902655 |
unit.0.0.1.WIDTH1=1.0574257 |
unit.0.0.1.X1=0.0 |
unit.0.0.1.Y1=0.3038348 |
unit.0.0.MFBitsA0=1XX0 |
unit.0.0.MFBitsB0=0000 |
unit.0.0.1.HEIGHT1=0.82300884 |
unit.0.0.1.WIDTH1=0.9352014 |
unit.0.0.1.X1=0.030647986 |
unit.0.0.1.Y1=0.15781711 |
unit.0.0.MFBitsA0=X1XXXXX |
unit.0.0.MFBitsB0=0000000 |
unit.0.0.MFCompareA0=0 |
unit.0.0.MFCompareB0=999 |
unit.0.0.MFCount=1 |
87,7 → 87,7
unit.0.0.port.-1.b.1.unsignedScaleFactor=1.0 |
unit.0.0.port.-1.b.1.visible=1 |
unit.0.0.port.-1.buscount=2 |
unit.0.0.port.-1.channelcount=45 |
unit.0.0.port.-1.channelcount=47 |
unit.0.0.port.-1.s.0.alias= |
unit.0.0.port.-1.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] |
unit.0.0.port.-1.s.0.name=/o_WRX_OBUF |
170,7 → 170,7
unit.0.0.port.-1.s.22.visible=1 |
unit.0.0.port.-1.s.23.alias= |
unit.0.0.port.-1.s.23.color=java.awt.Color[r\=0,g\=0,b\=124] |
unit.0.0.port.-1.s.23.name=/GPIF_INTERFACE/s_U2X_FULL |
unit.0.0.port.-1.s.23.name=/GPIF_INTERFACE/s_X2U_EMPTY |
unit.0.0.port.-1.s.23.orderindex=-1 |
unit.0.0.port.-1.s.23.visible=1 |
unit.0.0.port.-1.s.24.alias= |
280,7 → 280,7
unit.0.0.port.-1.s.42.visible=1 |
unit.0.0.port.-1.s.43.alias= |
unit.0.0.port.-1.s.43.color=java.awt.Color[r\=0,g\=0,b\=124] |
unit.0.0.port.-1.s.43.name=DataPort[43] |
unit.0.0.port.-1.s.43.name=/GPIF_INTERFACE/s_X2U_RD_EN |
unit.0.0.port.-1.s.43.orderindex=-1 |
unit.0.0.port.-1.s.43.visible=1 |
unit.0.0.port.-1.s.44.alias= |
288,6 → 288,16
unit.0.0.port.-1.s.44.name=/s_RD_EN |
unit.0.0.port.-1.s.44.orderindex=-1 |
unit.0.0.port.-1.s.44.visible=1 |
unit.0.0.port.-1.s.45.alias= |
unit.0.0.port.-1.s.45.color=java.awt.Color[r\=0,g\=0,b\=124] |
unit.0.0.port.-1.s.45.name=/GPIF_INTERFACE/i_EOM |
unit.0.0.port.-1.s.45.orderindex=-1 |
unit.0.0.port.-1.s.45.visible=1 |
unit.0.0.port.-1.s.46.alias= |
unit.0.0.port.-1.s.46.color=java.awt.Color[r\=0,g\=0,b\=124] |
unit.0.0.port.-1.s.46.name=/GPIF_INTERFACE/s_X2U_FULL_IFCLK |
unit.0.0.port.-1.s.46.orderindex=-1 |
unit.0.0.port.-1.s.46.visible=1 |
unit.0.0.port.-1.s.5.alias= |
unit.0.0.port.-1.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] |
unit.0.0.port.-1.s.5.name=/GPIF_INTERFACE/s_dbus_out<3> |
314,7 → 324,7
unit.0.0.port.-1.s.9.orderindex=-1 |
unit.0.0.port.-1.s.9.visible=0 |
unit.0.0.port.0.b.0.alias= |
unit.0.0.port.0.b.0.channellist=0 1 2 3 |
unit.0.0.port.0.b.0.channellist=0 1 2 3 4 5 6 |
unit.0.0.port.0.b.0.color=java.awt.Color[r\=0,g\=0,b\=124] |
unit.0.0.port.0.b.0.name=TriggerPort0 |
unit.0.0.port.0.b.0.orderindex=-1 |
327,7 → 337,7
unit.0.0.port.0.b.0.unsignedScaleFactor=1.0 |
unit.0.0.port.0.b.0.visible=1 |
unit.0.0.port.0.buscount=1 |
unit.0.0.port.0.channelcount=4 |
unit.0.0.port.0.channelcount=7 |
unit.0.0.port.0.s.0.alias= |
unit.0.0.port.0.s.0.color=java.awt.Color[r\=0,g\=0,b\=124] |
unit.0.0.port.0.s.0.name=/i_WRU_IBUF |
348,6 → 358,21
unit.0.0.port.0.s.3.name=/i_RDYU_IBUF |
unit.0.0.port.0.s.3.orderindex=-1 |
unit.0.0.port.0.s.3.visible=1 |
unit.0.0.port.0.s.4.alias= |
unit.0.0.port.0.s.4.color=java.awt.Color[r\=0,g\=0,b\=124] |
unit.0.0.port.0.s.4.name=/GPIF_INTERFACE/F_IN/o_full |
unit.0.0.port.0.s.4.orderindex=-1 |
unit.0.0.port.0.s.4.visible=1 |
unit.0.0.port.0.s.5.alias= |
unit.0.0.port.0.s.5.color=java.awt.Color[r\=0,g\=0,b\=124] |
unit.0.0.port.0.s.5.name=/GPIF_INTERFACE/F_OUT/o_empty |
unit.0.0.port.0.s.5.orderindex=-1 |
unit.0.0.port.0.s.5.visible=1 |
unit.0.0.port.0.s.6.alias= |
unit.0.0.port.0.s.6.color=java.awt.Color[r\=0,g\=0,b\=124] |
unit.0.0.port.0.s.6.name=/GPIF_INTERFACE/i_EOM |
unit.0.0.port.0.s.6.orderindex=-1 |
unit.0.0.port.0.s.6.visible=1 |
unit.0.0.portcount=1 |
unit.0.0.samplesPerTrigger=1 |
unit.0.0.triggerCapture=1 |
357,30 → 382,30
unit.0.0.triggerWindowDepth=512 |
unit.0.0.triggerWindowTS=0 |
unit.0.0.username=MyILA0 |
unit.0.0.waveform.count=15 |
unit.0.0.waveform.count=17 |
unit.0.0.waveform.posn.0.channel=0 |
unit.0.0.waveform.posn.0.name=/o_WRX_OBUF |
unit.0.0.waveform.posn.0.type=signal |
unit.0.0.waveform.posn.1.channel=0 |
unit.0.0.waveform.posn.1.name=/o_WRX_OBUF |
unit.0.0.waveform.posn.1.channel=1 |
unit.0.0.waveform.posn.1.name=/i_RDYU_IBUF |
unit.0.0.waveform.posn.1.type=signal |
unit.0.0.waveform.posn.10.channel=22 |
unit.0.0.waveform.posn.10.name=/GPIF_INTERFACE/s_U2X_WR_EN |
unit.0.0.waveform.posn.10.channel=42 |
unit.0.0.waveform.posn.10.name=/i_WRU_IBUF |
unit.0.0.waveform.posn.10.type=signal |
unit.0.0.waveform.posn.11.channel=23 |
unit.0.0.waveform.posn.11.name=/GPIF_INTERFACE/s_U2X_FULL |
unit.0.0.waveform.posn.11.channel=43 |
unit.0.0.waveform.posn.11.name=/GPIF_INTERFACE/s_X2U_RD_EN |
unit.0.0.waveform.posn.11.radix=1 |
unit.0.0.waveform.posn.11.type=signal |
unit.0.0.waveform.posn.12.channel=2147483646 |
unit.0.0.waveform.posn.12.name=/s_RX_DATA |
unit.0.0.waveform.posn.12.channel=44 |
unit.0.0.waveform.posn.12.name=/s_RD_EN |
unit.0.0.waveform.posn.12.radix=1 |
unit.0.0.waveform.posn.12.type=bus |
unit.0.0.waveform.posn.13.channel=41 |
unit.0.0.waveform.posn.13.name=/s_EMPTY |
unit.0.0.waveform.posn.12.type=signal |
unit.0.0.waveform.posn.13.channel=45 |
unit.0.0.waveform.posn.13.name=/GPIF_INTERFACE/i_EOM |
unit.0.0.waveform.posn.13.radix=1 |
unit.0.0.waveform.posn.13.type=signal |
unit.0.0.waveform.posn.14.channel=44 |
unit.0.0.waveform.posn.14.name=/s_RD_EN |
unit.0.0.waveform.posn.14.channel=46 |
unit.0.0.waveform.posn.14.name=/GPIF_INTERFACE/s_X2U_FULL_IFCLK |
unit.0.0.waveform.posn.14.radix=1 |
unit.0.0.waveform.posn.14.type=signal |
unit.0.0.waveform.posn.15.channel=2147483646 |
387,24 → 412,24
unit.0.0.waveform.posn.15.name=/GPIF_INTERFACE/s_dbus_out |
unit.0.0.waveform.posn.15.radix=1 |
unit.0.0.waveform.posn.15.type=bus |
unit.0.0.waveform.posn.16.channel=44 |
unit.0.0.waveform.posn.16.name=/s_RD_EN |
unit.0.0.waveform.posn.16.channel=2147483646 |
unit.0.0.waveform.posn.16.name=/s_RX_DATA |
unit.0.0.waveform.posn.16.radix=1 |
unit.0.0.waveform.posn.16.type=signal |
unit.0.0.waveform.posn.17.channel=44 |
unit.0.0.waveform.posn.17.name=/s_RD_EN |
unit.0.0.waveform.posn.16.type=bus |
unit.0.0.waveform.posn.17.channel=2147483646 |
unit.0.0.waveform.posn.17.name=/s_RX_DATA |
unit.0.0.waveform.posn.17.radix=1 |
unit.0.0.waveform.posn.17.type=signal |
unit.0.0.waveform.posn.18.channel=44 |
unit.0.0.waveform.posn.18.name=/s_RD_EN |
unit.0.0.waveform.posn.17.type=bus |
unit.0.0.waveform.posn.18.channel=46 |
unit.0.0.waveform.posn.18.name=/GPIF_INTERFACE/s_X2U_FULL_IFCLK |
unit.0.0.waveform.posn.18.radix=1 |
unit.0.0.waveform.posn.18.type=signal |
unit.0.0.waveform.posn.19.channel=44 |
unit.0.0.waveform.posn.19.name=/s_RD_EN |
unit.0.0.waveform.posn.19.channel=46 |
unit.0.0.waveform.posn.19.name=/GPIF_INTERFACE/s_X2U_FULL_IFCLK |
unit.0.0.waveform.posn.19.radix=1 |
unit.0.0.waveform.posn.19.type=signal |
unit.0.0.waveform.posn.2.channel=24 |
unit.0.0.waveform.posn.2.name=/GPIF_INTERFACE/o_RDYX |
unit.0.0.waveform.posn.2.channel=18 |
unit.0.0.waveform.posn.2.name=/GPIF_INTERFACE/s_dbus_trans_dir |
unit.0.0.waveform.posn.2.type=signal |
unit.0.0.waveform.posn.20.channel=44 |
unit.0.0.waveform.posn.20.name=/s_RD_EN |
446,8 → 471,8
unit.0.0.waveform.posn.29.name=/s_RD_EN |
unit.0.0.waveform.posn.29.radix=1 |
unit.0.0.waveform.posn.29.type=signal |
unit.0.0.waveform.posn.3.channel=1 |
unit.0.0.waveform.posn.3.name=/i_RDYU_IBUF |
unit.0.0.waveform.posn.3.channel=19 |
unit.0.0.waveform.posn.3.name=/GPIF_INTERFACE/o_RX |
unit.0.0.waveform.posn.3.type=signal |
unit.0.0.waveform.posn.30.channel=44 |
unit.0.0.waveform.posn.30.name=/s_RD_EN |
489,8 → 514,9
unit.0.0.waveform.posn.39.name=/s_RD_EN |
unit.0.0.waveform.posn.39.radix=1 |
unit.0.0.waveform.posn.39.type=signal |
unit.0.0.waveform.posn.4.channel=42 |
unit.0.0.waveform.posn.4.name=/i_WRU_IBUF |
unit.0.0.waveform.posn.4.channel=20 |
unit.0.0.waveform.posn.4.name=/GPIF_INTERFACE/o_TX |
unit.0.0.waveform.posn.4.radix=1 |
unit.0.0.waveform.posn.4.type=signal |
unit.0.0.waveform.posn.40.channel=44 |
unit.0.0.waveform.posn.40.name=/s_RD_EN |
512,19 → 538,19
unit.0.0.waveform.posn.45.channel=44 |
unit.0.0.waveform.posn.45.name=/s_RD_EN |
unit.0.0.waveform.posn.45.type=signal |
unit.0.0.waveform.posn.5.channel=2147483646 |
unit.0.0.waveform.posn.5.name=/GPIF_INTERFACE/s_dbus_out |
unit.0.0.waveform.posn.5.channel=21 |
unit.0.0.waveform.posn.5.name=/GPIF_INTERFACE/s_U2X_AM_FULL |
unit.0.0.waveform.posn.5.radix=1 |
unit.0.0.waveform.posn.5.type=bus |
unit.0.0.waveform.posn.6.channel=18 |
unit.0.0.waveform.posn.6.name=/GPIF_INTERFACE/s_dbus_trans_dir |
unit.0.0.waveform.posn.5.type=signal |
unit.0.0.waveform.posn.6.channel=22 |
unit.0.0.waveform.posn.6.name=/GPIF_INTERFACE/s_U2X_WR_EN |
unit.0.0.waveform.posn.6.type=signal |
unit.0.0.waveform.posn.7.channel=19 |
unit.0.0.waveform.posn.7.name=/GPIF_INTERFACE/o_RX |
unit.0.0.waveform.posn.7.channel=23 |
unit.0.0.waveform.posn.7.name=/GPIF_INTERFACE/s_X2U_EMPTY |
unit.0.0.waveform.posn.7.type=signal |
unit.0.0.waveform.posn.8.channel=20 |
unit.0.0.waveform.posn.8.name=/GPIF_INTERFACE/o_TX |
unit.0.0.waveform.posn.8.channel=24 |
unit.0.0.waveform.posn.8.name=/GPIF_INTERFACE/o_RDYX |
unit.0.0.waveform.posn.8.type=signal |
unit.0.0.waveform.posn.9.channel=21 |
unit.0.0.waveform.posn.9.name=/GPIF_INTERFACE/s_U2X_AM_FULL |
unit.0.0.waveform.posn.9.channel=41 |
unit.0.0.waveform.posn.9.name=/s_EMPTY |
unit.0.0.waveform.posn.9.type=signal |
/GECKO3COM/gecko3com-ip/core/message_rom.vhd
15,9 → 15,10
subtype ROM_WORD is std_logic_vector(15 downto 0); |
type ROM_TABLE is array(0 to 31) of ROM_WORD; |
signal ROM: ROM_TABLE := ROM_TABLE'( |
"0000000000000000", -- 0x0000 |
"0000001000000010", -- 0x0000 |
"0000000011111101", -- 0x0002 |
"0000000000100000", -- 0x0004 |
"0000000000100001", -- 0x0004 |
"0000000000000000", -- 0x0006 |
"0000000000000001", -- 0x0008 |
"0000000000000000", -- 0x000A |
45,8 → 46,7
"----------------", -- 0x0036 |
"----------------", -- 0x0038 |
"----------------", -- 0x003A |
"----------------", -- 0x003C |
"----------------"); -- 0x003E |
"----------------"); -- 0x003C |
begin |
D <= ROM(to_integer(unsigned(A))); |
end; |
/GECKO3COM/gecko3com-ip/core/gpif_com_test.vhd
79,7 → 79,7
----------------------------------------------------------------------------- |
signal s_EMPTY, s_FULL : std_logic; |
signal s_RX_DATA : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0); |
signal s_RD_EN, s_WR_EN : std_logic; |
signal s_RD_EN, s_WR_EN, s_EOM : std_logic; |
signal s_TX_DATA : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0); |
|
signal s_ABORT, s_ABORT_TMP : std_logic; |
104,6 → 104,7
i_RD_EN : in std_logic; |
o_EMPTY : out std_logic; |
o_RX_DATA : out std_logic_vector(SIZE_DBUS_GPIF-1 downto 0); |
i_EOM : in std_logic; |
i_WR_EN : in std_logic; |
o_FULL : out std_logic; |
i_TX_DATA : in std_logic_vector(SIZE_DBUS_GPIF-1 downto 0); |
133,6 → 134,7
i_RD_EN => s_RD_EN, |
o_EMPTY => s_EMPTY, |
o_RX_DATA => s_RX_DATA, |
i_EOM => s_EOM, |
i_WR_EN => s_WR_EN, |
o_FULL => s_FULL, |
i_TX_DATA => s_TX_DATA, |
166,7 → 168,7
v_rx_throtle_count := (others => '0'); |
s_RD_EN <= '0'; |
elsif i_SYSCLK = '1' and i_SYSCLK'event then |
if v_rx_throtle_count >= 2 then |
if v_rx_throtle_count >= 10 then |
s_RD_EN <= '1'; |
v_rx_throtle_count := (others => '0'); |
else |
220,16 → 222,19
begin |
if i_nReset = '0' then |
s_rom_adress <= (others => '0'); |
--s_WR_EN <= '1'; |
s_WR_EN <= '0'; |
--s_WR_EN <= '0'; |
elsif i_SYSCLK = '1' and i_SYSCLK'event then |
if s_rom_adress = 24 then |
if s_rom_adress >= 24 then |
s_rom_adress <= s_rom_adress; |
s_WR_EN <= '0'; |
s_EOM <= '1'; |
else |
s_rom_adress <= s_rom_adress + 1; |
--s_WR_EN <= '1'; |
s_WR_EN <= '0'; |
if s_FULL ='0' then |
s_rom_adress <= s_rom_adress + 1; |
s_WR_EN <= '1'; |
end if; |
s_EOM <= '0'; |
end if; |
end if; |
end process rom_adress_counter; |
/GECKO3COM/gecko3com-ip/core/gpif_com.vhd
59,6 → 59,7
i_RD_EN : in std_logic; -- read enable |
o_EMPTY : out std_logic; -- receive fifo empty |
o_RX_DATA : out std_logic_vector(SIZE_DBUS_GPIF-1 downto 0); -- receive data |
i_EOM : in std_logic; |
i_WR_EN : in std_logic; -- write enable |
o_FULL : out std_logic; -- send fifo full |
i_TX_DATA : in std_logic_vector(SIZE_DBUS_GPIF-1 downto 0); -- send data |
83,6 → 84,8
signal s_ABORT_FSM, s_ABORT_TMP : std_logic; |
signal s_RX_FSM, s_RX_TMP : std_logic; |
signal s_TX_FSM, s_TX_TMP : std_logic; |
signal s_EOM, s_EOM_TMP : std_logic; -- End of message |
signal s_X2U_FULL_IFCLK, s_X2U_FULL_TMP : std_logic; |
|
-- USB to Xilinx (U2X) |
signal s_U2X_WR_EN, |
118,24 → 121,25
-- FSM GPIF |
component gpif_com_fsm |
port ( |
i_nReset, |
i_IFCLK, -- GPIF CLK (is Master) |
i_WRU, -- write from GPIF |
i_RDYU : in std_logic; -- GPIF is ready |
i_U2X_FULL, |
i_U2X_AM_FULL, -- signals for IN FIFO |
i_X2U_AM_EMPTY, |
i_X2U_EMPTY : in std_logic; -- signals for OUT FIFO |
o_bus_trans_dir : out std_logic; |
o_U2X_WR_EN, -- signals for IN FIFO |
o_X2U_RD_EN, -- signals for OUT FIFO |
o_FIFOrst, |
o_WRX, -- To write to GPIF |
o_RDYX : out std_logic; -- Core is ready |
o_ABORT : out std_logic; -- abort condition detected. we have to flush the data |
o_RX, |
o_TX : out std_logic -- |
); |
i_nReset : in std_logic; |
i_IFCLK : in std_logic; |
i_WRU : in std_logic; |
i_RDYU : in std_logic; |
i_EOM : in std_logic; |
i_U2X_FULL : in std_logic; |
i_U2X_AM_FULL : in std_logic; |
i_X2U_FULL_IFCLK : in std_logic; |
i_X2U_AM_EMPTY : in std_logic; |
i_X2U_EMPTY : in std_logic; |
o_bus_trans_dir : out std_logic; |
o_U2X_WR_EN : out std_logic; |
o_X2U_RD_EN : out std_logic; |
o_FIFOrst : out std_logic; |
o_WRX : out std_logic; |
o_RDYX : out std_logic; |
o_ABORT : out std_logic; |
o_RX : out std_logic; |
o_TX : out std_logic); |
end component; |
|
-- FIFO dualclock to cross the clock domain between the GPIF and the FPGA |
195,23 → 199,25
|
FSM_GPIF : gpif_com_fsm |
port map ( |
i_nReset => i_nReset, |
i_IFCLK => i_IFCLK, |
i_WRU => i_WRU, |
i_RDYU => i_RDYU, |
i_U2X_FULL => s_U2X_FULL, |
i_U2X_AM_FULL => s_U2X_AM_FULL, |
i_X2U_AM_EMPTY => s_X2U_AM_EMPTY, |
i_X2U_EMPTY => s_X2U_EMPTY, |
o_U2X_WR_EN => s_U2X_WR_EN, |
o_X2U_RD_EN => s_X2U_RD_EN, |
o_FIFOrst => s_FIFOrst, |
o_bus_trans_dir => s_dbus_trans_dir, |
o_WRX => s_WRX, |
o_RDYX => s_RDYX, |
o_ABORT => s_ABORT_FSM, |
o_RX => s_RX_FSM, |
o_TX => s_TX_FSM |
i_nReset => i_nReset, |
i_IFCLK => i_IFCLK, |
i_WRU => i_WRU, |
i_RDYU => i_RDYU, |
i_EOM => s_EOM, |
i_U2X_FULL => s_U2X_FULL, |
i_U2X_AM_FULL => s_U2X_AM_FULL, |
i_X2U_FULL_IFCLK => s_X2U_FULL_IFCLK, |
i_X2U_AM_EMPTY => s_X2U_AM_EMPTY, |
i_X2U_EMPTY => s_X2U_EMPTY, |
o_U2X_WR_EN => s_U2X_WR_EN, |
o_X2U_RD_EN => s_X2U_RD_EN, |
o_FIFOrst => s_FIFOrst, |
o_bus_trans_dir => s_dbus_trans_dir, |
o_WRX => s_WRX, |
o_RDYX => s_RDYX, |
o_ABORT => s_ABORT_FSM, |
o_RX => s_RX_FSM, |
o_TX => s_TX_FSM |
); |
|
|
247,7 → 253,21
end if; |
end process double_buf_sig; |
|
-- Double buffer the ABORT, RX and TX signal to avoid metastability |
double_buf_ifclk : process (i_IFCLK, i_nReset) |
begin |
if i_nReset = '0' then |
s_X2U_FULL_TMP <= '0'; |
s_X2U_FULL_IFCLK <= '0'; |
elsif rising_edge(i_IFCLK) then |
s_EOM <= s_EOM_TMP; |
s_EOM_TMP <= i_EOM; |
s_X2U_FULL_IFCLK <= s_X2U_FULL_TMP; |
s_X2U_FULL_TMP <= s_X2U_FULL; |
end if; |
end process double_buf_ifclk; |
|
|
----------------------------------------------------------------------------- |
-- Data bus access |
----------------------------------------------------------------------------- |
/GECKO3COM/gecko3com-ip/COPYING
0,0 → 1,674
GNU GENERAL PUBLIC LICENSE |
Version 3, 29 June 2007 |
|
Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/> |
Everyone is permitted to copy and distribute verbatim copies |
of this license document, but changing it is not allowed. |
|
Preamble |
|
The GNU General Public License is a free, copyleft license for |
software and other kinds of works. |
|
The licenses for most software and other practical works are designed |
to take away your freedom to share and change the works. By contrast, |
the GNU General Public License is intended to guarantee your freedom to |
share and change all versions of a program--to make sure it remains free |
software for all its users. We, the Free Software Foundation, use the |
GNU General Public License for most of our software; it applies also to |
any other work released this way by its authors. You can apply it to |
your programs, too. |
|
When we speak of free software, we are referring to freedom, not |
price. Our General Public Licenses are designed to make sure that you |
have the freedom to distribute copies of free software (and charge for |
them if you wish), that you receive source code or can get it if you |
want it, that you can change the software or use pieces of it in new |
free programs, and that you know you can do these things. |
|
To protect your rights, we need to prevent others from denying you |
these rights or asking you to surrender the rights. Therefore, you have |
certain responsibilities if you distribute copies of the software, or if |
you modify it: responsibilities to respect the freedom of others. |
|
For example, if you distribute copies of such a program, whether |
gratis or for a fee, you must pass on to the recipients the same |
freedoms that you received. You must make sure that they, too, receive |
or can get the source code. And you must show them these terms so they |
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|
Developers that use the GNU GPL protect your rights with two steps: |
(1) assert copyright on the software, and (2) offer you this License |
giving you legal permission to copy, distribute and/or modify it. |
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For the developers' and authors' protection, the GPL clearly explains |
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Some devices are designed to deny users access to install or run |
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Finally, every program is threatened constantly by software patents. |
States should not allow patents to restrict development and use of |
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avoid the special danger that patents applied to a free program could |
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patents cannot be used to render the program non-free. |
|
The precise terms and conditions for copying, distribution and |
modification follow. |
|
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"This License" refers to version 3 of the GNU General Public License. |
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"Copyright" also means copyright-like laws that apply to other kinds of |
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<program> Copyright (C) <year> <name of author> |
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This is free software, and you are welcome to redistribute it |
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/GECKO3COM/gecko3com-ip/README
0,0 → 1,8
# |
# README -- the short version |
# |
|
|
|
For more information, read the source code documentation or the manual in the GECKO3 wiki: |
http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start |
/GECKO3COM/gecko3com-fw/firmware/include/gecko3com_regs.h
114,6 → 114,17
#define bmXILINX_BUSY bmBIT1 /**< bitmask to access busy */ |
|
|
/* define pinning of the GPIF interface RDY signals |
accessible in the GPIFREADYSTAT register */ |
#define bmWRX bmBIT0 /**< GPIFREADYSTAT bitmask to access Write Request Xilinx */ |
#define bmRDYX bmBIT1 /**< GPIFREADYSTAT bitmask to access ReDY Xilinx |
|
/* define pinning of the GPIF interface CTL signals |
accessible while the GPIF is in the IDLE state through the |
GPIFIDLECTL register */ |
#define bmWRU bmBIT1 /**< GPIFREADYSTAT bitmask to access Write Request Xilinx */ |
#define bmRDYU bmBIT2 /**< GPIFREADYSTAT bitmask to access ReDY Xilinx |
|
/* |
* Port A (bit addressable): |
*/ |
/GECKO3COM/gecko3com-fw/firmware/src/gecko3com_main.c
744,8 → 744,13
* After this command all endpoint 2 and 6 data goes directly to the |
* FPGA, the FX2 doesn't parse commands anymore. Use endpoint 0 TMC |
* commands to switch back */ |
init_gpif(); |
flLOCAL = GECKO3COM_REMOTE; |
if(fpga_done()) { |
init_gpif(); |
flLOCAL = GECKO3COM_REMOTE; |
} |
else { |
ieee488_status.EventStatusRegister |= bmEXECUTION_ERROR; |
} |
usb_tmc_state = TMC_STATE_IDLE; |
break; |
|
848,11 → 853,22
} |
} /* end of IN Transfer clause */ |
|
|
/* if we operate in REMOTE mode (means we pass the data to the FPGA) |
* continously check the DONE pin from the FPGA, to avoid that bad things |
* happen when someone reconfigures the FPGA through JTAG */ |
if(flLOCAL == GECKO3COM_REMOTE && !fpga_done()) { |
deactivate_gpif(); |
flLOCAL = GECKO3COM_LOCAL; |
} |
|
|
/* if the LED flag is set to off, disable the external LED */ |
if(flLED == LEDS_OFF) { |
set_led_ext(LEDS_OFF); |
} |
|
|
/* resets the watchdog timer back to the initial value */ |
watchdog_count = WATCHDOG_TIME; |
|
/GECKO3COM/gecko3com-fw/firmware/src/gecko3com_gpif.c
83,7 → 83,7
|
|
/** |
* \brief exectuted when the gpif wafeform terminates |
* \brief exectuted when the gpif waveform terminates |
*/ |
void |
isr_gpif_done (void) interrupt |
90,19 → 90,24
{ |
ISR_DEBUG_PORT |= bmGPIF_DONE; |
|
/* check if this is a end of a IN transfer */ |
if((flGPIF & bmGPIF_READ_IN_PROGRESS) == bmGPIF_READ_IN_PROGRESS){ |
INPKTEND = USB_TMC_EP_IN; |
} |
|
while(!(GPIFTRIG & bmGPIF_IDLE)); |
|
/* check if there is data available for an OUT transfer */ |
/*if((flGPIF & bmGPIF_PENDING_DATA) == bmGPIF_PENDING_DATA) { |
if((flGPIF & bmGPIF_PENDING_DATA) == bmGPIF_PENDING_DATA) { |
//if(!(EP2468STAT & bmEP2EMPTY)) { |
flGPIF &= ~bmGPIF_PENDING_DATA; |
GPIFABORT = 0xFF; |
SYNCDELAY; |
|
gpif_trigger_write(); |
flGPIF &= ~bmGPIF_READ_IN_PROGRESS; |
} |
else*/ { |
/* check if this is a end of a IN transfer */ |
//INPKTEND = USB_TMC_EP_IN; |
while(!(GPIFTRIG & bmGPIF_IDLE)); |
gpif_trigger_read(); |
else { |
gpif_trigger_read(); |
flGPIF |= bmGPIF_READ_IN_PROGRESS; |
} |
|
clear_fifo_gpif_irq(); |
120,14 → 125,15
ISR_DEBUG_PORT |= bmFIFO_PF; |
|
/* check if there is a active IN transfer */ |
/*if((GPIFIDLECTL & bmBIT3) == bmBIT3) { |
if((GPIFREADYSTAT & bmWRX) == bmWRX) { |
flGPIF |= bmGPIF_PENDING_DATA; |
} |
else*/ { |
else { |
GPIFABORT = 0xFF; |
SYNCDELAY; |
while(!(GPIFTRIG & bmGPIF_IDLE)); |
gpif_trigger_write(); |
flGPIF &= ~bmGPIF_READ_IN_PROGRESS; |
} |
|
clear_fifo_gpif_irq(); |
229,27 → 235,28
/** \brief aborts any gpif running gpif transaction */ |
void abort_gpif(void) { |
|
#ifdef GECKO3MAIN |
|
/* signal an abort condition to the FPGA */ |
//if(!(GPIFTRIG & bmGPIF_IDLE)) { |
//GPIFREADYCFG &= ~bmINTRDY; |
//udelay(10); |
//} |
#endif |
EA = 0; /* disable all interrupts */ |
|
flGPIF = 0; |
|
/* abort the current GPIF waveform */ |
GPIFABORT = 0xFF; |
SYNCDELAY; |
while(!(GPIFTRIG & bmGPIF_IDLE)); |
//print_info("gpif aborted\n"); |
|
EA = 1; /* global interrupt enable */ |
|
//print_info("gpif aborted\n"); |
|
#ifdef GECKO3MAIN |
/* signal an abort condition to the FPGA (both WRU and RDYU high) */ |
GPIFIDLECTL |= bmRDYU | bmWRU; |
udelay(10); |
GPIFIDLECTL = InitData[ 3 ]; /* restore original state */ |
#endif |
|
gpif_trigger_read(); |
flGPIF |= bmGPIF_READ_IN_PROGRESS; |
} |
|
|
256,18 → 263,8
/** \brief disables gpif system */ |
void deactivate_gpif(void) { |
|
#ifdef GECKO3MAIN |
|
/* signal an abort condition to the FPGA */ |
//if(!(GPIFTRIG & bmGPIF_IDLE)) { |
//GPIFREADYCFG &= ~bmINTRDY; |
//udelay(10); |
//} |
#endif |
EA = 0; /* disable all interrupts */ |
|
|
EA = 0; /* disable all interrupts */ |
|
EP2FIFOIE = 0; /* disable FIFO interrupt */ |
SYNCDELAY; |
GPIFIE = 0; /* disable all GPIF interrupts */ |
282,17 → 279,21
|
flGPIF = 0; /* unset all internal GPIF flags */ |
|
EA = 1; /* global interrupt enable */ |
|
while(!(GPIFTRIG & bmGPIF_IDLE)); |
|
#ifdef GECKO3MAIN |
/* signal an abort condition to the FPGA (both WRU and RDYU high) */ |
GPIFIDLECTL |= bmRDYU | bmWRU; |
udelay(10); |
GPIFIDLECTL = InitData[ 3 ]; /* restore original state */ |
|
EP2FIFOCFG &= ~bmAUTOOUT; /* disable AutoOUT feature */ |
SYNCDELAY; |
//EP6FIFOCFG &= ~bmINFM; |
EP6FIFOCFG &= ~bmAUTOIN; /* disable AutoIN feature */ |
|
#endif |
|
EA = 1; /* global interrupt enable */ |
|
|
//print_info("gpif deactivated\n"); |
} |
/GECKO3COM/gecko3com-fw/firmware/gpif-design/gecko3main_fifo_transfer.gpf
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/GECKO3COM/gecko3com-fw/firmware/gpif-design/gecko3main_gpif.c
103,13 → 103,13
// DataMode NO Data NO Data NO Data Activate Activate NO Data NO Data |
// NextData SameData SameData SameData SameData NextData SameData SameData |
// Int Trig No Int No Int No Int No Int Trig Int No Int No Int |
// IF/Wait IF IF Wait 1 IF Wait 1 IF IF |
// Term A WRX WRX RDYX WRX WRX |
// LFunc AND AND !A AND B AND AND |
// Term B WRX RDYX WRX WRX WRX |
// Branch1 Then 1 Then 0 Then 3 ThenIdle ThenIdle |
// Branch0 Else 0 Else 2 Else 4 ElseIdle ElseIdle |
// Re-Exec No Yes Yes No Yes |
// IF/Wait IF IF Wait 2 IF Wait 1 IF IF |
// Term A RDYX RDYX WRX WRX WRX |
// LFunc !A AND B !A AND B AND AND AND |
// Term B WRX WRX WRX WRX WRX |
// Branch1 Then 1 Then 2 Then 3 ThenIdle ThenIdle |
// Branch0 Else 0 Else 0 Else 4 ElseIdle ElseIdle |
// Re-Exec No No Yes No Yes |
// Sngl/CRC Default Default Default Default Default Default Default |
// RDYU 0 0 0 0 0 0 0 0 |
// WRU 0 0 0 0 0 0 0 0 |
169,10 → 169,10
/* Output*/ 0x00, 0x02, 0x02, 0x06, 0x06, 0x06, 0x06, 0x00, |
/* LFun */ 0x40, 0x09, 0x0F, 0x09, 0x00, 0x00, 0x00, 0x3F, |
// Wave 2 |
/* LenBr */ 0x08, 0x82, 0x01, 0x9C, 0x01, 0x3F, 0xBF, 0x07, |
/* LenBr */ 0x08, 0x10, 0x02, 0x9C, 0x01, 0x3F, 0xBF, 0x07, |
/* Opcode*/ 0x01, 0x01, 0x00, 0x03, 0x16, 0x01, 0x01, 0x00, |
/* Output*/ 0x00, 0x00, 0x0C, 0x0C, 0x0C, 0x00, 0x00, 0x00, |
/* LFun */ 0x00, 0x01, 0x00, 0xC8, 0x00, 0x00, 0x00, 0x3F, |
/* LFun */ 0xC8, 0xC8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, |
// Wave 3 |
/* LenBr */ 0x39, 0x01, 0x13, 0x23, 0xA5, 0x2F, 0x3F, 0x07, |
/* Opcode*/ 0x01, 0x00, 0x01, 0x03, 0x07, 0x17, 0x01, 0x00, |
186,7 → 186,7
{ |
/* Wave 0 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
/* Wave 1 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
/* Wave 2 FlowStates */ 0x83,0x36,0x04,0x00,0x03,0x23,0x03,0x02,0x00, |
/* Wave 2 FlowStates */ 0x83,0x4E,0x04,0x00,0x04,0x03,0x03,0x02,0x00, |
/* Wave 3 FlowStates */ 0x84,0x09,0x02,0x02,0x04,0x24,0x03,0x02,0x00, |
}; |
// END DO NOT EDIT |
/GECKO3COM/gecko3com-fw/README
2,28 → 2,19
# README -- the short version |
# |
|
The top level makefile handles the host code and FX2 firmware. |
The top level makefile handles the FX2 firmware. |
|
Besides the normal gcc suite and all the auto tools, you'll need |
the SDCC free C compiler to build the firmware. You MUST |
You'll need the SDCC free C compiler to build the firmware. You MUST |
USE VERSION 2.4.0 or VERSION 2.5.0 due to some problems with variable |
initialization. http://sdcc.sourceforge.net |
|
|
The high level interface to the USRP using our standard FPGA bitstram |
is contained in usrp/host/lib/usrp_standard.h |
|
If you've got doxygen installed, there are html docs in |
usrp/doc/html/index.html |
doc/html/index.html |
|
Possible make targets: |
* make (default will build the firmware as hex file) |
* make iic (will generate a downloadable iic file using Hex2Bix.exe with wine) |
* make doc (will generate the html documentation using doxygen) |
|
# Compiling the verilog (not required unless you're modifying it) |
|
If you want to build the FPGA .rbf file from source (not required; we |
provide pre-compiled .rbf files in usrp/fpga/rbf directory), you'll |
need Altera's no cost Quartus II development tools. We're currently |
building with Quartus II 5.1sp1 Web Edition. The project file is |
usrp/fpga/toplevel/usrp_std/usrp_std.qpf. The toplevel verilog file |
is usrp/fpga/toplevel/usrp_std/usrp_std.v. The bulk of the verilog |
modules are contained in usrp/fpga/sdr_lib |
|
For more information, read the source code documentation or the manual in the GECKO3 wiki: |
http://labs.ti.bfh.ch/gecko/wiki/systems/gecko3com/start |
/GECKO3COM/gecko3com-fw/gecko3com.iic
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