OpenCores
URL https://opencores.org/ocsvn/gecko3/gecko3/trunk

Subversion Repositories gecko3

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /gecko3
    from Rev 29 to Rev 30
    ↔ Reverse comparison
  •

Rev 29 → Rev 30

/trunk/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple.ise Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/GECKO3COM/gecko3com-ip/core/gpif_com_fsm.vhd
50,25 → 50,27
 
entity gpif_com_fsm is
port (
i_nReset : in std_logic;
i_IFCLK : in std_logic; -- GPIF CLK (GPIF is Master and provides the clock)
i_WRU : in std_logic; -- write from GPIF
i_RDYU : in std_logic; -- GPIF is ready
i_EOM : in std_logic; -- all data for X2U transfer is in FIFO
i_U2X_FULL : in std_logic;
i_U2X_AM_FULL : in std_logic; -- signals for IN FIFO
i_X2U_FULL_IFCLK : in std_logic;
i_X2U_AM_EMPTY : in std_logic;
i_X2U_EMPTY : in std_logic; -- signals for OUT FIFO
o_bus_trans_dir : out std_logic;
o_U2X_WR_EN : out std_logic; -- signals for IN FIFO
o_X2U_RD_EN : out std_logic; -- signals for OUT FIFO
o_FIFOrst : out std_logic;
o_WRX : out std_logic; -- To write to GPIF
o_RDYX : out std_logic; -- Core is ready
o_ABORT : out std_logic; -- abort condition detected. we have to flush the data
o_RX : out std_logic;
o_TX : out std_logic --
i_nReset : in std_logic;
i_IFCLK : in std_logic; -- GPIF CLK (GPIF is Master and
-- provides the clock)
i_WRU : in std_logic; -- write from GPIF
i_RDYU : in std_logic; -- GPIF is ready
i_EOM : in std_logic; -- all data for X2U transfer is in FIFO
i_U2X_FULL : in std_logic;
i_U2X_AM_FULL : in std_logic; -- signals for IN FIFO
i_X2U_AM_EMPTY : in std_logic;
i_X2U_EMPTY : in std_logic; -- signals for OUT FIFO
o_dbus_out_mux_sel : out std_logic;
o_bus_trans_dir : out std_logic;
o_U2X_WR_EN : out std_logic; -- signals for IN FIFO
o_X2U_RD_EN : out std_logic; -- signals for OUT FIFO
o_FIFOrst : out std_logic;
o_WRX : out std_logic; -- To write to GPIF
o_RDYX : out std_logic; -- Core is ready
o_ABORT : out std_logic; -- abort condition detected.
-- we have to flush the data
o_RX : out std_logic;
o_TX : out std_logic --
);
 
end gpif_com_fsm;
97,7 → 99,7
endInTrans,
-- out com states
outRQ, outRQdelay, outTrans, outACK, outACKwait,
outUSBwait, outUSBwaitEnd, outFIFOwait, endOutTrans);
outUSBwait, outFIFOwait, endOutTrans);
 
111,22 → 113,24
signal s_FIFOrst, s_RDYX, s_WRX, s_ABORT : std_logic;
 
-- USB to Xilinx (U2X)
signal s_U2X_WR_EN : std_logic;
signal s_U2X_WR_EN : std_logic;
 
-- Xilinx to USB (X2U)
signal s_X2U_RD_EN : std_logic;
signal s_X2U_RD_EN : std_logic;
signal s_dbus_out_mux_sel : std_logic;
begin
 
 
o_FIFOrst <= s_FIFOrst;
o_X2U_RD_EN <= s_X2U_RD_EN;
o_WRX <= s_WRX;
o_RDYX <= s_RDYX;
o_U2X_WR_EN <= s_U2X_WR_EN;
o_bus_trans_dir <= '1' when s_bus_trans_dir = writeToGPIF else '0';
o_ABORT <= s_ABORT;
o_FIFOrst <= s_FIFOrst;
o_X2U_RD_EN <= s_X2U_RD_EN;
o_WRX <= s_WRX;
o_RDYX <= s_RDYX;
o_U2X_WR_EN <= s_U2X_WR_EN;
o_bus_trans_dir <= '1' when s_bus_trans_dir = writeToGPIF else '0';
o_ABORT <= s_ABORT;
o_dbus_out_mux_sel <= s_dbus_out_mux_sel;
 
 
-----------------------------------------------------------------------------
148,20 → 152,21
 
-- comb logic
transaction : process(pr_state, i_WRU, i_RDYU, i_U2X_FULL, i_U2X_AM_FULL,
i_X2U_EMPTY, i_X2U_FULL_IFCLK, i_EOM)
i_X2U_EMPTY, i_EOM)
begin -- process transaction
 
-- default signal values to avoid latches:
s_FIFOrst <= '0';
s_bus_trans_dir <= readFromGPIF;
s_U2X_WR_EN <= '0';
s_X2U_RD_EN <= '0';
nx_state <= idle;
s_WRX <= '0';
s_RDYX <= '0';
s_ABORT <= '0';
o_RX <= '0';
o_TX <= '0';
s_FIFOrst <= '0';
s_bus_trans_dir <= readFromGPIF;
s_U2X_WR_EN <= '0';
s_X2U_RD_EN <= '0';
s_dbus_out_mux_sel <= '0';
nx_state <= idle;
s_WRX <= '0';
s_RDYX <= '0';
s_ABORT <= '0';
o_RX <= '0';
o_TX <= '0';
 
case pr_state is
-- controll
168,15 → 173,16
 
when rst =>
-- output signal values:
s_FIFOrst <= '1';
s_WRX <= '0';
s_RDYX <= '0';
s_U2X_WR_EN <= '0';
s_X2U_RD_EN <= '0';
s_ABORT <= '1';
o_RX <= '0';
o_TX <= '0';
s_bus_trans_dir <= readFromGPIF;
s_FIFOrst <= '1';
s_WRX <= '0';
s_RDYX <= '0';
s_U2X_WR_EN <= '0';
s_X2U_RD_EN <= '0';
s_ABORT <= '1';
s_dbus_out_mux_sel <= '0';
o_RX <= '0';
o_TX <= '0';
s_bus_trans_dir <= readFromGPIF;
 
-- state decisions
if i_WRU = '1' and i_RDYU = '1' then
200,7 → 206,6
elsif i_WRU = '1' and i_RDYU = '0' then
nx_state <= inRQ;
elsif i_WRU = '0' and
--(i_X2U_FULL_IFCLK = '1' or i_EOM = '1') and i_X2U_EMPTY = '0' then
i_X2U_EMPTY = '0' then
nx_state <= outRQ;
else
353,7 → 358,7
else
nx_state <= outACK;
end if;
 
when outACK =>
-- output signal values:
s_WRX <= '1';
382,7 → 387,6
nx_state <= rst;
elsif i_WRU = '0' and i_RDYU = '1' then
nx_state <= outTrans;
s_X2U_RD_EN <= '1';
else
nx_state <= outACKwait;
end if;
394,6 → 398,7
s_X2U_RD_EN <= '1';
o_TX <= '1';
s_bus_trans_dir <= writeToGPIF;
s_dbus_out_mux_sel <= '0';
-- state decisions
if i_WRU = '1' and i_RDYU = '1' then
406,7 → 411,7
nx_state <= outTrans;
else
nx_state <= outUSBwait;
s_X2U_RD_EN <= '0';
s_X2U_RD_EN <= '0';
end if;
 
when outUSBwait =>
416,6 → 421,7
s_X2U_RD_EN <= '0';
o_TX <= '1';
s_bus_trans_dir <= writeToGPIF;
s_dbus_out_mux_sel <= '1';
 
-- state decisions
if i_WRU = '1' and i_RDYU = '1' then
423,22 → 429,11
elsif i_X2U_EMPTY = '1' and i_EOM = '1' then
nx_state <= endOutTrans;
elsif i_WRU = '0' and i_RDYU = '1' then
nx_state <= outUSBwaitEnd;
nx_state <= outTrans;
else
nx_state <= outUSBwait;
end if;
end if;
when outUSBwaitEnd =>
-- output signal values:
s_WRX <= '1';
s_RDYX <= '0';
s_X2U_RD_EN <= '1';
o_TX <= '1';
s_bus_trans_dir <= writeToGPIF;
 
-- state decisions
nx_state <= outTrans;
when outFIFOwait =>
-- output signal values:
s_WRX <= '1';
454,7 → 449,6
nx_state <= endOutTrans;
elsif i_X2U_EMPTY = '0' then
nx_state <= outTrans;
s_X2U_RD_EN <= '1';
else
nx_state <= outFIFOwait;
end if;
/trunk/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple_test.vhd
354,7 → 354,8
'0';
 
 
-- purpose: subracts the send counter end value from the remaining transfer size value
-- purpose: subracts the send counter end value from the remaining transfer
-- size value
-- type : combinational
-- inputs : s_remaining_transfer_size, s_send_counter_value
-- outputs: s_subtract_value
/trunk/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple_test.cdc
1,5 → 1,5
#ChipScope Core Inserter Project File Version 3.0
#Sat Feb 27 18:00:38 CET 2010
#Sun Feb 28 00:15:45 CET 2010
Project.device.designInputFile=/home/chrigi/bfh-work/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple_test_cs.ngc
Project.device.designOutputFile=/home/chrigi/bfh-work/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple_test_cs.ngc
Project.device.deviceFamily=6
/trunk/GECKO3COM/gecko3com-ip/core/GECKO3COM_simple_test.cpj
1,5 → 1,5
#ChipScope Pro Analyzer Project File, Version 3.0
#Thu Feb 25 21:47:08 CET 2010
#Sun Feb 28 02:06:22 CET 2010
deviceChain.deviceName0=XC3S4000
deviceChain.iRLength0=6
deviceChain.name0=MyDevice0
34,7 → 34,7
unit.0.0.1.WIDTH1=1.0563822
unit.0.0.1.X1=-0.0031323414
unit.0.0.1.Y1=0.10463734
unit.0.0.MFBitsA0=XXXXX1XXXXXX
unit.0.0.MFBitsA0=XXXXXX1XXXXX
unit.0.0.MFBitsA1=XXXXX0XXXXXX
unit.0.0.MFBitsB0=000000000000
unit.0.0.MFBitsB1=000000000000
53,7 → 53,7
unit.0.0.TCActive=0
unit.0.0.TCAdvanced0=0
unit.0.0.TCCondition0_0=M0
unit.0.0.TCCondition0_1=M0
unit.0.0.TCCondition0_1=M0 --> M1 --> M0
unit.0.0.TCConditionType0=1
unit.0.0.TCCount=1
unit.0.0.TCEventCount0=1
119,10 → 119,10
unit.0.0.port.-1.b.10.unsignedPrecision=0
unit.0.0.port.-1.b.10.unsignedScaleFactor=1.0
unit.0.0.port.-1.b.10.visible=1
unit.0.0.port.-1.b.2.alias=/s_send_fifo_data
unit.0.0.port.-1.b.2.channellist=49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
unit.0.0.port.-1.b.2.alias=GECKO3COM_simple_fsm_1/state_FSM_FFd1
unit.0.0.port.-1.b.2.channellist=42 43 44 45 46
unit.0.0.port.-1.b.2.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.b.2.name=/s_send_fifo_data
unit.0.0.port.-1.b.2.name=/GECKO3COM_simple_1/o_receive_transfersize
unit.0.0.port.-1.b.2.orderindex=-1
unit.0.0.port.-1.b.2.radix=Hex
unit.0.0.port.-1.b.2.signedOffset=0.0
133,10 → 133,10
unit.0.0.port.-1.b.2.unsignedPrecision=0
unit.0.0.port.-1.b.2.unsignedScaleFactor=1.0
unit.0.0.port.-1.b.2.visible=1
unit.0.0.port.-1.b.3.alias=GECKO3COM_simple_fsm_1/state_FSM_FFd1
unit.0.0.port.-1.b.3.channellist=42 43 44 45 46
unit.0.0.port.-1.b.3.alias=GPIF_INTERFACE/s_dbus_out
unit.0.0.port.-1.b.3.channellist=49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
unit.0.0.port.-1.b.3.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.b.3.name=/GECKO3COM_simple_1/o_receive_transfersize
unit.0.0.port.-1.b.3.name=/s_send_fifo_data
unit.0.0.port.-1.b.3.orderindex=-1
unit.0.0.port.-1.b.3.radix=Hex
unit.0.0.port.-1.b.3.signedOffset=0.0
685,7 → 685,7
unit.0.0.port.-1.s.48.visible=1
unit.0.0.port.-1.s.49.alias=
unit.0.0.port.-1.s.49.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.49.name=/GECKO3COM_simple_1/GECKO3COM_simple_datapath_1/s_send_fifo_data<0>
unit.0.0.port.-1.s.49.name=/GECKO3COM_simple_1/GPIF_INTERFACE/s_dbus_out<0>
unit.0.0.port.-1.s.49.orderindex=-1
unit.0.0.port.-1.s.49.visible=0
unit.0.0.port.-1.s.5.alias=
695,52 → 695,52
unit.0.0.port.-1.s.5.visible=1
unit.0.0.port.-1.s.50.alias=
unit.0.0.port.-1.s.50.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.50.name=/GECKO3COM_simple_1/GECKO3COM_simple_datapath_1/s_send_fifo_data<1>
unit.0.0.port.-1.s.50.name=/GECKO3COM_simple_1/GPIF_INTERFACE/s_dbus_out<1>
unit.0.0.port.-1.s.50.orderindex=-1
unit.0.0.port.-1.s.50.visible=0
unit.0.0.port.-1.s.51.alias=
unit.0.0.port.-1.s.51.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.51.name=/GECKO3COM_simple_1/GECKO3COM_simple_datapath_1/s_send_fifo_data<2>
unit.0.0.port.-1.s.51.name=/GECKO3COM_simple_1/GPIF_INTERFACE/s_dbus_out<2>
unit.0.0.port.-1.s.51.orderindex=-1
unit.0.0.port.-1.s.51.visible=0
unit.0.0.port.-1.s.52.alias=
unit.0.0.port.-1.s.52.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.52.name=/GECKO3COM_simple_1/GECKO3COM_simple_datapath_1/s_send_fifo_data<3>
unit.0.0.port.-1.s.52.name=/GECKO3COM_simple_1/GPIF_INTERFACE/s_dbus_out<3>
unit.0.0.port.-1.s.52.orderindex=-1
unit.0.0.port.-1.s.52.visible=0
unit.0.0.port.-1.s.53.alias=
unit.0.0.port.-1.s.53.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.53.name=/GECKO3COM_simple_1/GECKO3COM_simple_datapath_1/s_send_fifo_data<4>
unit.0.0.port.-1.s.53.name=/GECKO3COM_simple_1/GPIF_INTERFACE/s_dbus_out<4>
unit.0.0.port.-1.s.53.orderindex=-1
unit.0.0.port.-1.s.53.visible=0
unit.0.0.port.-1.s.54.alias=
unit.0.0.port.-1.s.54.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.54.name=/GECKO3COM_simple_1/GECKO3COM_simple_datapath_1/s_send_fifo_data<5>
unit.0.0.port.-1.s.54.name=/GECKO3COM_simple_1/GPIF_INTERFACE/s_dbus_out<5>
unit.0.0.port.-1.s.54.orderindex=-1
unit.0.0.port.-1.s.54.visible=0
unit.0.0.port.-1.s.55.alias=
unit.0.0.port.-1.s.55.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.55.name=/GECKO3COM_simple_1/GECKO3COM_simple_datapath_1/s_send_fifo_data<6>
unit.0.0.port.-1.s.55.name=/GECKO3COM_simple_1/GPIF_INTERFACE/s_dbus_out<6>
unit.0.0.port.-1.s.55.orderindex=-1
unit.0.0.port.-1.s.55.visible=0
unit.0.0.port.-1.s.56.alias=
unit.0.0.port.-1.s.56.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.56.name=/GECKO3COM_simple_1/GECKO3COM_simple_datapath_1/s_send_fifo_data<7>
unit.0.0.port.-1.s.56.name=/GECKO3COM_simple_1/GPIF_INTERFACE/s_dbus_out<7>
unit.0.0.port.-1.s.56.orderindex=-1
unit.0.0.port.-1.s.56.visible=0
unit.0.0.port.-1.s.57.alias=
unit.0.0.port.-1.s.57.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.57.name=/GECKO3COM_simple_1/GECKO3COM_simple_datapath_1/s_send_fifo_data<8>
unit.0.0.port.-1.s.57.name=/GECKO3COM_simple_1/GPIF_INTERFACE/s_dbus_out<8>
unit.0.0.port.-1.s.57.orderindex=-1
unit.0.0.port.-1.s.57.visible=0
unit.0.0.port.-1.s.58.alias=
unit.0.0.port.-1.s.58.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.58.name=/GECKO3COM_simple_1/GECKO3COM_simple_datapath_1/s_send_fifo_data<9>
unit.0.0.port.-1.s.58.name=/GECKO3COM_simple_1/GPIF_INTERFACE/s_dbus_out<9>
unit.0.0.port.-1.s.58.orderindex=-1
unit.0.0.port.-1.s.58.visible=0
unit.0.0.port.-1.s.59.alias=
unit.0.0.port.-1.s.59.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.59.name=/GECKO3COM_simple_1/GECKO3COM_simple_datapath_1/s_send_fifo_data<10>
unit.0.0.port.-1.s.59.name=/GECKO3COM_simple_1/GPIF_INTERFACE/s_dbus_out<10>
unit.0.0.port.-1.s.59.orderindex=-1
unit.0.0.port.-1.s.59.visible=0
unit.0.0.port.-1.s.6.alias=
750,27 → 750,27
unit.0.0.port.-1.s.6.visible=1
unit.0.0.port.-1.s.60.alias=
unit.0.0.port.-1.s.60.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.60.name=/GECKO3COM_simple_1/GECKO3COM_simple_datapath_1/s_send_fifo_data<11>
unit.0.0.port.-1.s.60.name=/GECKO3COM_simple_1/GPIF_INTERFACE/s_dbus_out<11>
unit.0.0.port.-1.s.60.orderindex=-1
unit.0.0.port.-1.s.60.visible=0
unit.0.0.port.-1.s.61.alias=
unit.0.0.port.-1.s.61.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.61.name=/GECKO3COM_simple_1/GECKO3COM_simple_datapath_1/s_send_fifo_data<12>
unit.0.0.port.-1.s.61.name=/GECKO3COM_simple_1/GPIF_INTERFACE/s_dbus_out<12>
unit.0.0.port.-1.s.61.orderindex=-1
unit.0.0.port.-1.s.61.visible=0
unit.0.0.port.-1.s.62.alias=
unit.0.0.port.-1.s.62.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.62.name=/GECKO3COM_simple_1/GECKO3COM_simple_datapath_1/s_send_fifo_data<13>
unit.0.0.port.-1.s.62.name=/GECKO3COM_simple_1/GPIF_INTERFACE/s_dbus_out<13>
unit.0.0.port.-1.s.62.orderindex=-1
unit.0.0.port.-1.s.62.visible=0
unit.0.0.port.-1.s.63.alias=
unit.0.0.port.-1.s.63.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.63.name=/GECKO3COM_simple_1/GECKO3COM_simple_datapath_1/s_send_fifo_data<14>
unit.0.0.port.-1.s.63.name=/GECKO3COM_simple_1/GPIF_INTERFACE/s_dbus_out<14>
unit.0.0.port.-1.s.63.orderindex=-1
unit.0.0.port.-1.s.63.visible=0
unit.0.0.port.-1.s.64.alias=
unit.0.0.port.-1.s.64.color=java.awt.Color[r\=0,g\=0,b\=124]
unit.0.0.port.-1.s.64.name=/GECKO3COM_simple_1/GECKO3COM_simple_datapath_1/s_send_fifo_data<15>
unit.0.0.port.-1.s.64.name=/GECKO3COM_simple_1/GPIF_INTERFACE/s_dbus_out<15>
unit.0.0.port.-1.s.64.orderindex=-1
unit.0.0.port.-1.s.64.visible=0
unit.0.0.port.-1.s.65.alias=
1340,7 → 1340,7
unit.0.0.waveform.posn.4.name=/GECKO3COM_simple_1/o_receive_end_of_message
unit.0.0.waveform.posn.4.type=signal
unit.0.0.waveform.posn.40.channel=2147483646
unit.0.0.waveform.posn.40.name=/s_send_fifo_data
unit.0.0.waveform.posn.40.name=GPIF_INTERFACE/s_dbus_out
unit.0.0.waveform.posn.40.radix=1
unit.0.0.waveform.posn.40.type=bus
unit.0.0.waveform.posn.41.channel=2147483646
/trunk/GECKO3COM/gecko3com-ip/core/gpif_com.vhd
103,6 → 103,8
s_X2U_EMPTY,
s_X2U_AM_EMPTY : std_logic;
signal s_X2U_DATA : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
 
signal s_dbus_out_mux_sel : std_logic;
-----------------------------------------------------------------------------
-- data bus
112,7 → 114,9
signal s_dbus_trans_dir : std_logic;
signal s_dbus_in : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
signal s_dbus_out : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
signal s_dbus_out_fifo : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
 
signal s_fifo_out : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
signal s_fifo_old : std_logic_vector(SIZE_DBUS_GPIF-1 downto 0);
-----------------------------------------------------------------------------
-- COMPONENTS
121,25 → 125,25
-- FSM GPIF
component gpif_com_fsm
port (
i_nReset : in std_logic;
i_IFCLK : in std_logic;
i_WRU : in std_logic;
i_RDYU : in std_logic;
i_EOM : in std_logic;
i_U2X_FULL : in std_logic;
i_U2X_AM_FULL : in std_logic;
i_X2U_FULL_IFCLK : in std_logic;
i_X2U_AM_EMPTY : in std_logic;
i_X2U_EMPTY : in std_logic;
o_bus_trans_dir : out std_logic;
o_U2X_WR_EN : out std_logic;
o_X2U_RD_EN : out std_logic;
o_FIFOrst : out std_logic;
o_WRX : out std_logic;
o_RDYX : out std_logic;
o_ABORT : out std_logic;
o_RX : out std_logic;
o_TX : out std_logic);
i_nReset : in std_logic;
i_IFCLK : in std_logic;
i_WRU : in std_logic;
i_RDYU : in std_logic;
i_EOM : in std_logic;
i_U2X_FULL : in std_logic;
i_U2X_AM_FULL : in std_logic;
i_X2U_AM_EMPTY : in std_logic;
i_X2U_EMPTY : in std_logic;
o_dbus_out_mux_sel : out std_logic;
o_bus_trans_dir : out std_logic;
o_U2X_WR_EN : out std_logic;
o_X2U_RD_EN : out std_logic;
o_FIFOrst : out std_logic;
o_WRX : out std_logic;
o_RDYX : out std_logic;
o_ABORT : out std_logic;
o_RX : out std_logic;
o_TX : out std_logic);
end component;
 
-- FIFO dualclock to cross the clock domain between the GPIF and the FPGA
191,7 → 195,7
i_wr_en => s_X2U_WR_EN,
o_almost_empty => s_X2U_AM_EMPTY,
o_almost_full => s_X2U_AM_FULL,
o_dout => s_dbus_out_fifo,
o_dout => s_fifo_out,
o_empty => s_X2U_EMPTY,
o_full => s_X2U_FULL
);
199,26 → 203,26
 
FSM_GPIF : gpif_com_fsm
port map (
i_nReset => i_nReset,
i_IFCLK => i_IFCLK,
i_WRU => i_WRU,
i_RDYU => i_RDYU,
i_nReset => i_nReset,
i_IFCLK => i_IFCLK,
i_WRU => i_WRU,
i_RDYU => i_RDYU,
--i_EOM => s_EOM,
i_EOM => s_EOM_FF,
i_U2X_FULL => s_U2X_FULL,
i_U2X_AM_FULL => s_U2X_AM_FULL,
i_X2U_FULL_IFCLK => s_X2U_FULL_IFCLK,
i_X2U_AM_EMPTY => s_X2U_AM_EMPTY,
i_X2U_EMPTY => s_X2U_EMPTY,
o_U2X_WR_EN => s_U2X_WR_EN,
o_X2U_RD_EN => s_X2U_RD_EN,
o_FIFOrst => s_FIFOrst,
o_bus_trans_dir => s_dbus_trans_dir,
o_WRX => s_WRX,
o_RDYX => s_RDYX,
o_ABORT => s_ABORT_FSM,
o_RX => s_RX_FSM,
o_TX => s_TX_FSM
i_EOM => s_EOM_FF,
i_U2X_FULL => s_U2X_FULL,
i_U2X_AM_FULL => s_U2X_AM_FULL,
i_X2U_AM_EMPTY => s_X2U_AM_EMPTY,
i_X2U_EMPTY => s_X2U_EMPTY,
o_U2X_WR_EN => s_U2X_WR_EN,
o_X2U_RD_EN => s_X2U_RD_EN,
o_dbus_out_mux_sel => s_dbus_out_mux_sel,
o_FIFOrst => s_FIFOrst,
o_bus_trans_dir => s_dbus_trans_dir,
o_WRX => s_WRX,
o_RDYX => s_RDYX,
o_ABORT => s_ABORT_FSM,
o_RX => s_RX_FSM,
o_TX => s_TX_FSM
);
 
 
258,13 → 262,10
double_buf_ifclk : process (i_IFCLK, i_nReset)
begin
if i_nReset = '0' then
s_X2U_FULL_TMP <= '0';
s_X2U_FULL_IFCLK <= '0';
s_EOM <= '0';
elsif rising_edge(i_IFCLK) then
s_EOM <= s_EOM_TMP;
s_EOM_TMP <= i_EOM;
s_X2U_FULL_IFCLK <= s_X2U_FULL_TMP;
s_X2U_FULL_TMP <= s_X2U_FULL;
end if;
end process double_buf_ifclk;
 
311,10 → 312,22
s_dbus_in <= b_gpif_bus;
 
if s_X2U_RD_EN = '1' then
s_dbus_out <= s_dbus_out_fifo;
s_fifo_old <= s_fifo_out;
end if;
end if;
end process buf_input;
 
-- purpose: multiplexer to select two older copies of fifo data
-- type : combinational
-- inputs : s_dbus_out_mux_sel, s_fifo_old, s_fifo_out
-- outputs: s_dbus_out
dbus_out_mux: process (s_dbus_out_mux_sel, s_fifo_old, s_fifo_out)
begin -- process dbus_out_mux
case s_dbus_out_mux_sel is
when '0' => s_dbus_out <= s_fifo_out;
when '1' => s_dbus_out <= s_fifo_old;
when others => s_dbus_out <= s_fifo_out;
end case;
end process dbus_out_mux;
 
end structure;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.