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/trunk/GECKO4com/fx2_firmware/asm/usb_descriptors.a51
0,0 → 1,379
;;; -*- asm -*-
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; _ _ __ ____ ;;
;; / / | | / _| | __| ;;
;; | |_| | _ _ / / | |_ ;;
;; | _ | | | | | | | | _| ;;
;; | | | | | |_| | \ \_ | |__ ;;
;; |_| |_| \_____| \__| |____| microLab ;;
;; ;;
;; Bern University of Applied Sciences (BFH) ;;
;; Quellgasse 21 ;;
;; Room HG 4.33 ;;
;; 2501 Biel/Bienne ;;
;; Switzerland ;;
;; ;;
;; http://www.microlab.ch ;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;
;;; GECKO4COM
;;;
;;; This program is free software: you can redistribute it and/or modify
;;; it under the terms of the GNU General Public License as published by
;;; the Free Software Foundation, either version 3 of the License, or
;;; (at your option) any later version.
;;;
;;; This program is distributed in the hope that it will be useful,
;;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;;; GNU General Public License for more details.
;;; You should have received a copy of the GNU General Public License
;;; along with this program. If not, see <http://www.gnu.org/licenses/>.
;;;
;;;********************************************************************
;;;
;;; Endpoint configuration is according to USB TMC specification 1.0
;;;
 
.module usb_descriptors
 
VID_BFH = 0xBFF1 ; Just stole a non defined VID, not registered
PID_GECKO = 0x0004 ; GECKO4 PID
DID_GECKO = 0x0100 ; Device ID in BCD
DSCR_DEVICE_LENGTH = 18
DSCR_DQUAL_LENGTH = 10
DSCR_CONFIG_LENGTH = 9
DSCR_IF_LENGTH = 9
DSCR_EP_LENGTH = 7
DSCR_DEVICE = 1
DSCR_CONFIG = 2
DSCR_STRING = 3
DSCR_INTERFACE = 4
DSCR_END_POINT = 5
DSCR_DEVICE_QUAL = 6
DSCR_USB_VER = 0x0200
DSCR_US_ENGLISH = 0x0409
DSCR_DEVICE_CLASS = 0x00
DSCR_DEVICE_SUBCLASS = 0x00
DSCR_DEVICE_PROTOCOL = 0x00
DSCR_MAX_PACKET_SIZE = 64
DSCR_NUMBER_CONFIGS = 1
DSCR_RESERVED = 0
DSCR_BUS_POWERED = 0x80
DSCR_BUS_POWER_100mA = 50
DSCR_BUS_POWER_500mA = 250
DSCR_EP2_OUT = 0x02
DSCR_EP2_IN = 0x82
DSCR_EP4_OUT = 0x04
DSCR_EP4_IN = 0x84
DSCR_EP6_OUT = 0x06
DSCR_EP6_IN = 0x86
DSCR_EP8_OUT = 0x08
DSCR_EP8_IN = 0x88
NUM_INTERFACES = 1
CONFIG_VALUE = 1
INTERFACE_0 = 0
ALT_SETTING_0 = 0
NR_ENDPOINTS_ONE = 1
NR_ENDPOINTS_TWO = 2
ET_BULK = 0x02
FS_MAX_PACK_SIZE = 64
HS_MAX_PACK_SIZE = 512
USBTMC_IF_CLASS = 0xFE
USBTMC_IF_SUBCLASS = 0x03
USBTMC_PROTO = 0x01
INTERVAL_0 = 0
;;;-----------------------------------------------------------------------------
;;; external ram data
;;;-----------------------------------------------------------------------------
.area USBDESCSEG (XDATA)
 
;;;-----------------------------------------------------------------------------
;;; Default descriptors at initial enumeration (full speed mode)
;;;-----------------------------------------------------------------------------
_high_speed_device_descr::
_full_speed_device_descr::
.db DSCR_DEVICE_LENGTH
.db DSCR_DEVICE
.db <DSCR_USB_VER
.db >DSCR_USB_VER
.db DSCR_DEVICE_CLASS
.db DSCR_DEVICE_SUBCLASS
.db DSCR_DEVICE_PROTOCOL
.db DSCR_MAX_PACKET_SIZE
.db <VID_BFH
.db >VID_BFH
.db <PID_GECKO
.db >PID_GECKO
.db <DID_GECKO
.db >DID_GECKO
.db ID_MANUFACTURER
.db ID_PRODUCT
.db ID_SERIAL
.db DSCR_NUMBER_CONFIGS ; 18 bytes
_high_speed_devqual_descr::
_full_speed_devqual_descr::
.db DSCR_DQUAL_LENGTH
.db DSCR_DEVICE_QUAL
.db <DSCR_USB_VER
.db >DSCR_USB_VER
.db DSCR_DEVICE_CLASS
.db DSCR_DEVICE_SUBCLASS
.db DSCR_DEVICE_PROTOCOL
.db DSCR_MAX_PACKET_SIZE
.db DSCR_NUMBER_CONFIGS
.db DSCR_RESERVED ; 28 bytes
 
_full_speed_config_descr::
.db DSCR_CONFIG_LENGTH
.db DSCR_CONFIG
.db <(_full_speed_config_descr_end-_full_speed_config_descr)
.db >(_full_speed_config_descr_end-_full_speed_config_descr)
.db NUM_INTERFACES
.db CONFIG_VALUE
.db ID_FULL_SPEED
_device_bus_attributes_fs::
.db DSCR_BUS_POWERED
.db DSCR_BUS_POWER_500mA ; 37 bytes
 
;;; Interface 0 descriptor (USB TMC, ep8 OUT BULK, ep6 IN BULK)
.db DSCR_IF_LENGTH
.db DSCR_INTERFACE
.db INTERFACE_0
.db ALT_SETTING_0
.db NR_ENDPOINTS_TWO
.db USBTMC_IF_CLASS
.db USBTMC_IF_SUBCLASS
.db USBTMC_PROTO
.db ID_USBTMC ; 46 bytes
;;; Interface 0 OUT endpoint
.db DSCR_EP_LENGTH
.db DSCR_END_POINT
.db DSCR_EP8_OUT
.db ET_BULK
.db <FS_MAX_PACK_SIZE
.db >FS_MAX_PACK_SIZE
.db INTERVAL_0 ; 53 bytes
;;; Interface 0 IN endpoint
.db DSCR_EP_LENGTH
.db DSCR_END_POINT
.db DSCR_EP6_IN
.db ET_BULK
.db <FS_MAX_PACK_SIZE
.db >FS_MAX_PACK_SIZE
.db INTERVAL_0 ; 60 bytes
_full_speed_config_descr_end:
 
;;;-----------------------------------------------------------------------------
;;; High Speed descriptors
;;;-----------------------------------------------------------------------------
_high_speed_config_descr::
.db DSCR_CONFIG_LENGTH
.db DSCR_CONFIG
.db <(_high_speed_config_descr_end-_high_speed_config_descr)
.db >(_high_speed_config_descr_end-_high_speed_config_descr)
.db NUM_INTERFACES
.db CONFIG_VALUE
.db ID_HI_SPEED
_device_bus_attributes_hs::
.db DSCR_BUS_POWERED
.db DSCR_BUS_POWER_500mA
 
;;; Interface 0 descriptor (USB TMC, ep8 OUT BULK, ep6 IN BULK)
.db DSCR_IF_LENGTH
.db DSCR_INTERFACE
.db INTERFACE_0
.db ALT_SETTING_0
.db NR_ENDPOINTS_TWO
.db USBTMC_IF_CLASS
.db USBTMC_IF_SUBCLASS
.db USBTMC_PROTO
.db ID_USBTMC ; 46 bytes
;;; Interface 0 OUT endpoint
.db DSCR_EP_LENGTH
.db DSCR_END_POINT
.db DSCR_EP8_OUT
.db ET_BULK
.db <HS_MAX_PACK_SIZE
.db >HS_MAX_PACK_SIZE
.db INTERVAL_0 ; 53 bytes
;;; Interface 0 IN endpoint
.db DSCR_EP_LENGTH
.db DSCR_END_POINT
.db DSCR_EP6_IN
.db ET_BULK
.db <HS_MAX_PACK_SIZE
.db >HS_MAX_PACK_SIZE
.db INTERVAL_0 ; 60 bytes
_high_speed_config_descr_end:
 
;;;-----------------------------------------------------------------------------
;;; String index table
;;;-----------------------------------------------------------------------------
_nstring_descriptors::
.db (_string_index_table_end - _string_descriptors) / 2
_string_descriptors::
.db <_str_language , >_str_language
.db <_manufacturer , >_manufacturer
.db <_product , >_product
.db <_serial , >_serial
.db <_full_speed , >_full_speed
.db <_usbtmc , >_usbtmc
.db <_hi_speed , >_hi_speed
_string_index_table_end::
.db 0 ;; make even address, as the table is by definition odd
; +16 => 76 bytes
;;;-----------------------------------------------------------------------------
;;; String descriptors
;;;-----------------------------------------------------------------------------
 
ID_LANGUAGE = 0
_str_language:
.db _str_language_end - _str_language
.db DSCR_STRING
.db 0
.db 0
.db <DSCR_US_ENGLISH
.db >DSCR_US_ENGLISH
_str_language_end: ; +6 => 82 bytes
 
ID_MANUFACTURER = 1
_manufacturer:
.db _manufacturer_end - _manufacturer
.db DSCR_STRING
.db 'B , 0
.db 'e , 0
.db 'r , 0
.db 'n , 0
.db ' , 0
.db 'U , 0
.db 'n , 0
.db 'i , 0
.db 'v , 0
.db 'e , 0
.db 'r , 0
.db 's , 0
.db 'i , 0
.db 't , 0
.db 'y , 0
.db ' , 0
.db 'o , 0
.db 'f , 0
.db ' , 0
.db 'A , 0
.db 'p , 0
.db 'p , 0
.db 'l , 0
.db 'i , 0
.db 'e , 0
.db 'd , 0
.db ' , 0
.db 'S , 0
.db 'c , 0
.db 'i , 0
.db 'e , 0
.db 'n , 0
.db 'c , 0
.db 'e , 0
.db 's , 0
.db ': , 0
.db ' , 0
.db 'H , 0
.db 'U , 0
.db 'C , 0
.db 'E , 0
.db '- , 0
.db 'm , 0
.db 'i , 0
.db 'c , 0
.db 'r , 0
.db 'o , 0
.db 'l , 0
.db 'a , 0
.db 'b , 0
_manufacturer_end:
 
ID_PRODUCT = 2
_product:
.db _product_end - _product
.db DSCR_STRING
.db 'G , 0
.db 'E , 0
.db 'C , 0
.db 'K , 0
.db 'O , 0
.db '4 , 0
.db 'C , 0
.db 'O , 0
.db 'M , 0 ; +20 => 134 bytes
_product_end:
 
ID_SERIAL = 3
_serial:
.db _serial_end - _serial
.db DSCR_STRING
.db 'V , 0
.db '1 , 0
.db '. , 0
.db '0 , 0 ; +10 => 144 bytes
_serial_end:
 
ID_FULL_SPEED = 4
_full_speed:
.db _full_speed_end - _full_speed
.db DSCR_STRING
.db 'F , 0
.db 'u , 0
.db 'l , 0
.db 'l , 0
.db ' , 0
.db 'S , 0
.db 'p , 0
.db 'e , 0
.db 'e , 0
.db 'd , 0 ; +22 => 166 bytes
_full_speed_end:
 
ID_USBTMC = 5
_usbtmc:
.db _usbtmc_end - _usbtmc
.db DSCR_STRING
.db 'U , 0
.db 'S , 0
.db 'B , 0
.db 'T , 0
.db 'M , 0
.db 'C , 0
.db ' , 0
.db 'U , 0
.db 'S , 0
.db 'B , 0
.db '4 , 0
.db '8 , 0
.db '8 , 0 ; +28 => 194 bytes
_usbtmc_end:
 
ID_HI_SPEED = 6
_hi_speed:
.db _hi_speed_end - _hi_speed
.db DSCR_STRING
.db 'H , 0
.db 'i , 0
.db 'g , 0
.db 'h , 0
.db ' , 0
.db 'S , 0
.db 'p , 0
.db 'e , 0
.db 'e , 0
.db 'd , 0 ; +22 => 216 bytes
_hi_speed_end:
 
/trunk/GECKO4com/fx2_firmware/asm/startup.a51
0,0 → 1,78
;;; -*- asm -*-
;;;
;;;-----------------------------------------------------------------------------
;;; Startup code
;;;-----------------------------------------------------------------------------
;;; Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
;;; Copyright 2003 Free Software Foundation, Inc.
;;;-----------------------------------------------------------------------------
;;; This code is part of usbjtag. usbjtag is free software; you can redistribute
;;; it and/or modify it under the terms of the GNU General Public License as
;;; published by the Free Software Foundation; either version 2 of the License,
;;; or (at your option) any later version. usbjtag is distributed in the hope
;;; that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
;;; warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;;; GNU General Public License for more details. You should have received a
;;; copy of the GNU General Public License along with this program in the file
;;; COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
;;; St, Fifth Floor, Boston, MA 02110-1301 USA
;;;-----------------------------------------------------------------------------
 
;;; The default external memory initialization provided by sdcc is not
;;; appropriate to the FX2. This is derived from the sdcc code, but uses
;;; the FX2 specific _MPAGE sfr.
 
 
;; .area XISEG (XDATA) ; the initialized external data area
;; .area XINIT (CODE) ; the code space consts to init XISEG
.area XSEG (XDATA) ; zero initialized xdata
.area USBDESCSEG (XDATA) ; usb descriptors
 
 
.area CSEG (CODE)
 
;; sfr that sets upper address byte of MOVX using @r0 or @r1
_MPAGE = 0x0092
 
__sdcc_external_startup::
;; This system is now compiled with the --no-xinit-opt
;; which means that any initialized XDATA is handled
;; inline by code in the GSINIT segs emitted for each file.
;;
;; We zero XSEG and all of the internal ram to ensure
;; a known good state for uninitialized variables.
 
; _mcs51_genRAMCLEAR() start
mov r0,#l_XSEG
mov a,r0
orl a,#(l_XSEG >> 8)
jz 00002$
mov r1,#((l_XSEG + 255) >> 8)
mov dptr,#s_XSEG
clr a
00001$: movx @dptr,a
inc dptr
djnz r0,00001$
djnz r1,00001$
;; We're about to clear internal memory. This will overwrite
;; the stack which contains our return address.
;; Pop our return address into DPH, DPL
00002$: pop dph
pop dpl
;; R0 and A contain 0. This loop will execute 256 times.
;;
;; FWIW the first iteration writes direct address 0x00,
;; which is the location of r0. We get lucky, we're
;; writing the correct value (0)
00003$: mov @r0,a
djnz r0,00003$
 
push dpl ; restore our return address
push dph
 
mov dpl,#0 ; indicate that data init is still required
ret
/trunk/GECKO4com/fx2_firmware/asm/vectors.a51
0,0 → 1,176
;;; -*- asm -*-
;;;
;;;-----------------------------------------------------------------------------
;;; Interrupt vectors
;;;-----------------------------------------------------------------------------
;;; Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,
;;; Copyright 2003 Free Software Foundation, Inc.
;;;-----------------------------------------------------------------------------
;;; This code is part of usbjtag. usbjtag is free software; you can redistribute
;;; it and/or modify it under the terms of the GNU General Public License as
;;; published by the Free Software Foundation; either version 2 of the License,
;;; or (at your option) any later version. usbjtag is distributed in the hope
;;; that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
;;; warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;;; GNU General Public License for more details. You should have received a
;;; copy of the GNU General Public License along with this program in the file
;;; COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin
;;; St, Fifth Floor, Boston, MA 02110-1301 USA
;;;-----------------------------------------------------------------------------
 
;;; N.B. This object module must come first in the list of modules
 
.module vectors
 
;;; ----------------------------------------------------------------
;;; standard FX2 interrupt vectors
;;; ----------------------------------------------------------------
 
.area CSEG (CODE)
.area GSINIT (CODE)
.area CSEG (CODE)
__standard_interrupt_vector::
__reset_vector::
ljmp s_GSINIT
;; 13 8-byte entries. We point them all at __isr_nop
ljmp __isr_nop ; 3 bytes
.ds 5 ; + 5 = 8 bytes for vector slot
ljmp __isr_nop
.ds 5
ljmp __isr_nop
.ds 5
ljmp __isr_nop
.ds 5
ljmp __isr_nop
.ds 5
ljmp __isr_nop
.ds 5
ljmp __isr_nop
.ds 5
ljmp __isr_nop
.ds 5
ljmp __isr_nop
.ds 5
ljmp __isr_nop
.ds 5
ljmp __isr_nop
.ds 5
ljmp __isr_nop
.ds 5
ljmp __isr_nop
.ds 5
 
__isr_nop::
reti
 
;;; ----------------------------------------------------------------
;;; the FIFO/GPIF autovector. 14 4-byte entries.
;;; must start on a 128 byte boundary.
;;; ----------------------------------------------------------------
. = __reset_vector + 0x0080
__fifo_gpif_autovector::
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
 
;;; ----------------------------------------------------------------
;;; the USB autovector. 32 4-byte entries.
;;; must start on a 256 byte boundary.
;;; ----------------------------------------------------------------
 
. = __reset_vector + 0x0100
__usb_autovector::
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
ljmp __isr_nop
nop
/trunk/GECKO4com/fx2_firmware/c/delay.c
0,0 → 1,76
/* -*- c++ -*- */
/*
* Copyright 2003 Free Software Foundation, Inc.
*
* This file is part of GNU Radio
*
* GNU Radio is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3, or (at your option)
* any later version.
*
* GNU Radio is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GNU Radio; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
 
/*
* Delay approximately 1 microsecond (including overhead in udelay).
*/
static void
udelay1 (void) _naked
{
_asm ; lcall that got us here took 4 bus cycles
ret ; 4 bus cycles
_endasm;
}
 
/*
* delay for approximately usecs microseconds
*/
void
udelay (unsigned char usecs)
{
do {
udelay1 ();
} while (--usecs != 0);
}
 
 
/*
* Delay approximately 1 millisecond.
* We're running at 48 MHz, so we need 48,000 clock cycles.
*
* Note however, that each bus cycle takes 4 clock cycles (not obvious,
* but explains the factor of 4 problem below).
*/
static void
mdelay1 (void) _naked
{
_asm
mov dptr,#(-1200 & 0xffff)
002$:
inc dptr ; 3 bus cycles
mov a, dpl ; 2 bus cycles
orl a, dph ; 2 bus cycles
jnz 002$ ; 3 bus cycles
 
ret
_endasm;
}
 
void
mdelay (unsigned int msecs)
{
do {
mdelay1 ();
} while (--msecs != 0);
}
 
/trunk/GECKO4com/fx2_firmware/c/gecko4com_main.c
0,0 → 1,323
/******************************************************************************/
/* _ _ __ ____ */
/* / / | | / _| | __| */
/* | |_| | _ _ / / | |_ */
/* | _ | | | | | | | | _| */
/* | | | | | |_| | \ \_ | |__ */
/* |_| |_| \_____| \__| |____| microLab */
/* */
/* Bern University of Applied Sciences (BFH) */
/* Quellgasse 21 */
/* Room HG 4.33 */
/* 2501 Biel/Bienne */
/* Switzerland */
/* */
/* http://www.microlab.ch */
/******************************************************************************/
/* GECKO4COM
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
Parts of this code are based on the USRP2 firmware (GNU Radio Project),
version 3.0.2, Copyright 2003 Free Software Foundation, Inc
********************************************************************
*/
 
#include "fx2regs.h"
#include "isr.h"
#include "fx2utils.h"
#include "usb_common.h"
#include "usb_requests.h"
#include "syncdelay.h"
 
sbit at 0x80+0 PA0;
sbit at 0x80+1 PA1;
sbit at 0x80+2 PA2;
sbit at 0x80+3 PA3;
sbit at 0x80+4 PA4;
sbit at 0x80+5 PA5;
sbit at 0x80+6 PA6;
sbit at 0x80+7 PA7;
 
#define USB_TMC_STATUS_SUCCESS 1
#define USB_TMC_INDICATOR_PULSE_MASK 1<<2
#define USB_TMC_INITIATE_ABORT_BULK_OUT 1
#define USB_TMC_CHECK_ABORT_BULK_OUT_STATUS 2
#define USB_TMC_INITIATE_ABORT_BULK_IN 3
#define USB_TMC_CHECK_ABORT_BULK_IN_STATUS 4
#define USB_TMC_INITIATE_CLEAR 5
#define USB_TMC_CHECK_CLEAR_STATUS 6
#define USB_TMC_GET_CAPABILITIES 7
#define USB_TMC_INDICATOR_PULSE 64
#define USB_TMC_READ_STATUS_BYTE 128
 
#define IFCONFIG_INTERNAL_CLOCK 1<<7
#define IFCONFIG_INTERNAL_48MHZ_Clock 1<<6
#define IFCONFIG_DRIVE_IFCLK_PIN 1<<5
#define IFCONFIG_INVERT_IFCLK 1<<4
#define IFCONFIG_ASYNC_MODE 1<<3
#define IFCONFIG_USE_GSTATE 1<<2
#define IFCONFIG_USE_GPIF 2
#define IFCONFIG_USE_FIFOS 3
 
#define FIXED_EP2_PROG_FLAG 4
#define FIXED_EP4_PROG_FLAG 5
#define FIXED_EP6_PROG_FLAG 6
#define FIXED_EP8_PROG_FLAG 7
#define FIXED_EP2_EMPTY_FLAG 8
#define FIXED_EP4_EMPTY_FLAG 9
#define FIXED_EP6_EMPTY_FLAG 10
#define FIXED_EP8_EMPTY_FLAG 11
#define FIXED_EP2_FULL_FLAG 12
#define FIXED_EP4_FULL_FLAG 13
#define FIXED_EP6_FULL_FLAG 14
#define FIXED_EP8_FULL_FLAG 15
#define PORT_A_USE_FLAGD 1 << 7
#define PORT_A_USE_SLCS 1 << 6
#define PORT_A_USE_INT1 2
#define PORT_A_USE_INT0 1
#define PKTEND_ACTIVE_HIGH 1<<5
#define SLOE_ACTIVE_HIGH 1<<4
#define SLRD_ACTIVE_HIGH 1<<3
#define SLWR_ACTIVE_HIGH 1<<2
#define EMPTY_FLAG_ACTIVE_HIGH 2
#define FULL_FLAG_ACTIVE_HIGH 1
#define DISABLE_AUTO_ARMING 2
#define ENABLE_ENHANCED_PACKET_HANDLING 1
#define ACTIVE_ENDPOINT 1 << 7
#define IN_ENDPOINT 1<<6
#define ISOCHRONOUS_MODE 1 << 4
#define BULK_MODE 2 << 4
#define INTERRUPT_MODE 3 << 4
#define SIZE_1KB 1<<3
#define QUAD_BUFFERING 0
#define DOUBLE_BUFFERING 2
#define TRIPLE_BUFFERING 3
#define FIFO_IN_EARLY 1 << 6
#define FIFO_OUT_EARLY 1 << 5
#define FIFO_AUTO_OUT 1 << 4
#define FIFO_AUTO_IN 1 << 3
#define FIFO_ZEROLEN 1 << 2
#define FIFO_WORDWIDE 1
 
extern xdata char device_bus_attributes_hs[];
extern xdata char device_bus_attributes_fs[];
 
unsigned char app_class_cmd(void) {
switch (bRequestType) {
case 0xA1 : switch (bRequest) {
case USB_TMC_GET_CAPABILITIES :
EP0BUF[0] = USB_TMC_STATUS_SUCCESS;
EP0BUF[1] = 0;
EP0BUF[2] = 0;
EP0BUF[3] = 1;
EP0BUF[4] = USB_TMC_INDICATOR_PULSE_MASK;
EP0BUF[5] = 0;
EP0BUF[6] = 0;
EP0BUF[7] = 0;
EP0BUF[8] = 0;
EP0BUF[9] = 0;
EP0BUF[10] = 0;
EP0BUF[11] = 0;
EP0BUF[12] = 0;
EP0BUF[13] = 1;
EP0BUF[14] = 0;
EP0BUF[15] = 0;
EP0BUF[16] = 0;
EP0BUF[17] = 0;
EP0BUF[18] = 0;
EP0BUF[19] = 0;
EP0BUF[20] = 0;
EP0BUF[21] = 0;
EP0BUF[22] = 0;
EP0BUF[23] = 0;
EP0BCH = 0;
EP0BCL = 0x18;
return 1;
case USB_TMC_INDICATOR_PULSE :
IOD = 0xEF; /* indicator pulse */
EP0BUF[0] = USB_TMC_STATUS_SUCCESS;
IOD = 0xFF;
EP0BCH = 0;
EP0BCL = 1;
return 1;
case USB_TMC_INITIATE_CLEAR :
/* reset the stuff in the FPGA */
PA1 = 1;
NOP;
PA1 = 0;
EP0BUF[0] = USB_TMC_STATUS_SUCCESS;
EP0BCH = 0;
EP0BCL = 1;
return 1;
case USB_TMC_CHECK_CLEAR_STATUS :
EP0BUF[0] = USB_TMC_STATUS_SUCCESS;
EP0BUF[1] = 0;
EP0BCH = 0;
EP0BCL = 2;
return 1;
case USB_TMC_READ_STATUS_BYTE :
IOD = 0xFF; /* select the USB488 status word */
EP0BUF[0] = USB_TMC_STATUS_SUCCESS;
EP0BUF[1] = wValueL;
EP0BUF[2] = (IOD&0xF)<<2;/*status byte*/
EP0BCH = 0;
EP0BCL = 3;
return 1;
default : break;
}
/* TODO: finish the abort handling! */
case 0xA2 : switch (bRequest) {
case USB_TMC_INITIATE_ABORT_BULK_OUT :
IOD = 0xCF; /* read btag lo nibble */
EP0BUF[0] = USB_TMC_STATUS_SUCCESS;
EP0BUF[1] = IOD&0xF;
IOD= 0xDF; /* read btag hi nibble */
EP0BCH = 0;
EP0BUF[1] |= (IOD&0xF)<<4;
EP0BCL = 2;
return 1;
case USB_TMC_CHECK_ABORT_BULK_OUT_STATUS :
EP0BUF[0] = USB_TMC_STATUS_SUCCESS;
EP0BUF[1] = 0;
EP0BUF[2] = 0;
EP0BUF[3] = 0;
EP0BUF[4] = 0;
EP0BUF[5] = 0;
EP0BUF[6] = 0;
EP0BUF[7] = 0;
EP0BCH = 0;
EP0BCL = 8;
return 1;
case USB_TMC_INITIATE_ABORT_BULK_IN :
IOD = 0xCF; /* read btag lo nibble */
EP0BUF[0] = USB_TMC_STATUS_SUCCESS;
EP0BUF[1] = IOD&0xF;
IOD= 0xDF; /* read btag hi nibble */
EP0BCH = 0;
EP0BUF[1] |= (IOD&0xF)<<4;
EP0BCL = 2;
return 1;
case USB_TMC_CHECK_ABORT_BULK_IN_STATUS :
EP0BUF[0] = USB_TMC_STATUS_SUCCESS;
EP0BUF[1] = 0;
EP0BUF[2] = 0;
EP0BUF[3] = 0;
EP0BUF[4] = 0;
EP0BUF[5] = 0;
EP0BUF[6] = 0;
EP0BUF[7] = 0;
EP0BCH = 0;
EP0BCL = 8;
return 1;
default : break;
}
default : break;
}
return 0;
}
 
unsigned char app_vendor_cmd(void) {
return 0;
}
 
void setup_endpoint_fifos() {
/* IMPORTANT: Endpoint configurations:
EP6 => USBTMC IN endpoint (to PC) double buffered 512 bytes
EP8 => USBTMC OUT endpoint (from PC) double buffered 512 bytes
both endpoints are 8 bytes fifo
*/
IFCONFIG = IFCONFIG_USE_FIFOS;
SYNCDELAY;
SYNCDELAY;
PORTACFG = PORT_A_USE_FLAGD | PORT_A_USE_INT0;
SYNCDELAY;
PINFLAGSAB = (FIXED_EP6_FULL_FLAG << 4)|
FIXED_EP8_EMPTY_FLAG; /* Flag B is EP6 Full Flag; Flag A is EP8 Empty Flag */
SYNCDELAY;
PINFLAGSCD = (FIXED_EP4_FULL_FLAG << 4)|
FIXED_EP2_EMPTY_FLAG;
SYNCDELAY;
FIFOPINPOLAR = 0; /* All FIFO signals active low */
SYNCDELAY;
REVCTL = 0; /* Auto Arming and no enhanced packet handling */
SYNCDELAY;
EP2CFG=0; /* Disabled endpoint */
SYNCDELAY;
EP4CFG=0; /* Disabled endpoint */
SYNCDELAY;
EP6CFG=ACTIVE_ENDPOINT|IN_ENDPOINT|BULK_MODE|DOUBLE_BUFFERING;
SYNCDELAY;
EP8CFG=ACTIVE_ENDPOINT|BULK_MODE; /* fixed to double buffering ! */
SYNCDELAY;
EP2FIFOCFG = 0;
SYNCDELAY;
EP4FIFOCFG = 0;
SYNCDELAY;
EP6FIFOCFG = 0;
SYNCDELAY;
EP8FIFOCFG = 0;
SYNCDELAY; /* Set all FIFOs to passive byte wide */
 
FIFORESET=0x80;
SYNCDELAY;
FIFORESET=0x02;
SYNCDELAY;
FIFORESET=0x04;
SYNCDELAY;
FIFORESET=0x06;
SYNCDELAY;
FIFORESET=0x08;
SYNCDELAY;
FIFORESET=0x00;
SYNCDELAY; /* Reset all FIFOs */
EP8FIFOCFG=FIFO_AUTO_OUT|FIFO_OUT_EARLY; /* Autoout and OUTEARLY */
SYNCDELAY;
EP6FIFOCFG=FIFO_IN_EARLY;
SYNCDELAY;
 
}
 
 
 
void main(void) {
EA = 0; /* disable all interrupts */
 
PA1 = 1; /* indicate to the FPGA that the FX2 is still setting up things */
PA3 = 0; /* Indicate to the FPGA that the FX2 uses full speed */
OEA = 1<<3|1<<1; /* PA1 and PA3 are set to output, the rest of the pins as input */
setup_autovectors();
usb_install_handlers();
setup_endpoint_fifos();
OED = 0xF0; /* The high 4 pins of the d-port are outputs the low 4 are inputs */
IOD = 0xFF; /* select the USB488 status word */
EA = 1; /* enable all interrupts */
fx2_renumerate();
/* now everything should be fine */
PA1 = 0; /* indicate to the FPGA that the FX2 is ready */
 
while (1) {
if(usb_setup_packet_avail()) usb_handle_setup_packet();
}
}
/trunk/GECKO4com/fx2_firmware/c/fx2utils.c
0,0 → 1,54
/* -*- c++ -*- */
/*
* Copyright 2003 Free Software Foundation, Inc.
*
* This file is part of GNU Radio
*
* GNU Radio is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3, or (at your option)
* any later version.
*
* GNU Radio is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GNU Radio; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
 
#include "fx2utils.h"
#include "fx2regs.h"
#include "delay.h"
 
void
fx2_stall_ep0 (void)
{
EP0CS |= bmEPSTALL;
}
 
void
fx2_reset_data_toggle (unsigned char ep)
{
TOGCTL = ((ep & 0x80) >> 3 | (ep & 0x0f));
TOGCTL |= bmRESETTOGGLE;
}
 
void
fx2_renumerate (void)
{
USBCS |= bmDISCON | bmRENUM;
 
// mdelay (1500); // FIXME why 1.5 seconds?
mdelay (250); // FIXME why 0.25 seconds?
USBIRQ = 0xff; // clear any pending USB irqs...
EPIRQ = 0xff; // they're from before the renumeration
 
EXIF &= ~bmEXIF_USBINT;
 
USBCS &= ~bmDISCON; // reconnect USB
}
/trunk/GECKO4com/fx2_firmware/c/timer.c
0,0 → 1,52
/* -*- c++ -*- */
/*
* Copyright 2003 Free Software Foundation, Inc.
*
* This file is part of GNU Radio
*
* GNU Radio is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3, or (at your option)
* any later version.
*
* GNU Radio is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GNU Radio; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
 
/************************************************************************/
/** \file timer.c
************************************************************************/
 
#include "timer.h"
#include "fx2regs.h"
#include "isr.h"
 
/**
* Arrange to have isr_tick_handler called at 100 Hz.
*
* The cpu clock is running at 48e6. The input to the timer
* is 48e6 / 12 = 4e6.
*
* We arrange to have the timer overflow every 40000 clocks == 100 Hz
*/
#define RELOAD_VALUE ((unsigned short) -40000)
 
void
hook_timer_tick (unsigned short isr_tick_handler)
{
ET2 = 0; /* disable timer 2 interrupts */
hook_sv (SV_TIMER_2, isr_tick_handler);
RCAP2H = RELOAD_VALUE >> 8; /* setup the auto reload value */
RCAP2L = RELOAD_VALUE;
 
T2CON = 0x04; /* interrupt on overflow; reload; run */
ET2 = 1; /* enable timer 2 interrupts */
}
/trunk/GECKO4com/fx2_firmware/c/usb_common.c
0,0 → 1,397
/* -*- c++ -*- */
/*
* Copyright 2003 Free Software Foundation, Inc.
*
* This file is part of GNU Radio
*
* GNU Radio is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3, or (at your option)
* any later version.
*
* GNU Radio is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GNU Radio; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
 
#include <stdint.h>
#include <stdio.h>
 
#include "usb_common.h"
#include "fx2regs.h"
#include "syncdelay.h"
#include "fx2utils.h"
#include "isr.h"
#include "usb_descriptors.h"
#include "usb_requests.h"
 
extern xdata char str0[];
extern xdata char str1[];
extern xdata char str2[];
extern xdata char str3[];
extern xdata char str4[];
extern xdata char str5[];
 
 
sbit at 0x80+0 PA0;
sbit at 0x80+1 PA1;
sbit at 0x80+2 PA2;
sbit at 0x80+3 PA3;
sbit at 0x80+4 PA4;
sbit at 0x80+5 PA5;
sbit at 0x80+6 PA6;
sbit at 0x80+7 PA7;
 
#define MSB(x) (((unsigned short) x) >> 8)
#define LSB(x) (((unsigned short) x) & 0xff)
 
volatile bit _usb_got_SUDAV;
 
unsigned char _usb_config = 0;
unsigned char _usb_alt_setting = 0; // FIXME really 1/interface
 
xdata unsigned char *current_device_descr;
xdata unsigned char *current_devqual_descr;
xdata unsigned char *current_config_descr;
xdata unsigned char *other_config_descr;
 
static void
setup_descriptors (void)
{
if (USBCS & bmHSM){ // high speed mode
current_device_descr = high_speed_device_descr;
current_devqual_descr = high_speed_devqual_descr;
current_config_descr = high_speed_config_descr;
other_config_descr = full_speed_config_descr;
PA3 = 1; /* Indicate to the FPGA that we are in full speed */
}
else {
current_device_descr = full_speed_device_descr;
current_devqual_descr = full_speed_devqual_descr;
current_config_descr = full_speed_config_descr;
other_config_descr = high_speed_config_descr;
PA3 = 0; /* Indicate to the FPGA that we are in high speed */
}
// whack the type fields
// FIXME, may not be required.
// current_config_descr[1] = DT_CONFIG;
// other_config_descr[1] = DT_OTHER_SPEED;
}
 
static void
isr_SUDAV (void) interrupt
{
clear_usb_irq ();
_usb_got_SUDAV = 1;
}
 
static void
isr_USBRESET (void) interrupt
{
clear_usb_irq ();
setup_descriptors ();
 
}
 
static void
isr_HIGHSPEED (void) interrupt
{
clear_usb_irq ();
setup_descriptors ();
}
 
void
usb_install_handlers (void)
{
setup_descriptors (); // ensure that they're set before use
 
hook_uv (UV_SUDAV, (unsigned short) isr_SUDAV);
hook_uv (UV_USBRESET, (unsigned short) isr_USBRESET);
hook_uv (UV_HIGHSPEED, (unsigned short) isr_HIGHSPEED);
 
USBIE = bmSUDAV | bmURES | bmHSGRANT;
}
 
/** On the FX2 the only plausible endpoints are 0, 1, 2, 4, 6, 8
* This doesn't check to see that they're enabled */
unsigned char
plausible_endpoint (unsigned char ep)
{
ep &= ~0x80; // ignore direction bit
 
if (ep > 8)
return 0;
 
if (ep == 1)
return 1;
 
return (ep & 0x1) == 0; // must be even
}
 
/** return pointer to control and status register for endpoint.
* only called with plausible_endpoints */
xdata volatile unsigned char *
epcs (unsigned char ep)
{
if (ep == 0x01) // ep1 has different in and out CS regs
return &EP1OUTCS;
 
if (ep == 0x81)
return &EP1INCS;
 
ep &= ~0x80; // ignore direction bit
 
if (ep == 0x00) // ep0
return &EP0CS;
 
//return EP2CS + (ep >> 1); // 2, 4, 6, 8 are consecutive
return &EP1INCS + (ep >> 1); // EP2CS -1; 2, 4, 6, 8 are consecutive
}
 
void
usb_handle_setup_packet (void)
{
_usb_got_SUDAV = 0;
 
switch (bRequestType & bmRT_TYPE_MASK){
 
case bmRT_TYPE_CLASS:
// call the application code class requests.
// If it handles the command it returns non-zero
 
if (!app_class_cmd ())
fx2_stall_ep0 ();
break;
 
case bmRT_TYPE_RESERVED:
fx2_stall_ep0 (); // we don't handle these. indicate error
break;
case bmRT_TYPE_VENDOR:
// call the application code for vendor commands.
// If it handles the command it returns non-zero
 
if (!app_vendor_cmd ())
fx2_stall_ep0 ();
break;
 
case bmRT_TYPE_STD:
// these are the standard requests...
 
if ((bRequestType & bmRT_DIR_MASK) == bmRT_DIR_IN){
 
////////////////////////////////////
// handle the IN requests
////////////////////////////////////
 
switch (bRequest){
 
case RQ_GET_CONFIG:
EP0BUF[0] = _usb_config; // FIXME app should handle
EP0BCH = 0;
EP0BCL = 1;
break;
// --------------------------------
 
case RQ_GET_INTERFACE:
EP0BUF[0] = _usb_alt_setting; // FIXME app should handle
EP0BCH = 0;
EP0BCL = 1;
break;
 
// --------------------------------
 
case RQ_GET_DESCR:
switch (wValueH){
 
case DT_DEVICE:
SUDPTRH = MSB (current_device_descr);
SUDPTRL = LSB (current_device_descr);
break;
case DT_DEVQUAL:
SUDPTRH = MSB (current_devqual_descr);
SUDPTRL = LSB (current_devqual_descr);
break;
 
case DT_CONFIG:
if (0 && wValueL != 1) // FIXME only a single configuration
fx2_stall_ep0 ();
else {
SUDPTRH = MSB (current_config_descr);
SUDPTRL = LSB (current_config_descr);
}
break;
 
case DT_OTHER_SPEED:
if (0 && wValueL != 1) // FIXME only a single configuration
fx2_stall_ep0 ();
else {
SUDPTRH = MSB (other_config_descr);
SUDPTRL = LSB (other_config_descr);
}
break;
 
case DT_STRING:
if (wValueL >= nstring_descriptors)
fx2_stall_ep0 ();
else {
xdata char *p = string_descriptors[wValueL];
SUDPTRH = MSB (p);
SUDPTRL = LSB (p);
}
break;
 
default:
fx2_stall_ep0 (); // invalid request
break;
}
break;
// --------------------------------
 
case RQ_GET_STATUS:
switch (bRequestType & bmRT_RECIP_MASK){
case bmRT_RECIP_DEVICE:
EP0BUF[0] = bmGSDA_SELF_POWERED; // FIXME app should handle
EP0BUF[1] = 0;
EP0BCH = 0;
EP0BCL = 2;
break;
 
case bmRT_RECIP_INTERFACE:
EP0BUF[0] = 0;
EP0BUF[1] = 0;
EP0BCH = 0;
EP0BCL = 2;
break;
 
case bmRT_RECIP_ENDPOINT:
if (plausible_endpoint (wIndexL)){
EP0BUF[0] = *epcs (wIndexL) & bmEPSTALL;
EP0BUF[1] = 0;
EP0BCH = 0;
EP0BCL = 2;
}
else
fx2_stall_ep0 ();
break;
 
default:
fx2_stall_ep0 ();
break;
}
break;
 
// --------------------------------
 
case RQ_SYNCH_FRAME: // not implemented
default:
fx2_stall_ep0 ();
break;
}
}
 
else {
 
////////////////////////////////////
// handle the OUT requests
////////////////////////////////////
 
switch (bRequest){
 
case RQ_SET_CONFIG:
_usb_config = wValueL; // FIXME app should handle
break;
 
case RQ_SET_INTERFACE:
_usb_alt_setting = wValueL; // FIXME app should handle
break;
 
// --------------------------------
 
case RQ_CLEAR_FEATURE:
switch (bRequestType & bmRT_RECIP_MASK){
 
case bmRT_RECIP_DEVICE:
switch (wValueL){
case FS_DEV_REMOTE_WAKEUP:
default:
fx2_stall_ep0 ();
}
break;
 
case bmRT_RECIP_ENDPOINT:
if (wValueL == FS_ENDPOINT_HALT && plausible_endpoint (wIndexL)){
*epcs (wIndexL) &= ~bmEPSTALL;
EP2CS &= ~bmEPSTALL;
fx2_reset_data_toggle (wIndexL);
}
else
fx2_stall_ep0 ();
break;
 
default:
fx2_stall_ep0 ();
break;
}
break;
 
// --------------------------------
 
case RQ_SET_FEATURE:
switch (bRequestType & bmRT_RECIP_MASK){
 
case bmRT_RECIP_DEVICE:
switch (wValueL){
case FS_TEST_MODE:
// hardware handles this after we complete SETUP phase handshake
break;
 
case FS_DEV_REMOTE_WAKEUP:
default:
fx2_stall_ep0 ();
break;
}
}
break;
 
case bmRT_RECIP_ENDPOINT:
switch (wValueL){
case FS_ENDPOINT_HALT:
if (plausible_endpoint (wIndexL))
*epcs (wIndexL) |= bmEPSTALL;
else
fx2_stall_ep0 ();
break;
 
default:
fx2_stall_ep0 ();
break;
}
break;
 
// --------------------------------
 
case RQ_SET_ADDRESS: // handled by fx2 hardware
case RQ_SET_DESCR: // not implemented
default:
fx2_stall_ep0 ();
}
 
}
break;
 
} // bmRT_TYPE_MASK
 
// ack handshake phase of device request
EP0CS |= bmHSNAK;
}
/trunk/GECKO4com/fx2_firmware/c/include/usb_descriptors.h
0,0 → 1,82
/******************************************************************************/
/* _ _ __ ____ */
/* / / | | / _| | __| */
/* | |_| | _ _ / / | |_ */
/* | _ | | | | | | | | _| */
/* | | | | | |_| | \ \_ | |__ */
/* |_| |_| \_____| \__| |____| microLab */
/* */
/* Bern University of Applied Sciences (BFH) */
/* Quellgasse 21 */
/* Room HG 4.33 */
/* 2501 Biel/Bienne */
/* Switzerland */
/* */
/* http://www.microlab.ch */
/******************************************************************************/
/* GECKO4COM
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
 
/*********************************************************************/
/** \file usb_descriptors.h
*********************************************************************
* \brief header file for the USB descriptors. The descriptors are
* defined outside in the usb_descriptor.a51 file.
*
* \author GNUradio, Christoph Zimmermann bfh.ch
*
*/
 
/** USB High speed device descriptor */
extern xdata const char high_speed_device_descr[];
/** USB High speed device qualifier descriptor */
extern xdata const char high_speed_devqual_descr[];
/** USB High speed configuration descriptor */
extern xdata const char high_speed_config_descr[];
 
/** USB Full speed device descriptor */
extern xdata const char full_speed_device_descr[];
/** USB Full speed device qualifier descriptor */
extern xdata const char full_speed_devqual_descr[];
/** USB Full speed configuration descriptor */
extern xdata const char full_speed_config_descr[];
 
#ifdef USB_DFU_SUPPORT
/** USB DFU mode device descriptor */
extern xdata const char dfu_mode_device_descr[];
/** USB DFU mode configuration descriptor */
extern xdata const char dfu_mode_config_descr[];
/** USB DFU mode functional descriptor */
extern xdata const char dfu_mode_functional_descr[];
#endif
 
/** Number of USB String descriptors available */
extern xdata unsigned char nstring_descriptors;
 
/** USB String descriptors */
extern xdata char * xdata string_descriptors[];
 
/** We patch these locations with info read from the config eeprom */
extern xdata char usb_desc_hw_rev_binary_patch_location_0[];
/** We patch these locations with info read from the config eeprom */
extern xdata char usb_desc_hw_rev_binary_patch_location_1[];
/** We patch these locations with info read from the config eeprom */
extern xdata char usb_desc_hw_rev_binary_patch_location_2[];
/** We patch these locations with info read from the config eeprom */
/*extern xdata char usb_desc_hw_rev_ascii_patch_location_0[];*/
/** We patch these locations with info read from the config eeprom */
extern xdata char usb_desc_serial_number_ascii[];
 
/trunk/GECKO4com/fx2_firmware/c/include/syncdelay.h
0,0 → 1,76
/* -*- c++ -*- */
/*
* Copyright 2003 Free Software Foundation, Inc.
*
* This file is part of GNU Radio
*
* GNU Radio is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3, or (at your option)
* any later version.
*
* GNU Radio is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GNU Radio; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
 
/************************************************************************/
/** \file syncdelay.h
*************************************************************************
*
* \author GNU Radio
*
*/
 
#ifndef _SYNCDELAY_H_
#define _SYNCDELAY_H_
 
/**
* \brief Magic delay required between access to certain xdata registers (TRM page 15-106).
*
* For our configuration, 48 MHz FX2 / 48 MHz IFCLK, we need three cycles. Each
* NOP is a single cycle....
*
* From TRM page 15-105:
*
* Under certain conditions, some read and write access to the FX2 registers must
* be separated by a "synchronization delay". The delay is necessary only under the
* following conditions:
*
* - between a write to any register in the 0xE600 - 0xE6FF range and a write to one
* of the registers listed below.
*
* - between a write to one of the registers listed below and a read from any register
* in the 0xE600 - 0xE6FF range.
*
* Registers which require a synchronization delay:
*
* FIFORESET FIFOPINPOLAR
* INPKTEND EPxBCH:L
* EPxFIFOPFH:L EPxAUTOINLENH:L
* EPxFIFOCFG EPxGPIFFLGSEL
* PINFLAGSAB PINFLAGSCD
* EPxFIFOIE EPxFIFOIRQ
* GPIFIE GPIFIRQ
* UDMACRCH:L GPIFADRH:L
* GPIFTRIG EPxGPIFTRIG
* OUTPKTEND REVCTL
* GPIFTCB3 GPIFTCB2
* GPIFTCB1 GPIFTCB0
*
*
* FIXME ensure that the peep hole optimizer isn't screwing us
*/
#define SYNCDELAY _asm nop nop nop; nop; nop; nop; _endasm
 
/** no operation, idle for ony cycle */
#define NOP _asm nop; _endasm
 
 
#endif /* _SYNCDELAY_H_ */
/trunk/GECKO4com/fx2_firmware/c/include/isr.h
0,0 → 1,176
/* -*- c++ -*- */
/*
* Copyright 2003 Free Software Foundation, Inc.
*
* This file is part of GNU Radio
*
* GNU Radio is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3, or (at your option)
* any later version.
*
* GNU Radio is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GNU Radio; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
 
#ifndef _ISR_H_
#define _ISR_H_
 
/************************************************************************/
/** \file isr.h
*************************************************************************
* \brief routines for managing interrupt services routines
*
* The FX2 has three discrete sets of interrupt vectors.
* The first set is the standard 8051 vector (13 8-byte entries).
* The second set is USB interrupt autovector (32 4-byte entries).
* The third set is the FIFO/GPIF autovector (14 4-byte entries).
*
* Since all the code we're running in the FX2 is ram based, we
* forego the typical "initialize the interrupt vectors at link time"
* strategy, in favor of calls at run time that install the correct
* pointers to functions.
*
* \author GNU Radio
*/
 
/*
* Standard Vector numbers
*/
 
#define SV_INT_0 0x03 /**< INT0 Pin */
#define SV_TIMER_0 0x0b /**< Timer 0 Overflow */
#define SV_INT_1 0x13 /**< INT1 Pin */
#define SV_TIMER_1 0x1b /**< Timer 1 Overflow */
#define SV_SERIAL_0 0x23 /**< USART 0 Rx & Tx */
#define SV_TIMER_2 0x2b /**< Timer 2 Overflow */
#define SV_RESUME 0x33 /**< WAKEUP / WU2 Pin or USB Resume */
#define SV_SERIAL_1 0x3b /**< USART 1 Rx & Tx */
#define SV_INT_2 0x43 /**< (INT_2) points at USB autovector */
#define SV_I2C 0x4b /**< I2C Bus */
#define SV_INT_4 0x53 /**< (INT_4) points at FIFO/GPIF autovector */
#define SV_INT_5 0x5b /**< INT5 Pin */
#define SV_INT_6 0x63 /**< INT6 Pin */
 
#define SV_MIN SV_INT_0
#define SV_MAX SV_INT_6
 
/*
* USB Auto Vector numbers
*/
 
#define UV_SUDAV 0x00 /**< SETUP Data Available */
#define UV_SOF 0x04 /**< Start of Frame (or Microframe) */
#define UV_SUTOK 0x08 /**< Setup Token Received */
#define UV_SUSPEND 0x0c /**< USB Suspend request */
#define UV_USBRESET 0x10 /**< Bus Reset */
#define UV_HIGHSPEED 0x14 /**< Entered high speed operation */
#define UV_EP0ACK 0x18 /**< EZ-USB ACK'd the CONTROL Handshake */
#define UV_SPARE_1C 0x1c
#define UV_EP0IN 0x20 /**< EP0-IN ready to be loaded with data */
#define UV_EP0OUT 0x24 /**< EP0-OUT has USB data */
#define UV_EP1IN 0x28 /**< EP1-IN ready to be loaded with data */
#define UV_EP1OUT 0x2c /**< EP1-OUT has USB data */
#define UV_EP2 0x30 /**< IN: buffer available. OUT: buffer has data */
#define UV_EP4 0x34 /**< IN: buffer available. OUT: buffer has data */
#define UV_EP6 0x38 /**< IN: buffer available. OUT: buffer has data */
#define UV_EP8 0x3c /**< IN: buffer available. OUT: buffer has data */
#define UV_IBN 0x40 /**< IN-Bulk-NAK (any IN endpoint) */
#define UV_SPARE_44 0x44
#define UV_EP0PINGNAK 0x48 /**< EP0 OUT was Pinged and it NAK'd */
#define UV_EP1PINGNAK 0x4c /**< EP1 OUT was Pinged and it NAK'd */
#define UV_EP2PINGNAK 0x50 /**< EP2 OUT was Pinged and it NAK'd */
#define UV_EP4PINGNAK 0x54 /**< EP4 OUT was Pinged and it NAK'd */
#define UV_EP6PINGNAK 0x58 /**< EP6 OUT was Pinged and it NAK'd */
#define UV_EP8PINGNAK 0x5c /**< EP8 OUT was Pinged and it NAK'd */
#define UV_ERRLIMIT 0x60 /**< Bus errors exceeded the programmed limit */
#define UV_SPARE_64 0x64
#define UV_SPARE_68 0x68
#define UV_SPARE_6C 0x6c
#define UV_EP2ISOERR 0x70 /**< ISO EP2 OUT PID sequence error */
#define UV_EP4ISOERR 0x74 /**< ISO EP4 OUT PID sequence error */
#define UV_EP6ISOERR 0x78 /**< ISO EP6 OUT PID sequence error */
#define UV_EP8ISOERR 0x7c /**< ISO EP8 OUT PID sequence error */
 
#define UV_MIN UV_SUDAV
#define UV_MAX UV_EP8ISOERR
 
/*
* FIFO/GPIF Auto Vector numbers
*/
 
#define FGV_EP2PF 0x00 /**< Endpoint 2 Programmable Flag */
#define FGV_EP4PF 0x04 /**< Endpoint 4 Programmable Flag */
#define FGV_EP6PF 0x08 /**< Endpoint 6 Programmable Flag */
#define FGV_EP8PF 0x0c /**< Endpoint 8 Programmable Flag */
#define FGV_EP2EF 0x10 /**< Endpoint 2 Empty Flag */
#define FGV_EP4EF 0x14 /**< Endpoint 4 Empty Flag */
#define FGV_EP6EF 0x18 /**< Endpoint 6 Empty Flag */
#define FGV_EP8EF 0x1c /**< Endpoint 8 Empty Flag */
#define FGV_EP2FF 0x20 /**< Endpoint 2 Full Flag */
#define FGV_EP4FF 0x24 /**< Endpoint 4 Full Flag */
#define FGV_EP6FF 0x28 /**< Endpoint 6 Full Flag */
#define FGV_EP8FF 0x2c /**< Endpoint 8 Full Flag */
#define FGV_GPIFDONE 0x30 /**< GPIF Operation Complete */
#define FGV_GPIFWF 0x34 /**< GPIF Waveform */
 
#define FGV_MIN FGV_EP2PF
#define FGV_MAX FGV_GPIFWF
 
 
/**
* \brief Hook standard interrupt vector.
*
* \param[in] vector_number is from the SV_<foo> list above.
* \param[in] addr is the address of the interrupt service routine.
*/
void hook_sv (unsigned char vector_number, unsigned short addr);
 
/**
* \brief Hook usb interrupt vector.
*
* \param[in] vector_number is from the UV_<foo> list above.
* \param[in] addr is the address of the interrupt service routine.
*/
void hook_uv (unsigned char vector_number, unsigned short addr);
 
/**
* \brief Hook fifo/gpif interrupt vector.
*
* \param[in] vector_number is from the FGV_<foo> list above.
* \param[in] addr is the address of the interrupt service routine.
*/
void hook_fgv (unsigned char vector_number, unsigned short addr);
 
/**
* One time call to enable autovectoring for both USB and FIFO/GPIF
*/
void setup_autovectors (void);
 
 
/**
* Makro to clear the pending USB interrrupt
*
* \warning Must be called in each usb interrupt handler
*/
#define clear_usb_irq() \
EXIF &= ~bmEXIF_USBINT; \
INT2CLR = 0
 
/**
* Makro to clear the pending FIFO/GPIF interrupt
*
* \warning Must be called in each fifo/gpif interrupt handler
*/
#define clear_fifo_gpif_irq() \
EXIF &= ~bmEXIF_IE4; \
INT4CLR = 0
 
#endif /* _ISR_H_ */
/trunk/GECKO4com/fx2_firmware/c/include/i2c.h
0,0 → 1,57
/* -*- c++ -*- */
/*
* Copyright 2003 Free Software Foundation, Inc.
*
* This file is part of GNU Radio
*
* GNU Radio is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3, or (at your option)
* any later version.
*
* GNU Radio is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GNU Radio; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
 
/************************************************************************/
/** \file i2c.h
*************************************************************************
* \brief read and write functions for the i2c bus
*
* \author GNU Radio
*
* \warning This functions are blocking functions, so you have to wait
* until the transfer is finished!
*/
 
#ifndef _I2C_H_
#define _I2C_H_
 
/**
* i2c read function. reads a block of data with the length len
*
* \param[in] addr device adress on the i2c bus
* \param[out] buf result buffer, contains the readed data when successful
* \param[in] len length of the block to read
* \return returns non-zero if successful, else 0
*/
unsigned char i2c_read (unsigned char addr, xdata unsigned char *buf, unsigned char len);
 
/**
* i2c write function. writes a block of data with the length len
*
* \param[in] addr device adress on the i2c bus
* \param[in] buf data buffer, contains the data to be written
* \param[in] len length of the block to write
* \return returns non-zero if successful, else 0
*/
unsigned char i2c_write (unsigned char addr, xdata const unsigned char *buf, unsigned char len);
 
#endif /* _I2C_H_ */
/trunk/GECKO4com/fx2_firmware/c/include/delay.h
0,0 → 1,50
/* -*- c++ -*- */
/*
* Copyright 2003 Free Software Foundation, Inc.
*
* This file is part of GNU Radio
*
* GNU Radio is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3, or (at your option)
* any later version.
*
* GNU Radio is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GNU Radio; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
 
/************************************************************************/
/** \file delay.h
*************************************************************************
* \brief delay routines for Cypress EZ-USB FX2
*
* \details provides functions for a 1 us and a 1 ms delay
*
* \author GNU Radio
*/
 
#ifndef _DELAY_H_
#define _DELAY_H_
 
/**
* delay for approximately usecs microseconds
* \param[in] usecs number of microseconds to wait
* \warning limit of 255 usecs.
*/
void udelay (unsigned char usecs);
 
/**
* delay for approximately msecs milliseconds
* \param[in] msecs number of milliseconds to wait
*/
void mdelay (unsigned short msecs);
 
 
#endif /* _DELAY_H_ */
/trunk/GECKO4com/fx2_firmware/c/include/timer.h
0,0 → 1,44
/* -*- c++ -*- */
/*
* Copyright 2003 Free Software Foundation, Inc.
*
* This file is part of GNU Radio
*
* GNU Radio is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3, or (at your option)
* any later version.
*
* GNU Radio is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GNU Radio; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
 
/************************************************************************/
/** \file timer.h
*************************************************************************
* \brief setup timer and interrupt handler to be called at 100 Hz
*
* \author GNU Radio
*/
 
#ifndef _TIMER_H_
#define _TIMER_H_
 
/**
* Arrange to have isr_tick_handler called at 100 Hz
*/
void hook_timer_tick (unsigned short isr_tick_handler);
 
/** Makro to clear the interrupt flag of timer 2 */
#define clear_timer_irq() \
TF2 = 0 /* clear overflow flag */
 
 
#endif /* _TIMER_H_ */
/trunk/GECKO4com/fx2_firmware/c/include/fx2utils.h
0,0 → 1,55
/* -*- c -*- */
/*
* Copyright 2003 Free Software Foundation, Inc.
*
* This file is part of GNU Radio
*
* GNU Radio is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3, or (at your option)
* any later version.
*
* GNU Radio is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GNU Radio; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
 
/************************************************************************/
/** \file fx2utils.h
*************************************************************************
* \brief small helper functions for the Cypress EZ-USB FX2
*
* \author GNU Radio
*
*/
 
#ifndef _FX2UTILS_H_
#define _FX2UTILS_H_
 
/** Stall the endpoint 0
*/
void fx2_stall_ep0 (void);
 
/**
* \brief Resets the data toggle bit of the endpoint ep
*
* A description of the function and purpose of the toggle bit and
* when the firmware has to reset it is in the EZ-USB Technical
* Reference Manual. Chapter 8 Page 16
* \param[in] ep Endpoint number
*/
void fx2_reset_data_toggle (unsigned char ep);
 
/** \brief Renumerate the FX2.
* This means a disconnect and reconnect from the USB bus */
void fx2_renumerate (void);
 
 
 
#endif /* _FX2UTILS_H_ */
/trunk/GECKO4com/fx2_firmware/c/include/fx2regs.h
0,0 → 1,738
/* -*- c++ -*- */
/*
* Copyright 2003 Free Software Foundation, Inc.
*
* This file is part of GNU Radio
*
* GNU Radio is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3, or (at your option)
* any later version.
*
* GNU Radio is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GNU Radio; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
 
/*********************************************************************/
/** \file fx2regs.h
*********************************************************************
* \brief EZ-USB FX2 register declarations and bit mask definitions.
*
* \par FX2 Related Register Assignments
*
* The Ez-USB FX2 registers are defined here. We use FX2regs.h for register
* address allocation by using "#define ALLOCATE_EXTERN".
* When using "#define ALLOCATE_EXTERN", you get (for instance): \n
* xdata volatile BYTE OUT7BUF[64] _at_ 0x7B40; \n
* Such lines are created from FX2.h by using the preprocessor. \n
* Incidently, these lines will not generate any space in the resulting hex
* file; they just bind the symbols to the addresses for compilation.
* You just need to put "#define ALLOCATE_EXTERN" in your main program file;
* i.e. fw.c or a stand-alone C source file. \n
* Without "#define ALLOCATE_EXTERN", you just get the external reference:
* extern xdata volatile BYTE OUT7BUF[64] ;// 0x7B40;
* This uses the concatenation operator "##" to insert a comment "//"
* to cut off the end of the line, "_at_ 0x7B40;", which is not wanted.
*
* \date Date: 2007-07-20 20:44:38 -0700 (Fri, 20 Jul 2007)
* \version 6044
* \author Copyright (c) 2000 Cypress Semiconductor, All rights reserved
*
*/
 
 
#ifndef FX2REGS_H /* Header Sentry */
#define FX2REGS_H
 
#define ALLOCATE_EXTERN /* required for "right thing to happen" with fx2regs.h */
 
 
#ifdef ALLOCATE_EXTERN
#define EXTERN
#define _AT_(a) at a
#else
#define EXTERN extern
#define _AT_ ;/ ## /
#endif
 
typedef unsigned char BYTE;
typedef unsigned short WORD;
 
EXTERN xdata _AT_(0xE400) volatile BYTE GPIF_WAVE_DATA[128]; /**< GPIF Waveform Data Table */
EXTERN xdata _AT_(0xE480) volatile BYTE RES_WAVEDATA_END ; /**< End of GPIF Waveform Data */
 
/* General Configuration */
 
EXTERN xdata _AT_(0xE600) volatile BYTE CPUCS ; /**< Control & Status */
EXTERN xdata _AT_(0xE601) volatile BYTE IFCONFIG ; /**< Interface Configuration */
EXTERN xdata _AT_(0xE602) volatile BYTE PINFLAGSAB ; /**< FIFO FLAGA and FLAGB Assignments */
EXTERN xdata _AT_(0xE603) volatile BYTE PINFLAGSCD ; /**< FIFO FLAGC and FLAGD Assignments */
EXTERN xdata _AT_(0xE604) volatile BYTE FIFORESET ; /**< Restore FIFOS to default state */
EXTERN xdata _AT_(0xE605) volatile BYTE BREAKPT ; /**< Breakpoint */
EXTERN xdata _AT_(0xE606) volatile BYTE BPADDRH ; /**< Breakpoint Address H */
EXTERN xdata _AT_(0xE607) volatile BYTE BPADDRL ; /**< Breakpoint Address L */
EXTERN xdata _AT_(0xE608) volatile BYTE UART230 ; /**< 230 Kbaud clock for T0,T1,T2 */
EXTERN xdata _AT_(0xE609) volatile BYTE FIFOPINPOLAR ; /**< FIFO polarities */
EXTERN xdata _AT_(0xE60A) volatile BYTE REVID ; /**< Chip Revision */
EXTERN xdata _AT_(0xE60B) volatile BYTE REVCTL ; /**< Chip Revision Control */
 
/* Endpoint Configuration */
 
EXTERN xdata _AT_(0xE610) volatile BYTE EP1OUTCFG ; /**< Endpoint 1-OUT Configuration */
EXTERN xdata _AT_(0xE611) volatile BYTE EP1INCFG ; /**< Endpoint 1-IN Configuration */
EXTERN xdata _AT_(0xE612) volatile BYTE EP2CFG ; /**< Endpoint 2 Configuration */
EXTERN xdata _AT_(0xE613) volatile BYTE EP4CFG ; /**< Endpoint 4 Configuration */
EXTERN xdata _AT_(0xE614) volatile BYTE EP6CFG ; /**< Endpoint 6 Configuration */
EXTERN xdata _AT_(0xE615) volatile BYTE EP8CFG ; /**< Endpoint 8 Configuration */
EXTERN xdata _AT_(0xE618) volatile BYTE EP2FIFOCFG ; /**< Endpoint 2 FIFO configuration */
EXTERN xdata _AT_(0xE619) volatile BYTE EP4FIFOCFG ; /**< Endpoint 4 FIFO configuration */
EXTERN xdata _AT_(0xE61A) volatile BYTE EP6FIFOCFG ; /**< Endpoint 6 FIFO configuration */
EXTERN xdata _AT_(0xE61B) volatile BYTE EP8FIFOCFG ; /**< Endpoint 8 FIFO configuration */
EXTERN xdata _AT_(0xE620) volatile BYTE EP2AUTOINLENH ; /**< Endpoint 2 Packet Length H (IN only) */
EXTERN xdata _AT_(0xE621) volatile BYTE EP2AUTOINLENL ; /**< Endpoint 2 Packet Length L (IN only) */
EXTERN xdata _AT_(0xE622) volatile BYTE EP4AUTOINLENH ; /**< Endpoint 4 Packet Length H (IN only) */
EXTERN xdata _AT_(0xE623) volatile BYTE EP4AUTOINLENL ; /**< Endpoint 4 Packet Length L (IN only) */
EXTERN xdata _AT_(0xE624) volatile BYTE EP6AUTOINLENH ; /**< Endpoint 6 Packet Length H (IN only) */
EXTERN xdata _AT_(0xE625) volatile BYTE EP6AUTOINLENL ; /**< Endpoint 6 Packet Length L (IN only) */
EXTERN xdata _AT_(0xE626) volatile BYTE EP8AUTOINLENH ; /**< Endpoint 8 Packet Length H (IN only) */
EXTERN xdata _AT_(0xE627) volatile BYTE EP8AUTOINLENL ; /**< Endpoint 8 Packet Length L (IN only) */
EXTERN xdata _AT_(0xE630) volatile BYTE EP2FIFOPFH ; /**< EP2 Programmable Flag trigger H */
EXTERN xdata _AT_(0xE631) volatile BYTE EP2FIFOPFL ; /**< EP2 Programmable Flag trigger L */
EXTERN xdata _AT_(0xE632) volatile BYTE EP4FIFOPFH ; /**< EP4 Programmable Flag trigger H */
EXTERN xdata _AT_(0xE633) volatile BYTE EP4FIFOPFL ; /**< EP4 Programmable Flag trigger L */
EXTERN xdata _AT_(0xE634) volatile BYTE EP6FIFOPFH ; /**< EP6 Programmable Flag trigger H */
EXTERN xdata _AT_(0xE635) volatile BYTE EP6FIFOPFL ; /**< EP6 Programmable Flag trigger L */
EXTERN xdata _AT_(0xE636) volatile BYTE EP8FIFOPFH ; /**< EP8 Programmable Flag trigger H */
EXTERN xdata _AT_(0xE637) volatile BYTE EP8FIFOPFL ; /**< EP8 Programmable Flag trigger L */
EXTERN xdata _AT_(0xE640) volatile BYTE EP2ISOINPKTS ; /**< EP2 (if ISO) IN Packets per frame (1-3) */
EXTERN xdata _AT_(0xE641) volatile BYTE EP4ISOINPKTS ; /**< EP4 (if ISO) IN Packets per frame (1-3) */
EXTERN xdata _AT_(0xE642) volatile BYTE EP6ISOINPKTS ; /**< EP6 (if ISO) IN Packets per frame (1-3) */
EXTERN xdata _AT_(0xE643) volatile BYTE EP8ISOINPKTS ; /**< EP8 (if ISO) IN Packets per frame (1-3) */
EXTERN xdata _AT_(0xE648) volatile BYTE INPKTEND ; /**< Force IN Packet End */
EXTERN xdata _AT_(0xE649) volatile BYTE OUTPKTEND ; /**< Force OUT Packet End */
 
/* Interrupts */
 
EXTERN xdata _AT_(0xE650) volatile BYTE EP2FIFOIE ; /**< Endpoint 2 Flag Interrupt Enable */
EXTERN xdata _AT_(0xE651) volatile BYTE EP2FIFOIRQ ; /**< Endpoint 2 Flag Interrupt Request */
EXTERN xdata _AT_(0xE652) volatile BYTE EP4FIFOIE ; /**< Endpoint 4 Flag Interrupt Enable */
EXTERN xdata _AT_(0xE653) volatile BYTE EP4FIFOIRQ ; /**< Endpoint 4 Flag Interrupt Request */
EXTERN xdata _AT_(0xE654) volatile BYTE EP6FIFOIE ; /**< Endpoint 6 Flag Interrupt Enable */
EXTERN xdata _AT_(0xE655) volatile BYTE EP6FIFOIRQ ; /**< Endpoint 6 Flag Interrupt Request */
EXTERN xdata _AT_(0xE656) volatile BYTE EP8FIFOIE ; /**< Endpoint 8 Flag Interrupt Enable */
EXTERN xdata _AT_(0xE657) volatile BYTE EP8FIFOIRQ ; /**< Endpoint 8 Flag Interrupt Request */
EXTERN xdata _AT_(0xE658) volatile BYTE IBNIE ; /**< IN-BULK-NAK Interrupt Enable */
EXTERN xdata _AT_(0xE659) volatile BYTE IBNIRQ ; /**< IN-BULK-NAK interrupt Request */
EXTERN xdata _AT_(0xE65A) volatile BYTE NAKIE ; /**< Endpoint Ping NAK interrupt Enable */
EXTERN xdata _AT_(0xE65B) volatile BYTE NAKIRQ ; /**< Endpoint Ping NAK interrupt Request */
EXTERN xdata _AT_(0xE65C) volatile BYTE USBIE ; /**< USB Int Enables */
EXTERN xdata _AT_(0xE65D) volatile BYTE USBIRQ ; /**< USB Interrupt Requests */
EXTERN xdata _AT_(0xE65E) volatile BYTE EPIE ; /**< Endpoint Interrupt Enables */
EXTERN xdata _AT_(0xE65F) volatile BYTE EPIRQ ; /**< Endpoint Interrupt Requests */
EXTERN xdata _AT_(0xE660) volatile BYTE GPIFIE ; /**< GPIF Interrupt Enable */
EXTERN xdata _AT_(0xE661) volatile BYTE GPIFIRQ ; /**< GPIF Interrupt Request */
EXTERN xdata _AT_(0xE662) volatile BYTE USBERRIE ; /**< USB Error Interrupt Enables */
EXTERN xdata _AT_(0xE663) volatile BYTE USBERRIRQ ; /**< USB Error Interrupt Requests */
EXTERN xdata _AT_(0xE664) volatile BYTE ERRCNTLIM ; /**< USB Error counter and limit */
EXTERN xdata _AT_(0xE665) volatile BYTE CLRERRCNT ; /**< Clear Error Counter EC[3..0] */
EXTERN xdata _AT_(0xE666) volatile BYTE INT2IVEC ; /**< Interupt 2 (USB) Autovector */
EXTERN xdata _AT_(0xE667) volatile BYTE INT4IVEC ; /**< Interupt 4 (FIFOS & GPIF) Autovector */
EXTERN xdata _AT_(0xE668) volatile BYTE INTSETUP ; /**< Interrupt 2&4 Setup */
 
/* Input/Output */
 
EXTERN xdata _AT_(0xE670) volatile BYTE PORTACFG ; /**< I/O PORTA Alternate Configuration */
EXTERN xdata _AT_(0xE671) volatile BYTE PORTCCFG ; /**< I/O PORTC Alternate Configuration */
EXTERN xdata _AT_(0xE672) volatile BYTE PORTECFG ; /**< I/O PORTE Alternate Configuration */
EXTERN xdata _AT_(0xE678) volatile BYTE I2CS ; /**< Control & Status */
EXTERN xdata _AT_(0xE679) volatile BYTE I2DAT ; /**< Data */
EXTERN xdata _AT_(0xE67A) volatile BYTE I2CTL ; /**< I2C Control */
EXTERN xdata _AT_(0xE67B) volatile BYTE XAUTODAT1 ; /**< Autoptr1 MOVX access */
EXTERN xdata _AT_(0xE67C) volatile BYTE XAUTODAT2 ; /**< Autoptr2 MOVX access */
 
#define EXTAUTODAT1 XAUTODAT1
#define EXTAUTODAT2 XAUTODAT2
 
/* USB Control */
 
EXTERN xdata _AT_(0xE680) volatile BYTE USBCS ; /**< USB Control & Status */
EXTERN xdata _AT_(0xE681) volatile BYTE SUSPEND ; /**< Put chip into suspend */
EXTERN xdata _AT_(0xE682) volatile BYTE WAKEUPCS ; /**< Wakeup source and polarity */
EXTERN xdata _AT_(0xE683) volatile BYTE TOGCTL ; /**< Toggle Control */
EXTERN xdata _AT_(0xE684) volatile BYTE USBFRAMEH ; /**< USB Frame count H */
EXTERN xdata _AT_(0xE685) volatile BYTE USBFRAMEL ; /**< USB Frame count L */
EXTERN xdata _AT_(0xE686) volatile BYTE MICROFRAME ; /**< Microframe count, 0-7 */
EXTERN xdata _AT_(0xE687) volatile BYTE FNADDR ; /**< USB Function address */
 
/* Endpoints */
 
EXTERN xdata _AT_(0xE68A) volatile BYTE EP0BCH ; /**< Endpoint 0 Byte Count H */
EXTERN xdata _AT_(0xE68B) volatile BYTE EP0BCL ; /**< Endpoint 0 Byte Count L */
EXTERN xdata _AT_(0xE68D) volatile BYTE EP1OUTBC ; /**< Endpoint 1 OUT Byte Count */
EXTERN xdata _AT_(0xE68F) volatile BYTE EP1INBC ; /**< Endpoint 1 IN Byte Count */
EXTERN xdata _AT_(0xE690) volatile BYTE EP2BCH ; /**< Endpoint 2 Byte Count H */
EXTERN xdata _AT_(0xE691) volatile BYTE EP2BCL ; /**< Endpoint 2 Byte Count L */
EXTERN xdata _AT_(0xE694) volatile BYTE EP4BCH ; /**< Endpoint 4 Byte Count H */
EXTERN xdata _AT_(0xE695) volatile BYTE EP4BCL ; /**< Endpoint 4 Byte Count L */
EXTERN xdata _AT_(0xE698) volatile BYTE EP6BCH ; /**< Endpoint 6 Byte Count H */
EXTERN xdata _AT_(0xE699) volatile BYTE EP6BCL ; /**< Endpoint 6 Byte Count L */
EXTERN xdata _AT_(0xE69C) volatile BYTE EP8BCH ; /**< Endpoint 8 Byte Count H */
EXTERN xdata _AT_(0xE69D) volatile BYTE EP8BCL ; /**< Endpoint 8 Byte Count L */
EXTERN xdata _AT_(0xE6A0) volatile BYTE EP0CS ; /**< Endpoint Control and Status */
EXTERN xdata _AT_(0xE6A1) volatile BYTE EP1OUTCS ; /**< Endpoint 1 OUT Control and Status */
EXTERN xdata _AT_(0xE6A2) volatile BYTE EP1INCS ; /**< Endpoint 1 IN Control and Status */
EXTERN xdata _AT_(0xE6A3) volatile BYTE EP2CS ; /**< Endpoint 2 Control and Status */
EXTERN xdata _AT_(0xE6A4) volatile BYTE EP4CS ; /**< Endpoint 4 Control and Status */
EXTERN xdata _AT_(0xE6A5) volatile BYTE EP6CS ; /**< Endpoint 6 Control and Status */
EXTERN xdata _AT_(0xE6A6) volatile BYTE EP8CS ; /**< Endpoint 8 Control and Status */
EXTERN xdata _AT_(0xE6A7) volatile BYTE EP2FIFOFLGS ; /**< Endpoint 2 Flags */
EXTERN xdata _AT_(0xE6A8) volatile BYTE EP4FIFOFLGS ; /**< Endpoint 4 Flags */
EXTERN xdata _AT_(0xE6A9) volatile BYTE EP6FIFOFLGS ; /**< Endpoint 6 Flags */
EXTERN xdata _AT_(0xE6AA) volatile BYTE EP8FIFOFLGS ; /**< Endpoint 8 Flags */
EXTERN xdata _AT_(0xE6AB) volatile BYTE EP2FIFOBCH ; /**< EP2 FIFO total byte count H */
EXTERN xdata _AT_(0xE6AC) volatile BYTE EP2FIFOBCL ; /**< EP2 FIFO total byte count L */
EXTERN xdata _AT_(0xE6AD) volatile BYTE EP4FIFOBCH ; /**< EP4 FIFO total byte count H */
EXTERN xdata _AT_(0xE6AE) volatile BYTE EP4FIFOBCL ; /**< EP4 FIFO total byte count L */
EXTERN xdata _AT_(0xE6AF) volatile BYTE EP6FIFOBCH ; /**< EP6 FIFO total byte count H */
EXTERN xdata _AT_(0xE6B0) volatile BYTE EP6FIFOBCL ; /**< EP6 FIFO total byte count L */
EXTERN xdata _AT_(0xE6B1) volatile BYTE EP8FIFOBCH ; /**< EP8 FIFO total byte count H */
EXTERN xdata _AT_(0xE6B2) volatile BYTE EP8FIFOBCL ; /**< EP8 FIFO total byte count L */
EXTERN xdata _AT_(0xE6B3) volatile BYTE SUDPTRH ; /**< Setup Data Pointer high address byte */
EXTERN xdata _AT_(0xE6B4) volatile BYTE SUDPTRL ; /**< Setup Data Pointer low address byte */
EXTERN xdata _AT_(0xE6B5) volatile BYTE SUDPTRCTL ; /**< Setup Data Pointer Auto Mode */
EXTERN xdata _AT_(0xE6B8) volatile BYTE SETUPDAT[8] ; /**< 8 bytes of SETUP data */
 
/* GPIF */
 
EXTERN xdata _AT_(0xE6C0) volatile BYTE GPIFWFSELECT ; /**< Waveform Selector */
EXTERN xdata _AT_(0xE6C1) volatile BYTE GPIFIDLECS ; /**< GPIF Done, GPIF IDLE drive mode */
EXTERN xdata _AT_(0xE6C2) volatile BYTE GPIFIDLECTL ; /**< Inactive Bus, CTL states */
EXTERN xdata _AT_(0xE6C3) volatile BYTE GPIFCTLCFG ; /**< CTL OUT pin drive */
EXTERN xdata _AT_(0xE6C4) volatile BYTE GPIFADRH ; /**< GPIF Address H */
EXTERN xdata _AT_(0xE6C5) volatile BYTE GPIFADRL ; /**< GPIF Address L */
EXTERN xdata _AT_(0xE6CE) volatile BYTE GPIFTCB3 ; /**< GPIF Transaction Count Byte 3 */
EXTERN xdata _AT_(0xE6CF) volatile BYTE GPIFTCB2 ; /**< GPIF Transaction Count Byte 2 */
EXTERN xdata _AT_(0xE6D0) volatile BYTE GPIFTCB1 ; /**< GPIF Transaction Count Byte 1 */
EXTERN xdata _AT_(0xE6D1) volatile BYTE GPIFTCB0 ; /**< GPIF Transaction Count Byte 0 */
 
#define EP2GPIFTCH GPIFTCB1 /**< these are here for backwards compatibility */
#define EP2GPIFTCL GPIFTCB0 /**< before REVE silicon (ie. REVB and REVD) */
#define EP4GPIFTCH GPIFTCB1 /**< these are here for backwards compatibility */
#define EP4GPIFTCL GPIFTCB0 /**< before REVE silicon (ie. REVB and REVD) */
#define EP6GPIFTCH GPIFTCB1 /**< these are here for backwards compatibility */
#define EP6GPIFTCL GPIFTCB0 /**< before REVE silicon (ie. REVB and REVD) */
#define EP8GPIFTCH GPIFTCB1 /**< these are here for backwards compatibility */
#define EP8GPIFTCL GPIFTCB0 /**< before REVE silicon (ie. REVB and REVD) */
 
/* EXTERN xdata volatile BYTE EP2GPIFTCH _AT_ 0xE6D0;*/ /**< EP2 GPIF Transaction Count High */
/* EXTERN xdata volatile BYTE EP2GPIFTCL _AT_ 0xE6D1;*/ /**< EP2 GPIF Transaction Count Low */
EXTERN xdata _AT_(0xE6D2) volatile BYTE EP2GPIFFLGSEL ; /**< EP2 GPIF Flag select */
EXTERN xdata _AT_(0xE6D3) volatile BYTE EP2GPIFPFSTOP ; /**< Stop GPIF EP2 transaction on prog. flag */
EXTERN xdata _AT_(0xE6D4) volatile BYTE EP2GPIFTRIG ; /**< EP2 FIFO Trigger */
/* EXTERN xdata volatile BYTE EP4GPIFTCH _AT_ 0xE6D8;*/ /**< EP4 GPIF Transaction Count High */
/**< EXTERN xdata volatile BYTE EP4GPIFTCL _AT_ 0xE6D9;*/ /**< EP4 GPIF Transactionr Count Low */
EXTERN xdata _AT_(0xE6DA) volatile BYTE EP4GPIFFLGSEL ; /**< EP4 GPIF Flag select */
EXTERN xdata _AT_(0xE6DB) volatile BYTE EP4GPIFPFSTOP ; /**< Stop GPIF EP4 transaction on prog. flag */
EXTERN xdata _AT_(0xE6DC) volatile BYTE EP4GPIFTRIG ; /**< EP4 FIFO Trigger */
/**< EXTERN xdata volatile BYTE EP6GPIFTCH _AT_ 0xE6E0;*/ /**< EP6 GPIF Transaction Count High */
/**< EXTERN xdata volatile BYTE EP6GPIFTCL _AT_ 0xE6E1;*/ /**< EP6 GPIF Transaction Count Low */
EXTERN xdata _AT_(0xE6E2) volatile BYTE EP6GPIFFLGSEL ; /**< EP6 GPIF Flag select */
EXTERN xdata _AT_(0xE6E3) volatile BYTE EP6GPIFPFSTOP ; /**< Stop GPIF EP6 transaction on prog. flag */
EXTERN xdata _AT_(0xE6E4) volatile BYTE EP6GPIFTRIG ; /**< EP6 FIFO Trigger */
/* EXTERN xdata volatile BYTE EP8GPIFTCH _AT_ 0xE6E8;*/ /**< EP8 GPIF Transaction Count High */
/* EXTERN xdata volatile BYTE EP8GPIFTCL _AT_ 0xE6E9;*/ /**< EP8GPIF Transaction Count Low */
EXTERN xdata _AT_(0xE6EA) volatile BYTE EP8GPIFFLGSEL ; /**< EP8 GPIF Flag select */
EXTERN xdata _AT_(0xE6EB) volatile BYTE EP8GPIFPFSTOP ; /**< Stop GPIF EP8 transaction on prog. flag */
EXTERN xdata _AT_(0xE6EC) volatile BYTE EP8GPIFTRIG ; /**< EP8 FIFO Trigger */
EXTERN xdata _AT_(0xE6F0) volatile BYTE XGPIFSGLDATH ; /**< GPIF Data H (16-bit mode only) */
EXTERN xdata _AT_(0xE6F1) volatile BYTE XGPIFSGLDATLX ; /**< Read/Write GPIF Data L & trigger transac */
EXTERN xdata _AT_(0xE6F2) volatile BYTE XGPIFSGLDATLNOX ; /**< Read GPIF Data L, no transac trigger */
EXTERN xdata _AT_(0xE6F3) volatile BYTE GPIFREADYCFG ; /**< Internal RDY,Sync/Async, RDY5CFG */
EXTERN xdata _AT_(0xE6F4) volatile BYTE GPIFREADYSTAT ; /**< RDY pin states */
EXTERN xdata _AT_(0xE6F5) volatile BYTE GPIFABORT ; /**< Abort GPIF cycles */
 
/* UDMA */
 
EXTERN xdata _AT_(0xE6C6) volatile BYTE FLOWSTATE ; /**<Defines GPIF flow state */
EXTERN xdata _AT_(0xE6C7) volatile BYTE FLOWLOGIC ; /**<Defines flow/hold decision criteria */
EXTERN xdata _AT_(0xE6C8) volatile BYTE FLOWEQ0CTL ; /**<CTL states during active flow state */
EXTERN xdata _AT_(0xE6C9) volatile BYTE FLOWEQ1CTL ; /**<CTL states during hold flow state */
EXTERN xdata _AT_(0xE6CA) volatile BYTE FLOWHOLDOFF ;
EXTERN xdata _AT_(0xE6CB) volatile BYTE FLOWSTB ; /**<CTL/RDY Signal to use as master data strobe */
EXTERN xdata _AT_(0xE6CC) volatile BYTE FLOWSTBEDGE ; /**<Defines active master strobe edge */
EXTERN xdata _AT_(0xE6CD) volatile BYTE FLOWSTBHPERIOD ; /**<Half Period of output master strobe */
EXTERN xdata _AT_(0xE60C) volatile BYTE GPIFHOLDAMOUNT ; /**<Data delay shift */
EXTERN xdata _AT_(0xE67D) volatile BYTE UDMACRCH ; /**<CRC Upper byte */
EXTERN xdata _AT_(0xE67E) volatile BYTE UDMACRCL ; /**<CRC Lower byte */
EXTERN xdata _AT_(0xE67F) volatile BYTE UDMACRCQUAL ; /**<UDMA In only, host terminated use only */
 
 
/* Debug/Test */
 
EXTERN xdata _AT_(0xE6F8) volatile BYTE DBUG ; /**< Debug */
EXTERN xdata _AT_(0xE6F9) volatile BYTE TESTCFG ; /**< Test configuration */
EXTERN xdata _AT_(0xE6FA) volatile BYTE USBTEST ; /**< USB Test Modes */
EXTERN xdata _AT_(0xE6FB) volatile BYTE CT1 ; /**< Chirp Test--Override */
EXTERN xdata _AT_(0xE6FC) volatile BYTE CT2 ; /**< Chirp Test--FSM */
EXTERN xdata _AT_(0xE6FD) volatile BYTE CT3 ; /**< Chirp Test--Control Signals */
EXTERN xdata _AT_(0xE6FE) volatile BYTE CT4 ; /**< Chirp Test--Inputs */
 
/* Endpoint Buffers */
 
EXTERN xdata _AT_(0xE740) volatile BYTE EP0BUF[64] ; /**< EP0 IN-OUT buffer */
EXTERN xdata _AT_(0xE780) volatile BYTE EP1OUTBUF[64] ; /**< EP1-OUT buffer */
EXTERN xdata _AT_(0xE7C0) volatile BYTE EP1INBUF[64] ; /**< EP1-IN buffer */
EXTERN xdata _AT_(0xF000) volatile BYTE EP2FIFOBUF[1024] ; /**< 512/1024-byte EP2 buffer (IN or OUT) */
EXTERN xdata _AT_(0xF400) volatile BYTE EP4FIFOBUF[1024] ; /**< 512 byte EP4 buffer (IN or OUT) */
EXTERN xdata _AT_(0xF800) volatile BYTE EP6FIFOBUF[1024] ; /**< 512/1024-byte EP6 buffer (IN or OUT) */
EXTERN xdata _AT_(0xFC00) volatile BYTE EP8FIFOBUF[1024] ; /**< 512 byte EP8 buffer (IN or OUT) */
 
#undef EXTERN
#undef _AT_
 
/*-----------------------------------------------------------------------------
Special Function Registers (SFRs)
The byte registers and bits defined in the following list are based
on the Synopsis definition of the 8051 Special Function Registers for EZ-USB.
If you modify the register definitions below, please regenerate the file
"ezregs.inc" which includes the same basic information for assembly inclusion.
-----------------------------------------------------------------------------*/
 
sfr at 0x80 IOA;
sfr at 0x81 SP;
sfr at 0x82 DPL;
sfr at 0x83 DPH;
sfr at 0x84 DPL1;
sfr at 0x85 DPH1;
sfr at 0x86 DPS;
/* DPS */
sbit at 0x86+0 SEL;
sfr at 0x87 PCON; /* PCON */
/*sbit IDLE = 0x87+0;*/
/*sbit STOP = 0x87+1;*/
/*sbit GF0 = 0x87+2;*/
/*sbit GF1 = 0x87+3;*/
/*sbit SMOD0 = 0x87+7;*/
sfr at 0x88 TCON;
/* TCON */
sbit at 0x88+0 IT0;
sbit at 0x88+1 IE0;
sbit at 0x88+2 IT1;
sbit at 0x88+3 IE1;
sbit at 0x88+4 TR0;
sbit at 0x88+5 TF0;
sbit at 0x88+6 TR1;
sbit at 0x88+7 TF1;
sfr at 0x89 TMOD;
/* TMOD */
/*sbit M00 = 0x89+0;*/
/*sbit M10 = 0x89+1;*/
/*sbit CT0 = 0x89+2;*/
/*sbit GATE0 = 0x89+3;*/
/*sbit M01 = 0x89+4;*/
/*sbit M11 = 0x89+5;*/
/*sbit CT1 = 0x89+6;*/
/*sbit GATE1 = 0x89+7;*/
sfr at 0x8A TL0;
sfr at 0x8B TL1;
sfr at 0x8C TH0;
sfr at 0x8D TH1;
sfr at 0x8E CKCON;
/* CKCON */
/*sbit MD0 = 0x89+0;*/
/*sbit MD1 = 0x89+1;*/
/*sbit MD2 = 0x89+2;*/
/*sbit T0M = 0x89+3;*/
/*sbit T1M = 0x89+4;*/
/*sbit T2M = 0x89+5;*/
/* sfr at 0x8F SPC_FNC; */ /* Was WRS in Reg320 */
/* CKCON */
/*sbit WRS = 0x8F+0; */
sfr at 0x90 IOB;
sfr at 0x91 EXIF; /**< EXIF Bit Values differ from Reg320 */
/* EXIF */
/*sbit USBINT = 0x91+4;*/
/*sbit I2CINT = 0x91+5;*/
/*sbit IE4 = 0x91+6;*/
/*sbit IE5 = 0x91+7;*/
sfr at 0x92 MPAGE;
sfr at 0x98 SCON0;
/* SCON0 */
sbit at 0x98+0 RI;
sbit at 0x98+1 TI;
sbit at 0x98+2 RB8;
sbit at 0x98+3 TB8;
sbit at 0x98+4 REN;
sbit at 0x98+5 SM2;
sbit at 0x98+6 SM1;
sbit at 0x98+7 SM0;
sfr at 0x99 SBUF0;
 
sfr at 0x9A APTR1H;
sfr at 0x9B APTR1L;
sfr at 0x9C AUTODAT1;
sfr at 0x9D AUTOPTRH2;
sfr at 0x9E AUTOPTRL2;
sfr at 0x9F AUTODAT2;
sfr at 0xA0 IOC;
sfr at 0xA1 INT2CLR;
sfr at 0xA2 INT4CLR;
 
#define AUTOPTRH1 APTR1H
#define AUTOPTRL1 APTR1L
 
sfr at 0xA8 IE;
/* IE */
sbit at 0xA8+0 EX0;
sbit at 0xA8+1 ET0;
sbit at 0xA8+2 EX1;
sbit at 0xA8+3 ET1;
sbit at 0xA8+4 ES0;
sbit at 0xA8+5 ET2;
sbit at 0xA8+6 ES1;
sbit at 0xA8+7 EA;
 
sfr at 0xAA EP2468STAT;
/* EP2468STAT */
/*sbit EP2E = 0xAA+0;*/
/*sbit EP2F = 0xAA+1;*/
/*sbit EP4E = 0xAA+2;*/
/*sbit EP4F = 0xAA+3;*/
/*sbit EP6E = 0xAA+4;*/
/*sbit EP6F = 0xAA+5;*/
/*sbit EP8E = 0xAA+6;*/
/*sbit EP8F = 0xAA+7;*/
 
sfr at 0xAB EP24FIFOFLGS;
sfr at 0xAC EP68FIFOFLGS;
sfr at 0xAF AUTOPTRSETUP;
/* AUTOPTRSETUP */
/* sbit EXTACC = 0xAF+0;*/
/* sbit APTR1FZ = 0xAF+1;*/
/* sbit APTR2FZ = 0xAF+2;*/
 
sfr at 0xB0 IOD;
sfr at 0xB1 IOE;
sfr at 0xB2 OEA;
sfr at 0xB3 OEB;
sfr at 0xB4 OEC;
sfr at 0xB5 OED;
sfr at 0xB6 OEE;
 
sfr at 0xB8 IP;
/* IP */
sbit at 0xB8+0 PX0;
sbit at 0xB8+1 PT0;
sbit at 0xB8+2 PX1;
sbit at 0xB8+3 PT1;
sbit at 0xB8+4 PS0;
sbit at 0xB8+5 PT2;
sbit at 0xB8+6 PS1;
 
sfr at 0xBA EP01STAT;
sfr at 0xBB GPIFTRIG;
sfr at 0xBD GPIFSGLDATH;
sfr at 0xBE GPIFSGLDATLX;
sfr at 0xBF GPIFSGLDATLNOX;
 
sfr at 0xC0 SCON1;
/* SCON1 */
sbit at 0xC0+0 RI1;
sbit at 0xC0+1 TI1;
sbit at 0xC0+2 RB81;
sbit at 0xC0+3 TB81;
sbit at 0xC0+4 REN1;
sbit at 0xC0+5 SM21;
sbit at 0xC0+6 SM11;
sbit at 0xC0+7 SM01;
sfr at 0xC1 SBUF1;
sfr at 0xC8 T2CON;
/* T2CON */
sbit at 0xC8+0 CP_RL2;
sbit at 0xC8+1 C_T2;
sbit at 0xC8+2 TR2;
sbit at 0xC8+3 EXEN2;
sbit at 0xC8+4 TCLK;
sbit at 0xC8+5 RCLK;
sbit at 0xC8+6 EXF2;
sbit at 0xC8+7 TF2;
sfr at 0xCA RCAP2L;
sfr at 0xCB RCAP2H;
sfr at 0xCC TL2;
sfr at 0xCD TH2;
sfr at 0xD0 PSW;
/* PSW */
sbit at 0xD0+0 P;
sbit at 0xD0+1 FL;
sbit at 0xD0+2 OV;
sbit at 0xD0+3 RS0;
sbit at 0xD0+4 RS1;
sbit at 0xD0+5 F0;
sbit at 0xD0+6 AC;
sbit at 0xD0+7 CY;
sfr at 0xD8 EICON; /**< Was WDCON in DS80C320 EICON; Bit Values differ from Reg320 */
/* EICON */
sbit at 0xD8+3 INT6;
sbit at 0xD8+4 RESI;
sbit at 0xD8+5 ERESI;
sbit at 0xD8+7 SMOD1;
sfr at 0xE0 ACC;
sfr at 0xE8 EIE; /**< EIE Bit Values differ from Reg320 */
/* EIE */
sbit at 0xE8+0 EIUSB;
sbit at 0xE8+1 EI2C;
sbit at 0xE8+2 EIEX4;
sbit at 0xE8+3 EIEX5;
sbit at 0xE8+4 EIEX6;
sfr at 0xF0 B;
sfr at 0xF8 EIP; /**< EIP Bit Values differ from Reg320 */
/* EIP */
sbit at 0xF8+0 PUSB;
sbit at 0xF8+1 PI2C;
sbit at 0xF8+2 EIPX4;
sbit at 0xF8+3 EIPX5;
sbit at 0xF8+4 EIPX6;
 
/*-----------------------------------------------------------------------------
Bit Masks
-----------------------------------------------------------------------------*/
 
#define bmBIT0 1
#define bmBIT1 2
#define bmBIT2 4
#define bmBIT3 8
#define bmBIT4 16
#define bmBIT5 32
#define bmBIT6 64
#define bmBIT7 128
 
/* CPU Control & Status Register (CPUCS) */
#define bmPRTCSTB bmBIT5
#define bmCLKSPD (bmBIT4 | bmBIT3)
#define bmCLKSPD1 bmBIT4
#define bmCLKSPD0 bmBIT3
#define bmCLKINV bmBIT2
#define bmCLKOE bmBIT1
#define bm8051RES bmBIT0
/* Port Alternate Configuration Registers */
/* Port A (PORTACFG) */
#define bmFLAGD bmBIT7
#define bmINT1 bmBIT1
#define bmINT0 bmBIT0
/* Port C (PORTCCFG) */
#define bmGPIFA7 bmBIT7
#define bmGPIFA6 bmBIT6
#define bmGPIFA5 bmBIT5
#define bmGPIFA4 bmBIT4
#define bmGPIFA3 bmBIT3
#define bmGPIFA2 bmBIT2
#define bmGPIFA1 bmBIT1
#define bmGPIFA0 bmBIT0
/* Port E (PORTECFG) */
#define bmGPIFA8 bmBIT7
#define bmT2EX bmBIT6
#define bmINT6 bmBIT5
#define bmRXD1OUT bmBIT4
#define bmRXD0OUT bmBIT3
#define bmT2OUT bmBIT2
#define bmT1OUT bmBIT1
#define bmT0OUT bmBIT0
 
/* I2C Control & Status Register (I2CS) */
#define bmSTART bmBIT7
#define bmSTOP bmBIT6
#define bmLASTRD bmBIT5
#define bmID (bmBIT4 | bmBIT3)
#define bmBERR bmBIT2
#define bmACK bmBIT1
#define bmDONE bmBIT0
/* I2C Control Register (I2CTL) */
#define bmSTOPIE bmBIT1
#define bm400KHZ bmBIT0
/* Interrupt 2 (USB) Autovector Register (INT2IVEC) */
#define bmIV4 bmBIT6
#define bmIV3 bmBIT5
#define bmIV2 bmBIT4
#define bmIV1 bmBIT3
#define bmIV0 bmBIT2
/* USB Interrupt Request & Enable Registers (USBIE/USBIRQ) */
#define bmEP0ACK bmBIT6
#define bmHSGRANT bmBIT5
#define bmURES bmBIT4
#define bmSUSP bmBIT3
#define bmSUTOK bmBIT2
#define bmSOF bmBIT1
#define bmSUDAV bmBIT0
/* Breakpoint register (BREAKPT) */
#define bmBREAK bmBIT3
#define bmBPPULSE bmBIT2
#define bmBPEN bmBIT1
/* Interrupt 2 & 4 Setup (INTSETUP) */
#define bmAV2EN bmBIT3
#define bmINT4IN bmBIT1
#define bmAV4EN bmBIT0
/* USB Control & Status Register (USBCS) */
#define bmHSM bmBIT7
#define bmDISCON bmBIT3
#define bmNOSYNSOF bmBIT2
#define bmRENUM bmBIT1
#define bmSIGRESUME bmBIT0
/* Wakeup Control and Status Register (WAKEUPCS) */
#define bmWU2 bmBIT7
#define bmWU bmBIT6
#define bmWU2POL bmBIT5
#define bmWUPOL bmBIT4
#define bmDPEN bmBIT2
#define bmWU2EN bmBIT1
#define bmWUEN bmBIT0
/* End Point 0 Control & Status Register (EP0CS) */
#define bmHSNAK bmBIT7
/* End Point 0-1 Control & Status Registers (EP0CS/EP1OUTCS/EP1INCS) */
#define bmEPBUSY bmBIT1
#define bmEPSTALL bmBIT0
/* End Point 2-8 Control & Status Registers (EP2CS/EP4CS/EP6CS/EP8CS) */
#define bmNPAK (bmBIT6 | bmBIT5 | bmBIT4)
#define bmEPFULL bmBIT3
#define bmEPEMPTY bmBIT2
/* Endpoint Status (EP2468STAT) SFR bits */
#define bmEP8FULL bmBIT7
#define bmEP8EMPTY bmBIT6
#define bmEP6FULL bmBIT5
#define bmEP6EMPTY bmBIT4
#define bmEP4FULL bmBIT3
#define bmEP4EMPTY bmBIT2
#define bmEP2FULL bmBIT1
#define bmEP2EMPTY bmBIT0
/* SETUP Data Pointer Auto Mode (SUDPTRCTL) */
#define bmSDPAUTO bmBIT0
/* Endpoint Data Toggle Control (TOGCTL) */
#define bmQUERYTOGGLE bmBIT7
#define bmSETTOGGLE bmBIT6
#define bmRESETTOGGLE bmBIT5
#define bmTOGCTLEPMASK bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0
/* IBN (In Bulk Nak) enable and request bits (IBNIE/IBNIRQ) */
#define bmEP8IBN bmBIT5
#define bmEP6IBN bmBIT4
#define bmEP4IBN bmBIT3
#define bmEP2IBN bmBIT2
#define bmEP1IBN bmBIT1
#define bmEP0IBN bmBIT0
 
/* PING-NAK enable and request bits (NAKIE/NAKIRQ) */
#define bmEP8PING bmBIT7
#define bmEP6PING bmBIT6
#define bmEP4PING bmBIT5
#define bmEP2PING bmBIT4
#define bmEP1PING bmBIT3
#define bmEP0PING bmBIT2
#define bmIBN bmBIT0
 
/* Interface Configuration bits (IFCONFIG) */
#define bmIFCLKSRC bmBIT7 /**< set == INTERNAL */
#define bm3048MHZ bmBIT6 /**< set == 48 MHz */
#define bmIFCLKOE bmBIT5
#define bmIFCLKPOL bmBIT4
#define bmASYNC bmBIT3
#define bmGSTATE bmBIT2
#define bmIFCFG1 bmBIT1
#define bmIFCFG0 bmBIT0
#define bmIFCFGMASK (bmIFCFG0 | bmIFCFG1)
#define bmIFGPIF bmIFCFG1
 
/* EP 2468 FIFO Configuration bits (EP2FIFOCFG,EP4FIFOCFG,EP6FIFOCFG,EP8FIFOCFG) */
#define bmINFM bmBIT6
#define bmOEP bmBIT5
#define bmAUTOOUT bmBIT4
#define bmAUTOIN bmBIT3
#define bmZEROLENIN bmBIT2
// must be zero bmBIT1
#define bmWORDWIDE bmBIT0
 
/*
* Chip Revision Control Bits (REVCTL) - used to ebable/disable revision specific features
*/
#define bmNOAUTOARM bmBIT1 /**< these don't match the docs */
#define bmSKIPCOMMIT bmBIT0 /**< these don't match the docs */
 
#define bmDYN_OUT bmBIT1 /**< these do... */
#define bmENH_PKT bmBIT0
 
 
/* Fifo Reset bits (FIFORESET) */
#define bmNAKALL bmBIT7
 
/* Endpoint Configuration (EPxCFG) */
#define bmVALID bmBIT7
#define bmIN bmBIT6
#define bmTYPE1 bmBIT5
#define bmTYPE0 bmBIT4
#define bmISOCHRONOUS bmTYPE0
#define bmBULK bmTYPE1
#define bmINTERRUPT (bmTYPE1 | bmTYPE0)
#define bm1KBUF bmBIT3
#define bmBUF1 bmBIT1
#define bmBUF0 bmBIT0
#define bmQUADBUF 0
#define bmINVALIDBUF bmBUF0
#define bmDOUBLEBUF bmBUF1
#define bmTRIPLEBUF (bmBUF1 | bmBUF0)
 
/* OUTPKTEND */
#define bmSKIP bmBIT7 /**< low 4 bits specify which end point */
 
/* GPIFTRIG defs */
#define bmGPIF_IDLE bmBIT7 /**< status bit */
 
#define bmGPIF_EP2_START 0
#define bmGPIF_EP4_START 1
#define bmGPIF_EP6_START 2
#define bmGPIF_EP8_START 3
#define bmGPIF_READ bmBIT2
#define bmGPIF_WRITE 0
 
/* GPIFREADYCFG */
#define bmTCXRDY5 bmBIT5
#define bmSAS bmBIT6
#define bmINTRDY bmBIT7
 
/* EPxGPIFFLGSEL, GPIF Fifo flag select */
#define bmFLAG_PROGRAMMABLE 0
#define bmFLAG_EMPTY bmBIT0
#define bmFLAG_FULL bmBIT1
#define bmFLAG_RESERVED (bmBIT1 | bmBIT0)
 
/* EXIF bits */
#define bmEXIF_USBINT bmBIT4
#define bmEXIF_I2CINT bmBIT5
#define bmEXIF_IE4 bmBIT6
#define bmEXIF_IE5 bmBIT7
 
/* AUTOPTRSETUP setup bits */
#define bmAPTREN bmBIT0
#define bmAPTR1INC bmBIT1
#define bmAPTR2INC bmBIT2
 
/* EPxFIFOIE fifo interrupt enables */
#define bmFIFO_EDGEPF bmBIT3
#define bmFIFO_PF bmBIT2
#define bmFIFO_EF bmBIT1
#define bmFIFO_FF bmBIT0
 
/* GPIFIE gpif interrupt enables */
#define bmGPIFWF bmBIT1
#define bmGPIFDONE bmBIT0
 
/*EPxFIFOPFH fifo programmable flag register */
#define bmDECIS bmBIT7
#define bmPKTSTAT bmBIT6
 
 
#endif /* FX2REGS_H */
/trunk/GECKO4com/fx2_firmware/c/include/usb_common.h
0,0 → 1,72
/* -*- c -*- */
/*
* Copyright 2003 Free Software Foundation, Inc.
*
* This file is part of GNU Radio
*
* GNU Radio is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3, or (at your option)
* any later version.
*
* GNU Radio is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GNU Radio; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
 
/*********************************************************************/
/** \file usb_common.h
*********************************************************************
* \brief basic functions to setup and enable USB functionality
*
* usb_common provides the basic functions and interrupt
* routines to enable USB communication and handling of all
* basic functions like standard requests, USB reset,
* descriptor handling etc.\n
* When a USB Class command or a USB Vendor specific command
* is received usb_common calls the app_class_cmd or the
* app_vendor_cmd function. These functions are not implemented
* here. This is done by the user programm.
*
* \author GNUradio, Christoph Zimmermann bfh.ch
*
*/
 
#ifndef _USB_COMMON_H_
#define _USB_COMMON_H_
 
/** Global variable set by SUDAV isr (USB SETUP Data Available) */
extern volatile bit _usb_got_SUDAV;
 
/** Provided by user application to handle CLASS commands.
* \return returns non-zero if it handled the command. */
unsigned char app_class_cmd (void);
 
/** Provided by user application to handle VENDOR commands.
* \return returns non-zero if it handled the command. */
unsigned char app_vendor_cmd (void);
 
/** Installs the interrupt handlers to handle the standard USB interrupts */
void usb_install_handlers (void);
 
/** Handles the setup package and the basic device requests like reading
* descriptors, get/set confifuration etc. \n
* Also calls the app_class_cmd or app_vendor_cmd functions when needed. */
void usb_handle_setup_packet (void);
 
#ifdef USB_DFU_SUPPORT
/** Changes the interrupt handlers from runtime mode to DFU mode handlers
* and the oposite. */
void usb_toggle_dfu_handlers (void);
#endif
 
/** makro to check if new setup data is available */
#define usb_setup_packet_avail() _usb_got_SUDAV
 
#endif /* _USB_COMMON_H_ */
/trunk/GECKO4com/fx2_firmware/c/include/usb_requests.h
0,0 → 1,106
/* -*- c++ -*- */
/*
* Copyright 2003 Free Software Foundation, Inc.
*
* This file is part of GNU Radio
*
* GNU Radio is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3, or (at your option)
* any later version.
*
* GNU Radio is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GNU Radio; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
 
/*********************************************************************/
/** \file usb_requests.h
*********************************************************************
* \brief Standard USB requests.
* These are contained in end point 0 setup packets
*
* \author Christoph Zimmermann bfh.ch
* \date 2009-1-13
*
*/
 
 
#ifndef _USB_REQUESTS_H_
#define _USB_REQUESTS_H_
 
#define bRequestType SETUPDAT[0]
#define bRequest SETUPDAT[1]
#define wValueL SETUPDAT[2]
#define wValueH SETUPDAT[3]
#define wIndexL SETUPDAT[4]
#define wIndexH SETUPDAT[5]
#define wLengthL SETUPDAT[6]
#define wLengthH SETUPDAT[7]
 
/* format of bmRequestType byte */
 
#define bmRT_DIR_MASK (0x1 << 7)
#define bmRT_DIR_IN (1 << 7)
#define bmRT_DIR_OUT (0 << 7)
 
#define bmRT_TYPE_MASK (0x3 << 5)
#define bmRT_TYPE_STD (0 << 5)
#define bmRT_TYPE_CLASS (1 << 5)
#define bmRT_TYPE_VENDOR (2 << 5)
#define bmRT_TYPE_RESERVED (3 << 5)
 
#define bmRT_RECIP_MASK (0x1f << 0)
#define bmRT_RECIP_DEVICE (0 << 0)
#define bmRT_RECIP_INTERFACE (1 << 0)
#define bmRT_RECIP_ENDPOINT (2 << 0)
#define bmRT_RECIP_OTHER (3 << 0)
 
 
/* standard request codes (bRequest) */
 
#define RQ_GET_STATUS 0
#define RQ_CLEAR_FEATURE 1
#define RQ_RESERVED_2 2
#define RQ_SET_FEATURE 3
#define RQ_RESERVED_4 4
#define RQ_SET_ADDRESS 5
#define RQ_GET_DESCR 6
#define RQ_SET_DESCR 7
#define RQ_GET_CONFIG 8
#define RQ_SET_CONFIG 9
#define RQ_GET_INTERFACE 10
#define RQ_SET_INTERFACE 11
#define RQ_SYNCH_FRAME 12
 
/* standard descriptor types */
 
#define DT_DEVICE 1
#define DT_CONFIG 2
#define DT_STRING 3
#define DT_INTERFACE 4
#define DT_ENDPOINT 5
#define DT_DEVQUAL 6
#define DT_OTHER_SPEED 7
#define DT_INTERFACE_POWER 8
#define DT_DFU_FUNCTIONAL 0x21
 
/* standard feature selectors */
 
#define FS_ENDPOINT_HALT 0 /**< recip: endpoint */
#define FS_DEV_REMOTE_WAKEUP 1 /**< recip: device */
#define FS_TEST_MODE 2 /**< recip: device */
 
/* Get Status device attributes */
 
#define bmGSDA_SELF_POWERED 0x01
#define bmGSDA_REM_WAKEUP 0x02
 
 
#endif /* _USB_REQUESTS_H_ */
/trunk/GECKO4com/fx2_firmware/c/i2c.c
0,0 → 1,122
/* -*- c++ -*- */
/*
* Copyright 2003 Free Software Foundation, Inc.
*
* This file is part of GNU Radio
*
* GNU Radio is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3, or (at your option)
* any later version.
*
* GNU Radio is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GNU Radio; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
 
#include "i2c.h"
#include "fx2regs.h"
#include <string.h>
 
// issue a stop bus cycle and wait for completion
 
 
// returns non-zero if successful, else 0
unsigned char
i2c_read (unsigned char addr, xdata unsigned char *buf, unsigned char len)
{
volatile unsigned char junk;
if (len == 0) // reading zero bytes always works
return 1;
while (I2CS & bmSTOP) // wait for stop to clear
;
 
I2CS = bmSTART;
I2DAT = (addr << 1) | 1; // write address and direction (1's the read bit)
 
while ((I2CS & bmDONE) == 0)
;
 
if ((I2CS & bmBERR) || (I2CS & bmACK) == 0) // no device answered...
goto fail;
 
if (len == 1)
I2CS |= bmLASTRD;
 
junk = I2DAT; // trigger the first read cycle
 
while (--len != 0){
while ((I2CS & bmDONE) == 0)
;
 
if (I2CS & bmBERR)
goto fail;
 
if (len == 1)
I2CS |= bmLASTRD;
*buf++ = I2DAT; // get data, trigger another read
}
 
// wait for final byte
while ((I2CS & bmDONE) == 0)
;
if (I2CS & bmBERR)
goto fail;
 
I2CS |= bmSTOP;
*buf = I2DAT;
 
return 1;
 
fail:
I2CS |= bmSTOP;
return 0;
}
 
 
 
// returns non-zero if successful, else 0
unsigned char
i2c_write (unsigned char addr, xdata const unsigned char *buf, unsigned char len)
{
while (I2CS & bmSTOP) // wait for stop to clear
;
 
I2CS = bmSTART;
I2DAT = (addr << 1) | 0; // write address and direction (0's the write bit)
 
while ((I2CS & bmDONE) == 0)
;
 
if ((I2CS & bmBERR) || (I2CS & bmACK) == 0) // no device answered...
goto fail;
 
while (len > 0){
I2DAT = *buf++;
len--;
 
while ((I2CS & bmDONE) == 0)
;
 
if ((I2CS & bmBERR) || (I2CS & bmACK) == 0) // no device answered...
goto fail;
}
 
I2CS |= bmSTOP;
return 1;
 
fail:
I2CS |= bmSTOP;
return 0;
}
/trunk/GECKO4com/fx2_firmware/c/isr.c
0,0 → 1,167
/* -*- c++ -*- */
/*
* Copyright 2003 Free Software Foundation, Inc.
*
* This file is part of GNU Radio
*
* GNU Radio is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3, or (at your option)
* any later version.
*
* GNU Radio is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with GNU Radio; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
 
#include "isr.h"
#include "fx2regs.h"
#include "syncdelay.h"
 
extern xdata unsigned char _standard_interrupt_vector[];
extern xdata unsigned char _usb_autovector[];
extern xdata unsigned char _fifo_gpif_autovector[];
 
#define LJMP_OPCODE 0x02
 
/*
* Hook standard interrupt vector.
*
* vector_number is from the SV_<foo> list.
* addr is the address of the interrupt service routine.
*/
void
hook_sv (unsigned char vector_number, unsigned short addr)
{
bit t;
// sanity checks
 
if (vector_number < SV_MIN || vector_number > SV_MAX)
return;
 
if ((vector_number & 0x0f) != 0x03 && (vector_number & 0x0f) != 0x0b)
return;
 
t = EA;
EA = 0;
_standard_interrupt_vector[vector_number] = LJMP_OPCODE;
_standard_interrupt_vector[vector_number + 1] = addr >> 8;
_standard_interrupt_vector[vector_number + 2] = addr & 0xff;
EA = t;
}
 
/*
* Hook usb interrupt vector.
*
* vector_number is from the UV_<foo> list.
* addr is the address of the interrupt service routine.
*/
void
hook_uv (unsigned char vector_number, unsigned short addr)
{
bit t;
// sanity checks
 
if (vector_number < UV_MIN || vector_number > UV_MAX)
return;
 
if ((vector_number & 0x3) != 0)
return;
 
t = EA;
EA = 0;
_usb_autovector[vector_number] = LJMP_OPCODE;
_usb_autovector[vector_number + 1] = addr >> 8;
_usb_autovector[vector_number + 2] = addr & 0xff;
EA = t;
}
 
/*
* Hook fifo/gpif interrupt vector.
*
* vector_number is from the FGV_<foo> list.
* addr is the address of the interrupt service routine.
*/
void
hook_fgv (unsigned char vector_number, unsigned short addr)
{
bit t;
// sanity checks
 
if (vector_number < FGV_MIN || vector_number > FGV_MAX)
return;
 
if ((vector_number & 0x3) != 0)
return;
 
t = EA;
EA = 0;
_fifo_gpif_autovector[vector_number] = LJMP_OPCODE;
_fifo_gpif_autovector[vector_number + 1] = addr >> 8;
_fifo_gpif_autovector[vector_number + 2] = addr & 0xff;
EA = t;
}
 
/*
* One time call to enable autovectoring for both USB and FIFO/GPIF.
*
* This disables all USB and FIFO/GPIF interrupts and clears
* any pending interrupts too. It leaves the master USB and FIFO/GPIF
* interrupts enabled.
*/
void
setup_autovectors (void)
{
// disable master usb and fifo/gpif interrupt enables
EIUSB = 0;
EIEX4 = 0;
 
hook_sv (SV_INT_2, (unsigned short) _usb_autovector);
hook_sv (SV_INT_4, (unsigned short) _fifo_gpif_autovector);
 
// disable all fifo interrupt enables
SYNCDELAY;
EP2FIFOIE = 0; SYNCDELAY;
EP4FIFOIE = 0; SYNCDELAY;
EP6FIFOIE = 0; SYNCDELAY;
EP8FIFOIE = 0; SYNCDELAY;
 
// clear all pending fifo irqs
EP2FIFOIRQ = 0xff; SYNCDELAY;
EP4FIFOIRQ = 0xff; SYNCDELAY;
EP6FIFOIRQ = 0xff; SYNCDELAY;
EP8FIFOIRQ = 0xff; SYNCDELAY;
 
IBNIE = 0;
IBNIRQ = 0xff;
NAKIE = 0;
NAKIRQ = 0xff;
USBIE = 0;
USBIRQ = 0xff;
EPIE = 0;
EPIRQ = 0xff;
SYNCDELAY; GPIFIE = 0;
SYNCDELAY; GPIFIRQ = 0xff;
USBERRIE = 0;
USBERRIRQ = 0xff;
CLRERRCNT = 0;
INTSETUP = bmAV2EN | bmAV4EN | bmINT4IN;
 
// clear master irq's for usb and fifo/gpif
EXIF &= ~bmEXIF_USBINT;
EXIF &= ~bmEXIF_IE4;
// enable master usb and fifo/gpif interrrupts
EIUSB = 1;
EIEX4 = 1;
}
/trunk/GECKO4com/fx2_firmware/firmware/firmware.hex
0,0 → 1,211
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/trunk/GECKO4com/fx2_firmware/firmware/firmware_upload.hex
0,0 → 1,284
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/trunk/GECKO4com/fx2_firmware/Makefile
0,0 → 1,70
################################################################################
## _ _ __ ____ ##
## / / | | / _| | __| ##
## | |_| | _ _ / / | |_ ##
## | _ | | | | | | | | _| ##
## | | | | | |_| | \ \_ | |__ ##
## |_| |_| \_____| \__| |____| microLab ##
## ##
## Bern University of Applied Sciences (BFH) ##
## Quellgasse 21 ##
## Room HG 4.33 ##
## 2501 Biel/Bienne ##
## Switzerland ##
## ##
## http://www.microlab.ch ##
################################################################################
 
CC = sdcc
AS = asx8051
ASFLAGS = -plosgff
CFLAGS = --opt-code-size --no-xinit-opt -mmcs51 --model-small
#For the memory model following assumptions have been made:
#0x0000-0x0FFF 4 kbyte code memory
#0x1000-0x1FFF 4 kbyte data memory
#0xE000-0xE1FF 512 bytes USB descriptor tables
MEMOPTS = --code-loc 0x0000 --code-size 0x1000 \
--xram-loc 0x1000 --xram-size 0x1000 \
--iram-size 0x100 --data-loc 0x08\
--stack-size 0x80 --stack-loc 0x80 --no-pack-iram\
-Wl '-b USBDESCSEG=0xE000'
LDFLAGS=$(MEMOPTS) -L ${LIB_DIR}
SANDBOXDIR = sandbox
INCLUDE_DIR = c/include
LIB_DIR = lib
LIB = libfx2
PACKAGE = libfx2.lib
TARGETDIR = firmware
 
 
SEARCH_DIR = ${addprefix -I./,$(INCLUDE_DIR)}
FIRMWARE_OBJ = vectors.rel usb_descriptors.rel startup.rel gecko4com_main.rel
LIB_OBJ = i2c.rel delay.rel fx2utils.rel isr.rel timer.rel usb_common.rel
 
all : clean firmware.hex
 
$(SANDBOXDIR) :
mkdir -p $(SANDBOXDIR)
 
$(SANDBOXDIR)/%.a51 : asm/%.a51
cd $(SANDBOXDIR); ln -s ../$< . ; cd ..
 
$(SANDBOXDIR)/%.rel : $(SANDBOXDIR)/%.a51
$(AS) $(ASFLAGS) $<
 
$(SANDBOXDIR)/%.rel : c/%.c
pwd ; $(CC) -c $(CFLAGS) $(SEARCH_DIR) $< -o $@
 
$(LIB_DIR)/$(PACKAGE) : ${addprefix $(SANDBOXDIR)/,$(LIB_OBJ)}
mkdir -p $(LIB_DIR); for obj in $^; do sdcclib $@ $$obj; done
 
firmware.hex : ${addprefix $(SANDBOXDIR)/,$(FIRMWARE_OBJ)} ${LIB_DIR}/${PACKAGE}
$(CC) $(CFLAGS) $(LDFLAGS) -o $(SANDBOXDIR)/temp.hex $+;\
packihx $(SANDBOXDIR)/temp.hex > $(TARGETDIR)/$@; rm $(SANDBOXDIR)/temp.*
 
clean : sandbox
mkdir -p $(SANDBOXDIR) $(LIBDIR);cd $(SANDBOXDIR) ; ls | grep -v svn | xargs rm -rf ; \
cd .. ; cd $(LIB_DIR) ; ls | grep -v svn | xargs rm -rf ; cd ..\
rm -rf $(TARGETDIR)/firmware.hex
/trunk/GECKO4com/fx2_firmware/README
0,0 → 1,19
The firmware of the GECKO4com consists of 2 parts:
1) The contents (bitfile) of the Spartan 3 200AN FPGA.
2) The firmware of the Cypres FX2.
 
To be able to use the GECKO4com you have to first program the Spartan 3 200AN
FPGA before you can "burn" the Cypress FX2 firmware.
 
To make the Cypress FX2 firmware you require SDCC.
 
To build simply type "make all". The firmware will be available when all went
well in the directory and is called firmware.hex.
 
To burn the firmware you require the fxload tool.
 
Execute:
fxload -v -t fx2 -D /dev/bus/usb/<path to the GECKO4main> \
-I firmware/firmware.hex -s firmware/firmware_upload.hex -c 0xC2
 
That's all, you should be ready to go.

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