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URL https://opencores.org/ocsvn/gnextrapolator/gnextrapolator/trunk

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Rev 4 → Rev 5

/trunk/QuartusII/gnextrapolator.map.summary
0,0 → 1,15
Analysis & Synthesis Status : Successful - Tue Aug 14 00:26:26 2012
Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
Revision Name : gnextrapolator
Top-level Entity Name : gnextrapolator
Family : Stratix II
Logic utilization : N/A
Combinational ALUTs : 168
Dedicated logic registers : 190
Total registers : 190
Total pins : 107
Total virtual pins : 0
Total block memory bits : 512
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0
/trunk/QuartusII/gnextrapolator.qws
0,0 → 1,4
[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
/trunk/QuartusII/gnextrapolator.mif
0,0 → 1,25
-- Copyright (C) 1991-2010 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
 
-- Quartus II generated Memory Initialization File (.mif)
 
WIDTH=16;
DEPTH=32;
 
ADDRESS_RADIX=UNS;
DATA_RADIX=UNS;
 
CONTENT BEGIN
[0..31] : 0;
END;
/trunk/QuartusII/gnextrapolator.flow.rpt
0,0 → 1,118
Flow report for gnextrapolator
Tue Aug 14 00:28:18 2012
Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
 
 
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
 
 
 
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
 
 
 
+------------------------------------------------------------------------------+
; Flow Summary ;
+-------------------------------+----------------------------------------------+
; Flow Status ; Successful - Tue Aug 14 00:28:17 2012 ;
; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ;
; Revision Name ; gnextrapolator ;
; Top-level Entity Name ; gnextrapolator ;
; Family ; Stratix II ;
; Device ; EP2S15F484C4 ;
; Timing Models ; Final ;
; Met timing requirements ; Yes ;
; Logic utilization ; 2 % ;
; Combinational ALUTs ; 169 / 12,480 ( 1 % ) ;
; Dedicated logic registers ; 190 / 12,480 ( 2 % ) ;
; Total registers ; 190 ;
; Total pins ; 107 / 343 ( 31 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 512 / 419,328 ( < 1 % ) ;
; DSP block 9-bit elements ; 0 / 96 ( 0 % ) ;
; Total PLLs ; 0 / 6 ( 0 % ) ;
; Total DLLs ; 0 / 2 ( 0 % ) ;
+-------------------------------+----------------------------------------------+
 
 
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 08/14/2012 00:26:18 ;
; Main task ; Compilation ;
; Revision Name ; gnextrapolator ;
+-------------------+---------------------+
 
 
+--------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+------------------------------------+--------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+------------------------------------+--------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID ; 13608450046966.134491477702032 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
+------------------------------------+--------------------------------+---------------+-------------+----------------+
 
 
+-----------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:09 ; 1.0 ; 194 MB ; 00:00:09 ;
; Fitter ; 00:00:26 ; 1.0 ; 233 MB ; 00:00:26 ;
; Classic Timing Analyzer ; 00:00:05 ; 1.0 ; 153 MB ; 00:00:05 ;
; Total ; 00:00:40 ; -- ; -- ; 00:00:40 ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
 
 
+---------------------------------------------------------------------------------------+
; Flow OS Summary ;
+-------------------------+------------------+------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+-------------------------+------------------+------------+------------+----------------+
; Analysis & Synthesis ; LAPTOP ; Windows XP ; 5.1 ; i686 ;
; Fitter ; LAPTOP ; Windows XP ; 5.1 ; i686 ;
; Classic Timing Analyzer ; LAPTOP ; Windows XP ; 5.1 ; i686 ;
+-------------------------+------------------+------------+------------+----------------+
 
 
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolator
quartus_fit --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolator
quartus_tan --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolator --speed=4
 
 
 
/trunk/QuartusII/db/gnextrapolator.map_bb.cdb Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream
/trunk/QuartusII/db/gnextrapolator.map_bb.cdb
trunk/QuartusII/db/gnextrapolator.map_bb.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.fnsim.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.fnsim.hdb =================================================================== --- trunk/QuartusII/db/gnextrapolator.fnsim.hdb (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.fnsim.hdb (revision 5)
trunk/QuartusII/db/gnextrapolator.fnsim.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.map.kpt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.map.kpt =================================================================== --- trunk/QuartusII/db/gnextrapolator.map.kpt (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.map.kpt (revision 5)
trunk/QuartusII/db/gnextrapolator.map.kpt Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.cbx.xml =================================================================== --- trunk/QuartusII/db/gnextrapolator.cbx.xml (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.cbx.xml (revision 5) @@ -0,0 +1,6 @@ + + + + + + Index: trunk/QuartusII/db/gnextrapolator.cmp.kpt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.cmp.kpt =================================================================== --- trunk/QuartusII/db/gnextrapolator.cmp.kpt (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.cmp.kpt (revision 5)
trunk/QuartusII/db/gnextrapolator.cmp.kpt Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.map_bb.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.map_bb.hdb =================================================================== --- trunk/QuartusII/db/gnextrapolator.map_bb.hdb (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.map_bb.hdb (revision 5)
trunk/QuartusII/db/gnextrapolator.map_bb.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.(1).cnf.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.(1).cnf.cdb =================================================================== --- trunk/QuartusII/db/gnextrapolator.(1).cnf.cdb (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.(1).cnf.cdb (revision 5)
trunk/QuartusII/db/gnextrapolator.(1).cnf.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.lpc.html =================================================================== --- trunk/QuartusII/db/gnextrapolator.lpc.html (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.lpc.html (revision 5) @@ -0,0 +1,18 @@ + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
Index: trunk/QuartusII/db/gnextrapolator.(1).cnf.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.(1).cnf.hdb =================================================================== --- trunk/QuartusII/db/gnextrapolator.(1).cnf.hdb (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.(1).cnf.hdb (revision 5)
trunk/QuartusII/db/gnextrapolator.(1).cnf.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.tmw_info =================================================================== --- trunk/QuartusII/db/gnextrapolator.tmw_info (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.tmw_info (revision 5) @@ -0,0 +1,2 @@ +start_fitter:s:00:00:33 +start_timing_analyzer:s:00:00:09 Index: trunk/QuartusII/db/prev_cmp_gnextrapolator.tan.qmsg =================================================================== --- trunk/QuartusII/db/prev_cmp_gnextrapolator.tan.qmsg (nonexistent) +++ trunk/QuartusII/db/prev_cmp_gnextrapolator.tan.qmsg (revision 5) @@ -0,0 +1,12 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 13 23:53:04 2012 " "Info: Processing started: Mon Aug 13 23:53:04 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolator --speed=4 " "Info: Command: quartus_tan --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolator --speed=4" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} +{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "89 " "Warning: Found 89 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "indice_p_o\[0\] 0 " "Info: Pin \"indice_p_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "indice_p_o\[1\] 0 " "Info: Pin \"indice_p_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "indice_p_o\[2\] 0 " "Info: Pin \"indice_p_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "indice_p_o\[3\] 0 " "Info: Pin \"indice_p_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "indice_p_o\[4\] 0 " "Info: Pin \"indice_p_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[0\] 0 " "Info: Pin \"fxx_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[1\] 0 " "Info: Pin \"fxx_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[2\] 0 " "Info: Pin \"fxx_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[3\] 0 " "Info: Pin \"fxx_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[4\] 0 " "Info: Pin \"fxx_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[5\] 0 " "Info: Pin \"fxx_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[6\] 0 " "Info: Pin \"fxx_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[7\] 0 " "Info: Pin \"fxx_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[8\] 0 " "Info: Pin \"fxx_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[9\] 0 " "Info: Pin \"fxx_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[10\] 0 " "Info: Pin \"fxx_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[11\] 0 " "Info: Pin \"fxx_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[12\] 0 " "Info: Pin \"fxx_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[13\] 0 " "Info: Pin \"fxx_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[0\] 0 " "Info: Pin \"fxx1_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[1\] 0 " "Info: Pin \"fxx1_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[2\] 0 " "Info: Pin \"fxx1_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[3\] 0 " "Info: Pin \"fxx1_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[4\] 0 " "Info: Pin \"fxx1_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[5\] 0 " "Info: Pin \"fxx1_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[6\] 0 " "Info: Pin \"fxx1_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[7\] 0 " "Info: Pin \"fxx1_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[8\] 0 " "Info: Pin \"fxx1_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[9\] 0 " "Info: Pin \"fxx1_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[10\] 0 " "Info: Pin \"fxx1_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[11\] 0 " "Info: Pin \"fxx1_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[12\] 0 " "Info: Pin \"fxx1_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[13\] 0 " "Info: Pin \"fxx1_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[0\] 0 " "Info: Pin \"fxx2_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[1\] 0 " "Info: Pin \"fxx2_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[2\] 0 " "Info: Pin \"fxx2_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[3\] 0 " "Info: Pin \"fxx2_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[4\] 0 " "Info: Pin \"fxx2_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[5\] 0 " "Info: Pin \"fxx2_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[6\] 0 " "Info: Pin \"fxx2_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[7\] 0 " "Info: Pin \"fxx2_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[8\] 0 " "Info: Pin \"fxx2_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[9\] 0 " "Info: Pin \"fxx2_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[10\] 0 " "Info: Pin \"fxx2_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[11\] 0 " "Info: Pin \"fxx2_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[12\] 0 " "Info: Pin \"fxx2_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[13\] 0 " "Info: Pin \"fxx2_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[0\] 0 " "Info: Pin \"fxx3_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[1\] 0 " "Info: Pin \"fxx3_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[2\] 0 " "Info: Pin \"fxx3_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[3\] 0 " "Info: Pin \"fxx3_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[4\] 0 " "Info: Pin \"fxx3_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[5\] 0 " "Info: Pin \"fxx3_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[6\] 0 " "Info: Pin \"fxx3_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[7\] 0 " "Info: Pin \"fxx3_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[8\] 0 " "Info: Pin \"fxx3_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[9\] 0 " "Info: Pin \"fxx3_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[10\] 0 " "Info: Pin \"fxx3_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[11\] 0 " "Info: Pin \"fxx3_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[12\] 0 " "Info: Pin \"fxx3_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[13\] 0 " "Info: Pin \"fxx3_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[0\] 0 " "Info: Pin \"fxx4_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[1\] 0 " "Info: Pin \"fxx4_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[2\] 0 " "Info: Pin \"fxx4_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[3\] 0 " "Info: Pin \"fxx4_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[4\] 0 " "Info: Pin \"fxx4_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[5\] 0 " "Info: Pin \"fxx4_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[6\] 0 " "Info: Pin \"fxx4_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[7\] 0 " "Info: Pin \"fxx4_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[8\] 0 " "Info: Pin \"fxx4_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[9\] 0 " "Info: Pin \"fxx4_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[10\] 0 " "Info: Pin \"fxx4_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[11\] 0 " "Info: Pin \"fxx4_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[12\] 0 " "Info: Pin \"fxx4_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[13\] 0 " "Info: Pin \"fxx4_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[0\] 0 " "Info: Pin \"resul_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[1\] 0 " "Info: Pin \"resul_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[2\] 0 " "Info: Pin \"resul_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[3\] 0 " "Info: Pin \"resul_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[4\] 0 " "Info: Pin \"resul_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[5\] 0 " "Info: Pin \"resul_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[6\] 0 " "Info: Pin \"resul_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[7\] 0 " "Info: Pin \"resul_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[8\] 0 " "Info: Pin \"resul_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[9\] 0 " "Info: Pin \"resul_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[10\] 0 " "Info: Pin \"resul_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[11\] 0 " "Info: Pin \"resul_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[12\] 0 " "Info: Pin \"resul_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[13\] 0 " "Info: Pin \"resul_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1} +{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} +{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_i " "Info: Assuming node \"clk_i\" is an undefined clock" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } { "c:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_i" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_i register resultado\[4\] register resultado\[13\] 120.99 MHz 8.265 ns Internal " "Info: Clock \"clk_i\" has Internal fmax of 120.99 MHz between source register \"resultado\[4\]\" and destination register \"resultado\[13\]\" (period= 8.265 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.051 ns + Longest register register " "Info: + Longest register to register delay is 8.051 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns resultado\[4\] 1 REG LCFF_X17_Y12_N13 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X17_Y12_N13; Fanout = 3; REG Node = 'resultado\[4\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resultado[4] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.254 ns) + CELL(0.177 ns) 0.431 ns Mux86~0 2 COMB LCCOMB_X17_Y12_N0 7 " "Info: 2: + IC(0.254 ns) + CELL(0.177 ns) = 0.431 ns; Loc. = LCCOMB_X17_Y12_N0; Fanout = 7; COMB Node = 'Mux86~0'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.431 ns" { resultado[4] Mux86~0 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 126 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.364 ns) + CELL(0.403 ns) 2.198 ns Add2~26 3 COMB LCCOMB_X18_Y12_N20 2 " "Info: 3: + IC(1.364 ns) + CELL(0.403 ns) = 2.198 ns; Loc. = LCCOMB_X18_Y12_N20; Fanout = 2; COMB Node = 'Add2~26'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.767 ns" { Mux86~0 Add2~26 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 2.239 ns Add2~30 4 COMB LCCOMB_X18_Y12_N22 2 " "Info: 4: + IC(0.000 ns) + CELL(0.041 ns) = 2.239 ns; Loc. = LCCOMB_X18_Y12_N22; Fanout = 2; COMB Node = 'Add2~30'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add2~26 Add2~30 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 2.280 ns Add2~34 5 COMB LCCOMB_X18_Y12_N24 2 " "Info: 5: + IC(0.000 ns) + CELL(0.041 ns) = 2.280 ns; Loc. = LCCOMB_X18_Y12_N24; Fanout = 2; COMB Node = 'Add2~34'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add2~30 Add2~34 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 2.321 ns Add2~38 6 COMB LCCOMB_X18_Y12_N26 2 " "Info: 6: + IC(0.000 ns) + CELL(0.041 ns) = 2.321 ns; Loc. = LCCOMB_X18_Y12_N26; Fanout = 2; COMB Node = 'Add2~38'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add2~34 Add2~38 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 2.362 ns Add2~42 7 COMB LCCOMB_X18_Y12_N28 2 " "Info: 7: + IC(0.000 ns) + CELL(0.041 ns) = 2.362 ns; Loc. = LCCOMB_X18_Y12_N28; Fanout = 2; COMB Node = 'Add2~42'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add2~38 Add2~42 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.205 ns) 2.567 ns Add2~46 8 COMB LCCOMB_X18_Y12_N30 2 " "Info: 8: + IC(0.000 ns) + CELL(0.205 ns) = 2.567 ns; Loc. = LCCOMB_X18_Y12_N30; Fanout = 2; COMB Node = 'Add2~46'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.205 ns" { Add2~42 Add2~46 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 2.711 ns Add2~49 9 COMB LCCOMB_X18_Y11_N16 7 " "Info: 9: + IC(0.000 ns) + CELL(0.144 ns) = 2.711 ns; Loc. = LCCOMB_X18_Y11_N16; Fanout = 7; COMB Node = 'Add2~49'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add2~46 Add2~49 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.970 ns) + CELL(0.355 ns) 4.036 ns Add3~46 10 COMB LCCOMB_X19_Y13_N22 2 " "Info: 10: + IC(0.970 ns) + CELL(0.355 ns) = 4.036 ns; Loc. = LCCOMB_X19_Y13_N22; Fanout = 2; COMB Node = 'Add3~46'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.325 ns" { Add2~49 Add3~46 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 4.180 ns Add3~49 11 COMB LCCOMB_X19_Y13_N24 7 " "Info: 11: + IC(0.000 ns) + CELL(0.144 ns) = 4.180 ns; Loc. = LCCOMB_X19_Y13_N24; Fanout = 7; COMB Node = 'Add3~49'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add3~46 Add3~49 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.408 ns) + CELL(0.403 ns) 4.991 ns Add4~54 12 COMB LCCOMB_X18_Y13_N26 2 " "Info: 12: + IC(0.408 ns) + CELL(0.403 ns) = 4.991 ns; Loc. = LCCOMB_X18_Y13_N26; Fanout = 2; COMB Node = 'Add4~54'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { Add3~49 Add4~54 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 121 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 5.135 ns Add4~57 13 COMB LCCOMB_X18_Y13_N28 7 " "Info: 13: + IC(0.000 ns) + CELL(0.144 ns) = 5.135 ns; Loc. = LCCOMB_X18_Y13_N28; Fanout = 7; COMB Node = 'Add4~57'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add4~54 Add4~57 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 121 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.389 ns) + CELL(0.403 ns) 5.927 ns Add5~54 14 COMB LCCOMB_X17_Y13_N26 1 " "Info: 14: + IC(0.389 ns) + CELL(0.403 ns) = 5.927 ns; Loc. = LCCOMB_X17_Y13_N26; Fanout = 1; COMB Node = 'Add5~54'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.792 ns" { Add4~57 Add5~54 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 122 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 6.071 ns Add5~57 15 COMB LCCOMB_X17_Y13_N28 2 " "Info: 15: + IC(0.000 ns) + CELL(0.144 ns) = 6.071 ns; Loc. = LCCOMB_X17_Y13_N28; Fanout = 2; COMB Node = 'Add5~57'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add5~54 Add5~57 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 122 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.756 ns) + CELL(0.565 ns) 7.392 ns Add9~53 16 COMB LCCOMB_X17_Y11_N10 2 " "Info: 16: + IC(0.756 ns) + CELL(0.565 ns) = 7.392 ns; Loc. = LCCOMB_X17_Y11_N10; Fanout = 2; COMB Node = 'Add9~53'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.321 ns" { Add5~57 Add9~53 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 124 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.304 ns) + CELL(0.355 ns) 8.051 ns resultado\[13\] 17 REG LCFF_X17_Y11_N31 2 " "Info: 17: + IC(0.304 ns) + CELL(0.355 ns) = 8.051 ns; Loc. = LCFF_X17_Y11_N31; Fanout = 2; REG Node = 'resultado\[13\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.659 ns" { Add9~53 resultado[13] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.606 ns ( 44.79 % ) " "Info: Total cell delay = 3.606 ns ( 44.79 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.445 ns ( 55.21 % ) " "Info: Total interconnect delay = 4.445 ns ( 55.21 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.051 ns" { resultado[4] Mux86~0 Add2~26 Add2~30 Add2~34 Add2~38 Add2~42 Add2~46 Add2~49 Add3~46 Add3~49 Add4~54 Add4~57 Add5~54 Add5~57 Add9~53 resultado[13] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "8.051 ns" { resultado[4] {} Mux86~0 {} Add2~26 {} Add2~30 {} Add2~34 {} Add2~38 {} Add2~42 {} Add2~46 {} Add2~49 {} Add3~46 {} Add3~49 {} Add4~54 {} Add4~57 {} Add5~54 {} Add5~57 {} Add9~53 {} resultado[13] {} } { 0.000ns 0.254ns 1.364ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.970ns 0.000ns 0.408ns 0.000ns 0.389ns 0.000ns 0.756ns 0.304ns } { 0.000ns 0.177ns 0.403ns 0.041ns 0.041ns 0.041ns 0.041ns 0.205ns 0.144ns 0.355ns 0.144ns 0.403ns 0.144ns 0.403ns 0.144ns 0.565ns 0.355ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.001 ns - Smallest " "Info: - Smallest clock skew is -0.001 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i destination 2.829 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_i\" to destination register is 2.829 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.000 ns) 1.368 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 174 " "Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 174; COMB Node = 'clk_i~clkctrl'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.394 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.751 ns) + CELL(0.710 ns) 2.829 ns resultado\[13\] 3 REG LCFF_X17_Y11_N31 2 " "Info: 3: + IC(0.751 ns) + CELL(0.710 ns) = 2.829 ns; Loc. = LCFF_X17_Y11_N31; Fanout = 2; REG Node = 'resultado\[13\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.461 ns" { clk_i~clkctrl resultado[13] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.684 ns ( 59.53 % ) " "Info: Total cell delay = 1.684 ns ( 59.53 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.145 ns ( 40.47 % ) " "Info: Total interconnect delay = 1.145 ns ( 40.47 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.829 ns" { clk_i clk_i~clkctrl resultado[13] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.829 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[13] {} } { 0.000ns 0.000ns 0.394ns 0.751ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i source 2.830 ns - Longest register " "Info: - Longest clock path from clock \"clk_i\" to source register is 2.830 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.000 ns) 1.368 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 174 " "Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 174; COMB Node = 'clk_i~clkctrl'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.394 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.752 ns) + CELL(0.710 ns) 2.830 ns resultado\[4\] 3 REG LCFF_X17_Y12_N13 3 " "Info: 3: + IC(0.752 ns) + CELL(0.710 ns) = 2.830 ns; Loc. = LCFF_X17_Y12_N13; Fanout = 3; REG Node = 'resultado\[4\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.462 ns" { clk_i~clkctrl resultado[4] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.684 ns ( 59.51 % ) " "Info: Total cell delay = 1.684 ns ( 59.51 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.146 ns ( 40.49 % ) " "Info: Total interconnect delay = 1.146 ns ( 40.49 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.830 ns" { clk_i clk_i~clkctrl resultado[4] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.830 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[4] {} } { 0.000ns 0.000ns 0.394ns 0.752ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.829 ns" { clk_i clk_i~clkctrl resultado[13] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.829 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[13] {} } { 0.000ns 0.000ns 0.394ns 0.751ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.830 ns" { clk_i clk_i~clkctrl resultado[4] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.830 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[4] {} } { 0.000ns 0.000ns 0.394ns 0.752ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.109 ns + " "Info: + Micro clock to output delay of source is 0.109 ns" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.104 ns + " "Info: + Micro setup delay of destination is 0.104 ns" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "8.051 ns" { resultado[4] Mux86~0 Add2~26 Add2~30 Add2~34 Add2~38 Add2~42 Add2~46 Add2~49 Add3~46 Add3~49 Add4~54 Add4~57 Add5~54 Add5~57 Add9~53 resultado[13] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "8.051 ns" { resultado[4] {} Mux86~0 {} Add2~26 {} Add2~30 {} Add2~34 {} Add2~38 {} Add2~42 {} Add2~46 {} Add2~49 {} Add3~46 {} Add3~49 {} Add4~54 {} Add4~57 {} Add5~54 {} Add5~57 {} Add9~53 {} resultado[13] {} } { 0.000ns 0.254ns 1.364ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.970ns 0.000ns 0.408ns 0.000ns 0.389ns 0.000ns 0.756ns 0.304ns } { 0.000ns 0.177ns 0.403ns 0.041ns 0.041ns 0.041ns 0.041ns 0.205ns 0.144ns 0.355ns 0.144ns 0.403ns 0.144ns 0.403ns 0.144ns 0.565ns 0.355ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.829 ns" { clk_i clk_i~clkctrl resultado[13] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.829 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[13] {} } { 0.000ns 0.000ns 0.394ns 0.751ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.830 ns" { clk_i clk_i~clkctrl resultado[4] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.830 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[4] {} } { 0.000ns 0.000ns 0.394ns 0.752ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1} +{ "Info" "ITDB_TSU_RESULT" "resultado\[13\] extrapolar_i clk_i 10.977 ns register " "Info: tsu for register \"resultado\[13\]\" (data pin = \"extrapolar_i\", clock pin = \"clk_i\") is 10.977 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.702 ns + Longest pin register " "Info: + Longest pin to register delay is 13.702 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.944 ns) 0.944 ns extrapolar_i 1 PIN PIN_V11 43 " "Info: 1: + IC(0.000 ns) + CELL(0.944 ns) = 0.944 ns; Loc. = PIN_V11; Fanout = 43; PIN Node = 'extrapolar_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { extrapolar_i } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.825 ns) + CELL(0.313 ns) 6.082 ns Mux86~0 2 COMB LCCOMB_X17_Y12_N0 7 " "Info: 2: + IC(4.825 ns) + CELL(0.313 ns) = 6.082 ns; Loc. = LCCOMB_X17_Y12_N0; Fanout = 7; COMB Node = 'Mux86~0'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.138 ns" { extrapolar_i Mux86~0 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 126 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.364 ns) + CELL(0.403 ns) 7.849 ns Add2~26 3 COMB LCCOMB_X18_Y12_N20 2 " "Info: 3: + IC(1.364 ns) + CELL(0.403 ns) = 7.849 ns; Loc. = LCCOMB_X18_Y12_N20; Fanout = 2; COMB Node = 'Add2~26'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.767 ns" { Mux86~0 Add2~26 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 7.890 ns Add2~30 4 COMB LCCOMB_X18_Y12_N22 2 " "Info: 4: + IC(0.000 ns) + CELL(0.041 ns) = 7.890 ns; Loc. = LCCOMB_X18_Y12_N22; Fanout = 2; COMB Node = 'Add2~30'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add2~26 Add2~30 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 7.931 ns Add2~34 5 COMB LCCOMB_X18_Y12_N24 2 " "Info: 5: + IC(0.000 ns) + CELL(0.041 ns) = 7.931 ns; Loc. = LCCOMB_X18_Y12_N24; Fanout = 2; COMB Node = 'Add2~34'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add2~30 Add2~34 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 7.972 ns Add2~38 6 COMB LCCOMB_X18_Y12_N26 2 " "Info: 6: + IC(0.000 ns) + CELL(0.041 ns) = 7.972 ns; Loc. = LCCOMB_X18_Y12_N26; Fanout = 2; COMB Node = 'Add2~38'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add2~34 Add2~38 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 8.013 ns Add2~42 7 COMB LCCOMB_X18_Y12_N28 2 " "Info: 7: + IC(0.000 ns) + CELL(0.041 ns) = 8.013 ns; Loc. = LCCOMB_X18_Y12_N28; Fanout = 2; COMB Node = 'Add2~42'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add2~38 Add2~42 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.205 ns) 8.218 ns Add2~46 8 COMB LCCOMB_X18_Y12_N30 2 " "Info: 8: + IC(0.000 ns) + CELL(0.205 ns) = 8.218 ns; Loc. = LCCOMB_X18_Y12_N30; Fanout = 2; COMB Node = 'Add2~46'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.205 ns" { Add2~42 Add2~46 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 8.362 ns Add2~49 9 COMB LCCOMB_X18_Y11_N16 7 " "Info: 9: + IC(0.000 ns) + CELL(0.144 ns) = 8.362 ns; Loc. = LCCOMB_X18_Y11_N16; Fanout = 7; COMB Node = 'Add2~49'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add2~46 Add2~49 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.970 ns) + CELL(0.355 ns) 9.687 ns Add3~46 10 COMB LCCOMB_X19_Y13_N22 2 " "Info: 10: + IC(0.970 ns) + CELL(0.355 ns) = 9.687 ns; Loc. = LCCOMB_X19_Y13_N22; Fanout = 2; COMB Node = 'Add3~46'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.325 ns" { Add2~49 Add3~46 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 9.831 ns Add3~49 11 COMB LCCOMB_X19_Y13_N24 7 " "Info: 11: + IC(0.000 ns) + CELL(0.144 ns) = 9.831 ns; Loc. = LCCOMB_X19_Y13_N24; Fanout = 7; COMB Node = 'Add3~49'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add3~46 Add3~49 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.408 ns) + CELL(0.403 ns) 10.642 ns Add4~54 12 COMB LCCOMB_X18_Y13_N26 2 " "Info: 12: + IC(0.408 ns) + CELL(0.403 ns) = 10.642 ns; Loc. = LCCOMB_X18_Y13_N26; Fanout = 2; COMB Node = 'Add4~54'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.811 ns" { Add3~49 Add4~54 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 121 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 10.786 ns Add4~57 13 COMB LCCOMB_X18_Y13_N28 7 " "Info: 13: + IC(0.000 ns) + CELL(0.144 ns) = 10.786 ns; Loc. = LCCOMB_X18_Y13_N28; Fanout = 7; COMB Node = 'Add4~57'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add4~54 Add4~57 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 121 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.389 ns) + CELL(0.403 ns) 11.578 ns Add5~54 14 COMB LCCOMB_X17_Y13_N26 1 " "Info: 14: + IC(0.389 ns) + CELL(0.403 ns) = 11.578 ns; Loc. = LCCOMB_X17_Y13_N26; Fanout = 1; COMB Node = 'Add5~54'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.792 ns" { Add4~57 Add5~54 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 122 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 11.722 ns Add5~57 15 COMB LCCOMB_X17_Y13_N28 2 " "Info: 15: + IC(0.000 ns) + CELL(0.144 ns) = 11.722 ns; Loc. = LCCOMB_X17_Y13_N28; Fanout = 2; COMB Node = 'Add5~57'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add5~54 Add5~57 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 122 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.756 ns) + CELL(0.565 ns) 13.043 ns Add9~53 16 COMB LCCOMB_X17_Y11_N10 2 " "Info: 16: + IC(0.756 ns) + CELL(0.565 ns) = 13.043 ns; Loc. = LCCOMB_X17_Y11_N10; Fanout = 2; COMB Node = 'Add9~53'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.321 ns" { Add5~57 Add9~53 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 124 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.304 ns) + CELL(0.355 ns) 13.702 ns resultado\[13\] 17 REG LCFF_X17_Y11_N31 2 " "Info: 17: + IC(0.304 ns) + CELL(0.355 ns) = 13.702 ns; Loc. = LCFF_X17_Y11_N31; Fanout = 2; REG Node = 'resultado\[13\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.659 ns" { Add9~53 resultado[13] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.686 ns ( 34.20 % ) " "Info: Total cell delay = 4.686 ns ( 34.20 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "9.016 ns ( 65.80 % ) " "Info: Total interconnect delay = 9.016 ns ( 65.80 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "13.702 ns" { extrapolar_i Mux86~0 Add2~26 Add2~30 Add2~34 Add2~38 Add2~42 Add2~46 Add2~49 Add3~46 Add3~49 Add4~54 Add4~57 Add5~54 Add5~57 Add9~53 resultado[13] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "13.702 ns" { extrapolar_i {} extrapolar_i~combout {} Mux86~0 {} Add2~26 {} Add2~30 {} Add2~34 {} Add2~38 {} Add2~42 {} Add2~46 {} Add2~49 {} Add3~46 {} Add3~49 {} Add4~54 {} Add4~57 {} Add5~54 {} Add5~57 {} Add9~53 {} resultado[13] {} } { 0.000ns 0.000ns 4.825ns 1.364ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.970ns 0.000ns 0.408ns 0.000ns 0.389ns 0.000ns 0.756ns 0.304ns } { 0.000ns 0.944ns 0.313ns 0.403ns 0.041ns 0.041ns 0.041ns 0.041ns 0.205ns 0.144ns 0.355ns 0.144ns 0.403ns 0.144ns 0.403ns 0.144ns 0.565ns 0.355ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.104 ns + " "Info: + Micro setup delay of destination is 0.104 ns" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i destination 2.829 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_i\" to destination register is 2.829 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.000 ns) 1.368 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 174 " "Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 174; COMB Node = 'clk_i~clkctrl'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.394 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.751 ns) + CELL(0.710 ns) 2.829 ns resultado\[13\] 3 REG LCFF_X17_Y11_N31 2 " "Info: 3: + IC(0.751 ns) + CELL(0.710 ns) = 2.829 ns; Loc. = LCFF_X17_Y11_N31; Fanout = 2; REG Node = 'resultado\[13\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.461 ns" { clk_i~clkctrl resultado[13] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.684 ns ( 59.53 % ) " "Info: Total cell delay = 1.684 ns ( 59.53 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.145 ns ( 40.47 % ) " "Info: Total interconnect delay = 1.145 ns ( 40.47 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.829 ns" { clk_i clk_i~clkctrl resultado[13] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.829 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[13] {} } { 0.000ns 0.000ns 0.394ns 0.751ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "13.702 ns" { extrapolar_i Mux86~0 Add2~26 Add2~30 Add2~34 Add2~38 Add2~42 Add2~46 Add2~49 Add3~46 Add3~49 Add4~54 Add4~57 Add5~54 Add5~57 Add9~53 resultado[13] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "13.702 ns" { extrapolar_i {} extrapolar_i~combout {} Mux86~0 {} Add2~26 {} Add2~30 {} Add2~34 {} Add2~38 {} Add2~42 {} Add2~46 {} Add2~49 {} Add3~46 {} Add3~49 {} Add4~54 {} Add4~57 {} Add5~54 {} Add5~57 {} Add9~53 {} resultado[13] {} } { 0.000ns 0.000ns 4.825ns 1.364ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.970ns 0.000ns 0.408ns 0.000ns 0.389ns 0.000ns 0.756ns 0.304ns } { 0.000ns 0.944ns 0.313ns 0.403ns 0.041ns 0.041ns 0.041ns 0.041ns 0.205ns 0.144ns 0.355ns 0.144ns 0.403ns 0.144ns 0.403ns 0.144ns 0.565ns 0.355ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.829 ns" { clk_i clk_i~clkctrl resultado[13] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.829 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[13] {} } { 0.000ns 0.000ns 0.394ns 0.751ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_TCO_RESULT" "clk_i fxx3_o\[13\] fxx3_o\[13\]~reg0 7.983 ns register " "Info: tco from clock \"clk_i\" to destination pin \"fxx3_o\[13\]\" through register \"fxx3_o\[13\]~reg0\" is 7.983 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i source 2.829 ns + Longest register " "Info: + Longest clock path from clock \"clk_i\" to source register is 2.829 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.000 ns) 1.368 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 174 " "Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 174; COMB Node = 'clk_i~clkctrl'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.394 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.751 ns) + CELL(0.710 ns) 2.829 ns fxx3_o\[13\]~reg0 3 REG LCFF_X15_Y12_N1 1 " "Info: 3: + IC(0.751 ns) + CELL(0.710 ns) = 2.829 ns; Loc. = LCFF_X15_Y12_N1; Fanout = 1; REG Node = 'fxx3_o\[13\]~reg0'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.461 ns" { clk_i~clkctrl fxx3_o[13]~reg0 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.684 ns ( 59.53 % ) " "Info: Total cell delay = 1.684 ns ( 59.53 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.145 ns ( 40.47 % ) " "Info: Total interconnect delay = 1.145 ns ( 40.47 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.829 ns" { clk_i clk_i~clkctrl fxx3_o[13]~reg0 } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.829 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} fxx3_o[13]~reg0 {} } { 0.000ns 0.000ns 0.394ns 0.751ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.109 ns + " "Info: + Micro clock to output delay of source is 0.109 ns" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.045 ns + Longest register pin " "Info: + Longest register to pin delay is 5.045 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fxx3_o\[13\]~reg0 1 REG LCFF_X15_Y12_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y12_N1; Fanout = 1; REG Node = 'fxx3_o\[13\]~reg0'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[13]~reg0 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(2.445 ns) 5.045 ns fxx3_o\[13\] 2 PIN PIN_K3 0 " "Info: 2: + IC(2.600 ns) + CELL(2.445 ns) = 5.045 ns; Loc. = PIN_K3; Fanout = 0; PIN Node = 'fxx3_o\[13\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.045 ns" { fxx3_o[13]~reg0 fxx3_o[13] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.445 ns ( 48.46 % ) " "Info: Total cell delay = 2.445 ns ( 48.46 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns ( 51.54 % ) " "Info: Total interconnect delay = 2.600 ns ( 51.54 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.045 ns" { fxx3_o[13]~reg0 fxx3_o[13] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "5.045 ns" { fxx3_o[13]~reg0 {} fxx3_o[13] {} } { 0.000ns 2.600ns } { 0.000ns 2.445ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.829 ns" { clk_i clk_i~clkctrl fxx3_o[13]~reg0 } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.829 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} fxx3_o[13]~reg0 {} } { 0.000ns 0.000ns 0.394ns 0.751ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.045 ns" { fxx3_o[13]~reg0 fxx3_o[13] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "5.045 ns" { fxx3_o[13]~reg0 {} fxx3_o[13] {} } { 0.000ns 2.600ns } { 0.000ns 2.445ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1} +{ "Info" "ITDB_TH_RESULT" "fxx_o\[5\]~reg0 rst_i clk_i -0.647 ns register " "Info: th for register \"fxx_o\[5\]~reg0\" (data pin = \"rst_i\", clock pin = \"clk_i\") is -0.647 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i destination 2.829 ns + Longest register " "Info: + Longest clock path from clock \"clk_i\" to destination register is 2.829 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.000 ns) 1.368 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 174 " "Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 174; COMB Node = 'clk_i~clkctrl'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.394 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.751 ns) + CELL(0.710 ns) 2.829 ns fxx_o\[5\]~reg0 3 REG LCFF_X18_Y11_N3 1 " "Info: 3: + IC(0.751 ns) + CELL(0.710 ns) = 2.829 ns; Loc. = LCFF_X18_Y11_N3; Fanout = 1; REG Node = 'fxx_o\[5\]~reg0'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.461 ns" { clk_i~clkctrl fxx_o[5]~reg0 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.684 ns ( 59.53 % ) " "Info: Total cell delay = 1.684 ns ( 59.53 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.145 ns ( 40.47 % ) " "Info: Total interconnect delay = 1.145 ns ( 40.47 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.829 ns" { clk_i clk_i~clkctrl fxx_o[5]~reg0 } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.829 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} fxx_o[5]~reg0 {} } { 0.000ns 0.000ns 0.394ns 0.751ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.172 ns + " "Info: + Micro hold delay of destination is 0.172 ns" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.648 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.648 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns rst_i 1 PIN PIN_M21 86 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_M21; Fanout = 86; PIN Node = 'rst_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst_i } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 51 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.806 ns) + CELL(0.858 ns) 3.648 ns fxx_o\[5\]~reg0 2 REG LCFF_X18_Y11_N3 1 " "Info: 2: + IC(1.806 ns) + CELL(0.858 ns) = 3.648 ns; Loc. = LCFF_X18_Y11_N3; Fanout = 1; REG Node = 'fxx_o\[5\]~reg0'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.664 ns" { rst_i fxx_o[5]~reg0 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.842 ns ( 50.49 % ) " "Info: Total cell delay = 1.842 ns ( 50.49 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.806 ns ( 49.51 % ) " "Info: Total interconnect delay = 1.806 ns ( 49.51 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.648 ns" { rst_i fxx_o[5]~reg0 } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "3.648 ns" { rst_i {} rst_i~combout {} fxx_o[5]~reg0 {} } { 0.000ns 0.000ns 1.806ns } { 0.000ns 0.984ns 0.858ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.829 ns" { clk_i clk_i~clkctrl fxx_o[5]~reg0 } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.829 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} fxx_o[5]~reg0 {} } { 0.000ns 0.000ns 0.394ns 0.751ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.648 ns" { rst_i fxx_o[5]~reg0 } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "3.648 ns" { rst_i {} rst_i~combout {} fxx_o[5]~reg0 {} } { 0.000ns 0.000ns 1.806ns } { 0.000ns 0.984ns 0.858ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "152 " "Info: Peak virtual memory: 152 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 13 23:53:09 2012 " "Info: Processing ended: Mon Aug 13 23:53:09 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Info: Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} Index: trunk/QuartusII/db/prev_cmp_gnextrapolator.fit.qmsg =================================================================== --- trunk/QuartusII/db/prev_cmp_gnextrapolator.fit.qmsg (nonexistent) +++ trunk/QuartusII/db/prev_cmp_gnextrapolator.fit.qmsg (revision 5) @@ -0,0 +1,43 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 14 00:27:38 2012 " "Info: Processing started: Tue Aug 14 00:27:38 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolator " "Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolator" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "IMPP_MPP_USER_DEVICE" "gnextrapolator EP2S15F484C4 " "Info: Selected device EP2S15F484C4 for design \"gnextrapolator\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature." { } { } 0 0 "Feature %1!s! is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature." 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2S15F484I4 " "Info: Device EP2S15F484I4 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "1 " "Info: Fitter converted 1 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~DATA0~ E13 " "Info: Pin ~DATA0~ is reserved at location E13" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { ~DATA0~ } } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 1021 3016 4149 0} } } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 -1} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "107 107 " "Critical Warning: No exact pin location assignment(s) for 107 pins of 107 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[0\] " "Info: Pin fxx_o\[0\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[0] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 146 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[1\] " "Info: Pin fxx_o\[1\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[1] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 144 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[2\] " "Info: Pin fxx_o\[2\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[2] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 142 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[3\] " "Info: Pin fxx_o\[3\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[3] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 140 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[4\] " "Info: Pin fxx_o\[4\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[4] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 138 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[5\] " "Info: Pin fxx_o\[5\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[5] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 136 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[6\] " "Info: Pin fxx_o\[6\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[6] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 134 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[7\] " "Info: Pin fxx_o\[7\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[7] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 132 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[8\] " "Info: Pin fxx_o\[8\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[8] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 130 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[9\] " "Info: Pin fxx_o\[9\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[9] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 128 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[10\] " "Info: Pin fxx_o\[10\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[10] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 126 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[11\] " "Info: Pin fxx_o\[11\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[11] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 124 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[12\] " "Info: Pin fxx_o\[12\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[12] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 122 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[13\] " "Info: Pin fxx_o\[13\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[13] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 120 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[14\] " "Info: Pin fxx_o\[14\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[14] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 118 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[15\] " "Info: Pin fxx_o\[15\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[15] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 116 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[0\] " "Info: Pin fxx1_o\[0\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[0] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 178 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[1\] " "Info: Pin fxx1_o\[1\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[1] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 176 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[2\] " "Info: Pin fxx1_o\[2\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[2] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 174 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[3\] " "Info: Pin fxx1_o\[3\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[3] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 172 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[4\] " "Info: Pin fxx1_o\[4\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[4] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 170 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[5\] " "Info: Pin fxx1_o\[5\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[5] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 168 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[6\] " "Info: Pin fxx1_o\[6\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[6] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 166 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[7\] " "Info: Pin fxx1_o\[7\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[7] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 164 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[8\] " "Info: Pin fxx1_o\[8\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[8] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 162 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[9\] " "Info: Pin fxx1_o\[9\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[9] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 160 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[10\] " "Info: Pin fxx1_o\[10\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[10] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 158 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[11\] " "Info: Pin fxx1_o\[11\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[11] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 156 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[12\] " "Info: Pin fxx1_o\[12\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[12] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 154 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[13\] " "Info: Pin fxx1_o\[13\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[13] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 152 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[14\] " "Info: Pin fxx1_o\[14\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[14] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 150 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[15\] " "Info: Pin fxx1_o\[15\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[15] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 148 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[0\] " "Info: Pin fxx2_o\[0\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[0] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 210 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[1\] " "Info: Pin fxx2_o\[1\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[1] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 208 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[2\] " "Info: Pin fxx2_o\[2\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[2] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 206 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[3\] " "Info: Pin fxx2_o\[3\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[3] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 204 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[4\] " "Info: Pin fxx2_o\[4\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[4] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 202 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[5\] " "Info: Pin fxx2_o\[5\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[5] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 200 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[6\] " "Info: Pin fxx2_o\[6\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[6] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 198 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[7\] " "Info: Pin fxx2_o\[7\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[7] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 196 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[8\] " "Info: Pin fxx2_o\[8\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[8] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 194 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[9\] " "Info: Pin fxx2_o\[9\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[9] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 192 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[10\] " "Info: Pin fxx2_o\[10\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[10] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 190 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[11\] " "Info: Pin fxx2_o\[11\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[11] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 188 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[12\] " "Info: Pin fxx2_o\[12\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[12] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 186 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[13\] " "Info: Pin fxx2_o\[13\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[13] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 184 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[14\] " "Info: Pin fxx2_o\[14\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[14] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 182 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[15\] " "Info: Pin fxx2_o\[15\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[15] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 180 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[0\] " "Info: Pin fxx3_o\[0\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[0] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 242 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[1\] " "Info: Pin fxx3_o\[1\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[1] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 240 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[2\] " "Info: Pin fxx3_o\[2\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[2] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 238 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[3\] " "Info: Pin fxx3_o\[3\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[3] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 236 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[4\] " "Info: Pin fxx3_o\[4\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[4] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 234 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[5\] " "Info: Pin fxx3_o\[5\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[5] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 232 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[6\] " "Info: Pin fxx3_o\[6\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[6] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 230 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[7\] " "Info: Pin fxx3_o\[7\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[7] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 228 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[8\] " "Info: Pin fxx3_o\[8\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[8] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 226 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[9\] " "Info: Pin fxx3_o\[9\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[9] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 224 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[10\] " "Info: Pin fxx3_o\[10\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[10] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 222 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[11\] " "Info: Pin fxx3_o\[11\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[11] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 220 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[12\] " "Info: Pin fxx3_o\[12\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[12] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 218 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[13\] " "Info: Pin fxx3_o\[13\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[13] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 216 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[14\] " "Info: Pin fxx3_o\[14\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[14] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 214 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[15\] " "Info: Pin fxx3_o\[15\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[15] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 212 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[0\] " "Info: Pin fxx4_o\[0\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[0] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 274 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[1\] " "Info: Pin fxx4_o\[1\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[1] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 272 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[2\] " "Info: Pin fxx4_o\[2\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[2] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 270 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[3\] " "Info: Pin fxx4_o\[3\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[3] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 268 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[4\] " "Info: Pin fxx4_o\[4\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[4] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 266 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[5\] " "Info: Pin fxx4_o\[5\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[5] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 264 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[6\] " "Info: Pin fxx4_o\[6\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[6] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 262 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[7\] " "Info: Pin fxx4_o\[7\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[7] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 260 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[8\] " "Info: Pin fxx4_o\[8\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[8] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 258 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[9\] " "Info: Pin fxx4_o\[9\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[9] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 256 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[10\] " "Info: Pin fxx4_o\[10\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[10] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 254 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[11\] " "Info: Pin fxx4_o\[11\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[11] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 252 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[12\] " "Info: Pin fxx4_o\[12\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[12] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 250 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[13\] " "Info: Pin fxx4_o\[13\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[13] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 248 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[14\] " "Info: Pin fxx4_o\[14\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[14] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 246 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[15\] " "Info: Pin fxx4_o\[15\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[15] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 244 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[0\] " "Info: Pin resul_o\[0\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[0] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 306 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[1\] " "Info: Pin resul_o\[1\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[1] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 304 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[2\] " "Info: Pin resul_o\[2\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[2] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 302 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[3\] " "Info: Pin resul_o\[3\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[3] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 300 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[4\] " "Info: Pin resul_o\[4\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[4] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 298 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[5\] " "Info: Pin resul_o\[5\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[5] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 296 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[6\] " "Info: Pin resul_o\[6\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[6] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 294 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[7\] " "Info: Pin resul_o\[7\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[7] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 292 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[8\] " "Info: Pin resul_o\[8\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[8] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 290 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[9\] " "Info: Pin resul_o\[9\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[9] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 288 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[10\] " "Info: Pin resul_o\[10\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[10] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 286 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[11\] " "Info: Pin resul_o\[11\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[11] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 284 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[12\] " "Info: Pin resul_o\[12\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[12] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 282 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[13\] " "Info: Pin resul_o\[13\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[13] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 280 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[14\] " "Info: Pin resul_o\[14\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[14] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 278 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[15\] " "Info: Pin resul_o\[15\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[15] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 276 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "extrapolar_i " "Info: Pin extrapolar_i not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { extrapolar_i } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 54 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { extrapolar_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 328 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk_i " "Info: Pin clk_i not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { clk_i } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 327 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rst_i " "Info: Pin rst_i not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { rst_i } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 51 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 326 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[5\] " "Info: Pin distancia_i\[5\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[5] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 313 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[3\] " "Info: Pin distancia_i\[3\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[3] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 311 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[4\] " "Info: Pin distancia_i\[4\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[4] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 312 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[2\] " "Info: Pin distancia_i\[2\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[2] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 310 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[0\] " "Info: Pin distancia_i\[0\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[0] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 308 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[1\] " "Info: Pin distancia_i\[1\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[1] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 309 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[6\] " "Info: Pin distancia_i\[6\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[6] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 314 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[7\] " "Info: Pin distancia_i\[7\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[7] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 315 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 1 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 0 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "" 0 -1} +{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Timing-driven compilation is using the Classic Timing Analyzer" { } { } 0 0 "Timing-driven compilation is using the %1!s! Timing Analyzer" 0 0 "" 0 -1} +{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_i (placed in PIN N20 (CLK3p, Input)) " "Info: Automatically promoted node clk_i (placed in PIN N20 (CLK3p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { clk_i } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 327 3016 4149 0} } } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_i (placed in PIN M21 (CLK1p, Input)) " "Info: Automatically promoted node rst_i (placed in PIN M21 (CLK1p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G1 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "resultado\[0\] " "Info: Destination node resultado\[0\]" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resultado[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 110 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[15\]~reg0 " "Info: Destination node fxx_o\[15\]~reg0" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[15]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 117 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[14\]~reg0 " "Info: Destination node fxx_o\[14\]~reg0" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[14]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 119 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[13\]~reg0 " "Info: Destination node fxx_o\[13\]~reg0" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[13]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 121 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[12\]~reg0 " "Info: Destination node fxx_o\[12\]~reg0" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[12]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 123 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[11\]~reg0 " "Info: Destination node fxx_o\[11\]~reg0" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[11]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 125 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[10\]~reg0 " "Info: Destination node fxx_o\[10\]~reg0" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[10]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 127 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[9\]~reg0 " "Info: Destination node fxx_o\[9\]~reg0" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[9]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 129 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[8\]~reg0 " "Info: Destination node fxx_o\[8\]~reg0" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[8]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 131 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[7\]~reg0 " "Info: Destination node fxx_o\[7\]~reg0" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[7]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 133 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Info: Non-global destination nodes limited to 10 nodes" { } { } 0 0 "Non-global destination nodes limited to %1!d! nodes" 0 0 "" 0 -1} } { } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { rst_i } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 51 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 326 3016 4149 0} } } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 0 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 0 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 0 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 0 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 0 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "105 unused 3.3V 9 96 0 " "Info: Number of I/O pins in group: 105 (unused VREF, 3.3V VCCIO, 9 input, 96 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 1 39 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 39 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 1 43 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 43 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 49 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 49 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 35 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 44 " "Info: I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 44 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 0 40 " "Info: I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 34 " "Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 34 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "Info: I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use undetermined 0 6 " "Info: I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "10 does not use undetermined 0 6 " "Info: I/O bank number 10 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Info: Fitter preparation operations ending: elapsed time is 00:00:03" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Info: Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "10.924 ns memory register " "Info: Estimated most critical path is memory to register delay of 10.924 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a7~porta_address_reg4 1 MEM M512_X24_Y8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M512_X24_Y8; Fanout = 1; MEM Node = 'altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a7~porta_address_reg4'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7~porta_address_reg4 } "NODE_NAME" } } { "db/altsyncram_uv61.tdf" "" { Text "C:/Altera/qdesigns/gnextrapolator/db/altsyncram_uv61.tdf" 174 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.061 ns) 2.061 ns altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a7 2 MEM M512_X24_Y8 6 " "Info: 2: + IC(0.000 ns) + CELL(2.061 ns) = 2.061 ns; Loc. = M512_X24_Y8; Fanout = 6; MEM Node = 'altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a7'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.061 ns" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7~porta_address_reg4 altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7 } "NODE_NAME" } } { "db/altsyncram_uv61.tdf" "" { Text "C:/Altera/qdesigns/gnextrapolator/db/altsyncram_uv61.tdf" 174 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.821 ns) + CELL(0.313 ns) 3.195 ns fx~23 3 COMB LAB_X27_Y5 2 " "Info: 3: + IC(0.821 ns) + CELL(0.313 ns) = 3.195 ns; Loc. = LAB_X27_Y5; Fanout = 2; COMB Node = 'fx~23'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.134 ns" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7 fx~23 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 89 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.879 ns) + CELL(0.480 ns) 4.554 ns Add2~37 4 COMB LAB_X23_Y8 6 " "Info: 4: + IC(0.879 ns) + CELL(0.480 ns) = 4.554 ns; Loc. = LAB_X23_Y8; Fanout = 6; COMB Node = 'Add2~37'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.359 ns" { fx~23 Add2~37 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.580 ns) + CELL(0.480 ns) 5.614 ns Add3~33 5 COMB LAB_X22_Y7 7 " "Info: 5: + IC(0.580 ns) + CELL(0.480 ns) = 5.614 ns; Loc. = LAB_X22_Y7; Fanout = 7; COMB Node = 'Add3~33'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.060 ns" { Add2~37 Add3~33 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.833 ns) + CELL(0.426 ns) 6.873 ns Add4~37 6 COMB LAB_X22_Y6 7 " "Info: 6: + IC(0.833 ns) + CELL(0.426 ns) = 6.873 ns; Loc. = LAB_X22_Y6; Fanout = 7; COMB Node = 'Add4~37'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.259 ns" { Add3~33 Add4~37 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.775 ns) + CELL(0.480 ns) 8.128 ns Add8~29 7 COMB LAB_X25_Y6 2 " "Info: 7: + IC(0.775 ns) + CELL(0.480 ns) = 8.128 ns; Loc. = LAB_X25_Y6; Fanout = 2; COMB Node = 'Add8~29'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.255 ns" { Add4~37 Add8~29 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.580 ns) + CELL(0.403 ns) 9.111 ns Add9~30 8 COMB LAB_X26_Y5 2 " "Info: 8: + IC(0.580 ns) + CELL(0.403 ns) = 9.111 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~30'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.983 ns" { Add8~29 Add9~30 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.102 ns) + CELL(0.041 ns) 9.254 ns Add9~34 9 COMB LAB_X26_Y5 2 " "Info: 9: + IC(0.102 ns) + CELL(0.041 ns) = 9.254 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~34'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { Add9~30 Add9~34 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 9.295 ns Add9~38 10 COMB LAB_X26_Y5 2 " "Info: 10: + IC(0.000 ns) + CELL(0.041 ns) = 9.295 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~38'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add9~34 Add9~38 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 9.336 ns Add9~42 11 COMB LAB_X26_Y5 2 " "Info: 11: + IC(0.000 ns) + CELL(0.041 ns) = 9.336 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~42'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add9~38 Add9~42 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 9.377 ns Add9~46 12 COMB LAB_X26_Y5 2 " "Info: 12: + IC(0.000 ns) + CELL(0.041 ns) = 9.377 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~46'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add9~42 Add9~46 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 9.418 ns Add9~50 13 COMB LAB_X26_Y5 2 " "Info: 13: + IC(0.000 ns) + CELL(0.041 ns) = 9.418 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~50'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add9~46 Add9~50 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 9.459 ns Add9~54 14 COMB LAB_X26_Y5 2 " "Info: 14: + IC(0.000 ns) + CELL(0.041 ns) = 9.459 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~54'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add9~50 Add9~54 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 9.500 ns Add9~58 15 COMB LAB_X26_Y5 1 " "Info: 15: + IC(0.000 ns) + CELL(0.041 ns) = 9.500 ns; Loc. = LAB_X26_Y5; Fanout = 1; COMB Node = 'Add9~58'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add9~54 Add9~58 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 9.644 ns Add9~61 16 COMB LAB_X26_Y5 2 " "Info: 16: + IC(0.000 ns) + CELL(0.144 ns) = 9.644 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~61'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add9~58 Add9~61 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.102 ns) + CELL(0.178 ns) 10.924 ns resultado\[15\] 17 REG LAB_X23_Y7 4 " "Info: 17: + IC(1.102 ns) + CELL(0.178 ns) = 10.924 ns; Loc. = LAB_X23_Y7; Fanout = 4; REG Node = 'resultado\[15\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.280 ns" { Add9~61 resultado[15] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.252 ns ( 48.08 % ) " "Info: Total cell delay = 5.252 ns ( 48.08 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.672 ns ( 51.92 % ) " "Info: Total interconnect delay = 5.672 ns ( 51.92 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "10.924 ns" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7~porta_address_reg4 altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7 fx~23 Add2~37 Add3~33 Add4~37 Add8~29 Add9~30 Add9~34 Add9~38 Add9~42 Add9~46 Add9~50 Add9~54 Add9~58 Add9~61 resultado[15] } "NODE_NAME" } } } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X13_Y0 X26_Y13 " "Info: Peak interconnect usage is 2% of the available device resources in the region that extends from location X13_Y0 to location X26_Y13" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Info: Fitter routing operations ending: elapsed time is 00:00:02" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1} +{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} +{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "96 " "Warning: Found 96 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[0\] 0 " "Info: Pin \"fxx_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[1\] 0 " "Info: Pin \"fxx_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[2\] 0 " "Info: Pin \"fxx_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[3\] 0 " "Info: Pin \"fxx_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[4\] 0 " "Info: Pin \"fxx_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[5\] 0 " "Info: Pin \"fxx_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[6\] 0 " "Info: Pin \"fxx_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[7\] 0 " "Info: Pin \"fxx_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[8\] 0 " "Info: Pin \"fxx_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[9\] 0 " "Info: Pin \"fxx_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[10\] 0 " "Info: Pin \"fxx_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[11\] 0 " "Info: Pin \"fxx_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[12\] 0 " "Info: Pin \"fxx_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[13\] 0 " "Info: Pin \"fxx_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[14\] 0 " "Info: Pin \"fxx_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[15\] 0 " "Info: Pin \"fxx_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[0\] 0 " "Info: Pin \"fxx1_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[1\] 0 " "Info: Pin \"fxx1_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[2\] 0 " "Info: Pin \"fxx1_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[3\] 0 " "Info: Pin \"fxx1_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[4\] 0 " "Info: Pin \"fxx1_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[5\] 0 " "Info: Pin \"fxx1_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[6\] 0 " "Info: Pin \"fxx1_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[7\] 0 " "Info: Pin \"fxx1_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[8\] 0 " "Info: Pin \"fxx1_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[9\] 0 " "Info: Pin \"fxx1_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[10\] 0 " "Info: Pin \"fxx1_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[11\] 0 " "Info: Pin \"fxx1_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[12\] 0 " "Info: Pin \"fxx1_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[13\] 0 " "Info: Pin \"fxx1_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[14\] 0 " "Info: Pin \"fxx1_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[15\] 0 " "Info: Pin \"fxx1_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[0\] 0 " "Info: Pin \"fxx2_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[1\] 0 " "Info: Pin \"fxx2_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[2\] 0 " "Info: Pin \"fxx2_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[3\] 0 " "Info: Pin \"fxx2_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[4\] 0 " "Info: Pin \"fxx2_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[5\] 0 " "Info: Pin \"fxx2_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[6\] 0 " "Info: Pin \"fxx2_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[7\] 0 " "Info: Pin \"fxx2_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[8\] 0 " "Info: Pin \"fxx2_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[9\] 0 " "Info: Pin \"fxx2_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[10\] 0 " "Info: Pin \"fxx2_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[11\] 0 " "Info: Pin \"fxx2_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[12\] 0 " "Info: Pin \"fxx2_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[13\] 0 " "Info: Pin \"fxx2_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[14\] 0 " "Info: Pin \"fxx2_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[15\] 0 " "Info: Pin \"fxx2_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[0\] 0 " "Info: Pin \"fxx3_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[1\] 0 " "Info: Pin \"fxx3_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[2\] 0 " "Info: Pin \"fxx3_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[3\] 0 " "Info: Pin \"fxx3_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[4\] 0 " "Info: Pin \"fxx3_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[5\] 0 " "Info: Pin \"fxx3_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[6\] 0 " "Info: Pin \"fxx3_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[7\] 0 " "Info: Pin \"fxx3_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[8\] 0 " "Info: Pin \"fxx3_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[9\] 0 " "Info: Pin \"fxx3_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[10\] 0 " "Info: Pin \"fxx3_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[11\] 0 " "Info: Pin \"fxx3_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[12\] 0 " "Info: Pin \"fxx3_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[13\] 0 " "Info: Pin \"fxx3_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[14\] 0 " "Info: Pin \"fxx3_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[15\] 0 " "Info: Pin \"fxx3_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[0\] 0 " "Info: Pin \"fxx4_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[1\] 0 " "Info: Pin \"fxx4_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[2\] 0 " "Info: Pin \"fxx4_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[3\] 0 " "Info: Pin \"fxx4_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[4\] 0 " "Info: Pin \"fxx4_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[5\] 0 " "Info: Pin \"fxx4_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[6\] 0 " "Info: Pin \"fxx4_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[7\] 0 " "Info: Pin \"fxx4_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[8\] 0 " "Info: Pin \"fxx4_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[9\] 0 " "Info: Pin \"fxx4_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[10\] 0 " "Info: Pin \"fxx4_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[11\] 0 " "Info: Pin \"fxx4_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[12\] 0 " "Info: Pin \"fxx4_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[13\] 0 " "Info: Pin \"fxx4_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[14\] 0 " "Info: Pin \"fxx4_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[15\] 0 " "Info: Pin \"fxx4_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[0\] 0 " "Info: Pin \"resul_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[1\] 0 " "Info: Pin \"resul_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[2\] 0 " "Info: Pin \"resul_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[3\] 0 " "Info: Pin \"resul_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[4\] 0 " "Info: Pin \"resul_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[5\] 0 " "Info: Pin \"resul_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[6\] 0 " "Info: Pin \"resul_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[7\] 0 " "Info: Pin \"resul_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[8\] 0 " "Info: Pin \"resul_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[9\] 0 " "Info: Pin \"resul_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[10\] 0 " "Info: Pin \"resul_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[11\] 0 " "Info: Pin \"resul_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[12\] 0 " "Info: Pin \"resul_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[13\] 0 " "Info: Pin \"resul_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[14\] 0 " "Info: Pin \"resul_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[15\] 0 " "Info: Pin \"resul_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1} +{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "233 " "Info: Peak virtual memory: 233 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 14 00:28:05 2012 " "Info: Processing ended: Tue Aug 14 00:28:05 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:27 " "Info: Elapsed time: 00:00:27" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:27 " "Info: Total CPU time (on all processors): 00:00:27" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} Index: trunk/QuartusII/db/gnextrapolator.rtlv.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.rtlv.hdb =================================================================== --- trunk/QuartusII/db/gnextrapolator.rtlv.hdb (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.rtlv.hdb (revision 5)
trunk/QuartusII/db/gnextrapolator.rtlv.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.lpc.rdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.lpc.rdb =================================================================== --- trunk/QuartusII/db/gnextrapolator.lpc.rdb (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.lpc.rdb (revision 5)
trunk/QuartusII/db/gnextrapolator.lpc.rdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.cmp0.ddb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.cmp0.ddb =================================================================== --- trunk/QuartusII/db/gnextrapolator.cmp0.ddb (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.cmp0.ddb (revision 5)
trunk/QuartusII/db/gnextrapolator.cmp0.ddb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.fit.qmsg =================================================================== --- trunk/QuartusII/db/gnextrapolator.fit.qmsg (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.fit.qmsg (revision 5) @@ -0,0 +1,43 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 14 00:27:38 2012 " "Info: Processing started: Tue Aug 14 00:27:38 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolator " "Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolator" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "IMPP_MPP_USER_DEVICE" "gnextrapolator EP2S15F484C4 " "Info: Selected device EP2S15F484C4 for design \"gnextrapolator\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature." { } { } 0 0 "Feature %1!s! is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature." 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2S15F484I4 " "Info: Device EP2S15F484I4 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "1 " "Info: Fitter converted 1 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~DATA0~ E13 " "Info: Pin ~DATA0~ is reserved at location E13" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { ~DATA0~ } } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 1021 3016 4149 0} } } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 -1} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "107 107 " "Critical Warning: No exact pin location assignment(s) for 107 pins of 107 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[0\] " "Info: Pin fxx_o\[0\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[0] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 146 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[1\] " "Info: Pin fxx_o\[1\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[1] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 144 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[2\] " "Info: Pin fxx_o\[2\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[2] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 142 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[3\] " "Info: Pin fxx_o\[3\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[3] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 140 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[4\] " "Info: Pin fxx_o\[4\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[4] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 138 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[5\] " "Info: Pin fxx_o\[5\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[5] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 136 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[6\] " "Info: Pin fxx_o\[6\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[6] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 134 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[7\] " "Info: Pin fxx_o\[7\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[7] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 132 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[8\] " "Info: Pin fxx_o\[8\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[8] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 130 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[9\] " "Info: Pin fxx_o\[9\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[9] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 128 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[10\] " "Info: Pin fxx_o\[10\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[10] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 126 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[11\] " "Info: Pin fxx_o\[11\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[11] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 124 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[12\] " "Info: Pin fxx_o\[12\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[12] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 122 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[13\] " "Info: Pin fxx_o\[13\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[13] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 120 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[14\] " "Info: Pin fxx_o\[14\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[14] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 118 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[15\] " "Info: Pin fxx_o\[15\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[15] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 116 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[0\] " "Info: Pin fxx1_o\[0\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[0] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 178 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[1\] " "Info: Pin fxx1_o\[1\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[1] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 176 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[2\] " "Info: Pin fxx1_o\[2\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[2] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 174 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[3\] " "Info: Pin fxx1_o\[3\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[3] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 172 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[4\] " "Info: Pin fxx1_o\[4\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[4] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 170 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[5\] " "Info: Pin fxx1_o\[5\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[5] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 168 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[6\] " "Info: Pin fxx1_o\[6\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[6] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 166 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[7\] " "Info: Pin fxx1_o\[7\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[7] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 164 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[8\] " "Info: Pin fxx1_o\[8\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[8] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 162 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[9\] " "Info: Pin fxx1_o\[9\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[9] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 160 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[10\] " "Info: Pin fxx1_o\[10\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[10] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 158 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[11\] " "Info: Pin fxx1_o\[11\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[11] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 156 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[12\] " "Info: Pin fxx1_o\[12\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[12] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 154 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[13\] " "Info: Pin fxx1_o\[13\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[13] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 152 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[14\] " "Info: Pin fxx1_o\[14\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[14] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 150 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[15\] " "Info: Pin fxx1_o\[15\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[15] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 148 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[0\] " "Info: Pin fxx2_o\[0\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[0] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 210 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[1\] " "Info: Pin fxx2_o\[1\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[1] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 208 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[2\] " "Info: Pin fxx2_o\[2\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[2] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 206 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[3\] " "Info: Pin fxx2_o\[3\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[3] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 204 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[4\] " "Info: Pin fxx2_o\[4\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[4] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 202 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[5\] " "Info: Pin fxx2_o\[5\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[5] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 200 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[6\] " "Info: Pin fxx2_o\[6\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[6] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 198 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[7\] " "Info: Pin fxx2_o\[7\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[7] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 196 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[8\] " "Info: Pin fxx2_o\[8\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[8] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 194 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[9\] " "Info: Pin fxx2_o\[9\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[9] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 192 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[10\] " "Info: Pin fxx2_o\[10\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[10] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 190 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[11\] " "Info: Pin fxx2_o\[11\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[11] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 188 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[12\] " "Info: Pin fxx2_o\[12\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[12] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 186 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[13\] " "Info: Pin fxx2_o\[13\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[13] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 184 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[14\] " "Info: Pin fxx2_o\[14\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[14] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 182 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[15\] " "Info: Pin fxx2_o\[15\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[15] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 180 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[0\] " "Info: Pin fxx3_o\[0\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[0] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 242 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[1\] " "Info: Pin fxx3_o\[1\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[1] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 240 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[2\] " "Info: Pin fxx3_o\[2\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[2] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 238 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[3\] " "Info: Pin fxx3_o\[3\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[3] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 236 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[4\] " "Info: Pin fxx3_o\[4\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[4] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 234 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[5\] " "Info: Pin fxx3_o\[5\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[5] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 232 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[6\] " "Info: Pin fxx3_o\[6\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[6] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 230 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[7\] " "Info: Pin fxx3_o\[7\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[7] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 228 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[8\] " "Info: Pin fxx3_o\[8\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[8] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 226 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[9\] " "Info: Pin fxx3_o\[9\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[9] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 224 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[10\] " "Info: Pin fxx3_o\[10\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[10] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 222 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[11\] " "Info: Pin fxx3_o\[11\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[11] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 220 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[12\] " "Info: Pin fxx3_o\[12\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[12] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 218 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[13\] " "Info: Pin fxx3_o\[13\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[13] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 216 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[14\] " "Info: Pin fxx3_o\[14\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[14] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 214 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[15\] " "Info: Pin fxx3_o\[15\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[15] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 212 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[0\] " "Info: Pin fxx4_o\[0\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[0] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 274 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[1\] " "Info: Pin fxx4_o\[1\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[1] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 272 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[2\] " "Info: Pin fxx4_o\[2\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[2] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 270 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[3\] " "Info: Pin fxx4_o\[3\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[3] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 268 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[4\] " "Info: Pin fxx4_o\[4\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[4] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 266 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[5\] " "Info: Pin fxx4_o\[5\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[5] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 264 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[6\] " "Info: Pin fxx4_o\[6\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[6] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 262 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[7\] " "Info: Pin fxx4_o\[7\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[7] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 260 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[8\] " "Info: Pin fxx4_o\[8\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[8] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 258 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[9\] " "Info: Pin fxx4_o\[9\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[9] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 256 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[10\] " "Info: Pin fxx4_o\[10\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[10] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 254 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[11\] " "Info: Pin fxx4_o\[11\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[11] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 252 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[12\] " "Info: Pin fxx4_o\[12\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[12] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 250 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[13\] " "Info: Pin fxx4_o\[13\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[13] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 248 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[14\] " "Info: Pin fxx4_o\[14\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[14] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 246 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[15\] " "Info: Pin fxx4_o\[15\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[15] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 244 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[0\] " "Info: Pin resul_o\[0\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[0] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 306 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[1\] " "Info: Pin resul_o\[1\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[1] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 304 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[2\] " "Info: Pin resul_o\[2\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[2] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 302 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[3\] " "Info: Pin resul_o\[3\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[3] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 300 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[4\] " "Info: Pin resul_o\[4\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[4] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 298 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[5\] " "Info: Pin resul_o\[5\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[5] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 296 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[6\] " "Info: Pin resul_o\[6\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[6] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 294 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[7\] " "Info: Pin resul_o\[7\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[7] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 292 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[8\] " "Info: Pin resul_o\[8\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[8] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 290 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[9\] " "Info: Pin resul_o\[9\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[9] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 288 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[10\] " "Info: Pin resul_o\[10\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[10] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 286 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[11\] " "Info: Pin resul_o\[11\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[11] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 284 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[12\] " "Info: Pin resul_o\[12\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[12] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 282 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[13\] " "Info: Pin resul_o\[13\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[13] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 280 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[14\] " "Info: Pin resul_o\[14\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[14] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 278 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[15\] " "Info: Pin resul_o\[15\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[15] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 276 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "extrapolar_i " "Info: Pin extrapolar_i not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { extrapolar_i } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 54 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { extrapolar_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 328 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk_i " "Info: Pin clk_i not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { clk_i } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 327 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rst_i " "Info: Pin rst_i not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { rst_i } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 51 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 326 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[5\] " "Info: Pin distancia_i\[5\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[5] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 313 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[3\] " "Info: Pin distancia_i\[3\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[3] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 311 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[4\] " "Info: Pin distancia_i\[4\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[4] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 312 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[2\] " "Info: Pin distancia_i\[2\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[2] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 310 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[0\] " "Info: Pin distancia_i\[0\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[0] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 308 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[1\] " "Info: Pin distancia_i\[1\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[1] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 309 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[6\] " "Info: Pin distancia_i\[6\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[6] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 314 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[7\] " "Info: Pin distancia_i\[7\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[7] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 315 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 1 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 0 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "" 0 -1} +{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Timing-driven compilation is using the Classic Timing Analyzer" { } { } 0 0 "Timing-driven compilation is using the %1!s! Timing Analyzer" 0 0 "" 0 -1} +{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_i (placed in PIN N20 (CLK3p, Input)) " "Info: Automatically promoted node clk_i (placed in PIN N20 (CLK3p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { clk_i } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 327 3016 4149 0} } } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_i (placed in PIN M21 (CLK1p, Input)) " "Info: Automatically promoted node rst_i (placed in PIN M21 (CLK1p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G1 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "resultado\[0\] " "Info: Destination node resultado\[0\]" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resultado[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 110 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[15\]~reg0 " "Info: Destination node fxx_o\[15\]~reg0" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[15]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 117 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[14\]~reg0 " "Info: Destination node fxx_o\[14\]~reg0" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[14]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 119 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[13\]~reg0 " "Info: Destination node fxx_o\[13\]~reg0" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[13]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 121 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[12\]~reg0 " "Info: Destination node fxx_o\[12\]~reg0" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[12]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 123 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[11\]~reg0 " "Info: Destination node fxx_o\[11\]~reg0" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[11]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 125 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[10\]~reg0 " "Info: Destination node fxx_o\[10\]~reg0" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[10]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 127 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[9\]~reg0 " "Info: Destination node fxx_o\[9\]~reg0" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[9]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 129 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[8\]~reg0 " "Info: Destination node fxx_o\[8\]~reg0" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[8]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 131 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[7\]~reg0 " "Info: Destination node fxx_o\[7\]~reg0" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[7]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 133 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Info: Non-global destination nodes limited to 10 nodes" { } { } 0 0 "Non-global destination nodes limited to %1!d! nodes" 0 0 "" 0 -1} } { } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { rst_i } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 51 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 326 3016 4149 0} } } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 0 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 0 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 0 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 0 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 0 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "105 unused 3.3V 9 96 0 " "Info: Number of I/O pins in group: 105 (unused VREF, 3.3V VCCIO, 9 input, 96 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 1 39 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 39 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 1 43 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 43 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 49 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 49 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 35 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 44 " "Info: I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 44 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 0 40 " "Info: I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 34 " "Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 34 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "Info: I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use undetermined 0 6 " "Info: I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "10 does not use undetermined 0 6 " "Info: I/O bank number 10 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Info: Fitter preparation operations ending: elapsed time is 00:00:03" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Info: Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "10.924 ns memory register " "Info: Estimated most critical path is memory to register delay of 10.924 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a7~porta_address_reg4 1 MEM M512_X24_Y8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M512_X24_Y8; Fanout = 1; MEM Node = 'altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a7~porta_address_reg4'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7~porta_address_reg4 } "NODE_NAME" } } { "db/altsyncram_uv61.tdf" "" { Text "C:/Altera/qdesigns/gnextrapolator/db/altsyncram_uv61.tdf" 174 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.061 ns) 2.061 ns altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a7 2 MEM M512_X24_Y8 6 " "Info: 2: + IC(0.000 ns) + CELL(2.061 ns) = 2.061 ns; Loc. = M512_X24_Y8; Fanout = 6; MEM Node = 'altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a7'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.061 ns" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7~porta_address_reg4 altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7 } "NODE_NAME" } } { "db/altsyncram_uv61.tdf" "" { Text "C:/Altera/qdesigns/gnextrapolator/db/altsyncram_uv61.tdf" 174 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.821 ns) + CELL(0.313 ns) 3.195 ns fx~23 3 COMB LAB_X27_Y5 2 " "Info: 3: + IC(0.821 ns) + CELL(0.313 ns) = 3.195 ns; Loc. = LAB_X27_Y5; Fanout = 2; COMB Node = 'fx~23'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.134 ns" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7 fx~23 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 89 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.879 ns) + CELL(0.480 ns) 4.554 ns Add2~37 4 COMB LAB_X23_Y8 6 " "Info: 4: + IC(0.879 ns) + CELL(0.480 ns) = 4.554 ns; Loc. = LAB_X23_Y8; Fanout = 6; COMB Node = 'Add2~37'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.359 ns" { fx~23 Add2~37 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.580 ns) + CELL(0.480 ns) 5.614 ns Add3~33 5 COMB LAB_X22_Y7 7 " "Info: 5: + IC(0.580 ns) + CELL(0.480 ns) = 5.614 ns; Loc. = LAB_X22_Y7; Fanout = 7; COMB Node = 'Add3~33'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.060 ns" { Add2~37 Add3~33 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.833 ns) + CELL(0.426 ns) 6.873 ns Add4~37 6 COMB LAB_X22_Y6 7 " "Info: 6: + IC(0.833 ns) + CELL(0.426 ns) = 6.873 ns; Loc. = LAB_X22_Y6; Fanout = 7; COMB Node = 'Add4~37'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.259 ns" { Add3~33 Add4~37 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.775 ns) + CELL(0.480 ns) 8.128 ns Add8~29 7 COMB LAB_X25_Y6 2 " "Info: 7: + IC(0.775 ns) + CELL(0.480 ns) = 8.128 ns; Loc. = LAB_X25_Y6; Fanout = 2; COMB Node = 'Add8~29'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.255 ns" { Add4~37 Add8~29 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.580 ns) + CELL(0.403 ns) 9.111 ns Add9~30 8 COMB LAB_X26_Y5 2 " "Info: 8: + IC(0.580 ns) + CELL(0.403 ns) = 9.111 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~30'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.983 ns" { Add8~29 Add9~30 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.102 ns) + CELL(0.041 ns) 9.254 ns Add9~34 9 COMB LAB_X26_Y5 2 " "Info: 9: + IC(0.102 ns) + CELL(0.041 ns) = 9.254 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~34'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { Add9~30 Add9~34 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 9.295 ns Add9~38 10 COMB LAB_X26_Y5 2 " "Info: 10: + IC(0.000 ns) + CELL(0.041 ns) = 9.295 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~38'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add9~34 Add9~38 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 9.336 ns Add9~42 11 COMB LAB_X26_Y5 2 " "Info: 11: + IC(0.000 ns) + CELL(0.041 ns) = 9.336 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~42'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add9~38 Add9~42 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 9.377 ns Add9~46 12 COMB LAB_X26_Y5 2 " "Info: 12: + IC(0.000 ns) + CELL(0.041 ns) = 9.377 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~46'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add9~42 Add9~46 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 9.418 ns Add9~50 13 COMB LAB_X26_Y5 2 " "Info: 13: + IC(0.000 ns) + CELL(0.041 ns) = 9.418 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~50'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add9~46 Add9~50 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 9.459 ns Add9~54 14 COMB LAB_X26_Y5 2 " "Info: 14: + IC(0.000 ns) + CELL(0.041 ns) = 9.459 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~54'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add9~50 Add9~54 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 9.500 ns Add9~58 15 COMB LAB_X26_Y5 1 " "Info: 15: + IC(0.000 ns) + CELL(0.041 ns) = 9.500 ns; Loc. = LAB_X26_Y5; Fanout = 1; COMB Node = 'Add9~58'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add9~54 Add9~58 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 9.644 ns Add9~61 16 COMB LAB_X26_Y5 2 " "Info: 16: + IC(0.000 ns) + CELL(0.144 ns) = 9.644 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~61'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add9~58 Add9~61 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.102 ns) + CELL(0.178 ns) 10.924 ns resultado\[15\] 17 REG LAB_X23_Y7 4 " "Info: 17: + IC(1.102 ns) + CELL(0.178 ns) = 10.924 ns; Loc. = LAB_X23_Y7; Fanout = 4; REG Node = 'resultado\[15\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.280 ns" { Add9~61 resultado[15] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.252 ns ( 48.08 % ) " "Info: Total cell delay = 5.252 ns ( 48.08 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.672 ns ( 51.92 % ) " "Info: Total interconnect delay = 5.672 ns ( 51.92 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "10.924 ns" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7~porta_address_reg4 altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7 fx~23 Add2~37 Add3~33 Add4~37 Add8~29 Add9~30 Add9~34 Add9~38 Add9~42 Add9~46 Add9~50 Add9~54 Add9~58 Add9~61 resultado[15] } "NODE_NAME" } } } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X13_Y0 X26_Y13 " "Info: Peak interconnect usage is 2% of the available device resources in the region that extends from location X13_Y0 to location X26_Y13" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Info: Fitter routing operations ending: elapsed time is 00:00:02" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1} +{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} +{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "96 " "Warning: Found 96 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[0\] 0 " "Info: Pin \"fxx_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[1\] 0 " "Info: Pin \"fxx_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[2\] 0 " "Info: Pin \"fxx_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[3\] 0 " "Info: Pin \"fxx_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[4\] 0 " "Info: Pin \"fxx_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[5\] 0 " "Info: Pin \"fxx_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[6\] 0 " "Info: Pin \"fxx_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[7\] 0 " "Info: Pin \"fxx_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[8\] 0 " "Info: Pin \"fxx_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[9\] 0 " "Info: Pin \"fxx_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[10\] 0 " "Info: Pin \"fxx_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[11\] 0 " "Info: Pin \"fxx_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[12\] 0 " "Info: Pin \"fxx_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[13\] 0 " "Info: Pin \"fxx_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[14\] 0 " "Info: Pin \"fxx_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[15\] 0 " "Info: Pin \"fxx_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[0\] 0 " "Info: Pin \"fxx1_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[1\] 0 " "Info: Pin \"fxx1_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[2\] 0 " "Info: Pin \"fxx1_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[3\] 0 " "Info: Pin \"fxx1_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[4\] 0 " "Info: Pin \"fxx1_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[5\] 0 " "Info: Pin \"fxx1_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[6\] 0 " "Info: Pin \"fxx1_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[7\] 0 " "Info: Pin \"fxx1_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[8\] 0 " "Info: Pin \"fxx1_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[9\] 0 " "Info: Pin \"fxx1_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[10\] 0 " "Info: Pin \"fxx1_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[11\] 0 " "Info: Pin \"fxx1_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[12\] 0 " "Info: Pin \"fxx1_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[13\] 0 " "Info: Pin \"fxx1_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[14\] 0 " "Info: Pin \"fxx1_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[15\] 0 " "Info: Pin \"fxx1_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[0\] 0 " "Info: Pin \"fxx2_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[1\] 0 " "Info: Pin \"fxx2_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[2\] 0 " "Info: Pin \"fxx2_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[3\] 0 " "Info: Pin \"fxx2_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[4\] 0 " "Info: Pin \"fxx2_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[5\] 0 " "Info: Pin \"fxx2_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[6\] 0 " "Info: Pin \"fxx2_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[7\] 0 " "Info: Pin \"fxx2_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[8\] 0 " "Info: Pin \"fxx2_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[9\] 0 " "Info: Pin \"fxx2_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[10\] 0 " "Info: Pin \"fxx2_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[11\] 0 " "Info: Pin \"fxx2_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[12\] 0 " "Info: Pin \"fxx2_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[13\] 0 " "Info: Pin \"fxx2_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[14\] 0 " "Info: Pin \"fxx2_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[15\] 0 " "Info: Pin \"fxx2_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[0\] 0 " "Info: Pin \"fxx3_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[1\] 0 " "Info: Pin \"fxx3_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[2\] 0 " "Info: Pin \"fxx3_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[3\] 0 " "Info: Pin \"fxx3_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[4\] 0 " "Info: Pin \"fxx3_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[5\] 0 " "Info: Pin \"fxx3_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[6\] 0 " "Info: Pin \"fxx3_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[7\] 0 " "Info: Pin \"fxx3_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[8\] 0 " "Info: Pin \"fxx3_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[9\] 0 " "Info: Pin \"fxx3_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[10\] 0 " "Info: Pin \"fxx3_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[11\] 0 " "Info: Pin \"fxx3_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[12\] 0 " "Info: Pin \"fxx3_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[13\] 0 " "Info: Pin \"fxx3_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[14\] 0 " "Info: Pin \"fxx3_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[15\] 0 " "Info: Pin \"fxx3_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[0\] 0 " "Info: Pin \"fxx4_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[1\] 0 " "Info: Pin \"fxx4_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[2\] 0 " "Info: Pin \"fxx4_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[3\] 0 " "Info: Pin \"fxx4_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[4\] 0 " "Info: Pin \"fxx4_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[5\] 0 " "Info: Pin \"fxx4_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[6\] 0 " "Info: Pin \"fxx4_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[7\] 0 " "Info: Pin \"fxx4_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[8\] 0 " "Info: Pin \"fxx4_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[9\] 0 " "Info: Pin \"fxx4_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[10\] 0 " "Info: Pin \"fxx4_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[11\] 0 " "Info: Pin \"fxx4_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[12\] 0 " "Info: Pin \"fxx4_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[13\] 0 " "Info: Pin \"fxx4_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[14\] 0 " "Info: Pin \"fxx4_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[15\] 0 " "Info: Pin \"fxx4_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[0\] 0 " "Info: Pin \"resul_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[1\] 0 " "Info: Pin \"resul_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[2\] 0 " "Info: Pin \"resul_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[3\] 0 " "Info: Pin \"resul_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[4\] 0 " "Info: Pin \"resul_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[5\] 0 " "Info: Pin \"resul_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[6\] 0 " "Info: Pin \"resul_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[7\] 0 " "Info: Pin \"resul_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[8\] 0 " "Info: Pin \"resul_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[9\] 0 " "Info: Pin \"resul_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[10\] 0 " "Info: Pin \"resul_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[11\] 0 " "Info: Pin \"resul_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[12\] 0 " "Info: Pin \"resul_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[13\] 0 " "Info: Pin \"resul_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[14\] 0 " "Info: Pin \"resul_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[15\] 0 " "Info: Pin \"resul_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1} +{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "233 " "Info: Peak virtual memory: 233 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 14 00:28:05 2012 " "Info: Processing ended: Tue Aug 14 00:28:05 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:27 " "Info: Elapsed time: 00:00:27" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:27 " "Info: Total CPU time (on all processors): 00:00:27" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} Index: trunk/QuartusII/db/gnextrapolator.tan.qmsg =================================================================== --- trunk/QuartusII/db/gnextrapolator.tan.qmsg (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.tan.qmsg (revision 5) @@ -0,0 +1,12 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 14 00:28:12 2012 " "Info: Processing started: Tue Aug 14 00:28:12 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolator --speed=4 " "Info: Command: quartus_tan --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolator --speed=4" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} +{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "96 " "Warning: Found 96 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[0\] 0 " "Info: Pin \"fxx_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[1\] 0 " "Info: Pin \"fxx_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[2\] 0 " "Info: Pin \"fxx_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[3\] 0 " "Info: Pin \"fxx_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[4\] 0 " "Info: Pin \"fxx_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[5\] 0 " "Info: Pin \"fxx_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[6\] 0 " "Info: Pin \"fxx_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[7\] 0 " "Info: Pin \"fxx_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[8\] 0 " "Info: Pin \"fxx_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[9\] 0 " "Info: Pin \"fxx_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[10\] 0 " "Info: Pin \"fxx_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[11\] 0 " "Info: Pin \"fxx_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[12\] 0 " "Info: Pin \"fxx_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[13\] 0 " "Info: Pin \"fxx_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[14\] 0 " "Info: Pin \"fxx_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[15\] 0 " "Info: Pin \"fxx_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[0\] 0 " "Info: Pin \"fxx1_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[1\] 0 " "Info: Pin \"fxx1_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[2\] 0 " "Info: Pin \"fxx1_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[3\] 0 " "Info: Pin \"fxx1_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[4\] 0 " "Info: Pin \"fxx1_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[5\] 0 " "Info: Pin \"fxx1_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[6\] 0 " "Info: Pin \"fxx1_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[7\] 0 " "Info: Pin \"fxx1_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[8\] 0 " "Info: Pin \"fxx1_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[9\] 0 " "Info: Pin \"fxx1_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[10\] 0 " "Info: Pin \"fxx1_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[11\] 0 " "Info: Pin \"fxx1_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[12\] 0 " "Info: Pin \"fxx1_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[13\] 0 " "Info: Pin \"fxx1_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[14\] 0 " "Info: Pin \"fxx1_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[15\] 0 " "Info: Pin \"fxx1_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[0\] 0 " "Info: Pin \"fxx2_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[1\] 0 " "Info: Pin \"fxx2_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[2\] 0 " "Info: Pin \"fxx2_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[3\] 0 " "Info: Pin \"fxx2_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[4\] 0 " "Info: Pin \"fxx2_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[5\] 0 " "Info: Pin \"fxx2_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[6\] 0 " "Info: Pin \"fxx2_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[7\] 0 " "Info: Pin \"fxx2_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[8\] 0 " "Info: Pin \"fxx2_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[9\] 0 " "Info: Pin \"fxx2_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[10\] 0 " "Info: Pin \"fxx2_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[11\] 0 " "Info: Pin \"fxx2_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[12\] 0 " "Info: Pin \"fxx2_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[13\] 0 " "Info: Pin \"fxx2_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[14\] 0 " "Info: Pin \"fxx2_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[15\] 0 " "Info: Pin \"fxx2_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[0\] 0 " "Info: Pin \"fxx3_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[1\] 0 " "Info: Pin \"fxx3_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[2\] 0 " "Info: Pin \"fxx3_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[3\] 0 " "Info: Pin \"fxx3_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[4\] 0 " "Info: Pin \"fxx3_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[5\] 0 " "Info: Pin \"fxx3_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[6\] 0 " "Info: Pin \"fxx3_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[7\] 0 " "Info: Pin \"fxx3_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[8\] 0 " "Info: Pin \"fxx3_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[9\] 0 " "Info: Pin \"fxx3_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[10\] 0 " "Info: Pin \"fxx3_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[11\] 0 " "Info: Pin \"fxx3_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[12\] 0 " "Info: Pin \"fxx3_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[13\] 0 " "Info: Pin \"fxx3_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[14\] 0 " "Info: Pin \"fxx3_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[15\] 0 " "Info: Pin \"fxx3_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[0\] 0 " "Info: Pin \"fxx4_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[1\] 0 " "Info: Pin \"fxx4_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[2\] 0 " "Info: Pin \"fxx4_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[3\] 0 " "Info: Pin \"fxx4_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[4\] 0 " "Info: Pin \"fxx4_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[5\] 0 " "Info: Pin \"fxx4_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[6\] 0 " "Info: Pin \"fxx4_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[7\] 0 " "Info: Pin \"fxx4_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[8\] 0 " "Info: Pin \"fxx4_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[9\] 0 " "Info: Pin \"fxx4_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[10\] 0 " "Info: Pin \"fxx4_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[11\] 0 " "Info: Pin \"fxx4_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[12\] 0 " "Info: Pin \"fxx4_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[13\] 0 " "Info: Pin \"fxx4_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[14\] 0 " "Info: Pin \"fxx4_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[15\] 0 " "Info: Pin \"fxx4_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[0\] 0 " "Info: Pin \"resul_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[1\] 0 " "Info: Pin \"resul_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[2\] 0 " "Info: Pin \"resul_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[3\] 0 " "Info: Pin \"resul_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[4\] 0 " "Info: Pin \"resul_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[5\] 0 " "Info: Pin \"resul_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[6\] 0 " "Info: Pin \"resul_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[7\] 0 " "Info: Pin \"resul_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[8\] 0 " "Info: Pin \"resul_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[9\] 0 " "Info: Pin \"resul_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[10\] 0 " "Info: Pin \"resul_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[11\] 0 " "Info: Pin \"resul_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[12\] 0 " "Info: Pin \"resul_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[13\] 0 " "Info: Pin \"resul_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[14\] 0 " "Info: Pin \"resul_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[15\] 0 " "Info: Pin \"resul_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1} +{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1} +{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_i " "Info: Assuming node \"clk_i\" is an undefined clock" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } { "c:/altera/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_i" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_i memory altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a0~porta_address_reg0 register resultado\[15\] 46.88 MHz 21.332 ns Internal " "Info: Clock \"clk_i\" has Internal fmax of 46.88 MHz between source memory \"altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a0~porta_address_reg0\" and destination register \"resultado\[15\]\" (period= 21.332 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.577 ns + Longest memory register " "Info: + Longest memory to register delay is 10.577 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a0~porta_address_reg0 1 MEM M512_X24_Y8 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M512_X24_Y8; Fanout = 16; MEM Node = 'altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a0~porta_address_reg0'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_uv61.tdf" "" { Text "C:/Altera/qdesigns/gnextrapolator/db/altsyncram_uv61.tdf" 34 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.061 ns) 2.061 ns altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a7 2 MEM M512_X24_Y8 6 " "Info: 2: + IC(0.000 ns) + CELL(2.061 ns) = 2.061 ns; Loc. = M512_X24_Y8; Fanout = 6; MEM Node = 'altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a7'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.061 ns" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7 } "NODE_NAME" } } { "db/altsyncram_uv61.tdf" "" { Text "C:/Altera/qdesigns/gnextrapolator/db/altsyncram_uv61.tdf" 174 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.866 ns) + CELL(0.060 ns) 2.987 ns fx~23 3 COMB LCCOMB_X27_Y5_N22 2 " "Info: 3: + IC(0.866 ns) + CELL(0.060 ns) = 2.987 ns; Loc. = LCCOMB_X27_Y5_N22; Fanout = 2; COMB Node = 'fx~23'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.926 ns" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7 fx~23 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 89 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.874 ns) + CELL(0.426 ns) 4.287 ns Add2~37 4 COMB LCCOMB_X23_Y8_N30 6 " "Info: 4: + IC(0.874 ns) + CELL(0.426 ns) = 4.287 ns; Loc. = LCCOMB_X23_Y8_N30; Fanout = 6; COMB Node = 'Add2~37'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.300 ns" { fx~23 Add2~37 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.671 ns) + CELL(0.426 ns) 5.384 ns Add3~33 5 COMB LCCOMB_X22_Y7_N0 7 " "Info: 5: + IC(0.671 ns) + CELL(0.426 ns) = 5.384 ns; Loc. = LCCOMB_X22_Y7_N0; Fanout = 7; COMB Node = 'Add3~33'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.097 ns" { Add2~37 Add3~33 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.674 ns) + CELL(0.570 ns) 6.628 ns Add4~38 6 COMB LCCOMB_X22_Y6_N30 2 " "Info: 6: + IC(0.674 ns) + CELL(0.570 ns) = 6.628 ns; Loc. = LCCOMB_X22_Y6_N30; Fanout = 2; COMB Node = 'Add4~38'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.244 ns" { Add3~33 Add4~38 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 6.669 ns Add4~42 7 COMB LCCOMB_X22_Y5_N0 2 " "Info: 7: + IC(0.000 ns) + CELL(0.041 ns) = 6.669 ns; Loc. = LCCOMB_X22_Y5_N0; Fanout = 2; COMB Node = 'Add4~42'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add4~38 Add4~42 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 6.710 ns Add4~46 8 COMB LCCOMB_X22_Y5_N2 2 " "Info: 8: + IC(0.000 ns) + CELL(0.041 ns) = 6.710 ns; Loc. = LCCOMB_X22_Y5_N2; Fanout = 2; COMB Node = 'Add4~46'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add4~42 Add4~46 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 6.751 ns Add4~50 9 COMB LCCOMB_X22_Y5_N4 2 " "Info: 9: + IC(0.000 ns) + CELL(0.041 ns) = 6.751 ns; Loc. = LCCOMB_X22_Y5_N4; Fanout = 2; COMB Node = 'Add4~50'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add4~46 Add4~50 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 6.895 ns Add4~53 10 COMB LCCOMB_X22_Y5_N6 7 " "Info: 10: + IC(0.000 ns) + CELL(0.144 ns) = 6.895 ns; Loc. = LCCOMB_X22_Y5_N6; Fanout = 7; COMB Node = 'Add4~53'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add4~50 Add4~53 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.677 ns) + CELL(0.502 ns) 8.074 ns Add8~46 11 COMB LCCOMB_X25_Y5_N6 2 " "Info: 11: + IC(0.677 ns) + CELL(0.502 ns) = 8.074 ns; Loc. = LCCOMB_X25_Y5_N6; Fanout = 2; COMB Node = 'Add8~46'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.179 ns" { Add4~53 Add8~46 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 8.115 ns Add8~50 12 COMB LCCOMB_X25_Y5_N8 2 " "Info: 12: + IC(0.000 ns) + CELL(0.041 ns) = 8.115 ns; Loc. = LCCOMB_X25_Y5_N8; Fanout = 2; COMB Node = 'Add8~50'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add8~46 Add8~50 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 8.156 ns Add8~54 13 COMB LCCOMB_X25_Y5_N10 2 " "Info: 13: + IC(0.000 ns) + CELL(0.041 ns) = 8.156 ns; Loc. = LCCOMB_X25_Y5_N10; Fanout = 2; COMB Node = 'Add8~54'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add8~50 Add8~54 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 8.197 ns Add8~58 14 COMB LCCOMB_X25_Y5_N12 1 " "Info: 14: + IC(0.000 ns) + CELL(0.041 ns) = 8.197 ns; Loc. = LCCOMB_X25_Y5_N12; Fanout = 1; COMB Node = 'Add8~58'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add8~54 Add8~58 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 8.341 ns Add8~61 15 COMB LCCOMB_X25_Y5_N14 1 " "Info: 15: + IC(0.000 ns) + CELL(0.144 ns) = 8.341 ns; Loc. = LCCOMB_X25_Y5_N14; Fanout = 1; COMB Node = 'Add8~61'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add8~58 Add8~61 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.553 ns) + CELL(0.426 ns) 9.320 ns Add9~61 16 COMB LCCOMB_X26_Y5_N30 2 " "Info: 16: + IC(0.553 ns) + CELL(0.426 ns) = 9.320 ns; Loc. = LCCOMB_X26_Y5_N30; Fanout = 2; COMB Node = 'Add9~61'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.979 ns" { Add8~61 Add9~61 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.902 ns) + CELL(0.355 ns) 10.577 ns resultado\[15\] 17 REG LCFF_X23_Y7_N3 4 " "Info: 17: + IC(0.902 ns) + CELL(0.355 ns) = 10.577 ns; Loc. = LCFF_X23_Y7_N3; Fanout = 4; REG Node = 'resultado\[15\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.257 ns" { Add9~61 resultado[15] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.360 ns ( 50.68 % ) " "Info: Total cell delay = 5.360 ns ( 50.68 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.217 ns ( 49.32 % ) " "Info: Total interconnect delay = 5.217 ns ( 49.32 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "10.577 ns" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7 fx~23 Add2~37 Add3~33 Add4~38 Add4~42 Add4~46 Add4~50 Add4~53 Add8~46 Add8~50 Add8~54 Add8~58 Add8~61 Add9~61 resultado[15] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "10.577 ns" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 {} altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7 {} fx~23 {} Add2~37 {} Add3~33 {} Add4~38 {} Add4~42 {} Add4~46 {} Add4~50 {} Add4~53 {} Add8~46 {} Add8~50 {} Add8~54 {} Add8~58 {} Add8~61 {} Add9~61 {} resultado[15] {} } { 0.000ns 0.000ns 0.866ns 0.874ns 0.671ns 0.674ns 0.000ns 0.000ns 0.000ns 0.000ns 0.677ns 0.000ns 0.000ns 0.000ns 0.000ns 0.553ns 0.902ns } { 0.000ns 2.061ns 0.060ns 0.426ns 0.426ns 0.570ns 0.041ns 0.041ns 0.041ns 0.144ns 0.502ns 0.041ns 0.041ns 0.041ns 0.144ns 0.426ns 0.355ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.176 ns - Smallest " "Info: - Smallest clock skew is 0.176 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i destination 2.830 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_i\" to destination register is 2.830 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.000 ns) 1.368 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 195 " "Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 195; COMB Node = 'clk_i~clkctrl'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.394 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.752 ns) + CELL(0.710 ns) 2.830 ns resultado\[15\] 3 REG LCFF_X23_Y7_N3 4 " "Info: 3: + IC(0.752 ns) + CELL(0.710 ns) = 2.830 ns; Loc. = LCFF_X23_Y7_N3; Fanout = 4; REG Node = 'resultado\[15\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.462 ns" { clk_i~clkctrl resultado[15] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.684 ns ( 59.51 % ) " "Info: Total cell delay = 1.684 ns ( 59.51 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.146 ns ( 40.49 % ) " "Info: Total interconnect delay = 1.146 ns ( 40.49 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.830 ns" { clk_i clk_i~clkctrl resultado[15] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.830 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[15] {} } { 0.000ns 0.000ns 0.394ns 0.752ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i source 2.654 ns - Longest memory " "Info: - Longest clock path from clock \"clk_i\" to source memory is 2.654 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.000 ns) 1.368 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 195 " "Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 195; COMB Node = 'clk_i~clkctrl'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.394 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.760 ns) + CELL(0.526 ns) 2.654 ns altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a0~porta_address_reg0 3 MEM M512_X24_Y8 16 " "Info: 3: + IC(0.760 ns) + CELL(0.526 ns) = 2.654 ns; Loc. = M512_X24_Y8; Fanout = 16; MEM Node = 'altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a0~porta_address_reg0'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.286 ns" { clk_i~clkctrl altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_uv61.tdf" "" { Text "C:/Altera/qdesigns/gnextrapolator/db/altsyncram_uv61.tdf" 34 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.500 ns ( 56.52 % ) " "Info: Total cell delay = 1.500 ns ( 56.52 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.154 ns ( 43.48 % ) " "Info: Total interconnect delay = 1.154 ns ( 43.48 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.654 ns" { clk_i clk_i~clkctrl altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.654 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 {} } { 0.000ns 0.000ns 0.394ns 0.760ns } { 0.000ns 0.974ns 0.000ns 0.526ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.830 ns" { clk_i clk_i~clkctrl resultado[15] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.830 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[15] {} } { 0.000ns 0.000ns 0.394ns 0.752ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.654 ns" { clk_i clk_i~clkctrl altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.654 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 {} } { 0.000ns 0.000ns 0.394ns 0.760ns } { 0.000ns 0.974ns 0.000ns 0.526ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.161 ns + " "Info: + Micro clock to output delay of source is 0.161 ns" { } { { "db/altsyncram_uv61.tdf" "" { Text "C:/Altera/qdesigns/gnextrapolator/db/altsyncram_uv61.tdf" 34 2 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.104 ns + " "Info: + Micro setup delay of destination is 0.104 ns" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" { } { { "db/altsyncram_uv61.tdf" "" { Text "C:/Altera/qdesigns/gnextrapolator/db/altsyncram_uv61.tdf" 34 2 0 } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "10.577 ns" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7 fx~23 Add2~37 Add3~33 Add4~38 Add4~42 Add4~46 Add4~50 Add4~53 Add8~46 Add8~50 Add8~54 Add8~58 Add8~61 Add9~61 resultado[15] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "10.577 ns" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 {} altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7 {} fx~23 {} Add2~37 {} Add3~33 {} Add4~38 {} Add4~42 {} Add4~46 {} Add4~50 {} Add4~53 {} Add8~46 {} Add8~50 {} Add8~54 {} Add8~58 {} Add8~61 {} Add9~61 {} resultado[15] {} } { 0.000ns 0.000ns 0.866ns 0.874ns 0.671ns 0.674ns 0.000ns 0.000ns 0.000ns 0.000ns 0.677ns 0.000ns 0.000ns 0.000ns 0.000ns 0.553ns 0.902ns } { 0.000ns 2.061ns 0.060ns 0.426ns 0.426ns 0.570ns 0.041ns 0.041ns 0.041ns 0.144ns 0.502ns 0.041ns 0.041ns 0.041ns 0.144ns 0.426ns 0.355ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.830 ns" { clk_i clk_i~clkctrl resultado[15] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.830 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[15] {} } { 0.000ns 0.000ns 0.394ns 0.752ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.654 ns" { clk_i clk_i~clkctrl altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.654 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 {} } { 0.000ns 0.000ns 0.394ns 0.760ns } { 0.000ns 0.974ns 0.000ns 0.526ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1} +{ "Info" "ITDB_TSU_RESULT" "resultado\[15\] extrapolar_i clk_i 12.402 ns register " "Info: tsu for register \"resultado\[15\]\" (data pin = \"extrapolar_i\", clock pin = \"clk_i\") is 12.402 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "15.128 ns + Longest pin register " "Info: + Longest pin to register delay is 15.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.920 ns) 0.920 ns extrapolar_i 1 PIN PIN_B9 96 " "Info: 1: + IC(0.000 ns) + CELL(0.920 ns) = 0.920 ns; Loc. = PIN_B9; Fanout = 96; PIN Node = 'extrapolar_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { extrapolar_i } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 54 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(6.261 ns) + CELL(0.435 ns) 7.616 ns fx~22 2 COMB LCCOMB_X23_Y5_N24 2 " "Info: 2: + IC(6.261 ns) + CELL(0.435 ns) = 7.616 ns; Loc. = LCCOMB_X23_Y5_N24; Fanout = 2; COMB Node = 'fx~22'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "6.696 ns" { extrapolar_i fx~22 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 89 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.675 ns) + CELL(0.403 ns) 8.694 ns Add2~34 3 COMB LCCOMB_X23_Y8_N28 2 " "Info: 3: + IC(0.675 ns) + CELL(0.403 ns) = 8.694 ns; Loc. = LCCOMB_X23_Y8_N28; Fanout = 2; COMB Node = 'Add2~34'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.078 ns" { fx~22 Add2~34 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 8.838 ns Add2~37 4 COMB LCCOMB_X23_Y8_N30 6 " "Info: 4: + IC(0.000 ns) + CELL(0.144 ns) = 8.838 ns; Loc. = LCCOMB_X23_Y8_N30; Fanout = 6; COMB Node = 'Add2~37'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add2~34 Add2~37 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.671 ns) + CELL(0.426 ns) 9.935 ns Add3~33 5 COMB LCCOMB_X22_Y7_N0 7 " "Info: 5: + IC(0.671 ns) + CELL(0.426 ns) = 9.935 ns; Loc. = LCCOMB_X22_Y7_N0; Fanout = 7; COMB Node = 'Add3~33'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.097 ns" { Add2~37 Add3~33 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.674 ns) + CELL(0.570 ns) 11.179 ns Add4~38 6 COMB LCCOMB_X22_Y6_N30 2 " "Info: 6: + IC(0.674 ns) + CELL(0.570 ns) = 11.179 ns; Loc. = LCCOMB_X22_Y6_N30; Fanout = 2; COMB Node = 'Add4~38'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.244 ns" { Add3~33 Add4~38 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 11.220 ns Add4~42 7 COMB LCCOMB_X22_Y5_N0 2 " "Info: 7: + IC(0.000 ns) + CELL(0.041 ns) = 11.220 ns; Loc. = LCCOMB_X22_Y5_N0; Fanout = 2; COMB Node = 'Add4~42'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add4~38 Add4~42 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 11.261 ns Add4~46 8 COMB LCCOMB_X22_Y5_N2 2 " "Info: 8: + IC(0.000 ns) + CELL(0.041 ns) = 11.261 ns; Loc. = LCCOMB_X22_Y5_N2; Fanout = 2; COMB Node = 'Add4~46'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add4~42 Add4~46 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 11.302 ns Add4~50 9 COMB LCCOMB_X22_Y5_N4 2 " "Info: 9: + IC(0.000 ns) + CELL(0.041 ns) = 11.302 ns; Loc. = LCCOMB_X22_Y5_N4; Fanout = 2; COMB Node = 'Add4~50'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add4~46 Add4~50 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 11.446 ns Add4~53 10 COMB LCCOMB_X22_Y5_N6 7 " "Info: 10: + IC(0.000 ns) + CELL(0.144 ns) = 11.446 ns; Loc. = LCCOMB_X22_Y5_N6; Fanout = 7; COMB Node = 'Add4~53'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add4~50 Add4~53 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.677 ns) + CELL(0.502 ns) 12.625 ns Add8~46 11 COMB LCCOMB_X25_Y5_N6 2 " "Info: 11: + IC(0.677 ns) + CELL(0.502 ns) = 12.625 ns; Loc. = LCCOMB_X25_Y5_N6; Fanout = 2; COMB Node = 'Add8~46'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.179 ns" { Add4~53 Add8~46 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 12.666 ns Add8~50 12 COMB LCCOMB_X25_Y5_N8 2 " "Info: 12: + IC(0.000 ns) + CELL(0.041 ns) = 12.666 ns; Loc. = LCCOMB_X25_Y5_N8; Fanout = 2; COMB Node = 'Add8~50'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add8~46 Add8~50 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 12.707 ns Add8~54 13 COMB LCCOMB_X25_Y5_N10 2 " "Info: 13: + IC(0.000 ns) + CELL(0.041 ns) = 12.707 ns; Loc. = LCCOMB_X25_Y5_N10; Fanout = 2; COMB Node = 'Add8~54'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add8~50 Add8~54 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 12.748 ns Add8~58 14 COMB LCCOMB_X25_Y5_N12 1 " "Info: 14: + IC(0.000 ns) + CELL(0.041 ns) = 12.748 ns; Loc. = LCCOMB_X25_Y5_N12; Fanout = 1; COMB Node = 'Add8~58'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add8~54 Add8~58 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 12.892 ns Add8~61 15 COMB LCCOMB_X25_Y5_N14 1 " "Info: 15: + IC(0.000 ns) + CELL(0.144 ns) = 12.892 ns; Loc. = LCCOMB_X25_Y5_N14; Fanout = 1; COMB Node = 'Add8~61'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add8~58 Add8~61 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.553 ns) + CELL(0.426 ns) 13.871 ns Add9~61 16 COMB LCCOMB_X26_Y5_N30 2 " "Info: 16: + IC(0.553 ns) + CELL(0.426 ns) = 13.871 ns; Loc. = LCCOMB_X26_Y5_N30; Fanout = 2; COMB Node = 'Add9~61'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.979 ns" { Add8~61 Add9~61 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.902 ns) + CELL(0.355 ns) 15.128 ns resultado\[15\] 17 REG LCFF_X23_Y7_N3 4 " "Info: 17: + IC(0.902 ns) + CELL(0.355 ns) = 15.128 ns; Loc. = LCFF_X23_Y7_N3; Fanout = 4; REG Node = 'resultado\[15\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.257 ns" { Add9~61 resultado[15] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.715 ns ( 31.17 % ) " "Info: Total cell delay = 4.715 ns ( 31.17 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "10.413 ns ( 68.83 % ) " "Info: Total interconnect delay = 10.413 ns ( 68.83 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "15.128 ns" { extrapolar_i fx~22 Add2~34 Add2~37 Add3~33 Add4~38 Add4~42 Add4~46 Add4~50 Add4~53 Add8~46 Add8~50 Add8~54 Add8~58 Add8~61 Add9~61 resultado[15] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "15.128 ns" { extrapolar_i {} extrapolar_i~combout {} fx~22 {} Add2~34 {} Add2~37 {} Add3~33 {} Add4~38 {} Add4~42 {} Add4~46 {} Add4~50 {} Add4~53 {} Add8~46 {} Add8~50 {} Add8~54 {} Add8~58 {} Add8~61 {} Add9~61 {} resultado[15] {} } { 0.000ns 0.000ns 6.261ns 0.675ns 0.000ns 0.671ns 0.674ns 0.000ns 0.000ns 0.000ns 0.000ns 0.677ns 0.000ns 0.000ns 0.000ns 0.000ns 0.553ns 0.902ns } { 0.000ns 0.920ns 0.435ns 0.403ns 0.144ns 0.426ns 0.570ns 0.041ns 0.041ns 0.041ns 0.144ns 0.502ns 0.041ns 0.041ns 0.041ns 0.144ns 0.426ns 0.355ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.104 ns + " "Info: + Micro setup delay of destination is 0.104 ns" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i destination 2.830 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_i\" to destination register is 2.830 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.000 ns) 1.368 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 195 " "Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 195; COMB Node = 'clk_i~clkctrl'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.394 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.752 ns) + CELL(0.710 ns) 2.830 ns resultado\[15\] 3 REG LCFF_X23_Y7_N3 4 " "Info: 3: + IC(0.752 ns) + CELL(0.710 ns) = 2.830 ns; Loc. = LCFF_X23_Y7_N3; Fanout = 4; REG Node = 'resultado\[15\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.462 ns" { clk_i~clkctrl resultado[15] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.684 ns ( 59.51 % ) " "Info: Total cell delay = 1.684 ns ( 59.51 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.146 ns ( 40.49 % ) " "Info: Total interconnect delay = 1.146 ns ( 40.49 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.830 ns" { clk_i clk_i~clkctrl resultado[15] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.830 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[15] {} } { 0.000ns 0.000ns 0.394ns 0.752ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "15.128 ns" { extrapolar_i fx~22 Add2~34 Add2~37 Add3~33 Add4~38 Add4~42 Add4~46 Add4~50 Add4~53 Add8~46 Add8~50 Add8~54 Add8~58 Add8~61 Add9~61 resultado[15] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "15.128 ns" { extrapolar_i {} extrapolar_i~combout {} fx~22 {} Add2~34 {} Add2~37 {} Add3~33 {} Add4~38 {} Add4~42 {} Add4~46 {} Add4~50 {} Add4~53 {} Add8~46 {} Add8~50 {} Add8~54 {} Add8~58 {} Add8~61 {} Add9~61 {} resultado[15] {} } { 0.000ns 0.000ns 6.261ns 0.675ns 0.000ns 0.671ns 0.674ns 0.000ns 0.000ns 0.000ns 0.000ns 0.677ns 0.000ns 0.000ns 0.000ns 0.000ns 0.553ns 0.902ns } { 0.000ns 0.920ns 0.435ns 0.403ns 0.144ns 0.426ns 0.570ns 0.041ns 0.041ns 0.041ns 0.144ns 0.502ns 0.041ns 0.041ns 0.041ns 0.144ns 0.426ns 0.355ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.830 ns" { clk_i clk_i~clkctrl resultado[15] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.830 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[15] {} } { 0.000ns 0.000ns 0.394ns 0.752ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_TCO_RESULT" "clk_i fxx3_o\[14\] fxx3_o\[14\]~reg0 8.310 ns register " "Info: tco from clock \"clk_i\" to destination pin \"fxx3_o\[14\]\" through register \"fxx3_o\[14\]~reg0\" is 8.310 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i source 2.842 ns + Longest register " "Info: + Longest clock path from clock \"clk_i\" to source register is 2.842 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.000 ns) 1.368 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 195 " "Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 195; COMB Node = 'clk_i~clkctrl'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.394 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.764 ns) + CELL(0.710 ns) 2.842 ns fxx3_o\[14\]~reg0 3 REG LCFF_X22_Y5_N13 1 " "Info: 3: + IC(0.764 ns) + CELL(0.710 ns) = 2.842 ns; Loc. = LCFF_X22_Y5_N13; Fanout = 1; REG Node = 'fxx3_o\[14\]~reg0'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.474 ns" { clk_i~clkctrl fxx3_o[14]~reg0 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.684 ns ( 59.25 % ) " "Info: Total cell delay = 1.684 ns ( 59.25 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.158 ns ( 40.75 % ) " "Info: Total interconnect delay = 1.158 ns ( 40.75 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.842 ns" { clk_i clk_i~clkctrl fxx3_o[14]~reg0 } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.842 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} fxx3_o[14]~reg0 {} } { 0.000ns 0.000ns 0.394ns 0.764ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.109 ns + " "Info: + Micro clock to output delay of source is 0.109 ns" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.359 ns + Longest register pin " "Info: + Longest register to pin delay is 5.359 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns fxx3_o\[14\]~reg0 1 REG LCFF_X22_Y5_N13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y5_N13; Fanout = 1; REG Node = 'fxx3_o\[14\]~reg0'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[14]~reg0 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.924 ns) + CELL(2.435 ns) 5.359 ns fxx3_o\[14\] 2 PIN PIN_J5 0 " "Info: 2: + IC(2.924 ns) + CELL(2.435 ns) = 5.359 ns; Loc. = PIN_J5; Fanout = 0; PIN Node = 'fxx3_o\[14\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.359 ns" { fxx3_o[14]~reg0 fxx3_o[14] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.435 ns ( 45.44 % ) " "Info: Total cell delay = 2.435 ns ( 45.44 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.924 ns ( 54.56 % ) " "Info: Total interconnect delay = 2.924 ns ( 54.56 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.359 ns" { fxx3_o[14]~reg0 fxx3_o[14] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "5.359 ns" { fxx3_o[14]~reg0 {} fxx3_o[14] {} } { 0.000ns 2.924ns } { 0.000ns 2.435ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.842 ns" { clk_i clk_i~clkctrl fxx3_o[14]~reg0 } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.842 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} fxx3_o[14]~reg0 {} } { 0.000ns 0.000ns 0.394ns 0.764ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "5.359 ns" { fxx3_o[14]~reg0 fxx3_o[14] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "5.359 ns" { fxx3_o[14]~reg0 {} fxx3_o[14] {} } { 0.000ns 2.924ns } { 0.000ns 2.435ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1} +{ "Info" "ITDB_TH_RESULT" "resultado\[15\] rst_i clk_i -1.094 ns register " "Info: th for register \"resultado\[15\]\" (data pin = \"rst_i\", clock pin = \"clk_i\") is -1.094 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_i destination 2.830 ns + Longest register " "Info: + Longest clock path from clock \"clk_i\" to destination register is 2.830 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.974 ns) 0.974 ns clk_i 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.394 ns) + CELL(0.000 ns) 1.368 ns clk_i~clkctrl 2 COMB CLKCTRL_G3 195 " "Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 195; COMB Node = 'clk_i~clkctrl'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.394 ns" { clk_i clk_i~clkctrl } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.752 ns) + CELL(0.710 ns) 2.830 ns resultado\[15\] 3 REG LCFF_X23_Y7_N3 4 " "Info: 3: + IC(0.752 ns) + CELL(0.710 ns) = 2.830 ns; Loc. = LCFF_X23_Y7_N3; Fanout = 4; REG Node = 'resultado\[15\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.462 ns" { clk_i~clkctrl resultado[15] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.684 ns ( 59.51 % ) " "Info: Total cell delay = 1.684 ns ( 59.51 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.146 ns ( 40.49 % ) " "Info: Total interconnect delay = 1.146 ns ( 40.49 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.830 ns" { clk_i clk_i~clkctrl resultado[15] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.830 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[15] {} } { 0.000ns 0.000ns 0.394ns 0.752ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.172 ns + " "Info: + Micro hold delay of destination is 0.172 ns" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.096 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.096 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns rst_i 1 PIN PIN_M21 98 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_M21; Fanout = 98; PIN Node = 'rst_i'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst_i } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 51 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.254 ns) + CELL(0.858 ns) 4.096 ns resultado\[15\] 2 REG LCFF_X23_Y7_N3 4 " "Info: 2: + IC(2.254 ns) + CELL(0.858 ns) = 4.096 ns; Loc. = LCFF_X23_Y7_N3; Fanout = 4; REG Node = 'resultado\[15\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "3.112 ns" { rst_i resultado[15] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.842 ns ( 44.97 % ) " "Info: Total cell delay = 1.842 ns ( 44.97 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "2.254 ns ( 55.03 % ) " "Info: Total interconnect delay = 2.254 ns ( 55.03 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.096 ns" { rst_i resultado[15] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "4.096 ns" { rst_i {} rst_i~combout {} resultado[15] {} } { 0.000ns 0.000ns 2.254ns } { 0.000ns 0.984ns 0.858ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.830 ns" { clk_i clk_i~clkctrl resultado[15] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "2.830 ns" { clk_i {} clk_i~combout {} clk_i~clkctrl {} resultado[15] {} } { 0.000ns 0.000ns 0.394ns 0.752ns } { 0.000ns 0.974ns 0.000ns 0.710ns } "" } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "4.096 ns" { rst_i resultado[15] } "NODE_NAME" } } { "c:/altera/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/quartus/bin/Technology_Viewer.qrui" "4.096 ns" { rst_i {} rst_i~combout {} resultado[15] {} } { 0.000ns 0.000ns 2.254ns } { 0.000ns 0.984ns 0.858ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "153 " "Info: Peak virtual memory: 153 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 14 00:28:18 2012 " "Info: Processing ended: Tue Aug 14 00:28:18 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:06 " "Info: Total CPU time (on all processors): 00:00:06" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} Index: trunk/QuartusII/db/gnextrapolator.sgdiff.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.sgdiff.cdb =================================================================== --- trunk/QuartusII/db/gnextrapolator.sgdiff.cdb (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.sgdiff.cdb (revision 5)
trunk/QuartusII/db/gnextrapolator.sgdiff.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.cmp2.ddb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.cmp2.ddb =================================================================== --- trunk/QuartusII/db/gnextrapolator.cmp2.ddb (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.cmp2.ddb (revision 5)
trunk/QuartusII/db/gnextrapolator.cmp2.ddb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.cmp_merge.kpt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.cmp_merge.kpt =================================================================== --- trunk/QuartusII/db/gnextrapolator.cmp_merge.kpt (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.cmp_merge.kpt (revision 5)
trunk/QuartusII/db/gnextrapolator.cmp_merge.kpt Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.syn_hier_info =================================================================== Index: trunk/QuartusII/db/gnextrapolator.eco.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.eco.cdb =================================================================== --- trunk/QuartusII/db/gnextrapolator.eco.cdb (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.eco.cdb (revision 5)
trunk/QuartusII/db/gnextrapolator.eco.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.sgdiff.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.sgdiff.hdb =================================================================== --- trunk/QuartusII/db/gnextrapolator.sgdiff.hdb (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.sgdiff.hdb (revision 5)
trunk/QuartusII/db/gnextrapolator.sgdiff.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.db_info =================================================================== --- trunk/QuartusII/db/gnextrapolator.db_info (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.db_info (revision 5) @@ -0,0 +1,3 @@ +Quartus_Version = Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition +Version_Index = 184638978 +Creation_Time = Mon Aug 13 23:38:03 2012 Index: trunk/QuartusII/db/gnextrapolator.rtlv_sg_swap.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.rtlv_sg_swap.cdb =================================================================== --- trunk/QuartusII/db/gnextrapolator.rtlv_sg_swap.cdb (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.rtlv_sg_swap.cdb (revision 5)
trunk/QuartusII/db/gnextrapolator.rtlv_sg_swap.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.hier_info =================================================================== --- trunk/QuartusII/db/gnextrapolator.hier_info (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.hier_info (revision 5) @@ -0,0 +1,1001 @@ +|gnextrapolator +rst_i => indice[0].ACLR +rst_i => indice[1].ACLR +rst_i => indice[2].ACLR +rst_i => indice[3].ACLR +rst_i => indice[4].ACLR +rst_i => nabla4fx[0][0].ACLR +rst_i => nabla4fx[0][1].ACLR +rst_i => nabla4fx[0][2].ACLR +rst_i => nabla4fx[0][3].ACLR +rst_i => nabla4fx[0][4].ACLR +rst_i => nabla4fx[0][5].ACLR +rst_i => nabla4fx[0][6].ACLR +rst_i => nabla4fx[0][7].ACLR +rst_i => nabla4fx[0][8].ACLR +rst_i => nabla4fx[0][9].ACLR +rst_i => nabla4fx[0][10].ACLR +rst_i => nabla4fx[0][11].ACLR +rst_i => nabla4fx[0][12].ACLR +rst_i => nabla4fx[0][13].ACLR +rst_i => nabla4fx[0][14].ACLR +rst_i => nabla4fx[0][15].ACLR +rst_i => nabla3fx[0][0].ACLR +rst_i => nabla3fx[0][1].ACLR +rst_i => nabla3fx[0][2].ACLR +rst_i => nabla3fx[0][3].ACLR +rst_i => nabla3fx[0][4].ACLR +rst_i => nabla3fx[0][5].ACLR +rst_i => nabla3fx[0][6].ACLR +rst_i => nabla3fx[0][7].ACLR +rst_i => nabla3fx[0][8].ACLR +rst_i => nabla3fx[0][9].ACLR +rst_i => nabla3fx[0][10].ACLR +rst_i => nabla3fx[0][11].ACLR +rst_i => nabla3fx[0][12].ACLR +rst_i => nabla3fx[0][13].ACLR +rst_i => nabla3fx[0][14].ACLR +rst_i => nabla3fx[0][15].ACLR +rst_i => nabla2fx[0][0].ACLR +rst_i => nabla2fx[0][1].ACLR +rst_i => nabla2fx[0][2].ACLR +rst_i => nabla2fx[0][3].ACLR +rst_i => nabla2fx[0][4].ACLR +rst_i => nabla2fx[0][5].ACLR +rst_i => nabla2fx[0][6].ACLR +rst_i => nabla2fx[0][7].ACLR +rst_i => nabla2fx[0][8].ACLR +rst_i => nabla2fx[0][9].ACLR +rst_i => nabla2fx[0][10].ACLR +rst_i => nabla2fx[0][11].ACLR +rst_i => nabla2fx[0][12].ACLR +rst_i => nabla2fx[0][13].ACLR +rst_i => nabla2fx[0][14].ACLR +rst_i => nabla2fx[0][15].ACLR +rst_i => nabla1fx[0][0].ACLR +rst_i => nabla1fx[0][1].ACLR +rst_i => nabla1fx[0][2].ACLR +rst_i => nabla1fx[0][3].ACLR +rst_i => nabla1fx[0][4].ACLR +rst_i => nabla1fx[0][5].ACLR +rst_i => nabla1fx[0][6].ACLR +rst_i => nabla1fx[0][7].ACLR +rst_i => nabla1fx[0][8].ACLR +rst_i => nabla1fx[0][9].ACLR +rst_i => nabla1fx[0][10].ACLR +rst_i => nabla1fx[0][11].ACLR +rst_i => nabla1fx[0][12].ACLR +rst_i => nabla1fx[0][13].ACLR +rst_i => nabla1fx[0][14].ACLR +rst_i => nabla1fx[0][15].ACLR +rst_i => fx[0][0].ACLR +rst_i => fx[0][1].ACLR +rst_i => fx[0][2].ACLR +rst_i => fx[0][3].ACLR +rst_i => fx[0][4].ACLR +rst_i => fx[0][5].ACLR +rst_i => fx[0][6].ACLR +rst_i => fx[0][7].ACLR +rst_i => fx[0][8].ACLR +rst_i => fx[0][9].ACLR +rst_i => fx[0][10].ACLR +rst_i => fx[0][11].ACLR +rst_i => fx[0][12].ACLR +rst_i => fx[0][13].ACLR +rst_i => fx[0][14].ACLR +rst_i => fx[0][15].ACLR +rst_i => cont[0].ACLR +rst_i => cont[1].ACLR +rst_i => cont[2].ACLR +rst_i => cont[3].ACLR +rst_i => cont[4].ACLR +rst_i => cont[5].ACLR +rst_i => cont[6].ACLR +rst_i => cont[7].ACLR +rst_i => cont[8].ACLR +rst_i => cont[9].ACLR +rst_i => cont[10].ACLR +rst_i => cont[11].ACLR +rst_i => cont[12].ACLR +rst_i => cont[13].ACLR +rst_i => cont[14].ACLR +rst_i => cont[15].ACLR +rst_i => i[0].ACLR +rst_i => i[1].ACLR +rst_i => fx[1][15].ENA +rst_i => fx[1][14].ENA +rst_i => fx[1][13].ENA +rst_i => fx[1][12].ENA +rst_i => fx[1][11].ENA +rst_i => fx[1][10].ENA +rst_i => fx[1][9].ENA +rst_i => fx[1][8].ENA +rst_i => fx[1][7].ENA +rst_i => fx[1][6].ENA +rst_i => fx[1][5].ENA +rst_i => fx[1][4].ENA +rst_i => fx[1][3].ENA +rst_i => fx[1][2].ENA +rst_i => fx[1][1].ENA +rst_i => fx[1][0].ENA +rst_i => fx[2][15].ENA +rst_i => fx[2][14].ENA +rst_i => fx[2][13].ENA +rst_i => fx[2][12].ENA +rst_i => fx[2][11].ENA +rst_i => fx[2][10].ENA +rst_i => fx[2][9].ENA +rst_i => fx[2][8].ENA +rst_i => fx[2][7].ENA +rst_i => fx[2][6].ENA +rst_i => fx[2][5].ENA +rst_i => fx[2][4].ENA +rst_i => fx[2][3].ENA +rst_i => fx[2][2].ENA +rst_i => fx[2][1].ENA +rst_i => fx[2][0].ENA +rst_i => nabla1fx[1][15].ENA +rst_i => nabla1fx[1][14].ENA +rst_i => nabla1fx[1][13].ENA +rst_i => nabla1fx[1][12].ENA +rst_i => nabla1fx[1][11].ENA +rst_i => nabla1fx[1][10].ENA +rst_i => nabla1fx[1][9].ENA +rst_i => nabla1fx[1][8].ENA +rst_i => nabla1fx[1][7].ENA +rst_i => nabla1fx[1][6].ENA +rst_i => nabla1fx[1][5].ENA +rst_i => nabla1fx[1][4].ENA +rst_i => nabla1fx[1][3].ENA +rst_i => nabla1fx[1][2].ENA +rst_i => nabla1fx[1][1].ENA +rst_i => nabla1fx[1][0].ENA +rst_i => nabla1fx[2][15].ENA +rst_i => nabla1fx[2][14].ENA +rst_i => nabla1fx[2][13].ENA +rst_i => nabla1fx[2][12].ENA +rst_i => nabla1fx[2][11].ENA +rst_i => nabla1fx[2][10].ENA +rst_i => nabla1fx[2][9].ENA +rst_i => nabla1fx[2][8].ENA +rst_i => nabla1fx[2][7].ENA +rst_i => nabla1fx[2][6].ENA +rst_i => nabla1fx[2][5].ENA +rst_i => nabla1fx[2][4].ENA +rst_i => nabla1fx[2][3].ENA +rst_i => nabla1fx[2][2].ENA +rst_i => nabla1fx[2][1].ENA +rst_i => nabla1fx[2][0].ENA +rst_i => nabla2fx[1][15].ENA +rst_i => nabla2fx[1][14].ENA +rst_i => nabla2fx[1][13].ENA +rst_i => nabla2fx[1][12].ENA +rst_i => nabla2fx[1][11].ENA +rst_i => nabla2fx[1][10].ENA +rst_i => nabla2fx[1][9].ENA +rst_i => nabla2fx[1][8].ENA +rst_i => nabla2fx[1][7].ENA +rst_i => nabla2fx[1][6].ENA +rst_i => nabla2fx[1][5].ENA +rst_i => nabla2fx[1][4].ENA +rst_i => nabla2fx[1][3].ENA +rst_i => nabla2fx[1][2].ENA +rst_i => nabla2fx[1][1].ENA +rst_i => nabla2fx[1][0].ENA +rst_i => nabla2fx[2][15].ENA +rst_i => nabla2fx[2][14].ENA +rst_i => nabla2fx[2][13].ENA +rst_i => nabla2fx[2][12].ENA +rst_i => nabla2fx[2][11].ENA +rst_i => nabla2fx[2][10].ENA +rst_i => nabla2fx[2][9].ENA +rst_i => nabla2fx[2][8].ENA +rst_i => nabla2fx[2][7].ENA +rst_i => nabla2fx[2][6].ENA +rst_i => nabla2fx[2][5].ENA +rst_i => nabla2fx[2][4].ENA +rst_i => nabla2fx[2][3].ENA +rst_i => nabla2fx[2][2].ENA +rst_i => nabla2fx[2][1].ENA +rst_i => nabla2fx[2][0].ENA +rst_i => nabla3fx[1][15].ENA +rst_i => nabla3fx[1][14].ENA +rst_i => nabla3fx[1][13].ENA +rst_i => nabla3fx[1][12].ENA +rst_i => nabla3fx[1][11].ENA +rst_i => nabla3fx[1][10].ENA +rst_i => nabla3fx[1][9].ENA +rst_i => nabla3fx[1][8].ENA +rst_i => nabla3fx[1][7].ENA +rst_i => nabla3fx[1][6].ENA +rst_i => nabla3fx[1][5].ENA +rst_i => nabla3fx[1][4].ENA +rst_i => nabla3fx[1][3].ENA +rst_i => nabla3fx[1][2].ENA +rst_i => nabla3fx[1][1].ENA +rst_i => nabla3fx[1][0].ENA +rst_i => nabla3fx[2][15].ENA +rst_i => nabla3fx[2][14].ENA +rst_i => nabla3fx[2][13].ENA +rst_i => nabla3fx[2][12].ENA +rst_i => nabla3fx[2][11].ENA +rst_i => nabla3fx[2][10].ENA +rst_i => nabla3fx[2][9].ENA +rst_i => nabla3fx[2][8].ENA +rst_i => nabla3fx[2][7].ENA +rst_i => nabla3fx[2][6].ENA +rst_i => nabla3fx[2][5].ENA +rst_i => nabla3fx[2][4].ENA +rst_i => nabla3fx[2][3].ENA +rst_i => nabla3fx[2][2].ENA +rst_i => nabla3fx[2][1].ENA +rst_i => nabla3fx[2][0].ENA +rst_i => nabla4fx[1][15].ENA +rst_i => nabla4fx[1][14].ENA +rst_i => nabla4fx[1][13].ENA +rst_i => nabla4fx[1][12].ENA +rst_i => nabla4fx[1][11].ENA +rst_i => nabla4fx[1][10].ENA +rst_i => nabla4fx[1][9].ENA +rst_i => nabla4fx[1][8].ENA +rst_i => nabla4fx[1][7].ENA +rst_i => nabla4fx[1][6].ENA +rst_i => nabla4fx[1][5].ENA +rst_i => nabla4fx[1][4].ENA +rst_i => nabla4fx[1][3].ENA +rst_i => nabla4fx[1][2].ENA +rst_i => nabla4fx[1][1].ENA +rst_i => nabla4fx[1][0].ENA +rst_i => nabla4fx[2][15].ENA +rst_i => nabla4fx[2][14].ENA +rst_i => nabla4fx[2][13].ENA +rst_i => nabla4fx[2][12].ENA +rst_i => nabla4fx[2][11].ENA +rst_i => nabla4fx[2][10].ENA +rst_i => nabla4fx[2][9].ENA +rst_i => nabla4fx[2][8].ENA +rst_i => nabla4fx[2][7].ENA +rst_i => nabla4fx[2][6].ENA +rst_i => nabla4fx[2][5].ENA +rst_i => nabla4fx[2][4].ENA +rst_i => nabla4fx[2][3].ENA +rst_i => nabla4fx[2][2].ENA +rst_i => nabla4fx[2][1].ENA +rst_i => nabla4fx[2][0].ENA +rst_i => resultado[15].ENA +rst_i => resultado[14].ENA +rst_i => resultado[13].ENA +rst_i => resultado[12].ENA +rst_i => resultado[11].ENA +rst_i => resultado[10].ENA +rst_i => resultado[9].ENA +rst_i => resultado[8].ENA +rst_i => resultado[7].ENA +rst_i => resultado[6].ENA +rst_i => resultado[5].ENA +rst_i => resultado[4].ENA +rst_i => resultado[3].ENA +rst_i => resultado[2].ENA +rst_i => resultado[1].ENA +rst_i => resultado[0].ENA +rst_i => fxx_o[15]~reg0.ENA +rst_i => fxx_o[14]~reg0.ENA +rst_i => fxx_o[13]~reg0.ENA +rst_i => fxx_o[12]~reg0.ENA +rst_i => fxx_o[11]~reg0.ENA +rst_i => fxx_o[10]~reg0.ENA +rst_i => fxx_o[9]~reg0.ENA +rst_i => fxx_o[8]~reg0.ENA +rst_i => fxx_o[7]~reg0.ENA +rst_i => fxx_o[6]~reg0.ENA +rst_i => fxx_o[5]~reg0.ENA +rst_i => fxx_o[4]~reg0.ENA +rst_i => fxx_o[3]~reg0.ENA +rst_i => fxx_o[2]~reg0.ENA +rst_i => fxx_o[1]~reg0.ENA +rst_i => fxx_o[0]~reg0.ENA +rst_i => fxx1_o[15]~reg0.ENA +rst_i => fxx1_o[14]~reg0.ENA +rst_i => fxx1_o[13]~reg0.ENA +rst_i => fxx1_o[12]~reg0.ENA +rst_i => fxx1_o[11]~reg0.ENA +rst_i => fxx1_o[10]~reg0.ENA +rst_i => fxx1_o[9]~reg0.ENA +rst_i => fxx1_o[8]~reg0.ENA +rst_i => fxx1_o[7]~reg0.ENA +rst_i => fxx1_o[6]~reg0.ENA +rst_i => fxx1_o[5]~reg0.ENA +rst_i => fxx1_o[4]~reg0.ENA +rst_i => fxx1_o[3]~reg0.ENA +rst_i => fxx1_o[2]~reg0.ENA +rst_i => fxx1_o[1]~reg0.ENA +rst_i => fxx1_o[0]~reg0.ENA +rst_i => fxx2_o[15]~reg0.ENA +rst_i => fxx2_o[14]~reg0.ENA +rst_i => fxx2_o[13]~reg0.ENA +rst_i => fxx2_o[12]~reg0.ENA +rst_i => fxx2_o[11]~reg0.ENA +rst_i => fxx2_o[10]~reg0.ENA +rst_i => fxx2_o[9]~reg0.ENA +rst_i => fxx2_o[8]~reg0.ENA +rst_i => fxx2_o[7]~reg0.ENA +rst_i => fxx2_o[6]~reg0.ENA +rst_i => fxx2_o[5]~reg0.ENA +rst_i => fxx2_o[4]~reg0.ENA +rst_i => fxx2_o[3]~reg0.ENA +rst_i => fxx2_o[2]~reg0.ENA +rst_i => fxx2_o[1]~reg0.ENA +rst_i => fxx2_o[0]~reg0.ENA +rst_i => fxx3_o[15]~reg0.ENA +rst_i => fxx3_o[14]~reg0.ENA +rst_i => fxx3_o[13]~reg0.ENA +rst_i => fxx3_o[12]~reg0.ENA +rst_i => fxx3_o[11]~reg0.ENA +rst_i => fxx3_o[10]~reg0.ENA +rst_i => fxx3_o[9]~reg0.ENA +rst_i => fxx3_o[8]~reg0.ENA +rst_i => fxx3_o[7]~reg0.ENA +rst_i => fxx3_o[6]~reg0.ENA +rst_i => fxx3_o[5]~reg0.ENA +rst_i => fxx3_o[4]~reg0.ENA +rst_i => fxx3_o[3]~reg0.ENA +rst_i => fxx3_o[2]~reg0.ENA +rst_i => fxx3_o[1]~reg0.ENA +rst_i => fxx3_o[0]~reg0.ENA +rst_i => fxx4_o[15]~reg0.ENA +rst_i => fxx4_o[14]~reg0.ENA +rst_i => fxx4_o[13]~reg0.ENA +rst_i => fxx4_o[12]~reg0.ENA +rst_i => fxx4_o[11]~reg0.ENA +rst_i => fxx4_o[10]~reg0.ENA +rst_i => fxx4_o[9]~reg0.ENA +rst_i => fxx4_o[8]~reg0.ENA +rst_i => fxx4_o[7]~reg0.ENA +rst_i => fxx4_o[6]~reg0.ENA +rst_i => fxx4_o[5]~reg0.ENA +rst_i => fxx4_o[4]~reg0.ENA +rst_i => fxx4_o[3]~reg0.ENA +rst_i => fxx4_o[2]~reg0.ENA +rst_i => fxx4_o[1]~reg0.ENA +rst_i => fxx4_o[0]~reg0.ENA +rst_i => resul_o[15]~reg0.ENA +rst_i => resul_o[14]~reg0.ENA +rst_i => resul_o[13]~reg0.ENA +rst_i => resul_o[12]~reg0.ENA +rst_i => resul_o[11]~reg0.ENA +rst_i => resul_o[10]~reg0.ENA +rst_i => resul_o[9]~reg0.ENA +rst_i => resul_o[8]~reg0.ENA +rst_i => resul_o[7]~reg0.ENA +rst_i => resul_o[6]~reg0.ENA +rst_i => resul_o[5]~reg0.ENA +rst_i => resul_o[4]~reg0.ENA +rst_i => resul_o[3]~reg0.ENA +rst_i => resul_o[2]~reg0.ENA +rst_i => resul_o[1]~reg0.ENA +rst_i => resul_o[0]~reg0.ENA +clk_i => resul_o[0]~reg0.CLK +clk_i => resul_o[1]~reg0.CLK +clk_i => resul_o[2]~reg0.CLK +clk_i => resul_o[3]~reg0.CLK +clk_i => resul_o[4]~reg0.CLK +clk_i => resul_o[5]~reg0.CLK +clk_i => resul_o[6]~reg0.CLK +clk_i => resul_o[7]~reg0.CLK +clk_i => resul_o[8]~reg0.CLK +clk_i => resul_o[9]~reg0.CLK +clk_i => resul_o[10]~reg0.CLK +clk_i => resul_o[11]~reg0.CLK +clk_i => resul_o[12]~reg0.CLK +clk_i => resul_o[13]~reg0.CLK +clk_i => resul_o[14]~reg0.CLK +clk_i => resul_o[15]~reg0.CLK +clk_i => fxx4_o[0]~reg0.CLK +clk_i => fxx4_o[1]~reg0.CLK +clk_i => fxx4_o[2]~reg0.CLK +clk_i => fxx4_o[3]~reg0.CLK +clk_i => fxx4_o[4]~reg0.CLK +clk_i => fxx4_o[5]~reg0.CLK +clk_i => fxx4_o[6]~reg0.CLK +clk_i => fxx4_o[7]~reg0.CLK +clk_i => fxx4_o[8]~reg0.CLK +clk_i => fxx4_o[9]~reg0.CLK +clk_i => fxx4_o[10]~reg0.CLK +clk_i => fxx4_o[11]~reg0.CLK +clk_i => fxx4_o[12]~reg0.CLK +clk_i => fxx4_o[13]~reg0.CLK +clk_i => fxx4_o[14]~reg0.CLK +clk_i => fxx4_o[15]~reg0.CLK +clk_i => fxx3_o[0]~reg0.CLK +clk_i => fxx3_o[1]~reg0.CLK +clk_i => fxx3_o[2]~reg0.CLK +clk_i => fxx3_o[3]~reg0.CLK +clk_i => fxx3_o[4]~reg0.CLK +clk_i => fxx3_o[5]~reg0.CLK +clk_i => fxx3_o[6]~reg0.CLK +clk_i => fxx3_o[7]~reg0.CLK +clk_i => fxx3_o[8]~reg0.CLK +clk_i => fxx3_o[9]~reg0.CLK +clk_i => fxx3_o[10]~reg0.CLK +clk_i => fxx3_o[11]~reg0.CLK +clk_i => fxx3_o[12]~reg0.CLK +clk_i => fxx3_o[13]~reg0.CLK +clk_i => fxx3_o[14]~reg0.CLK +clk_i => fxx3_o[15]~reg0.CLK +clk_i => fxx2_o[0]~reg0.CLK +clk_i => fxx2_o[1]~reg0.CLK +clk_i => fxx2_o[2]~reg0.CLK +clk_i => fxx2_o[3]~reg0.CLK +clk_i => fxx2_o[4]~reg0.CLK +clk_i => fxx2_o[5]~reg0.CLK +clk_i => fxx2_o[6]~reg0.CLK +clk_i => fxx2_o[7]~reg0.CLK +clk_i => fxx2_o[8]~reg0.CLK +clk_i => fxx2_o[9]~reg0.CLK +clk_i => fxx2_o[10]~reg0.CLK +clk_i => fxx2_o[11]~reg0.CLK +clk_i => fxx2_o[12]~reg0.CLK +clk_i => fxx2_o[13]~reg0.CLK +clk_i => fxx2_o[14]~reg0.CLK +clk_i => fxx2_o[15]~reg0.CLK +clk_i => fxx1_o[0]~reg0.CLK +clk_i => fxx1_o[1]~reg0.CLK +clk_i => fxx1_o[2]~reg0.CLK +clk_i => fxx1_o[3]~reg0.CLK +clk_i => fxx1_o[4]~reg0.CLK +clk_i => fxx1_o[5]~reg0.CLK +clk_i => fxx1_o[6]~reg0.CLK +clk_i => fxx1_o[7]~reg0.CLK +clk_i => fxx1_o[8]~reg0.CLK +clk_i => fxx1_o[9]~reg0.CLK +clk_i => fxx1_o[10]~reg0.CLK +clk_i => fxx1_o[11]~reg0.CLK +clk_i => fxx1_o[12]~reg0.CLK +clk_i => fxx1_o[13]~reg0.CLK +clk_i => fxx1_o[14]~reg0.CLK +clk_i => fxx1_o[15]~reg0.CLK +clk_i => fxx_o[0]~reg0.CLK +clk_i => fxx_o[1]~reg0.CLK +clk_i => fxx_o[2]~reg0.CLK +clk_i => fxx_o[3]~reg0.CLK +clk_i => fxx_o[4]~reg0.CLK +clk_i => fxx_o[5]~reg0.CLK +clk_i => fxx_o[6]~reg0.CLK +clk_i => fxx_o[7]~reg0.CLK +clk_i => fxx_o[8]~reg0.CLK +clk_i => fxx_o[9]~reg0.CLK +clk_i => fxx_o[10]~reg0.CLK +clk_i => fxx_o[11]~reg0.CLK +clk_i => fxx_o[12]~reg0.CLK +clk_i => fxx_o[13]~reg0.CLK +clk_i => fxx_o[14]~reg0.CLK +clk_i => fxx_o[15]~reg0.CLK +clk_i => indice[0].CLK +clk_i => indice[1].CLK +clk_i => indice[2].CLK +clk_i => indice[3].CLK +clk_i => indice[4].CLK +clk_i => resultado[0].CLK +clk_i => resultado[1].CLK +clk_i => resultado[2].CLK +clk_i => resultado[3].CLK +clk_i => resultado[4].CLK +clk_i => resultado[5].CLK +clk_i => resultado[6].CLK +clk_i => resultado[7].CLK +clk_i => resultado[8].CLK +clk_i => resultado[9].CLK +clk_i => resultado[10].CLK +clk_i => resultado[11].CLK +clk_i => resultado[12].CLK +clk_i => resultado[13].CLK +clk_i => resultado[14].CLK +clk_i => resultado[15].CLK +clk_i => nabla4fx[2][0].CLK +clk_i => nabla4fx[2][1].CLK +clk_i => nabla4fx[2][2].CLK +clk_i => nabla4fx[2][3].CLK +clk_i => nabla4fx[2][4].CLK +clk_i => nabla4fx[2][5].CLK +clk_i => nabla4fx[2][6].CLK +clk_i => nabla4fx[2][7].CLK +clk_i => nabla4fx[2][8].CLK +clk_i => nabla4fx[2][9].CLK +clk_i => nabla4fx[2][10].CLK +clk_i => nabla4fx[2][11].CLK +clk_i => nabla4fx[2][12].CLK +clk_i => nabla4fx[2][13].CLK +clk_i => nabla4fx[2][14].CLK +clk_i => nabla4fx[2][15].CLK +clk_i => nabla4fx[1][0].CLK +clk_i => nabla4fx[1][1].CLK +clk_i => nabla4fx[1][2].CLK +clk_i => nabla4fx[1][3].CLK +clk_i => nabla4fx[1][4].CLK +clk_i => nabla4fx[1][5].CLK +clk_i => nabla4fx[1][6].CLK +clk_i => nabla4fx[1][7].CLK +clk_i => nabla4fx[1][8].CLK +clk_i => nabla4fx[1][9].CLK +clk_i => nabla4fx[1][10].CLK +clk_i => nabla4fx[1][11].CLK +clk_i => nabla4fx[1][12].CLK +clk_i => nabla4fx[1][13].CLK +clk_i => nabla4fx[1][14].CLK +clk_i => nabla4fx[1][15].CLK +clk_i => nabla4fx[0][0].CLK +clk_i => nabla4fx[0][1].CLK +clk_i => nabla4fx[0][2].CLK +clk_i => nabla4fx[0][3].CLK +clk_i => nabla4fx[0][4].CLK +clk_i => nabla4fx[0][5].CLK +clk_i => nabla4fx[0][6].CLK +clk_i => nabla4fx[0][7].CLK +clk_i => nabla4fx[0][8].CLK +clk_i => nabla4fx[0][9].CLK +clk_i => nabla4fx[0][10].CLK +clk_i => nabla4fx[0][11].CLK +clk_i => nabla4fx[0][12].CLK +clk_i => nabla4fx[0][13].CLK +clk_i => nabla4fx[0][14].CLK +clk_i => nabla4fx[0][15].CLK +clk_i => nabla3fx[2][0].CLK +clk_i => nabla3fx[2][1].CLK +clk_i => nabla3fx[2][2].CLK +clk_i => nabla3fx[2][3].CLK +clk_i => nabla3fx[2][4].CLK +clk_i => nabla3fx[2][5].CLK +clk_i => nabla3fx[2][6].CLK +clk_i => nabla3fx[2][7].CLK +clk_i => nabla3fx[2][8].CLK +clk_i => nabla3fx[2][9].CLK +clk_i => nabla3fx[2][10].CLK +clk_i => nabla3fx[2][11].CLK +clk_i => nabla3fx[2][12].CLK +clk_i => nabla3fx[2][13].CLK +clk_i => nabla3fx[2][14].CLK +clk_i => nabla3fx[2][15].CLK +clk_i => nabla3fx[1][0].CLK +clk_i => nabla3fx[1][1].CLK +clk_i => nabla3fx[1][2].CLK +clk_i => nabla3fx[1][3].CLK +clk_i => nabla3fx[1][4].CLK +clk_i => nabla3fx[1][5].CLK +clk_i => nabla3fx[1][6].CLK +clk_i => nabla3fx[1][7].CLK +clk_i => nabla3fx[1][8].CLK +clk_i => nabla3fx[1][9].CLK +clk_i => nabla3fx[1][10].CLK +clk_i => nabla3fx[1][11].CLK +clk_i => nabla3fx[1][12].CLK +clk_i => nabla3fx[1][13].CLK +clk_i => nabla3fx[1][14].CLK +clk_i => nabla3fx[1][15].CLK +clk_i => nabla3fx[0][0].CLK +clk_i => nabla3fx[0][1].CLK +clk_i => nabla3fx[0][2].CLK +clk_i => nabla3fx[0][3].CLK +clk_i => nabla3fx[0][4].CLK +clk_i => nabla3fx[0][5].CLK +clk_i => nabla3fx[0][6].CLK +clk_i => nabla3fx[0][7].CLK +clk_i => nabla3fx[0][8].CLK +clk_i => nabla3fx[0][9].CLK +clk_i => nabla3fx[0][10].CLK +clk_i => nabla3fx[0][11].CLK +clk_i => nabla3fx[0][12].CLK +clk_i => nabla3fx[0][13].CLK +clk_i => nabla3fx[0][14].CLK +clk_i => nabla3fx[0][15].CLK +clk_i => nabla2fx[2][0].CLK +clk_i => nabla2fx[2][1].CLK +clk_i => nabla2fx[2][2].CLK +clk_i => nabla2fx[2][3].CLK +clk_i => nabla2fx[2][4].CLK +clk_i => nabla2fx[2][5].CLK +clk_i => nabla2fx[2][6].CLK +clk_i => nabla2fx[2][7].CLK +clk_i => nabla2fx[2][8].CLK +clk_i => nabla2fx[2][9].CLK +clk_i => nabla2fx[2][10].CLK +clk_i => nabla2fx[2][11].CLK +clk_i => nabla2fx[2][12].CLK +clk_i => nabla2fx[2][13].CLK +clk_i => nabla2fx[2][14].CLK +clk_i => nabla2fx[2][15].CLK +clk_i => nabla2fx[1][0].CLK +clk_i => nabla2fx[1][1].CLK +clk_i => nabla2fx[1][2].CLK +clk_i => nabla2fx[1][3].CLK +clk_i => nabla2fx[1][4].CLK +clk_i => nabla2fx[1][5].CLK +clk_i => nabla2fx[1][6].CLK +clk_i => nabla2fx[1][7].CLK +clk_i => nabla2fx[1][8].CLK +clk_i => nabla2fx[1][9].CLK +clk_i => nabla2fx[1][10].CLK +clk_i => nabla2fx[1][11].CLK +clk_i => nabla2fx[1][12].CLK +clk_i => nabla2fx[1][13].CLK +clk_i => nabla2fx[1][14].CLK +clk_i => nabla2fx[1][15].CLK +clk_i => nabla2fx[0][0].CLK +clk_i => nabla2fx[0][1].CLK +clk_i => nabla2fx[0][2].CLK +clk_i => nabla2fx[0][3].CLK +clk_i => nabla2fx[0][4].CLK +clk_i => nabla2fx[0][5].CLK +clk_i => nabla2fx[0][6].CLK +clk_i => nabla2fx[0][7].CLK +clk_i => nabla2fx[0][8].CLK +clk_i => nabla2fx[0][9].CLK +clk_i => nabla2fx[0][10].CLK +clk_i => nabla2fx[0][11].CLK +clk_i => nabla2fx[0][12].CLK +clk_i => nabla2fx[0][13].CLK +clk_i => nabla2fx[0][14].CLK +clk_i => nabla2fx[0][15].CLK +clk_i => nabla1fx[2][0].CLK +clk_i => nabla1fx[2][1].CLK +clk_i => nabla1fx[2][2].CLK +clk_i => nabla1fx[2][3].CLK +clk_i => nabla1fx[2][4].CLK +clk_i => nabla1fx[2][5].CLK +clk_i => nabla1fx[2][6].CLK +clk_i => nabla1fx[2][7].CLK +clk_i => nabla1fx[2][8].CLK +clk_i => nabla1fx[2][9].CLK +clk_i => nabla1fx[2][10].CLK +clk_i => nabla1fx[2][11].CLK +clk_i => nabla1fx[2][12].CLK +clk_i => nabla1fx[2][13].CLK +clk_i => nabla1fx[2][14].CLK +clk_i => nabla1fx[2][15].CLK +clk_i => nabla1fx[1][0].CLK +clk_i => nabla1fx[1][1].CLK +clk_i => nabla1fx[1][2].CLK +clk_i => nabla1fx[1][3].CLK +clk_i => nabla1fx[1][4].CLK +clk_i => nabla1fx[1][5].CLK +clk_i => nabla1fx[1][6].CLK +clk_i => nabla1fx[1][7].CLK +clk_i => nabla1fx[1][8].CLK +clk_i => nabla1fx[1][9].CLK +clk_i => nabla1fx[1][10].CLK +clk_i => nabla1fx[1][11].CLK +clk_i => nabla1fx[1][12].CLK +clk_i => nabla1fx[1][13].CLK +clk_i => nabla1fx[1][14].CLK +clk_i => nabla1fx[1][15].CLK +clk_i => nabla1fx[0][0].CLK +clk_i => nabla1fx[0][1].CLK +clk_i => nabla1fx[0][2].CLK +clk_i => nabla1fx[0][3].CLK +clk_i => nabla1fx[0][4].CLK +clk_i => nabla1fx[0][5].CLK +clk_i => nabla1fx[0][6].CLK +clk_i => nabla1fx[0][7].CLK +clk_i => nabla1fx[0][8].CLK +clk_i => nabla1fx[0][9].CLK +clk_i => nabla1fx[0][10].CLK +clk_i => nabla1fx[0][11].CLK +clk_i => nabla1fx[0][12].CLK +clk_i => nabla1fx[0][13].CLK +clk_i => nabla1fx[0][14].CLK +clk_i => nabla1fx[0][15].CLK +clk_i => fx[2][0].CLK +clk_i => fx[2][1].CLK +clk_i => fx[2][2].CLK +clk_i => fx[2][3].CLK +clk_i => fx[2][4].CLK +clk_i => fx[2][5].CLK +clk_i => fx[2][6].CLK +clk_i => fx[2][7].CLK +clk_i => fx[2][8].CLK +clk_i => fx[2][9].CLK +clk_i => fx[2][10].CLK +clk_i => fx[2][11].CLK +clk_i => fx[2][12].CLK +clk_i => fx[2][13].CLK +clk_i => fx[2][14].CLK +clk_i => fx[2][15].CLK +clk_i => fx[1][0].CLK +clk_i => fx[1][1].CLK +clk_i => fx[1][2].CLK +clk_i => fx[1][3].CLK +clk_i => fx[1][4].CLK +clk_i => fx[1][5].CLK +clk_i => fx[1][6].CLK +clk_i => fx[1][7].CLK +clk_i => fx[1][8].CLK +clk_i => fx[1][9].CLK +clk_i => fx[1][10].CLK +clk_i => fx[1][11].CLK +clk_i => fx[1][12].CLK +clk_i => fx[1][13].CLK +clk_i => fx[1][14].CLK +clk_i => fx[1][15].CLK +clk_i => fx[0][0].CLK +clk_i => fx[0][1].CLK +clk_i => fx[0][2].CLK +clk_i => fx[0][3].CLK +clk_i => fx[0][4].CLK +clk_i => fx[0][5].CLK +clk_i => fx[0][6].CLK +clk_i => fx[0][7].CLK +clk_i => fx[0][8].CLK +clk_i => fx[0][9].CLK +clk_i => fx[0][10].CLK +clk_i => fx[0][11].CLK +clk_i => fx[0][12].CLK +clk_i => fx[0][13].CLK +clk_i => fx[0][14].CLK +clk_i => fx[0][15].CLK +clk_i => cont[0].CLK +clk_i => cont[1].CLK +clk_i => cont[2].CLK +clk_i => cont[3].CLK +clk_i => cont[4].CLK +clk_i => cont[5].CLK +clk_i => cont[6].CLK +clk_i => cont[7].CLK +clk_i => cont[8].CLK +clk_i => cont[9].CLK +clk_i => cont[10].CLK +clk_i => cont[11].CLK +clk_i => cont[12].CLK +clk_i => cont[13].CLK +clk_i => cont[14].CLK +clk_i => cont[15].CLK +clk_i => i[0].CLK +clk_i => i[1].CLK +clk_i => sram[0].CLK +clk_i => sram[1].CLK +clk_i => sram[2].CLK +clk_i => sram[3].CLK +clk_i => sram[4].CLK +clk_i => sram[5].CLK +clk_i => sram[6].CLK +clk_i => sram[7].CLK +clk_i => sram[8].CLK +clk_i => sram[9].CLK +clk_i => sram[10].CLK +clk_i => sram[11].CLK +clk_i => sram[12].CLK +clk_i => sram[13].CLK +clk_i => sram[14].CLK +clk_i => sram[15].CLK +distancia_i[0] => Equal0.IN15 +distancia_i[1] => Equal0.IN14 +distancia_i[2] => Equal0.IN13 +distancia_i[3] => Equal0.IN12 +distancia_i[4] => Equal0.IN11 +distancia_i[5] => Equal0.IN10 +distancia_i[6] => Equal0.IN9 +distancia_i[7] => Equal0.IN8 +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => fx.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +extrapolar_i => cont.OUTPUTSELECT +fxx_o[0] <= fxx_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx_o[1] <= fxx_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx_o[2] <= fxx_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx_o[3] <= fxx_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx_o[4] <= fxx_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx_o[5] <= fxx_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx_o[6] <= fxx_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx_o[7] <= fxx_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx_o[8] <= fxx_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx_o[9] <= fxx_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx_o[10] <= fxx_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx_o[11] <= fxx_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx_o[12] <= fxx_o[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx_o[13] <= fxx_o[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx_o[14] <= fxx_o[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx_o[15] <= fxx_o[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx1_o[0] <= fxx1_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx1_o[1] <= fxx1_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx1_o[2] <= fxx1_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx1_o[3] <= fxx1_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx1_o[4] <= fxx1_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx1_o[5] <= fxx1_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx1_o[6] <= fxx1_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx1_o[7] <= fxx1_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx1_o[8] <= fxx1_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx1_o[9] <= fxx1_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx1_o[10] <= fxx1_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx1_o[11] <= fxx1_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx1_o[12] <= fxx1_o[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx1_o[13] <= fxx1_o[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx1_o[14] <= fxx1_o[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx1_o[15] <= fxx1_o[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx2_o[0] <= fxx2_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx2_o[1] <= fxx2_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx2_o[2] <= fxx2_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx2_o[3] <= fxx2_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx2_o[4] <= fxx2_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx2_o[5] <= fxx2_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx2_o[6] <= fxx2_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx2_o[7] <= fxx2_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx2_o[8] <= fxx2_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx2_o[9] <= fxx2_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx2_o[10] <= fxx2_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx2_o[11] <= fxx2_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx2_o[12] <= fxx2_o[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx2_o[13] <= fxx2_o[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx2_o[14] <= fxx2_o[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx2_o[15] <= fxx2_o[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx3_o[0] <= fxx3_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx3_o[1] <= fxx3_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx3_o[2] <= fxx3_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx3_o[3] <= fxx3_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx3_o[4] <= fxx3_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx3_o[5] <= fxx3_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx3_o[6] <= fxx3_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx3_o[7] <= fxx3_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx3_o[8] <= fxx3_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx3_o[9] <= fxx3_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx3_o[10] <= fxx3_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx3_o[11] <= fxx3_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx3_o[12] <= fxx3_o[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx3_o[13] <= fxx3_o[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx3_o[14] <= fxx3_o[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx3_o[15] <= fxx3_o[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx4_o[0] <= fxx4_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx4_o[1] <= fxx4_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx4_o[2] <= fxx4_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx4_o[3] <= fxx4_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx4_o[4] <= fxx4_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx4_o[5] <= fxx4_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx4_o[6] <= fxx4_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx4_o[7] <= fxx4_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx4_o[8] <= fxx4_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx4_o[9] <= fxx4_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx4_o[10] <= fxx4_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx4_o[11] <= fxx4_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx4_o[12] <= fxx4_o[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx4_o[13] <= fxx4_o[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx4_o[14] <= fxx4_o[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +fxx4_o[15] <= fxx4_o[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE +resul_o[0] <= resul_o[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +resul_o[1] <= resul_o[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +resul_o[2] <= resul_o[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +resul_o[3] <= resul_o[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +resul_o[4] <= resul_o[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +resul_o[5] <= resul_o[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +resul_o[6] <= resul_o[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +resul_o[7] <= resul_o[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE +resul_o[8] <= resul_o[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE +resul_o[9] <= resul_o[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE +resul_o[10] <= resul_o[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE +resul_o[11] <= resul_o[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE +resul_o[12] <= resul_o[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE +resul_o[13] <= resul_o[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE +resul_o[14] <= resul_o[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE +resul_o[15] <= resul_o[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE + + Index: trunk/QuartusII/db/prev_cmp_gnextrapolator.qmsg =================================================================== --- trunk/QuartusII/db/prev_cmp_gnextrapolator.qmsg (nonexistent) +++ trunk/QuartusII/db/prev_cmp_gnextrapolator.qmsg (revision 5) @@ -0,0 +1,40 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 14 00:27:38 2012 " "Info: Processing started: Tue Aug 14 00:27:38 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolator " "Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolator" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "IMPP_MPP_USER_DEVICE" "gnextrapolator EP2S15F484C4 " "Info: Selected device EP2S15F484C4 for design \"gnextrapolator\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Info: Low junction temperature is 0 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "Info: High junction temperature is 85 degrees C" { } { } 0 0 "%1!s! is %2!s!" 0 0 "" 0 -1} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature." { } { } 0 0 "Feature %1!s! is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature." 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2S15F484I4 " "Info: Device EP2S15F484I4 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "1 " "Info: Fitter converted 1 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~DATA0~ E13 " "Info: Pin ~DATA0~ is reserved at location E13" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { ~DATA0~ } } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { ~DATA0~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 1021 3016 4149 0} } } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 -1} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "107 107 " "Critical Warning: No exact pin location assignment(s) for 107 pins of 107 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[0\] " "Info: Pin fxx_o\[0\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[0] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 146 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[1\] " "Info: Pin fxx_o\[1\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[1] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 144 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[2\] " "Info: Pin fxx_o\[2\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[2] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 142 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[3\] " "Info: Pin fxx_o\[3\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[3] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 140 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[4\] " "Info: Pin fxx_o\[4\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[4] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 138 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[5\] " "Info: Pin fxx_o\[5\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[5] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 136 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[6\] " "Info: Pin fxx_o\[6\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[6] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 134 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[7\] " "Info: Pin fxx_o\[7\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[7] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 132 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[8\] " "Info: Pin fxx_o\[8\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[8] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 130 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[9\] " "Info: Pin fxx_o\[9\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[9] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 128 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[10\] " "Info: Pin fxx_o\[10\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[10] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 126 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[11\] " "Info: Pin fxx_o\[11\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[11] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 124 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[12\] " "Info: Pin fxx_o\[12\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[12] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 122 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[13\] " "Info: Pin fxx_o\[13\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[13] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 120 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[14\] " "Info: Pin fxx_o\[14\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[14] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 118 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx_o\[15\] " "Info: Pin fxx_o\[15\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx_o[15] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 116 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[0\] " "Info: Pin fxx1_o\[0\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[0] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 178 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[1\] " "Info: Pin fxx1_o\[1\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[1] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 176 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[2\] " "Info: Pin fxx1_o\[2\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[2] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 174 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[3\] " "Info: Pin fxx1_o\[3\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[3] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 172 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[4\] " "Info: Pin fxx1_o\[4\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[4] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 170 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[5\] " "Info: Pin fxx1_o\[5\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[5] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 168 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[6\] " "Info: Pin fxx1_o\[6\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[6] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 166 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[7\] " "Info: Pin fxx1_o\[7\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[7] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 164 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[8\] " "Info: Pin fxx1_o\[8\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[8] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 162 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[9\] " "Info: Pin fxx1_o\[9\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[9] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 160 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[10\] " "Info: Pin fxx1_o\[10\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[10] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 158 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[11\] " "Info: Pin fxx1_o\[11\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[11] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 156 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[12\] " "Info: Pin fxx1_o\[12\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[12] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 154 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[13\] " "Info: Pin fxx1_o\[13\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[13] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 152 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[14\] " "Info: Pin fxx1_o\[14\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[14] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 150 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx1_o\[15\] " "Info: Pin fxx1_o\[15\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx1_o[15] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx1_o[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 148 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[0\] " "Info: Pin fxx2_o\[0\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[0] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 210 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[1\] " "Info: Pin fxx2_o\[1\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[1] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 208 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[2\] " "Info: Pin fxx2_o\[2\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[2] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 206 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[3\] " "Info: Pin fxx2_o\[3\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[3] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 204 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[4\] " "Info: Pin fxx2_o\[4\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[4] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 202 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[5\] " "Info: Pin fxx2_o\[5\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[5] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 200 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[6\] " "Info: Pin fxx2_o\[6\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[6] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 198 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[7\] " "Info: Pin fxx2_o\[7\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[7] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 196 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[8\] " "Info: Pin fxx2_o\[8\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[8] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 194 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[9\] " "Info: Pin fxx2_o\[9\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[9] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 192 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[10\] " "Info: Pin fxx2_o\[10\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[10] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 190 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[11\] " "Info: Pin fxx2_o\[11\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[11] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 188 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[12\] " "Info: Pin fxx2_o\[12\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[12] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 186 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[13\] " "Info: Pin fxx2_o\[13\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[13] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 184 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[14\] " "Info: Pin fxx2_o\[14\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[14] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 182 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx2_o\[15\] " "Info: Pin fxx2_o\[15\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx2_o[15] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx2_o[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 180 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[0\] " "Info: Pin fxx3_o\[0\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[0] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 242 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[1\] " "Info: Pin fxx3_o\[1\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[1] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 240 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[2\] " "Info: Pin fxx3_o\[2\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[2] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 238 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[3\] " "Info: Pin fxx3_o\[3\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[3] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 236 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[4\] " "Info: Pin fxx3_o\[4\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[4] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 234 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[5\] " "Info: Pin fxx3_o\[5\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[5] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 232 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[6\] " "Info: Pin fxx3_o\[6\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[6] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 230 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[7\] " "Info: Pin fxx3_o\[7\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[7] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 228 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[8\] " "Info: Pin fxx3_o\[8\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[8] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 226 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[9\] " "Info: Pin fxx3_o\[9\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[9] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 224 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[10\] " "Info: Pin fxx3_o\[10\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[10] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 222 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[11\] " "Info: Pin fxx3_o\[11\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[11] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 220 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[12\] " "Info: Pin fxx3_o\[12\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[12] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 218 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[13\] " "Info: Pin fxx3_o\[13\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[13] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 216 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[14\] " "Info: Pin fxx3_o\[14\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[14] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 214 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx3_o\[15\] " "Info: Pin fxx3_o\[15\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx3_o[15] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx3_o[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 212 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[0\] " "Info: Pin fxx4_o\[0\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[0] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 274 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[1\] " "Info: Pin fxx4_o\[1\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[1] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 272 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[2\] " "Info: Pin fxx4_o\[2\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[2] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 270 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[3\] " "Info: Pin fxx4_o\[3\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[3] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 268 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[4\] " "Info: Pin fxx4_o\[4\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[4] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 266 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[5\] " "Info: Pin fxx4_o\[5\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[5] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 264 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[6\] " "Info: Pin fxx4_o\[6\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[6] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 262 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[7\] " "Info: Pin fxx4_o\[7\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[7] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 260 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[8\] " "Info: Pin fxx4_o\[8\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[8] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 258 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[9\] " "Info: Pin fxx4_o\[9\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[9] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 256 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[10\] " "Info: Pin fxx4_o\[10\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[10] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 254 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[11\] " "Info: Pin fxx4_o\[11\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[11] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 252 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[12\] " "Info: Pin fxx4_o\[12\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[12] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 250 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[13\] " "Info: Pin fxx4_o\[13\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[13] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 248 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[14\] " "Info: Pin fxx4_o\[14\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[14] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 246 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "fxx4_o\[15\] " "Info: Pin fxx4_o\[15\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { fxx4_o[15] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx4_o[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 244 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[0\] " "Info: Pin resul_o\[0\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[0] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 306 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[1\] " "Info: Pin resul_o\[1\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[1] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 304 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[2\] " "Info: Pin resul_o\[2\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[2] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 302 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[3\] " "Info: Pin resul_o\[3\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[3] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 300 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[4\] " "Info: Pin resul_o\[4\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[4] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 298 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[5\] " "Info: Pin resul_o\[5\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[5] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 296 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[6\] " "Info: Pin resul_o\[6\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[6] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 294 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[7\] " "Info: Pin resul_o\[7\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[7] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 292 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[8\] " "Info: Pin resul_o\[8\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[8] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 290 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[9\] " "Info: Pin resul_o\[9\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[9] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 288 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[10\] " "Info: Pin resul_o\[10\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[10] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 286 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[11\] " "Info: Pin resul_o\[11\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[11] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 284 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[12\] " "Info: Pin resul_o\[12\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[12] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 282 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[13\] " "Info: Pin resul_o\[13\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[13] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 280 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[14\] " "Info: Pin resul_o\[14\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[14] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 278 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "resul_o\[15\] " "Info: Pin resul_o\[15\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { resul_o[15] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resul_o[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 276 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "extrapolar_i " "Info: Pin extrapolar_i not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { extrapolar_i } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 54 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { extrapolar_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 328 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk_i " "Info: Pin clk_i not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { clk_i } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 327 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rst_i " "Info: Pin rst_i not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { rst_i } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 51 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 326 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[5\] " "Info: Pin distancia_i\[5\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[5] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 313 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[3\] " "Info: Pin distancia_i\[3\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[3] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 311 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[4\] " "Info: Pin distancia_i\[4\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[4] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 312 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[2\] " "Info: Pin distancia_i\[2\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[2] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 310 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[0\] " "Info: Pin distancia_i\[0\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[0] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 308 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[1\] " "Info: Pin distancia_i\[1\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[1] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 309 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[6\] " "Info: Pin distancia_i\[6\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[6] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 314 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "distancia_i\[7\] " "Info: Pin distancia_i\[7\] not assigned to an exact location on the device" { } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { distancia_i[7] } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 53 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { distancia_i[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 315 3016 4149 0} } } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 1 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1} +{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 0 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "" 0 -1} +{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Timing-driven compilation is using the Classic Timing Analyzer" { } { } 0 0 "Timing-driven compilation is using the %1!s! Timing Analyzer" 0 0 "" 0 -1} +{ "Info" "ITAN_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." { } { } 0 0 "Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time." 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_i (placed in PIN N20 (CLK3p, Input)) " "Info: Automatically promoted node clk_i (placed in PIN N20 (CLK3p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { clk_i } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 52 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 327 3016 4149 0} } } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst_i (placed in PIN M21 (CLK1p, Input)) " "Info: Automatically promoted node rst_i (placed in PIN M21 (CLK1p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G1 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1" { } { } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Info: Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "resultado\[0\] " "Info: Destination node resultado\[0\]" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { resultado[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 110 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[15\]~reg0 " "Info: Destination node fxx_o\[15\]~reg0" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[15]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 117 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[14\]~reg0 " "Info: Destination node fxx_o\[14\]~reg0" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[14]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 119 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[13\]~reg0 " "Info: Destination node fxx_o\[13\]~reg0" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[13]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 121 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[12\]~reg0 " "Info: Destination node fxx_o\[12\]~reg0" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[12]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 123 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[11\]~reg0 " "Info: Destination node fxx_o\[11\]~reg0" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[11]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 125 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[10\]~reg0 " "Info: Destination node fxx_o\[10\]~reg0" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[10]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 127 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[9\]~reg0 " "Info: Destination node fxx_o\[9\]~reg0" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[9]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 129 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[8\]~reg0 " "Info: Destination node fxx_o\[8\]~reg0" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[8]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 131 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "fxx_o\[7\]~reg0 " "Info: Destination node fxx_o\[7\]~reg0" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 0 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { fxx_o[7]~reg0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 133 3016 4149 0} } } } } 0 0 "Destination node %1!s!" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_LIMITED_TO_SUB" "10 " "Info: Non-global destination nodes limited to 10 nodes" { } { } 0 0 "Non-global destination nodes limited to %1!d! nodes" 0 0 "" 0 -1} } { } 0 0 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/pin_planner.ppl" "" { PinPlanner "c:/altera/quartus/bin/pin_planner.ppl" { rst_i } } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 51 -1 0 } } { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { rst_i } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/Altera/qdesigns/gnextrapolator/" 0 { } { { 0 { 0 ""} 0 326 3016 4149 0} } } } } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "" 0 -1} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" { } { } 1 0 "No registers were packed into other blocks" 0 0 "" 0 -1} } { } 0 0 "Finished register packing" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "105 unused 3.3V 9 96 0 " "Info: Number of I/O pins in group: 105 (unused VREF, 3.3V VCCIO, 9 input, 96 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 1 39 " "Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 39 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 1 43 " "Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 43 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 1 49 " "Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 49 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 35 " "Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 44 " "Info: I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 44 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 0 40 " "Info: I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 34 " "Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 34 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "Info: I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use undetermined 0 6 " "Info: I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "10 does not use undetermined 0 6 " "Info: I/O bank number 10 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Info: Fitter preparation operations ending: elapsed time is 00:00:03" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Info: Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} +{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "10.924 ns memory register " "Info: Estimated most critical path is memory to register delay of 10.924 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a7~porta_address_reg4 1 MEM M512_X24_Y8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M512_X24_Y8; Fanout = 1; MEM Node = 'altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a7~porta_address_reg4'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7~porta_address_reg4 } "NODE_NAME" } } { "db/altsyncram_uv61.tdf" "" { Text "C:/Altera/qdesigns/gnextrapolator/db/altsyncram_uv61.tdf" 174 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.061 ns) 2.061 ns altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a7 2 MEM M512_X24_Y8 6 " "Info: 2: + IC(0.000 ns) + CELL(2.061 ns) = 2.061 ns; Loc. = M512_X24_Y8; Fanout = 6; MEM Node = 'altsyncram:ram_rtl_0\|altsyncram_uv61:auto_generated\|ram_block1a7'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "2.061 ns" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7~porta_address_reg4 altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7 } "NODE_NAME" } } { "db/altsyncram_uv61.tdf" "" { Text "C:/Altera/qdesigns/gnextrapolator/db/altsyncram_uv61.tdf" 174 2 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.821 ns) + CELL(0.313 ns) 3.195 ns fx~23 3 COMB LAB_X27_Y5 2 " "Info: 3: + IC(0.821 ns) + CELL(0.313 ns) = 3.195 ns; Loc. = LAB_X27_Y5; Fanout = 2; COMB Node = 'fx~23'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.134 ns" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7 fx~23 } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 89 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.879 ns) + CELL(0.480 ns) 4.554 ns Add2~37 4 COMB LAB_X23_Y8 6 " "Info: 4: + IC(0.879 ns) + CELL(0.480 ns) = 4.554 ns; Loc. = LAB_X23_Y8; Fanout = 6; COMB Node = 'Add2~37'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.359 ns" { fx~23 Add2~37 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.580 ns) + CELL(0.480 ns) 5.614 ns Add3~33 5 COMB LAB_X22_Y7 7 " "Info: 5: + IC(0.580 ns) + CELL(0.480 ns) = 5.614 ns; Loc. = LAB_X22_Y7; Fanout = 7; COMB Node = 'Add3~33'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.060 ns" { Add2~37 Add3~33 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.833 ns) + CELL(0.426 ns) 6.873 ns Add4~37 6 COMB LAB_X22_Y6 7 " "Info: 6: + IC(0.833 ns) + CELL(0.426 ns) = 6.873 ns; Loc. = LAB_X22_Y6; Fanout = 7; COMB Node = 'Add4~37'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.259 ns" { Add3~33 Add4~37 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 1120 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.775 ns) + CELL(0.480 ns) 8.128 ns Add8~29 7 COMB LAB_X25_Y6 2 " "Info: 7: + IC(0.775 ns) + CELL(0.480 ns) = 8.128 ns; Loc. = LAB_X25_Y6; Fanout = 2; COMB Node = 'Add8~29'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.255 ns" { Add4~37 Add8~29 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.580 ns) + CELL(0.403 ns) 9.111 ns Add9~30 8 COMB LAB_X26_Y5 2 " "Info: 8: + IC(0.580 ns) + CELL(0.403 ns) = 9.111 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~30'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.983 ns" { Add8~29 Add9~30 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.102 ns) + CELL(0.041 ns) 9.254 ns Add9~34 9 COMB LAB_X26_Y5 2 " "Info: 9: + IC(0.102 ns) + CELL(0.041 ns) = 9.254 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~34'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { Add9~30 Add9~34 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 9.295 ns Add9~38 10 COMB LAB_X26_Y5 2 " "Info: 10: + IC(0.000 ns) + CELL(0.041 ns) = 9.295 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~38'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add9~34 Add9~38 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 9.336 ns Add9~42 11 COMB LAB_X26_Y5 2 " "Info: 11: + IC(0.000 ns) + CELL(0.041 ns) = 9.336 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~42'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add9~38 Add9~42 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 9.377 ns Add9~46 12 COMB LAB_X26_Y5 2 " "Info: 12: + IC(0.000 ns) + CELL(0.041 ns) = 9.377 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~46'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add9~42 Add9~46 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 9.418 ns Add9~50 13 COMB LAB_X26_Y5 2 " "Info: 13: + IC(0.000 ns) + CELL(0.041 ns) = 9.418 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~50'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add9~46 Add9~50 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 9.459 ns Add9~54 14 COMB LAB_X26_Y5 2 " "Info: 14: + IC(0.000 ns) + CELL(0.041 ns) = 9.459 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~54'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add9~50 Add9~54 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.041 ns) 9.500 ns Add9~58 15 COMB LAB_X26_Y5 1 " "Info: 15: + IC(0.000 ns) + CELL(0.041 ns) = 9.500 ns; Loc. = LAB_X26_Y5; Fanout = 1; COMB Node = 'Add9~58'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.041 ns" { Add9~54 Add9~58 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.144 ns) 9.644 ns Add9~61 16 COMB LAB_X26_Y5 2 " "Info: 16: + IC(0.000 ns) + CELL(0.144 ns) = 9.644 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~61'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "0.144 ns" { Add9~58 Add9~61 } "NODE_NAME" } } { "synopsys/ieee/syn_arit.vhd" "" { Text "c:/altera/quartus/libraries/vhdl/synopsys/ieee/syn_arit.vhd" 845 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.102 ns) + CELL(0.178 ns) 10.924 ns resultado\[15\] 17 REG LAB_X23_Y7 4 " "Info: 17: + IC(1.102 ns) + CELL(0.178 ns) = 10.924 ns; Loc. = LAB_X23_Y7; Fanout = 4; REG Node = 'resultado\[15\]'" { } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "1.280 ns" { Add9~61 resultado[15] } "NODE_NAME" } } { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 98 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.252 ns ( 48.08 % ) " "Info: Total cell delay = 5.252 ns ( 48.08 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.672 ns ( 51.92 % ) " "Info: Total interconnect delay = 5.672 ns ( 51.92 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus/bin/TimingClosureFloorplan.fld" "" "10.924 ns" { altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7~porta_address_reg4 altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7 fx~23 Add2~37 Add3~33 Add4~37 Add8~29 Add9~30 Add9~34 Add9~38 Add9~42 Add9~46 Add9~50 Add9~54 Add9~58 Add9~61 resultado[15] } "NODE_NAME" } } } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "2 X13_Y0 X26_Y13 " "Info: Peak interconnect usage is 2% of the available device resources in the region that extends from location X13_Y0 to location X26_Y13" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Info: Fitter routing operations ending: elapsed time is 00:00:02" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1} +{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1} +{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "96 " "Warning: Found 96 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[0\] 0 " "Info: Pin \"fxx_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[1\] 0 " "Info: Pin \"fxx_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[2\] 0 " "Info: Pin \"fxx_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[3\] 0 " "Info: Pin \"fxx_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[4\] 0 " "Info: Pin \"fxx_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[5\] 0 " "Info: Pin \"fxx_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[6\] 0 " "Info: Pin \"fxx_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[7\] 0 " "Info: Pin \"fxx_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[8\] 0 " "Info: Pin \"fxx_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[9\] 0 " "Info: Pin \"fxx_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[10\] 0 " "Info: Pin \"fxx_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[11\] 0 " "Info: Pin \"fxx_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[12\] 0 " "Info: Pin \"fxx_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[13\] 0 " "Info: Pin \"fxx_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[14\] 0 " "Info: Pin \"fxx_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx_o\[15\] 0 " "Info: Pin \"fxx_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[0\] 0 " "Info: Pin \"fxx1_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[1\] 0 " "Info: Pin \"fxx1_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[2\] 0 " "Info: Pin \"fxx1_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[3\] 0 " "Info: Pin \"fxx1_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[4\] 0 " "Info: Pin \"fxx1_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[5\] 0 " "Info: Pin \"fxx1_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[6\] 0 " "Info: Pin \"fxx1_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[7\] 0 " "Info: Pin \"fxx1_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[8\] 0 " "Info: Pin \"fxx1_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[9\] 0 " "Info: Pin \"fxx1_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[10\] 0 " "Info: Pin \"fxx1_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[11\] 0 " "Info: Pin \"fxx1_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[12\] 0 " "Info: Pin \"fxx1_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[13\] 0 " "Info: Pin \"fxx1_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[14\] 0 " "Info: Pin \"fxx1_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx1_o\[15\] 0 " "Info: Pin \"fxx1_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[0\] 0 " "Info: Pin \"fxx2_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[1\] 0 " "Info: Pin \"fxx2_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[2\] 0 " "Info: Pin \"fxx2_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[3\] 0 " "Info: Pin \"fxx2_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[4\] 0 " "Info: Pin \"fxx2_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[5\] 0 " "Info: Pin \"fxx2_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[6\] 0 " "Info: Pin \"fxx2_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[7\] 0 " "Info: Pin \"fxx2_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[8\] 0 " "Info: Pin \"fxx2_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[9\] 0 " "Info: Pin \"fxx2_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[10\] 0 " "Info: Pin \"fxx2_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[11\] 0 " "Info: Pin \"fxx2_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[12\] 0 " "Info: Pin \"fxx2_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[13\] 0 " "Info: Pin \"fxx2_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[14\] 0 " "Info: Pin \"fxx2_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx2_o\[15\] 0 " "Info: Pin \"fxx2_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[0\] 0 " "Info: Pin \"fxx3_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[1\] 0 " "Info: Pin \"fxx3_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[2\] 0 " "Info: Pin \"fxx3_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[3\] 0 " "Info: Pin \"fxx3_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[4\] 0 " "Info: Pin \"fxx3_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[5\] 0 " "Info: Pin \"fxx3_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[6\] 0 " "Info: Pin \"fxx3_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[7\] 0 " "Info: Pin \"fxx3_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[8\] 0 " "Info: Pin \"fxx3_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[9\] 0 " "Info: Pin \"fxx3_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[10\] 0 " "Info: Pin \"fxx3_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[11\] 0 " "Info: Pin \"fxx3_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[12\] 0 " "Info: Pin \"fxx3_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[13\] 0 " "Info: Pin \"fxx3_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[14\] 0 " "Info: Pin \"fxx3_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx3_o\[15\] 0 " "Info: Pin \"fxx3_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[0\] 0 " "Info: Pin \"fxx4_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[1\] 0 " "Info: Pin \"fxx4_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[2\] 0 " "Info: Pin \"fxx4_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[3\] 0 " "Info: Pin \"fxx4_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[4\] 0 " "Info: Pin \"fxx4_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[5\] 0 " "Info: Pin \"fxx4_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[6\] 0 " "Info: Pin \"fxx4_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[7\] 0 " "Info: Pin \"fxx4_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[8\] 0 " "Info: Pin \"fxx4_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[9\] 0 " "Info: Pin \"fxx4_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[10\] 0 " "Info: Pin \"fxx4_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[11\] 0 " "Info: Pin \"fxx4_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[12\] 0 " "Info: Pin \"fxx4_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[13\] 0 " "Info: Pin \"fxx4_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[14\] 0 " "Info: Pin \"fxx4_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "fxx4_o\[15\] 0 " "Info: Pin \"fxx4_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[0\] 0 " "Info: Pin \"resul_o\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[1\] 0 " "Info: Pin \"resul_o\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[2\] 0 " "Info: Pin \"resul_o\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[3\] 0 " "Info: Pin \"resul_o\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[4\] 0 " "Info: Pin \"resul_o\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[5\] 0 " "Info: Pin \"resul_o\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[6\] 0 " "Info: Pin \"resul_o\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[7\] 0 " "Info: Pin \"resul_o\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[8\] 0 " "Info: Pin \"resul_o\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[9\] 0 " "Info: Pin \"resul_o\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[10\] 0 " "Info: Pin \"resul_o\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[11\] 0 " "Info: Pin \"resul_o\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[12\] 0 " "Info: Pin \"resul_o\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[13\] 0 " "Info: Pin \"resul_o\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[14\] 0 " "Info: Pin \"resul_o\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "resul_o\[15\] 0 " "Info: Pin \"resul_o\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1} Index: trunk/QuartusII/db/gnextrapolator.map.logdb =================================================================== --- trunk/QuartusII/db/gnextrapolator.map.logdb (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.map.logdb (revision 5) @@ -0,0 +1 @@ +v1 Index: trunk/QuartusII/db/gnextrapolator.map.ecobp =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.map.ecobp =================================================================== --- trunk/QuartusII/db/gnextrapolator.map.ecobp (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.map.ecobp (revision 5)
trunk/QuartusII/db/gnextrapolator.map.ecobp Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.map.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.map.cdb =================================================================== --- trunk/QuartusII/db/gnextrapolator.map.cdb (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.map.cdb (revision 5)
trunk/QuartusII/db/gnextrapolator.map.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.cmp.logdb =================================================================== --- trunk/QuartusII/db/gnextrapolator.cmp.logdb (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.cmp.logdb (revision 5) @@ -0,0 +1,165 @@ +v1 +RAM_PACKING,0,M512,18,18,SimpleDual,0,3,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0, +RAM_PACKING,0,M512,18,18,SimpleDual,0,2,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a1, +RAM_PACKING,0,M512,18,18,SimpleDual,0,8,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a2, +RAM_PACKING,0,M512,18,18,SimpleDual,0,16,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a3, +RAM_PACKING,0,M512,18,18,SimpleDual,0,9,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a4, +RAM_PACKING,0,M512,18,18,SimpleDual,0,10,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a5, +RAM_PACKING,0,M512,18,18,SimpleDual,0,13,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a6, +RAM_PACKING,0,M512,18,18,SimpleDual,0,4,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7, +RAM_PACKING,0,M512,18,18,SimpleDual,0,1,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a8, +RAM_PACKING,0,M512,18,18,SimpleDual,0,11,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a9, +RAM_PACKING,0,M512,18,18,SimpleDual,0,17,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a10, +RAM_PACKING,0,M512,18,18,SimpleDual,0,7,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a11, +RAM_PACKING,0,M512,18,18,SimpleDual,0,14,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a12, +RAM_PACKING,0,M512,18,18,SimpleDual,0,6,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a13, +RAM_PACKING,0,M512,18,18,SimpleDual,0,12,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a14, +RAM_PACKING,0,M512,18,18,SimpleDual,0,0,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a15, +IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, +IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,, +IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,, +IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,, +IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,, +IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,, +IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No PCI I/O assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,No Termination assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No PCI I/O assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,, +IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,, +IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,INAPPLICABLE,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,No Termination assignments found.,,I/O,, +IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength or Termination assignments found.,,I/O,, +IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,, +IO_RULES,IO_REG_AND_SERDES_NOT_USED_AT_SAME_XY_LOC,INAPPLICABLE,IO_000032,I/O Properties Checks for Multiple I/Os,I/O registers and SERDES should not be used at the same XY location.,Critical,No I/O Registers or Differential I/O Standard assignments found.,,I/O,, +IO_RULES,CURRENT_DENSITY_FOR_CONSECUTIVE_IO_NOT_EXCEED_CURRENT_VALUE,PASS,IO_000033,Electromigration Checks,Current density for consecutive I/Os should not exceed 250mA for row I/Os and 250mA for column I/Os.,Critical,0 such failures found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 1 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,SINGLE_ENDED_IO_AND_DIFF_IO_NOT_COEXIST_IN_PLL_OUTPUT_IO_BANK,INAPPLICABLE,IO_000037,SI Related Distance Checks,Single-ended I/O and differential I/O should not coexist in a PLL output I/O bank.,High,No Differential I/O Standard assignments found.,,I/O,, +IO_RULES,SINGLE_ENDED_OUTPUTS_AND_LVDS_NOT_COEXIST_IN_IO_BANK,INAPPLICABLE,IO_000038,SI Related SSO Limit Checks,Single-ended outputs and High-speed LVDS should not coexist in an I/O bank.,High,No High-speed LVDS found.,,I/O,, +IO_RULES,MAX_20_OUTPUTS_ALLOWED_IN_VREFGROUP,INAPPLICABLE,IO_000042,SI Related SSO Limit Checks,No more than 20 outputs are allowed in a VREF group when VREF is being read from.,High,No VREF I/O Standard assignments found.,,I/O,, +IO_RULES,TOTAL_DRIVE_STRENGTH_FOR_SINGLE_ENDED_OUTPUTS_IN_DPA_NOT_EXCEED_CURRENT_VALUE,INAPPLICABLE,IO_000040,SI Related SSO Limit Checks,The total drive strength of single ended outputs in a DPA bank should not exceed 120mA.,High,No DPA found.,,I/O,, +IO_RULES_MATRIX,Pin/Rules,IO_000001;IO_000002;IO_000003;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000009;IO_000010;IO_000011;IO_000012;IO_000013;IO_000014;IO_000015;IO_000018;IO_000019;IO_000020;IO_000021;IO_000022;IO_000023;IO_000024;IO_000026;IO_000027;IO_000032;IO_000033;IO_000034;IO_000037;IO_000038;IO_000042;IO_000040, +IO_RULES_MATRIX,Total Pass,0;0;0;0;0;107;0;0;107;107;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;107;0;0;0;0;0, +IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,Total Inapplicable,107;107;107;107;107;0;107;107;0;0;107;107;107;107;107;107;107;107;107;107;107;107;107;107;107;0;107;107;107;107;107, +IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0, +IO_RULES_MATRIX,fxx_o[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx_o[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx_o[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx_o[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx_o[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx_o[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx_o[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx_o[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx_o[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx_o[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx_o[10],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx_o[11],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx_o[12],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx_o[13],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx_o[14],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx_o[15],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx1_o[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx1_o[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx1_o[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx1_o[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx1_o[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx1_o[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx1_o[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx1_o[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx1_o[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx1_o[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx1_o[10],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx1_o[11],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx1_o[12],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx1_o[13],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx1_o[14],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx1_o[15],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx2_o[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx2_o[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx2_o[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx2_o[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx2_o[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx2_o[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx2_o[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx2_o[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx2_o[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx2_o[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx2_o[10],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx2_o[11],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx2_o[12],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx2_o[13],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx2_o[14],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx2_o[15],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx3_o[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx3_o[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx3_o[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx3_o[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx3_o[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx3_o[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx3_o[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx3_o[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx3_o[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx3_o[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx3_o[10],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx3_o[11],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx3_o[12],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx3_o[13],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx3_o[14],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx3_o[15],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx4_o[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx4_o[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx4_o[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx4_o[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx4_o[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx4_o[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx4_o[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx4_o[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx4_o[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx4_o[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx4_o[10],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx4_o[11],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx4_o[12],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx4_o[13],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx4_o[14],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,fxx4_o[15],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,resul_o[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,resul_o[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,resul_o[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,resul_o[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,resul_o[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,resul_o[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,resul_o[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,resul_o[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,resul_o[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,resul_o[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,resul_o[10],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,resul_o[11],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,resul_o[12],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,resul_o[13],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,resul_o[14],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,resul_o[15],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,extrapolar_i,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,clk_i,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,rst_i,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,distancia_i[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,distancia_i[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,distancia_i[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,distancia_i[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,distancia_i[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,distancia_i[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,distancia_i[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_MATRIX,distancia_i[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Pass;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable, +IO_RULES_SUMMARY,Total I/O Rules,31, +IO_RULES_SUMMARY,Number of I/O Rules Passed,4, +IO_RULES_SUMMARY,Number of I/O Rules Failed,0, +IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0, +IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,27, Index: trunk/QuartusII/db/gnextrapolator.cmp.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.cmp.cdb =================================================================== --- trunk/QuartusII/db/gnextrapolator.cmp.cdb (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.cmp.cdb (revision 5)
trunk/QuartusII/db/gnextrapolator.cmp.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.cmp.ecobp =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.cmp.ecobp =================================================================== --- trunk/QuartusII/db/gnextrapolator.cmp.ecobp (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.cmp.ecobp (revision 5)
trunk/QuartusII/db/gnextrapolator.cmp.ecobp Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.rtlv_sg.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.rtlv_sg.cdb =================================================================== --- trunk/QuartusII/db/gnextrapolator.rtlv_sg.cdb (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.rtlv_sg.cdb (revision 5)
trunk/QuartusII/db/gnextrapolator.rtlv_sg.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.map.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.map.hdb =================================================================== --- trunk/QuartusII/db/gnextrapolator.map.hdb (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.map.hdb (revision 5)
trunk/QuartusII/db/gnextrapolator.map.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.sld_design_entry.sci =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.sld_design_entry.sci =================================================================== --- trunk/QuartusII/db/gnextrapolator.sld_design_entry.sci (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.sld_design_entry.sci (revision 5)
trunk/QuartusII/db/gnextrapolator.sld_design_entry.sci Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.pre_map.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.pre_map.cdb =================================================================== --- trunk/QuartusII/db/gnextrapolator.pre_map.cdb (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.pre_map.cdb (revision 5)
trunk/QuartusII/db/gnextrapolator.pre_map.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.cmp.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.cmp.hdb =================================================================== --- trunk/QuartusII/db/gnextrapolator.cmp.hdb (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.cmp.hdb (revision 5)
trunk/QuartusII/db/gnextrapolator.cmp.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.(0).cnf.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.(0).cnf.cdb =================================================================== --- trunk/QuartusII/db/gnextrapolator.(0).cnf.cdb (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.(0).cnf.cdb (revision 5)
trunk/QuartusII/db/gnextrapolator.(0).cnf.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/prev_cmp_gnextrapolator.map.qmsg =================================================================== --- trunk/QuartusII/db/prev_cmp_gnextrapolator.map.qmsg (nonexistent) +++ trunk/QuartusII/db/prev_cmp_gnextrapolator.map.qmsg (revision 5) @@ -0,0 +1,13 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 14 00:26:16 2012 " "Info: Processing started: Tue Aug 14 00:26:16 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolator " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolator" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gnextrapolator.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file gnextrapolator.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 gnextrapolator-grenew " "Info: Found design unit 1: gnextrapolator-grenew" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 66 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 gnextrapolator " "Info: Found entity 1: gnextrapolator" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 48 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_TOP" "gnextrapolator " "Info: Elaborating entity \"gnextrapolator\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} +{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "ram gnextrapolator.vhd(76) " "Warning (10541): VHDL Signal Declaration warning at gnextrapolator.vhd(76): used implicit default value for signal \"ram\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 76 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1} +{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_ALTSYNCRAM_INFERRED" "ram~0 " "Info: Inferred altsyncram megafunction from the following design logic: \"ram~0\" " { { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE ROM " "Info: Parameter OPERATION_MODE set to ROM" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 16 " "Info: Parameter WIDTH_A set to 16" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 5 " "Info: Parameter WIDTHAD_A set to 5" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 32 " "Info: Parameter NUMWORDS_A set to 32" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_A UNREGISTERED " "Info: Parameter OUTDATA_REG_A set to UNREGISTERED" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Info: Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_A NONE " "Info: Parameter OUTDATA_ACLR_A set to NONE" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Info: Parameter INDATA_ACLR_A set to NONE" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Info: Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "RAM_BLOCK_TYPE M512 " "Info: Parameter RAM_BLOCK_TYPE set to M512" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "INIT_FILE gnextrapolator.mif " "Info: Parameter INIT_FILE set to gnextrapolator.mif" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} } { { "gnextrapolator.vhd" "ram~0" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 76 -1 0 } } } 0 0 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "" 0 -1} } { } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0 "" 0 -1} +{ "Info" "ISGN_ELABORATION_HEADER" "altsyncram:ram_rtl_0 " "Info: Elaborated megafunction instantiation \"altsyncram:ram_rtl_0\"" { } { } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "altsyncram:ram_rtl_0 " "Info: Instantiated megafunction \"altsyncram:ram_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE ROM " "Info: Parameter \"OPERATION_MODE\" = \"ROM\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 16 " "Info: Parameter \"WIDTH_A\" = \"16\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 5 " "Info: Parameter \"WIDTHAD_A\" = \"5\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 32 " "Info: Parameter \"NUMWORDS_A\" = \"32\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_A UNREGISTERED " "Info: Parameter \"OUTDATA_REG_A\" = \"UNREGISTERED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Info: Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_A NONE " "Info: Parameter \"OUTDATA_ACLR_A\" = \"NONE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Info: Parameter \"INDATA_ACLR_A\" = \"NONE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Info: Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "RAM_BLOCK_TYPE M512 " "Info: Parameter \"RAM_BLOCK_TYPE\" = \"M512\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INIT_FILE gnextrapolator.mif " "Info: Parameter \"INIT_FILE\" = \"gnextrapolator.mif\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_uv61.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_uv61.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_uv61 " "Info: Found entity 1: altsyncram_uv61" { } { { "db/altsyncram_uv61.tdf" "" { Text "C:/Altera/qdesigns/gnextrapolator/db/altsyncram_uv61.tdf" 27 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "120 120 " "Info: 120 registers lost all their fanouts during netlist optimizations. The first 120 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[15\] " "Info: Register \"nabla4fx\[2\]\[15\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[14\] " "Info: Register \"nabla4fx\[2\]\[14\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[13\] " "Info: Register \"nabla4fx\[2\]\[13\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[12\] " "Info: Register \"nabla4fx\[2\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[11\] " "Info: Register \"nabla4fx\[2\]\[11\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[10\] " "Info: Register \"nabla4fx\[2\]\[10\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[9\] " "Info: Register \"nabla4fx\[2\]\[9\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[8\] " "Info: Register \"nabla4fx\[2\]\[8\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[7\] " "Info: Register \"nabla4fx\[2\]\[7\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[6\] " "Info: Register \"nabla4fx\[2\]\[6\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[5\] " "Info: Register \"nabla4fx\[2\]\[5\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[4\] " "Info: Register \"nabla4fx\[2\]\[4\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[3\] " "Info: Register \"nabla4fx\[2\]\[3\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[2\] " "Info: Register \"nabla4fx\[2\]\[2\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[1\] " "Info: Register \"nabla4fx\[2\]\[1\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[0\] " "Info: Register \"nabla4fx\[2\]\[0\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[0\] " "Info: Register \"nabla1fx\[1\]\[0\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[1\] " "Info: Register \"nabla1fx\[1\]\[1\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[2\] " "Info: Register \"nabla1fx\[1\]\[2\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[3\] " "Info: Register \"nabla1fx\[1\]\[3\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[4\] " "Info: Register \"nabla1fx\[1\]\[4\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[5\] " "Info: Register \"nabla1fx\[1\]\[5\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[6\] " "Info: Register \"nabla1fx\[1\]\[6\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[7\] " "Info: Register \"nabla1fx\[1\]\[7\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[8\] " "Info: Register \"nabla1fx\[1\]\[8\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[9\] " "Info: Register \"nabla1fx\[1\]\[9\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[10\] " "Info: Register \"nabla1fx\[1\]\[10\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[11\] " "Info: Register \"nabla1fx\[1\]\[11\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[12\] " "Info: Register \"nabla1fx\[1\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[13\] " "Info: Register \"nabla1fx\[1\]\[13\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[14\] " "Info: Register \"nabla1fx\[1\]\[14\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[15\] " "Info: Register \"nabla1fx\[1\]\[15\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[0\] " "Info: Register \"nabla2fx\[1\]\[0\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[1\] " "Info: Register \"nabla2fx\[1\]\[1\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[2\] " "Info: Register \"nabla2fx\[1\]\[2\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[3\] " "Info: Register \"nabla2fx\[1\]\[3\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[4\] " "Info: Register \"nabla2fx\[1\]\[4\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[5\] " "Info: Register \"nabla2fx\[1\]\[5\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[6\] " "Info: Register \"nabla2fx\[1\]\[6\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[7\] " "Info: Register \"nabla2fx\[1\]\[7\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[8\] " "Info: Register \"nabla2fx\[1\]\[8\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[9\] " "Info: Register \"nabla2fx\[1\]\[9\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[10\] " "Info: Register \"nabla2fx\[1\]\[10\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[11\] " "Info: Register \"nabla2fx\[1\]\[11\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[12\] " "Info: Register \"nabla2fx\[1\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[13\] " "Info: Register \"nabla2fx\[1\]\[13\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[14\] " "Info: Register \"nabla2fx\[1\]\[14\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[15\] " "Info: Register \"nabla2fx\[1\]\[15\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[0\] " "Info: Register \"nabla3fx\[1\]\[0\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[1\] " "Info: Register \"nabla3fx\[1\]\[1\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[2\] " "Info: Register \"nabla3fx\[1\]\[2\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[3\] " "Info: Register \"nabla3fx\[1\]\[3\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[4\] " "Info: Register \"nabla3fx\[1\]\[4\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[5\] " "Info: Register \"nabla3fx\[1\]\[5\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[6\] " "Info: Register \"nabla3fx\[1\]\[6\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[7\] " "Info: Register \"nabla3fx\[1\]\[7\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[8\] " "Info: Register \"nabla3fx\[1\]\[8\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[9\] " "Info: Register \"nabla3fx\[1\]\[9\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[10\] " "Info: Register \"nabla3fx\[1\]\[10\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[11\] " "Info: Register \"nabla3fx\[1\]\[11\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[12\] " "Info: Register \"nabla3fx\[1\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[13\] " "Info: Register \"nabla3fx\[1\]\[13\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[14\] " "Info: Register \"nabla3fx\[1\]\[14\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[15\] " "Info: Register \"nabla3fx\[1\]\[15\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[0\] " "Info: Register \"nabla4fx\[1\]\[0\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[1\] " "Info: Register \"nabla4fx\[1\]\[1\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[2\] " "Info: Register \"nabla4fx\[1\]\[2\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[3\] " "Info: Register \"nabla4fx\[1\]\[3\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[4\] " "Info: Register \"nabla4fx\[1\]\[4\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[5\] " "Info: Register \"nabla4fx\[1\]\[5\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[6\] " "Info: Register \"nabla4fx\[1\]\[6\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[7\] " "Info: Register \"nabla4fx\[1\]\[7\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[8\] " "Info: Register \"nabla4fx\[1\]\[8\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[9\] " "Info: Register \"nabla4fx\[1\]\[9\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[10\] " "Info: Register \"nabla4fx\[1\]\[10\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[11\] " "Info: Register \"nabla4fx\[1\]\[11\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[12\] " "Info: Register \"nabla4fx\[1\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[13\] " "Info: Register \"nabla4fx\[1\]\[13\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[14\] " "Info: Register \"nabla4fx\[1\]\[14\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[15\] " "Info: Register \"nabla4fx\[1\]\[15\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[0\] " "Info: Register \"nabla4fx\[0\]\[0\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[1\] " "Info: Register \"nabla4fx\[0\]\[1\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[2\] " "Info: Register \"nabla4fx\[0\]\[2\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[3\] " "Info: Register \"nabla4fx\[0\]\[3\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[4\] " "Info: Register \"nabla4fx\[0\]\[4\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[5\] " "Info: Register \"nabla4fx\[0\]\[5\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[6\] " "Info: Register \"nabla4fx\[0\]\[6\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[7\] " "Info: Register \"nabla4fx\[0\]\[7\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[8\] " "Info: Register \"nabla4fx\[0\]\[8\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[9\] " "Info: Register \"nabla4fx\[0\]\[9\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[10\] " "Info: Register \"nabla4fx\[0\]\[10\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[11\] " "Info: Register \"nabla4fx\[0\]\[11\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[12\] " "Info: Register \"nabla4fx\[0\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[13\] " "Info: Register \"nabla4fx\[0\]\[13\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[14\] " "Info: Register \"nabla4fx\[0\]\[14\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[15\] " "Info: Register \"nabla4fx\[0\]\[15\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[0\] " "Info: Register \"fx\[1\]\[0\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[1\] " "Info: Register \"fx\[1\]\[1\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[2\] " "Info: Register \"fx\[1\]\[2\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[3\] " "Info: Register \"fx\[1\]\[3\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[4\] " "Info: Register \"fx\[1\]\[4\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[5\] " "Info: Register \"fx\[1\]\[5\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[6\] " "Info: Register \"fx\[1\]\[6\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[7\] " "Info: Register \"fx\[1\]\[7\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[8\] " "Info: Register \"fx\[1\]\[8\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[9\] " "Info: Register \"fx\[1\]\[9\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[10\] " "Info: Register \"fx\[1\]\[10\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[11\] " "Info: Register \"fx\[1\]\[11\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[12\] " "Info: Register \"fx\[1\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[13\] " "Info: Register \"fx\[1\]\[13\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[14\] " "Info: Register \"fx\[1\]\[14\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[15\] " "Info: Register \"fx\[1\]\[15\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "cont\[15\] " "Info: Register \"cont\[15\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "cont\[14\] " "Info: Register \"cont\[14\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "cont\[13\] " "Info: Register \"cont\[13\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "cont\[12\] " "Info: Register \"cont\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "cont\[11\] " "Info: Register \"cont\[11\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "cont\[10\] " "Info: Register \"cont\[10\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "cont\[9\] " "Info: Register \"cont\[9\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "cont\[8\] " "Info: Register \"cont\[8\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} } { } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 -1} +{ "Info" "ICUT_CUT_TM_SUMMARY" "476 " "Info: Implemented 476 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Info: Implemented 11 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "96 " "Info: Implemented 96 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "353 " "Info: Implemented 353 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_RAMS" "16 " "Info: Implemented 16 RAM segments" { } { } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "194 " "Info: Peak virtual memory: 194 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 14 00:26:26 2012 " "Info: Processing ended: Tue Aug 14 00:26:26 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Info: Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} Index: trunk/QuartusII/db/gnextrapolator.(2).cnf.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.(2).cnf.cdb =================================================================== --- trunk/QuartusII/db/gnextrapolator.(2).cnf.cdb (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.(2).cnf.cdb (revision 5)
trunk/QuartusII/db/gnextrapolator.(2).cnf.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.pre_map.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.pre_map.hdb =================================================================== --- trunk/QuartusII/db/gnextrapolator.pre_map.hdb (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.pre_map.hdb (revision 5)
trunk/QuartusII/db/gnextrapolator.pre_map.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.(0).cnf.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.(0).cnf.hdb =================================================================== --- trunk/QuartusII/db/gnextrapolator.(0).cnf.hdb (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.(0).cnf.hdb (revision 5)
trunk/QuartusII/db/gnextrapolator.(0).cnf.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.fnsim.qmsg =================================================================== --- trunk/QuartusII/db/gnextrapolator.fnsim.qmsg (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.fnsim.qmsg (revision 5) @@ -0,0 +1,13 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon Aug 13 23:49:31 2012 " "Info: Processing started: Mon Aug 13 23:49:31 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolator --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolator --generate_functional_sim_netlist" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gnextrapolator.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file gnextrapolator.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 gnextrapolator-grenew " "Info: Found design unit 1: gnextrapolator-grenew" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 66 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 gnextrapolator " "Info: Found entity 1: gnextrapolator" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 48 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_TOP" "gnextrapolator " "Info: Elaborating entity \"gnextrapolator\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} +{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "ram gnextrapolator.vhd(76) " "Warning (10541): VHDL Signal Declaration warning at gnextrapolator.vhd(76): used implicit default value for signal \"ram\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 76 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1} +{ "Info" "ILPMS_INFERENCING_SUMMARY" "126 " "Info: Inferred 126 megafunctions from design logic" { { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux0 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux0\"" { } { { "gnextrapolator.vhd" "Mux0" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux1 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux1\"" { } { { "gnextrapolator.vhd" "Mux1" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux2 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux2\"" { } { { "gnextrapolator.vhd" "Mux2" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux3 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux3\"" { } { { "gnextrapolator.vhd" "Mux3" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux4 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux4\"" { } { { "gnextrapolator.vhd" "Mux4" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux5 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux5\"" { } { { "gnextrapolator.vhd" "Mux5" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux6 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux6\"" { } { { "gnextrapolator.vhd" "Mux6" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux7 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux7\"" { } { { "gnextrapolator.vhd" "Mux7" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux8 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux8\"" { } { { "gnextrapolator.vhd" "Mux8" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux9 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux9\"" { } { { "gnextrapolator.vhd" "Mux9" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux10 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux10\"" { } { { "gnextrapolator.vhd" "Mux10" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux11 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux11\"" { } { { "gnextrapolator.vhd" "Mux11" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux12 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux12\"" { } { { "gnextrapolator.vhd" "Mux12" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux13 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux13\"" { } { { "gnextrapolator.vhd" "Mux13" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux16 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux16\"" { } { { "gnextrapolator.vhd" "Mux16" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 120 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux17 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux17\"" { } { { "gnextrapolator.vhd" "Mux17" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 120 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux18 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux18\"" { } { { "gnextrapolator.vhd" "Mux18" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 120 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux19 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux19\"" { } { { "gnextrapolator.vhd" "Mux19" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 120 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux20 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux20\"" { } { { "gnextrapolator.vhd" "Mux20" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 120 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux21 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux21\"" { } { { "gnextrapolator.vhd" "Mux21" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 120 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux22 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux22\"" { } { { "gnextrapolator.vhd" "Mux22" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 120 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux23 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux23\"" { } { { "gnextrapolator.vhd" "Mux23" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 120 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux24 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux24\"" { } { { "gnextrapolator.vhd" "Mux24" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 120 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux25 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux25\"" { } { { "gnextrapolator.vhd" "Mux25" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 120 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux26 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux26\"" { } { { "gnextrapolator.vhd" "Mux26" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 120 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux27 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux27\"" { } { { "gnextrapolator.vhd" "Mux27" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 120 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux28 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux28\"" { } { { "gnextrapolator.vhd" "Mux28" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 120 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux29 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux29\"" { } { { "gnextrapolator.vhd" "Mux29" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 120 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux36 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux36\"" { } { { "gnextrapolator.vhd" "Mux36" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 121 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux37 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux37\"" { } { { "gnextrapolator.vhd" "Mux37" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 121 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux38 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux38\"" { } { { "gnextrapolator.vhd" "Mux38" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 121 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux39 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux39\"" { } { { "gnextrapolator.vhd" "Mux39" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 121 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux40 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux40\"" { } { { "gnextrapolator.vhd" "Mux40" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 121 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux41 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux41\"" { } { { "gnextrapolator.vhd" "Mux41" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 121 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux42 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux42\"" { } { { "gnextrapolator.vhd" "Mux42" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 121 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux43 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux43\"" { } { { "gnextrapolator.vhd" "Mux43" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 121 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux44 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux44\"" { } { { "gnextrapolator.vhd" "Mux44" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 121 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux45 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux45\"" { } { { "gnextrapolator.vhd" "Mux45" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 121 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux46 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux46\"" { } { { "gnextrapolator.vhd" "Mux46" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 121 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux47 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux47\"" { } { { "gnextrapolator.vhd" "Mux47" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 121 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux48 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux48\"" { } { { "gnextrapolator.vhd" "Mux48" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 121 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux49 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux49\"" { } { { "gnextrapolator.vhd" "Mux49" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 121 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux58 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux58\"" { } { { "gnextrapolator.vhd" "Mux58" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 122 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux59 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux59\"" { } { { "gnextrapolator.vhd" "Mux59" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 122 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux60 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux60\"" { } { { "gnextrapolator.vhd" "Mux60" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 122 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux61 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux61\"" { } { { "gnextrapolator.vhd" "Mux61" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 122 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux62 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux62\"" { } { { "gnextrapolator.vhd" "Mux62" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 122 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux63 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux63\"" { } { { "gnextrapolator.vhd" "Mux63" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 122 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux64 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux64\"" { } { { "gnextrapolator.vhd" "Mux64" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 122 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux65 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux65\"" { } { { "gnextrapolator.vhd" "Mux65" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 122 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux66 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux66\"" { } { { "gnextrapolator.vhd" "Mux66" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 122 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux67 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux67\"" { } { { "gnextrapolator.vhd" "Mux67" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 122 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux68 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux68\"" { } { { "gnextrapolator.vhd" "Mux68" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 122 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux69 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux69\"" { } { { "gnextrapolator.vhd" "Mux69" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 122 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux70 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux70\"" { } { { "gnextrapolator.vhd" "Mux70" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 122 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux71 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux71\"" { } { { "gnextrapolator.vhd" "Mux71" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 122 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux77 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux77\"" { } { { "gnextrapolator.vhd" "Mux77" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 126 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux78 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux78\"" { } { { "gnextrapolator.vhd" "Mux78" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 126 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux79 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux79\"" { } { { "gnextrapolator.vhd" "Mux79" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 126 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux80 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux80\"" { } { { "gnextrapolator.vhd" "Mux80" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 126 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux81 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux81\"" { } { { "gnextrapolator.vhd" "Mux81" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 126 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux82 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux82\"" { } { { "gnextrapolator.vhd" "Mux82" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 126 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux83 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux83\"" { } { { "gnextrapolator.vhd" "Mux83" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 126 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux84 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux84\"" { } { { "gnextrapolator.vhd" "Mux84" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 126 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux85 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux85\"" { } { { "gnextrapolator.vhd" "Mux85" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 126 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux86 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux86\"" { } { { "gnextrapolator.vhd" "Mux86" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 126 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux87 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux87\"" { } { { "gnextrapolator.vhd" "Mux87" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 126 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux88 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux88\"" { } { { "gnextrapolator.vhd" "Mux88" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 126 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux89 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux89\"" { } { { "gnextrapolator.vhd" "Mux89" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 126 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux90 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux90\"" { } { { "gnextrapolator.vhd" "Mux90" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 126 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux91 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux91\"" { } { { "gnextrapolator.vhd" "Mux91" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 127 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux92 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux92\"" { } { { "gnextrapolator.vhd" "Mux92" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 127 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux93 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux93\"" { } { { "gnextrapolator.vhd" "Mux93" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 127 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux94 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux94\"" { } { { "gnextrapolator.vhd" "Mux94" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 127 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux95 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux95\"" { } { { "gnextrapolator.vhd" "Mux95" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 127 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux96 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux96\"" { } { { "gnextrapolator.vhd" "Mux96" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 127 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux97 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux97\"" { } { { "gnextrapolator.vhd" "Mux97" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 127 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux98 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux98\"" { } { { "gnextrapolator.vhd" "Mux98" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 127 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux99 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux99\"" { } { { "gnextrapolator.vhd" "Mux99" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 127 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux100 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux100\"" { } { { "gnextrapolator.vhd" "Mux100" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 127 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux101 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux101\"" { } { { "gnextrapolator.vhd" "Mux101" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 127 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux102 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux102\"" { } { { "gnextrapolator.vhd" "Mux102" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 127 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux103 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux103\"" { } { { "gnextrapolator.vhd" "Mux103" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 127 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux104 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux104\"" { } { { "gnextrapolator.vhd" "Mux104" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 127 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux105 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux105\"" { } { { "gnextrapolator.vhd" "Mux105" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 128 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux106 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux106\"" { } { { "gnextrapolator.vhd" "Mux106" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 128 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux107 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux107\"" { } { { "gnextrapolator.vhd" "Mux107" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 128 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux108 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux108\"" { } { { "gnextrapolator.vhd" "Mux108" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 128 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux109 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux109\"" { } { { "gnextrapolator.vhd" "Mux109" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 128 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux110 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux110\"" { } { { "gnextrapolator.vhd" "Mux110" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 128 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux111 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux111\"" { } { { "gnextrapolator.vhd" "Mux111" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 128 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux112 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux112\"" { } { { "gnextrapolator.vhd" "Mux112" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 128 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux113 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux113\"" { } { { "gnextrapolator.vhd" "Mux113" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 128 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux114 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux114\"" { } { { "gnextrapolator.vhd" "Mux114" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 128 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux115 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux115\"" { } { { "gnextrapolator.vhd" "Mux115" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 128 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux116 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux116\"" { } { { "gnextrapolator.vhd" "Mux116" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 128 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux117 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux117\"" { } { { "gnextrapolator.vhd" "Mux117" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 128 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux118 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux118\"" { } { { "gnextrapolator.vhd" "Mux118" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 128 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux119 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux119\"" { } { { "gnextrapolator.vhd" "Mux119" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 129 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux120 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux120\"" { } { { "gnextrapolator.vhd" "Mux120" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 129 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux121 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux121\"" { } { { "gnextrapolator.vhd" "Mux121" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 129 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux122 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux122\"" { } { { "gnextrapolator.vhd" "Mux122" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 129 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux123 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux123\"" { } { { "gnextrapolator.vhd" "Mux123" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 129 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux124 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux124\"" { } { { "gnextrapolator.vhd" "Mux124" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 129 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux125 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux125\"" { } { { "gnextrapolator.vhd" "Mux125" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 129 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux126 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux126\"" { } { { "gnextrapolator.vhd" "Mux126" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 129 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux127 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux127\"" { } { { "gnextrapolator.vhd" "Mux127" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 129 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux128 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux128\"" { } { { "gnextrapolator.vhd" "Mux128" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 129 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux129 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux129\"" { } { { "gnextrapolator.vhd" "Mux129" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 129 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux130 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux130\"" { } { { "gnextrapolator.vhd" "Mux130" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 129 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux131 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux131\"" { } { { "gnextrapolator.vhd" "Mux131" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 129 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux132 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux132\"" { } { { "gnextrapolator.vhd" "Mux132" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 129 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux133 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux133\"" { } { { "gnextrapolator.vhd" "Mux133" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 130 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux134 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux134\"" { } { { "gnextrapolator.vhd" "Mux134" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 130 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux135 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux135\"" { } { { "gnextrapolator.vhd" "Mux135" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 130 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux136 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux136\"" { } { { "gnextrapolator.vhd" "Mux136" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 130 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux137 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux137\"" { } { { "gnextrapolator.vhd" "Mux137" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 130 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux138 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux138\"" { } { { "gnextrapolator.vhd" "Mux138" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 130 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux139 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux139\"" { } { { "gnextrapolator.vhd" "Mux139" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 130 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux140 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux140\"" { } { { "gnextrapolator.vhd" "Mux140" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 130 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux141 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux141\"" { } { { "gnextrapolator.vhd" "Mux141" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 130 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux142 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux142\"" { } { { "gnextrapolator.vhd" "Mux142" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 130 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux143 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux143\"" { } { { "gnextrapolator.vhd" "Mux143" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 130 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux144 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux144\"" { } { { "gnextrapolator.vhd" "Mux144" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 130 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux145 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux145\"" { } { { "gnextrapolator.vhd" "Mux145" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 130 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} { "Info" "ILPMS_LPM_MUX_INFERRED" "Mux146 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"Mux146\"" { } { { "gnextrapolator.vhd" "Mux146" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 130 -1 0 } } } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0 -1} } { } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0 -1} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux0 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux0\"" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mux:Mux0 " "Info: Instantiated megafunction \"lpm_mux:Mux0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 1 " "Info: Parameter \"LPM_WIDTH\" = \"1\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_SIZE 4 " "Info: Parameter \"LPM_SIZE\" = \"4\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 2 " "Info: Parameter \"LPM_WIDTHS\" = \"2\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CASCADE_CHAIN IGNORE " "Info: Parameter \"CASCADE_CHAIN\" = \"IGNORE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 119 -1 0 } } } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_0oc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_0oc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_0oc " "Info: Found entity 1: mux_0oc" { } { { "db/mux_0oc.tdf" "" { Text "C:/Altera/qdesigns/gnextrapolator/db/mux_0oc.tdf" 22 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_ELABORATION_HEADER" "lpm_mux:Mux77 " "Info: Elaborated megafunction instantiation \"lpm_mux:Mux77\"" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 126 -1 0 } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "lpm_mux:Mux77 " "Info: Instantiated megafunction \"lpm_mux:Mux77\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 1 " "Info: Parameter \"LPM_WIDTH\" = \"1\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_SIZE 4 " "Info: Parameter \"LPM_SIZE\" = \"4\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHS 2 " "Info: Parameter \"LPM_WIDTHS\" = \"2\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "CASCADE_CHAIN IGNORE " "Info: Parameter \"CASCADE_CHAIN\" = \"IGNORE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 126 -1 0 } } } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 1 Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "189 " "Info: Peak virtual memory: 189 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 13 23:49:40 2012 " "Info: Processing ended: Mon Aug 13 23:49:40 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:08 " "Info: Total CPU time (on all processors): 00:00:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} Index: trunk/QuartusII/db/gnextrapolator.(2).cnf.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.(2).cnf.hdb =================================================================== --- trunk/QuartusII/db/gnextrapolator.(2).cnf.hdb (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.(2).cnf.hdb (revision 5)
trunk/QuartusII/db/gnextrapolator.(2).cnf.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.map.qmsg =================================================================== --- trunk/QuartusII/db/gnextrapolator.map.qmsg (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.map.qmsg (revision 5) @@ -0,0 +1,13 @@ +{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition " "Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 14 00:26:16 2012 " "Info: Processing started: Tue Aug 14 00:26:16 2012" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolator " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolator" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "gnextrapolator.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file gnextrapolator.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 gnextrapolator-grenew " "Info: Found design unit 1: gnextrapolator-grenew" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 66 -1 0 } } } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0 -1} { "Info" "ISGN_ENTITY_NAME" "1 gnextrapolator " "Info: Found entity 1: gnextrapolator" { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 48 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} +{ "Info" "ISGN_START_ELABORATION_TOP" "gnextrapolator " "Info: Elaborating entity \"gnextrapolator\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1} +{ "Warning" "WVRFX_VHDL_USED_IMPLICIT_DEFAULT_VALUE" "ram gnextrapolator.vhd(76) " "Warning (10541): VHDL Signal Declaration warning at gnextrapolator.vhd(76): used implicit default value for signal \"ram\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." { } { { "gnextrapolator.vhd" "" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 76 0 0 } } } 0 10541 "VHDL Signal Declaration warning at %2!s!: used implicit default value for signal \"%1!s!\" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations." 0 0 "" 0 -1} +{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_ALTSYNCRAM_INFERRED" "ram~0 " "Info: Inferred altsyncram megafunction from the following design logic: \"ram~0\" " { { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE ROM " "Info: Parameter OPERATION_MODE set to ROM" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 16 " "Info: Parameter WIDTH_A set to 16" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 5 " "Info: Parameter WIDTHAD_A set to 5" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 32 " "Info: Parameter NUMWORDS_A set to 32" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_A UNREGISTERED " "Info: Parameter OUTDATA_REG_A set to UNREGISTERED" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Info: Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_A NONE " "Info: Parameter OUTDATA_ACLR_A set to NONE" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Info: Parameter INDATA_ACLR_A set to NONE" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Info: Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "RAM_BLOCK_TYPE M512 " "Info: Parameter RAM_BLOCK_TYPE set to M512" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} { "Info" "IOPT_INFERRED_MEGAFUNCTION_PARAMETER" "INIT_FILE gnextrapolator.mif " "Info: Parameter INIT_FILE set to gnextrapolator.mif" { } { } 0 0 "Parameter %1!s! set to %2!s!" 0 0 "" 0 -1} } { { "gnextrapolator.vhd" "ram~0" { Text "C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd" 76 -1 0 } } } 0 0 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "" 0 -1} } { } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0 "" 0 -1} +{ "Info" "ISGN_ELABORATION_HEADER" "altsyncram:ram_rtl_0 " "Info: Elaborated megafunction instantiation \"altsyncram:ram_rtl_0\"" { } { } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1} +{ "Info" "ISGN_MEGAFN_PARAM_TOP" "altsyncram:ram_rtl_0 " "Info: Instantiated megafunction \"altsyncram:ram_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE ROM " "Info: Parameter \"OPERATION_MODE\" = \"ROM\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 16 " "Info: Parameter \"WIDTH_A\" = \"16\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 5 " "Info: Parameter \"WIDTHAD_A\" = \"5\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 32 " "Info: Parameter \"NUMWORDS_A\" = \"32\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_A UNREGISTERED " "Info: Parameter \"OUTDATA_REG_A\" = \"UNREGISTERED\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Info: Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_A NONE " "Info: Parameter \"OUTDATA_ACLR_A\" = \"NONE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Info: Parameter \"INDATA_ACLR_A\" = \"NONE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Info: Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "RAM_BLOCK_TYPE M512 " "Info: Parameter \"RAM_BLOCK_TYPE\" = \"M512\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INIT_FILE gnextrapolator.mif " "Info: Parameter \"INIT_FILE\" = \"gnextrapolator.mif\"" { } { } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 -1} } { } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 -1} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_uv61.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_uv61.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_uv61 " "Info: Found entity 1: altsyncram_uv61" { } { { "db/altsyncram_uv61.tdf" "" { Text "C:/Altera/qdesigns/gnextrapolator/db/altsyncram_uv61.tdf" 27 1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1} +{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "120 120 " "Info: 120 registers lost all their fanouts during netlist optimizations. The first 120 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[15\] " "Info: Register \"nabla4fx\[2\]\[15\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[14\] " "Info: Register \"nabla4fx\[2\]\[14\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[13\] " "Info: Register \"nabla4fx\[2\]\[13\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[12\] " "Info: Register \"nabla4fx\[2\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[11\] " "Info: Register \"nabla4fx\[2\]\[11\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[10\] " "Info: Register \"nabla4fx\[2\]\[10\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[9\] " "Info: Register \"nabla4fx\[2\]\[9\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[8\] " "Info: Register \"nabla4fx\[2\]\[8\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[7\] " "Info: Register \"nabla4fx\[2\]\[7\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[6\] " "Info: Register \"nabla4fx\[2\]\[6\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[5\] " "Info: Register \"nabla4fx\[2\]\[5\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[4\] " "Info: Register \"nabla4fx\[2\]\[4\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[3\] " "Info: Register \"nabla4fx\[2\]\[3\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[2\] " "Info: Register \"nabla4fx\[2\]\[2\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[1\] " "Info: Register \"nabla4fx\[2\]\[1\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[2\]\[0\] " "Info: Register \"nabla4fx\[2\]\[0\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[0\] " "Info: Register \"nabla1fx\[1\]\[0\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[1\] " "Info: Register \"nabla1fx\[1\]\[1\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[2\] " "Info: Register \"nabla1fx\[1\]\[2\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[3\] " "Info: Register \"nabla1fx\[1\]\[3\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[4\] " "Info: Register \"nabla1fx\[1\]\[4\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[5\] " "Info: Register \"nabla1fx\[1\]\[5\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[6\] " "Info: Register \"nabla1fx\[1\]\[6\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[7\] " "Info: Register \"nabla1fx\[1\]\[7\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[8\] " "Info: Register \"nabla1fx\[1\]\[8\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[9\] " "Info: Register \"nabla1fx\[1\]\[9\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[10\] " "Info: Register \"nabla1fx\[1\]\[10\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[11\] " "Info: Register \"nabla1fx\[1\]\[11\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[12\] " "Info: Register \"nabla1fx\[1\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[13\] " "Info: Register \"nabla1fx\[1\]\[13\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[14\] " "Info: Register \"nabla1fx\[1\]\[14\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla1fx\[1\]\[15\] " "Info: Register \"nabla1fx\[1\]\[15\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[0\] " "Info: Register \"nabla2fx\[1\]\[0\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[1\] " "Info: Register \"nabla2fx\[1\]\[1\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[2\] " "Info: Register \"nabla2fx\[1\]\[2\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[3\] " "Info: Register \"nabla2fx\[1\]\[3\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[4\] " "Info: Register \"nabla2fx\[1\]\[4\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[5\] " "Info: Register \"nabla2fx\[1\]\[5\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[6\] " "Info: Register \"nabla2fx\[1\]\[6\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[7\] " "Info: Register \"nabla2fx\[1\]\[7\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[8\] " "Info: Register \"nabla2fx\[1\]\[8\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[9\] " "Info: Register \"nabla2fx\[1\]\[9\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[10\] " "Info: Register \"nabla2fx\[1\]\[10\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[11\] " "Info: Register \"nabla2fx\[1\]\[11\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[12\] " "Info: Register \"nabla2fx\[1\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[13\] " "Info: Register \"nabla2fx\[1\]\[13\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[14\] " "Info: Register \"nabla2fx\[1\]\[14\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla2fx\[1\]\[15\] " "Info: Register \"nabla2fx\[1\]\[15\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[0\] " "Info: Register \"nabla3fx\[1\]\[0\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[1\] " "Info: Register \"nabla3fx\[1\]\[1\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[2\] " "Info: Register \"nabla3fx\[1\]\[2\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[3\] " "Info: Register \"nabla3fx\[1\]\[3\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[4\] " "Info: Register \"nabla3fx\[1\]\[4\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[5\] " "Info: Register \"nabla3fx\[1\]\[5\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[6\] " "Info: Register \"nabla3fx\[1\]\[6\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[7\] " "Info: Register \"nabla3fx\[1\]\[7\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[8\] " "Info: Register \"nabla3fx\[1\]\[8\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[9\] " "Info: Register \"nabla3fx\[1\]\[9\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[10\] " "Info: Register \"nabla3fx\[1\]\[10\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[11\] " "Info: Register \"nabla3fx\[1\]\[11\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[12\] " "Info: Register \"nabla3fx\[1\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[13\] " "Info: Register \"nabla3fx\[1\]\[13\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[14\] " "Info: Register \"nabla3fx\[1\]\[14\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla3fx\[1\]\[15\] " "Info: Register \"nabla3fx\[1\]\[15\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[0\] " "Info: Register \"nabla4fx\[1\]\[0\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[1\] " "Info: Register \"nabla4fx\[1\]\[1\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[2\] " "Info: Register \"nabla4fx\[1\]\[2\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[3\] " "Info: Register \"nabla4fx\[1\]\[3\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[4\] " "Info: Register \"nabla4fx\[1\]\[4\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[5\] " "Info: Register \"nabla4fx\[1\]\[5\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[6\] " "Info: Register \"nabla4fx\[1\]\[6\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[7\] " "Info: Register \"nabla4fx\[1\]\[7\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[8\] " "Info: Register \"nabla4fx\[1\]\[8\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[9\] " "Info: Register \"nabla4fx\[1\]\[9\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[10\] " "Info: Register \"nabla4fx\[1\]\[10\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[11\] " "Info: Register \"nabla4fx\[1\]\[11\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[12\] " "Info: Register \"nabla4fx\[1\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[13\] " "Info: Register \"nabla4fx\[1\]\[13\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[14\] " "Info: Register \"nabla4fx\[1\]\[14\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[1\]\[15\] " "Info: Register \"nabla4fx\[1\]\[15\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[0\] " "Info: Register \"nabla4fx\[0\]\[0\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[1\] " "Info: Register \"nabla4fx\[0\]\[1\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[2\] " "Info: Register \"nabla4fx\[0\]\[2\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[3\] " "Info: Register \"nabla4fx\[0\]\[3\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[4\] " "Info: Register \"nabla4fx\[0\]\[4\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[5\] " "Info: Register \"nabla4fx\[0\]\[5\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[6\] " "Info: Register \"nabla4fx\[0\]\[6\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[7\] " "Info: Register \"nabla4fx\[0\]\[7\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[8\] " "Info: Register \"nabla4fx\[0\]\[8\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[9\] " "Info: Register \"nabla4fx\[0\]\[9\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[10\] " "Info: Register \"nabla4fx\[0\]\[10\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[11\] " "Info: Register \"nabla4fx\[0\]\[11\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[12\] " "Info: Register \"nabla4fx\[0\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[13\] " "Info: Register \"nabla4fx\[0\]\[13\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[14\] " "Info: Register \"nabla4fx\[0\]\[14\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "nabla4fx\[0\]\[15\] " "Info: Register \"nabla4fx\[0\]\[15\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[0\] " "Info: Register \"fx\[1\]\[0\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[1\] " "Info: Register \"fx\[1\]\[1\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[2\] " "Info: Register \"fx\[1\]\[2\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[3\] " "Info: Register \"fx\[1\]\[3\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[4\] " "Info: Register \"fx\[1\]\[4\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[5\] " "Info: Register \"fx\[1\]\[5\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[6\] " "Info: Register \"fx\[1\]\[6\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[7\] " "Info: Register \"fx\[1\]\[7\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[8\] " "Info: Register \"fx\[1\]\[8\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[9\] " "Info: Register \"fx\[1\]\[9\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[10\] " "Info: Register \"fx\[1\]\[10\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[11\] " "Info: Register \"fx\[1\]\[11\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[12\] " "Info: Register \"fx\[1\]\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[13\] " "Info: Register \"fx\[1\]\[13\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[14\] " "Info: Register \"fx\[1\]\[14\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "fx\[1\]\[15\] " "Info: Register \"fx\[1\]\[15\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "cont\[15\] " "Info: Register \"cont\[15\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "cont\[14\] " "Info: Register \"cont\[14\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "cont\[13\] " "Info: Register \"cont\[13\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "cont\[12\] " "Info: Register \"cont\[12\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "cont\[11\] " "Info: Register \"cont\[11\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "cont\[10\] " "Info: Register \"cont\[10\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "cont\[9\] " "Info: Register \"cont\[9\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "cont\[8\] " "Info: Register \"cont\[8\]\" lost all its fanouts during netlist optimizations." { } { } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0 "" 0 -1} } { } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0 "" 0 -1} +{ "Info" "ICUT_CUT_TM_SUMMARY" "476 " "Info: Implemented 476 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "11 " "Info: Implemented 11 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "96 " "Info: Implemented 96 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "353 " "Info: Implemented 353 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_RAMS" "16 " "Info: Implemented 16 RAM segments" { } { } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1 Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "194 " "Info: Peak virtual memory: 194 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 14 00:26:26 2012 " "Info: Processing ended: Tue Aug 14 00:26:26 2012" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Info: Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1} Index: trunk/QuartusII/db/gnextrapolator.cmp.rdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.cmp.rdb =================================================================== --- trunk/QuartusII/db/gnextrapolator.cmp.rdb (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.cmp.rdb (revision 5)
trunk/QuartusII/db/gnextrapolator.cmp.rdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.tis_db_list.ddb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.tis_db_list.ddb =================================================================== --- trunk/QuartusII/db/gnextrapolator.tis_db_list.ddb (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.tis_db_list.ddb (revision 5)
trunk/QuartusII/db/gnextrapolator.tis_db_list.ddb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.cmp.tdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.cmp.tdb =================================================================== --- trunk/QuartusII/db/gnextrapolator.cmp.tdb (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.cmp.tdb (revision 5)
trunk/QuartusII/db/gnextrapolator.cmp.tdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.map.bpm =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.map.bpm =================================================================== --- trunk/QuartusII/db/gnextrapolator.map.bpm (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.map.bpm (revision 5)
trunk/QuartusII/db/gnextrapolator.map.bpm Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.lpc.txt =================================================================== --- trunk/QuartusII/db/gnextrapolator.lpc.txt (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.lpc.txt (revision 5) @@ -0,0 +1,5 @@ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ Index: trunk/QuartusII/db/gnextrapolator.cmp.bpm =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.cmp.bpm =================================================================== --- trunk/QuartusII/db/gnextrapolator.cmp.bpm (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.cmp.bpm (revision 5)
trunk/QuartusII/db/gnextrapolator.cmp.bpm Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/gnextrapolator.smart_action.txt =================================================================== --- trunk/QuartusII/db/gnextrapolator.smart_action.txt (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.smart_action.txt (revision 5) @@ -0,0 +1 @@ +SOURCE Index: trunk/QuartusII/db/gnextrapolator.sld_design_entry_dsc.sci =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/db/gnextrapolator.sld_design_entry_dsc.sci =================================================================== --- trunk/QuartusII/db/gnextrapolator.sld_design_entry_dsc.sci (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.sld_design_entry_dsc.sci (revision 5)
trunk/QuartusII/db/gnextrapolator.sld_design_entry_dsc.sci Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/db/altsyncram_uv61.tdf =================================================================== --- trunk/QuartusII/db/altsyncram_uv61.tdf (nonexistent) +++ trunk/QuartusII/db/altsyncram_uv61.tdf (revision 5) @@ -0,0 +1,362 @@ +--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Stratix II" INDATA_ACLR_A="NONE" INIT_FILE="gnextrapolator.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=32 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="UNREGISTERED" RAM_BLOCK_TYPE="M512" WIDTH_A=16 WIDTHAD_A=5 WRCONTROL_ACLR_A="NONE" address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 +--VERSION_BEGIN 9.1SP2 cbx_altsyncram 2010:03:24:20:43:42:SJ cbx_cycloneii 2010:03:24:20:43:43:SJ cbx_lpm_add_sub 2010:03:24:20:43:43:SJ cbx_lpm_compare 2010:03:24:20:43:43:SJ cbx_lpm_decode 2010:03:24:20:43:43:SJ cbx_lpm_mux 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ cbx_stratix 2010:03:24:20:43:43:SJ cbx_stratixii 2010:03:24:20:43:43:SJ cbx_stratixiii 2010:03:24:20:43:43:SJ cbx_util_mgl 2010:03:24:20:43:43:SJ VERSION_END + + +-- Copyright (C) 1991-2010 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + +FUNCTION stratixii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe) +WITH ( CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, LOGICAL_RAM_NAME, mem_init0, mem_init1, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS, PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS, PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE) +RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]); + +--synthesis_resources = M512 1 +OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION"; + +SUBDESIGN altsyncram_uv61 +( + address_a[4..0] : input; + clock0 : input; + q_a[15..0] : output; +) +VARIABLE + ram_block1a0 : stratixii_ram_block + WITH ( + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "gnextrapolator.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", + PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 0, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 16, + RAM_BLOCK_TYPE = "M512" + ); + ram_block1a1 : stratixii_ram_block + WITH ( + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "gnextrapolator.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", + PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 1, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 16, + RAM_BLOCK_TYPE = "M512" + ); + ram_block1a2 : stratixii_ram_block + WITH ( + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "gnextrapolator.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", + PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 2, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 16, + RAM_BLOCK_TYPE = "M512" + ); + ram_block1a3 : stratixii_ram_block + WITH ( + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "gnextrapolator.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", + PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 3, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 16, + RAM_BLOCK_TYPE = "M512" + ); + ram_block1a4 : stratixii_ram_block + WITH ( + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "gnextrapolator.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", + PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 4, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 16, + RAM_BLOCK_TYPE = "M512" + ); + ram_block1a5 : stratixii_ram_block + WITH ( + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "gnextrapolator.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", + PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 5, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 16, + RAM_BLOCK_TYPE = "M512" + ); + ram_block1a6 : stratixii_ram_block + WITH ( + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "gnextrapolator.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", + PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 6, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 16, + RAM_BLOCK_TYPE = "M512" + ); + ram_block1a7 : stratixii_ram_block + WITH ( + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "gnextrapolator.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", + PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 7, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 16, + RAM_BLOCK_TYPE = "M512" + ); + ram_block1a8 : stratixii_ram_block + WITH ( + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "gnextrapolator.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", + PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 8, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 16, + RAM_BLOCK_TYPE = "M512" + ); + ram_block1a9 : stratixii_ram_block + WITH ( + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "gnextrapolator.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", + PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 9, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 16, + RAM_BLOCK_TYPE = "M512" + ); + ram_block1a10 : stratixii_ram_block + WITH ( + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "gnextrapolator.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", + PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 10, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 16, + RAM_BLOCK_TYPE = "M512" + ); + ram_block1a11 : stratixii_ram_block + WITH ( + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "gnextrapolator.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", + PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 11, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 16, + RAM_BLOCK_TYPE = "M512" + ); + ram_block1a12 : stratixii_ram_block + WITH ( + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "gnextrapolator.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", + PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 12, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 16, + RAM_BLOCK_TYPE = "M512" + ); + ram_block1a13 : stratixii_ram_block + WITH ( + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "gnextrapolator.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", + PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 13, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 16, + RAM_BLOCK_TYPE = "M512" + ); + ram_block1a14 : stratixii_ram_block + WITH ( + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "gnextrapolator.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", + PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 14, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 16, + RAM_BLOCK_TYPE = "M512" + ); + ram_block1a15 : stratixii_ram_block + WITH ( + CONNECTIVITY_CHECKING = "OFF", + INIT_FILE = "gnextrapolator.mif", + INIT_FILE_LAYOUT = "port_a", + LOGICAL_RAM_NAME = "ALTSYNCRAM", + OPERATION_MODE = "rom", + PORT_A_ADDRESS_WIDTH = 5, + PORT_A_DATA_OUT_CLEAR = "none", + PORT_A_DATA_OUT_CLOCK = "none", + PORT_A_DATA_WIDTH = 1, + PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on", + PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on", + PORT_A_FIRST_ADDRESS = 0, + PORT_A_FIRST_BIT_NUMBER = 15, + PORT_A_LAST_ADDRESS = 31, + PORT_A_LOGICAL_RAM_DEPTH = 32, + PORT_A_LOGICAL_RAM_WIDTH = 16, + RAM_BLOCK_TYPE = "M512" + ); + address_a_wire[4..0] : WIRE; + +BEGIN + ram_block1a[15..0].clk0 = clock0; + ram_block1a[15..0].portaaddr[] = ( address_a_wire[4..0]); + address_a_wire[] = address_a[]; + q_a[] = ( ram_block1a[15..0].portadataout[0..0]); +END; +--VALID FILE Index: trunk/QuartusII/db/gnextrapolator.map_bb.logdb =================================================================== --- trunk/QuartusII/db/gnextrapolator.map_bb.logdb (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.map_bb.logdb (revision 5) @@ -0,0 +1 @@ +v1 Index: trunk/QuartusII/db/gnextrapolator.hif =================================================================== --- trunk/QuartusII/db/gnextrapolator.hif (nonexistent) +++ trunk/QuartusII/db/gnextrapolator.hif (revision 5) @@ -0,0 +1,424 @@ +Quartus II +Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition +7 +489 +OFF +OFF +OFF +ON +ON +ON +FV_OFF +Level2 +0 +0 +VRSM_ON +VHSM_ON +0 +-- Start Library Paths -- +-- End Library Paths -- +-- Start VHDL Libraries -- +-- End VHDL Libraries -- +# entity +gnextrapolator +# storage +db|gnextrapolator.(0).cnf +db|gnextrapolator.(0).cnf +# logic_option { +AUTO_RAM_RECOGNITION +ON +} +# case_insensitive +# source_file +gnextrapolator.vhd +c0497f7d48f534f05be4f64f5db791c +5 +# internal_option { +HDL_INITIAL_FANOUT_LIMIT +OFF +AUTO_RESOURCE_SHARING +OFF +AUTO_RAM_RECOGNITION +ON +AUTO_ROM_RECOGNITION +ON +} +# hierarchies { +| +} +# lmf +|altera|quartus|lmf|maxplus2.lmf +a36c8ec425c8a2589af98b2d4daabc3 +# macro_sequence + +# end +# entity +altsyncram +# storage +db|gnextrapolator.(1).cnf +db|gnextrapolator.(1).cnf +# case_insensitive +# source_file +|altera|quartus|libraries|megafunctions|altsyncram.tdf +67d9a3902c8a461c1d5750189e124f2 +7 +# user_parameter { +BYTE_SIZE_BLOCK +8 +PARAMETER_UNKNOWN +DEF +AUTO_CARRY_CHAINS +ON +AUTO_CARRY +USR +IGNORE_CARRY_BUFFERS +OFF +IGNORE_CARRY +USR +AUTO_CASCADE_CHAINS +ON +AUTO_CASCADE +USR +IGNORE_CASCADE_BUFFERS +OFF +IGNORE_CASCADE +USR +WIDTH_BYTEENA +1 +PARAMETER_UNKNOWN +DEF +OPERATION_MODE +ROM +PARAMETER_UNKNOWN +USR +WIDTH_A +16 +PARAMETER_UNKNOWN +USR +WIDTHAD_A +5 +PARAMETER_UNKNOWN +USR +NUMWORDS_A +32 +PARAMETER_UNKNOWN +USR +OUTDATA_REG_A +UNREGISTERED +PARAMETER_UNKNOWN +USR +ADDRESS_ACLR_A +NONE +PARAMETER_UNKNOWN +USR +OUTDATA_ACLR_A +NONE +PARAMETER_UNKNOWN +USR +WRCONTROL_ACLR_A +NONE +PARAMETER_UNKNOWN +USR +INDATA_ACLR_A +NONE +PARAMETER_UNKNOWN +USR +BYTEENA_ACLR_A +NONE +PARAMETER_UNKNOWN +DEF +WIDTH_B +1 +PARAMETER_UNKNOWN +DEF +WIDTHAD_B +1 +PARAMETER_UNKNOWN +DEF +NUMWORDS_B +1 +PARAMETER_UNKNOWN +DEF +INDATA_REG_B +CLOCK1 +PARAMETER_UNKNOWN +DEF +WRCONTROL_WRADDRESS_REG_B +CLOCK1 +PARAMETER_UNKNOWN +DEF +RDCONTROL_REG_B +CLOCK1 +PARAMETER_UNKNOWN +DEF +ADDRESS_REG_B +CLOCK1 +PARAMETER_UNKNOWN +DEF +OUTDATA_REG_B +UNREGISTERED +PARAMETER_UNKNOWN +DEF +BYTEENA_REG_B +CLOCK1 +PARAMETER_UNKNOWN +DEF +INDATA_ACLR_B +NONE +PARAMETER_UNKNOWN +DEF +WRCONTROL_ACLR_B +NONE +PARAMETER_UNKNOWN +DEF +ADDRESS_ACLR_B +NONE +PARAMETER_UNKNOWN +DEF +OUTDATA_ACLR_B +NONE +PARAMETER_UNKNOWN +DEF +RDCONTROL_ACLR_B +NONE +PARAMETER_UNKNOWN +DEF +BYTEENA_ACLR_B +NONE +PARAMETER_UNKNOWN +DEF +WIDTH_BYTEENA_A +1 +PARAMETER_UNKNOWN +DEF +WIDTH_BYTEENA_B +1 +PARAMETER_UNKNOWN +DEF +RAM_BLOCK_TYPE +M512 +PARAMETER_UNKNOWN +USR +BYTE_SIZE +8 +PARAMETER_UNKNOWN +DEF +READ_DURING_WRITE_MODE_MIXED_PORTS +DONT_CARE +PARAMETER_UNKNOWN +DEF +READ_DURING_WRITE_MODE_PORT_A +NEW_DATA_NO_NBE_READ +PARAMETER_UNKNOWN +DEF +READ_DURING_WRITE_MODE_PORT_B +NEW_DATA_NO_NBE_READ +PARAMETER_UNKNOWN +DEF +INIT_FILE +gnextrapolator.mif +PARAMETER_UNKNOWN +USR +INIT_FILE_LAYOUT +PORT_A +PARAMETER_UNKNOWN +DEF +MAXIMUM_DEPTH +0 +PARAMETER_UNKNOWN +DEF +CLOCK_ENABLE_INPUT_A +NORMAL +PARAMETER_UNKNOWN +DEF +CLOCK_ENABLE_INPUT_B +NORMAL +PARAMETER_UNKNOWN +DEF +CLOCK_ENABLE_OUTPUT_A +NORMAL +PARAMETER_UNKNOWN +DEF +CLOCK_ENABLE_OUTPUT_B +NORMAL +PARAMETER_UNKNOWN +DEF +CLOCK_ENABLE_CORE_A +USE_INPUT_CLKEN +PARAMETER_UNKNOWN +DEF +CLOCK_ENABLE_CORE_B +USE_INPUT_CLKEN +PARAMETER_UNKNOWN +DEF +ENABLE_ECC +FALSE +PARAMETER_UNKNOWN +DEF +DEVICE_FAMILY +Stratix II +PARAMETER_UNKNOWN +USR +CBXI_PARAMETER +altsyncram_uv61 +PARAMETER_UNKNOWN +USR +} +# used_port { +q_a9 +-1 +3 +q_a8 +-1 +3 +q_a7 +-1 +3 +q_a6 +-1 +3 +q_a5 +-1 +3 +q_a4 +-1 +3 +q_a3 +-1 +3 +q_a2 +-1 +3 +q_a15 +-1 +3 +q_a14 +-1 +3 +q_a13 +-1 +3 +q_a12 +-1 +3 +q_a11 +-1 +3 +q_a10 +-1 +3 +q_a1 +-1 +3 +q_a0 +-1 +3 +clock0 +-1 +3 +address_a4 +-1 +3 +address_a3 +-1 +3 +address_a2 +-1 +3 +address_a1 +-1 +3 +address_a0 +-1 +3 +} +# macro_sequence + +# end +# entity +altsyncram_uv61 +# storage +db|gnextrapolator.(2).cnf +db|gnextrapolator.(2).cnf +# case_insensitive +# source_file +db|altsyncram_uv61.tdf +6bbbbed65e2061f9561eb6568126fb +7 +# used_port { +q_a9 +-1 +3 +q_a8 +-1 +3 +q_a7 +-1 +3 +q_a6 +-1 +3 +q_a5 +-1 +3 +q_a4 +-1 +3 +q_a3 +-1 +3 +q_a2 +-1 +3 +q_a15 +-1 +3 +q_a14 +-1 +3 +q_a13 +-1 +3 +q_a12 +-1 +3 +q_a11 +-1 +3 +q_a10 +-1 +3 +q_a1 +-1 +3 +q_a0 +-1 +3 +clock0 +-1 +3 +address_a4 +-1 +3 +address_a3 +-1 +3 +address_a2 +-1 +3 +address_a1 +-1 +3 +address_a0 +-1 +3 +} +# memory_file { +gnextrapolator.mif +451394458b14cffb5908eee7fcef8ab +} +# macro_sequence + +# end +# complete + Index: trunk/QuartusII/gnextrapolator.vhd.bak =================================================================== --- trunk/QuartusII/gnextrapolator.vhd.bak (nonexistent) +++ trunk/QuartusII/gnextrapolator.vhd.bak (revision 5) @@ -0,0 +1,157 @@ +--//// This file is part of the GNExtrapolator project //// +--//// http://opencores.org/project,gnextrapolator //// +--//// //// +--//// Description //// +--//// Implementation of Algoritm for extrapolation functions //// +--//// //// +--//// //// +--//// To Do: //// +--//// - //// +--//// //// +--//// Author(s): //// +--//// - Rodrigo Villegas, ruyvillegas@gmail.com, designer //// +--//// - Iván Millán, ivanmillan36@gmail.com, designer //// +--//// - Pablo A. Salvadeo, pas.@opencores, manager //// +--//// //// +--////////////////////////////////////////////////////////////////////// +--//// //// +--//// Copyright (C) 2011 Authors and OPENCORES.ORG //// +--//// //// +--//// This source file may be used and distributed without //// +--//// restriction provided that this copyright statement is not //// +--//// removed from the file and that any derivative work contains //// +--//// the original copyright notice and the associated disclaimer. //// +--//// //// +--//// This source file is free software; you can redistribute it //// +--//// and/or modify it under the terms of the GNU Lesser General //// +--//// Public License as published by the Free Software Foundation; //// +--//// either version 2.1 of the License, or (at your option) any //// +--//// later version. //// +--//// //// +--//// This source is distributed in the hope that it will be //// +--//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +--//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +--//// PURPOSE. See the GNU Lesser General Public License for more //// +--//// details. //// +--//// //// +--//// You should have received a copy of the GNU Lesser General //// +--//// Public License along with this source; if not, download it //// +--//// from http://www.opencores.org/lgpl.shtml //// +--//// //// +--////////////////////////////////////////////////////////////////////// + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_signed.all; +USE ieee.std_logic_arith.all; + +entity gnextrapolator is + port + ( + rst_i : in std_logic; + clk_i : in std_logic; + distancia_i: in std_logic_vector(7 downto 0); + extrapolar_i: in std_logic; + indice_p_o: out std_logic_vector(4 downto 0); + fxx_o: out std_logic_vector(15 downto 0); + fxx1_o: out std_logic_vector(15 downto 0); + fxx2_o: out std_logic_vector(15 downto 0); + fxx3_o: out std_logic_vector(15 downto 0); + fxx4_o: out std_logic_vector(15 downto 0); + resul_o: out std_logic_vector(15 downto 0) + ); +end gnextrapolator; + + +architecture grenew of gnextrapolator is +------------------------------------------------------------------------------------------------------- +type columna is array(0 to 2) of std_logic_vector(15 downto 0); +signal sfx: columna; +signal indice: integer range 0 to 31; +signal sram: std_logic_vector(15 downto 0); + +------------------------------------------------------------------------------------------------------- + subtype word_t is std_logic_vector(15 downto 0); + type memory_t is array(0 to 31) of word_t; + signal ram : memory_t; + attribute romstyle : string; + attribute romstyle of ram : signal is "M512"; + attribute ram_init_file : string; + attribute ram_init_file of ram :signal is "gnextrapolator.mif"; +------------------------------------------------------------------------------------------------------- + + + +begin +process(rst_i,clk_i) +variable i:integer range 0 to 2 ; +variable resultado:std_logic_vector(15 downto 0); +variable fx: columna; +variable nabla1fx: columna; +variable nabla2fx: columna; +variable nabla3fx: columna; +variable nabla4fx: columna; +variable compensacion: columna; +variable cont:integer range 0 to 65535; + +begin +if (rst_i='1') then + i:=0; + cont:=0; + fx(0):= (others=>'0'); + nabla1fx(0):= (others=>'0'); + nabla2fx(0):= (others=>'0'); + nabla3fx(0):= (others=>'0'); + nabla4fx(0):= (others=>'0'); + indice<=0; +elsif(rising_edge(clk_i)) then + + if(extrapolar_i = '0') then + fx(i):= sram; + -- + -- Se resiben los datos hasta que se ponga en alto el pin + elsif(extrapolar_i = '1') then -- 'extrapolar', con lo cual, se comienza a usar como valores + fx(i):=resultado; -- + cont:= cont+1; -- de la funcion los resultados calculados, y se deja de tomar datos + end if; -- de la entrada. + + + nabla1fx(i):=(fx(i)-fx(i-1)); -- Se calculan los nablas y el resultado + nabla2fx(i):=(nabla1fx(i)-nabla1fx(i-1)); -- de sumar la ultima fila de vaores de + nabla3fx(i):=(nabla2fx(i)-nabla2fx(i-1)); -- la tabla. + nabla4fx(i):=(nabla3fx(i)-nabla3fx(i-1)); -- + -- + resultado:=fx(i)+nabla1fx(i)+nabla2fx(i)+nabla3fx(i)+nabla4fx(i); -- + + fxx_o <= fx(i); -- + fxx1_o<= nabla1fx(i); -- Se envian los datos a salidas para su observacion, + fxx2_o<= nabla2fx(i); -- el resultado se envia cada cierta cantidad de muestras + fxx3_o<= nabla3fx(i); -- definida por el usuario. + fxx4_o<= nabla4fx(i); -- + if(cont = distancia_i) then -- + resul_o<=resultado; -- + cont:=0; -- + end if; -- + + + fx(0):= fx(i); -- se desplaza la fila hacia atras para poder calcular la siguiente + nabla1fx(0):= nabla1fx(i); -- + nabla2fx(0):= nabla2fx(i); -- + nabla3fx(0):= nabla3fx(i); -- + nabla4fx(0):= nabla4fx(i); -- + +i:=1; +indice <= indice+1; +end if; + +end process; +indice_p_o <= std_logic_vector(to_signed(indice)); +-------------------------------------------------------------------------------------------------------------- +process(clk_i) + begin + if(falling_edge(clk_i)) then + sram <= ram(indice); + end if; +end process; +----------------------------------------------------------------------------------------------------------------- +end grenew; Index: trunk/QuartusII/gnextrapolator.fit.summary =================================================================== --- trunk/QuartusII/gnextrapolator.fit.summary (nonexistent) +++ trunk/QuartusII/gnextrapolator.fit.summary (revision 5) @@ -0,0 +1,17 @@ +Fitter Status : Successful - Tue Aug 14 00:28:04 2012 +Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition +Revision Name : gnextrapolator +Top-level Entity Name : gnextrapolator +Family : Stratix II +Device : EP2S15F484C4 +Timing Models : Final +Logic utilization : 2 % + Combinational ALUTs : 169 / 12,480 ( 1 % ) + Dedicated logic registers : 190 / 12,480 ( 2 % ) +Total registers : 190 +Total pins : 107 / 343 ( 31 % ) +Total virtual pins : 0 +Total block memory bits : 512 / 419,328 ( < 1 % ) +DSP block 9-bit elements : 0 / 96 ( 0 % ) +Total PLLs : 0 / 6 ( 0 % ) +Total DLLs : 0 / 2 ( 0 % ) Index: trunk/QuartusII/gnextrapolator.tan.summary =================================================================== --- trunk/QuartusII/gnextrapolator.tan.summary (nonexistent) +++ trunk/QuartusII/gnextrapolator.tan.summary (revision 5) @@ -0,0 +1,56 @@ +-------------------------------------------------------------------------------------- +Timing Analyzer Summary +-------------------------------------------------------------------------------------- + +Type : Worst-case tsu +Slack : N/A +Required Time : None +Actual Time : 12.402 ns +From : extrapolar_i +To : resultado[15] +From Clock : -- +To Clock : clk_i +Failed Paths : 0 + +Type : Worst-case tco +Slack : N/A +Required Time : None +Actual Time : 8.310 ns +From : fxx3_o[14]~reg0 +To : fxx3_o[14] +From Clock : clk_i +To Clock : -- +Failed Paths : 0 + +Type : Worst-case th +Slack : N/A +Required Time : None +Actual Time : -1.094 ns +From : rst_i +To : fxx1_o[15]~reg0 +From Clock : -- +To Clock : clk_i +Failed Paths : 0 + +Type : Clock Setup: 'clk_i' +Slack : N/A +Required Time : None +Actual Time : 46.88 MHz ( period = 21.332 ns ) +From : altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 +To : resultado[15] +From Clock : clk_i +To Clock : clk_i +Failed Paths : 0 + +Type : Total number of failed paths +Slack : +Required Time : +Actual Time : +From : +To : +From Clock : +To Clock : +Failed Paths : 0 + +-------------------------------------------------------------------------------------- + Index: trunk/QuartusII/gnextrapolator.vhd =================================================================== --- trunk/QuartusII/gnextrapolator.vhd (nonexistent) +++ trunk/QuartusII/gnextrapolator.vhd (revision 5) @@ -0,0 +1,157 @@ +--//// This file is part of the GNExtrapolator project //// +--//// http://opencores.org/project,gnextrapolator //// +--//// //// +--//// Description //// +--//// Implementation of Algoritm for extrapolation functions //// +--//// //// +--//// //// +--//// To Do: //// +--//// - //// +--//// //// +--//// Author(s): //// +--//// - Rodrigo Villegas, ruyvillegas@gmail.com, designer //// +--//// - Iván Millán, ivanmillan36@gmail.com, designer //// +--//// - Pablo A. Salvadeo, pas.@opencores, manager //// +--//// //// +--////////////////////////////////////////////////////////////////////// +--//// //// +--//// Copyright (C) 2011 Authors and OPENCORES.ORG //// +--//// //// +--//// This source file may be used and distributed without //// +--//// restriction provided that this copyright statement is not //// +--//// removed from the file and that any derivative work contains //// +--//// the original copyright notice and the associated disclaimer. //// +--//// //// +--//// This source file is free software; you can redistribute it //// +--//// and/or modify it under the terms of the GNU Lesser General //// +--//// Public License as published by the Free Software Foundation; //// +--//// either version 2.1 of the License, or (at your option) any //// +--//// later version. //// +--//// //// +--//// This source is distributed in the hope that it will be //// +--//// useful, but WITHOUT ANY WARRANTY; without even the implied //// +--//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// +--//// PURPOSE. See the GNU Lesser General Public License for more //// +--//// details. //// +--//// //// +--//// You should have received a copy of the GNU Lesser General //// +--//// Public License along with this source; if not, download it //// +--//// from http://www.opencores.org/lgpl.shtml //// +--//// //// +--////////////////////////////////////////////////////////////////////// + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_signed.all; +USE ieee.std_logic_arith.all; + +entity gnextrapolator is + port + ( + rst_i : in std_logic; + clk_i : in std_logic; + distancia_i: in std_logic_vector(7 downto 0); + extrapolar_i: in std_logic; + --indice_p_o: out std_logic_vector(4 downto 0); + fxx_o: out std_logic_vector(15 downto 0); + fxx1_o: out std_logic_vector(15 downto 0); + fxx2_o: out std_logic_vector(15 downto 0); + fxx3_o: out std_logic_vector(15 downto 0); + fxx4_o: out std_logic_vector(15 downto 0); + resul_o: out std_logic_vector(15 downto 0) + ); +end gnextrapolator; + + +architecture grenew of gnextrapolator is +------------------------------------------------------------------------------------------------------- +type columna is array(0 to 2) of std_logic_vector(15 downto 0); +signal sfx: columna; +signal indice: integer range 0 to 31; +signal sram: std_logic_vector(15 downto 0); + +------------------------------------------------------------------------------------------------------- + subtype word_t is std_logic_vector(15 downto 0); + type memory_t is array(0 to 31) of word_t; + signal ram : memory_t; + attribute romstyle : string; + attribute romstyle of ram : signal is "M512"; + attribute ram_init_file : string; + attribute ram_init_file of ram :signal is "gnextrapolator.mif"; +------------------------------------------------------------------------------------------------------- + + + +begin +process(rst_i,clk_i) +variable i:integer range 0 to 2 ; +variable resultado:std_logic_vector(15 downto 0); +variable fx: columna; +variable nabla1fx: columna; +variable nabla2fx: columna; +variable nabla3fx: columna; +variable nabla4fx: columna; +variable compensacion: columna; +variable cont:integer range 0 to 65535; + +begin +if (rst_i='1') then + i:=0; + cont:=0; + fx(0):= (others=>'0'); + nabla1fx(0):= (others=>'0'); + nabla2fx(0):= (others=>'0'); + nabla3fx(0):= (others=>'0'); + nabla4fx(0):= (others=>'0'); + indice<=0; +elsif(rising_edge(clk_i)) then + + if(extrapolar_i = '0') then + fx(i):= sram; + -- + -- Se resiben los datos hasta que se ponga en alto el pin + elsif(extrapolar_i = '1') then -- 'extrapolar', con lo cual, se comienza a usar como valores + fx(i):=resultado; -- + cont:= cont+1; -- de la funcion los resultados calculados, y se deja de tomar datos + end if; -- de la entrada. + + + nabla1fx(i):=(fx(i)-fx(i-1)); -- Se calculan los nablas y el resultado + nabla2fx(i):=(nabla1fx(i)-nabla1fx(i-1)); -- de sumar la ultima fila de vaores de + nabla3fx(i):=(nabla2fx(i)-nabla2fx(i-1)); -- la tabla. + nabla4fx(i):=(nabla3fx(i)-nabla3fx(i-1)); -- + -- + resultado:=fx(i)+nabla1fx(i)+nabla2fx(i)+nabla3fx(i)+nabla4fx(i); -- + + fxx_o <= fx(i); -- + fxx1_o<= nabla1fx(i); -- Se envian los datos a salidas para su observacion, + fxx2_o<= nabla2fx(i); -- el resultado se envia cada cierta cantidad de muestras + fxx3_o<= nabla3fx(i); -- definida por el usuario. + fxx4_o<= nabla4fx(i); -- + if(cont = distancia_i) then -- + resul_o<=resultado; -- + cont:=0; -- + end if; -- + + + fx(0):= fx(i); -- se desplaza la fila hacia atras para poder calcular la siguiente + nabla1fx(0):= nabla1fx(i); -- + nabla2fx(0):= nabla2fx(i); -- + nabla3fx(0):= nabla3fx(i); -- + nabla4fx(0):= nabla4fx(i); -- + +i:=1; +indice <= indice+1; +end if; + +end process; +--indice_p_o <= std_logic_vector(indice); +-------------------------------------------------------------------------------------------------------------- +process(clk_i) + begin + if(falling_edge(clk_i)) then + sram <= ram(indice); + end if; +end process; +----------------------------------------------------------------------------------------------------------------- +end grenew; Index: trunk/QuartusII/gnextrapolator.map.rpt =================================================================== --- trunk/QuartusII/gnextrapolator.map.rpt (nonexistent) +++ trunk/QuartusII/gnextrapolator.map.rpt (revision 5) @@ -0,0 +1,718 @@ +Analysis & Synthesis report for gnextrapolator +Tue Aug 14 00:26:26 2012 +Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Analysis & Synthesis Source Files Read + 5. Analysis & Synthesis Resource Usage Summary + 6. Analysis & Synthesis Resource Utilization by Entity + 7. Analysis & Synthesis RAM Summary + 8. Registers Removed During Synthesis + 9. General Register Statistics + 10. Registers Packed Into Inferred Megafunctions + 11. Multiplexer Restructuring Statistics (Restructuring Performed) + 12. Source assignments for altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated + 13. Parameter Settings for Inferred Entity Instance: altsyncram:ram_rtl_0 + 14. altsyncram Parameter Settings by Entity Instance + 15. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++-------------------------------+----------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Tue Aug 14 00:26:26 2012 ; +; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ; +; Revision Name ; gnextrapolator ; +; Top-level Entity Name ; gnextrapolator ; +; Family ; Stratix II ; +; Logic utilization ; N/A ; +; Combinational ALUTs ; 168 ; +; Dedicated logic registers ; 190 ; +; Total registers ; 190 ; +; Total pins ; 107 ; +; Total virtual pins ; 0 ; +; Total block memory bits ; 512 ; +; DSP block 9-bit elements ; 0 ; +; Total PLLs ; 0 ; +; Total DLLs ; 0 ; ++-------------------------------+----------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP2S15F484C4 ; ; +; Top-level entity name ; gnextrapolator ; gnextrapolator ; +; Family name ; Stratix II ; Stratix II ; +; Use Generated Physical Constraints File ; Off ; ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto DSP Block Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM Block Balancing ; On ; On ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; Off ; Off ; +; Show Parameter Settings Tables in Synthesis Report ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; ++----------------------------------------------------------------------------+--------------------+--------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+----------------------------------+----------------------------------------------------------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; ++----------------------------------+-----------------+----------------------------------+----------------------------------------------------------+ +; gnextrapolator.vhd ; yes ; User VHDL File ; C:/Altera/qdesigns/gnextrapolator/gnextrapolator.vhd ; +; gnextrapolator.mif ; yes ; User Memory Initialization File ; C:/Altera/qdesigns/gnextrapolator/gnextrapolator.mif ; +; altsyncram.tdf ; yes ; Megafunction ; c:/altera/quartus/libraries/megafunctions/altsyncram.tdf ; +; db/altsyncram_uv61.tdf ; yes ; Auto-Generated Megafunction ; C:/Altera/qdesigns/gnextrapolator/db/altsyncram_uv61.tdf ; ++----------------------------------+-----------------+----------------------------------+----------------------------------------------------------+ + + ++-------------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++-----------------------------------------------+-------+ +; Resource ; Usage ; ++-----------------------------------------------+-------+ +; Estimated ALUTs Used ; 168 ; +; Dedicated logic registers ; 190 ; +; ; ; +; Estimated ALUTs Unavailable ; 0 ; +; ; ; +; Total combinational functions ; 168 ; +; Combinational ALUT usage by number of inputs ; ; +; -- 7 input functions ; 0 ; +; -- 6 input functions ; 4 ; +; -- 5 input functions ; 16 ; +; -- 4 input functions ; 32 ; +; -- <=3 input functions ; 116 ; +; ; ; +; Combinational ALUTs by mode ; ; +; -- normal mode ; 38 ; +; -- extended LUT mode ; 0 ; +; -- arithmetic mode ; 114 ; +; -- shared arithmetic mode ; 16 ; +; ; ; +; Estimated ALUT/register pairs used ; 223 ; +; ; ; +; Total registers ; 190 ; +; -- Dedicated logic registers ; 190 ; +; -- I/O registers ; 0 ; +; ; ; +; Estimated ALMs: partially or completely used ; 112 ; +; ; ; +; I/O pins ; 107 ; +; Total block memory bits ; 512 ; +; Maximum fan-out node ; clk_i ; +; Maximum fan-out ; 206 ; +; Total fan-out ; 1365 ; +; Average fan-out ; 2.84 ; ++-----------------------------------------------+-------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++----------------------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------------------------------------------------------+--------------+ +; |gnextrapolator ; 168 (168) ; 190 (190) ; 512 ; 0 ; 0 ; 0 ; 0 ; 107 ; 0 ; |gnextrapolator ; work ; +; |altsyncram:ram_rtl_0| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |gnextrapolator|altsyncram:ram_rtl_0 ; ; +; |altsyncram_uv61:auto_generated| ; 0 (0) ; 0 (0) ; 512 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |gnextrapolator|altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated ; ; ++----------------------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------------------------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis RAM Summary ; ++----------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+--------------------+ +; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ; ++----------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+--------------------+ +; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ALTSYNCRAM ; M512 ; ROM ; 32 ; 16 ; -- ; -- ; 512 ; gnextrapolator.mif ; ++----------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+------+--------------------+ + + ++----------------------------------------------------------------------------------+ +; Registers Removed During Synthesis ; ++-----------------------------------------+----------------------------------------+ +; Register name ; Reason for Removal ; ++-----------------------------------------+----------------------------------------+ +; i[1] ; Stuck at GND due to stuck port data_in ; +; nabla4fx[2][15] ; Lost fanout ; +; nabla4fx[2][14] ; Lost fanout ; +; nabla4fx[2][13] ; Lost fanout ; +; nabla4fx[2][12] ; Lost fanout ; +; nabla4fx[2][11] ; Lost fanout ; +; nabla4fx[2][10] ; Lost fanout ; +; nabla4fx[2][9] ; Lost fanout ; +; nabla4fx[2][8] ; Lost fanout ; +; nabla4fx[2][7] ; Lost fanout ; +; nabla4fx[2][6] ; Lost fanout ; +; nabla4fx[2][5] ; Lost fanout ; +; nabla4fx[2][4] ; Lost fanout ; +; nabla4fx[2][3] ; Lost fanout ; +; nabla4fx[2][2] ; Lost fanout ; +; nabla4fx[2][1] ; Lost fanout ; +; nabla4fx[2][0] ; Lost fanout ; +; fx[2][13] ; Merged with fx[2][15] ; +; nabla2fx[2][1] ; Merged with fx[2][15] ; +; fx[2][9] ; Merged with fx[2][15] ; +; nabla2fx[2][14] ; Merged with fx[2][15] ; +; nabla1fx[2][9] ; Merged with fx[2][15] ; +; fx[2][7] ; Merged with fx[2][15] ; +; nabla2fx[2][9] ; Merged with fx[2][15] ; +; nabla3fx[2][8] ; Merged with fx[2][15] ; +; nabla1fx[2][13] ; Merged with fx[2][15] ; +; nabla1fx[2][0] ; Merged with fx[2][15] ; +; nabla2fx[2][12] ; Merged with fx[2][15] ; +; nabla3fx[2][9] ; Merged with fx[2][15] ; +; fx[2][5] ; Merged with fx[2][15] ; +; fx[2][14] ; Merged with fx[2][15] ; +; nabla2fx[2][6] ; Merged with fx[2][15] ; +; nabla2fx[2][13] ; Merged with fx[2][15] ; +; fx[2][11] ; Merged with fx[2][15] ; +; nabla2fx[2][5] ; Merged with fx[2][15] ; +; nabla2fx[2][2] ; Merged with fx[2][15] ; +; nabla1fx[2][15] ; Merged with fx[2][15] ; +; nabla1fx[2][6] ; Merged with fx[2][15] ; +; nabla1fx[2][11] ; Merged with fx[2][15] ; +; fx[2][2] ; Merged with fx[2][15] ; +; nabla3fx[2][13] ; Merged with fx[2][15] ; +; nabla1fx[2][5] ; Merged with fx[2][15] ; +; nabla2fx[2][10] ; Merged with fx[2][15] ; +; nabla3fx[2][5] ; Merged with fx[2][15] ; +; nabla3fx[2][10] ; Merged with fx[2][15] ; +; fx[2][0] ; Merged with fx[2][15] ; +; nabla2fx[2][0] ; Merged with fx[2][15] ; +; nabla2fx[2][8] ; Merged with fx[2][15] ; +; fx[2][6] ; Merged with fx[2][15] ; +; nabla3fx[2][4] ; Merged with fx[2][15] ; +; nabla2fx[2][15] ; Merged with fx[2][15] ; +; fx[2][12] ; Merged with fx[2][15] ; +; nabla2fx[2][11] ; Merged with fx[2][15] ; +; nabla3fx[2][12] ; Merged with fx[2][15] ; +; nabla2fx[2][7] ; Merged with fx[2][15] ; +; fx[2][10] ; Merged with fx[2][15] ; +; nabla2fx[2][3] ; Merged with fx[2][15] ; +; nabla1fx[2][4] ; Merged with fx[2][15] ; +; nabla1fx[2][8] ; Merged with fx[2][15] ; +; fx[2][4] ; Merged with fx[2][15] ; +; nabla1fx[2][14] ; Merged with fx[2][15] ; +; nabla3fx[2][14] ; Merged with fx[2][15] ; +; nabla1fx[2][12] ; Merged with fx[2][15] ; +; nabla3fx[2][6] ; Merged with fx[2][15] ; +; nabla1fx[2][10] ; Merged with fx[2][15] ; +; nabla1fx[2][2] ; Merged with fx[2][15] ; +; nabla3fx[2][15] ; Merged with fx[2][15] ; +; nabla1fx[2][7] ; Merged with fx[2][15] ; +; nabla3fx[2][11] ; Merged with fx[2][15] ; +; fx[2][3] ; Merged with fx[2][15] ; +; nabla3fx[2][7] ; Merged with fx[2][15] ; +; nabla1fx[2][3] ; Merged with fx[2][15] ; +; nabla2fx[2][4] ; Merged with fx[2][15] ; +; nabla3fx[2][3] ; Merged with fx[2][15] ; +; fx[2][8] ; Merged with fx[2][15] ; +; nabla3fx[2][0] ; Merged with fx[2][15] ; +; nabla3fx[2][2] ; Merged with fx[2][15] ; +; fx[2][1] ; Merged with fx[2][15] ; +; nabla1fx[2][1] ; Merged with fx[2][15] ; +; nabla3fx[2][1] ; Merged with fx[2][15] ; +; fx[2][15] ; Stuck at GND due to stuck port data_in ; +; nabla1fx[1][0] ; Lost fanout ; +; nabla1fx[1][1] ; Lost fanout ; +; nabla1fx[1][2] ; Lost fanout ; +; nabla1fx[1][3] ; Lost fanout ; +; nabla1fx[1][4] ; Lost fanout ; +; nabla1fx[1][5] ; Lost fanout ; +; nabla1fx[1][6] ; Lost fanout ; +; nabla1fx[1][7] ; Lost fanout ; +; nabla1fx[1][8] ; Lost fanout ; +; nabla1fx[1][9] ; Lost fanout ; +; nabla1fx[1][10] ; Lost fanout ; +; nabla1fx[1][11] ; Lost fanout ; +; nabla1fx[1][12] ; Lost fanout ; +; nabla1fx[1][13] ; Lost fanout ; +; nabla1fx[1][14] ; Lost fanout ; +; nabla1fx[1][15] ; Lost fanout ; +; nabla2fx[1][0] ; Lost fanout ; +; nabla2fx[1][1] ; Lost fanout ; +; nabla2fx[1][2] ; Lost fanout ; +; nabla2fx[1][3] ; Lost fanout ; +; nabla2fx[1][4] ; Lost fanout ; +; nabla2fx[1][5] ; Lost fanout ; +; nabla2fx[1][6] ; Lost fanout ; +; nabla2fx[1][7] ; Lost fanout ; +; nabla2fx[1][8] ; Lost fanout ; +; nabla2fx[1][9] ; Lost fanout ; +; nabla2fx[1][10] ; Lost fanout ; +; nabla2fx[1][11] ; Lost fanout ; +; nabla2fx[1][12] ; Lost fanout ; +; nabla2fx[1][13] ; Lost fanout ; +; nabla2fx[1][14] ; Lost fanout ; +; nabla2fx[1][15] ; Lost fanout ; +; nabla3fx[1][0] ; Lost fanout ; +; nabla3fx[1][1] ; Lost fanout ; +; nabla3fx[1][2] ; Lost fanout ; +; nabla3fx[1][3] ; Lost fanout ; +; nabla3fx[1][4] ; Lost fanout ; +; nabla3fx[1][5] ; Lost fanout ; +; nabla3fx[1][6] ; Lost fanout ; +; nabla3fx[1][7] ; Lost fanout ; +; nabla3fx[1][8] ; Lost fanout ; +; nabla3fx[1][9] ; Lost fanout ; +; nabla3fx[1][10] ; Lost fanout ; +; nabla3fx[1][11] ; Lost fanout ; +; nabla3fx[1][12] ; Lost fanout ; +; nabla3fx[1][13] ; Lost fanout ; +; nabla3fx[1][14] ; Lost fanout ; +; nabla3fx[1][15] ; Lost fanout ; +; nabla4fx[1][0] ; Lost fanout ; +; nabla4fx[1][1] ; Lost fanout ; +; nabla4fx[1][2] ; Lost fanout ; +; nabla4fx[1][3] ; Lost fanout ; +; nabla4fx[1][4] ; Lost fanout ; +; nabla4fx[1][5] ; Lost fanout ; +; nabla4fx[1][6] ; Lost fanout ; +; nabla4fx[1][7] ; Lost fanout ; +; nabla4fx[1][8] ; Lost fanout ; +; nabla4fx[1][9] ; Lost fanout ; +; nabla4fx[1][10] ; Lost fanout ; +; nabla4fx[1][11] ; Lost fanout ; +; nabla4fx[1][12] ; Lost fanout ; +; nabla4fx[1][13] ; Lost fanout ; +; nabla4fx[1][14] ; Lost fanout ; +; nabla4fx[1][15] ; Lost fanout ; +; nabla4fx[0][0] ; Lost fanout ; +; nabla4fx[0][1] ; Lost fanout ; +; nabla4fx[0][2] ; Lost fanout ; +; nabla4fx[0][3] ; Lost fanout ; +; nabla4fx[0][4] ; Lost fanout ; +; nabla4fx[0][5] ; Lost fanout ; +; nabla4fx[0][6] ; Lost fanout ; +; nabla4fx[0][7] ; Lost fanout ; +; nabla4fx[0][8] ; Lost fanout ; +; nabla4fx[0][9] ; Lost fanout ; +; nabla4fx[0][10] ; Lost fanout ; +; nabla4fx[0][11] ; Lost fanout ; +; nabla4fx[0][12] ; Lost fanout ; +; nabla4fx[0][13] ; Lost fanout ; +; nabla4fx[0][14] ; Lost fanout ; +; nabla4fx[0][15] ; Lost fanout ; +; fx[1][0] ; Lost fanout ; +; fx[1][1] ; Lost fanout ; +; fx[1][2] ; Lost fanout ; +; fx[1][3] ; Lost fanout ; +; fx[1][4] ; Lost fanout ; +; fx[1][5] ; Lost fanout ; +; fx[1][6] ; Lost fanout ; +; fx[1][7] ; Lost fanout ; +; fx[1][8] ; Lost fanout ; +; fx[1][9] ; Lost fanout ; +; fx[1][10] ; Lost fanout ; +; fx[1][11] ; Lost fanout ; +; fx[1][12] ; Lost fanout ; +; fx[1][13] ; Lost fanout ; +; fx[1][14] ; Lost fanout ; +; fx[1][15] ; Lost fanout ; +; cont[8..15] ; Lost fanout ; +; Total Number of Removed Registers = 185 ; ; ++-----------------------------------------+----------------------------------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 190 ; +; Number of registers using Synchronous Clear ; 8 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 78 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 112 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++----------------------------------------------+ +; Registers Packed Into Inferred Megafunctions ; ++---------------+--------------+---------------+ +; Register Name ; Megafunction ; Type ; ++---------------+--------------+---------------+ +; sram[0] ; ram~0 ; RAM ; +; sram[1] ; ram~0 ; RAM ; +; sram[2] ; ram~0 ; RAM ; +; sram[3] ; ram~0 ; RAM ; +; sram[4] ; ram~0 ; RAM ; +; sram[5] ; ram~0 ; RAM ; +; sram[6] ; ram~0 ; RAM ; +; sram[7] ; ram~0 ; RAM ; +; sram[8] ; ram~0 ; RAM ; +; sram[9] ; ram~0 ; RAM ; +; sram[10] ; ram~0 ; RAM ; +; sram[11] ; ram~0 ; RAM ; +; sram[12] ; ram~0 ; RAM ; +; sram[13] ; ram~0 ; RAM ; +; sram[14] ; ram~0 ; RAM ; +; sram[15] ; ram~0 ; RAM ; ++---------------+--------------+---------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ +; 1:1 ; 64 bits ; 0 ALUTs ; 0 ALUTs ; 0 ALUTs ; No ; |gnextrapolator|Mux48 ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+ + + ++----------------------------------------------------------------------------+ +; Source assignments for altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated ; ++---------------------------------+--------------------+------+--------------+ +; Assignment ; Value ; From ; To ; ++---------------------------------+--------------------+------+--------------+ +; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ; ++---------------------------------+--------------------+------+--------------+ + + ++----------------------------------------------------------------------------+ +; Parameter Settings for Inferred Entity Instance: altsyncram:ram_rtl_0 ; ++------------------------------------+----------------------+----------------+ +; Parameter Name ; Value ; Type ; ++------------------------------------+----------------------+----------------+ +; BYTE_SIZE_BLOCK ; 8 ; Untyped ; +; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; +; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; +; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; +; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +; WIDTH_BYTEENA ; 1 ; Untyped ; +; OPERATION_MODE ; ROM ; Untyped ; +; WIDTH_A ; 16 ; Untyped ; +; WIDTHAD_A ; 5 ; Untyped ; +; NUMWORDS_A ; 32 ; Untyped ; +; OUTDATA_REG_A ; UNREGISTERED ; Untyped ; +; ADDRESS_ACLR_A ; NONE ; Untyped ; +; OUTDATA_ACLR_A ; NONE ; Untyped ; +; WRCONTROL_ACLR_A ; NONE ; Untyped ; +; INDATA_ACLR_A ; NONE ; Untyped ; +; BYTEENA_ACLR_A ; NONE ; Untyped ; +; WIDTH_B ; 1 ; Untyped ; +; WIDTHAD_B ; 1 ; Untyped ; +; NUMWORDS_B ; 1 ; Untyped ; +; INDATA_REG_B ; CLOCK1 ; Untyped ; +; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ; +; RDCONTROL_REG_B ; CLOCK1 ; Untyped ; +; ADDRESS_REG_B ; CLOCK1 ; Untyped ; +; OUTDATA_REG_B ; UNREGISTERED ; Untyped ; +; BYTEENA_REG_B ; CLOCK1 ; Untyped ; +; INDATA_ACLR_B ; NONE ; Untyped ; +; WRCONTROL_ACLR_B ; NONE ; Untyped ; +; ADDRESS_ACLR_B ; NONE ; Untyped ; +; OUTDATA_ACLR_B ; NONE ; Untyped ; +; RDCONTROL_ACLR_B ; NONE ; Untyped ; +; BYTEENA_ACLR_B ; NONE ; Untyped ; +; WIDTH_BYTEENA_A ; 1 ; Untyped ; +; WIDTH_BYTEENA_B ; 1 ; Untyped ; +; RAM_BLOCK_TYPE ; M512 ; Untyped ; +; BYTE_SIZE ; 8 ; Untyped ; +; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ; +; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ; +; INIT_FILE ; gnextrapolator.mif ; Untyped ; +; INIT_FILE_LAYOUT ; PORT_A ; Untyped ; +; MAXIMUM_DEPTH ; 0 ; Untyped ; +; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ; +; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ; +; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ; +; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ; +; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ; +; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ; +; ENABLE_ECC ; FALSE ; Untyped ; +; DEVICE_FAMILY ; Stratix II ; Untyped ; +; CBXI_PARAMETER ; altsyncram_uv61 ; Untyped ; ++------------------------------------+----------------------+----------------+ +Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". + + ++------------------------------------------------------------------+ +; altsyncram Parameter Settings by Entity Instance ; ++-------------------------------------------+----------------------+ +; Name ; Value ; ++-------------------------------------------+----------------------+ +; Number of entity instances ; 1 ; +; Entity Instance ; altsyncram:ram_rtl_0 ; +; -- OPERATION_MODE ; ROM ; +; -- WIDTH_A ; 16 ; +; -- NUMWORDS_A ; 32 ; +; -- OUTDATA_REG_A ; UNREGISTERED ; +; -- WIDTH_B ; 1 ; +; -- NUMWORDS_B ; 1 ; +; -- ADDRESS_REG_B ; CLOCK1 ; +; -- OUTDATA_REG_B ; UNREGISTERED ; +; -- RAM_BLOCK_TYPE ; M512 ; +; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; ++-------------------------------------------+----------------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Analysis & Synthesis + Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + Info: Processing started: Tue Aug 14 00:26:16 2012 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolator +Info: Found 2 design units, including 1 entities, in source file gnextrapolator.vhd + Info: Found design unit 1: gnextrapolator-grenew + Info: Found entity 1: gnextrapolator +Info: Elaborating entity "gnextrapolator" for the top level hierarchy +Warning (10541): VHDL Signal Declaration warning at gnextrapolator.vhd(76): used implicit default value for signal "ram" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. +Info: Inferred 1 megafunctions from design logic + Info: Inferred altsyncram megafunction from the following design logic: "ram~0" + Info: Parameter OPERATION_MODE set to ROM + Info: Parameter WIDTH_A set to 16 + Info: Parameter WIDTHAD_A set to 5 + Info: Parameter NUMWORDS_A set to 32 + Info: Parameter OUTDATA_REG_A set to UNREGISTERED + Info: Parameter ADDRESS_ACLR_A set to NONE + Info: Parameter OUTDATA_ACLR_A set to NONE + Info: Parameter INDATA_ACLR_A set to NONE + Info: Parameter WRCONTROL_ACLR_A set to NONE + Info: Parameter RAM_BLOCK_TYPE set to M512 + Info: Parameter INIT_FILE set to gnextrapolator.mif +Info: Elaborated megafunction instantiation "altsyncram:ram_rtl_0" +Info: Instantiated megafunction "altsyncram:ram_rtl_0" with the following parameter: + Info: Parameter "OPERATION_MODE" = "ROM" + Info: Parameter "WIDTH_A" = "16" + Info: Parameter "WIDTHAD_A" = "5" + Info: Parameter "NUMWORDS_A" = "32" + Info: Parameter "OUTDATA_REG_A" = "UNREGISTERED" + Info: Parameter "ADDRESS_ACLR_A" = "NONE" + Info: Parameter "OUTDATA_ACLR_A" = "NONE" + Info: Parameter "INDATA_ACLR_A" = "NONE" + Info: Parameter "WRCONTROL_ACLR_A" = "NONE" + Info: Parameter "RAM_BLOCK_TYPE" = "M512" + Info: Parameter "INIT_FILE" = "gnextrapolator.mif" +Info: Found 1 design units, including 1 entities, in source file db/altsyncram_uv61.tdf + Info: Found entity 1: altsyncram_uv61 +Info: 120 registers lost all their fanouts during netlist optimizations. The first 120 are displayed below. + Info: Register "nabla4fx[2][15]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[2][14]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[2][13]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[2][12]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[2][11]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[2][10]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[2][9]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[2][8]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[2][7]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[2][6]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[2][5]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[2][4]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[2][3]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[2][2]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[2][1]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[2][0]" lost all its fanouts during netlist optimizations. + Info: Register "nabla1fx[1][0]" lost all its fanouts during netlist optimizations. + Info: Register "nabla1fx[1][1]" lost all its fanouts during netlist optimizations. + Info: Register "nabla1fx[1][2]" lost all its fanouts during netlist optimizations. + Info: Register "nabla1fx[1][3]" lost all its fanouts during netlist optimizations. + Info: Register "nabla1fx[1][4]" lost all its fanouts during netlist optimizations. + Info: Register "nabla1fx[1][5]" lost all its fanouts during netlist optimizations. + Info: Register "nabla1fx[1][6]" lost all its fanouts during netlist optimizations. + Info: Register "nabla1fx[1][7]" lost all its fanouts during netlist optimizations. + Info: Register "nabla1fx[1][8]" lost all its fanouts during netlist optimizations. + Info: Register "nabla1fx[1][9]" lost all its fanouts during netlist optimizations. + Info: Register "nabla1fx[1][10]" lost all its fanouts during netlist optimizations. + Info: Register "nabla1fx[1][11]" lost all its fanouts during netlist optimizations. + Info: Register "nabla1fx[1][12]" lost all its fanouts during netlist optimizations. + Info: Register "nabla1fx[1][13]" lost all its fanouts during netlist optimizations. + Info: Register "nabla1fx[1][14]" lost all its fanouts during netlist optimizations. + Info: Register "nabla1fx[1][15]" lost all its fanouts during netlist optimizations. + Info: Register "nabla2fx[1][0]" lost all its fanouts during netlist optimizations. + Info: Register "nabla2fx[1][1]" lost all its fanouts during netlist optimizations. + Info: Register "nabla2fx[1][2]" lost all its fanouts during netlist optimizations. + Info: Register "nabla2fx[1][3]" lost all its fanouts during netlist optimizations. + Info: Register "nabla2fx[1][4]" lost all its fanouts during netlist optimizations. + Info: Register "nabla2fx[1][5]" lost all its fanouts during netlist optimizations. + Info: Register "nabla2fx[1][6]" lost all its fanouts during netlist optimizations. + Info: Register "nabla2fx[1][7]" lost all its fanouts during netlist optimizations. + Info: Register "nabla2fx[1][8]" lost all its fanouts during netlist optimizations. + Info: Register "nabla2fx[1][9]" lost all its fanouts during netlist optimizations. + Info: Register "nabla2fx[1][10]" lost all its fanouts during netlist optimizations. + Info: Register "nabla2fx[1][11]" lost all its fanouts during netlist optimizations. + Info: Register "nabla2fx[1][12]" lost all its fanouts during netlist optimizations. + Info: Register "nabla2fx[1][13]" lost all its fanouts during netlist optimizations. + Info: Register "nabla2fx[1][14]" lost all its fanouts during netlist optimizations. + Info: Register "nabla2fx[1][15]" lost all its fanouts during netlist optimizations. + Info: Register "nabla3fx[1][0]" lost all its fanouts during netlist optimizations. + Info: Register "nabla3fx[1][1]" lost all its fanouts during netlist optimizations. + Info: Register "nabla3fx[1][2]" lost all its fanouts during netlist optimizations. + Info: Register "nabla3fx[1][3]" lost all its fanouts during netlist optimizations. + Info: Register "nabla3fx[1][4]" lost all its fanouts during netlist optimizations. + Info: Register "nabla3fx[1][5]" lost all its fanouts during netlist optimizations. + Info: Register "nabla3fx[1][6]" lost all its fanouts during netlist optimizations. + Info: Register "nabla3fx[1][7]" lost all its fanouts during netlist optimizations. + Info: Register "nabla3fx[1][8]" lost all its fanouts during netlist optimizations. + Info: Register "nabla3fx[1][9]" lost all its fanouts during netlist optimizations. + Info: Register "nabla3fx[1][10]" lost all its fanouts during netlist optimizations. + Info: Register "nabla3fx[1][11]" lost all its fanouts during netlist optimizations. + Info: Register "nabla3fx[1][12]" lost all its fanouts during netlist optimizations. + Info: Register "nabla3fx[1][13]" lost all its fanouts during netlist optimizations. + Info: Register "nabla3fx[1][14]" lost all its fanouts during netlist optimizations. + Info: Register "nabla3fx[1][15]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[1][0]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[1][1]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[1][2]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[1][3]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[1][4]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[1][5]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[1][6]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[1][7]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[1][8]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[1][9]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[1][10]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[1][11]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[1][12]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[1][13]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[1][14]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[1][15]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[0][0]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[0][1]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[0][2]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[0][3]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[0][4]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[0][5]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[0][6]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[0][7]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[0][8]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[0][9]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[0][10]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[0][11]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[0][12]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[0][13]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[0][14]" lost all its fanouts during netlist optimizations. + Info: Register "nabla4fx[0][15]" lost all its fanouts during netlist optimizations. + Info: Register "fx[1][0]" lost all its fanouts during netlist optimizations. + Info: Register "fx[1][1]" lost all its fanouts during netlist optimizations. + Info: Register "fx[1][2]" lost all its fanouts during netlist optimizations. + Info: Register "fx[1][3]" lost all its fanouts during netlist optimizations. + Info: Register "fx[1][4]" lost all its fanouts during netlist optimizations. + Info: Register "fx[1][5]" lost all its fanouts during netlist optimizations. + Info: Register "fx[1][6]" lost all its fanouts during netlist optimizations. + Info: Register "fx[1][7]" lost all its fanouts during netlist optimizations. + Info: Register "fx[1][8]" lost all its fanouts during netlist optimizations. + Info: Register "fx[1][9]" lost all its fanouts during netlist optimizations. + Info: Register "fx[1][10]" lost all its fanouts during netlist optimizations. + Info: Register "fx[1][11]" lost all its fanouts during netlist optimizations. + Info: Register "fx[1][12]" lost all its fanouts during netlist optimizations. + Info: Register "fx[1][13]" lost all its fanouts during netlist optimizations. + Info: Register "fx[1][14]" lost all its fanouts during netlist optimizations. + Info: Register "fx[1][15]" lost all its fanouts during netlist optimizations. + Info: Register "cont[15]" lost all its fanouts during netlist optimizations. + Info: Register "cont[14]" lost all its fanouts during netlist optimizations. + Info: Register "cont[13]" lost all its fanouts during netlist optimizations. + Info: Register "cont[12]" lost all its fanouts during netlist optimizations. + Info: Register "cont[11]" lost all its fanouts during netlist optimizations. + Info: Register "cont[10]" lost all its fanouts during netlist optimizations. + Info: Register "cont[9]" lost all its fanouts during netlist optimizations. + Info: Register "cont[8]" lost all its fanouts during netlist optimizations. +Info: Implemented 476 device resources after synthesis - the final resource count might be different + Info: Implemented 11 input pins + Info: Implemented 96 output pins + Info: Implemented 353 logic cells + Info: Implemented 16 RAM segments +Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning + Info: Peak virtual memory: 194 megabytes + Info: Processing ended: Tue Aug 14 00:26:26 2012 + Info: Elapsed time: 00:00:10 + Info: Total CPU time (on all processors): 00:00:09 + + Index: trunk/QuartusII/gnextrapolator.done =================================================================== --- trunk/QuartusII/gnextrapolator.done (nonexistent) +++ trunk/QuartusII/gnextrapolator.done (revision 5) @@ -0,0 +1 @@ +Tue Aug 14 00:28:19 2012 Index: trunk/QuartusII/gnextrapolator.tan.rpt =================================================================== --- trunk/QuartusII/gnextrapolator.tan.rpt (nonexistent) +++ trunk/QuartusII/gnextrapolator.tan.rpt (revision 5) @@ -0,0 +1,1033 @@ +Classic Timing Analyzer report for gnextrapolator +Tue Aug 14 00:28:18 2012 +Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Timing Analyzer Summary + 3. Timing Analyzer Settings + 4. Clock Settings Summary + 5. Clock Setup: 'clk_i' + 6. tsu + 7. tco + 8. th + 9. Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Timing Analyzer Summary ; ++------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------+-----------------+------------+----------+--------------+ +; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ; ++------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------+-----------------+------------+----------+--------------+ +; Worst-case tsu ; N/A ; None ; 12.402 ns ; extrapolar_i ; resultado[15] ; -- ; clk_i ; 0 ; +; Worst-case tco ; N/A ; None ; 8.310 ns ; fxx3_o[14]~reg0 ; fxx3_o[14] ; clk_i ; -- ; 0 ; +; Worst-case th ; N/A ; None ; -1.094 ns ; rst_i ; fxx1_o[15]~reg0 ; -- ; clk_i ; 0 ; +; Clock Setup: 'clk_i' ; N/A ; None ; 46.88 MHz ( period = 21.332 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[15] ; clk_i ; clk_i ; 0 ; +; Total number of failed paths ; ; ; ; ; ; ; ; 0 ; ++------------------------------+-------+---------------+----------------------------------+-------------------------------------------------------------------------------------+-----------------+------------+----------+--------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------+ +; Timing Analyzer Settings ; ++------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+ +; Option ; Setting ; From ; To ; Entity Name ; ++------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+ +; Device Name ; EP2S15F484C4 ; ; ; ; +; Timing Models ; Final ; ; ; ; +; Default hold multicycle ; Same as Multicycle ; ; ; ; +; Cut paths between unrelated clock domains ; On ; ; ; ; +; Cut off read during write signal paths ; On ; ; ; ; +; Cut off feedback from I/O pins ; On ; ; ; ; +; Report Combined Fast/Slow Timing ; Off ; ; ; ; +; Ignore Clock Settings ; Off ; ; ; ; +; Analyze latches as synchronous elements ; On ; ; ; ; +; Enable Recovery/Removal analysis ; Off ; ; ; ; +; Enable Clock Latency ; Off ; ; ; ; +; Use TimeQuest Timing Analyzer ; Off ; ; ; ; +; Minimum Core Junction Temperature ; 0 ; ; ; ; +; Maximum Core Junction Temperature ; 85 ; ; ; ; +; Number of source nodes to report per destination node ; 10 ; ; ; ; +; Number of destination nodes to report ; 10 ; ; ; ; +; Number of paths to report ; 200 ; ; ; ; +; Report Minimum Timing Checks ; Off ; ; ; ; +; Use Fast Timing Models ; Off ; ; ; ; +; Report IO Paths Separately ; Off ; ; ; ; +; Perform Multicorner Analysis ; On ; ; ; ; +; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ; +; Reports worst-case timing paths for each clock domain and analysis ; Off ; ; ; ; +; Specifies the maximum number of worst-case timing paths to report for each clock domain and analysis ; 100 ; ; ; ; +; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ; +; Output I/O Timing Endpoint ; Near End ; ; ; ; ++------------------------------------------------------------------------------------------------------+--------------------+------+----+-------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Settings Summary ; ++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ +; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ; ++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ +; clk_i ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ; ++-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clock Setup: 'clk_i' ; ++-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------+------------------+------------+----------+-----------------------------+---------------------------+-------------------------+ +; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ; ++-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------+------------------+------------+----------+-----------------------------+---------------------------+-------------------------+ +; N/A ; 46.88 MHz ( period = 21.332 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[15] ; clk_i ; clk_i ; None ; None ; 10.577 ns ; +; N/A ; 46.88 MHz ( period = 21.332 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[15] ; clk_i ; clk_i ; None ; None ; 10.577 ns ; +; N/A ; 46.88 MHz ( period = 21.332 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[15] ; clk_i ; clk_i ; None ; None ; 10.577 ns ; +; N/A ; 46.88 MHz ( period = 21.332 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[15] ; clk_i ; clk_i ; None ; None ; 10.577 ns ; +; N/A ; 46.88 MHz ( period = 21.332 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[15] ; clk_i ; clk_i ; None ; None ; 10.577 ns ; +; N/A ; 48.22 MHz ( period = 20.738 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[14] ; clk_i ; clk_i ; None ; None ; 10.284 ns ; +; N/A ; 48.22 MHz ( period = 20.738 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[14] ; clk_i ; clk_i ; None ; None ; 10.284 ns ; +; N/A ; 48.22 MHz ( period = 20.738 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[14] ; clk_i ; clk_i ; None ; None ; 10.284 ns ; +; N/A ; 48.22 MHz ( period = 20.738 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[14] ; clk_i ; clk_i ; None ; None ; 10.284 ns ; +; N/A ; 48.22 MHz ( period = 20.738 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[14] ; clk_i ; clk_i ; None ; None ; 10.284 ns ; +; N/A ; 49.20 MHz ( period = 20.324 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[13] ; clk_i ; clk_i ; None ; None ; 10.087 ns ; +; N/A ; 49.20 MHz ( period = 20.324 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[13] ; clk_i ; clk_i ; None ; None ; 10.087 ns ; +; N/A ; 49.20 MHz ( period = 20.324 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[13] ; clk_i ; clk_i ; None ; None ; 10.087 ns ; +; N/A ; 49.20 MHz ( period = 20.324 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[13] ; clk_i ; clk_i ; None ; None ; 10.087 ns ; +; N/A ; 49.20 MHz ( period = 20.324 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[13] ; clk_i ; clk_i ; None ; None ; 10.087 ns ; +; N/A ; 50.45 MHz ( period = 19.822 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 9.842 ns ; +; N/A ; 50.45 MHz ( period = 19.822 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 9.842 ns ; +; N/A ; 50.45 MHz ( period = 19.822 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 9.842 ns ; +; N/A ; 50.45 MHz ( period = 19.822 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 9.842 ns ; +; N/A ; 50.45 MHz ( period = 19.822 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 9.842 ns ; +; N/A ; 50.83 MHz ( period = 19.674 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[11]~reg0 ; clk_i ; clk_i ; None ; None ; 9.768 ns ; +; N/A ; 50.83 MHz ( period = 19.674 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[11]~reg0 ; clk_i ; clk_i ; None ; None ; 9.768 ns ; +; N/A ; 50.83 MHz ( period = 19.674 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[11]~reg0 ; clk_i ; clk_i ; None ; None ; 9.768 ns ; +; N/A ; 50.83 MHz ( period = 19.674 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[11]~reg0 ; clk_i ; clk_i ; None ; None ; 9.768 ns ; +; N/A ; 50.83 MHz ( period = 19.674 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[11]~reg0 ; clk_i ; clk_i ; None ; None ; 9.768 ns ; +; N/A ; 50.92 MHz ( period = 19.638 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[8] ; clk_i ; clk_i ; None ; None ; 9.744 ns ; +; N/A ; 50.92 MHz ( period = 19.638 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[8] ; clk_i ; clk_i ; None ; None ; 9.744 ns ; +; N/A ; 50.92 MHz ( period = 19.638 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[8] ; clk_i ; clk_i ; None ; None ; 9.744 ns ; +; N/A ; 50.92 MHz ( period = 19.638 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[8] ; clk_i ; clk_i ; None ; None ; 9.744 ns ; +; N/A ; 50.92 MHz ( period = 19.638 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[8] ; clk_i ; clk_i ; None ; None ; 9.744 ns ; +; N/A ; 51.30 MHz ( period = 19.492 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[9]~reg0 ; clk_i ; clk_i ; None ; None ; 9.677 ns ; +; N/A ; 51.30 MHz ( period = 19.492 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[9]~reg0 ; clk_i ; clk_i ; None ; None ; 9.677 ns ; +; N/A ; 51.30 MHz ( period = 19.492 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[9]~reg0 ; clk_i ; clk_i ; None ; None ; 9.677 ns ; +; N/A ; 51.30 MHz ( period = 19.492 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[9]~reg0 ; clk_i ; clk_i ; None ; None ; 9.677 ns ; +; N/A ; 51.30 MHz ( period = 19.492 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[9]~reg0 ; clk_i ; clk_i ; None ; None ; 9.677 ns ; +; N/A ; 51.78 MHz ( period = 19.314 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[10]~reg0 ; clk_i ; clk_i ; None ; None ; 9.588 ns ; +; N/A ; 51.78 MHz ( period = 19.314 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[10]~reg0 ; clk_i ; clk_i ; None ; None ; 9.588 ns ; +; N/A ; 51.78 MHz ( period = 19.314 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[10]~reg0 ; clk_i ; clk_i ; None ; None ; 9.588 ns ; +; N/A ; 51.78 MHz ( period = 19.314 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[10]~reg0 ; clk_i ; clk_i ; None ; None ; 9.588 ns ; +; N/A ; 51.78 MHz ( period = 19.314 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[10]~reg0 ; clk_i ; clk_i ; None ; None ; 9.588 ns ; +; N/A ; 52.62 MHz ( period = 19.004 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[15]~reg0 ; clk_i ; clk_i ; None ; None ; 9.432 ns ; +; N/A ; 52.62 MHz ( period = 19.004 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[15]~reg0 ; clk_i ; clk_i ; None ; None ; 9.432 ns ; +; N/A ; 52.62 MHz ( period = 19.004 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[15]~reg0 ; clk_i ; clk_i ; None ; None ; 9.432 ns ; +; N/A ; 52.62 MHz ( period = 19.004 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[15]~reg0 ; clk_i ; clk_i ; None ; None ; 9.432 ns ; +; N/A ; 52.62 MHz ( period = 19.004 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[15]~reg0 ; clk_i ; clk_i ; None ; None ; 9.432 ns ; +; N/A ; 52.69 MHz ( period = 18.978 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[5] ; clk_i ; clk_i ; None ; None ; 9.407 ns ; +; N/A ; 52.69 MHz ( period = 18.978 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[5] ; clk_i ; clk_i ; None ; None ; 9.407 ns ; +; N/A ; 52.69 MHz ( period = 18.978 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[5] ; clk_i ; clk_i ; None ; None ; 9.407 ns ; +; N/A ; 52.69 MHz ( period = 18.978 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[5] ; clk_i ; clk_i ; None ; None ; 9.407 ns ; +; N/A ; 52.69 MHz ( period = 18.978 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[5] ; clk_i ; clk_i ; None ; None ; 9.407 ns ; +; N/A ; 52.83 MHz ( period = 18.930 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[4] ; clk_i ; clk_i ; None ; None ; 9.383 ns ; +; N/A ; 52.83 MHz ( period = 18.930 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[4] ; clk_i ; clk_i ; None ; None ; 9.383 ns ; +; N/A ; 52.83 MHz ( period = 18.930 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[4] ; clk_i ; clk_i ; None ; None ; 9.383 ns ; +; N/A ; 52.83 MHz ( period = 18.930 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[4] ; clk_i ; clk_i ; None ; None ; 9.383 ns ; +; N/A ; 52.83 MHz ( period = 18.930 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[4] ; clk_i ; clk_i ; None ; None ; 9.383 ns ; +; N/A ; 52.99 MHz ( period = 18.872 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[6] ; clk_i ; clk_i ; None ; None ; 9.361 ns ; +; N/A ; 52.99 MHz ( period = 18.872 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[6] ; clk_i ; clk_i ; None ; None ; 9.361 ns ; +; N/A ; 52.99 MHz ( period = 18.872 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[6] ; clk_i ; clk_i ; None ; None ; 9.361 ns ; +; N/A ; 52.99 MHz ( period = 18.872 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[6] ; clk_i ; clk_i ; None ; None ; 9.361 ns ; +; N/A ; 52.99 MHz ( period = 18.872 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[6] ; clk_i ; clk_i ; None ; None ; 9.361 ns ; +; N/A ; 53.04 MHz ( period = 18.854 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[7]~reg0 ; clk_i ; clk_i ; None ; None ; 9.358 ns ; +; N/A ; 53.04 MHz ( period = 18.854 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[7]~reg0 ; clk_i ; clk_i ; None ; None ; 9.358 ns ; +; N/A ; 53.04 MHz ( period = 18.854 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[7]~reg0 ; clk_i ; clk_i ; None ; None ; 9.358 ns ; +; N/A ; 53.04 MHz ( period = 18.854 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[7]~reg0 ; clk_i ; clk_i ; None ; None ; 9.358 ns ; +; N/A ; 53.04 MHz ( period = 18.854 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[7]~reg0 ; clk_i ; clk_i ; None ; None ; 9.358 ns ; +; N/A ; 53.12 MHz ( period = 18.826 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[3] ; clk_i ; clk_i ; None ; None ; 9.331 ns ; +; N/A ; 53.12 MHz ( period = 18.826 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[3] ; clk_i ; clk_i ; None ; None ; 9.331 ns ; +; N/A ; 53.12 MHz ( period = 18.826 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[3] ; clk_i ; clk_i ; None ; None ; 9.331 ns ; +; N/A ; 53.12 MHz ( period = 18.826 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[3] ; clk_i ; clk_i ; None ; None ; 9.331 ns ; +; N/A ; 53.12 MHz ( period = 18.826 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[3] ; clk_i ; clk_i ; None ; None ; 9.331 ns ; +; N/A ; 53.13 MHz ( period = 18.822 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[2] ; clk_i ; clk_i ; None ; None ; 9.329 ns ; +; N/A ; 53.13 MHz ( period = 18.822 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[2] ; clk_i ; clk_i ; None ; None ; 9.329 ns ; +; N/A ; 53.13 MHz ( period = 18.822 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[2] ; clk_i ; clk_i ; None ; None ; 9.329 ns ; +; N/A ; 53.13 MHz ( period = 18.822 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[2] ; clk_i ; clk_i ; None ; None ; 9.329 ns ; +; N/A ; 53.13 MHz ( period = 18.822 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[2] ; clk_i ; clk_i ; None ; None ; 9.329 ns ; +; N/A ; 53.28 MHz ( period = 18.770 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[14]~reg0 ; clk_i ; clk_i ; None ; None ; 9.315 ns ; +; N/A ; 53.28 MHz ( period = 18.770 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[14]~reg0 ; clk_i ; clk_i ; None ; None ; 9.315 ns ; +; N/A ; 53.28 MHz ( period = 18.770 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[14]~reg0 ; clk_i ; clk_i ; None ; None ; 9.315 ns ; +; N/A ; 53.28 MHz ( period = 18.770 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[14]~reg0 ; clk_i ; clk_i ; None ; None ; 9.315 ns ; +; N/A ; 53.28 MHz ( period = 18.770 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[14]~reg0 ; clk_i ; clk_i ; None ; None ; 9.315 ns ; +; N/A ; 53.51 MHz ( period = 18.688 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[13]~reg0 ; clk_i ; clk_i ; None ; None ; 9.274 ns ; +; N/A ; 53.51 MHz ( period = 18.688 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[13]~reg0 ; clk_i ; clk_i ; None ; None ; 9.274 ns ; +; N/A ; 53.51 MHz ( period = 18.688 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[13]~reg0 ; clk_i ; clk_i ; None ; None ; 9.274 ns ; +; N/A ; 53.51 MHz ( period = 18.688 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[13]~reg0 ; clk_i ; clk_i ; None ; None ; 9.274 ns ; +; N/A ; 53.51 MHz ( period = 18.688 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[13]~reg0 ; clk_i ; clk_i ; None ; None ; 9.274 ns ; +; N/A ; 53.90 MHz ( period = 18.554 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[12] ; clk_i ; clk_i ; None ; None ; 9.207 ns ; +; N/A ; 53.90 MHz ( period = 18.554 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[12] ; clk_i ; clk_i ; None ; None ; 9.207 ns ; +; N/A ; 53.90 MHz ( period = 18.554 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[12] ; clk_i ; clk_i ; None ; None ; 9.207 ns ; +; N/A ; 53.90 MHz ( period = 18.554 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[12] ; clk_i ; clk_i ; None ; None ; 9.207 ns ; +; N/A ; 53.90 MHz ( period = 18.554 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[12] ; clk_i ; clk_i ; None ; None ; 9.207 ns ; +; N/A ; 54.31 MHz ( period = 18.414 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[11] ; clk_i ; clk_i ; None ; None ; 9.137 ns ; +; N/A ; 54.31 MHz ( period = 18.414 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[11] ; clk_i ; clk_i ; None ; None ; 9.137 ns ; +; N/A ; 54.31 MHz ( period = 18.414 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[11] ; clk_i ; clk_i ; None ; None ; 9.137 ns ; +; N/A ; 54.31 MHz ( period = 18.414 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[11] ; clk_i ; clk_i ; None ; None ; 9.137 ns ; +; N/A ; 54.31 MHz ( period = 18.414 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[11] ; clk_i ; clk_i ; None ; None ; 9.137 ns ; +; N/A ; 54.56 MHz ( period = 18.328 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[10] ; clk_i ; clk_i ; None ; None ; 9.094 ns ; +; N/A ; 54.56 MHz ( period = 18.328 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[10] ; clk_i ; clk_i ; None ; None ; 9.094 ns ; +; N/A ; 54.56 MHz ( period = 18.328 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[10] ; clk_i ; clk_i ; None ; None ; 9.094 ns ; +; N/A ; 54.56 MHz ( period = 18.328 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[10] ; clk_i ; clk_i ; None ; None ; 9.094 ns ; +; N/A ; 54.56 MHz ( period = 18.328 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[10] ; clk_i ; clk_i ; None ; None ; 9.094 ns ; +; N/A ; 54.71 MHz ( period = 18.278 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[1] ; clk_i ; clk_i ; None ; None ; 9.061 ns ; +; N/A ; 54.71 MHz ( period = 18.278 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[1] ; clk_i ; clk_i ; None ; None ; 9.061 ns ; +; N/A ; 54.71 MHz ( period = 18.278 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[1] ; clk_i ; clk_i ; None ; None ; 9.061 ns ; +; N/A ; 54.71 MHz ( period = 18.278 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[1] ; clk_i ; clk_i ; None ; None ; 9.061 ns ; +; N/A ; 54.71 MHz ( period = 18.278 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[1] ; clk_i ; clk_i ; None ; None ; 9.061 ns ; +; N/A ; 54.81 MHz ( period = 18.246 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[9] ; clk_i ; clk_i ; None ; None ; 9.053 ns ; +; N/A ; 54.81 MHz ( period = 18.246 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[9] ; clk_i ; clk_i ; None ; None ; 9.053 ns ; +; N/A ; 54.81 MHz ( period = 18.246 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[9] ; clk_i ; clk_i ; None ; None ; 9.053 ns ; +; N/A ; 54.81 MHz ( period = 18.246 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[9] ; clk_i ; clk_i ; None ; None ; 9.053 ns ; +; N/A ; 54.81 MHz ( period = 18.246 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[9] ; clk_i ; clk_i ; None ; None ; 9.053 ns ; +; N/A ; 55.10 MHz ( period = 18.148 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[8]~reg0 ; clk_i ; clk_i ; None ; None ; 9.004 ns ; +; N/A ; 55.10 MHz ( period = 18.148 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[8]~reg0 ; clk_i ; clk_i ; None ; None ; 9.004 ns ; +; N/A ; 55.10 MHz ( period = 18.148 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[8]~reg0 ; clk_i ; clk_i ; None ; None ; 9.004 ns ; +; N/A ; 55.10 MHz ( period = 18.148 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[8]~reg0 ; clk_i ; clk_i ; None ; None ; 9.004 ns ; +; N/A ; 55.10 MHz ( period = 18.148 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[8]~reg0 ; clk_i ; clk_i ; None ; None ; 9.004 ns ; +; N/A ; 55.71 MHz ( period = 17.950 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[0] ; clk_i ; clk_i ; None ; None ; 8.897 ns ; +; N/A ; 55.71 MHz ( period = 17.950 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[0] ; clk_i ; clk_i ; None ; None ; 8.897 ns ; +; N/A ; 55.71 MHz ( period = 17.950 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[0] ; clk_i ; clk_i ; None ; None ; 8.897 ns ; +; N/A ; 55.71 MHz ( period = 17.950 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[0] ; clk_i ; clk_i ; None ; None ; 8.897 ns ; +; N/A ; 55.71 MHz ( period = 17.950 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[0] ; clk_i ; clk_i ; None ; None ; 8.897 ns ; +; N/A ; 55.98 MHz ( period = 17.862 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resultado[7] ; clk_i ; clk_i ; None ; None ; 8.861 ns ; +; N/A ; 55.98 MHz ( period = 17.862 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resultado[7] ; clk_i ; clk_i ; None ; None ; 8.861 ns ; +; N/A ; 55.98 MHz ( period = 17.862 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resultado[7] ; clk_i ; clk_i ; None ; None ; 8.861 ns ; +; N/A ; 55.98 MHz ( period = 17.862 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resultado[7] ; clk_i ; clk_i ; None ; None ; 8.861 ns ; +; N/A ; 55.98 MHz ( period = 17.862 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resultado[7] ; clk_i ; clk_i ; None ; None ; 8.861 ns ; +; N/A ; 58.12 MHz ( period = 17.206 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[6]~reg0 ; clk_i ; clk_i ; None ; None ; 8.533 ns ; +; N/A ; 58.12 MHz ( period = 17.206 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[6]~reg0 ; clk_i ; clk_i ; None ; None ; 8.533 ns ; +; N/A ; 58.12 MHz ( period = 17.206 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[6]~reg0 ; clk_i ; clk_i ; None ; None ; 8.533 ns ; +; N/A ; 58.12 MHz ( period = 17.206 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[6]~reg0 ; clk_i ; clk_i ; None ; None ; 8.533 ns ; +; N/A ; 58.12 MHz ( period = 17.206 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[6]~reg0 ; clk_i ; clk_i ; None ; None ; 8.533 ns ; +; N/A ; 59.72 MHz ( period = 16.746 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[5]~reg0 ; clk_i ; clk_i ; None ; None ; 8.303 ns ; +; N/A ; 59.72 MHz ( period = 16.746 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[5]~reg0 ; clk_i ; clk_i ; None ; None ; 8.303 ns ; +; N/A ; 59.72 MHz ( period = 16.746 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[5]~reg0 ; clk_i ; clk_i ; None ; None ; 8.303 ns ; +; N/A ; 59.72 MHz ( period = 16.746 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[5]~reg0 ; clk_i ; clk_i ; None ; None ; 8.303 ns ; +; N/A ; 59.72 MHz ( period = 16.746 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[5]~reg0 ; clk_i ; clk_i ; None ; None ; 8.303 ns ; +; N/A ; 60.01 MHz ( period = 16.664 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; fxx4_o[15]~reg0 ; clk_i ; clk_i ; None ; None ; 8.257 ns ; +; N/A ; 60.01 MHz ( period = 16.664 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; fxx4_o[15]~reg0 ; clk_i ; clk_i ; None ; None ; 8.257 ns ; +; N/A ; 60.01 MHz ( period = 16.664 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; fxx4_o[15]~reg0 ; clk_i ; clk_i ; None ; None ; 8.257 ns ; +; N/A ; 60.01 MHz ( period = 16.664 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; fxx4_o[15]~reg0 ; clk_i ; clk_i ; None ; None ; 8.257 ns ; +; N/A ; 60.01 MHz ( period = 16.664 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; fxx4_o[15]~reg0 ; clk_i ; clk_i ; None ; None ; 8.257 ns ; +; N/A ; 60.01 MHz ( period = 16.664 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[4]~reg0 ; clk_i ; clk_i ; None ; None ; 8.262 ns ; +; N/A ; 60.01 MHz ( period = 16.664 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[4]~reg0 ; clk_i ; clk_i ; None ; None ; 8.262 ns ; +; N/A ; 60.01 MHz ( period = 16.664 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[4]~reg0 ; clk_i ; clk_i ; None ; None ; 8.262 ns ; +; N/A ; 60.01 MHz ( period = 16.664 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[4]~reg0 ; clk_i ; clk_i ; None ; None ; 8.262 ns ; +; N/A ; 60.01 MHz ( period = 16.664 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[4]~reg0 ; clk_i ; clk_i ; None ; None ; 8.262 ns ; +; N/A ; 60.31 MHz ( period = 16.582 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[3]~reg0 ; clk_i ; clk_i ; None ; None ; 8.221 ns ; +; N/A ; 60.31 MHz ( period = 16.582 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[3]~reg0 ; clk_i ; clk_i ; None ; None ; 8.221 ns ; +; N/A ; 60.31 MHz ( period = 16.582 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[3]~reg0 ; clk_i ; clk_i ; None ; None ; 8.221 ns ; +; N/A ; 60.31 MHz ( period = 16.582 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[3]~reg0 ; clk_i ; clk_i ; None ; None ; 8.221 ns ; +; N/A ; 60.31 MHz ( period = 16.582 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[3]~reg0 ; clk_i ; clk_i ; None ; None ; 8.221 ns ; +; N/A ; 60.61 MHz ( period = 16.500 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[2]~reg0 ; clk_i ; clk_i ; None ; None ; 8.180 ns ; +; N/A ; 60.61 MHz ( period = 16.500 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[2]~reg0 ; clk_i ; clk_i ; None ; None ; 8.180 ns ; +; N/A ; 60.61 MHz ( period = 16.500 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[2]~reg0 ; clk_i ; clk_i ; None ; None ; 8.180 ns ; +; N/A ; 60.61 MHz ( period = 16.500 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[2]~reg0 ; clk_i ; clk_i ; None ; None ; 8.180 ns ; +; N/A ; 60.61 MHz ( period = 16.500 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[2]~reg0 ; clk_i ; clk_i ; None ; None ; 8.180 ns ; +; N/A ; 61.06 MHz ( period = 16.378 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; fxx4_o[14]~reg0 ; clk_i ; clk_i ; None ; None ; 8.114 ns ; +; N/A ; 61.06 MHz ( period = 16.378 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; fxx4_o[14]~reg0 ; clk_i ; clk_i ; None ; None ; 8.114 ns ; +; N/A ; 61.06 MHz ( period = 16.378 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; fxx4_o[14]~reg0 ; clk_i ; clk_i ; None ; None ; 8.114 ns ; +; N/A ; 61.06 MHz ( period = 16.378 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; fxx4_o[14]~reg0 ; clk_i ; clk_i ; None ; None ; 8.114 ns ; +; N/A ; 61.06 MHz ( period = 16.378 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; fxx4_o[14]~reg0 ; clk_i ; clk_i ; None ; None ; 8.114 ns ; +; N/A ; 61.10 MHz ( period = 16.366 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; resul_o[1]~reg0 ; clk_i ; clk_i ; None ; None ; 8.113 ns ; +; N/A ; 61.10 MHz ( period = 16.366 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; resul_o[1]~reg0 ; clk_i ; clk_i ; None ; None ; 8.113 ns ; +; N/A ; 61.10 MHz ( period = 16.366 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; resul_o[1]~reg0 ; clk_i ; clk_i ; None ; None ; 8.113 ns ; +; N/A ; 61.10 MHz ( period = 16.366 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; resul_o[1]~reg0 ; clk_i ; clk_i ; None ; None ; 8.113 ns ; +; N/A ; 61.10 MHz ( period = 16.366 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; resul_o[1]~reg0 ; clk_i ; clk_i ; None ; None ; 8.113 ns ; +; N/A ; 61.36 MHz ( period = 16.296 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; fxx4_o[13]~reg0 ; clk_i ; clk_i ; None ; None ; 8.073 ns ; +; N/A ; 61.36 MHz ( period = 16.296 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; fxx4_o[13]~reg0 ; clk_i ; clk_i ; None ; None ; 8.073 ns ; +; N/A ; 61.36 MHz ( period = 16.296 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; fxx4_o[13]~reg0 ; clk_i ; clk_i ; None ; None ; 8.073 ns ; +; N/A ; 61.36 MHz ( period = 16.296 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; fxx4_o[13]~reg0 ; clk_i ; clk_i ; None ; None ; 8.073 ns ; +; N/A ; 61.36 MHz ( period = 16.296 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; fxx4_o[13]~reg0 ; clk_i ; clk_i ; None ; None ; 8.073 ns ; +; N/A ; 61.68 MHz ( period = 16.214 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; fxx4_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 8.032 ns ; +; N/A ; 61.68 MHz ( period = 16.214 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; fxx4_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 8.032 ns ; +; N/A ; 61.68 MHz ( period = 16.214 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; fxx4_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 8.032 ns ; +; N/A ; 61.68 MHz ( period = 16.214 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; fxx4_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 8.032 ns ; +; N/A ; 61.68 MHz ( period = 16.214 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; fxx4_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 8.032 ns ; +; N/A ; 61.99 MHz ( period = 16.132 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; fxx4_o[11]~reg0 ; clk_i ; clk_i ; None ; None ; 7.991 ns ; +; N/A ; 61.99 MHz ( period = 16.132 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; fxx4_o[11]~reg0 ; clk_i ; clk_i ; None ; None ; 7.991 ns ; +; N/A ; 61.99 MHz ( period = 16.132 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; fxx4_o[11]~reg0 ; clk_i ; clk_i ; None ; None ; 7.991 ns ; +; N/A ; 61.99 MHz ( period = 16.132 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; fxx4_o[11]~reg0 ; clk_i ; clk_i ; None ; None ; 7.991 ns ; +; N/A ; 61.99 MHz ( period = 16.132 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; fxx4_o[11]~reg0 ; clk_i ; clk_i ; None ; None ; 7.991 ns ; +; N/A ; 62.31 MHz ( period = 16.050 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; fxx4_o[10]~reg0 ; clk_i ; clk_i ; None ; None ; 7.950 ns ; +; N/A ; 62.31 MHz ( period = 16.050 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; fxx4_o[10]~reg0 ; clk_i ; clk_i ; None ; None ; 7.950 ns ; +; N/A ; 62.31 MHz ( period = 16.050 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; fxx4_o[10]~reg0 ; clk_i ; clk_i ; None ; None ; 7.950 ns ; +; N/A ; 62.31 MHz ( period = 16.050 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; fxx4_o[10]~reg0 ; clk_i ; clk_i ; None ; None ; 7.950 ns ; +; N/A ; 62.31 MHz ( period = 16.050 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; fxx4_o[10]~reg0 ; clk_i ; clk_i ; None ; None ; 7.950 ns ; +; N/A ; 62.63 MHz ( period = 15.968 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; fxx4_o[9]~reg0 ; clk_i ; clk_i ; None ; None ; 7.909 ns ; +; N/A ; 62.63 MHz ( period = 15.968 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; fxx4_o[9]~reg0 ; clk_i ; clk_i ; None ; None ; 7.909 ns ; +; N/A ; 62.63 MHz ( period = 15.968 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; fxx4_o[9]~reg0 ; clk_i ; clk_i ; None ; None ; 7.909 ns ; +; N/A ; 62.63 MHz ( period = 15.968 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; fxx4_o[9]~reg0 ; clk_i ; clk_i ; None ; None ; 7.909 ns ; +; N/A ; 62.63 MHz ( period = 15.968 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; fxx4_o[9]~reg0 ; clk_i ; clk_i ; None ; None ; 7.909 ns ; +; N/A ; 62.84 MHz ( period = 15.914 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; fxx3_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 7.886 ns ; +; N/A ; 62.84 MHz ( period = 15.914 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; fxx3_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 7.886 ns ; +; N/A ; 62.84 MHz ( period = 15.914 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; fxx3_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 7.886 ns ; +; N/A ; 62.84 MHz ( period = 15.914 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; fxx3_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 7.886 ns ; +; N/A ; 62.84 MHz ( period = 15.914 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; fxx3_o[12]~reg0 ; clk_i ; clk_i ; None ; None ; 7.886 ns ; +; N/A ; 62.95 MHz ( period = 15.886 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0 ; fxx4_o[8]~reg0 ; clk_i ; clk_i ; None ; None ; 7.868 ns ; +; N/A ; 62.95 MHz ( period = 15.886 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg1 ; fxx4_o[8]~reg0 ; clk_i ; clk_i ; None ; None ; 7.868 ns ; +; N/A ; 62.95 MHz ( period = 15.886 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg2 ; fxx4_o[8]~reg0 ; clk_i ; clk_i ; None ; None ; 7.868 ns ; +; N/A ; 62.95 MHz ( period = 15.886 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg3 ; fxx4_o[8]~reg0 ; clk_i ; clk_i ; None ; None ; 7.868 ns ; +; N/A ; 62.95 MHz ( period = 15.886 ns ) ; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg4 ; fxx4_o[8]~reg0 ; clk_i ; clk_i ; None ; None ; 7.868 ns ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+-------------------------------------------------------------------------------------+------------------+------------+----------+-----------------------------+---------------------------+-------------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; tsu ; ++-----------------------------------------+-----------------------------------------------------+------------+----------------+------------------+----------+ +; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ; ++-----------------------------------------+-----------------------------------------------------+------------+----------------+------------------+----------+ +; N/A ; None ; 12.402 ns ; extrapolar_i ; resultado[15] ; clk_i ; +; N/A ; None ; 12.105 ns ; extrapolar_i ; resultado[14] ; clk_i ; +; N/A ; None ; 11.898 ns ; extrapolar_i ; resultado[13] ; clk_i ; +; N/A ; None ; 11.647 ns ; extrapolar_i ; resul_o[12]~reg0 ; clk_i ; +; N/A ; None ; 11.573 ns ; extrapolar_i ; resul_o[11]~reg0 ; clk_i ; +; N/A ; None ; 11.555 ns ; extrapolar_i ; resultado[8] ; clk_i ; +; N/A ; None ; 11.482 ns ; extrapolar_i ; resul_o[9]~reg0 ; clk_i ; +; N/A ; None ; 11.411 ns ; extrapolar_i ; resultado[6] ; clk_i ; +; N/A ; None ; 11.393 ns ; extrapolar_i ; resul_o[10]~reg0 ; clk_i ; +; N/A ; None ; 11.238 ns ; extrapolar_i ; resul_o[15]~reg0 ; clk_i ; +; N/A ; None ; 11.163 ns ; extrapolar_i ; resul_o[7]~reg0 ; clk_i ; +; N/A ; None ; 11.121 ns ; extrapolar_i ; resul_o[14]~reg0 ; clk_i ; +; N/A ; None ; 11.080 ns ; extrapolar_i ; resul_o[13]~reg0 ; clk_i ; +; N/A ; None ; 11.013 ns ; extrapolar_i ; resultado[12] ; clk_i ; +; N/A ; None ; 10.943 ns ; extrapolar_i ; resultado[11] ; clk_i ; +; N/A ; None ; 10.900 ns ; extrapolar_i ; resultado[10] ; clk_i ; +; N/A ; None ; 10.859 ns ; extrapolar_i ; resultado[9] ; clk_i ; +; N/A ; None ; 10.810 ns ; extrapolar_i ; resul_o[8]~reg0 ; clk_i ; +; N/A ; None ; 10.742 ns ; extrapolar_i ; resultado[5] ; clk_i ; +; N/A ; None ; 10.718 ns ; extrapolar_i ; resultado[4] ; clk_i ; +; N/A ; None ; 10.667 ns ; extrapolar_i ; resultado[7] ; clk_i ; +; N/A ; None ; 10.666 ns ; extrapolar_i ; resultado[3] ; clk_i ; +; N/A ; None ; 10.664 ns ; extrapolar_i ; resultado[2] ; clk_i ; +; N/A ; None ; 10.578 ns ; extrapolar_i ; resul_o[6]~reg0 ; clk_i ; +; N/A ; None ; 10.392 ns ; extrapolar_i ; resultado[1] ; clk_i ; +; N/A ; None ; 10.228 ns ; extrapolar_i ; resultado[0] ; clk_i ; +; N/A ; None ; 10.068 ns ; extrapolar_i ; fxx4_o[15]~reg0 ; clk_i ; +; N/A ; None ; 9.925 ns ; extrapolar_i ; fxx4_o[14]~reg0 ; clk_i ; +; N/A ; None ; 9.884 ns ; extrapolar_i ; fxx4_o[13]~reg0 ; clk_i ; +; N/A ; None ; 9.843 ns ; extrapolar_i ; fxx4_o[12]~reg0 ; clk_i ; +; N/A ; None ; 9.802 ns ; extrapolar_i ; fxx4_o[11]~reg0 ; clk_i ; +; N/A ; None ; 9.761 ns ; extrapolar_i ; fxx4_o[10]~reg0 ; clk_i ; +; N/A ; None ; 9.720 ns ; extrapolar_i ; fxx4_o[9]~reg0 ; clk_i ; +; N/A ; None ; 9.693 ns ; extrapolar_i ; fxx3_o[12]~reg0 ; clk_i ; +; N/A ; None ; 9.679 ns ; extrapolar_i ; fxx4_o[8]~reg0 ; clk_i ; +; N/A ; None ; 9.626 ns ; extrapolar_i ; resul_o[5]~reg0 ; clk_i ; +; N/A ; None ; 9.612 ns ; extrapolar_i ; fxx4_o[7]~reg0 ; clk_i ; +; N/A ; None ; 9.607 ns ; extrapolar_i ; fxx3_o[10]~reg0 ; clk_i ; +; N/A ; None ; 9.585 ns ; extrapolar_i ; resul_o[4]~reg0 ; clk_i ; +; N/A ; None ; 9.544 ns ; extrapolar_i ; resul_o[3]~reg0 ; clk_i ; +; N/A ; None ; 9.503 ns ; extrapolar_i ; resul_o[2]~reg0 ; clk_i ; +; N/A ; None ; 9.498 ns ; extrapolar_i ; nabla3fx[0][14] ; clk_i ; +; N/A ; None ; 9.436 ns ; extrapolar_i ; resul_o[1]~reg0 ; clk_i ; +; N/A ; None ; 9.415 ns ; extrapolar_i ; fxx3_o[15]~reg0 ; clk_i ; +; N/A ; None ; 9.375 ns ; extrapolar_i ; nabla3fx[0][11] ; clk_i ; +; N/A ; None ; 9.336 ns ; extrapolar_i ; fxx3_o[13]~reg0 ; clk_i ; +; N/A ; None ; 9.298 ns ; extrapolar_i ; nabla3fx[0][9] ; clk_i ; +; N/A ; None ; 9.128 ns ; extrapolar_i ; nabla3fx[0][8] ; clk_i ; +; N/A ; None ; 9.118 ns ; extrapolar_i ; resul_o[0]~reg0 ; clk_i ; +; N/A ; None ; 9.015 ns ; extrapolar_i ; fxx4_o[6]~reg0 ; clk_i ; +; N/A ; None ; 8.984 ns ; extrapolar_i ; nabla3fx[0][15] ; clk_i ; +; N/A ; None ; 8.943 ns ; extrapolar_i ; fxx3_o[14]~reg0 ; clk_i ; +; N/A ; None ; 8.902 ns ; extrapolar_i ; nabla3fx[0][13] ; clk_i ; +; N/A ; None ; 8.861 ns ; extrapolar_i ; nabla3fx[0][12] ; clk_i ; +; N/A ; None ; 8.850 ns ; extrapolar_i ; fxx3_o[7]~reg0 ; clk_i ; +; N/A ; None ; 8.841 ns ; extrapolar_i ; fxx2_o[13]~reg0 ; clk_i ; +; N/A ; None ; 8.820 ns ; extrapolar_i ; fxx3_o[11]~reg0 ; clk_i ; +; N/A ; None ; 8.779 ns ; extrapolar_i ; nabla3fx[0][10] ; clk_i ; +; N/A ; None ; 8.772 ns ; extrapolar_i ; fxx2_o[15]~reg0 ; clk_i ; +; N/A ; None ; 8.758 ns ; extrapolar_i ; nabla3fx[0][6] ; clk_i ; +; N/A ; None ; 8.738 ns ; extrapolar_i ; fxx3_o[9]~reg0 ; clk_i ; +; N/A ; None ; 8.726 ns ; extrapolar_i ; fxx2_o[14]~reg0 ; clk_i ; +; N/A ; None ; 8.697 ns ; extrapolar_i ; fxx3_o[8]~reg0 ; clk_i ; +; N/A ; None ; 8.674 ns ; extrapolar_i ; fxx2_o[10]~reg0 ; clk_i ; +; N/A ; None ; 8.628 ns ; extrapolar_i ; fxx2_o[12]~reg0 ; clk_i ; +; N/A ; None ; 8.610 ns ; extrapolar_i ; fxx2_o[8]~reg0 ; clk_i ; +; N/A ; None ; 8.490 ns ; extrapolar_i ; nabla2fx[0][11] ; clk_i ; +; N/A ; None ; 8.422 ns ; extrapolar_i ; nabla2fx[0][9] ; clk_i ; +; N/A ; None ; 8.416 ns ; extrapolar_i ; nabla3fx[0][7] ; clk_i ; +; N/A ; None ; 8.202 ns ; extrapolar_i ; fxx3_o[6]~reg0 ; clk_i ; +; N/A ; None ; 7.921 ns ; extrapolar_i ; fxx1_o[14]~reg0 ; clk_i ; +; N/A ; None ; 7.906 ns ; extrapolar_i ; cont[3] ; clk_i ; +; N/A ; None ; 7.906 ns ; extrapolar_i ; cont[2] ; clk_i ; +; N/A ; None ; 7.906 ns ; extrapolar_i ; cont[7] ; clk_i ; +; N/A ; None ; 7.906 ns ; extrapolar_i ; cont[6] ; clk_i ; +; N/A ; None ; 7.906 ns ; extrapolar_i ; cont[1] ; clk_i ; +; N/A ; None ; 7.906 ns ; extrapolar_i ; cont[0] ; clk_i ; +; N/A ; None ; 7.906 ns ; extrapolar_i ; cont[4] ; clk_i ; +; N/A ; None ; 7.906 ns ; extrapolar_i ; cont[5] ; clk_i ; +; N/A ; None ; 7.802 ns ; extrapolar_i ; fxx4_o[5]~reg0 ; clk_i ; +; N/A ; None ; 7.760 ns ; extrapolar_i ; fxx2_o[7]~reg0 ; clk_i ; +; N/A ; None ; 7.753 ns ; extrapolar_i ; nabla2fx[0][15] ; clk_i ; +; N/A ; None ; 7.746 ns ; extrapolar_i ; fxx4_o[4]~reg0 ; clk_i ; +; N/A ; None ; 7.723 ns ; extrapolar_i ; fxx1_o[11]~reg0 ; clk_i ; +; N/A ; None ; 7.682 ns ; extrapolar_i ; fxx4_o[3]~reg0 ; clk_i ; +; N/A ; None ; 7.650 ns ; extrapolar_i ; fxx3_o[3]~reg0 ; clk_i ; +; N/A ; None ; 7.642 ns ; extrapolar_i ; nabla2fx[0][14] ; clk_i ; +; N/A ; None ; 7.641 ns ; extrapolar_i ; fxx4_o[2]~reg0 ; clk_i ; +; N/A ; None ; 7.620 ns ; extrapolar_i ; nabla1fx[0][7] ; clk_i ; +; N/A ; None ; 7.601 ns ; extrapolar_i ; nabla2fx[0][13] ; clk_i ; +; N/A ; None ; 7.595 ns ; extrapolar_i ; fxx3_o[2]~reg0 ; clk_i ; +; N/A ; None ; 7.574 ns ; extrapolar_i ; fxx4_o[1]~reg0 ; clk_i ; +; N/A ; None ; 7.560 ns ; extrapolar_i ; nabla2fx[0][12] ; clk_i ; +; N/A ; None ; 7.547 ns ; extrapolar_i ; fxx3_o[1]~reg0 ; clk_i ; +; N/A ; None ; 7.519 ns ; extrapolar_i ; fxx2_o[11]~reg0 ; clk_i ; +; N/A ; None ; 7.508 ns ; extrapolar_i ; fxx1_o[9]~reg0 ; clk_i ; +; N/A ; None ; 7.478 ns ; extrapolar_i ; nabla2fx[0][10] ; clk_i ; +; N/A ; None ; 7.457 ns ; extrapolar_i ; nabla2fx[0][6] ; clk_i ; +; N/A ; None ; 7.443 ns ; extrapolar_i ; nabla1fx[0][15] ; clk_i ; +; N/A ; None ; 7.437 ns ; extrapolar_i ; fxx2_o[9]~reg0 ; clk_i ; +; N/A ; None ; 7.428 ns ; extrapolar_i ; fxx4_o[0]~reg0 ; clk_i ; +; N/A ; None ; 7.413 ns ; extrapolar_i ; nabla3fx[0][4] ; clk_i ; +; N/A ; None ; 7.396 ns ; extrapolar_i ; nabla2fx[0][8] ; clk_i ; +; N/A ; None ; 7.354 ns ; extrapolar_i ; nabla1fx[0][10] ; clk_i ; +; N/A ; None ; 7.341 ns ; extrapolar_i ; fxx3_o[5]~reg0 ; clk_i ; +; N/A ; None ; 7.323 ns ; extrapolar_i ; nabla2fx[0][7] ; clk_i ; +; N/A ; None ; 7.229 ns ; extrapolar_i ; nabla1fx[0][12] ; clk_i ; +; N/A ; None ; 7.154 ns ; extrapolar_i ; nabla1fx[0][13] ; clk_i ; +; N/A ; None ; 7.056 ns ; extrapolar_i ; nabla3fx[0][0] ; clk_i ; +; N/A ; None ; 7.023 ns ; extrapolar_i ; fxx2_o[6]~reg0 ; clk_i ; +; N/A ; None ; 6.946 ns ; extrapolar_i ; nabla1fx[0][8] ; clk_i ; +; N/A ; None ; 6.911 ns ; extrapolar_i ; fxx1_o[6]~reg0 ; clk_i ; +; N/A ; None ; 6.908 ns ; extrapolar_i ; nabla3fx[0][5] ; clk_i ; +; N/A ; None ; 6.870 ns ; extrapolar_i ; fxx2_o[3]~reg0 ; clk_i ; +; N/A ; None ; 6.859 ns ; extrapolar_i ; fxx3_o[4]~reg0 ; clk_i ; +; N/A ; None ; 6.818 ns ; extrapolar_i ; nabla3fx[0][3] ; clk_i ; +; N/A ; None ; 6.777 ns ; extrapolar_i ; nabla3fx[0][2] ; clk_i ; +; N/A ; None ; 6.716 ns ; extrapolar_i ; fxx1_o[15]~reg0 ; clk_i ; +; N/A ; None ; 6.710 ns ; extrapolar_i ; nabla3fx[0][1] ; clk_i ; +; N/A ; None ; 6.675 ns ; extrapolar_i ; nabla1fx[0][14] ; clk_i ; +; N/A ; None ; 6.634 ns ; extrapolar_i ; fxx1_o[13]~reg0 ; clk_i ; +; N/A ; None ; 6.619 ns ; extrapolar_i ; fxx3_o[0]~reg0 ; clk_i ; +; N/A ; None ; 6.593 ns ; extrapolar_i ; fxx1_o[12]~reg0 ; clk_i ; +; N/A ; None ; 6.552 ns ; extrapolar_i ; nabla1fx[0][11] ; clk_i ; +; N/A ; None ; 6.511 ns ; extrapolar_i ; fxx1_o[10]~reg0 ; clk_i ; +; N/A ; None ; 6.470 ns ; extrapolar_i ; nabla1fx[0][9] ; clk_i ; +; N/A ; None ; 6.455 ns ; distancia_i[4] ; resul_o[0]~reg0 ; clk_i ; +; N/A ; None ; 6.455 ns ; distancia_i[4] ; resul_o[1]~reg0 ; clk_i ; +; N/A ; None ; 6.455 ns ; distancia_i[4] ; resul_o[2]~reg0 ; clk_i ; +; N/A ; None ; 6.455 ns ; distancia_i[4] ; resul_o[3]~reg0 ; clk_i ; +; N/A ; None ; 6.455 ns ; distancia_i[4] ; resul_o[4]~reg0 ; clk_i ; +; N/A ; None ; 6.455 ns ; distancia_i[4] ; resul_o[5]~reg0 ; clk_i ; +; N/A ; None ; 6.455 ns ; distancia_i[4] ; resul_o[6]~reg0 ; clk_i ; +; N/A ; None ; 6.455 ns ; distancia_i[4] ; resul_o[8]~reg0 ; clk_i ; +; N/A ; None ; 6.455 ns ; distancia_i[4] ; resul_o[13]~reg0 ; clk_i ; +; N/A ; None ; 6.455 ns ; distancia_i[4] ; resul_o[14]~reg0 ; clk_i ; +; N/A ; None ; 6.455 ns ; distancia_i[4] ; resul_o[15]~reg0 ; clk_i ; +; N/A ; None ; 6.429 ns ; extrapolar_i ; fxx1_o[8]~reg0 ; clk_i ; +; N/A ; None ; 6.376 ns ; extrapolar_i ; nabla2fx[0][0] ; clk_i ; +; N/A ; None ; 6.296 ns ; distancia_i[5] ; resul_o[0]~reg0 ; clk_i ; +; N/A ; None ; 6.296 ns ; distancia_i[5] ; resul_o[1]~reg0 ; clk_i ; +; N/A ; None ; 6.296 ns ; distancia_i[5] ; resul_o[2]~reg0 ; clk_i ; +; N/A ; None ; 6.296 ns ; distancia_i[5] ; resul_o[3]~reg0 ; clk_i ; +; N/A ; None ; 6.296 ns ; distancia_i[5] ; resul_o[4]~reg0 ; clk_i ; +; N/A ; None ; 6.296 ns ; distancia_i[5] ; resul_o[5]~reg0 ; clk_i ; +; N/A ; None ; 6.296 ns ; distancia_i[5] ; resul_o[6]~reg0 ; clk_i ; +; N/A ; None ; 6.296 ns ; distancia_i[5] ; resul_o[8]~reg0 ; clk_i ; +; N/A ; None ; 6.296 ns ; distancia_i[5] ; resul_o[13]~reg0 ; clk_i ; +; N/A ; None ; 6.296 ns ; distancia_i[5] ; resul_o[14]~reg0 ; clk_i ; +; N/A ; None ; 6.296 ns ; distancia_i[5] ; resul_o[15]~reg0 ; clk_i ; +; N/A ; None ; 6.275 ns ; extrapolar_i ; fxx1_o[2]~reg0 ; clk_i ; +; N/A ; None ; 6.272 ns ; extrapolar_i ; nabla2fx[0][5] ; clk_i ; +; N/A ; None ; 6.218 ns ; extrapolar_i ; fxx1_o[7]~reg0 ; clk_i ; +; N/A ; None ; 6.151 ns ; extrapolar_i ; nabla1fx[0][6] ; clk_i ; +; N/A ; None ; 6.150 ns ; distancia_i[4] ; resul_o[7]~reg0 ; clk_i ; +; N/A ; None ; 6.150 ns ; distancia_i[4] ; resul_o[9]~reg0 ; clk_i ; +; N/A ; None ; 6.150 ns ; distancia_i[4] ; resul_o[10]~reg0 ; clk_i ; +; N/A ; None ; 6.150 ns ; distancia_i[4] ; resul_o[11]~reg0 ; clk_i ; +; N/A ; None ; 6.150 ns ; distancia_i[4] ; resul_o[12]~reg0 ; clk_i ; +; N/A ; None ; 6.113 ns ; extrapolar_i ; nabla2fx[0][4] ; clk_i ; +; N/A ; None ; 6.092 ns ; extrapolar_i ; nabla2fx[0][2] ; clk_i ; +; N/A ; None ; 6.075 ns ; extrapolar_i ; fxx1_o[1]~reg0 ; clk_i ; +; N/A ; None ; 6.056 ns ; distancia_i[4] ; cont[3] ; clk_i ; +; N/A ; None ; 6.056 ns ; distancia_i[4] ; cont[2] ; clk_i ; +; N/A ; None ; 6.056 ns ; distancia_i[4] ; cont[7] ; clk_i ; +; N/A ; None ; 6.056 ns ; distancia_i[4] ; cont[6] ; clk_i ; +; N/A ; None ; 6.056 ns ; distancia_i[4] ; cont[1] ; clk_i ; +; N/A ; None ; 6.056 ns ; distancia_i[4] ; cont[0] ; clk_i ; +; N/A ; None ; 6.056 ns ; distancia_i[4] ; cont[4] ; clk_i ; +; N/A ; None ; 6.056 ns ; distancia_i[4] ; cont[5] ; clk_i ; +; N/A ; None ; 6.026 ns ; extrapolar_i ; fxx1_o[5]~reg0 ; clk_i ; +; N/A ; None ; 5.991 ns ; distancia_i[5] ; resul_o[7]~reg0 ; clk_i ; +; N/A ; None ; 5.991 ns ; distancia_i[5] ; resul_o[9]~reg0 ; clk_i ; +; N/A ; None ; 5.991 ns ; distancia_i[5] ; resul_o[10]~reg0 ; clk_i ; +; N/A ; None ; 5.991 ns ; distancia_i[5] ; resul_o[11]~reg0 ; clk_i ; +; N/A ; None ; 5.991 ns ; distancia_i[5] ; resul_o[12]~reg0 ; clk_i ; +; N/A ; None ; 5.978 ns ; extrapolar_i ; fx[0][8] ; clk_i ; +; N/A ; None ; 5.942 ns ; distancia_i[6] ; resul_o[0]~reg0 ; clk_i ; +; N/A ; None ; 5.942 ns ; distancia_i[6] ; resul_o[1]~reg0 ; clk_i ; +; N/A ; None ; 5.942 ns ; distancia_i[6] ; resul_o[2]~reg0 ; clk_i ; +; N/A ; None ; 5.942 ns ; distancia_i[6] ; resul_o[3]~reg0 ; clk_i ; +; N/A ; None ; 5.942 ns ; distancia_i[6] ; resul_o[4]~reg0 ; clk_i ; +; N/A ; None ; 5.942 ns ; distancia_i[6] ; resul_o[5]~reg0 ; clk_i ; +; N/A ; None ; 5.942 ns ; distancia_i[6] ; resul_o[6]~reg0 ; clk_i ; +; N/A ; None ; 5.942 ns ; distancia_i[6] ; resul_o[8]~reg0 ; clk_i ; +; N/A ; None ; 5.942 ns ; distancia_i[6] ; resul_o[13]~reg0 ; clk_i ; +; N/A ; None ; 5.942 ns ; distancia_i[6] ; resul_o[14]~reg0 ; clk_i ; +; N/A ; None ; 5.942 ns ; distancia_i[6] ; resul_o[15]~reg0 ; clk_i ; +; N/A ; None ; 5.907 ns ; extrapolar_i ; nabla2fx[0][1] ; clk_i ; +; N/A ; None ; 5.897 ns ; distancia_i[5] ; cont[3] ; clk_i ; +; N/A ; None ; 5.897 ns ; distancia_i[5] ; cont[2] ; clk_i ; +; N/A ; None ; 5.897 ns ; distancia_i[5] ; cont[7] ; clk_i ; +; N/A ; None ; 5.897 ns ; distancia_i[5] ; cont[6] ; clk_i ; +; N/A ; None ; 5.897 ns ; distancia_i[5] ; cont[1] ; clk_i ; +; N/A ; None ; 5.897 ns ; distancia_i[5] ; cont[0] ; clk_i ; +; N/A ; None ; 5.897 ns ; distancia_i[5] ; cont[4] ; clk_i ; +; N/A ; None ; 5.897 ns ; distancia_i[5] ; cont[5] ; clk_i ; +; N/A ; None ; 5.720 ns ; extrapolar_i ; fxx2_o[5]~reg0 ; clk_i ; +; N/A ; None ; 5.697 ns ; rst_i ; resul_o[0]~reg0 ; clk_i ; +; N/A ; None ; 5.697 ns ; rst_i ; resul_o[1]~reg0 ; clk_i ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+------------+----------------+------------------+----------+ + + ++---------------------------------------------------------------------------------+ +; tco ; ++-------+--------------+------------+------------------+-------------+------------+ +; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ; ++-------+--------------+------------+------------------+-------------+------------+ +; N/A ; None ; 8.310 ns ; fxx3_o[14]~reg0 ; fxx3_o[14] ; clk_i ; +; N/A ; None ; 8.308 ns ; resul_o[11]~reg0 ; resul_o[11] ; clk_i ; +; N/A ; None ; 8.281 ns ; fxx3_o[15]~reg0 ; fxx3_o[15] ; clk_i ; +; N/A ; None ; 8.216 ns ; fxx2_o[14]~reg0 ; fxx2_o[14] ; clk_i ; +; N/A ; None ; 8.118 ns ; fxx3_o[3]~reg0 ; fxx3_o[3] ; clk_i ; +; N/A ; None ; 7.959 ns ; fxx3_o[0]~reg0 ; fxx3_o[0] ; clk_i ; +; N/A ; None ; 7.910 ns ; fxx_o[12]~reg0 ; fxx_o[12] ; clk_i ; +; N/A ; None ; 7.902 ns ; fxx1_o[1]~reg0 ; fxx1_o[1] ; clk_i ; +; N/A ; None ; 7.891 ns ; resul_o[7]~reg0 ; resul_o[7] ; clk_i ; +; N/A ; None ; 7.865 ns ; fxx2_o[7]~reg0 ; fxx2_o[7] ; clk_i ; +; N/A ; None ; 7.859 ns ; fxx3_o[7]~reg0 ; fxx3_o[7] ; clk_i ; +; N/A ; None ; 7.853 ns ; fxx1_o[8]~reg0 ; fxx1_o[8] ; clk_i ; +; N/A ; None ; 7.848 ns ; fxx3_o[5]~reg0 ; fxx3_o[5] ; clk_i ; +; N/A ; None ; 7.836 ns ; fxx_o[0]~reg0 ; fxx_o[0] ; clk_i ; +; N/A ; None ; 7.762 ns ; fxx1_o[15]~reg0 ; fxx1_o[15] ; clk_i ; +; N/A ; None ; 7.757 ns ; fxx1_o[12]~reg0 ; fxx1_o[12] ; clk_i ; +; N/A ; None ; 7.677 ns ; fxx_o[4]~reg0 ; fxx_o[4] ; clk_i ; +; N/A ; None ; 7.677 ns ; fxx_o[3]~reg0 ; fxx_o[3] ; clk_i ; +; N/A ; None ; 7.650 ns ; fxx_o[10]~reg0 ; fxx_o[10] ; clk_i ; +; N/A ; None ; 7.650 ns ; fxx_o[6]~reg0 ; fxx_o[6] ; clk_i ; +; N/A ; None ; 7.646 ns ; fxx1_o[2]~reg0 ; fxx1_o[2] ; clk_i ; +; N/A ; None ; 7.645 ns ; fxx2_o[15]~reg0 ; fxx2_o[15] ; clk_i ; +; N/A ; None ; 7.612 ns ; fxx2_o[1]~reg0 ; fxx2_o[1] ; clk_i ; +; N/A ; None ; 7.604 ns ; resul_o[14]~reg0 ; resul_o[14] ; clk_i ; +; N/A ; None ; 7.589 ns ; fxx_o[1]~reg0 ; fxx_o[1] ; clk_i ; +; N/A ; None ; 7.588 ns ; fxx3_o[2]~reg0 ; fxx3_o[2] ; clk_i ; +; N/A ; None ; 7.588 ns ; fxx1_o[0]~reg0 ; fxx1_o[0] ; clk_i ; +; N/A ; None ; 7.584 ns ; fxx1_o[11]~reg0 ; fxx1_o[11] ; clk_i ; +; N/A ; None ; 7.581 ns ; fxx1_o[4]~reg0 ; fxx1_o[4] ; clk_i ; +; N/A ; None ; 7.567 ns ; fxx2_o[6]~reg0 ; fxx2_o[6] ; clk_i ; +; N/A ; None ; 7.551 ns ; fxx_o[2]~reg0 ; fxx_o[2] ; clk_i ; +; N/A ; None ; 7.479 ns ; fxx4_o[9]~reg0 ; fxx4_o[9] ; clk_i ; +; N/A ; None ; 7.473 ns ; fxx4_o[13]~reg0 ; fxx4_o[13] ; clk_i ; +; N/A ; None ; 7.469 ns ; fxx3_o[12]~reg0 ; fxx3_o[12] ; clk_i ; +; N/A ; None ; 7.467 ns ; fxx2_o[8]~reg0 ; fxx2_o[8] ; clk_i ; +; N/A ; None ; 7.435 ns ; fxx4_o[15]~reg0 ; fxx4_o[15] ; clk_i ; +; N/A ; None ; 7.370 ns ; resul_o[8]~reg0 ; resul_o[8] ; clk_i ; +; N/A ; None ; 7.340 ns ; fxx3_o[9]~reg0 ; fxx3_o[9] ; clk_i ; +; N/A ; None ; 7.337 ns ; fxx2_o[2]~reg0 ; fxx2_o[2] ; clk_i ; +; N/A ; None ; 7.331 ns ; fxx_o[11]~reg0 ; fxx_o[11] ; clk_i ; +; N/A ; None ; 7.328 ns ; fxx2_o[9]~reg0 ; fxx2_o[9] ; clk_i ; +; N/A ; None ; 7.279 ns ; fxx1_o[6]~reg0 ; fxx1_o[6] ; clk_i ; +; N/A ; None ; 7.204 ns ; fxx3_o[11]~reg0 ; fxx3_o[11] ; clk_i ; +; N/A ; None ; 7.201 ns ; resul_o[6]~reg0 ; resul_o[6] ; clk_i ; +; N/A ; None ; 7.181 ns ; fxx4_o[14]~reg0 ; fxx4_o[14] ; clk_i ; +; N/A ; None ; 7.179 ns ; fxx4_o[12]~reg0 ; fxx4_o[12] ; clk_i ; +; N/A ; None ; 7.154 ns ; fxx4_o[11]~reg0 ; fxx4_o[11] ; clk_i ; +; N/A ; None ; 7.154 ns ; fxx3_o[8]~reg0 ; fxx3_o[8] ; clk_i ; +; N/A ; None ; 7.137 ns ; fxx4_o[1]~reg0 ; fxx4_o[1] ; clk_i ; +; N/A ; None ; 7.135 ns ; fxx_o[5]~reg0 ; fxx_o[5] ; clk_i ; +; N/A ; None ; 7.114 ns ; fxx2_o[4]~reg0 ; fxx2_o[4] ; clk_i ; +; N/A ; None ; 7.066 ns ; fxx2_o[3]~reg0 ; fxx2_o[3] ; clk_i ; +; N/A ; None ; 7.046 ns ; resul_o[15]~reg0 ; resul_o[15] ; clk_i ; +; N/A ; None ; 7.035 ns ; fxx_o[8]~reg0 ; fxx_o[8] ; clk_i ; +; N/A ; None ; 7.010 ns ; resul_o[5]~reg0 ; resul_o[5] ; clk_i ; +; N/A ; None ; 7.004 ns ; fxx3_o[1]~reg0 ; fxx3_o[1] ; clk_i ; +; N/A ; None ; 7.003 ns ; fxx_o[14]~reg0 ; fxx_o[14] ; clk_i ; +; N/A ; None ; 6.994 ns ; fxx2_o[0]~reg0 ; fxx2_o[0] ; clk_i ; +; N/A ; None ; 6.924 ns ; fxx1_o[13]~reg0 ; fxx1_o[13] ; clk_i ; +; N/A ; None ; 6.921 ns ; fxx1_o[5]~reg0 ; fxx1_o[5] ; clk_i ; +; N/A ; None ; 6.904 ns ; fxx4_o[4]~reg0 ; fxx4_o[4] ; clk_i ; +; N/A ; None ; 6.879 ns ; resul_o[4]~reg0 ; resul_o[4] ; clk_i ; +; N/A ; None ; 6.877 ns ; fxx4_o[7]~reg0 ; fxx4_o[7] ; clk_i ; +; N/A ; None ; 6.857 ns ; fxx1_o[3]~reg0 ; fxx1_o[3] ; clk_i ; +; N/A ; None ; 6.835 ns ; fxx_o[7]~reg0 ; fxx_o[7] ; clk_i ; +; N/A ; None ; 6.753 ns ; resul_o[10]~reg0 ; resul_o[10] ; clk_i ; +; N/A ; None ; 6.750 ns ; fxx2_o[11]~reg0 ; fxx2_o[11] ; clk_i ; +; N/A ; None ; 6.736 ns ; fxx4_o[0]~reg0 ; fxx4_o[0] ; clk_i ; +; N/A ; None ; 6.693 ns ; fxx2_o[5]~reg0 ; fxx2_o[5] ; clk_i ; +; N/A ; None ; 6.686 ns ; fxx_o[9]~reg0 ; fxx_o[9] ; clk_i ; +; N/A ; None ; 6.661 ns ; fxx_o[13]~reg0 ; fxx_o[13] ; clk_i ; +; N/A ; None ; 6.659 ns ; fxx2_o[10]~reg0 ; fxx2_o[10] ; clk_i ; +; N/A ; None ; 6.647 ns ; fxx4_o[10]~reg0 ; fxx4_o[10] ; clk_i ; +; N/A ; None ; 6.647 ns ; fxx1_o[14]~reg0 ; fxx1_o[14] ; clk_i ; +; N/A ; None ; 6.617 ns ; fxx4_o[8]~reg0 ; fxx4_o[8] ; clk_i ; +; N/A ; None ; 6.561 ns ; fxx3_o[4]~reg0 ; fxx3_o[4] ; clk_i ; +; N/A ; None ; 6.548 ns ; resul_o[13]~reg0 ; resul_o[13] ; clk_i ; +; N/A ; None ; 6.541 ns ; resul_o[9]~reg0 ; resul_o[9] ; clk_i ; +; N/A ; None ; 6.532 ns ; fxx1_o[9]~reg0 ; fxx1_o[9] ; clk_i ; +; N/A ; None ; 6.504 ns ; fxx4_o[2]~reg0 ; fxx4_o[2] ; clk_i ; +; N/A ; None ; 6.489 ns ; fxx4_o[6]~reg0 ; fxx4_o[6] ; clk_i ; +; N/A ; None ; 6.479 ns ; resul_o[12]~reg0 ; resul_o[12] ; clk_i ; +; N/A ; None ; 6.479 ns ; fxx4_o[3]~reg0 ; fxx4_o[3] ; clk_i ; +; N/A ; None ; 6.476 ns ; fxx3_o[6]~reg0 ; fxx3_o[6] ; clk_i ; +; N/A ; None ; 6.456 ns ; resul_o[3]~reg0 ; resul_o[3] ; clk_i ; +; N/A ; None ; 6.435 ns ; resul_o[2]~reg0 ; resul_o[2] ; clk_i ; +; N/A ; None ; 6.430 ns ; fxx1_o[7]~reg0 ; fxx1_o[7] ; clk_i ; +; N/A ; None ; 6.415 ns ; fxx1_o[10]~reg0 ; fxx1_o[10] ; clk_i ; +; N/A ; None ; 6.407 ns ; fxx_o[15]~reg0 ; fxx_o[15] ; clk_i ; +; N/A ; None ; 6.346 ns ; resul_o[1]~reg0 ; resul_o[1] ; clk_i ; +; N/A ; None ; 6.190 ns ; fxx4_o[5]~reg0 ; fxx4_o[5] ; clk_i ; +; N/A ; None ; 6.183 ns ; fxx2_o[13]~reg0 ; fxx2_o[13] ; clk_i ; +; N/A ; None ; 6.175 ns ; fxx2_o[12]~reg0 ; fxx2_o[12] ; clk_i ; +; N/A ; None ; 6.173 ns ; fxx3_o[10]~reg0 ; fxx3_o[10] ; clk_i ; +; N/A ; None ; 6.161 ns ; resul_o[0]~reg0 ; resul_o[0] ; clk_i ; +; N/A ; None ; 6.114 ns ; fxx3_o[13]~reg0 ; fxx3_o[13] ; clk_i ; ++-------+--------------+------------+------------------+-------------+------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; th ; ++-----------------------------------------+-----------------------------------------------------+-----------+----------------+------------------+----------+ +; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ; ++-----------------------------------------+-----------------------------------------------------+-----------+----------------+------------------+----------+ +; N/A ; None ; -1.094 ns ; rst_i ; resultado[15] ; clk_i ; +; N/A ; None ; -1.094 ns ; rst_i ; fxx1_o[8]~reg0 ; clk_i ; +; N/A ; None ; -1.094 ns ; rst_i ; fxx1_o[10]~reg0 ; clk_i ; +; N/A ; None ; -1.094 ns ; rst_i ; fxx1_o[12]~reg0 ; clk_i ; +; N/A ; None ; -1.094 ns ; rst_i ; fxx1_o[13]~reg0 ; clk_i ; +; N/A ; None ; -1.094 ns ; rst_i ; fxx1_o[15]~reg0 ; clk_i ; +; N/A ; None ; -3.585 ns ; extrapolar_i ; fxx_o[2]~reg0 ; clk_i ; +; N/A ; None ; -3.585 ns ; extrapolar_i ; fxx_o[4]~reg0 ; clk_i ; +; N/A ; None ; -3.585 ns ; extrapolar_i ; fxx_o[5]~reg0 ; clk_i ; +; N/A ; None ; -3.926 ns ; extrapolar_i ; nabla1fx[0][5] ; clk_i ; +; N/A ; None ; -3.926 ns ; extrapolar_i ; nabla1fx[0][6] ; clk_i ; +; N/A ; None ; -3.926 ns ; extrapolar_i ; fxx1_o[4]~reg0 ; clk_i ; +; N/A ; None ; -3.926 ns ; extrapolar_i ; fxx1_o[7]~reg0 ; clk_i ; +; N/A ; None ; -3.929 ns ; extrapolar_i ; nabla1fx[0][2] ; clk_i ; +; N/A ; None ; -3.929 ns ; extrapolar_i ; fxx1_o[3]~reg0 ; clk_i ; +; N/A ; None ; -3.930 ns ; extrapolar_i ; nabla1fx[0][1] ; clk_i ; +; N/A ; None ; -3.930 ns ; extrapolar_i ; fxx1_o[0]~reg0 ; clk_i ; +; N/A ; None ; -3.986 ns ; extrapolar_i ; fxx_o[3]~reg0 ; clk_i ; +; N/A ; None ; -4.012 ns ; extrapolar_i ; fxx_o[7]~reg0 ; clk_i ; +; N/A ; None ; -4.072 ns ; rst_i ; fxx2_o[0]~reg0 ; clk_i ; +; N/A ; None ; -4.072 ns ; rst_i ; fxx2_o[1]~reg0 ; clk_i ; +; N/A ; None ; -4.072 ns ; rst_i ; fxx2_o[2]~reg0 ; clk_i ; +; N/A ; None ; -4.072 ns ; rst_i ; fxx2_o[4]~reg0 ; clk_i ; +; N/A ; None ; -4.072 ns ; rst_i ; fxx2_o[5]~reg0 ; clk_i ; +; N/A ; None ; -4.072 ns ; rst_i ; fxx2_o[6]~reg0 ; clk_i ; +; N/A ; None ; -4.078 ns ; rst_i ; fxx1_o[0]~reg0 ; clk_i ; +; N/A ; None ; -4.078 ns ; rst_i ; fxx1_o[3]~reg0 ; clk_i ; +; N/A ; None ; -4.078 ns ; rst_i ; fxx1_o[4]~reg0 ; clk_i ; +; N/A ; None ; -4.078 ns ; rst_i ; fxx1_o[7]~reg0 ; clk_i ; +; N/A ; None ; -4.091 ns ; rst_i ; fxx1_o[6]~reg0 ; clk_i ; +; N/A ; None ; -4.091 ns ; rst_i ; fxx1_o[9]~reg0 ; clk_i ; +; N/A ; None ; -4.091 ns ; rst_i ; fxx1_o[11]~reg0 ; clk_i ; +; N/A ; None ; -4.091 ns ; rst_i ; fxx1_o[14]~reg0 ; clk_i ; +; N/A ; None ; -4.126 ns ; extrapolar_i ; fxx1_o[8]~reg0 ; clk_i ; +; N/A ; None ; -4.136 ns ; distancia_i[7] ; resul_o[7]~reg0 ; clk_i ; +; N/A ; None ; -4.136 ns ; distancia_i[7] ; resul_o[9]~reg0 ; clk_i ; +; N/A ; None ; -4.136 ns ; distancia_i[7] ; resul_o[10]~reg0 ; clk_i ; +; N/A ; None ; -4.136 ns ; distancia_i[7] ; resul_o[11]~reg0 ; clk_i ; +; N/A ; None ; -4.136 ns ; distancia_i[7] ; resul_o[12]~reg0 ; clk_i ; +; N/A ; None ; -4.161 ns ; rst_i ; fxx2_o[7]~reg0 ; clk_i ; +; N/A ; None ; -4.161 ns ; rst_i ; fxx2_o[9]~reg0 ; clk_i ; +; N/A ; None ; -4.161 ns ; rst_i ; fxx2_o[11]~reg0 ; clk_i ; +; N/A ; None ; -4.167 ns ; extrapolar_i ; nabla1fx[0][9] ; clk_i ; +; N/A ; None ; -4.197 ns ; extrapolar_i ; fxx_o[12]~reg0 ; clk_i ; +; N/A ; None ; -4.200 ns ; extrapolar_i ; fxx_o[1]~reg0 ; clk_i ; +; N/A ; None ; -4.201 ns ; extrapolar_i ; fxx_o[0]~reg0 ; clk_i ; +; N/A ; None ; -4.205 ns ; rst_i ; fxx3_o[8]~reg0 ; clk_i ; +; N/A ; None ; -4.205 ns ; rst_i ; fxx3_o[9]~reg0 ; clk_i ; +; N/A ; None ; -4.205 ns ; rst_i ; fxx3_o[11]~reg0 ; clk_i ; +; N/A ; None ; -4.205 ns ; rst_i ; fxx3_o[13]~reg0 ; clk_i ; +; N/A ; None ; -4.205 ns ; rst_i ; fxx3_o[14]~reg0 ; clk_i ; +; N/A ; None ; -4.205 ns ; rst_i ; fxx3_o[15]~reg0 ; clk_i ; +; N/A ; None ; -4.208 ns ; extrapolar_i ; fxx1_o[10]~reg0 ; clk_i ; +; N/A ; None ; -4.249 ns ; extrapolar_i ; nabla1fx[0][11] ; clk_i ; +; N/A ; None ; -4.253 ns ; extrapolar_i ; fxx_o[10]~reg0 ; clk_i ; +; N/A ; None ; -4.253 ns ; extrapolar_i ; fxx_o[11]~reg0 ; clk_i ; +; N/A ; None ; -4.253 ns ; extrapolar_i ; fxx_o[14]~reg0 ; clk_i ; +; N/A ; None ; -4.253 ns ; extrapolar_i ; fxx_o[15]~reg0 ; clk_i ; +; N/A ; None ; -4.254 ns ; extrapolar_i ; fxx_o[9]~reg0 ; clk_i ; +; N/A ; None ; -4.254 ns ; extrapolar_i ; fxx_o[13]~reg0 ; clk_i ; +; N/A ; None ; -4.290 ns ; extrapolar_i ; fxx1_o[12]~reg0 ; clk_i ; +; N/A ; None ; -4.331 ns ; extrapolar_i ; fxx1_o[13]~reg0 ; clk_i ; +; N/A ; None ; -4.353 ns ; rst_i ; resultado[14] ; clk_i ; +; N/A ; None ; -4.353 ns ; rst_i ; fxx_o[9]~reg0 ; clk_i ; +; N/A ; None ; -4.353 ns ; rst_i ; fxx_o[10]~reg0 ; clk_i ; +; N/A ; None ; -4.353 ns ; rst_i ; fxx_o[11]~reg0 ; clk_i ; +; N/A ; None ; -4.353 ns ; rst_i ; fxx_o[13]~reg0 ; clk_i ; +; N/A ; None ; -4.353 ns ; rst_i ; fxx_o[14]~reg0 ; clk_i ; +; N/A ; None ; -4.353 ns ; rst_i ; fxx_o[15]~reg0 ; clk_i ; +; N/A ; None ; -4.357 ns ; distancia_i[1] ; resul_o[7]~reg0 ; clk_i ; +; N/A ; None ; -4.357 ns ; distancia_i[1] ; resul_o[9]~reg0 ; clk_i ; +; N/A ; None ; -4.357 ns ; distancia_i[1] ; resul_o[10]~reg0 ; clk_i ; +; N/A ; None ; -4.357 ns ; distancia_i[1] ; resul_o[11]~reg0 ; clk_i ; +; N/A ; None ; -4.357 ns ; distancia_i[1] ; resul_o[12]~reg0 ; clk_i ; +; N/A ; None ; -4.372 ns ; extrapolar_i ; nabla1fx[0][14] ; clk_i ; +; N/A ; None ; -4.380 ns ; rst_i ; fxx3_o[0]~reg0 ; clk_i ; +; N/A ; None ; -4.380 ns ; rst_i ; fxx3_o[4]~reg0 ; clk_i ; +; N/A ; None ; -4.380 ns ; rst_i ; fxx3_o[5]~reg0 ; clk_i ; +; N/A ; None ; -4.380 ns ; rst_i ; fxx3_o[6]~reg0 ; clk_i ; +; N/A ; None ; -4.380 ns ; rst_i ; fxx3_o[7]~reg0 ; clk_i ; +; N/A ; None ; -4.387 ns ; rst_i ; resultado[2] ; clk_i ; +; N/A ; None ; -4.387 ns ; rst_i ; resultado[3] ; clk_i ; +; N/A ; None ; -4.387 ns ; rst_i ; resultado[4] ; clk_i ; +; N/A ; None ; -4.387 ns ; rst_i ; resultado[5] ; clk_i ; +; N/A ; None ; -4.387 ns ; rst_i ; fxx_o[2]~reg0 ; clk_i ; +; N/A ; None ; -4.387 ns ; rst_i ; fxx_o[3]~reg0 ; clk_i ; +; N/A ; None ; -4.387 ns ; rst_i ; fxx_o[4]~reg0 ; clk_i ; +; N/A ; None ; -4.387 ns ; rst_i ; fxx_o[5]~reg0 ; clk_i ; +; N/A ; None ; -4.387 ns ; rst_i ; fxx4_o[0]~reg0 ; clk_i ; +; N/A ; None ; -4.387 ns ; rst_i ; fxx4_o[1]~reg0 ; clk_i ; +; N/A ; None ; -4.387 ns ; rst_i ; fxx4_o[2]~reg0 ; clk_i ; +; N/A ; None ; -4.387 ns ; rst_i ; fxx4_o[3]~reg0 ; clk_i ; +; N/A ; None ; -4.387 ns ; rst_i ; fxx4_o[4]~reg0 ; clk_i ; +; N/A ; None ; -4.387 ns ; rst_i ; fxx4_o[5]~reg0 ; clk_i ; +; N/A ; None ; -4.387 ns ; rst_i ; fxx4_o[6]~reg0 ; clk_i ; +; N/A ; None ; -4.392 ns ; extrapolar_i ; cont[0] ; clk_i ; +; N/A ; None ; -4.399 ns ; rst_i ; resultado[0] ; clk_i ; +; N/A ; None ; -4.399 ns ; rst_i ; resultado[1] ; clk_i ; +; N/A ; None ; -4.399 ns ; rst_i ; fxx_o[0]~reg0 ; clk_i ; +; N/A ; None ; -4.399 ns ; rst_i ; fxx_o[1]~reg0 ; clk_i ; +; N/A ; None ; -4.399 ns ; rst_i ; fxx2_o[3]~reg0 ; clk_i ; +; N/A ; None ; -4.399 ns ; rst_i ; fxx3_o[1]~reg0 ; clk_i ; +; N/A ; None ; -4.399 ns ; rst_i ; fxx3_o[2]~reg0 ; clk_i ; +; N/A ; None ; -4.399 ns ; rst_i ; fxx3_o[3]~reg0 ; clk_i ; +; N/A ; None ; -4.406 ns ; extrapolar_i ; fx[0][2] ; clk_i ; +; N/A ; None ; -4.413 ns ; extrapolar_i ; fxx1_o[15]~reg0 ; clk_i ; +; N/A ; None ; -4.420 ns ; rst_i ; resultado[6] ; clk_i ; +; N/A ; None ; -4.420 ns ; rst_i ; resultado[8] ; clk_i ; +; N/A ; None ; -4.420 ns ; rst_i ; resultado[13] ; clk_i ; +; N/A ; None ; -4.420 ns ; rst_i ; fxx_o[6]~reg0 ; clk_i ; +; N/A ; None ; -4.420 ns ; rst_i ; fxx_o[8]~reg0 ; clk_i ; +; N/A ; None ; -4.420 ns ; rst_i ; fxx4_o[7]~reg0 ; clk_i ; +; N/A ; None ; -4.420 ns ; rst_i ; fxx4_o[8]~reg0 ; clk_i ; +; N/A ; None ; -4.420 ns ; rst_i ; fxx4_o[9]~reg0 ; clk_i ; +; N/A ; None ; -4.420 ns ; rst_i ; fxx4_o[10]~reg0 ; clk_i ; +; N/A ; None ; -4.420 ns ; rst_i ; fxx4_o[11]~reg0 ; clk_i ; +; N/A ; None ; -4.420 ns ; rst_i ; fxx4_o[12]~reg0 ; clk_i ; +; N/A ; None ; -4.420 ns ; rst_i ; fxx4_o[13]~reg0 ; clk_i ; +; N/A ; None ; -4.420 ns ; rst_i ; fxx4_o[14]~reg0 ; clk_i ; +; N/A ; None ; -4.420 ns ; rst_i ; fxx4_o[15]~reg0 ; clk_i ; +; N/A ; None ; -4.426 ns ; extrapolar_i ; fx[0][5] ; clk_i ; +; N/A ; None ; -4.429 ns ; rst_i ; fxx2_o[8]~reg0 ; clk_i ; +; N/A ; None ; -4.429 ns ; rst_i ; fxx2_o[10]~reg0 ; clk_i ; +; N/A ; None ; -4.429 ns ; rst_i ; fxx2_o[12]~reg0 ; clk_i ; +; N/A ; None ; -4.429 ns ; rst_i ; fxx2_o[13]~reg0 ; clk_i ; +; N/A ; None ; -4.429 ns ; rst_i ; fxx2_o[14]~reg0 ; clk_i ; +; N/A ; None ; -4.429 ns ; rst_i ; fxx2_o[15]~reg0 ; clk_i ; +; N/A ; None ; -4.429 ns ; rst_i ; fxx3_o[10]~reg0 ; clk_i ; +; N/A ; None ; -4.429 ns ; rst_i ; fxx3_o[12]~reg0 ; clk_i ; +; N/A ; None ; -4.432 ns ; extrapolar_i ; fx[0][7] ; clk_i ; +; N/A ; None ; -4.441 ns ; distancia_i[7] ; resul_o[0]~reg0 ; clk_i ; +; N/A ; None ; -4.441 ns ; distancia_i[7] ; resul_o[1]~reg0 ; clk_i ; +; N/A ; None ; -4.441 ns ; distancia_i[7] ; resul_o[2]~reg0 ; clk_i ; +; N/A ; None ; -4.441 ns ; distancia_i[7] ; resul_o[3]~reg0 ; clk_i ; +; N/A ; None ; -4.441 ns ; distancia_i[7] ; resul_o[4]~reg0 ; clk_i ; +; N/A ; None ; -4.441 ns ; distancia_i[7] ; resul_o[5]~reg0 ; clk_i ; +; N/A ; None ; -4.441 ns ; distancia_i[7] ; resul_o[6]~reg0 ; clk_i ; +; N/A ; None ; -4.441 ns ; distancia_i[7] ; resul_o[8]~reg0 ; clk_i ; +; N/A ; None ; -4.441 ns ; distancia_i[7] ; resul_o[13]~reg0 ; clk_i ; +; N/A ; None ; -4.441 ns ; distancia_i[7] ; resul_o[14]~reg0 ; clk_i ; +; N/A ; None ; -4.441 ns ; distancia_i[7] ; resul_o[15]~reg0 ; clk_i ; +; N/A ; None ; -4.443 ns ; extrapolar_i ; fx[0][4] ; clk_i ; +; N/A ; None ; -4.444 ns ; extrapolar_i ; nabla1fx[0][0] ; clk_i ; +; N/A ; None ; -4.448 ns ; extrapolar_i ; cont[1] ; clk_i ; +; N/A ; None ; -4.468 ns ; distancia_i[6] ; cont[3] ; clk_i ; +; N/A ; None ; -4.468 ns ; distancia_i[6] ; cont[2] ; clk_i ; +; N/A ; None ; -4.468 ns ; distancia_i[6] ; cont[7] ; clk_i ; +; N/A ; None ; -4.468 ns ; distancia_i[6] ; cont[6] ; clk_i ; +; N/A ; None ; -4.468 ns ; distancia_i[6] ; cont[1] ; clk_i ; +; N/A ; None ; -4.468 ns ; distancia_i[6] ; cont[0] ; clk_i ; +; N/A ; None ; -4.468 ns ; distancia_i[6] ; cont[4] ; clk_i ; +; N/A ; None ; -4.468 ns ; distancia_i[6] ; cont[5] ; clk_i ; +; N/A ; None ; -4.487 ns ; distancia_i[1] ; cont[3] ; clk_i ; +; N/A ; None ; -4.487 ns ; distancia_i[1] ; cont[2] ; clk_i ; +; N/A ; None ; -4.487 ns ; distancia_i[1] ; cont[7] ; clk_i ; +; N/A ; None ; -4.487 ns ; distancia_i[1] ; cont[6] ; clk_i ; +; N/A ; None ; -4.487 ns ; distancia_i[1] ; cont[1] ; clk_i ; +; N/A ; None ; -4.487 ns ; distancia_i[1] ; cont[0] ; clk_i ; +; N/A ; None ; -4.487 ns ; distancia_i[1] ; cont[4] ; clk_i ; +; N/A ; None ; -4.487 ns ; distancia_i[1] ; cont[5] ; clk_i ; +; N/A ; None ; -4.489 ns ; extrapolar_i ; cont[2] ; clk_i ; +; N/A ; None ; -4.530 ns ; extrapolar_i ; cont[3] ; clk_i ; +; N/A ; None ; -4.555 ns ; distancia_i[3] ; cont[3] ; clk_i ; +; N/A ; None ; -4.555 ns ; distancia_i[3] ; cont[2] ; clk_i ; +; N/A ; None ; -4.555 ns ; distancia_i[3] ; cont[7] ; clk_i ; +; N/A ; None ; -4.555 ns ; distancia_i[3] ; cont[6] ; clk_i ; +; N/A ; None ; -4.555 ns ; distancia_i[3] ; cont[1] ; clk_i ; +; N/A ; None ; -4.555 ns ; distancia_i[3] ; cont[0] ; clk_i ; +; N/A ; None ; -4.555 ns ; distancia_i[3] ; cont[4] ; clk_i ; +; N/A ; None ; -4.555 ns ; distancia_i[3] ; cont[5] ; clk_i ; +; N/A ; None ; -4.561 ns ; extrapolar_i ; nabla1fx[0][4] ; clk_i ; +; N/A ; None ; -4.571 ns ; extrapolar_i ; cont[4] ; clk_i ; +; N/A ; None ; -4.572 ns ; extrapolar_i ; nabla1fx[0][3] ; clk_i ; +; N/A ; None ; -4.607 ns ; distancia_i[7] ; cont[3] ; clk_i ; +; N/A ; None ; -4.607 ns ; distancia_i[7] ; cont[2] ; clk_i ; +; N/A ; None ; -4.607 ns ; distancia_i[7] ; cont[7] ; clk_i ; +; N/A ; None ; -4.607 ns ; distancia_i[7] ; cont[6] ; clk_i ; +; N/A ; None ; -4.607 ns ; distancia_i[7] ; cont[1] ; clk_i ; +; N/A ; None ; -4.607 ns ; distancia_i[7] ; cont[0] ; clk_i ; +; N/A ; None ; -4.607 ns ; distancia_i[7] ; cont[4] ; clk_i ; +; N/A ; None ; -4.607 ns ; distancia_i[7] ; cont[5] ; clk_i ; +; N/A ; None ; -4.612 ns ; extrapolar_i ; cont[5] ; clk_i ; +; N/A ; None ; -4.631 ns ; rst_i ; resultado[7] ; clk_i ; +; N/A ; None ; -4.631 ns ; rst_i ; resultado[9] ; clk_i ; +; N/A ; None ; -4.631 ns ; rst_i ; resultado[10] ; clk_i ; +; N/A ; None ; -4.631 ns ; rst_i ; resultado[11] ; clk_i ; +; N/A ; None ; -4.631 ns ; rst_i ; resultado[12] ; clk_i ; +; N/A ; None ; -4.640 ns ; distancia_i[2] ; resul_o[7]~reg0 ; clk_i ; +; N/A ; None ; -4.640 ns ; distancia_i[2] ; resul_o[9]~reg0 ; clk_i ; +; N/A ; None ; -4.640 ns ; distancia_i[2] ; resul_o[10]~reg0 ; clk_i ; +; N/A ; None ; -4.640 ns ; distancia_i[2] ; resul_o[11]~reg0 ; clk_i ; +; N/A ; None ; -4.640 ns ; distancia_i[2] ; resul_o[12]~reg0 ; clk_i ; +; N/A ; None ; -4.643 ns ; extrapolar_i ; nabla1fx[0][8] ; clk_i ; +; N/A ; None ; -4.649 ns ; distancia_i[3] ; resul_o[7]~reg0 ; clk_i ; +; N/A ; None ; -4.649 ns ; distancia_i[3] ; resul_o[9]~reg0 ; clk_i ; +; N/A ; None ; -4.649 ns ; distancia_i[3] ; resul_o[10]~reg0 ; clk_i ; +; N/A ; None ; -4.649 ns ; distancia_i[3] ; resul_o[11]~reg0 ; clk_i ; +; N/A ; None ; -4.649 ns ; distancia_i[3] ; resul_o[12]~reg0 ; clk_i ; +; N/A ; None ; -4.653 ns ; extrapolar_i ; cont[6] ; clk_i ; +; N/A ; None ; -4.656 ns ; rst_i ; fxx_o[7]~reg0 ; clk_i ; +; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ++-----------------------------------------+-----------------------------------------------------+-----------+----------------+------------------+----------+ + + ++--------------------------+ +; Timing Analyzer Messages ; ++--------------------------+ +Info: ******************************************************************* +Info: Running Quartus II Classic Timing Analyzer + Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + Info: Processing started: Tue Aug 14 00:28:12 2012 +Info: Command: quartus_tan --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolator --speed=4 +Info: Started post-fitting delay annotation +Warning: Found 96 output pins without output pin load capacitance assignment + Info: Pin "fxx_o[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis +Info: Delay annotation completed successfully +Warning: Found pins functioning as undefined clocks and/or memory enables + Info: Assuming node "clk_i" is an undefined clock +Info: Clock "clk_i" has Internal fmax of 46.88 MHz between source memory "altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0" and destination register "resultado[15]" (period= 21.332 ns) + Info: + Longest memory to register delay is 10.577 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M512_X24_Y8; Fanout = 16; MEM Node = 'altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0' + Info: 2: + IC(0.000 ns) + CELL(2.061 ns) = 2.061 ns; Loc. = M512_X24_Y8; Fanout = 6; MEM Node = 'altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7' + Info: 3: + IC(0.866 ns) + CELL(0.060 ns) = 2.987 ns; Loc. = LCCOMB_X27_Y5_N22; Fanout = 2; COMB Node = 'fx~23' + Info: 4: + IC(0.874 ns) + CELL(0.426 ns) = 4.287 ns; Loc. = LCCOMB_X23_Y8_N30; Fanout = 6; COMB Node = 'Add2~37' + Info: 5: + IC(0.671 ns) + CELL(0.426 ns) = 5.384 ns; Loc. = LCCOMB_X22_Y7_N0; Fanout = 7; COMB Node = 'Add3~33' + Info: 6: + IC(0.674 ns) + CELL(0.570 ns) = 6.628 ns; Loc. = LCCOMB_X22_Y6_N30; Fanout = 2; COMB Node = 'Add4~38' + Info: 7: + IC(0.000 ns) + CELL(0.041 ns) = 6.669 ns; Loc. = LCCOMB_X22_Y5_N0; Fanout = 2; COMB Node = 'Add4~42' + Info: 8: + IC(0.000 ns) + CELL(0.041 ns) = 6.710 ns; Loc. = LCCOMB_X22_Y5_N2; Fanout = 2; COMB Node = 'Add4~46' + Info: 9: + IC(0.000 ns) + CELL(0.041 ns) = 6.751 ns; Loc. = LCCOMB_X22_Y5_N4; Fanout = 2; COMB Node = 'Add4~50' + Info: 10: + IC(0.000 ns) + CELL(0.144 ns) = 6.895 ns; Loc. = LCCOMB_X22_Y5_N6; Fanout = 7; COMB Node = 'Add4~53' + Info: 11: + IC(0.677 ns) + CELL(0.502 ns) = 8.074 ns; Loc. = LCCOMB_X25_Y5_N6; Fanout = 2; COMB Node = 'Add8~46' + Info: 12: + IC(0.000 ns) + CELL(0.041 ns) = 8.115 ns; Loc. = LCCOMB_X25_Y5_N8; Fanout = 2; COMB Node = 'Add8~50' + Info: 13: + IC(0.000 ns) + CELL(0.041 ns) = 8.156 ns; Loc. = LCCOMB_X25_Y5_N10; Fanout = 2; COMB Node = 'Add8~54' + Info: 14: + IC(0.000 ns) + CELL(0.041 ns) = 8.197 ns; Loc. = LCCOMB_X25_Y5_N12; Fanout = 1; COMB Node = 'Add8~58' + Info: 15: + IC(0.000 ns) + CELL(0.144 ns) = 8.341 ns; Loc. = LCCOMB_X25_Y5_N14; Fanout = 1; COMB Node = 'Add8~61' + Info: 16: + IC(0.553 ns) + CELL(0.426 ns) = 9.320 ns; Loc. = LCCOMB_X26_Y5_N30; Fanout = 2; COMB Node = 'Add9~61' + Info: 17: + IC(0.902 ns) + CELL(0.355 ns) = 10.577 ns; Loc. = LCFF_X23_Y7_N3; Fanout = 4; REG Node = 'resultado[15]' + Info: Total cell delay = 5.360 ns ( 50.68 % ) + Info: Total interconnect delay = 5.217 ns ( 49.32 % ) + Info: - Smallest clock skew is 0.176 ns + Info: + Shortest clock path from clock "clk_i" to destination register is 2.830 ns + Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i' + Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 195; COMB Node = 'clk_i~clkctrl' + Info: 3: + IC(0.752 ns) + CELL(0.710 ns) = 2.830 ns; Loc. = LCFF_X23_Y7_N3; Fanout = 4; REG Node = 'resultado[15]' + Info: Total cell delay = 1.684 ns ( 59.51 % ) + Info: Total interconnect delay = 1.146 ns ( 40.49 % ) + Info: - Longest clock path from clock "clk_i" to source memory is 2.654 ns + Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i' + Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 195; COMB Node = 'clk_i~clkctrl' + Info: 3: + IC(0.760 ns) + CELL(0.526 ns) = 2.654 ns; Loc. = M512_X24_Y8; Fanout = 16; MEM Node = 'altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0~porta_address_reg0' + Info: Total cell delay = 1.500 ns ( 56.52 % ) + Info: Total interconnect delay = 1.154 ns ( 43.48 % ) + Info: + Micro clock to output delay of source is 0.161 ns + Info: + Micro setup delay of destination is 0.104 ns + Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two +Info: tsu for register "resultado[15]" (data pin = "extrapolar_i", clock pin = "clk_i") is 12.402 ns + Info: + Longest pin to register delay is 15.128 ns + Info: 1: + IC(0.000 ns) + CELL(0.920 ns) = 0.920 ns; Loc. = PIN_B9; Fanout = 96; PIN Node = 'extrapolar_i' + Info: 2: + IC(6.261 ns) + CELL(0.435 ns) = 7.616 ns; Loc. = LCCOMB_X23_Y5_N24; Fanout = 2; COMB Node = 'fx~22' + Info: 3: + IC(0.675 ns) + CELL(0.403 ns) = 8.694 ns; Loc. = LCCOMB_X23_Y8_N28; Fanout = 2; COMB Node = 'Add2~34' + Info: 4: + IC(0.000 ns) + CELL(0.144 ns) = 8.838 ns; Loc. = LCCOMB_X23_Y8_N30; Fanout = 6; COMB Node = 'Add2~37' + Info: 5: + IC(0.671 ns) + CELL(0.426 ns) = 9.935 ns; Loc. = LCCOMB_X22_Y7_N0; Fanout = 7; COMB Node = 'Add3~33' + Info: 6: + IC(0.674 ns) + CELL(0.570 ns) = 11.179 ns; Loc. = LCCOMB_X22_Y6_N30; Fanout = 2; COMB Node = 'Add4~38' + Info: 7: + IC(0.000 ns) + CELL(0.041 ns) = 11.220 ns; Loc. = LCCOMB_X22_Y5_N0; Fanout = 2; COMB Node = 'Add4~42' + Info: 8: + IC(0.000 ns) + CELL(0.041 ns) = 11.261 ns; Loc. = LCCOMB_X22_Y5_N2; Fanout = 2; COMB Node = 'Add4~46' + Info: 9: + IC(0.000 ns) + CELL(0.041 ns) = 11.302 ns; Loc. = LCCOMB_X22_Y5_N4; Fanout = 2; COMB Node = 'Add4~50' + Info: 10: + IC(0.000 ns) + CELL(0.144 ns) = 11.446 ns; Loc. = LCCOMB_X22_Y5_N6; Fanout = 7; COMB Node = 'Add4~53' + Info: 11: + IC(0.677 ns) + CELL(0.502 ns) = 12.625 ns; Loc. = LCCOMB_X25_Y5_N6; Fanout = 2; COMB Node = 'Add8~46' + Info: 12: + IC(0.000 ns) + CELL(0.041 ns) = 12.666 ns; Loc. = LCCOMB_X25_Y5_N8; Fanout = 2; COMB Node = 'Add8~50' + Info: 13: + IC(0.000 ns) + CELL(0.041 ns) = 12.707 ns; Loc. = LCCOMB_X25_Y5_N10; Fanout = 2; COMB Node = 'Add8~54' + Info: 14: + IC(0.000 ns) + CELL(0.041 ns) = 12.748 ns; Loc. = LCCOMB_X25_Y5_N12; Fanout = 1; COMB Node = 'Add8~58' + Info: 15: + IC(0.000 ns) + CELL(0.144 ns) = 12.892 ns; Loc. = LCCOMB_X25_Y5_N14; Fanout = 1; COMB Node = 'Add8~61' + Info: 16: + IC(0.553 ns) + CELL(0.426 ns) = 13.871 ns; Loc. = LCCOMB_X26_Y5_N30; Fanout = 2; COMB Node = 'Add9~61' + Info: 17: + IC(0.902 ns) + CELL(0.355 ns) = 15.128 ns; Loc. = LCFF_X23_Y7_N3; Fanout = 4; REG Node = 'resultado[15]' + Info: Total cell delay = 4.715 ns ( 31.17 % ) + Info: Total interconnect delay = 10.413 ns ( 68.83 % ) + Info: + Micro setup delay of destination is 0.104 ns + Info: - Shortest clock path from clock "clk_i" to destination register is 2.830 ns + Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i' + Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 195; COMB Node = 'clk_i~clkctrl' + Info: 3: + IC(0.752 ns) + CELL(0.710 ns) = 2.830 ns; Loc. = LCFF_X23_Y7_N3; Fanout = 4; REG Node = 'resultado[15]' + Info: Total cell delay = 1.684 ns ( 59.51 % ) + Info: Total interconnect delay = 1.146 ns ( 40.49 % ) +Info: tco from clock "clk_i" to destination pin "fxx3_o[14]" through register "fxx3_o[14]~reg0" is 8.310 ns + Info: + Longest clock path from clock "clk_i" to source register is 2.842 ns + Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i' + Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 195; COMB Node = 'clk_i~clkctrl' + Info: 3: + IC(0.764 ns) + CELL(0.710 ns) = 2.842 ns; Loc. = LCFF_X22_Y5_N13; Fanout = 1; REG Node = 'fxx3_o[14]~reg0' + Info: Total cell delay = 1.684 ns ( 59.25 % ) + Info: Total interconnect delay = 1.158 ns ( 40.75 % ) + Info: + Micro clock to output delay of source is 0.109 ns + Info: + Longest register to pin delay is 5.359 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y5_N13; Fanout = 1; REG Node = 'fxx3_o[14]~reg0' + Info: 2: + IC(2.924 ns) + CELL(2.435 ns) = 5.359 ns; Loc. = PIN_J5; Fanout = 0; PIN Node = 'fxx3_o[14]' + Info: Total cell delay = 2.435 ns ( 45.44 % ) + Info: Total interconnect delay = 2.924 ns ( 54.56 % ) +Info: th for register "resultado[15]" (data pin = "rst_i", clock pin = "clk_i") is -1.094 ns + Info: + Longest clock path from clock "clk_i" to destination register is 2.830 ns + Info: 1: + IC(0.000 ns) + CELL(0.974 ns) = 0.974 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk_i' + Info: 2: + IC(0.394 ns) + CELL(0.000 ns) = 1.368 ns; Loc. = CLKCTRL_G3; Fanout = 195; COMB Node = 'clk_i~clkctrl' + Info: 3: + IC(0.752 ns) + CELL(0.710 ns) = 2.830 ns; Loc. = LCFF_X23_Y7_N3; Fanout = 4; REG Node = 'resultado[15]' + Info: Total cell delay = 1.684 ns ( 59.51 % ) + Info: Total interconnect delay = 1.146 ns ( 40.49 % ) + Info: + Micro hold delay of destination is 0.172 ns + Info: - Shortest pin to register delay is 4.096 ns + Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_M21; Fanout = 98; PIN Node = 'rst_i' + Info: 2: + IC(2.254 ns) + CELL(0.858 ns) = 4.096 ns; Loc. = LCFF_X23_Y7_N3; Fanout = 4; REG Node = 'resultado[15]' + Info: Total cell delay = 1.842 ns ( 44.97 % ) + Info: Total interconnect delay = 2.254 ns ( 55.03 % ) +Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings + Info: Peak virtual memory: 153 megabytes + Info: Processing ended: Tue Aug 14 00:28:18 2012 + Info: Elapsed time: 00:00:06 + Info: Total CPU time (on all processors): 00:00:06 + + Index: trunk/QuartusII/gnextrapolator.pin =================================================================== --- trunk/QuartusII/gnextrapolator.pin (nonexistent) +++ trunk/QuartusII/gnextrapolator.pin (revision 5) @@ -0,0 +1,559 @@ + -- Copyright (C) 1991-2010 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- Bank 3: 3.3V + -- Bank 4: 3.3V + -- Bank 5: 3.3V + -- Bank 6: 3.3V + -- Bank 7: 3.3V + -- Bank 8: 3.3V + -- Bank 9: 3.3V + -- Bank 10: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. For transceiver I/O banks, connect each pin marked GND* + -- either individually through a 10k Ohm resistor to GND or tie all pins + -- together and connect through a single 10k Ohm resistor to GND. + -- For non-transceiver I/O banks, connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition +CHIP "gnextrapolator" ASSIGNED TO AN: EP2S15F484C4 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +TEMPDIODEp : A2 : : : : : +VCCIO4 : A3 : power : : 3.3V : 4 : +MSEL3 : A4 : : : : 4 : +GND* : A5 : : : : 4 : +GND* : A6 : : : : 4 : +fxx1_o[1] : A7 : output : 3.3-V LVTTL : : 4 : N +fxx_o[8] : A8 : output : 3.3-V LVTTL : : 4 : N +GND : A9 : gnd : : : : +fxx3_o[2] : A10 : output : 3.3-V LVTTL : : 9 : N +VCCIO4 : A11 : power : : 3.3V : 4 : +VCCIO3 : A12 : power : : 3.3V : 3 : +fxx3_o[7] : A13 : output : 3.3-V LVTTL : : 3 : N +GND : A14 : gnd : : : : +GND* : A15 : : : : 3 : +GND* : A16 : : : : 3 : +GND* : A17 : : : : 3 : +GND* : A18 : : : : 3 : +GND* : A19 : : : : 3 : +VCCIO3 : A20 : power : : 3.3V : 3 : +nCE : A21 : : : : 3 : +GND : A22 : gnd : : : : +VCCIO6 : AA1 : power : : 3.3V : 6 : +GND : AA2 : gnd : : : : +nCEO : AA3 : : : : 7 : +GND* : AA4 : : : : 7 : +GND* : AA5 : : : : 7 : +GND* : AA6 : : : : 7 : +resul_o[1] : AA7 : output : 3.3-V LVTTL : : 7 : N +distancia_i[3] : AA8 : input : 3.3-V LVTTL : : 7 : N +fxx3_o[10] : AA9 : output : 3.3-V LVTTL : : 10 : N +fxx2_o[13] : AA10 : output : 3.3-V LVTTL : : 10 : N +fxx3_o[6] : AA11 : output : 3.3-V LVTTL : : 7 : N +GND* : AA12 : : : : 8 : +GND* : AA13 : : : : 8 : +VREFB8 : AA14 : power : : : 8 : +GND* : AA15 : : : : 8 : +GND* : AA16 : : : : 8 : +GND* : AA17 : : : : 8 : +GND* : AA18 : : : : 8 : +TCK : AA19 : input : : : 8 : +TMS : AA20 : input : : : 8 : +GND : AA21 : gnd : : : : +VCCIO1 : AA22 : power : : 3.3V : 1 : +GND : AB1 : gnd : : : : +nIO_PULLUP : AB2 : : : : 7 : +VCCIO7 : AB3 : power : : 3.3V : 7 : +GND : AB4 : gnd : : : : +resul_o[3] : AB5 : output : 3.3-V LVTTL : : 7 : N +resul_o[12] : AB6 : output : 3.3-V LVTTL : : 7 : N +GND* : AB7 : : : : 7 : +resul_o[0] : AB8 : output : 3.3-V LVTTL : : 7 : N +GND : AB9 : gnd : : : : +fxx2_o[12] : AB10 : output : 3.3-V LVTTL : : 10 : N +VCCIO7 : AB11 : power : : 3.3V : 7 : +VCCIO8 : AB12 : power : : 3.3V : 8 : +fxx4_o[6] : AB13 : output : 3.3-V LVTTL : : 8 : N +GND : AB14 : gnd : : : : +GND* : AB15 : : : : 8 : +GND* : AB16 : : : : 8 : +GND* : AB17 : : : : 8 : +fxx2_o[0] : AB18 : output : 3.3-V LVTTL : : 8 : N +TRST : AB19 : input : : : 8 : +VCCIO8 : AB20 : power : : 3.3V : 8 : +TDI : AB21 : input : : : 8 : +GND : AB22 : gnd : : : : +VCCIO5 : B1 : power : : 3.3V : 5 : +GND : B2 : gnd : : : : +TDO : B3 : output : : : 4 : +MSEL2 : B4 : : : : 4 : +GND* : B5 : : : : 4 : +GND* : B6 : : : : 4 : +fxx_o[11] : B7 : output : 3.3-V LVTTL : : 4 : N +distancia_i[5] : B8 : input : 3.3-V LVTTL : : 4 : N +extrapolar_i : B9 : input : 3.3-V LVTTL : : 9 : N +fxx_o[10] : B10 : output : 3.3-V LVTTL : : 9 : N +GND* : B11 : : : : 4 : +fxx2_o[9] : B12 : output : 3.3-V LVTTL : : 4 : N +fxx3_o[0] : B13 : output : 3.3-V LVTTL : : 3 : N +VREFB3 : B14 : power : : : 3 : +resul_o[11] : B15 : output : 3.3-V LVTTL : : 3 : N +GND* : B16 : : : : 3 : +GND* : B17 : : : : 3 : +GND* : B18 : : : : 3 : +GND* : B19 : : : : 3 : +nSTATUS : B20 : : : : 3 : +GND : B21 : gnd : : : : +VCCIO2 : B22 : power : : 3.3V : 2 : +GND* : C1 : : : : 5 : +GND* : C2 : : : : 5 : +TEMPDIODEn : C3 : : : : : +GND* : C4 : : : : 4 : +GND* : C5 : : : : 4 : +GND* : C6 : : : : 4 : +fxx3_o[12] : C7 : output : 3.3-V LVTTL : : 4 : N +GND* : C8 : : : : 4 : +fxx2_o[14] : C9 : output : 3.3-V LVTTL : : 9 : N +fxx2_o[15] : C10 : output : 3.3-V LVTTL : : 9 : N +fxx1_o[4] : C11 : output : 3.3-V LVTTL : : 4 : N +fxx_o[2] : C12 : output : 3.3-V LVTTL : : 4 : N +fxx2_o[6] : C13 : output : 3.3-V LVTTL : : 3 : N +GND* : C14 : : : : 3 : +GND* : C15 : : : : 3 : +GND* : C16 : : : : 3 : +GND* : C17 : : : : 3 : +GND* : C18 : : : : 3 : +GND* : C19 : : : : 3 : +CONF_DONE : C20 : : : : 3 : +GND* : C21 : : : : 2 : +GND* : C22 : : : : 2 : +GND* : D1 : : : : 5 : +GND* : D2 : : : : 5 : +GND* : D3 : : : : 4 : +MSEL1 : D4 : : : : 4 : +GND* : D5 : : : : 4 : +fxx_o[3] : D6 : output : 3.3-V LVTTL : : 4 : N +VREFB4 : D7 : power : : : 4 : +GND* : D8 : : : : 4 : +VREFB4 : D9 : power : : : 4 : +fxx_o[5] : D10 : output : 3.3-V LVTTL : : 9 : N +GND* : D11 : : : : 3 : +fxx3_o[5] : D12 : output : 3.3-V LVTTL : : 3 : N +GND* : D13 : : : : 3 : +GND* : D14 : : : : 3 : +GND* : D15 : : : : 3 : +VREFB3 : D16 : power : : : 3 : +GND* : D17 : : : : 3 : +GND* : D18 : : : : 3 : +DCLK : D19 : : : : 3 : +GND* : D20 : : : : 3 : +GND* : D21 : : : : 2 : +GND* : D22 : : : : 2 : +GND* : E1 : : : : 5 : +GND* : E2 : : : : 5 : +GND* : E3 : : : : 5 : +GND* : E4 : : : : 5 : +MSEL0 : E5 : : : : 4 : +GND* : E6 : : : : 4 : +distancia_i[4] : E7 : input : 3.3-V LVTTL : : 4 : N +GND* : E8 : : : : 4 : +GND* : E9 : : : : 4 : +GND* : E10 : : : : 4 : +GND* : E11 : : : : 3 : +GND* : E12 : : : : 3 : +~DATA0~ / RESERVED_INPUT : E13 : input : 3.3-V LVTTL : : 3 : N +GND* : E14 : : : : 3 : +GND* : E15 : : : : 3 : +GND* : E16 : : : : 3 : +GND* : E17 : : : : 3 : +GND* : E18 : : : : 3 : +GND* : E19 : : : : 2 : +GND* : E20 : : : : 2 : +GND* : E21 : : : : 2 : +GND* : E22 : : : : 2 : +GND* : F1 : : : : 5 : +GND* : F2 : : : : 5 : +VREFB5 : F3 : power : : : 5 : +GND* : F4 : : : : 5 : +GND* : F5 : : : : 5 : +GND* : F6 : : : : 4 : +GND* : F7 : : : : 4 : +GND* : F8 : : : : 4 : +GND* : F9 : : : : 4 : +GNDA_PLL5 : F10 : gnd : : : : +GNDA_PLL5 : F11 : gnd : : : : +VCCA_PLL5 : F12 : power : : 1.2V : : +GND* : F13 : : : : 3 : +GND* : F14 : : : : 3 : +GND* : F15 : : : : 3 : +GND* : F16 : : : : 3 : +GND* : F17 : : : : 3 : +VREFB2 : F18 : power : : : 2 : +GND* : F19 : : : : 2 : +GND* : F20 : : : : 2 : +GND* : F21 : : : : 2 : +GND* : F22 : : : : 2 : +GND* : G1 : : : : 5 : +GND* : G2 : : : : 5 : +GND* : G3 : : : : 5 : +GND* : G4 : : : : 5 : +GND* : G5 : : : : 5 : +GND* : G6 : : : : 5 : +GND* : G7 : : : : 4 : +GND* : G8 : : : : 4 : +GND* : G9 : : : : 4 : +VCC_PLL5_OUT : G10 : power : : 3.3V : 9 : +VCCD_PLL5 : G11 : power : : 1.2V : : +GND* : G12 : : : : 3 : +GND* : G13 : : : : 3 : +GND* : G14 : : : : 3 : +GND* : G15 : : : : 3 : +GND* : G16 : : : : 3 : +GND* : G17 : : : : 2 : +GND* : G18 : : : : 2 : +GND* : G19 : : : : 2 : +GND* : G20 : : : : 2 : +GND* : G21 : : : : 2 : +GND* : G22 : : : : 2 : +fxx3_o[3] : H1 : output : 3.3-V LVTTL : : 5 : N +GND* : H2 : : : : 5 : +GND* : H3 : : : : 5 : +GND* : H4 : : : : 5 : +GND* : H5 : : : : 5 : +GND* : H6 : : : : 5 : +GND* : H7 : : : : 4 : +VCCINT : H8 : power : : 1.2V : : +GND* : H9 : : : : 4 : +VCCPD4 : H10 : power : : 3.3V : 4 : +fxx_o[6] : H11 : output : 3.3-V LVTTL : : 3 : N +GND* : H12 : : : : 3 : +VCCPD3 : H13 : power : : 3.3V : 3 : +GND* : H14 : : : : 3 : +GND : H15 : gnd : : : : +GND* : H16 : : : : 3 : +GND* : H17 : : : : 2 : +GND* : H18 : : : : 2 : +GND* : H19 : : : : 2 : +GND* : H20 : : : : 2 : +GND* : H21 : : : : 2 : +GND* : H22 : : : : 2 : +GND : J1 : gnd : : : : +GND* : J2 : : : : 5 : +fxx1_o[8] : J3 : output : 3.3-V LVTTL : : 5 : N +VREFB5 : J4 : power : : : 5 : +fxx3_o[14] : J5 : output : 3.3-V LVTTL : : 5 : N +fxx3_o[15] : J6 : output : 3.3-V LVTTL : : 5 : N +GND* : J7 : : : : 5 : +GND* : J8 : : : : 5 : +VCCINT : J9 : power : : 1.2V : : +GND : J10 : gnd : : : : +VCCINT : J11 : power : : 1.2V : : +GND : J12 : gnd : : : : +VCCINT : J13 : power : : 1.2V : : +GND : J14 : gnd : : : : +GND* : J15 : : : : 3 : +GND* : J16 : : : : 2 : +GND* : J17 : : : : 2 : +GND* : J18 : : : : 2 : +GND* : J19 : : : : 2 : +GND* : J20 : : : : 2 : +GND* : J21 : : : : 2 : +GND : J22 : gnd : : : : +GND* : K1 : : : : 5 : +GND* : K2 : : : : 5 : +fxx1_o[12] : K3 : output : 3.3-V LVTTL : : 5 : N +fxx1_o[11] : K4 : output : 3.3-V LVTTL : : 5 : N +fxx1_o[15] : K5 : output : 3.3-V LVTTL : : 5 : N +GND* : K6 : : : : 5 : +fxx_o[0] : K7 : output : 3.3-V LVTTL : : 5 : N +distancia_i[7] : K8 : input : 3.3-V LVTTL : : 5 : N +GND : K9 : gnd : : : : +VCCINT : K10 : power : : 1.2V : : +GND : K11 : gnd : : : : +VCCINT : K12 : power : : 1.2V : : +GND : K13 : gnd : : : : +VCCPD2 : K14 : power : : 3.3V : 2 : +GND* : K15 : : : : 2 : +GND* : K16 : : : : 2 : +GND* : K17 : : : : 2 : +GND* : K18 : : : : 2 : +GND* : K19 : : : : 2 : +GND* : K20 : : : : 2 : +GND* : K21 : : : : 2 : +GND* : K22 : : : : 2 : +VCCIO5 : L1 : power : : 3.3V : 5 : +fxx1_o[0] : L2 : output : 3.3-V LVTTL : : 5 : N +fxx2_o[1] : L3 : output : 3.3-V LVTTL : : 5 : N +GNDA_PLL4 : L4 : gnd : : : : +GNDA_PLL4 : L5 : gnd : : : : +VCCD_PLL4 : L6 : power : : 1.2V : : +fxx2_o[7] : L7 : output : 3.3-V LVTTL : : 5 : N +fxx_o[4] : L8 : output : 3.3-V LVTTL : : 5 : N +VCCPD5 : L9 : power : : 3.3V : 5 : +GND : L10 : gnd : : : : +VCCINT : L11 : power : : 1.2V : : +GND : L12 : gnd : : : : +VCCINT : L13 : power : : 1.2V : : +GND : L14 : gnd : : : : +GND* : L15 : : : : 2 : +GND* : L16 : : : : 2 : +GNDA_PLL1 : L17 : gnd : : : : +GNDA_PLL1 : L18 : gnd : : : : +VREFB2 : L19 : power : : : 2 : +fxx1_o[2] : L20 : output : 3.3-V LVTTL : : 2 : N +GND* : L21 : : : : 2 : +VCCIO2 : L22 : power : : 3.3V : 2 : +VCCIO6 : M1 : power : : 3.3V : 6 : +distancia_i[6] : M2 : input : 3.3-V LVTTL : : 5 : N +GND+ : M3 : : : : 5 : +VCCA_PLL3 : M4 : power : : 1.2V : : +VCCD_PLL3 : M5 : power : : 1.2V : : +VCCA_PLL4 : M6 : power : : 1.2V : : +GND : M7 : gnd : : : : +VCCINT : M8 : power : : 1.2V : : +GND : M9 : gnd : : : : +VCCINT : M10 : power : : 1.2V : : +GND : M11 : gnd : : : : +VCCINT : M12 : power : : 1.2V : : +GND : M13 : gnd : : : : +VCCINT : M14 : power : : 1.2V : : +GND : M15 : gnd : : : : +VCCD_PLL1 : M16 : power : : 1.2V : : +VCCA_PLL1 : M17 : power : : 1.2V : : +VCCD_PLL2 : M18 : power : : 1.2V : : +VCCA_PLL2 : M19 : power : : 1.2V : : +GND+ : M20 : : : : 2 : +rst_i : M21 : input : 3.3-V LVTTL : : 2 : N +VCCIO1 : M22 : power : : 3.3V : 1 : +GND* : N1 : : : : 6 : +fxx2_o[5] : N2 : output : 3.3-V LVTTL : : 6 : N +distancia_i[2] : N3 : input : 3.3-V LVTTL : : 6 : N +GND+ : N4 : : : : 6 : +GNDA_PLL3 : N5 : gnd : : : : +GNDA_PLL3 : N6 : gnd : : : : +fxx2_o[4] : N7 : output : 3.3-V LVTTL : : 6 : N +fxx2_o[2] : N8 : output : 3.3-V LVTTL : : 6 : N +VCCPD6 : N9 : power : : 3.3V : 6 : +GND : N10 : gnd : : : : +VCCINT : N11 : power : : 1.2V : : +GND : N12 : gnd : : : : +VCCINT : N13 : power : : 1.2V : : +GND : N14 : gnd : : : : +GND* : N15 : : : : 1 : +GND* : N16 : : : : 1 : +GNDA_PLL2 : N17 : gnd : : : : +GNDA_PLL2 : N18 : gnd : : : : +GND+ : N19 : : : : 1 : +clk_i : N20 : input : 3.3-V LVTTL : : 1 : N +GND* : N21 : : : : 1 : +GND* : N22 : : : : 1 : +GND : P1 : gnd : : : : +fxx4_o[1] : P2 : output : 3.3-V LVTTL : : 6 : N +fxx_o[14] : P3 : output : 3.3-V LVTTL : : 6 : N +VREFB6 : P4 : power : : : 6 : +fxx1_o[3] : P5 : output : 3.3-V LVTTL : : 6 : N +fxx1_o[14] : P6 : output : 3.3-V LVTTL : : 6 : N +fxx_o[7] : P7 : output : 3.3-V LVTTL : : 6 : N +distancia_i[1] : P8 : input : 3.3-V LVTTL : : 6 : N +VCCINT : P9 : power : : 1.2V : : +VCCPD7 : P10 : power : : 3.3V : 7 : +GND : P11 : gnd : : : : +VCCINT : P12 : power : : 1.2V : : +GND : P13 : gnd : : : : +VCCINT : P14 : power : : 1.2V : : +VCCPD1 : P15 : power : : 3.3V : 1 : +fxx2_o[8] : P16 : output : 3.3-V LVTTL : : 1 : N +fxx_o[1] : P17 : output : 3.3-V LVTTL : : 1 : N +fxx1_o[6] : P18 : output : 3.3-V LVTTL : : 1 : N +GND* : P19 : : : : 1 : +GND* : P20 : : : : 1 : +GND* : P21 : : : : 1 : +GND : P22 : gnd : : : : +fxx1_o[7] : R1 : output : 3.3-V LVTTL : : 6 : N +resul_o[5] : R2 : output : 3.3-V LVTTL : : 6 : N +GND* : R3 : : : : 6 : +fxx3_o[11] : R4 : output : 3.3-V LVTTL : : 6 : N +resul_o[10] : R5 : output : 3.3-V LVTTL : : 6 : N +fxx4_o[0] : R6 : output : 3.3-V LVTTL : : 6 : N +fxx3_o[8] : R7 : output : 3.3-V LVTTL : : 6 : N +fxx4_o[11] : R8 : output : 3.3-V LVTTL : : 6 : N +distancia_i[0] : R9 : input : 3.3-V LVTTL : : 7 : N +GND : R10 : gnd : : : : +VCC_PLL6_OUT : R11 : power : : 3.3V : 10 : +VCCA_PLL6 : R12 : power : : 1.2V : : +VCCPD8 : R13 : power : : 3.3V : 8 : +GND* : R14 : : : : 8 : +GND* : R15 : : : : 8 : +GND* : R16 : : : : 1 : +GND* : R17 : : : : 1 : +GND* : R18 : : : : 1 : +fxx4_o[15] : R19 : output : 3.3-V LVTTL : : 1 : N +VREFB1 : R20 : power : : : 1 : +GND* : R21 : : : : 1 : +GND* : R22 : : : : 1 : +fxx_o[9] : T1 : output : 3.3-V LVTTL : : 6 : N +fxx_o[13] : T2 : output : 3.3-V LVTTL : : 6 : N +fxx3_o[9] : T3 : output : 3.3-V LVTTL : : 6 : N +fxx4_o[12] : T4 : output : 3.3-V LVTTL : : 6 : N +fxx4_o[9] : T5 : output : 3.3-V LVTTL : : 6 : N +fxx2_o[10] : T6 : output : 3.3-V LVTTL : : 6 : N +GND* : T7 : : : : 7 : +GND* : T8 : : : : 7 : +fxx1_o[13] : T9 : output : 3.3-V LVTTL : : 7 : N +fxx_o[15] : T10 : output : 3.3-V LVTTL : : 7 : N +GNDA_PLL6 : T11 : gnd : : : : +GNDA_PLL6 : T12 : gnd : : : : +GND* : T13 : : : : 8 : +GND* : T14 : : : : 8 : +GND* : T15 : : : : 8 : +resul_o[14] : T16 : output : 3.3-V LVTTL : : 8 : N +resul_o[8] : T17 : output : 3.3-V LVTTL : : 1 : N +fxx4_o[10] : T18 : output : 3.3-V LVTTL : : 1 : N +resul_o[4] : T19 : output : 3.3-V LVTTL : : 1 : N +resul_o[13] : T20 : output : 3.3-V LVTTL : : 1 : N +fxx_o[12] : T21 : output : 3.3-V LVTTL : : 1 : N +resul_o[7] : T22 : output : 3.3-V LVTTL : : 1 : N +fxx4_o[14] : U1 : output : 3.3-V LVTTL : : 6 : N +fxx4_o[7] : U2 : output : 3.3-V LVTTL : : 6 : N +VREFB6 : U3 : power : : : 6 : +resul_o[15] : U4 : output : 3.3-V LVTTL : : 6 : N +fxx4_o[8] : U5 : output : 3.3-V LVTTL : : 6 : N +GND* : U6 : : : : 7 : +GND* : U7 : : : : 7 : +GND* : U8 : : : : 7 : +GND* : U9 : : : : 7 : +GND* : U10 : : : : 7 : +VCCD_PLL6 : U11 : power : : 1.2V : : +GND* : U12 : : : : 8 : +GND* : U13 : : : : 8 : +GND* : U14 : : : : 8 : +GND* : U15 : : : : 8 : +GND* : U16 : : : : 8 : +GND* : U17 : : : : 1 : +GND* : U18 : : : : 1 : +GND* : U19 : : : : 1 : +fxx3_o[1] : U20 : output : 3.3-V LVTTL : : 1 : N +resul_o[6] : U21 : output : 3.3-V LVTTL : : 1 : N +fxx4_o[13] : U22 : output : 3.3-V LVTTL : : 1 : N +GND* : V1 : : : : 6 : +fxx1_o[5] : V2 : output : 3.3-V LVTTL : : 6 : N +GND* : V3 : : : : 6 : +GND* : V4 : : : : 6 : +PORSEL : V5 : : : : 7 : +GND* : V6 : : : : 7 : +GND* : V7 : : : : 7 : +fxx4_o[4] : V8 : output : 3.3-V LVTTL : : 7 : N +fxx4_o[2] : V9 : output : 3.3-V LVTTL : : 10 : N +GND* : V10 : : : : 7 : +GND* : V11 : : : : 8 : +fxx2_o[11] : V12 : output : 3.3-V LVTTL : : 8 : N +GND* : V13 : : : : 8 : +GND* : V14 : : : : 8 : +GND* : V15 : : : : 8 : +GND* : V16 : : : : 8 : +VCCSEL : V17 : : : : 8 : +GND* : V18 : : : : 1 : +GND* : V19 : : : : 1 : +VREFB1 : V20 : power : : : 1 : +GND* : V21 : : : : 1 : +GND* : V22 : : : : 1 : +fxx2_o[3] : W1 : output : 3.3-V LVTTL : : 6 : N +GND* : W2 : : : : 6 : +GND* : W3 : : : : 6 : +GND* : W4 : : : : 6 : +GND* : W5 : : : : 7 : +VREFB7 : W6 : power : : : 7 : +GND* : W7 : : : : 7 : +VREFB7 : W8 : power : : : 7 : +fxx1_o[9] : W9 : output : 3.3-V LVTTL : : 10 : N +fxx4_o[5] : W10 : output : 3.3-V LVTTL : : 7 : N +GND* : W11 : : : : 8 : +GND* : W12 : : : : 8 : +GND* : W13 : : : : 8 : +GND* : W14 : : : : 8 : +GND* : W15 : : : : 8 : +GND* : W16 : : : : 8 : +GND* : W17 : : : : 8 : +nCONFIG : W18 : : : : 8 : +GND* : W19 : : : : 1 : +GND* : W20 : : : : 1 : +GND* : W21 : : : : 1 : +GND* : W22 : : : : 1 : +GND* : Y1 : : : : 6 : +GND* : Y2 : : : : 6 : +GND* : Y3 : : : : 7 : +PLL_ENA : Y4 : : : : 7 : +GND* : Y5 : : : : 7 : +GND* : Y6 : : : : 7 : +resul_o[2] : Y7 : output : 3.3-V LVTTL : : 7 : N +resul_o[9] : Y8 : output : 3.3-V LVTTL : : 7 : N +fxx4_o[3] : Y9 : output : 3.3-V LVTTL : : 10 : N +fxx1_o[10] : Y10 : output : 3.3-V LVTTL : : 7 : N +fxx3_o[13] : Y11 : output : 3.3-V LVTTL : : 7 : N +fxx3_o[4] : Y12 : output : 3.3-V LVTTL : : 8 : N +GND* : Y13 : : : : 8 : +GND* : Y14 : : : : 8 : +GND* : Y15 : : : : 8 : +GND* : Y16 : : : : 8 : +GND* : Y17 : : : : 8 : +GND* : Y18 : : : : 8 : +VREFB8 : Y19 : power : : : 8 : +GND* : Y20 : : : : 8 : +GND* : Y21 : : : : 1 : +GND* : Y22 : : : : 1 : Index: trunk/QuartusII/gnextrapolator.qpf =================================================================== --- trunk/QuartusII/gnextrapolator.qpf (nonexistent) +++ trunk/QuartusII/gnextrapolator.qpf (revision 5) @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2010 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition +# Date created = 23:38:03 August 13, 2012 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "9.1" +DATE = "23:38:03 August 13, 2012" + +# Revisions + +PROJECT_REVISION = "gnextrapolator" Index: trunk/QuartusII/gnextrapolator.fit.rpt =================================================================== --- trunk/QuartusII/gnextrapolator.fit.rpt (nonexistent) +++ trunk/QuartusII/gnextrapolator.fit.rpt (revision 5) @@ -0,0 +1,2129 @@ +Fitter report for gnextrapolator +Tue Aug 14 00:28:05 2012 +Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. I/O Assignment Warnings + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Input Pins + 11. Output Pins + 12. I/O Bank Usage + 13. All Package Pins + 14. Output Pin Default Load For Reported TCO + 15. Fitter Resource Utilization by Entity + 16. Delay Chain Summary + 17. Pad To Core Delay Chain Fanout + 18. Control Signals + 19. Global & Other Fast Signals + 20. Non-Global High Fan-Out Signals + 21. Fitter RAM Summary + 22. Interconnect Usage Summary + 23. LAB Logic Elements + 24. LAB-wide Signals + 25. LAB Signals Sourced + 26. LAB Signals Sourced Out + 27. LAB Distinct Inputs + 28. I/O Rules Summary + 29. I/O Rules Details + 30. I/O Rules Matrix + 31. Fitter Device Options + 32. Operating Settings and Conditions + 33. Estimated Delay Added for Hold Timing + 34. Fitter Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++------------------------------------------------------------------------------+ +; Fitter Summary ; ++-------------------------------+----------------------------------------------+ +; Fitter Status ; Successful - Tue Aug 14 00:28:04 2012 ; +; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ; +; Revision Name ; gnextrapolator ; +; Top-level Entity Name ; gnextrapolator ; +; Family ; Stratix II ; +; Device ; EP2S15F484C4 ; +; Timing Models ; Final ; +; Logic utilization ; 2 % ; +; Combinational ALUTs ; 169 / 12,480 ( 1 % ) ; +; Dedicated logic registers ; 190 / 12,480 ( 2 % ) ; +; Total registers ; 190 ; +; Total pins ; 107 / 343 ( 31 % ) ; +; Total virtual pins ; 0 ; +; Total block memory bits ; 512 / 419,328 ( < 1 % ) ; +; DSP block 9-bit elements ; 0 / 96 ( 0 % ) ; +; Total PLLs ; 0 / 6 ( 0 % ) ; +; Total DLLs ; 0 / 2 ( 0 % ) ; ++-------------------------------+----------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Device ; EP2S15F484C4 ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Use TimeQuest Timing Analyzer ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Always Enable Input Buffers ; Off ; Off ; +; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; +; Optimize Multi-Corner Timing ; Off ; Off ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; On ; On ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Global Memory Control Signals ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Merge PLLs ; On ; On ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ; +; Auto Register Duplication ; Auto ; Auto ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Stop After Congestion Map Generation ; Off ; Off ; +; Save Intermediate Fitting Results ; Off ; Off ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; +; Use Best Effort Settings for Compilation ; Off ; Off ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ + + ++------------------------------------------------+ +; I/O Assignment Warnings ; ++----------------+-------------------------------+ +; Pin Name ; Reason ; ++----------------+-------------------------------+ +; fxx_o[0] ; Incomplete set of assignments ; +; fxx_o[1] ; Incomplete set of assignments ; +; fxx_o[2] ; Incomplete set of assignments ; +; fxx_o[3] ; Incomplete set of assignments ; +; fxx_o[4] ; Incomplete set of assignments ; +; fxx_o[5] ; Incomplete set of assignments ; +; fxx_o[6] ; Incomplete set of assignments ; +; fxx_o[7] ; Incomplete set of assignments ; +; fxx_o[8] ; Incomplete set of assignments ; +; fxx_o[9] ; Incomplete set of assignments ; +; fxx_o[10] ; Incomplete set of assignments ; +; fxx_o[11] ; Incomplete set of assignments ; +; fxx_o[12] ; Incomplete set of assignments ; +; fxx_o[13] ; Incomplete set of assignments ; +; fxx_o[14] ; Incomplete set of assignments ; +; fxx_o[15] ; Incomplete set of assignments ; +; fxx1_o[0] ; Incomplete set of assignments ; +; fxx1_o[1] ; Incomplete set of assignments ; +; fxx1_o[2] ; Incomplete set of assignments ; +; fxx1_o[3] ; Incomplete set of assignments ; +; fxx1_o[4] ; Incomplete set of assignments ; +; fxx1_o[5] ; Incomplete set of assignments ; +; fxx1_o[6] ; Incomplete set of assignments ; +; fxx1_o[7] ; Incomplete set of assignments ; +; fxx1_o[8] ; Incomplete set of assignments ; +; fxx1_o[9] ; Incomplete set of assignments ; +; fxx1_o[10] ; Incomplete set of assignments ; +; fxx1_o[11] ; Incomplete set of assignments ; +; fxx1_o[12] ; Incomplete set of assignments ; +; fxx1_o[13] ; Incomplete set of assignments ; +; fxx1_o[14] ; Incomplete set of assignments ; +; fxx1_o[15] ; Incomplete set of assignments ; +; fxx2_o[0] ; Incomplete set of assignments ; +; fxx2_o[1] ; Incomplete set of assignments ; +; fxx2_o[2] ; Incomplete set of assignments ; +; fxx2_o[3] ; Incomplete set of assignments ; +; fxx2_o[4] ; Incomplete set of assignments ; +; fxx2_o[5] ; Incomplete set of assignments ; +; fxx2_o[6] ; Incomplete set of assignments ; +; fxx2_o[7] ; Incomplete set of assignments ; +; fxx2_o[8] ; Incomplete set of assignments ; +; fxx2_o[9] ; Incomplete set of assignments ; +; fxx2_o[10] ; Incomplete set of assignments ; +; fxx2_o[11] ; Incomplete set of assignments ; +; fxx2_o[12] ; Incomplete set of assignments ; +; fxx2_o[13] ; Incomplete set of assignments ; +; fxx2_o[14] ; Incomplete set of assignments ; +; fxx2_o[15] ; Incomplete set of assignments ; +; fxx3_o[0] ; Incomplete set of assignments ; +; fxx3_o[1] ; Incomplete set of assignments ; +; fxx3_o[2] ; Incomplete set of assignments ; +; fxx3_o[3] ; Incomplete set of assignments ; +; fxx3_o[4] ; Incomplete set of assignments ; +; fxx3_o[5] ; Incomplete set of assignments ; +; fxx3_o[6] ; Incomplete set of assignments ; +; fxx3_o[7] ; Incomplete set of assignments ; +; fxx3_o[8] ; Incomplete set of assignments ; +; fxx3_o[9] ; Incomplete set of assignments ; +; fxx3_o[10] ; Incomplete set of assignments ; +; fxx3_o[11] ; Incomplete set of assignments ; +; fxx3_o[12] ; Incomplete set of assignments ; +; fxx3_o[13] ; Incomplete set of assignments ; +; fxx3_o[14] ; Incomplete set of assignments ; +; fxx3_o[15] ; Incomplete set of assignments ; +; fxx4_o[0] ; Incomplete set of assignments ; +; fxx4_o[1] ; Incomplete set of assignments ; +; fxx4_o[2] ; Incomplete set of assignments ; +; fxx4_o[3] ; Incomplete set of assignments ; +; fxx4_o[4] ; Incomplete set of assignments ; +; fxx4_o[5] ; Incomplete set of assignments ; +; fxx4_o[6] ; Incomplete set of assignments ; +; fxx4_o[7] ; Incomplete set of assignments ; +; fxx4_o[8] ; Incomplete set of assignments ; +; fxx4_o[9] ; Incomplete set of assignments ; +; fxx4_o[10] ; Incomplete set of assignments ; +; fxx4_o[11] ; Incomplete set of assignments ; +; fxx4_o[12] ; Incomplete set of assignments ; +; fxx4_o[13] ; Incomplete set of assignments ; +; fxx4_o[14] ; Incomplete set of assignments ; +; fxx4_o[15] ; Incomplete set of assignments ; +; resul_o[0] ; Incomplete set of assignments ; +; resul_o[1] ; Incomplete set of assignments ; +; resul_o[2] ; Incomplete set of assignments ; +; resul_o[3] ; Incomplete set of assignments ; +; resul_o[4] ; Incomplete set of assignments ; +; resul_o[5] ; Incomplete set of assignments ; +; resul_o[6] ; Incomplete set of assignments ; +; resul_o[7] ; Incomplete set of assignments ; +; resul_o[8] ; Incomplete set of assignments ; +; resul_o[9] ; Incomplete set of assignments ; +; resul_o[10] ; Incomplete set of assignments ; +; resul_o[11] ; Incomplete set of assignments ; +; resul_o[12] ; Incomplete set of assignments ; +; resul_o[13] ; Incomplete set of assignments ; +; resul_o[14] ; Incomplete set of assignments ; +; resul_o[15] ; Incomplete set of assignments ; +; extrapolar_i ; Incomplete set of assignments ; +; clk_i ; Incomplete set of assignments ; +; rst_i ; Incomplete set of assignments ; +; distancia_i[5] ; Incomplete set of assignments ; +; distancia_i[3] ; Incomplete set of assignments ; +; distancia_i[4] ; Incomplete set of assignments ; +; distancia_i[2] ; Incomplete set of assignments ; +; distancia_i[0] ; Incomplete set of assignments ; +; distancia_i[1] ; Incomplete set of assignments ; +; distancia_i[6] ; Incomplete set of assignments ; +; distancia_i[7] ; Incomplete set of assignments ; ++----------------+-------------------------------+ + + ++----------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++-------------------------+--------------------+ +; Type ; Value ; ++-------------------------+--------------------+ +; Placement ; ; +; -- Requested ; 0 / 485 ( 0.00 % ) ; +; -- Achieved ; 0 / 485 ( 0.00 % ) ; +; ; ; +; Routing (by Connection) ; ; +; -- Requested ; 0 / 0 ( 0.00 % ) ; +; -- Achieved ; 0 / 0 ( 0.00 % ) ; ++-------------------------+--------------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; ++----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+ + + ++--------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++----------------+---------+-------------------+-------------------------+-------------------+ +; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; ++----------------+---------+-------------------+-------------------------+-------------------+ +; Top ; 485 ; 0 ; N/A ; Source File ; ++----------------+---------+-------------------+-------------------------+-------------------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in C:/Altera/qdesigns/gnextrapolator/gnextrapolator.pin. + + ++-------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++-----------------------------------------------------------------------------------+-------------------------+ +; Resource ; Usage ; ++-----------------------------------------------------------------------------------+-------------------------+ +; Combinational ALUTs ; 169 / 12,480 ( 1 % ) ; +; Dedicated logic registers ; 190 / 12,480 ( 2 % ) ; +; ; ; +; Combinational ALUT usage by number of inputs ; ; +; -- 7 input functions ; 0 ; +; -- 6 input functions ; 4 ; +; -- 5 input functions ; 16 ; +; -- 4 input functions ; 32 ; +; -- <=3 input functions ; 117 ; +; ; ; +; Combinational ALUTs by mode ; ; +; -- normal mode ; 39 ; +; -- extended LUT mode ; 0 ; +; -- arithmetic mode ; 114 ; +; -- shared arithmetic mode ; 16 ; +; ; ; +; Logic utilization ; 232 / 12,480 ( 2 % ) ; +; -- Difficulty Clustering Design ; Low ; +; -- Combinational ALUT/register pairs used in final Placement ; 233 ; +; -- Combinational with no register ; 43 ; +; -- Register only ; 64 ; +; -- Combinational with a register ; 126 ; +; -- Estimated pairs recoverable by pairing ALUTs and registers as design grows ; -1 ; +; -- Estimated Combinational ALUT/register pairs unavailable ; 0 ; +; -- Unavailable due to unpartnered 7 LUTs ; 0 ; +; -- Unavailable due to unpartnered 6 LUTs ; 0 ; +; -- Unavailable due to unpartnered 5 LUTs ; 0 ; +; -- Unavailable due to LAB-wide signal conflicts ; 0 ; +; -- Unavailable due to LAB input limits ; 0 ; +; ; ; +; Total registers* ; 190 / 14,410 ( 1 % ) ; +; -- Dedicated logic registers ; 190 / 12,480 ( 2 % ) ; +; -- I/O registers ; 0 / 1,930 ( 0 % ) ; +; ; ; +; ALMs: partially or completely used ; 117 / 6,240 ( 2 % ) ; +; ; ; +; Total LABs: partially or completely used ; 16 / 780 ( 2 % ) ; +; ; ; +; User inserted logic elements ; 0 ; +; Virtual pins ; 0 ; +; I/O pins ; 107 / 343 ( 31 % ) ; +; -- Clock pins ; 15 / 16 ( 94 % ) ; +; Global signals ; 2 ; +; M512s ; 1 / 104 ( < 1 % ) ; +; M4Ks ; 0 / 78 ( 0 % ) ; +; Total block memory bits ; 512 / 419,328 ( < 1 % ) ; +; Total block memory implementation bits ; 576 / 419,328 ( < 1 % ) ; +; DSP block 9-bit elements ; 0 / 96 ( 0 % ) ; +; PLLs ; 0 / 6 ( 0 % ) ; +; Global clocks ; 2 / 16 ( 13 % ) ; +; Regional clocks ; 0 / 32 ( 0 % ) ; +; SERDES transmitters ; 0 / 38 ( 0 % ) ; +; SERDES receivers ; 0 / 42 ( 0 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Remote update blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 1% / 0% / 1% ; +; Peak interconnect usage (total/H/V) ; 3% / 2% / 3% ; +; Maximum fan-out node ; clk_i~clkctrl ; +; Maximum fan-out ; 191 ; +; Highest non-global fan-out signal ; rst_i ; +; Highest non-global fan-out ; 97 ; +; Total fan-out ; 1304 ; +; Average fan-out ; 2.63 ; ++-----------------------------------------------------------------------------------+-------------------------+ +* Register count does not include registers inside block RAM or DSP blocks. + + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++----------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ; ++----------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; clk_i ; N20 ; 1 ; 0 ; 10 ; 1 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; distancia_i[0] ; R9 ; 7 ; 34 ; 0 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; distancia_i[1] ; P8 ; 6 ; 40 ; 7 ; 2 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; distancia_i[2] ; N3 ; 6 ; 40 ; 10 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; distancia_i[3] ; AA8 ; 7 ; 26 ; 0 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; distancia_i[4] ; E7 ; 4 ; 37 ; 27 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; distancia_i[5] ; B8 ; 4 ; 26 ; 27 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; distancia_i[6] ; M2 ; 5 ; 40 ; 16 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; distancia_i[7] ; K8 ; 5 ; 40 ; 18 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; extrapolar_i ; B9 ; 9 ; 26 ; 27 ; 2 ; 65 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; rst_i ; M21 ; 2 ; 0 ; 16 ; 2 ; 98 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; ++----------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++-------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; ++-------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ +; fxx1_o[0] ; L2 ; 5 ; 40 ; 16 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx1_o[10] ; Y10 ; 7 ; 22 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx1_o[11] ; K4 ; 5 ; 40 ; 18 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx1_o[12] ; K3 ; 5 ; 40 ; 18 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx1_o[13] ; T9 ; 7 ; 34 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx1_o[14] ; P6 ; 6 ; 40 ; 8 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx1_o[15] ; K5 ; 5 ; 40 ; 19 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx1_o[1] ; A7 ; 4 ; 29 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx1_o[2] ; L20 ; 2 ; 0 ; 16 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx1_o[3] ; P5 ; 6 ; 40 ; 8 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx1_o[4] ; C11 ; 4 ; 22 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx1_o[5] ; V2 ; 6 ; 40 ; 3 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx1_o[6] ; P18 ; 1 ; 0 ; 8 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx1_o[7] ; R1 ; 6 ; 40 ; 8 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx1_o[8] ; J3 ; 5 ; 40 ; 19 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx1_o[9] ; W9 ; 10 ; 26 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx2_o[0] ; AB18 ; 8 ; 11 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx2_o[10] ; T6 ; 6 ; 40 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx2_o[11] ; V12 ; 8 ; 17 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx2_o[12] ; AB10 ; 10 ; 25 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx2_o[13] ; AA10 ; 10 ; 25 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx2_o[14] ; C9 ; 9 ; 26 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx2_o[15] ; C10 ; 9 ; 25 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx2_o[1] ; L3 ; 5 ; 40 ; 16 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx2_o[2] ; N8 ; 6 ; 40 ; 9 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx2_o[3] ; W1 ; 6 ; 40 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx2_o[4] ; N7 ; 6 ; 40 ; 9 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx2_o[5] ; N2 ; 6 ; 40 ; 10 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx2_o[6] ; C13 ; 3 ; 18 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx2_o[7] ; L7 ; 5 ; 40 ; 17 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx2_o[8] ; P16 ; 1 ; 0 ; 7 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx2_o[9] ; B12 ; 4 ; 22 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx3_o[0] ; B13 ; 3 ; 18 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx3_o[10] ; AA9 ; 10 ; 25 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx3_o[11] ; R4 ; 6 ; 40 ; 6 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx3_o[12] ; C7 ; 4 ; 29 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx3_o[13] ; Y11 ; 7 ; 22 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx3_o[14] ; J5 ; 5 ; 40 ; 20 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx3_o[15] ; J6 ; 5 ; 40 ; 20 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx3_o[1] ; U20 ; 1 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx3_o[2] ; A10 ; 9 ; 25 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx3_o[3] ; H1 ; 5 ; 40 ; 20 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx3_o[4] ; Y12 ; 8 ; 18 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx3_o[5] ; D12 ; 3 ; 17 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx3_o[6] ; AA11 ; 7 ; 22 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx3_o[7] ; A13 ; 3 ; 18 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx3_o[8] ; R7 ; 6 ; 40 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx3_o[9] ; T3 ; 6 ; 40 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx4_o[0] ; R6 ; 6 ; 40 ; 6 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx4_o[10] ; T18 ; 1 ; 0 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx4_o[11] ; R8 ; 6 ; 40 ; 3 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx4_o[12] ; T4 ; 6 ; 40 ; 4 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx4_o[13] ; U22 ; 1 ; 0 ; 6 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx4_o[14] ; U1 ; 6 ; 40 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx4_o[15] ; R19 ; 1 ; 0 ; 6 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx4_o[1] ; P2 ; 6 ; 40 ; 9 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx4_o[2] ; V9 ; 10 ; 26 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx4_o[3] ; Y9 ; 10 ; 25 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx4_o[4] ; V8 ; 7 ; 33 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx4_o[5] ; W10 ; 7 ; 22 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx4_o[6] ; AB13 ; 8 ; 18 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx4_o[7] ; U2 ; 6 ; 40 ; 5 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx4_o[8] ; U5 ; 6 ; 40 ; 4 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx4_o[9] ; T5 ; 6 ; 40 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx_o[0] ; K7 ; 5 ; 40 ; 18 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx_o[10] ; B10 ; 9 ; 25 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx_o[11] ; B7 ; 4 ; 29 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx_o[12] ; T21 ; 1 ; 0 ; 7 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx_o[13] ; T2 ; 6 ; 40 ; 7 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx_o[14] ; P3 ; 6 ; 40 ; 9 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx_o[15] ; T10 ; 7 ; 30 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx_o[1] ; P17 ; 1 ; 0 ; 7 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx_o[2] ; C12 ; 4 ; 22 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx_o[3] ; D6 ; 4 ; 35 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx_o[4] ; L8 ; 5 ; 40 ; 17 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx_o[5] ; D10 ; 9 ; 25 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx_o[6] ; H11 ; 3 ; 17 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx_o[7] ; P7 ; 6 ; 40 ; 7 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx_o[8] ; A8 ; 4 ; 26 ; 27 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; fxx_o[9] ; T1 ; 6 ; 40 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; resul_o[0] ; AB8 ; 7 ; 26 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; resul_o[10] ; R5 ; 6 ; 40 ; 6 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; resul_o[11] ; B15 ; 3 ; 14 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; resul_o[12] ; AB6 ; 7 ; 30 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; resul_o[13] ; T20 ; 1 ; 0 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; resul_o[14] ; T16 ; 8 ; 2 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; resul_o[15] ; U4 ; 6 ; 40 ; 4 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; resul_o[1] ; AA7 ; 7 ; 29 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; resul_o[2] ; Y7 ; 7 ; 29 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; resul_o[3] ; AB5 ; 7 ; 31 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; resul_o[4] ; T19 ; 1 ; 0 ; 5 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; resul_o[5] ; R2 ; 6 ; 40 ; 8 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; resul_o[6] ; U21 ; 1 ; 0 ; 6 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; resul_o[7] ; T22 ; 1 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; resul_o[8] ; T17 ; 1 ; 0 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 12mA ; Off ; Fitter ; 0 pF ; - ; - ; +; resul_o[9] ; Y8 ; 7 ; 29 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; ++-------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1 ; 14 / 40 ( 35 % ) ; 3.3V ; -- ; +; 2 ; 2 / 44 ( 5 % ) ; 3.3V ; -- ; +; 3 ; 7 / 50 ( 14 % ) ; 3.3V ; -- ; +; 4 ; 10 / 35 ( 29 % ) ; 3.3V ; -- ; +; 5 ; 14 / 44 ( 32 % ) ; 3.3V ; -- ; +; 6 ; 29 / 40 ( 73 % ) ; 3.3V ; -- ; +; 7 ; 15 / 34 ( 44 % ) ; 3.3V ; -- ; +; 8 ; 5 / 43 ( 12 % ) ; 3.3V ; -- ; +; 9 ; 6 / 6 ( 100 % ) ; 3.3V ; -- ; +; 10 ; 6 / 6 ( 100 % ) ; 3.3V ; -- ; ++----------+------------------+---------------+--------------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+--------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+--------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; ; ; TEMPDIODEp ; ; ; ; -- ; ; -- ; -- ; +; A3 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A4 ; 277 ; 4 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ; +; A5 ; 307 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A6 ; 311 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A7 ; 315 ; 4 ; fxx1_o[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; A8 ; 318 ; 4 ; fxx_o[8] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; A9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A10 ; 323 ; 9 ; fxx3_o[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; A11 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A12 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A13 ; 329 ; 3 ; fxx3_o[7] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; A14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A15 ; 343 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A16 ; 347 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A17 ; 351 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A18 ; 350 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A19 ; 375 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A20 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A21 ; 383 ; 3 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA3 ; 191 ; 7 ; ^nCEO ; ; ; ; -- ; ; -- ; -- ; +; AA4 ; 181 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA5 ; 163 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA6 ; 159 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA7 ; 155 ; 7 ; resul_o[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; AA8 ; 151 ; 7 ; distancia_i[3] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; AA9 ; 144 ; 10 ; fxx3_o[10] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; AA10 ; 147 ; 10 ; fxx2_o[13] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; AA11 ; 141 ; 7 ; fxx3_o[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; AA12 ; 138 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA13 ; 137 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA14 ; ; 8 ; VREFB8 ; power ; ; ; -- ; ; -- ; -- ; +; AA15 ; 127 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA16 ; 123 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA17 ; 119 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA18 ; 115 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA19 ; 85 ; 8 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; AA20 ; 86 ; 8 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; AA21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA22 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; 190 ; 7 ; ^nIO_PULLUP ; ; ; ; -- ; ; -- ; -- ; +; AB3 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB5 ; 161 ; 7 ; resul_o[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; AB6 ; 157 ; 7 ; resul_o[12] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; AB7 ; 153 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB8 ; 150 ; 7 ; resul_o[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; AB9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB10 ; 145 ; 10 ; fxx2_o[12] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; AB11 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB12 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB13 ; 139 ; 8 ; fxx4_o[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; AB14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB15 ; 125 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB16 ; 124 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB17 ; 117 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB18 ; 118 ; 8 ; fxx2_o[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; AB19 ; 87 ; 8 ; #TRST ; input ; ; ; -- ; ; -- ; -- ; +; AB20 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB21 ; 84 ; 8 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B3 ; 276 ; 4 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; B4 ; 279 ; 4 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ; +; B5 ; 305 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B6 ; 309 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B7 ; 313 ; 4 ; fxx_o[11] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; B8 ; 317 ; 4 ; distancia_i[5] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; B9 ; 320 ; 9 ; extrapolar_i ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; B10 ; 321 ; 9 ; fxx_o[10] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; B11 ; 327 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B12 ; 328 ; 4 ; fxx2_o[9] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; B13 ; 331 ; 3 ; fxx3_o[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; B14 ; ; 3 ; VREFB3 ; power ; ; ; -- ; ; -- ; -- ; +; B15 ; 341 ; 3 ; resul_o[11] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; B16 ; 345 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B17 ; 349 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B18 ; 353 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B19 ; 377 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B20 ; 381 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; B21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B22 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C1 ; 275 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C2 ; 273 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C3 ; ; ; TEMPDIODEn ; ; ; ; -- ; ; -- ; -- ; +; C4 ; 285 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C5 ; 306 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C6 ; 308 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C7 ; 316 ; 4 ; fxx3_o[12] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; C8 ; 314 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C9 ; 319 ; 9 ; fxx2_o[14] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; C10 ; 324 ; 9 ; fxx2_o[15] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; C11 ; 325 ; 4 ; fxx1_o[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; C12 ; 326 ; 4 ; fxx_o[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; C13 ; 330 ; 3 ; fxx2_o[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; C14 ; 354 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C15 ; 342 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C16 ; 344 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C17 ; 352 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C18 ; 355 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C19 ; 369 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C20 ; 384 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; C21 ; 2 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C22 ; 0 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D1 ; 271 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D2 ; 269 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D3 ; 287 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D4 ; 278 ; 4 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; D5 ; 283 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D6 ; 293 ; 4 ; fxx_o[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; D7 ; ; 4 ; VREFB4 ; power ; ; ; -- ; ; -- ; -- ; +; D8 ; 297 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D9 ; ; 4 ; VREFB4 ; power ; ; ; -- ; ; -- ; -- ; +; D10 ; 322 ; 9 ; fxx_o[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; D11 ; 337 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D12 ; 333 ; 3 ; fxx3_o[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; D13 ; 332 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D14 ; 356 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D15 ; 361 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D16 ; ; 3 ; VREFB3 ; power ; ; ; -- ; ; -- ; -- ; +; D17 ; 373 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D18 ; 379 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D19 ; 382 ; 3 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ; +; D20 ; 371 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D21 ; 6 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D22 ; 4 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E1 ; 267 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E2 ; 265 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E3 ; 274 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E4 ; 272 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E5 ; 280 ; 4 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; E6 ; 281 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E7 ; 289 ; 4 ; distancia_i[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; E8 ; 298 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E9 ; 301 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E10 ; 312 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E11 ; 335 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E12 ; 339 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E13 ; 338 ; 3 ; ~DATA0~ / RESERVED_INPUT ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; E14 ; 357 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E15 ; 365 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E16 ; 374 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E17 ; 376 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E18 ; 380 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E19 ; 3 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E20 ; 1 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E21 ; 10 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E22 ; 8 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F1 ; 263 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F2 ; 261 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F3 ; ; 5 ; VREFB5 ; power ; ; ; -- ; ; -- ; -- ; +; F4 ; 270 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F5 ; 268 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F6 ; 288 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F7 ; 296 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F8 ; 294 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F9 ; 300 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F10 ; ; ; GNDA_PLL5 ; gnd ; ; ; -- ; ; -- ; -- ; +; F11 ; ; ; GNDA_PLL5 ; gnd ; ; ; -- ; ; -- ; -- ; +; F12 ; ; ; VCCA_PLL5 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; F13 ; 346 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F14 ; 358 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F15 ; 367 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F16 ; 362 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F17 ; 378 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F18 ; ; 2 ; VREFB2 ; power ; ; ; -- ; ; -- ; -- ; +; F19 ; 11 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F20 ; 9 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F21 ; 14 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F22 ; 12 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G1 ; 255 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G2 ; 253 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G3 ; 262 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G4 ; 260 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G5 ; 266 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G6 ; 264 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G7 ; 286 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G8 ; 291 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G9 ; 302 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G10 ; ; 9 ; VCC_PLL5_OUT ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; G11 ; ; ; VCCD_PLL5 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; G12 ; 336 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G13 ; 348 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G14 ; 359 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G15 ; 366 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G16 ; 370 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G17 ; 7 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G18 ; 5 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G19 ; 19 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G20 ; 17 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G21 ; 22 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G22 ; 20 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H1 ; 251 ; 5 ; fxx3_o[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; H2 ; 249 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H3 ; 259 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H4 ; 257 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H5 ; 254 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H6 ; 252 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H7 ; 284 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; H9 ; 304 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H10 ; ; 4 ; VCCPD4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; H11 ; 334 ; 3 ; fxx_o[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; H12 ; 340 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H13 ; ; 3 ; VCCPD3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; H14 ; 360 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H16 ; 368 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H17 ; 15 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H18 ; 13 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H19 ; 18 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H20 ; 16 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H21 ; 26 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H22 ; 24 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J2 ; 247 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J3 ; 245 ; 5 ; fxx1_o[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; J4 ; ; 5 ; VREFB5 ; power ; ; ; -- ; ; -- ; -- ; +; J5 ; 250 ; 5 ; fxx3_o[14] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; J6 ; 248 ; 5 ; fxx3_o[15] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; J7 ; 258 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J8 ; 256 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; J15 ; 364 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; J16 ; 23 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J17 ; 21 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J18 ; 27 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J19 ; 25 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J20 ; 30 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J21 ; 28 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K1 ; 239 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; K2 ; 237 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; K3 ; 243 ; 5 ; fxx1_o[12] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; K4 ; 241 ; 5 ; fxx1_o[11] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; K5 ; 246 ; 5 ; fxx1_o[15] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; K6 ; 244 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; K7 ; 242 ; 5 ; fxx_o[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; K8 ; 240 ; 5 ; distancia_i[7] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; K9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K14 ; ; 2 ; VCCPD2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; K15 ; 35 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; K16 ; 33 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; K17 ; 31 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; K18 ; 29 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; K19 ; 34 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; K20 ; 32 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; K21 ; 38 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; K22 ; 36 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L1 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; L2 ; 233 ; 5 ; fxx1_o[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; L3 ; 235 ; 5 ; fxx2_o[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; L4 ; ; ; GNDA_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; +; L5 ; ; ; GNDA_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; +; L6 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L7 ; 238 ; 5 ; fxx2_o[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; L8 ; 236 ; 5 ; fxx_o[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; L9 ; ; 5 ; VCCPD5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L15 ; 39 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L16 ; 37 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L17 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; L18 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; L19 ; ; 2 ; VREFB2 ; power ; ; ; -- ; ; -- ; -- ; +; L20 ; 40 ; 2 ; fxx1_o[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; L21 ; 42 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L22 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; M1 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; M2 ; 232 ; 5 ; distancia_i[6] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; M3 ; 234 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; M4 ; ; ; VCCA_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M5 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M6 ; ; ; VCCA_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M16 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M17 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M18 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M19 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M20 ; 41 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; M21 ; 43 ; 2 ; rst_i ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; M22 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; N1 ; 231 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N2 ; 229 ; 6 ; fxx2_o[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; N3 ; 230 ; 6 ; distancia_i[2] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; N4 ; 228 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; N5 ; ; ; GNDA_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; +; N6 ; ; ; GNDA_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; +; N7 ; 226 ; 6 ; fxx2_o[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; N8 ; 224 ; 6 ; fxx2_o[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; N9 ; ; 6 ; VCCPD6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N15 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N16 ; 49 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N17 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; N18 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; N19 ; 47 ; 1 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; N20 ; 45 ; 1 ; clk_i ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; N21 ; 46 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N22 ; 44 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P2 ; 227 ; 6 ; fxx4_o[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; P3 ; 225 ; 6 ; fxx_o[14] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; P4 ; ; 6 ; VREFB6 ; power ; ; ; -- ; ; -- ; -- ; +; P5 ; 222 ; 6 ; fxx1_o[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; P6 ; 220 ; 6 ; fxx1_o[14] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; P7 ; 218 ; 6 ; fxx_o[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; P8 ; 216 ; 6 ; distancia_i[1] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; P9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P10 ; ; 7 ; VCCPD7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; P11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; P14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P15 ; ; 1 ; VCCPD1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; P16 ; 59 ; 1 ; fxx2_o[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; P17 ; 57 ; 1 ; fxx_o[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; P18 ; 55 ; 1 ; fxx1_o[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; P19 ; 53 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P20 ; 50 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P21 ; 48 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R1 ; 223 ; 6 ; fxx1_o[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; R2 ; 221 ; 6 ; resul_o[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; R3 ; 215 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R4 ; 213 ; 6 ; fxx3_o[11] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; R5 ; 214 ; 6 ; resul_o[10] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; R6 ; 212 ; 6 ; fxx4_o[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; R7 ; 202 ; 6 ; fxx3_o[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; R8 ; 200 ; 6 ; fxx4_o[11] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; R9 ; 168 ; 7 ; distancia_i[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; R10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R11 ; ; 10 ; VCC_PLL6_OUT ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; R12 ; ; ; VCCA_PLL6 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; R13 ; ; 8 ; VCCPD8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; R14 ; 106 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R15 ; 89 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R16 ; 83 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R17 ; 81 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R18 ; 63 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R19 ; 61 ; 1 ; fxx4_o[15] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; R20 ; ; 1 ; VREFB1 ; power ; ; ; -- ; ; -- ; -- ; +; R21 ; 54 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R22 ; 52 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T1 ; 219 ; 6 ; fxx_o[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; T2 ; 217 ; 6 ; fxx_o[13] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; T3 ; 207 ; 6 ; fxx3_o[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; T4 ; 205 ; 6 ; fxx4_o[12] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; T5 ; 210 ; 6 ; fxx4_o[9] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; T6 ; 208 ; 6 ; fxx2_o[10] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; T7 ; 186 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T8 ; 172 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T9 ; 170 ; 7 ; fxx1_o[13] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; T10 ; 156 ; 7 ; fxx_o[15] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; T11 ; ; ; GNDA_PLL6 ; gnd ; ; ; -- ; ; -- ; -- ; +; T12 ; ; ; GNDA_PLL6 ; gnd ; ; ; -- ; ; -- ; -- ; +; T13 ; 120 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T14 ; 108 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T15 ; 98 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T16 ; 92 ; 8 ; resul_o[14] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; T17 ; 67 ; 1 ; resul_o[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; T18 ; 65 ; 1 ; fxx4_o[10] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; T19 ; 66 ; 1 ; resul_o[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; T20 ; 64 ; 1 ; resul_o[13] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; T21 ; 58 ; 1 ; fxx_o[12] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; T22 ; 56 ; 1 ; resul_o[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; U1 ; 211 ; 6 ; fxx4_o[14] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; U2 ; 209 ; 6 ; fxx4_o[7] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; U3 ; ; 6 ; VREFB6 ; power ; ; ; -- ; ; -- ; -- ; +; U4 ; 206 ; 6 ; resul_o[15] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; U5 ; 204 ; 6 ; fxx4_o[8] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; U6 ; 179 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U7 ; 180 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U8 ; 173 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U9 ; 171 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U10 ; 158 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U11 ; ; ; VCCD_PLL6 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U12 ; 130 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U13 ; 112 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U14 ; 103 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U15 ; 99 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U16 ; 94 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U17 ; 71 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U18 ; 69 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U19 ; 70 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U20 ; 68 ; 1 ; fxx3_o[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; U21 ; 62 ; 1 ; resul_o[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; U22 ; 60 ; 1 ; fxx4_o[13] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; V1 ; 203 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V2 ; 201 ; 6 ; fxx1_o[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; V3 ; 198 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V4 ; 196 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V5 ; 188 ; 7 ; ^PORSEL ; ; ; ; -- ; ; -- ; -- ; +; V6 ; 185 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V7 ; 175 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V8 ; 166 ; 7 ; fxx4_o[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; V9 ; 149 ; 10 ; fxx4_o[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; V10 ; 165 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V11 ; 132 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V12 ; 134 ; 8 ; fxx2_o[11] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; V13 ; 114 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V14 ; 105 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V15 ; 97 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V16 ; 93 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V17 ; 90 ; 8 ; ^VCCSEL ; ; ; ; -- ; ; -- ; -- ; +; V18 ; 75 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V19 ; 73 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V20 ; ; 1 ; VREFB1 ; power ; ; ; -- ; ; -- ; -- ; +; V21 ; 74 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V22 ; 72 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W1 ; 199 ; 6 ; fxx2_o[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; W2 ; 197 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W3 ; 194 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W4 ; 192 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W5 ; 182 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W6 ; ; 7 ; VREFB7 ; power ; ; ; -- ; ; -- ; -- ; +; W7 ; 177 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W8 ; ; 7 ; VREFB7 ; power ; ; ; -- ; ; -- ; -- ; +; W9 ; 148 ; 10 ; fxx1_o[9] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; W10 ; 142 ; 7 ; fxx4_o[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; W11 ; 133 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W12 ; 135 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W13 ; 128 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W14 ; 109 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W15 ; 102 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W16 ; 101 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W17 ; 95 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W18 ; 88 ; 8 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; W19 ; 79 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W20 ; 77 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W21 ; 78 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W22 ; 76 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y1 ; 195 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y2 ; 193 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y3 ; 184 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y4 ; 189 ; 7 ; PLL_ENA ; ; ; ; -- ; ; -- ; -- ; +; Y5 ; 162 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y6 ; 160 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y7 ; 154 ; 7 ; resul_o[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; Y8 ; 152 ; 7 ; resul_o[9] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; Y9 ; 146 ; 10 ; fxx4_o[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; Y10 ; 140 ; 7 ; fxx1_o[10] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; Y11 ; 143 ; 7 ; fxx3_o[13] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; Y12 ; 136 ; 8 ; fxx3_o[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; Y13 ; 131 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y14 ; 110 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y15 ; 126 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y16 ; 121 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y17 ; 116 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y18 ; 113 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y19 ; ; 8 ; VREFB8 ; power ; ; ; -- ; ; -- ; -- ; +; Y20 ; 91 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y21 ; 82 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y22 ; 80 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ++----------+------------+----------+--------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-------------------------------------------------------------------------------+ +; Output Pin Default Load For Reported TCO ; ++----------------------------------+-------+------------------------------------+ +; I/O Standard ; Load ; Termination Resistance ; ++----------------------------------+-------+------------------------------------+ +; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ; +; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ; +; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ; +; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ; +; LVDS ; 0 pF ; 100 Ohm (Differential) ; +; HyperTransport ; 0 pF ; 100 Ohm (Differential) ; +; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ; +; 3.3-V LVTTL ; 0 pF ; Not Available ; +; 3.3-V LVCMOS ; 0 pF ; Not Available ; +; 2.5 V ; 0 pF ; Not Available ; +; 1.8 V ; 0 pF ; Not Available ; +; 1.5 V ; 0 pF ; Not Available ; +; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; 1.2-V HSTL ; 0 pF ; Not Available ; +; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ; +; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ; +; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ; +; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ; +; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ; +; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ; +; Differential 1.2-V HSTL ; 0 pF ; Not Available ; ++----------------------------------+-------+------------------------------------+ +Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------------------+---------------------+-----------+---------------------------+---------------+-------------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------------------------+--------------------+-------------------------------+---------------------------------------------------------------------+--------------+ +; Compilation Hierarchy Node ; Combinational ALUTs ; ALMs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Combinational with no register ; Register-Only ; Combinational with a register ; Full Hierarchy Name ; Library Name ; +; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ALUT/register pair ; ALUT/register pair ; ALUT/register pair ; ; ; ++----------------------------------------+---------------------+-----------+---------------------------+---------------+-------------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------------------------+--------------------+-------------------------------+---------------------------------------------------------------------+--------------+ +; |gnextrapolator ; 169 (169) ; 117 (117) ; 190 (190) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 107 ; 0 ; 43 (43) ; 64 (64) ; 126 (126) ; |gnextrapolator ; work ; +; |altsyncram:ram_rtl_0| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |gnextrapolator|altsyncram:ram_rtl_0 ; ; +; |altsyncram_uv61:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 512 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |gnextrapolator|altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated ; ; ++----------------------------------------+---------------------+-----------+---------------------------+---------------+-------------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------------------------+--------------------+-------------------------------+---------------------------------------------------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++---------------------------------------------------------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++----------------+----------+---------------+---------------+-----------------------+-----+-----------+---------+----------+------------+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ; DQS bus ; NDQS bus ; DQS output ; ++----------------+----------+---------------+---------------+-----------------------+-----+-----------+---------+----------+------------+ +; fxx_o[0] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx_o[1] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx_o[2] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx_o[3] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx_o[4] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx_o[5] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx_o[6] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx_o[7] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx_o[8] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx_o[9] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx_o[10] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx_o[11] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx_o[12] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx_o[13] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx_o[14] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx_o[15] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx1_o[0] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx1_o[1] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx1_o[2] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx1_o[3] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx1_o[4] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx1_o[5] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx1_o[6] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx1_o[7] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx1_o[8] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx1_o[9] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx1_o[10] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx1_o[11] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx1_o[12] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx1_o[13] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx1_o[14] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx1_o[15] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx2_o[0] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx2_o[1] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx2_o[2] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx2_o[3] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx2_o[4] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx2_o[5] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx2_o[6] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx2_o[7] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx2_o[8] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx2_o[9] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx2_o[10] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx2_o[11] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx2_o[12] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx2_o[13] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx2_o[14] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx2_o[15] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx3_o[0] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx3_o[1] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx3_o[2] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx3_o[3] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx3_o[4] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx3_o[5] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx3_o[6] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx3_o[7] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx3_o[8] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx3_o[9] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx3_o[10] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx3_o[11] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx3_o[12] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx3_o[13] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx3_o[14] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx3_o[15] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx4_o[0] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx4_o[1] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx4_o[2] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx4_o[3] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx4_o[4] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx4_o[5] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx4_o[6] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx4_o[7] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx4_o[8] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx4_o[9] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx4_o[10] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx4_o[11] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx4_o[12] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx4_o[13] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx4_o[14] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; fxx4_o[15] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; resul_o[0] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; resul_o[1] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; resul_o[2] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; resul_o[3] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; resul_o[4] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; resul_o[5] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; resul_o[6] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; resul_o[7] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; resul_o[8] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; resul_o[9] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; resul_o[10] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; resul_o[11] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; resul_o[12] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; resul_o[13] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; resul_o[14] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; resul_o[15] ; Output ; -- ; -- ; -- ; -- ; (0) 59 ps ; -- ; -- ; -- ; +; extrapolar_i ; Input ; (7) 3445 ps ; (7) 3445 ps ; -- ; -- ; -- ; -- ; -- ; -- ; +; clk_i ; Input ; (0) 236 ps ; (0) 236 ps ; -- ; -- ; -- ; -- ; -- ; -- ; +; rst_i ; Input ; (7) 3544 ps ; (7) 3544 ps ; -- ; -- ; -- ; -- ; -- ; -- ; +; distancia_i[5] ; Input ; (7) 3445 ps ; (7) 3445 ps ; -- ; -- ; -- ; -- ; -- ; -- ; +; distancia_i[3] ; Input ; (7) 3445 ps ; (7) 3445 ps ; -- ; -- ; -- ; -- ; -- ; -- ; +; distancia_i[4] ; Input ; (7) 3445 ps ; (7) 3445 ps ; -- ; -- ; -- ; -- ; -- ; -- ; +; distancia_i[2] ; Input ; (7) 3544 ps ; (7) 3544 ps ; -- ; -- ; -- ; -- ; -- ; -- ; +; distancia_i[0] ; Input ; (7) 3445 ps ; (7) 3445 ps ; -- ; -- ; -- ; -- ; -- ; -- ; +; distancia_i[1] ; Input ; (7) 3544 ps ; (7) 3544 ps ; -- ; -- ; -- ; -- ; -- ; -- ; +; distancia_i[6] ; Input ; (7) 3544 ps ; (7) 3544 ps ; -- ; -- ; -- ; -- ; -- ; -- ; +; distancia_i[7] ; Input ; (7) 3544 ps ; (7) 3544 ps ; -- ; -- ; -- ; -- ; -- ; -- ; ++----------------+----------+---------------+---------------+-----------------------+-----+-----------+---------+----------+------------+ + + ++------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++------------------------+-------------------+---------+ +; extrapolar_i ; ; ; +; - Add2~9 ; 0 ; 7 ; +; - Add2~13 ; 0 ; 7 ; +; - Add2~17 ; 0 ; 7 ; +; - Add2~21 ; 0 ; 7 ; +; - Add2~25 ; 0 ; 7 ; +; - Add2~29 ; 0 ; 7 ; +; - Add2~33 ; 0 ; 7 ; +; - Add2~37 ; 0 ; 7 ; +; - Add2~41 ; 0 ; 7 ; +; - Add2~45 ; 0 ; 7 ; +; - Add2~49 ; 0 ; 7 ; +; - Add2~53 ; 0 ; 7 ; +; - Add2~57 ; 0 ; 7 ; +; - Add2~61 ; 0 ; 7 ; +; - Add2~65 ; 0 ; 7 ; +; - Add2~69 ; 0 ; 7 ; +; - Add6~1 ; 0 ; 7 ; +; - Add6~5 ; 0 ; 7 ; +; - Add6~9 ; 0 ; 7 ; +; - Add6~13 ; 0 ; 7 ; +; - Add6~17 ; 0 ; 7 ; +; - Add6~21 ; 0 ; 7 ; +; - Add6~25 ; 0 ; 7 ; +; - Add6~29 ; 0 ; 7 ; +; - Add6~33 ; 0 ; 7 ; +; - Add6~37 ; 0 ; 7 ; +; - Add6~41 ; 0 ; 7 ; +; - Add6~45 ; 0 ; 7 ; +; - Add6~49 ; 0 ; 7 ; +; - Add6~53 ; 0 ; 7 ; +; - Add6~57 ; 0 ; 7 ; +; - Add6~61 ; 0 ; 7 ; +; - Add0~1 ; 0 ; 7 ; +; - fx~0 ; 0 ; 7 ; +; - fx~1 ; 0 ; 7 ; +; - fx~2 ; 0 ; 7 ; +; - fx~3 ; 0 ; 7 ; +; - fx~4 ; 0 ; 7 ; +; - fx~5 ; 0 ; 7 ; +; - fx~6 ; 0 ; 7 ; +; - fx~7 ; 0 ; 7 ; +; - fx~8 ; 0 ; 7 ; +; - fx~9 ; 0 ; 7 ; +; - fx~10 ; 0 ; 7 ; +; - fx~11 ; 0 ; 7 ; +; - fx~12 ; 0 ; 7 ; +; - fx~13 ; 0 ; 7 ; +; - fx~14 ; 0 ; 7 ; +; - fx~15 ; 0 ; 7 ; +; - fx~16 ; 0 ; 7 ; +; - fx~17 ; 0 ; 7 ; +; - fx~18 ; 0 ; 7 ; +; - fx~19 ; 0 ; 7 ; +; - fx~20 ; 0 ; 7 ; +; - fx~21 ; 0 ; 7 ; +; - fx~22 ; 0 ; 7 ; +; - fx~23 ; 0 ; 7 ; +; - fx~24 ; 0 ; 7 ; +; - fx~25 ; 0 ; 7 ; +; - fx~26 ; 0 ; 7 ; +; - fx~27 ; 0 ; 7 ; +; - fx~28 ; 0 ; 7 ; +; - fx~29 ; 0 ; 7 ; +; - fx~30 ; 0 ; 7 ; +; - fx~31 ; 0 ; 7 ; +; clk_i ; ; ; +; rst_i ; ; ; +; - resultado[0] ; 1 ; 7 ; +; - fxx_o[15]~reg0 ; 1 ; 7 ; +; - fxx_o[14]~reg0 ; 1 ; 7 ; +; - fxx_o[13]~reg0 ; 1 ; 7 ; +; - fxx_o[12]~reg0 ; 1 ; 7 ; +; - fxx_o[11]~reg0 ; 1 ; 7 ; +; - fxx_o[10]~reg0 ; 1 ; 7 ; +; - fxx_o[9]~reg0 ; 1 ; 7 ; +; - fxx_o[8]~reg0 ; 1 ; 7 ; +; - fxx_o[7]~reg0 ; 1 ; 7 ; +; - fxx_o[6]~reg0 ; 1 ; 7 ; +; - fxx_o[5]~reg0 ; 1 ; 7 ; +; - fxx_o[4]~reg0 ; 1 ; 7 ; +; - fxx_o[3]~reg0 ; 1 ; 7 ; +; - fxx_o[2]~reg0 ; 1 ; 7 ; +; - fxx_o[1]~reg0 ; 1 ; 7 ; +; - fxx_o[0]~reg0 ; 1 ; 7 ; +; - fxx1_o[14]~reg0 ; 1 ; 7 ; +; - fxx1_o[11]~reg0 ; 1 ; 7 ; +; - fxx1_o[9]~reg0 ; 1 ; 7 ; +; - fxx1_o[7]~reg0 ; 1 ; 7 ; +; - fxx1_o[6]~reg0 ; 1 ; 7 ; +; - fxx1_o[5]~reg0 ; 1 ; 7 ; +; - fxx1_o[4]~reg0 ; 1 ; 7 ; +; - fxx1_o[3]~reg0 ; 1 ; 7 ; +; - fxx1_o[2]~reg0 ; 1 ; 7 ; +; - fxx1_o[1]~reg0 ; 1 ; 7 ; +; - fxx1_o[0]~reg0 ; 1 ; 7 ; +; - fxx2_o[15]~reg0 ; 1 ; 7 ; +; - fxx2_o[14]~reg0 ; 1 ; 7 ; +; - fxx2_o[13]~reg0 ; 1 ; 7 ; +; - fxx2_o[12]~reg0 ; 1 ; 7 ; +; - fxx2_o[11]~reg0 ; 1 ; 7 ; +; - fxx2_o[10]~reg0 ; 1 ; 7 ; +; - fxx2_o[9]~reg0 ; 1 ; 7 ; +; - fxx2_o[8]~reg0 ; 1 ; 7 ; +; - fxx2_o[7]~reg0 ; 1 ; 7 ; +; - fxx2_o[6]~reg0 ; 1 ; 7 ; +; - fxx2_o[5]~reg0 ; 1 ; 7 ; +; - fxx2_o[4]~reg0 ; 1 ; 7 ; +; - fxx2_o[3]~reg0 ; 1 ; 7 ; +; - fxx2_o[2]~reg0 ; 1 ; 7 ; +; - fxx2_o[1]~reg0 ; 1 ; 7 ; +; - fxx2_o[0]~reg0 ; 1 ; 7 ; +; - fxx3_o[15]~reg0 ; 1 ; 7 ; +; - fxx3_o[14]~reg0 ; 1 ; 7 ; +; - fxx3_o[13]~reg0 ; 1 ; 7 ; +; - fxx3_o[12]~reg0 ; 1 ; 7 ; +; - fxx3_o[11]~reg0 ; 1 ; 7 ; +; - fxx3_o[10]~reg0 ; 1 ; 7 ; +; - fxx3_o[9]~reg0 ; 1 ; 7 ; +; - fxx3_o[8]~reg0 ; 1 ; 7 ; +; - fxx3_o[7]~reg0 ; 1 ; 7 ; +; - fxx3_o[6]~reg0 ; 1 ; 7 ; +; - fxx3_o[5]~reg0 ; 1 ; 7 ; +; - fxx3_o[4]~reg0 ; 1 ; 7 ; +; - fxx3_o[3]~reg0 ; 1 ; 7 ; +; - fxx3_o[2]~reg0 ; 1 ; 7 ; +; - fxx3_o[1]~reg0 ; 1 ; 7 ; +; - fxx3_o[0]~reg0 ; 1 ; 7 ; +; - fxx4_o[15]~reg0 ; 1 ; 7 ; +; - fxx4_o[14]~reg0 ; 1 ; 7 ; +; - fxx4_o[13]~reg0 ; 1 ; 7 ; +; - fxx4_o[12]~reg0 ; 1 ; 7 ; +; - fxx4_o[11]~reg0 ; 1 ; 7 ; +; - fxx4_o[10]~reg0 ; 1 ; 7 ; +; - fxx4_o[9]~reg0 ; 1 ; 7 ; +; - fxx4_o[8]~reg0 ; 1 ; 7 ; +; - fxx4_o[7]~reg0 ; 1 ; 7 ; +; - fxx4_o[6]~reg0 ; 1 ; 7 ; +; - fxx4_o[5]~reg0 ; 1 ; 7 ; +; - fxx4_o[4]~reg0 ; 1 ; 7 ; +; - fxx4_o[3]~reg0 ; 1 ; 7 ; +; - fxx4_o[2]~reg0 ; 1 ; 7 ; +; - fxx4_o[1]~reg0 ; 1 ; 7 ; +; - fxx4_o[0]~reg0 ; 1 ; 7 ; +; - resultado[1] ; 1 ; 7 ; +; - resultado[2] ; 1 ; 7 ; +; - resultado[3] ; 1 ; 7 ; +; - resultado[4] ; 1 ; 7 ; +; - resultado[5] ; 1 ; 7 ; +; - resultado[6] ; 1 ; 7 ; +; - resultado[7] ; 1 ; 7 ; +; - resultado[8] ; 1 ; 7 ; +; - resultado[9] ; 1 ; 7 ; +; - resultado[10] ; 1 ; 7 ; +; - resultado[11] ; 1 ; 7 ; +; - resultado[12] ; 1 ; 7 ; +; - resultado[13] ; 1 ; 7 ; +; - resultado[14] ; 1 ; 7 ; +; - resul_o[15]~0 ; 1 ; 7 ; +; distancia_i[5] ; ; ; +; - Equal0~0 ; 0 ; 7 ; +; distancia_i[3] ; ; ; +; - Equal0~0 ; 0 ; 7 ; +; distancia_i[4] ; ; ; +; - Equal0~0 ; 0 ; 7 ; +; distancia_i[2] ; ; ; +; - Equal0~1 ; 1 ; 7 ; +; distancia_i[0] ; ; ; +; - Equal0~1 ; 1 ; 7 ; +; distancia_i[1] ; ; ; +; - Equal0~1 ; 0 ; 7 ; +; distancia_i[6] ; ; ; +; - Equal0~2 ; 0 ; 7 ; +; - Equal0~3 ; 0 ; 7 ; +; distancia_i[7] ; ; ; +; - resul_o[15]~0 ; 0 ; 7 ; +; - Equal0~3 ; 0 ; 7 ; ++------------------------+-------------------+---------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++---------------+-------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++---------------+-------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; Equal0~3 ; LCCOMB_X27_Y5_N10 ; 8 ; Sync. clear ; no ; -- ; -- ; -- ; +; clk_i ; PIN_N20 ; 191 ; Clock ; yes ; Global Clock ; GCLK3 ; -- ; +; resul_o[15]~0 ; LCCOMB_X27_Y5_N14 ; 16 ; Clock enable ; no ; -- ; -- ; -- ; +; rst_i ; PIN_M21 ; 98 ; Clock enable ; no ; -- ; -- ; -- ; +; rst_i ; PIN_M21 ; 78 ; Async. clear ; yes ; Global Clock ; GCLK1 ; -- ; ++---------------+-------------------+---------+--------------+--------+----------------------+------------------+---------------------------+ + + ++--------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++-------+----------+---------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++-------+----------+---------+----------------------+------------------+---------------------------+ +; clk_i ; PIN_N20 ; 191 ; Global Clock ; GCLK3 ; -- ; +; rst_i ; PIN_M21 ; 78 ; Global Clock ; GCLK1 ; -- ; ++-------+----------+---------+----------------------+------------------+---------------------------+ + + ++---------------------------------+ +; Non-Global High Fan-Out Signals ; ++---------------+-----------------+ +; Name ; Fan-Out ; ++---------------+-----------------+ +; rst_i ; 97 ; +; extrapolar_i ; 65 ; +; resul_o[15]~0 ; 16 ; +; i[0] ; 16 ; +; Equal0~3 ; 8 ; +; resultado[15] ; 4 ; +; resultado[14] ; 4 ; +; resultado[13] ; 4 ; +; resultado[12] ; 4 ; +; resultado[11] ; 4 ; +; resultado[10] ; 4 ; +; resultado[9] ; 4 ; +; resultado[8] ; 4 ; +; resultado[7] ; 4 ; +; resultado[6] ; 4 ; +; resultado[5] ; 4 ; +; resultado[4] ; 4 ; +; resultado[3] ; 4 ; +; resultado[2] ; 4 ; +; resultado[1] ; 4 ; +; resultado[0] ; 4 ; +; Add4~69 ; 4 ; +; Add4~65 ; 4 ; +; Add4~61 ; 4 ; +; Add4~57 ; 4 ; +; Add4~53 ; 4 ; +; Add4~49 ; 4 ; +; Add4~45 ; 4 ; +; Add4~41 ; 4 ; +; Add4~37 ; 4 ; +; Add4~33 ; 4 ; +; Add4~29 ; 4 ; +; Add4~25 ; 4 ; +; Add4~21 ; 4 ; +; Add4~17 ; 4 ; +; Add4~13 ; 4 ; +; Add4~9 ; 4 ; +; Add3~65 ; 4 ; +; Add3~61 ; 4 ; +; Add3~57 ; 4 ; +; Add3~53 ; 4 ; +; Add3~49 ; 4 ; +; Add3~45 ; 4 ; +; Add3~41 ; 4 ; +; Add3~37 ; 4 ; +; Add3~33 ; 4 ; +; Add3~29 ; 4 ; +; Add3~25 ; 4 ; +; Add3~21 ; 4 ; +; Add3~17 ; 4 ; ++---------------+-----------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter RAM Summary ; ++----------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------+------+--------+--------------------+-------------+ +; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M512s ; M4Ks ; M-RAMs ; MIF ; Location ; ++----------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------+------+--------+--------------------+-------------+ +; altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ALTSYNCRAM ; M512 ; ROM ; Single Clock ; 32 ; 16 ; -- ; -- ; yes ; no ; -- ; -- ; 512 ; 32 ; 16 ; -- ; -- ; 512 ; 1 ; 0 ; 0 ; gnextrapolator.mif ; M512_X24_Y8 ; ++----------------------------------------------------------------+------+------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------+------+--------+--------------------+-------------+ +Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section. + + ++--------------------------------------------------------------------+ +; Interconnect Usage Summary ; ++-------------------------------------------+------------------------+ +; Interconnect Resource Type ; Usage ; ++-------------------------------------------+------------------------+ +; Block interconnects ; 453 / 51,960 ( < 1 % ) ; +; C16 interconnects ; 18 / 1,680 ( 1 % ) ; +; C4 interconnects ; 379 / 38,400 ( < 1 % ) ; +; DPA clocks ; 0 / 4 ( 0 % ) ; +; DQS bus muxes ; 0 / 18 ( 0 % ) ; +; DQS-18 I/O buses ; 0 / 4 ( 0 % ) ; +; DQS-4 I/O buses ; 0 / 18 ( 0 % ) ; +; DQS-9 I/O buses ; 0 / 8 ( 0 % ) ; +; Differential I/O clocks ; 0 / 32 ( 0 % ) ; +; Direct links ; 54 / 51,960 ( < 1 % ) ; +; Global clocks ; 2 / 16 ( 13 % ) ; +; Local interconnects ; 58 / 12,480 ( < 1 % ) ; +; NDQS bus muxes ; 0 / 18 ( 0 % ) ; +; NDQS-18 I/O buses ; 0 / 4 ( 0 % ) ; +; NDQS-4 I/O buses ; 0 / 18 ( 0 % ) ; +; NDQS-9 I/O buses ; 0 / 8 ( 0 % ) ; +; PLL transmitter or receiver load enables ; 0 / 8 ( 0 % ) ; +; PLL transmitter or receiver synch. clocks ; 0 / 8 ( 0 % ) ; +; R24 interconnects ; 16 / 1,664 ( < 1 % ) ; +; R24/C16 interconnect drivers ; 23 / 4,160 ( < 1 % ) ; +; R4 interconnects ; 524 / 59,488 ( < 1 % ) ; +; Regional clocks ; 0 / 32 ( 0 % ) ; ++-------------------------------------------+------------------------+ + + ++-----------------------------------------------------------------+ +; LAB Logic Elements ; ++----------------------------------+------------------------------+ +; Number of ALMs (Average = 7.31) ; Number of LABs (Total = 16) ; ++----------------------------------+------------------------------+ +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 1 ; +; 4 ; 1 ; +; 5 ; 0 ; +; 6 ; 1 ; +; 7 ; 0 ; +; 8 ; 13 ; ++----------------------------------+------------------------------+ + + ++-------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+------------------------------+ +; LAB-wide Signals (Average = 2.63) ; Number of LABs (Total = 16) ; ++------------------------------------+------------------------------+ +; 1 Async. clear ; 11 ; +; 1 Clock ; 16 ; +; 1 Clock enable ; 13 ; +; 1 Sync. clear ; 1 ; +; 2 Clock enables ; 1 ; ++------------------------------------+------------------------------+ + + ++-----------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++----------------------------------------------+------------------------------+ +; Number of Signals Sourced (Average = 15.94) ; Number of LABs (Total = 16) ; ++----------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 1 ; +; 7 ; 1 ; +; 8 ; 1 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 1 ; +; 12 ; 0 ; +; 13 ; 1 ; +; 14 ; 0 ; +; 15 ; 1 ; +; 16 ; 1 ; +; 17 ; 1 ; +; 18 ; 0 ; +; 19 ; 3 ; +; 20 ; 2 ; +; 21 ; 2 ; +; 22 ; 0 ; +; 23 ; 1 ; ++----------------------------------------------+------------------------------+ + + ++---------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++--------------------------------------------------+------------------------------+ +; Number of Signals Sourced Out (Average = 10.75) ; Number of LABs (Total = 16) ; ++--------------------------------------------------+------------------------------+ +; 0 ; 1 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 1 ; +; 5 ; 1 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 2 ; +; 9 ; 1 ; +; 10 ; 2 ; +; 11 ; 0 ; +; 12 ; 1 ; +; 13 ; 2 ; +; 14 ; 2 ; +; 15 ; 0 ; +; 16 ; 1 ; +; 17 ; 1 ; +; 18 ; 0 ; +; 19 ; 1 ; ++--------------------------------------------------+------------------------------+ + + ++-----------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++----------------------------------------------+------------------------------+ +; Number of Distinct Inputs (Average = 23.31) ; Number of LABs (Total = 16) ; ++----------------------------------------------+------------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 1 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 1 ; +; 16 ; 1 ; +; 17 ; 0 ; +; 18 ; 2 ; +; 19 ; 0 ; +; 20 ; 0 ; +; 21 ; 0 ; +; 22 ; 0 ; +; 23 ; 0 ; +; 24 ; 0 ; +; 25 ; 0 ; +; 26 ; 1 ; +; 27 ; 0 ; +; 28 ; 2 ; +; 29 ; 1 ; +; 30 ; 3 ; +; 31 ; 1 ; +; 32 ; 0 ; +; 33 ; 1 ; +; 34 ; 0 ; +; 35 ; 1 ; ++----------------------------------------------+------------------------------+ + + ++------------------------------------------+ +; I/O Rules Summary ; ++----------------------------------+-------+ +; I/O Rules Statistic ; Total ; ++----------------------------------+-------+ +; Total I/O Rules ; 31 ; +; Number of I/O Rules Passed ; 4 ; +; Number of I/O Rules Failed ; 0 ; +; Number of I/O Rules Unchecked ; 0 ; +; Number of I/O Rules Inapplicable ; 27 ; ++----------------------------------+-------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Details ; ++--------------+-----------+-----------------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+ +; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ; ++--------------+-----------+-----------------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+ +; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ; +; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ; +; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ; +; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ; +; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ; +; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ; +; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No PCI I/O assignments found. ; I/O ; ; +; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ; +; Inapplicable ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ; +; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No PCI I/O assignments found. ; I/O ; ; +; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ; +; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ; +; Inapplicable ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; No Termination assignments found. ; I/O ; ; +; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength or Termination assignments found. ; I/O ; ; +; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ; +; Inapplicable ; IO_000032 ; I/O Properties Checks for Multiple I/Os ; I/O registers and SERDES should not be used at the same XY location. ; Critical ; No I/O Registers or Differential I/O Standard assignments found. ; I/O ; ; +; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 250mA for row I/Os and 250mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ; +; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 1 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000037 ; SI Related Distance Checks ; Single-ended I/O and differential I/O should not coexist in a PLL output I/O bank. ; High ; No Differential I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000038 ; SI Related SSO Limit Checks ; Single-ended outputs and High-speed LVDS should not coexist in an I/O bank. ; High ; No High-speed LVDS found. ; I/O ; ; +; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ; +; Inapplicable ; IO_000040 ; SI Related SSO Limit Checks ; The total drive strength of single ended outputs in a DPA bank should not exceed 120mA. ; High ; No DPA found. ; I/O ; ; ++--------------+-----------+-----------------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+------+-------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; I/O Rules Matrix ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+ +; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000032 ; IO_000033 ; IO_000034 ; IO_000037 ; IO_000038 ; IO_000042 ; IO_000040 ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+ +; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 107 ; 0 ; 0 ; 107 ; 107 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 107 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; Total Inapplicable ; 107 ; 107 ; 107 ; 107 ; 107 ; 0 ; 107 ; 107 ; 0 ; 0 ; 107 ; 107 ; 107 ; 107 ; 107 ; 107 ; 107 ; 107 ; 107 ; 107 ; 107 ; 107 ; 107 ; 107 ; 107 ; 0 ; 107 ; 107 ; 107 ; 107 ; 107 ; +; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; fxx_o[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx_o[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx_o[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx_o[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx_o[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx_o[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx_o[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx_o[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx_o[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx_o[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx_o[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx_o[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx_o[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx_o[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx_o[14] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx_o[15] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx1_o[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx1_o[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx1_o[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx1_o[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx1_o[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx1_o[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx1_o[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx1_o[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx1_o[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx1_o[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx1_o[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx1_o[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx1_o[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx1_o[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx1_o[14] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx1_o[15] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx2_o[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx2_o[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx2_o[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx2_o[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx2_o[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx2_o[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx2_o[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx2_o[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx2_o[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx2_o[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx2_o[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx2_o[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx2_o[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx2_o[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx2_o[14] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx2_o[15] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx3_o[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx3_o[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx3_o[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx3_o[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx3_o[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx3_o[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx3_o[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx3_o[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx3_o[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx3_o[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx3_o[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx3_o[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx3_o[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx3_o[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx3_o[14] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx3_o[15] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx4_o[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx4_o[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx4_o[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx4_o[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx4_o[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx4_o[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx4_o[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx4_o[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx4_o[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx4_o[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx4_o[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx4_o[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx4_o[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx4_o[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx4_o[14] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; fxx4_o[15] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; resul_o[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; resul_o[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; resul_o[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; resul_o[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; resul_o[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; resul_o[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; resul_o[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; resul_o[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; resul_o[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; resul_o[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; resul_o[10] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; resul_o[11] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; resul_o[12] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; resul_o[13] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; resul_o[14] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; resul_o[15] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; extrapolar_i ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; clk_i ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; rst_i ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; distancia_i[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; distancia_i[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; distancia_i[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; distancia_i[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; distancia_i[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; distancia_i[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; distancia_i[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; +; distancia_i[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; ++--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+ + + ++-------------------------------------------------------------------------+ +; Fitter Device Options ; ++----------------------------------------------+--------------------------+ +; Option ; Setting ; ++----------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Passive Serial ; +; Error detection CRC ; Off ; +; Configuration Voltage Level ; Auto ; +; Force Configuration Voltage Level ; Off ; +; nWS, nRS, nCS, CS ; Unreserved ; +; RDYnBUSY ; Unreserved ; +; Data[7..1] ; Unreserved ; +; Data[0] ; As input tri-stated ; +; ASDO,nCSO ; Unreserved ; +; Reserve all unused pins ; As output driving ground ; +; Base pin-out file on sameframe device ; Off ; ++----------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++------------------------------------------------------------+ +; Estimated Delay Added for Hold Timing ; ++-----------------+----------------------+-------------------+ +; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ; ++-----------------+----------------------+-------------------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Info: ******************************************************************* +Info: Running Quartus II Fitter + Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition + Info: Processing started: Tue Aug 14 00:27:38 2012 +Info: Command: quartus_fit --read_settings_files=on --write_settings_files=off gnextrapolator -c gnextrapolator +Info: Selected device EP2S15F484C4 for design "gnextrapolator" +Info: Low junction temperature is 0 degrees C +Info: High junction temperature is 85 degrees C +Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning: Feature LogicLock is only available with a valid subscription license. Please purchase a software subscription to gain full access to this feature. +Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info: Device EP2S15F484I4 is compatible +Info: Fitter converted 1 user pins into dedicated programming pins + Info: Pin ~DATA0~ is reserved at location E13 +Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements. +Critical Warning: No exact pin location assignment(s) for 107 pins of 107 total pins + Info: Pin fxx_o[0] not assigned to an exact location on the device + Info: Pin fxx_o[1] not assigned to an exact location on the device + Info: Pin fxx_o[2] not assigned to an exact location on the device + Info: Pin fxx_o[3] not assigned to an exact location on the device + Info: Pin fxx_o[4] not assigned to an exact location on the device + Info: Pin fxx_o[5] not assigned to an exact location on the device + Info: Pin fxx_o[6] not assigned to an exact location on the device + Info: Pin fxx_o[7] not assigned to an exact location on the device + Info: Pin fxx_o[8] not assigned to an exact location on the device + Info: Pin fxx_o[9] not assigned to an exact location on the device + Info: Pin fxx_o[10] not assigned to an exact location on the device + Info: Pin fxx_o[11] not assigned to an exact location on the device + Info: Pin fxx_o[12] not assigned to an exact location on the device + Info: Pin fxx_o[13] not assigned to an exact location on the device + Info: Pin fxx_o[14] not assigned to an exact location on the device + Info: Pin fxx_o[15] not assigned to an exact location on the device + Info: Pin fxx1_o[0] not assigned to an exact location on the device + Info: Pin fxx1_o[1] not assigned to an exact location on the device + Info: Pin fxx1_o[2] not assigned to an exact location on the device + Info: Pin fxx1_o[3] not assigned to an exact location on the device + Info: Pin fxx1_o[4] not assigned to an exact location on the device + Info: Pin fxx1_o[5] not assigned to an exact location on the device + Info: Pin fxx1_o[6] not assigned to an exact location on the device + Info: Pin fxx1_o[7] not assigned to an exact location on the device + Info: Pin fxx1_o[8] not assigned to an exact location on the device + Info: Pin fxx1_o[9] not assigned to an exact location on the device + Info: Pin fxx1_o[10] not assigned to an exact location on the device + Info: Pin fxx1_o[11] not assigned to an exact location on the device + Info: Pin fxx1_o[12] not assigned to an exact location on the device + Info: Pin fxx1_o[13] not assigned to an exact location on the device + Info: Pin fxx1_o[14] not assigned to an exact location on the device + Info: Pin fxx1_o[15] not assigned to an exact location on the device + Info: Pin fxx2_o[0] not assigned to an exact location on the device + Info: Pin fxx2_o[1] not assigned to an exact location on the device + Info: Pin fxx2_o[2] not assigned to an exact location on the device + Info: Pin fxx2_o[3] not assigned to an exact location on the device + Info: Pin fxx2_o[4] not assigned to an exact location on the device + Info: Pin fxx2_o[5] not assigned to an exact location on the device + Info: Pin fxx2_o[6] not assigned to an exact location on the device + Info: Pin fxx2_o[7] not assigned to an exact location on the device + Info: Pin fxx2_o[8] not assigned to an exact location on the device + Info: Pin fxx2_o[9] not assigned to an exact location on the device + Info: Pin fxx2_o[10] not assigned to an exact location on the device + Info: Pin fxx2_o[11] not assigned to an exact location on the device + Info: Pin fxx2_o[12] not assigned to an exact location on the device + Info: Pin fxx2_o[13] not assigned to an exact location on the device + Info: Pin fxx2_o[14] not assigned to an exact location on the device + Info: Pin fxx2_o[15] not assigned to an exact location on the device + Info: Pin fxx3_o[0] not assigned to an exact location on the device + Info: Pin fxx3_o[1] not assigned to an exact location on the device + Info: Pin fxx3_o[2] not assigned to an exact location on the device + Info: Pin fxx3_o[3] not assigned to an exact location on the device + Info: Pin fxx3_o[4] not assigned to an exact location on the device + Info: Pin fxx3_o[5] not assigned to an exact location on the device + Info: Pin fxx3_o[6] not assigned to an exact location on the device + Info: Pin fxx3_o[7] not assigned to an exact location on the device + Info: Pin fxx3_o[8] not assigned to an exact location on the device + Info: Pin fxx3_o[9] not assigned to an exact location on the device + Info: Pin fxx3_o[10] not assigned to an exact location on the device + Info: Pin fxx3_o[11] not assigned to an exact location on the device + Info: Pin fxx3_o[12] not assigned to an exact location on the device + Info: Pin fxx3_o[13] not assigned to an exact location on the device + Info: Pin fxx3_o[14] not assigned to an exact location on the device + Info: Pin fxx3_o[15] not assigned to an exact location on the device + Info: Pin fxx4_o[0] not assigned to an exact location on the device + Info: Pin fxx4_o[1] not assigned to an exact location on the device + Info: Pin fxx4_o[2] not assigned to an exact location on the device + Info: Pin fxx4_o[3] not assigned to an exact location on the device + Info: Pin fxx4_o[4] not assigned to an exact location on the device + Info: Pin fxx4_o[5] not assigned to an exact location on the device + Info: Pin fxx4_o[6] not assigned to an exact location on the device + Info: Pin fxx4_o[7] not assigned to an exact location on the device + Info: Pin fxx4_o[8] not assigned to an exact location on the device + Info: Pin fxx4_o[9] not assigned to an exact location on the device + Info: Pin fxx4_o[10] not assigned to an exact location on the device + Info: Pin fxx4_o[11] not assigned to an exact location on the device + Info: Pin fxx4_o[12] not assigned to an exact location on the device + Info: Pin fxx4_o[13] not assigned to an exact location on the device + Info: Pin fxx4_o[14] not assigned to an exact location on the device + Info: Pin fxx4_o[15] not assigned to an exact location on the device + Info: Pin resul_o[0] not assigned to an exact location on the device + Info: Pin resul_o[1] not assigned to an exact location on the device + Info: Pin resul_o[2] not assigned to an exact location on the device + Info: Pin resul_o[3] not assigned to an exact location on the device + Info: Pin resul_o[4] not assigned to an exact location on the device + Info: Pin resul_o[5] not assigned to an exact location on the device + Info: Pin resul_o[6] not assigned to an exact location on the device + Info: Pin resul_o[7] not assigned to an exact location on the device + Info: Pin resul_o[8] not assigned to an exact location on the device + Info: Pin resul_o[9] not assigned to an exact location on the device + Info: Pin resul_o[10] not assigned to an exact location on the device + Info: Pin resul_o[11] not assigned to an exact location on the device + Info: Pin resul_o[12] not assigned to an exact location on the device + Info: Pin resul_o[13] not assigned to an exact location on the device + Info: Pin resul_o[14] not assigned to an exact location on the device + Info: Pin resul_o[15] not assigned to an exact location on the device + Info: Pin extrapolar_i not assigned to an exact location on the device + Info: Pin clk_i not assigned to an exact location on the device + Info: Pin rst_i not assigned to an exact location on the device + Info: Pin distancia_i[5] not assigned to an exact location on the device + Info: Pin distancia_i[3] not assigned to an exact location on the device + Info: Pin distancia_i[4] not assigned to an exact location on the device + Info: Pin distancia_i[2] not assigned to an exact location on the device + Info: Pin distancia_i[0] not assigned to an exact location on the device + Info: Pin distancia_i[1] not assigned to an exact location on the device + Info: Pin distancia_i[6] not assigned to an exact location on the device + Info: Pin distancia_i[7] not assigned to an exact location on the device +Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details +Info: Timing-driven compilation is using the Classic Timing Analyzer +Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time. +Info: Automatically promoted node clk_i (placed in PIN N20 (CLK3p, Input)) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3 +Info: Automatically promoted node rst_i (placed in PIN M21 (CLK1p, Input)) + Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1 + Info: Following destination nodes may be non-global or may not use global or regional clocks + Info: Destination node resultado[0] + Info: Destination node fxx_o[15]~reg0 + Info: Destination node fxx_o[14]~reg0 + Info: Destination node fxx_o[13]~reg0 + Info: Destination node fxx_o[12]~reg0 + Info: Destination node fxx_o[11]~reg0 + Info: Destination node fxx_o[10]~reg0 + Info: Destination node fxx_o[9]~reg0 + Info: Destination node fxx_o[8]~reg0 + Info: Destination node fxx_o[7]~reg0 + Info: Non-global destination nodes limited to 10 nodes +Info: Starting register packing +Extra Info: Performing register packing on registers with non-logic cell location assignments +Extra Info: Completed register packing on registers with non-logic cell location assignments +Extra Info: Started Fast Input/Output/OE register processing +Extra Info: Finished Fast Input/Output/OE register processing +Extra Info: Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density +Extra Info: Finished moving registers into I/O cells, DSP blocks, and RAM blocks +Info: Finished register packing + Extra Info: No registers were packed into other blocks +Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info: Number of I/O pins in group: 105 (unused VREF, 3.3V VCCIO, 9 input, 96 output, 0 bidirectional) + Info: I/O standards used: 3.3-V LVTTL. +Info: I/O bank details before I/O pin placement + Info: Statistics of I/O banks + Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 39 pins available + Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 43 pins available + Info: I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 49 pins available + Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 35 pins available + Info: I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 44 pins available + Info: I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available + Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 34 pins available + Info: I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available + Info: I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available + Info: I/O bank number 10 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available +Info: Fitter preparation operations ending: elapsed time is 00:00:03 +Info: Fitter placement preparation operations beginning +Info: Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info: Fitter placement operations beginning +Info: Fitter placement was successful +Info: Fitter placement operations ending: elapsed time is 00:00:03 +Info: Estimated most critical path is memory to register delay of 10.924 ns + Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M512_X24_Y8; Fanout = 1; MEM Node = 'altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7~porta_address_reg4' + Info: 2: + IC(0.000 ns) + CELL(2.061 ns) = 2.061 ns; Loc. = M512_X24_Y8; Fanout = 6; MEM Node = 'altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7' + Info: 3: + IC(0.821 ns) + CELL(0.313 ns) = 3.195 ns; Loc. = LAB_X27_Y5; Fanout = 2; COMB Node = 'fx~23' + Info: 4: + IC(0.879 ns) + CELL(0.480 ns) = 4.554 ns; Loc. = LAB_X23_Y8; Fanout = 6; COMB Node = 'Add2~37' + Info: 5: + IC(0.580 ns) + CELL(0.480 ns) = 5.614 ns; Loc. = LAB_X22_Y7; Fanout = 7; COMB Node = 'Add3~33' + Info: 6: + IC(0.833 ns) + CELL(0.426 ns) = 6.873 ns; Loc. = LAB_X22_Y6; Fanout = 7; COMB Node = 'Add4~37' + Info: 7: + IC(0.775 ns) + CELL(0.480 ns) = 8.128 ns; Loc. = LAB_X25_Y6; Fanout = 2; COMB Node = 'Add8~29' + Info: 8: + IC(0.580 ns) + CELL(0.403 ns) = 9.111 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~30' + Info: 9: + IC(0.102 ns) + CELL(0.041 ns) = 9.254 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~34' + Info: 10: + IC(0.000 ns) + CELL(0.041 ns) = 9.295 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~38' + Info: 11: + IC(0.000 ns) + CELL(0.041 ns) = 9.336 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~42' + Info: 12: + IC(0.000 ns) + CELL(0.041 ns) = 9.377 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~46' + Info: 13: + IC(0.000 ns) + CELL(0.041 ns) = 9.418 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~50' + Info: 14: + IC(0.000 ns) + CELL(0.041 ns) = 9.459 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~54' + Info: 15: + IC(0.000 ns) + CELL(0.041 ns) = 9.500 ns; Loc. = LAB_X26_Y5; Fanout = 1; COMB Node = 'Add9~58' + Info: 16: + IC(0.000 ns) + CELL(0.144 ns) = 9.644 ns; Loc. = LAB_X26_Y5; Fanout = 2; COMB Node = 'Add9~61' + Info: 17: + IC(1.102 ns) + CELL(0.178 ns) = 10.924 ns; Loc. = LAB_X23_Y7; Fanout = 4; REG Node = 'resultado[15]' + Info: Total cell delay = 5.252 ns ( 48.08 % ) + Info: Total interconnect delay = 5.672 ns ( 51.92 % ) +Info: Fitter routing operations beginning +Info: Average interconnect usage is 0% of the available device resources + Info: Peak interconnect usage is 2% of the available device resources in the region that extends from location X13_Y0 to location X26_Y13 +Info: Fitter routing operations ending: elapsed time is 00:00:02 +Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info: Optimizations that may affect the design's routability were skipped + Info: Optimizations that may affect the design's timing were skipped +Info: Started post-fitting delay annotation +Warning: Found 96 output pins without output pin load capacitance assignment + Info: Pin "fxx_o[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx_o[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx1_o[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx2_o[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx3_o[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "fxx4_o[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info: Pin "resul_o[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis +Info: Delay annotation completed successfully +Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. +Info: Quartus II Fitter was successful. 0 errors, 5 warnings + Info: Peak virtual memory: 233 megabytes + Info: Processing ended: Tue Aug 14 00:28:05 2012 + Info: Elapsed time: 00:00:27 + Info: Total CPU time (on all processors): 00:00:27 + + Index: trunk/QuartusII/gnextrapolator.qsf =================================================================== --- trunk/QuartusII/gnextrapolator.qsf (nonexistent) +++ trunk/QuartusII/gnextrapolator.qsf (revision 5) @@ -0,0 +1,56 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2010 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II +# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition +# Date created = 23:38:03 August 13, 2012 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# gnextrapolator_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Stratix II" +set_global_assignment -name DEVICE EP2S15F484C4 +set_global_assignment -name TOP_LEVEL_ENTITY gnextrapolator +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.1 SP2" +set_global_assignment -name PROJECT_CREATION_TIME_DATE "23:38:03 AUGUST 13, 2012" +set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2" +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name VHDL_FILE gnextrapolator.vhd +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name VECTOR_WAVEFORM_FILE gnextrapolator.vwf +set_global_assignment -name MIF_FILE gnextrapolator.mif +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file Index: trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.kpt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.kpt =================================================================== --- trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.kpt (nonexistent) +++ trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.kpt (revision 5)
trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.kpt Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.rcfdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.rcfdb =================================================================== --- trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.rcfdb (nonexistent) +++ trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.rcfdb (revision 5)
trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.rcfdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.re.rcfdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.re.rcfdb =================================================================== --- trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.re.rcfdb (nonexistent) +++ trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.re.rcfdb (revision 5)
trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.re.rcfdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.map.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.map.cdb =================================================================== --- trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.map.cdb (nonexistent) +++ trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.map.cdb (revision 5)
trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.map.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.logdb =================================================================== --- trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.logdb (nonexistent) +++ trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.logdb (revision 5) @@ -0,0 +1,17 @@ +v1 +RAM_PACKING,0,M512,18,18,SimpleDual,0,3,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a0, +RAM_PACKING,0,M512,18,18,SimpleDual,0,2,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a1, +RAM_PACKING,0,M512,18,18,SimpleDual,0,8,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a2, +RAM_PACKING,0,M512,18,18,SimpleDual,0,16,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a3, +RAM_PACKING,0,M512,18,18,SimpleDual,0,9,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a4, +RAM_PACKING,0,M512,18,18,SimpleDual,0,10,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a5, +RAM_PACKING,0,M512,18,18,SimpleDual,0,13,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a6, +RAM_PACKING,0,M512,18,18,SimpleDual,0,4,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a7, +RAM_PACKING,0,M512,18,18,SimpleDual,0,1,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a8, +RAM_PACKING,0,M512,18,18,SimpleDual,0,11,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a9, +RAM_PACKING,0,M512,18,18,SimpleDual,0,17,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a10, +RAM_PACKING,0,M512,18,18,SimpleDual,0,7,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a11, +RAM_PACKING,0,M512,18,18,SimpleDual,0,14,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a12, +RAM_PACKING,0,M512,18,18,SimpleDual,0,6,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a13, +RAM_PACKING,0,M512,18,18,SimpleDual,0,12,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a14, +RAM_PACKING,0,M512,18,18,SimpleDual,0,0,10000000,altsyncram:ram_rtl_0|altsyncram_uv61:auto_generated|ram_block1a15, Index: trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.cdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.cdb =================================================================== --- trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.cdb (nonexistent) +++ trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.cdb (revision 5)
trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.cdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.dfp =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.dfp =================================================================== --- trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.dfp (nonexistent) +++ trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.dfp (revision 5)
trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.dfp Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.map.dpi =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.map.dpi =================================================================== --- trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.map.dpi (nonexistent) +++ trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.map.dpi (revision 5)
trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.map.dpi Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.map.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.map.hdb =================================================================== --- trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.map.hdb (nonexistent) +++ trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.map.hdb (revision 5)
trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.map.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.map.kpt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.map.kpt =================================================================== --- trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.map.kpt (nonexistent) +++ trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.map.kpt (revision 5)
trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.map.kpt Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.hdb =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.hdb =================================================================== --- trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.hdb (nonexistent) +++ trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.hdb (revision 5)
trunk/QuartusII/incremental_db/compiled_partitions/gnextrapolator.root_partition.cmp.hdb Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/QuartusII/gnextrapolator.vwf =================================================================== --- trunk/QuartusII/gnextrapolator.vwf (nonexistent) +++ trunk/QuartusII/gnextrapolator.vwf (revision 5) @@ -0,0 +1,2845 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2010 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("clk_i") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("distancia_i") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 5; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("distancia_i[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "distancia_i"; +} + +SIGNAL("distancia_i[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "distancia_i"; +} + +SIGNAL("distancia_i[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "distancia_i"; +} + +SIGNAL("distancia_i[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "distancia_i"; +} + +SIGNAL("distancia_i[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "distancia_i"; +} + +SIGNAL("extrapolar_i") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("fxx1_o") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 14; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("fxx1_o[13]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx1_o"; +} + +SIGNAL("fxx1_o[12]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx1_o"; +} + +SIGNAL("fxx1_o[11]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx1_o"; +} + +SIGNAL("fxx1_o[10]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx1_o"; +} + +SIGNAL("fxx1_o[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx1_o"; +} + +SIGNAL("fxx1_o[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx1_o"; +} + +SIGNAL("fxx1_o[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx1_o"; +} + +SIGNAL("fxx1_o[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx1_o"; +} + +SIGNAL("fxx1_o[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx1_o"; +} + +SIGNAL("fxx1_o[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx1_o"; +} + +SIGNAL("fxx1_o[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx1_o"; +} + +SIGNAL("fxx1_o[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx1_o"; +} + +SIGNAL("fxx1_o[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx1_o"; +} + +SIGNAL("fxx1_o[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx1_o"; +} + +SIGNAL("fxx2_o") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 14; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("fxx2_o[13]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx2_o"; +} + +SIGNAL("fxx2_o[12]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx2_o"; +} + +SIGNAL("fxx2_o[11]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx2_o"; +} + +SIGNAL("fxx2_o[10]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx2_o"; +} + +SIGNAL("fxx2_o[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx2_o"; +} + +SIGNAL("fxx2_o[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx2_o"; +} + +SIGNAL("fxx2_o[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx2_o"; +} + +SIGNAL("fxx2_o[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx2_o"; +} + +SIGNAL("fxx2_o[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx2_o"; +} + +SIGNAL("fxx2_o[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx2_o"; +} + +SIGNAL("fxx2_o[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx2_o"; +} + +SIGNAL("fxx2_o[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx2_o"; +} + +SIGNAL("fxx2_o[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx2_o"; +} + +SIGNAL("fxx2_o[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx2_o"; +} + +SIGNAL("fxx3_o") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 14; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("fxx3_o[13]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx3_o"; +} + +SIGNAL("fxx3_o[12]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx3_o"; +} + +SIGNAL("fxx3_o[11]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx3_o"; +} + +SIGNAL("fxx3_o[10]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx3_o"; +} + +SIGNAL("fxx3_o[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx3_o"; +} + +SIGNAL("fxx3_o[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx3_o"; +} + +SIGNAL("fxx3_o[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx3_o"; +} + +SIGNAL("fxx3_o[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx3_o"; +} + +SIGNAL("fxx3_o[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx3_o"; +} + +SIGNAL("fxx3_o[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx3_o"; +} + +SIGNAL("fxx3_o[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx3_o"; +} + +SIGNAL("fxx3_o[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx3_o"; +} + +SIGNAL("fxx3_o[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx3_o"; +} + +SIGNAL("fxx3_o[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx3_o"; +} + +SIGNAL("fxx4_o") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 14; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("fxx4_o[13]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx4_o"; +} + +SIGNAL("fxx4_o[12]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx4_o"; +} + +SIGNAL("fxx4_o[11]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx4_o"; +} + +SIGNAL("fxx4_o[10]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx4_o"; +} + +SIGNAL("fxx4_o[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx4_o"; +} + +SIGNAL("fxx4_o[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx4_o"; +} + +SIGNAL("fxx4_o[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx4_o"; +} + +SIGNAL("fxx4_o[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx4_o"; +} + +SIGNAL("fxx4_o[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx4_o"; +} + +SIGNAL("fxx4_o[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx4_o"; +} + +SIGNAL("fxx4_o[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx4_o"; +} + +SIGNAL("fxx4_o[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx4_o"; +} + +SIGNAL("fxx4_o[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx4_o"; +} + +SIGNAL("fxx4_o[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx4_o"; +} + +SIGNAL("fxx_o") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 14; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("fxx_o[13]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx_o"; +} + +SIGNAL("fxx_o[12]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx_o"; +} + +SIGNAL("fxx_o[11]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx_o"; +} + +SIGNAL("fxx_o[10]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx_o"; +} + +SIGNAL("fxx_o[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx_o"; +} + +SIGNAL("fxx_o[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx_o"; +} + +SIGNAL("fxx_o[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx_o"; +} + +SIGNAL("fxx_o[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx_o"; +} + +SIGNAL("fxx_o[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx_o"; +} + +SIGNAL("fxx_o[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx_o"; +} + +SIGNAL("fxx_o[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx_o"; +} + +SIGNAL("fxx_o[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx_o"; +} + +SIGNAL("fxx_o[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx_o"; +} + +SIGNAL("fxx_o[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "fxx_o"; +} + +SIGNAL("resul_o") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 14; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("resul_o[13]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "resul_o"; +} + +SIGNAL("resul_o[12]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "resul_o"; +} + +SIGNAL("resul_o[11]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "resul_o"; +} + +SIGNAL("resul_o[10]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "resul_o"; +} + +SIGNAL("resul_o[9]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "resul_o"; +} + +SIGNAL("resul_o[8]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "resul_o"; +} + +SIGNAL("resul_o[7]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "resul_o"; +} + +SIGNAL("resul_o[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "resul_o"; +} + +SIGNAL("resul_o[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "resul_o"; +} + +SIGNAL("resul_o[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "resul_o"; +} + +SIGNAL("resul_o[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "resul_o"; +} + +SIGNAL("resul_o[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "resul_o"; +} + +SIGNAL("resul_o[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "resul_o"; +} + +SIGNAL("resul_o[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "resul_o"; +} + +SIGNAL("rst_i") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +TRANSITION_LIST("clk_i") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("distancia_i[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("distancia_i[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("distancia_i[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("distancia_i[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("distancia_i[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("extrapolar_i") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("fxx1_o[13]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx1_o[12]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx1_o[11]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx1_o[10]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx1_o[9]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx1_o[8]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx1_o[7]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx1_o[6]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx1_o[5]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx1_o[4]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx1_o[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx1_o[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx1_o[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx1_o[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx2_o[13]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx2_o[12]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx2_o[11]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx2_o[10]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx2_o[9]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx2_o[8]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx2_o[7]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx2_o[6]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx2_o[5]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx2_o[4]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx2_o[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx2_o[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx2_o[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx2_o[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx3_o[13]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx3_o[12]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx3_o[11]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx3_o[10]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx3_o[9]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx3_o[8]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx3_o[7]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx3_o[6]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx3_o[5]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx3_o[4]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx3_o[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx3_o[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx3_o[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx3_o[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx4_o[13]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx4_o[12]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx4_o[11]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx4_o[10]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx4_o[9]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx4_o[8]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx4_o[7]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx4_o[6]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx4_o[5]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx4_o[4]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx4_o[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx4_o[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx4_o[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx4_o[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx_o[13]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx_o[12]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx_o[11]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx_o[10]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx_o[9]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx_o[8]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx_o[7]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx_o[6]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx_o[5]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx_o[4]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx_o[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx_o[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx_o[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("fxx_o[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("resul_o[13]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("resul_o[12]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("resul_o[11]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("resul_o[10]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("resul_o[9]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("resul_o[8]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("resul_o[7]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("resul_o[6]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("resul_o[5]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("resul_o[4]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("resul_o[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("resul_o[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("resul_o[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("resul_o[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("rst_i") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "clk_i"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "rst_i"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "extrapolar_i"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "distancia_i"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 0; + CHILDREN = 4, 5, 6, 7, 8; +} + +DISPLAY_LINE +{ + CHANNEL = "distancia_i[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "distancia_i[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "distancia_i[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "distancia_i[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "distancia_i[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx1_o"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 0; + CHILDREN = 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx1_o[13]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx1_o[12]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx1_o[11]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx1_o[10]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx1_o[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx1_o[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx1_o[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx1_o[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 17; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx1_o[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 18; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx1_o[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 19; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx1_o[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 20; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx1_o[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 21; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx1_o[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 22; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx1_o[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 23; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx2_o"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 24; + TREE_LEVEL = 0; + CHILDREN = 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx2_o[13]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 25; + TREE_LEVEL = 1; + PARENT = 24; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx2_o[12]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 26; + TREE_LEVEL = 1; + PARENT = 24; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx2_o[11]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 27; + TREE_LEVEL = 1; + PARENT = 24; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx2_o[10]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 28; + TREE_LEVEL = 1; + PARENT = 24; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx2_o[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 29; + TREE_LEVEL = 1; + PARENT = 24; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx2_o[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 30; + TREE_LEVEL = 1; + PARENT = 24; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx2_o[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 31; + TREE_LEVEL = 1; + PARENT = 24; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx2_o[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 32; + TREE_LEVEL = 1; + PARENT = 24; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx2_o[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 33; + TREE_LEVEL = 1; + PARENT = 24; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx2_o[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 34; + TREE_LEVEL = 1; + PARENT = 24; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx2_o[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 35; + TREE_LEVEL = 1; + PARENT = 24; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx2_o[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 36; + TREE_LEVEL = 1; + PARENT = 24; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx2_o[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 37; + TREE_LEVEL = 1; + PARENT = 24; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx2_o[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 38; + TREE_LEVEL = 1; + PARENT = 24; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx3_o"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 39; + TREE_LEVEL = 0; + CHILDREN = 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx3_o[13]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 40; + TREE_LEVEL = 1; + PARENT = 39; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx3_o[12]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 41; + TREE_LEVEL = 1; + PARENT = 39; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx3_o[11]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 42; + TREE_LEVEL = 1; + PARENT = 39; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx3_o[10]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 43; + TREE_LEVEL = 1; + PARENT = 39; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx3_o[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 44; + TREE_LEVEL = 1; + PARENT = 39; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx3_o[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 45; + TREE_LEVEL = 1; + PARENT = 39; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx3_o[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 46; + TREE_LEVEL = 1; + PARENT = 39; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx3_o[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 47; + TREE_LEVEL = 1; + PARENT = 39; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx3_o[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 48; + TREE_LEVEL = 1; + PARENT = 39; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx3_o[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 49; + TREE_LEVEL = 1; + PARENT = 39; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx3_o[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 50; + TREE_LEVEL = 1; + PARENT = 39; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx3_o[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 51; + TREE_LEVEL = 1; + PARENT = 39; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx3_o[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 52; + TREE_LEVEL = 1; + PARENT = 39; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx3_o[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 53; + TREE_LEVEL = 1; + PARENT = 39; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx4_o"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 54; + TREE_LEVEL = 0; + CHILDREN = 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx4_o[13]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 55; + TREE_LEVEL = 1; + PARENT = 54; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx4_o[12]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 56; + TREE_LEVEL = 1; + PARENT = 54; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx4_o[11]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 57; + TREE_LEVEL = 1; + PARENT = 54; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx4_o[10]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 58; + TREE_LEVEL = 1; + PARENT = 54; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx4_o[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 59; + TREE_LEVEL = 1; + PARENT = 54; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx4_o[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 60; + TREE_LEVEL = 1; + PARENT = 54; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx4_o[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 61; + TREE_LEVEL = 1; + PARENT = 54; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx4_o[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 62; + TREE_LEVEL = 1; + PARENT = 54; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx4_o[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 63; + TREE_LEVEL = 1; + PARENT = 54; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx4_o[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 64; + TREE_LEVEL = 1; + PARENT = 54; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx4_o[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 65; + TREE_LEVEL = 1; + PARENT = 54; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx4_o[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 66; + TREE_LEVEL = 1; + PARENT = 54; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx4_o[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 67; + TREE_LEVEL = 1; + PARENT = 54; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx4_o[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 68; + TREE_LEVEL = 1; + PARENT = 54; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx_o"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 69; + TREE_LEVEL = 0; + CHILDREN = 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx_o[13]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 70; + TREE_LEVEL = 1; + PARENT = 69; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx_o[12]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 71; + TREE_LEVEL = 1; + PARENT = 69; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx_o[11]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 72; + TREE_LEVEL = 1; + PARENT = 69; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx_o[10]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 73; + TREE_LEVEL = 1; + PARENT = 69; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx_o[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 74; + TREE_LEVEL = 1; + PARENT = 69; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx_o[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 75; + TREE_LEVEL = 1; + PARENT = 69; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx_o[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 76; + TREE_LEVEL = 1; + PARENT = 69; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx_o[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 77; + TREE_LEVEL = 1; + PARENT = 69; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx_o[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 78; + TREE_LEVEL = 1; + PARENT = 69; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx_o[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 79; + TREE_LEVEL = 1; + PARENT = 69; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx_o[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 80; + TREE_LEVEL = 1; + PARENT = 69; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx_o[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 81; + TREE_LEVEL = 1; + PARENT = 69; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx_o[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 82; + TREE_LEVEL = 1; + PARENT = 69; +} + +DISPLAY_LINE +{ + CHANNEL = "fxx_o[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 83; + TREE_LEVEL = 1; + PARENT = 69; +} + +DISPLAY_LINE +{ + CHANNEL = "resul_o"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 84; + TREE_LEVEL = 0; + CHILDREN = 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98; +} + +DISPLAY_LINE +{ + CHANNEL = "resul_o[13]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 85; + TREE_LEVEL = 1; + PARENT = 84; +} + +DISPLAY_LINE +{ + CHANNEL = "resul_o[12]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 86; + TREE_LEVEL = 1; + PARENT = 84; +} + +DISPLAY_LINE +{ + CHANNEL = "resul_o[11]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 87; + TREE_LEVEL = 1; + PARENT = 84; +} + +DISPLAY_LINE +{ + CHANNEL = "resul_o[10]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 88; + TREE_LEVEL = 1; + PARENT = 84; +} + +DISPLAY_LINE +{ + CHANNEL = "resul_o[9]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 89; + TREE_LEVEL = 1; + PARENT = 84; +} + +DISPLAY_LINE +{ + CHANNEL = "resul_o[8]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 90; + TREE_LEVEL = 1; + PARENT = 84; +} + +DISPLAY_LINE +{ + CHANNEL = "resul_o[7]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 91; + TREE_LEVEL = 1; + PARENT = 84; +} + +DISPLAY_LINE +{ + CHANNEL = "resul_o[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 92; + TREE_LEVEL = 1; + PARENT = 84; +} + +DISPLAY_LINE +{ + CHANNEL = "resul_o[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 93; + TREE_LEVEL = 1; + PARENT = 84; +} + +DISPLAY_LINE +{ + CHANNEL = "resul_o[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 94; + TREE_LEVEL = 1; + PARENT = 84; +} + +DISPLAY_LINE +{ + CHANNEL = "resul_o[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 95; + TREE_LEVEL = 1; + PARENT = 84; +} + +DISPLAY_LINE +{ + CHANNEL = "resul_o[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 96; + TREE_LEVEL = 1; + PARENT = 84; +} + +DISPLAY_LINE +{ + CHANNEL = "resul_o[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 97; + TREE_LEVEL = 1; + PARENT = 84; +} + +DISPLAY_LINE +{ + CHANNEL = "resul_o[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 98; + TREE_LEVEL = 1; + PARENT = 84; +} + +TIME_BAR +{ + TIME = 10900; + MASTER = TRUE; +} +;

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