OpenCores
URL https://opencores.org/ocsvn/ha1588/ha1588/trunk

Subversion Repositories ha1588

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    /ha1588
    from Rev 72 to Rev 73
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Rev 72 → Rev 73

/trunk/rtl/bus/xps/pcores/ha1588_axi_v1_00_a/hdl/verilog/ha1588_axi.v
26,7 → 26,7
 
// Register Slave Interface Write Response Ports
output wire [2-1:0] S_AXI_REG_BRESP,
output wire S_AXI_REG_BVALID,
output reg S_AXI_REG_BVALID,
input wire S_AXI_REG_BREADY,
 
// Register Slave Interface Read Address Ports
78,7 → 78,10
assign S_AXI_REG_AWREADY = 1'b1;
assign S_AXI_REG_WREADY = 1'b1;
assign S_AXI_REG_BRESP = 2'b00;
assign S_AXI_REG_BVALID = S_AXI_REG_WVALID;
always @(negedge S_AXI_REG_ARESETN or posedge S_AXI_REG_ACLK) begin
if (!S_AXI_REG_ARESETN) S_AXI_REG_BVALID <= 1'b0;
else S_AXI_REG_BVALID <= S_AXI_REG_WVALID;
end
assign S_AXI_REG_ARREADY = 1'b1;
assign S_AXI_REG_RDATA = up_data_rd;
assign S_AXI_REG_RRESP = 2'b00;
/trunk/rtl/reg/reg.v
125,7 → 125,7
wire cs_7c = (addr_in[7:2]==const_7c[7:2])? 1'b1: 1'b0;
 
reg [31:0] reg_00; // ctrl 5 bit
reg [31:0] reg_04; // null
reg [31:0] reg_04; // scratch reg
reg [31:0] reg_08; // null
reg [31:0] reg_0c; // null
reg [31:0] reg_10; // time 16 bit s
208,7 → 208,7
always @(posedge clk) begin
// register mapping: RTC
if (rd_in && cs_00) data_out_reg <= {27'd0, reg_00[ 4: 2], adj_ld_done_in, time_ok};
if (rd_in && cs_04) data_out_reg <= 32'd0;
if (rd_in && cs_04) data_out_reg <= reg_04;
if (rd_in && cs_08) data_out_reg <= 32'd0;
if (rd_in && cs_0c) data_out_reg <= 32'd0;
if (rd_in && cs_10) data_out_reg <= {16'd0, time_reg_sec_int[47:32]};
/trunk/par/xilinx/ReadMe.txt
0,0 → 1,2
1. Double click ha1588.ppr to open the PlanAhead IDE.
2. Run "source ha1588.tcl" to setup the project.
/trunk/sys/altera/cleanup.sh
0,0 → 1,2
rm -rf db incremental_db output .qsys_edit
rm -f *.qdf
/trunk/sys/altera/system.qsys
0,0 → 1,213
<?xml version="1.0" encoding="UTF-8"?>
<system name="$${FILENAME}">
<component
name="$${FILENAME}"
displayName="$${FILENAME}"
version="1.0"
description=""
tags=""
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $${FILENAME}
{
}
element clk_0
{
datum _sortIndex
{
value = "0";
type = "int";
}
}
element ha1588_avl_0
{
datum _sortIndex
{
value = "1";
type = "int";
}
}
element mgc_axi4_inline_monitor_0
{
datum _sortIndex
{
value = "4";
type = "int";
}
}
element mgc_axi4_master_0
{
datum _sortIndex
{
value = "2";
type = "int";
}
}
element mgc_axi4_slave_0
{
datum _sortIndex
{
value = "3";
type = "int";
}
}
element ha1588_avl_0.reg_interface
{
datum baseAddress
{
value = "65536";
type = "String";
}
}
}
]]></parameter>
<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
<parameter name="device" value="5CSEBA5U19A7" />
<parameter name="deviceFamily" value="Cyclone V" />
<parameter name="deviceSpeedGrade" value="7" />
<parameter name="fabricMode" value="QSYS" />
<parameter name="generateLegacySim" value="false" />
<parameter name="generationId" value="0" />
<parameter name="globalResetBus" value="false" />
<parameter name="hdlLanguage" value="VERILOG" />
<parameter name="maxAdditionalLatency" value="1" />
<parameter name="projectName" value="system.qpf" />
<parameter name="sopcBorderPoints" value="false" />
<parameter name="systemHash" value="1" />
<parameter name="timeStamp" value="1360206312732" />
<parameter name="useTestBenchNamingPattern" value="false" />
<instanceScript></instanceScript>
<interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
<interface
name="ha1588_avl_0_rtc_interface"
internal="ha1588_avl_0.rtc_interface"
type="conduit"
dir="end" />
<interface
name="ha1588_avl_0_tsu_interface"
internal="ha1588_avl_0.tsu_interface"
type="conduit"
dir="end" />
<interface
name="clk_0_clk_in_reset"
internal="clk_0.clk_in_reset"
type="reset"
dir="end" />
<module kind="clock_source" version="12.1" enabled="1" name="clk_0">
<parameter name="clockFrequency" value="50000000" />
<parameter name="clockFrequencyKnown" value="true" />
<parameter name="inputClockFrequency" value="0" />
<parameter name="resetSynchronousEdges" value="NONE" />
</module>
<module kind="ha1588_avl" version="1.0" enabled="1" name="ha1588_avl_0">
<parameter name="addr_is_in_word" value="true" />
<parameter name="AUTO_CLOCK_CLOCK_RATE" value="50000000" />
</module>
<module
kind="mgc_axi4_master"
version="10.1.3.1"
enabled="1"
name="mgc_axi4_master_0">
<parameter name="AXI4_ADDRESS_WIDTH" value="32" />
<parameter name="AXI4_RDATA_WIDTH" value="32" />
<parameter name="AXI4_WDATA_WIDTH" value="32" />
<parameter name="AXI4_ID_WIDTH" value="8" />
<parameter name="AXI4_USER_WIDTH" value="8" />
<parameter name="AXI4_REGION_MAP_SIZE" value="16" />
<parameter name="index" value="0" />
<parameter name="AUTO_CLOCK_SINK_CLOCK_RATE" value="50000000" />
</module>
<module
kind="mgc_axi4_inline_monitor"
version="10.1.3.1"
enabled="1"
name="mgc_axi4_inline_monitor_0">
<parameter name="AXI4_ADDRESS_WIDTH" value="32" />
<parameter name="AXI4_RDATA_WIDTH" value="32" />
<parameter name="AXI4_WDATA_WIDTH" value="32" />
<parameter name="AXI4_ID_WIDTH" value="8" />
<parameter name="AXI4_USER_WIDTH" value="8" />
<parameter name="AXI4_REGION_MAP_SIZE" value="16" />
<parameter name="index" value="0" />
<parameter name="AUTO_CLOCK_SINK_CLOCK_RATE" value="50000000" />
</module>
<module
kind="mgc_axi4_slave"
version="10.1.3.1"
enabled="1"
name="mgc_axi4_slave_0">
<parameter name="AXI4_ADDRESS_WIDTH" value="16" />
<parameter name="AXI4_RDATA_WIDTH" value="1024" />
<parameter name="AXI4_WDATA_WIDTH" value="1024" />
<parameter name="AXI4_ID_WIDTH" value="18" />
<parameter name="AXI4_USER_WIDTH" value="8" />
<parameter name="AXI4_REGION_MAP_SIZE" value="16" />
<parameter name="index" value="0" />
<parameter name="AUTO_CLOCK_SINK_CLOCK_RATE" value="50000000" />
</module>
<connection
kind="clock"
version="12.1"
start="clk_0.clk"
end="ha1588_avl_0.clock" />
<connection
kind="reset"
version="12.1"
start="clk_0.clk_reset"
end="ha1588_avl_0.clock_reset" />
<connection
kind="avalon"
version="12.1"
start="mgc_axi4_master_0.altera_axi4_master"
end="ha1588_avl_0.reg_interface">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00010000" />
</connection>
<connection
kind="clock"
version="12.1"
start="clk_0.clk"
end="mgc_axi4_master_0.clock_sink" />
<connection
kind="reset"
version="12.1"
start="clk_0.clk_reset"
end="mgc_axi4_master_0.reset_sink" />
<connection
kind="clock"
version="12.1"
start="clk_0.clk"
end="mgc_axi4_inline_monitor_0.clock_sink" />
<connection
kind="reset"
version="12.1"
start="clk_0.clk_reset"
end="mgc_axi4_inline_monitor_0.reset_sink" />
<connection
kind="avalon"
version="12.1"
start="mgc_axi4_inline_monitor_0.altera_axi4_master"
end="ha1588_avl_0.reg_interface">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x00010000" />
</connection>
<connection
kind="clock"
version="12.1"
start="clk_0.clk"
end="mgc_axi4_slave_0.clock_sink" />
<connection
kind="reset"
version="12.1"
start="clk_0.clk_reset"
end="mgc_axi4_slave_0.reset_sink" />
<connection
kind="avalon"
version="12.1"
start="mgc_axi4_master_0.altera_axi4_master"
end="mgc_axi4_slave_0.altera_axi4_slave">
<parameter name="arbitrationPriority" value="1" />
<parameter name="baseAddress" value="0x0000" />
</connection>
</system>
/trunk/sys/altera/system.qpf
0,0 → 1,30
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2012 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 12.1 Build 177 11/07/2012 SJ Web Edition
# Date created = 15:58:54 February 03, 2013
#
# -------------------------------------------------------------------------- #
 
QUARTUS_VERSION = "12.1"
DATE = "15:58:54 February 03, 2013"
 
# Revisions
 
PROJECT_REVISION = "system"
/trunk/sys/altera/ReadMe.txt
0,0 → 1,2
Need to add IP Search Path first:
In Tool->Options->IP Search Path, add ../../rtl/bus/qsys/.
/trunk/sys/altera/system.qsf
0,0 → 1,49
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2012 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 12.1 Build 177 11/07/2012 SJ Web Edition
# Date created = 15:58:54 February 03, 2013
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# system_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
 
 
set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CSEBA5U19A7
set_global_assignment -name TOP_LEVEL_ENTITY system
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:58:54 FEBRUARY 03, 2013"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
/trunk/sys/altera/cleanup.bat
0,0 → 1,2
rmdir /S /Q db incremental_db output .qsys_edit
del *.qws *.qdf
/trunk/sys/xilinx/system.sim.bat
0,0 → 1,12
rem build simulation project
simgen -p xc7z020clg484-2 -lang verilog -intstyle default -lp ../../sys/xilinx/../../ -lp ../../rtl/bus -msg simrun.lst -s isim -m behavioral ../../sys/xilinx/system.mhs -od .
 
rem compile and elaborate compiled models
vlogcomp -work work ../../sys/xilinx/system.tb.v -i ../../sys/xilinx/
fuse -incremental work.system_tb work.glbl -prj simulation/behavioral/system.prj -L xilinxcorelib_ver -L secureip -L unisims_ver -L unimacro_ver -o system.exe
 
rem run simulation
system.exe -gui -tclbatch simulation/behavioral/system_setup.tcl
 
pause
 
/trunk/sys/xilinx/cleanup.sh
0,0 → 1,3
rm -f -r etc hdl synthesis implementation simulation __xps data isim
rm -f *.log *.opt *.cmd *.make *.bxml *.bmm *.mss *.xmsgs *.wdb *.exe
 
/trunk/sys/xilinx/system.sim.sh
0,0 → 1,10
# build simulation project
simgen -p xc7z020clg484-2 -lang verilog -intstyle default -lp ../../sys/xilinx/../../ -lp ../../rtl/bus -msg simrun.lst -s isim -m behavioral ../../sys/xilinx/system.mhs -od .
 
# compile and elaborate compiled models
vlogcomp -work work ../../sys/xilinx/system.tb.v -i ../../sys/xilinx/
fuse -incremental work.system_tb work.glbl -prj simulation/behavioral/system.prj -L xilinxcorelib_ver -L secureip -L unisims_ver -L unimacro_ver -o system.exe
 
# run simulation
system.exe -gui -tclbatch simulation/behavioral/system_setup.tcl
 
/trunk/sys/xilinx/system.xmp
0,0 → 1,29
#Please do not modify this file by hand
XmpVersion: 14.3
VerMgmt: 14.3
IntStyle: default
Flow: ise
ModuleSearchPath: ../../rtl/bus/xps/pcores/ha1588_axi_v1_00_a/../../../
ModuleSearchPath: ../../
MHS File: system.mhs
Architecture: zynq
Device: xc7z020
Package: clg400
SpeedGrade: -2
UserCmd1:
UserCmd1Type: 0
UserCmd2:
UserCmd2Type: 0
GenSimTB: 0
SdkExportBmmBit: 1
SdkExportDir: SDK/SDK_Export
InsertNoPads: 0
WarnForEAArch: 1
HdlLang: Verilog
SimModel: BEHAVIORAL
ExternalMemSim: 0
UcfFile: data/system.ucf
EnableParTimingError: 1
ShowLicenseDialog: 1
BInfo:
LockAddr: ha1588_axi_0,C_S_AXI_REG_RNG00_BASEADDR
/trunk/sys/xilinx/system.wcfg
0,0 → 1,162
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="./isim.wdb" id="1" type="auto">
<top_modules>
<top_module name="glbl" />
<top_module name="system_tb" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="33" />
<wvobject fp_name="/system_tb/dut/ha1588_axi_0/ha1588_axi_0/ha1588_inst/rst" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rst</obj_property>
<obj_property name="ObjectShortName">rst</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/dut/ha1588_axi_0/ha1588_axi_0/ha1588_inst/clk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">clk</obj_property>
<obj_property name="ObjectShortName">clk</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/dut/ha1588_axi_0/ha1588_axi_0/ha1588_inst/wr_in" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">wr_in</obj_property>
<obj_property name="ObjectShortName">wr_in</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/dut/ha1588_axi_0/ha1588_axi_0/ha1588_inst/rd_in" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rd_in</obj_property>
<obj_property name="ObjectShortName">rd_in</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/dut/ha1588_axi_0/ha1588_axi_0/ha1588_inst/addr_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">addr_in[7:0]</obj_property>
<obj_property name="ObjectShortName">addr_in[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/dut/ha1588_axi_0/ha1588_axi_0/ha1588_inst/data_in" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data_in[31:0]</obj_property>
<obj_property name="ObjectShortName">data_in[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/dut/ha1588_axi_0/ha1588_axi_0/ha1588_inst/data_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">data_out[31:0]</obj_property>
<obj_property name="ObjectShortName">data_out[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="divider32" type="divider">
<obj_property name="label">system_tb</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/INTR" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">INTR</obj_property>
<obj_property name="ObjectShortName">INTR</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/CLK" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">CLK</obj_property>
<obj_property name="ObjectShortName">CLK</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/RST_N" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">RST_N</obj_property>
<obj_property name="ObjectShortName">RST_N</obj_property>
</wvobject>
<wvobject fp_name="divider33" type="divider">
<obj_property name="label">wrapper_axi</obj_property>
<obj_property name="DisplayName">label</obj_property>
<obj_property name="BkColor">128 128 255</obj_property>
<obj_property name="TextColor">230 230 230</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/dut/ha1588_axi_0/S_AXI_REG_ACLK" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">S_AXI_REG_ACLK</obj_property>
<obj_property name="ObjectShortName">S_AXI_REG_ACLK</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/dut/ha1588_axi_0/S_AXI_REG_ARESETN" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">S_AXI_REG_ARESETN</obj_property>
<obj_property name="ObjectShortName">S_AXI_REG_ARESETN</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/dut/ha1588_axi_0/S_AXI_REG_AWADDR" type="array" db_ref_id="1">
<obj_property name="ElementShortName">S_AXI_REG_AWADDR[31:0]</obj_property>
<obj_property name="ObjectShortName">S_AXI_REG_AWADDR[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/dut/ha1588_axi_0/S_AXI_REG_AWPROT" type="array" db_ref_id="1">
<obj_property name="ElementShortName">S_AXI_REG_AWPROT[2:0]</obj_property>
<obj_property name="ObjectShortName">S_AXI_REG_AWPROT[2:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/dut/ha1588_axi_0/S_AXI_REG_AWVALID" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">S_AXI_REG_AWVALID</obj_property>
<obj_property name="ObjectShortName">S_AXI_REG_AWVALID</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/dut/ha1588_axi_0/S_AXI_REG_AWREADY" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">S_AXI_REG_AWREADY</obj_property>
<obj_property name="ObjectShortName">S_AXI_REG_AWREADY</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/dut/ha1588_axi_0/S_AXI_REG_WDATA" type="array" db_ref_id="1">
<obj_property name="ElementShortName">S_AXI_REG_WDATA[31:0]</obj_property>
<obj_property name="ObjectShortName">S_AXI_REG_WDATA[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/dut/ha1588_axi_0/S_AXI_REG_WSTRB" type="array" db_ref_id="1">
<obj_property name="ElementShortName">S_AXI_REG_WSTRB[3:0]</obj_property>
<obj_property name="ObjectShortName">S_AXI_REG_WSTRB[3:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/dut/ha1588_axi_0/S_AXI_REG_WVALID" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">S_AXI_REG_WVALID</obj_property>
<obj_property name="ObjectShortName">S_AXI_REG_WVALID</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/dut/ha1588_axi_0/S_AXI_REG_WREADY" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">S_AXI_REG_WREADY</obj_property>
<obj_property name="ObjectShortName">S_AXI_REG_WREADY</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/dut/ha1588_axi_0/S_AXI_REG_BRESP" type="array" db_ref_id="1">
<obj_property name="ElementShortName">S_AXI_REG_BRESP[1:0]</obj_property>
<obj_property name="ObjectShortName">S_AXI_REG_BRESP[1:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/dut/ha1588_axi_0/S_AXI_REG_BVALID" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">S_AXI_REG_BVALID</obj_property>
<obj_property name="ObjectShortName">S_AXI_REG_BVALID</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/dut/ha1588_axi_0/S_AXI_REG_BREADY" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">S_AXI_REG_BREADY</obj_property>
<obj_property name="ObjectShortName">S_AXI_REG_BREADY</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/dut/ha1588_axi_0/S_AXI_REG_ARADDR" type="array" db_ref_id="1">
<obj_property name="ElementShortName">S_AXI_REG_ARADDR[31:0]</obj_property>
<obj_property name="ObjectShortName">S_AXI_REG_ARADDR[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/dut/ha1588_axi_0/S_AXI_REG_ARPROT" type="array" db_ref_id="1">
<obj_property name="ElementShortName">S_AXI_REG_ARPROT[2:0]</obj_property>
<obj_property name="ObjectShortName">S_AXI_REG_ARPROT[2:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/dut/ha1588_axi_0/S_AXI_REG_ARVALID" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">S_AXI_REG_ARVALID</obj_property>
<obj_property name="ObjectShortName">S_AXI_REG_ARVALID</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/dut/ha1588_axi_0/S_AXI_REG_ARREADY" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">S_AXI_REG_ARREADY</obj_property>
<obj_property name="ObjectShortName">S_AXI_REG_ARREADY</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/dut/ha1588_axi_0/S_AXI_REG_RDATA" type="array" db_ref_id="1">
<obj_property name="ElementShortName">S_AXI_REG_RDATA[31:0]</obj_property>
<obj_property name="ObjectShortName">S_AXI_REG_RDATA[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/dut/ha1588_axi_0/S_AXI_REG_RRESP" type="array" db_ref_id="1">
<obj_property name="ElementShortName">S_AXI_REG_RRESP[1:0]</obj_property>
<obj_property name="ObjectShortName">S_AXI_REG_RRESP[1:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/dut/ha1588_axi_0/S_AXI_REG_RVALID" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">S_AXI_REG_RVALID</obj_property>
<obj_property name="ObjectShortName">S_AXI_REG_RVALID</obj_property>
</wvobject>
<wvobject fp_name="/system_tb/dut/ha1588_axi_0/S_AXI_REG_RREADY" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">S_AXI_REG_RREADY</obj_property>
<obj_property name="ObjectShortName">S_AXI_REG_RREADY</obj_property>
</wvobject>
</wave_config>
/trunk/sys/xilinx/system.mhs
0,0 → 1,59
 
PARAMETER VERSION = 2.1.0
 
 
PORT ha1588_axi_0_rx_gmii_data_pin = ha1588_axi_0_rx_gmii_data, DIR = I, VEC = [7:0]
PORT ha1588_axi_0_rtc_time_ptp_ns_pin = ha1588_axi_0_rtc_time_ptp_ns, DIR = O, VEC = [31:0]
PORT ha1588_axi_0_tx_giga_mode_pin = ha1588_axi_0_tx_giga_mode, DIR = I
PORT ha1588_axi_0_rx_giga_mode_pin = ha1588_axi_0_rx_giga_mode, DIR = I
PORT ha1588_axi_0_rtc_time_one_pps_pin = ha1588_axi_0_rtc_time_one_pps, DIR = O
PORT ha1588_axi_0_tx_gmii_clk_pin = ha1588_axi_0_tx_gmii_clk, DIR = I
PORT ha1588_axi_0_rtc_time_ptp_sec_pin = ha1588_axi_0_rtc_time_ptp_sec, DIR = O, VEC = [47:0]
PORT ha1588_axi_0_rx_gmii_clk_pin = ha1588_axi_0_rx_gmii_clk, DIR = I
PORT ha1588_axi_0_tx_gmii_ctrl_pin = ha1588_axi_0_tx_gmii_ctrl, DIR = I
PORT ha1588_axi_0_rx_gmii_ctrl_pin = ha1588_axi_0_rx_gmii_ctrl, DIR = I
PORT ha1588_axi_0_tx_gmii_data_pin = ha1588_axi_0_tx_gmii_data, DIR = I, VEC = [7:0]
PORT INTR_OUT = ha1588_axi_0_INTR_OUT, DIR = O, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH
PORT INTR_IN = axi_lite_master_bfm_0_INTR_IN, DIR = I
PORT CLK = net_axi_lite_master_bfm_0_M_AXI_ACLK_pin, DIR = I, SIGIS = CLK
PORT RST_N = net_axi_interconnect_0_INTERCONNECT_ARESETN_pin, DIR = I, SIGIS = RST
 
 
BEGIN ha1588_axi
PARAMETER INSTANCE = ha1588_axi_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_S_AXI_REG_RNG00_BASEADDR = 0x00000000
PARAMETER C_S_AXI_REG_RNG00_HIGHADDR = 0x00000FFF
BUS_INTERFACE S_AXI_REG = axi_interconnect_0
PORT S_AXI_REG_ACLK = net_axi_lite_master_bfm_0_M_AXI_ACLK_pin
PORT rx_gmii_data = ha1588_axi_0_rx_gmii_data
PORT rtc_time_ptp_ns = ha1588_axi_0_rtc_time_ptp_ns
PORT tx_giga_mode = ha1588_axi_0_tx_giga_mode
PORT rx_giga_mode = ha1588_axi_0_rx_giga_mode
PORT rtc_time_one_pps = ha1588_axi_0_rtc_time_one_pps
PORT tx_gmii_clk = ha1588_axi_0_tx_gmii_clk
PORT rtc_time_ptp_sec = ha1588_axi_0_rtc_time_ptp_sec
PORT rx_gmii_clk = ha1588_axi_0_rx_gmii_clk
PORT tx_gmii_ctrl = ha1588_axi_0_tx_gmii_ctrl
PORT rx_gmii_ctrl = ha1588_axi_0_rx_gmii_ctrl
PORT tx_gmii_data = ha1588_axi_0_tx_gmii_data
PORT rtc_clk = net_axi_lite_master_bfm_0_M_AXI_ACLK_pin
PORT INTR_OUT = ha1588_axi_0_INTR_OUT
END
 
BEGIN axi_interconnect
PARAMETER INSTANCE = axi_interconnect_0
PARAMETER HW_VER = 1.06.a
PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
PORT INTERCONNECT_ACLK = net_axi_lite_master_bfm_0_M_AXI_ACLK_pin
PORT INTERCONNECT_ARESETN = net_axi_interconnect_0_INTERCONNECT_ARESETN_pin
END
 
BEGIN axi_lite_master_bfm
PARAMETER INSTANCE = axi_lite_master_bfm_0
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE M_AXI = axi_interconnect_0
PORT M_AXI_ACLK = net_axi_lite_master_bfm_0_M_AXI_ACLK_pin
PORT INTR_IN = axi_lite_master_bfm_0_INTR_IN
END
 
/trunk/sys/xilinx/pcores/axi_lite_master_bfm_v1_00_a/hdl/verilog/axi_lite_master_bfm.v
0,0 → 1,367
///////////////////////////////////////////////////////////////////////////////
//
// AXI4-Lite Master BFM
//
////////////////////////////////////////////////////////////////////////////
//
// Structure:
// axi_lite_master_bfm
//
// Last Update:
// 13/8/2012
////////////////////////////////////////////////////////////////////////////
 
`timescale 1ns/1ps
 
module axi_lite_master_bfm #
(
parameter integer C_M_AXI_ADDR_WIDTH = 32,
parameter integer C_M_AXI_DATA_WIDTH = 32
)
(
// System Signals
input wire M_AXI_ACLK,
input wire M_AXI_ARESETN,
 
// Master Interface Write Address
output wire [C_M_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [3-1:0] M_AXI_AWPROT,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
 
// Master Interface Write Data
output wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_M_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
 
// Master Interface Write Response
input wire [2-1:0] M_AXI_BRESP,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
 
// Master Interface Read Address
output wire [C_M_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [3-1:0] M_AXI_ARPROT,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
 
// Master Interface Read Data
input wire [C_M_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
 
// External Signals
input wire INTR_IN
);
 
// AXI4 signals
reg awvalid;
reg wvalid;
reg push_write;
reg pop_read;
reg arvalid;
reg rready;
reg bready;
reg [31:0] awaddr;
reg [31:0] wdata;
reg [31:0] araddr;
wire write_resp_error;
wire read_resp_error;
/////////////////
//I/O Connections
/////////////////
////////////////////
//Write Address (AW)
////////////////////
assign M_AXI_AWADDR = awaddr;
assign M_AXI_WDATA = wdata;
assign M_AXI_AWPROT = 3'h0;
assign M_AXI_AWVALID = awvalid;
 
///////////////
//Write Data(W)
///////////////
assign M_AXI_WVALID = wvalid;
 
//Set all byte strobes in this example
assign M_AXI_WSTRB = -1;
 
////////////////////
//Write Response (B)
////////////////////
assign M_AXI_BREADY = bready;
 
///////////////////
//Read Address (AR)
///////////////////
assign M_AXI_ARADDR = araddr;
assign M_AXI_ARVALID = arvalid;
assign M_AXI_ARPROT = 3'b0;
 
////////////////////////////
//Read and Read Response (R)
////////////////////////////
assign M_AXI_RREADY = rready;
///////////////////////
//Write Address Channel
///////////////////////
/*
The purpose of the write address channel is to request the address and
command information for the entire transaction. It is a single beat
of information.
Note for this example the awvalid/wvalid are asserted at the same
time, and then each is deasserted independent from each other.
This is a lower-performance, but simplier control scheme.
AXI VALID signals must be held active until accepted by the partner.
A data transfer is accepted by the slave when a master has
VALID data and the slave acknoledges it is also READY. While the master
is allowed to generated multiple, back-to-back requests by not
deasserting VALID, this design will add an extra rest cycle for
simplicity.
Since only one outstanding transaction is issued by the user design,
there will not be a collision between a new request and an accepted
request on the same clock cycle. Otherwise, an additional clause is
necessary.
*/
always @(posedge M_AXI_ACLK)
begin
//Only VALID signals must be deasserted during reset per AXI spec
//Consider inverting then registering active-low reset for higher fmax
if (M_AXI_ARESETN == 0 )
awvalid <= 1'b0;
 
//Address accepted by interconnect/slave
else if (M_AXI_AWREADY && awvalid)
awvalid <= 1'b0;
 
//Signal a new address/data command is available by user logic
else if (push_write)
awvalid <= 1'b1;
else
awvalid <= awvalid;
end
 
////////////////////
//Write Data Channel
////////////////////
/*
The write data channel is for transfering the actual data.
The data generation is specific to the example design, and
so only the WVALID/WREADY handshake is shown here
*/
always @(posedge M_AXI_ACLK)
begin
if (M_AXI_ARESETN == 0 )
wvalid <= 1'b0;
//Data accepted by interconnect/slave
else if (M_AXI_WREADY && wvalid)
wvalid <= 1'b0;
 
//Signal a new address/data command is available by user logic
else if (push_write)
wvalid <= 1'b1;
else
wvalid <= awvalid;
end
 
////////////////////////////
//Write Response (B) Channel
////////////////////////////
/*
The write response channel provides feedback that the write has committed
to memory. BREADY will occur after both the data and the write address
has arrived and been accepted by the slave, and can guarantee that no
other accesses launched afterwards will be able to be reordered before it.
The BRESP bit [1] is used indicate any errors from the interconnect or
slave for the entire write burst. This example will capture the error.
While not necessary per spec, it is advisable to reset READY signals in
case of differing reset latencies between master/slave.
*/
 
//Always accept write responses
always @(posedge M_AXI_ACLK)
begin
if (M_AXI_ARESETN == 0)
bready <= 1'b0;
else
bready <= 1'b1;
end
 
//Flag write errors
assign write_resp_error = bready & M_AXI_BVALID & M_AXI_BRESP[1];
//////////////////////
//Read Address Channel
//////////////////////
always @(posedge M_AXI_ACLK)
begin
if (M_AXI_ARESETN == 0 )
arvalid <= 1'b0;
else if (M_AXI_ARREADY && arvalid)
arvalid <= 1'b0;
else if (pop_read)
arvalid <= 1'b1;
else
arvalid <= arvalid;
end
 
//////////////////////////////////
//Read Data (and Response) Channel
//////////////////////////////////
/*
The Read Data channel returns the results of the read request
In this example the data checker is always able to accept
more data, so no need to throttle the RREADY signal.
While not necessary per spec, it is advisable to reset READY signals in
case of differing reset latencies between master/slave.
*/
always @(posedge M_AXI_ACLK)
begin
if (M_AXI_ARESETN == 0)
rready <= 1'b0;
else
rready <= 1'b1;
end
 
//Flag write errors
assign read_resp_error = rready & M_AXI_RVALID & M_AXI_RRESP[1];
 
////////////
//User Logic
////////////
 
///////////////////////
//Main write controller
///////////////////////
/*
By only issuing one request at a time, the control logic is
simplified.
Request a new write if:
-A command was not just submitted
-AW and W channels are both idle
-A new request was not requested last cycle
*/
/*always @(posedge M_AXI_ACLK)
begin
if (M_AXI_ARESETN == 0 )
begin
push_write <= 1'b0;
end
 
//Request new write
else if (~awvalid && ~wvalid && ~push_write)
begin
push_write <= 1'b1;
end
else
begin
push_write <= 1'b0; //Negate to generate a pulse
end
end */
 
//////////////////////
//Main read controller
//////////////////////
/*
By only issuing one request at a time, the control logic is
simplified.
 
Request a new read if:
-A command was not just submitted
-AR channel is idle
-A new request was not requested last cycle
*/
/*always @(posedge M_AXI_ACLK)
begin
if (M_AXI_ARESETN == 0 )
begin
pop_read <= 1'b0;
end
 
//Request new read
else if (~arvalid && ~pop_read)
begin
pop_read <= 1'b1;
end
else
begin
pop_read <= 1'b0; //Negate to generate a pulse
end
end */
 
 
task axi4_wr_req(input [31:0]addr, input [31:0]data);
integer i;
begin
$write("axi4_wr %08x", addr);
$write(" %08x", data);
for (i=0; i<1; i=i+1) @(posedge M_AXI_ACLK);
awaddr = addr;
wdata = data;
push_write = 1'b1;
for (i=0; i<1; i=i+1) @(posedge M_AXI_ACLK);
awaddr = addr;
wdata = data;
push_write = 1'b0;
for (i=0; i<1; i=i+1) @(posedge M_AXI_ACLK);
@(~awvalid && ~wvalid);
end
endtask
 
task axi4_rd_req(input [31:0]addr);
integer i;
begin
$write("axi4_rd %08x", addr);
for (i=0; i<1; i=i+1) @(posedge M_AXI_ACLK);
araddr = addr;
pop_read = 1'b1;
for (i=0; i<1; i=i+1) @(posedge M_AXI_ACLK);
araddr = addr;
pop_read = 1'b0;
for (i=0; i<1; i=i+1) @(posedge M_AXI_ACLK);
@(~arvalid);
end
endtask
 
task axi4_wr_ack;
begin
@(M_AXI_BVALID && bready);
@(posedge M_AXI_ACLK);
$write(" W_RESP: %08x\n", M_AXI_BRESP);
end
endtask
 
task axi4_rd_ack;
begin
@(M_AXI_RVALID && rready);
@(posedge M_AXI_ACLK);
$write(" %08x", M_AXI_RDATA);
$write(" R_RESP: %08x\n", M_AXI_RRESP);
end
endtask
 
initial begin
#300;
@(posedge M_AXI_ACLK);
axi4_wr_req(32'h00000004,32'h12345678);axi4_wr_ack;
axi4_rd_req(32'h00000004 );axi4_rd_ack;
end
 
endmodule
/trunk/sys/xilinx/pcores/axi_lite_master_bfm_v1_00_a/data/axi_lite_master_bfm_v2_1_0.pao
0,0 → 1,49
## -- DISCLAIMER OF LIABILITY
## --
## -- This file contains proprietary and confidential information of
## -- Xilinx, Inc. ("Xilinx"), that is distributed under a license
## -- from Xilinx, and may be used, copied and/or disclosed only
## -- pursuant to the terms of a valid license agreement with Xilinx.
## --
## -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
## -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
## -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
## -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
## -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
## -- does not warrant that functions included in the Materials will
## -- meet the requirements of Licensee, or that the operation of the
## -- Materials will be uninterrupted or error-free, or that defects
## -- in the Materials will be corrected. Furthermore, Xilinx does
## -- not warrant or make any representations regarding use, or the
## -- results of the use, of the Materials in terms of correctness,
## -- accuracy, reliability or otherwise.
## --
## -- Xilinx products are not designed or intended to be fail-safe,
## -- or for use in any application requiring fail-safe performance,
## -- such as life-support or safety devices or systems, Class III
## -- medical devices, nuclear facilities, applications related to
## -- the deployment of airbags, or any other applications that could
## -- lead to death, personal injury or severe property or
## -- environmental damage (individually and collectively, "critical
## -- applications"). Customer assumes the sole risk and liability
## -- of any use of Xilinx products in critical applications,
## -- subject only to applicable laws and regulations governing
## -- limitations on product liability.
## --
## -- Copyright 2009 Xilinx, Inc.
## -- All rights reserved.
## --
## -- This disclaimer and copyright notice must be retained as part
## -- of this file at all times.
##
###############################################################################
##
## axi_master_bfm.pao
##
## Peripheral Analyze Order File
##
##
###############################################################################
 
 
lib axi_lite_master_bfm_v1_00_a axi_lite_master_bfm.v verilog
/trunk/sys/xilinx/pcores/axi_lite_master_bfm_v1_00_a/data/axi_lite_master_bfm_v2_1_0.mpd
0,0 → 1,93
#-- DISCLAIMER OF LIABILITY
#--
#-- This file contains proprietary and confidential information of
#-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
#-- from Xilinx, and may be used, copied and/or disclosed only
#-- pursuant to the terms of a valid license agreement with Xilinx.
#--
#-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
#-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
#-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
#-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
#-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
#-- does not warrant that functions included in the Materials will
#-- meet the requirements of Licensee, or that the operation of the
#-- Materials will be uninterrupted or error-free, or that defects
#-- in the Materials will be corrected. Furthermore, Xilinx does
#-- not warrant or make any representations regarding use, or the
#-- results of the use, of the Materials in terms of correctness,
#-- accuracy, reliability or otherwise.
#--
#-- Xilinx products are not designed or intended to be fail-safe,
#-- or for use in any application requiring fail-safe performance,
#-- such as life-support or safety devices or systems, Class III
#-- medical devices, nuclear facilities, applications related to
#-- the deployment of airbags, or any other applications that could
#-- lead to death, personal injury or severe property or
#-- environmental damage (individually and collectively, "critical
#-- applications"). Customer assumes the sole risk and liability
#-- of any use of Xilinx products in critical applications,
#-- subject only to applicable laws and regulations governing
#-- limitations on product liability.
#--
#-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
#--
#-- This disclaimer and copyright notice must be retained as part
#-- of this file at all times.
#--
###################################################################
##
## Name : axi_lite_master_bfm
## Desc : Microprocessor Peripheral Description
## : Automatically generated by PsfUtility
##
###################################################################
 
BEGIN axi_lite_master_bfm
 
## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION STYLE = HDL
OPTION DESC = AXI Lite Master BFM
OPTION LONG_DESC = AXI4-Lite Master BFM
OPTION HDL = MIXED
OPTION RUN_NGCBUILD = FALSE
 
## Bus Interfaces
BUS_INTERFACE BUS = M_AXI, BUS_STD = AXI, BUS_TYPE = MASTER
 
## Generics for VHDL or Parameters for Verilog
PARAMETER C_M_AXI_ADDR_WIDTH = 32, DT = integer, ASSIGNMENT = CONSTANT, BUS = M_AXI
PARAMETER C_M_AXI_DATA_WIDTH = 32, DT = integer, ASSIGNMENT = CONSTANT, BUS = M_AXI
PARAMETER C_M_AXI_PROTOCOL = AXI4Lite, DT = string, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, BUS = M_AXI
PARAMETER C_M_AXI_SUPPORTS_READ = 1, DT = integer, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, BUS = M_AXI
PARAMETER C_M_AXI_SUPPORTS_WRITE = 1, DT = integer, ASSIGNMENT = CONSTANT, TYPE = NON_HDL, BUS = M_AXI
 
## Ports
PORT M_AXI_ACLK = "", BUS = M_AXI, DIR = I, SIGIS = CLK
PORT M_AXI_ARESETN = ARESETN, BUS = M_AXI, DIR = I, SIGIS = RST
PORT M_AXI_AWADDR = AWADDR, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_ADDR_WIDTH-1):0]
PORT M_AXI_AWPROT = AWPROT, BUS = M_AXI, DIR = O, VEC = [2:0]
PORT M_AXI_AWVALID = AWVALID, BUS = M_AXI, DIR = O
PORT M_AXI_AWREADY = AWREADY, BUS = M_AXI, DIR = I
PORT M_AXI_WDATA = WDATA, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_DATA_WIDTH-1):0]
PORT M_AXI_WSTRB = WSTRB, BUS = M_AXI, DIR = O, VEC = [((C_M_AXI_DATA_WIDTH/8) -1):0]
PORT M_AXI_WVALID = WVALID, BUS = M_AXI, DIR = O
PORT M_AXI_WREADY = WREADY, BUS = M_AXI, DIR = I
PORT M_AXI_BRESP = BRESP, BUS = M_AXI, DIR = I, VEC = [1:0]
PORT M_AXI_BVALID = BVALID, BUS = M_AXI, DIR = I
PORT M_AXI_BREADY = BREADY, BUS = M_AXI, DIR = O
PORT M_AXI_ARADDR = ARADDR, BUS = M_AXI, DIR = O, VEC = [(C_M_AXI_ADDR_WIDTH-1):0
PORT M_AXI_ARPROT = ARPROT, BUS = M_AXI, DIR = O, VEC = [2:0]
PORT M_AXI_ARVALID = ARVALID, BUS = M_AXI, DIR = O
PORT M_AXI_ARREADY = ARREADY, BUS = M_AXI, DIR = I
PORT M_AXI_RDATA = RDATA, BUS = M_AXI, DIR = I, VEC = [(C_M_AXI_DATA_WIDTH-1):0]
PORT M_AXI_RRESP = RRESP, BUS = M_AXI, DIR = I, VEC = [1:0]
PORT M_AXI_RVALID = RVALID, BUS = M_AXI, DIR = I
PORT M_AXI_RREADY = RREADY, BUS = M_AXI, DIR = O
 
## External Ports
PORT INTR_IN = "", DIR = I
 
END
/trunk/sys/xilinx/pcores/axi_lite_master_bfm_v1_00_a/data/axi_lite_master_bfm_v2_1_0.mui
0,0 → 1,107
<?xml version="1.0" encoding="ISO-8859-1"?>
 
<!--
###############################################################################
## DISCLAIMER OF LIABILITY
##
## This file contains proprietary and confidential information of
## Xilinx, Inc. ("Xilinx"), that is distributed under a license
## from Xilinx, and may be used, copied and/or disclosed only
## pursuant to the terms of a valid license agreement with Xilinx.
##
## XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
## ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
## EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
## LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
## MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
## does not warrant that functions included in the Materials will
## meet the requirements of Licensee, or that the operation of the
## Materials will be uninterrupted or error-free, or that defects
## in the Materials will be corrected. Furthermore, Xilinx does
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## results of the use, of the Materials in terms of correctness,
## accuracy, reliability or otherwise.
##
## Xilinx products are not designed or intended to be fail-safe,
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## applications"). Customer assumes the sole risk and liability
## of any use of Xilinx products in critical applications,
## subject only to applicable laws and regulations governing
## limitations on product liability.
##
## Copyright 2009 Xilinx, Inc.
## All rights reserved.
##
## This disclaimer and copyright notice must be retained as part
## of this file at all times.
##
###############################################################################
-->
 
<!DOCTYPE doc SYSTEM "../../ipdialog.dtd" [
<!-- -->
 
<!ENTITY C_M_AXI_ADDR_WIDTH '
<widget id="C_M_AXI_ADDR_WIDTH">
<key>C_M_AXI_ADDR_WIDTH</key>
<label>C_M_AXI_ADDR_WIDTH</label>
<tip></tip>
</widget>
'>
<!ENTITY C_M_AXI_DATA_WIDTH '
<widget id="C_M_AXI_DATA_WIDTH">
<key>C_M_AXI_DATA_WIDTH</key>
<label>C_M_AXI_DATA_WIDTH</label>
<tip></tip>
</widget>
'>
<!ENTITY C_M_AXI_PROTOCOL '
<widget id="C_M_AXI_PROTOCOL">
<key>C_M_AXI_PROTOCOL</key>
<label>C_M_AXI_PROTOCOL</label>
<tip></tip>
</widget>
'>
<!ENTITY C_M_AXI_SUPPORTS_READ '
<widget id="C_M_AXI_SUPPORTS_READ">
<key>C_M_AXI_SUPPORTS_READ</key>
<label>C_M_AXI_SUPPORTS_READ</label>
<tip></tip>
</widget>
'>
<!ENTITY C_M_AXI_SUPPORTS_WRITE '
<widget id="C_M_AXI_SUPPORTS_WRITE">
<key>C_M_AXI_SUPPORTS_WRITE</key>
<label>C_M_AXI_SUPPORTS_WRITE</label>
<tip></tip>
</widget>
'>
 
]>
 
<doc>
<view id="User">
<display>User</display>
<group id="Common">
<display>Common</display>
<item>&C_M_AXI_PROTOCOL;</item>
</group>
</view>
<view id="System">
<display>System</display>
<group id="AXI">
<display>AXI</display>
<item>&C_M_AXI_ADDR_WIDTH;</item>
<item>&C_M_AXI_DATA_WIDTH;</item>
<item>&C_M_AXI_SUPPORTS_READ;</item>
<item>&C_M_AXI_SUPPORTS_WRITE;</item>
</group>
</view>
</doc>
/trunk/sys/xilinx/ReadMe.txt
0,0 → 1,5
Run system.sim.bat to start ISim based system-level simuation.
 
Run system.xmp to edit the system-level connection.
 
An AXI4-Lite Master BFM is included under pcores. Edit the .v file under hdl to change the behavior of the master.
/trunk/sys/xilinx/cleanup.bat
0,0 → 1,3
rmdir /S /Q etc hdl synthesis implementation simulation __xps data isim
del *.log *.opt *.cmd *.make *.bxml *.bmm *.mss *.xmsgs *.wdb *.exe
 
/trunk/sys/xilinx/system.tb.v
0,0 → 1,62
//-----------------------------------------------------------------------------
// system.tb.v
//-----------------------------------------------------------------------------
 
`timescale 1 ps / 100 fs
 
// START USER CODE (Do not remove this line)
 
// User: Put your directives here. Code in this
// section will not be overwritten.
 
// END USER CODE (Do not remove this line)
 
module system_tb
(
);
 
// START USER CODE (Do not remove this line)
 
// User: Put your signals here. Code in this
// section will not be overwritten.
parameter PERIOD = 10000;
 
// END USER CODE (Do not remove this line)
 
 
// Internal signals
 
reg CLK;
reg RST_N;
wire INTR;
 
system
dut (
.RST_N ( RST_N ),
.CLK ( CLK ),
.INTR_IN ( INTR ),
.INTR_OUT ( INTR )
);
 
// START USER CODE (Do not remove this line)
 
// User: Put your stimulus here. Code in this
// section will not be overwritten.
initial begin
RST_N = 1'b0;
@(negedge CLK);
@(negedge CLK);
@(negedge CLK);
RST_N = 1'b1;
end
always begin
CLK = 1'b0;
#(PERIOD/2) CLK = 1'b1;
#(PERIOD/2);
end
// END USER CODE (Do not remove this line)
 
endmodule
 

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