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https://opencores.org/ocsvn/hf-risc/hf-risc/trunk
Subversion Repositories hf-risc
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- This comparison shows the changes necessary to convert path
/hf-risc
- from Rev 9 to Rev 10
- ↔ Reverse comparison
Rev 9 → Rev 10
/trunk/ucore/peripherals_busmux.vhd
20,7 → 20,8
-- *Memory is accessed in big endian mode. |
-- *No unaligned loads/stores. |
-- *No co-processor is implemented and all peripherals are memory mapped. |
-- *Loads and stores take 2 cycles with separated code/data memories or peripherals and 3 cycles otherwise. |
-- *Loads and stores take 1 cycle with separated code/data memories and 3 cycles otherwise. This version is organized |
-- as a Von Neumann machine, so there is only one memory interface that is shared betweeen code and data accesses. |
-- No load delay slots are needed in code. |
-- *Branches have a 1 cycle delay (not taken) or 3 cycle dalay (taken), including two branch delay slots. |
-- This is a side effect of the pipeline refill and memory access policy. All other instructions are single |