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/trunk/v04.05/op_encode.h
0,0 → 1,77
`include "lg_sel_encode.h"
`include "tst_encode.h"
 
// `ifndef _op_encode_h_
// `define _op_encode_h_
 
// misc - 16 x 16 x 16 = 4096 codes
localparam [MEM_DATA_W-1:0] op_nop = { 4'h0, 4'h0, 4'hx, 4'hx }; // do nothing (no pops either)
localparam [MEM_DATA_W-1:0] op_pop = { 4'h0, 4'h1, 4'hx, 4'hx }; // pop [7:0] none/one/some/all stacks
localparam [MEM_DATA_W-1:0] op_pgc = { 4'h0, 4'h4, 4'hx, 4'hx }; // A=PC read PC (unsigned)
localparam [MEM_DATA_W-1:0] op_lit_s = { 4'h0, 4'h8, 4'hx, 4'hx }; // A=mem(PC) literal data signed
localparam [MEM_DATA_W-1:0] op_lit_h = { 4'h0, 4'h9, 4'hx, 4'hx }; // A={mem(PC),A[lo]} literal data high
localparam [MEM_DATA_W-1:0] op_lit_u = { 4'h0, 4'ha, 4'hx, 4'hx }; // A=mem(PC) literal data unsigned
localparam [MEM_DATA_W-1:0] op_reg_rs = { 4'h0, 4'hc, 4'hx, 4'hx }; // A=reg(B) register read signed
localparam [MEM_DATA_W-1:0] op_reg_rh = { 4'h0, 4'hd, 4'hx, 4'hx }; // A={reg(B),A[lo]} register read high
localparam [MEM_DATA_W-1:0] op_reg_w = { 4'h0, 4'he, 4'hx, 4'hx }; // reg(B)=A[lo] register write
localparam [MEM_DATA_W-1:0] op_reg_wh = { 4'h0, 4'hf, 4'hx, 4'hx }; // reg(B)=A[hi] register write high
// logical & other - 16 x 16 x 16 = 4096 codes
localparam [MEM_DATA_W-1:0] op_cpy = { 4'h1, `lg_cpy, 4'hx, 4'hx }; // A=B copy
localparam [MEM_DATA_W-1:0] op_nsg = { 4'h1, `lg_nsg, 4'hx, 4'hx }; // A[MSB]=~B[MSB] invert sign
localparam [MEM_DATA_W-1:0] op_not = { 4'h1, `lg_not, 4'hx, 4'hx }; // A=~B logical NOT
localparam [MEM_DATA_W-1:0] op_flp = { 4'h1, `lg_flp, 4'hx, 4'hx }; // A=flip(B) flip bits end for end
localparam [MEM_DATA_W-1:0] op_lzc = { 4'h1, `lg_lzc, 4'hx, 4'hx }; // A=lzc(B) leading zero count
localparam [MEM_DATA_W-1:0] op_bra = { 4'h1, `lg_bra, 4'hx, 4'hx }; // A=&B logical AND bit reduction
localparam [MEM_DATA_W-1:0] op_bro = { 4'h1, `lg_bro, 4'hx, 4'hx }; // A=|B logical OR bit reduction
localparam [MEM_DATA_W-1:0] op_brx = { 4'h1, `lg_brx, 4'hx, 4'hx }; // A=^B logical XOR bit reduction
localparam [MEM_DATA_W-1:0] op_and = { 4'h1, `lg_and, 4'hx, 4'hx }; // A=A&B logical AND
localparam [MEM_DATA_W-1:0] op_orr = { 4'h1, `lg_orr, 4'hx, 4'hx }; // A=A|B logical OR
localparam [MEM_DATA_W-1:0] op_xor = { 4'h1, `lg_xor, 4'hx, 4'hx }; // A=A^B logical XOR
// arithmetic - 16 x 16 x 16 = 4096 codes
localparam [MEM_DATA_W-1:0] op_add = { 4'h2, 4'h0, 4'hx, 4'hx }; // A=A+B add
localparam [MEM_DATA_W-1:0] op_add_xs = { 4'h2, 4'h2, 4'hx, 4'hx }; // A=A+B add extended signed
localparam [MEM_DATA_W-1:0] op_add_xu = { 4'h2, 4'h3, 4'hx, 4'hx }; // A=A+B add extended unsigned
localparam [MEM_DATA_W-1:0] op_sub = { 4'h2, 4'h4, 4'hx, 4'hx }; // A=A-B subtract
localparam [MEM_DATA_W-1:0] op_sub_xs = { 4'h2, 4'h6, 4'hx, 4'hx }; // A=A-B subtract extended signed
localparam [MEM_DATA_W-1:0] op_sub_xu = { 4'h2, 4'h7, 4'hx, 4'hx }; // A=A-B subtract extended unsigned
localparam [MEM_DATA_W-1:0] op_mul = { 4'h2, 4'h8, 4'hx, 4'hx }; // A=A*B multiply
localparam [MEM_DATA_W-1:0] op_mul_xs = { 4'h2, 4'ha, 4'hx, 4'hx }; // A=A*B multiply extended signed
localparam [MEM_DATA_W-1:0] op_mul_xu = { 4'h2, 4'hb, 4'hx, 4'hx }; // A=A*B multiply extended unsigned
localparam [MEM_DATA_W-1:0] op_shl_s = { 4'h2, 4'hc, 4'hx, 4'hx }; // A=A<<<B shift left A signed
localparam [MEM_DATA_W-1:0] op_shl_u = { 4'h2, 4'hd, 4'hx, 4'hx }; // A=A<<B shift left A unsigned
localparam [MEM_DATA_W-1:0] op_pow = { 4'h2, 4'he, 4'hx, 4'hx }; // A=1<<B power of 2
// branching - 16 x 16 x 16 = 4096 codes
localparam [MEM_DATA_W-1:0] op_jmp_z = { 4'h3, 2'b00, `z, 4'hx, 4'hx }; // PC=(A?0)?PC+B jump zero conditional
localparam [MEM_DATA_W-1:0] op_jmp_nz = { 4'h3, 2'b00, `nz, 4'hx, 4'hx };
localparam [MEM_DATA_W-1:0] op_jmp_lz = { 4'h3, 2'b00, `lz, 4'hx, 4'hx };
localparam [MEM_DATA_W-1:0] op_jmp_nlz = { 4'h3, 2'b00, `nlz, 4'hx, 4'hx };
localparam [MEM_DATA_W-1:0] op_jmp = { 4'h3, 4'hc, 4'hx, 4'hx }; // PC=PC+B jump unconditional
localparam [MEM_DATA_W-1:0] op_gto = { 4'h3, 4'hd, 4'hx, 4'hx }; // PC=B go to unconditional
localparam [MEM_DATA_W-1:0] op_gsb = { 4'h3, 4'he, 4'hx, 4'hx }; // PC=B,A=PC subroutine call unconditional
// immediate memory access - 4 x 16 x 16 x 16 = 16384 codes
localparam [MEM_DATA_W-1:0] op_mem_irs = { 4'h4, 4'hx, 4'hx, 4'hx }; // A=mem(B+I) memory read signed
localparam [MEM_DATA_W-1:0] op_mem_irh = { 4'h5, 4'hx, 4'hx, 4'hx }; // A={mem(B+I),A[lo]} memory read high
localparam [MEM_DATA_W-1:0] op_mem_iw = { 4'h6, 4'hx, 4'hx, 4'hx }; // mem(B+I)=A[lo] memory write
localparam [MEM_DATA_W-1:0] op_mem_iwh = { 4'h7, 4'hx, 4'hx, 4'hx }; // mem(B+I)=A[hi] memory write high
// immediate conditional (A?B) jumps - 6 x 16 x 16 x 16 = 24576 codes
localparam [MEM_DATA_W-1:0] op_jmp_ie = { `e, 4'hx, 4'hx, 4'hx }; // PC=(A?B)?PC+I jump immediate conditional
localparam [MEM_DATA_W-1:0] op_jmp_ine = { `ne, 4'hx, 4'hx, 4'hx };
localparam [MEM_DATA_W-1:0] op_jmp_ils = { `ls, 4'hx, 4'hx, 4'hx };
localparam [MEM_DATA_W-1:0] op_jmp_inls = { `nls, 4'hx, 4'hx, 4'hx };
localparam [MEM_DATA_W-1:0] op_jmp_ilu = { `lu, 4'hx, 4'hx, 4'hx };
localparam [MEM_DATA_W-1:0] op_jmp_inlu = { `nlu, 4'hx, 4'hx, 4'hx };
// immediate conditional (A?0) jumps - 4 x 64 x 16 = 4096 codes
localparam [MEM_DATA_W-1:0] op_jmp_iz = { 4'he, `z, 6'bxxxxxx, 4'hx }; // PC=(A?0)?PC+I jump immediate conditional
localparam [MEM_DATA_W-1:0] op_jmp_inz = { 4'he, `nz, 6'bxxxxxx, 4'hx };
localparam [MEM_DATA_W-1:0] op_jmp_ilz = { 4'he, `lz, 6'bxxxxxx, 4'hx };
localparam [MEM_DATA_W-1:0] op_jmp_inlz = { 4'he, `nlz, 6'bxxxxxx, 4'hx };
// immediate data - 1 x 64 x 16 = 1024 codes
localparam [MEM_DATA_W-1:0] op_dat_is = { 4'hf, 2'b00, 6'bxxxxxx, 4'hx }; // A=I data immediate signed
// immediate add - 1 x 64 x 16 = 1024 codes
localparam [MEM_DATA_W-1:0] op_add_is = { 4'hf, 2'b01, 6'bxxxxxx, 4'hx }; // A=A+I add immediate signed
// immediate shifts - 2 x 64 x 16 = 2048 codes
localparam [MEM_DATA_W-1:0] op_shl_is = { 4'hf, 2'b10, 6'bxxxxxx, 4'hx }; // A=A<<<I shift left A signed
localparam [MEM_DATA_W-1:0] op_psu_i = { 4'hf, 2'b11, 6'bxxxxxx, 4'hx }; // A=1<<I power of 2; A=A<<I shift A unsigned
 
// `endif // _op_encode_h_
 
/trunk/v04.05/alu_mult_shift.v
0,0 → 1,223
/*
--------------------------------------------------------------------------------
 
Module : alu_mult_shift
 
--------------------------------------------------------------------------------
 
Function:
- Multiply & shift unit for a processor ALU.
 
Instantiates:
- functions.h (clog2)
- (1x) alu_multiply.v
- (1x) pipe.v (debug mode only)
- (4x) pipe.v
 
Notes:
- I/O optionally registered.
- 5 stage pipeline w/ 4 mid registers (not counting I/O registering).
- (pow=0 & shl=0) gives unsigned (sgn=0) and signed (sgn=1) A*B.
- (pow=0 & shl=1) gives A unsigned (sgn=0) and A signed (sgn=1) A<<B.
- (pow=1 & shl=0) gives 1<<B (sign=x).
- (pow=1 & shl=1) and (B>=0) gives 1<<B, (B<0) gives A<<B (A signed & unsigned).
- Debug mode for comparison to native signed multiplication, only use for
simulation as it consumes resources and negatively impacts top speed.
 
--------------------------------------------------------------------------------
*/
 
module alu_mult_shift
#(
parameter integer REGS_IN = 1, // in register option
parameter integer REGS_OUT = 1, // out register option
parameter integer DATA_W = 32, // data width
parameter integer DEBUG_MODE = 0 // 1=debug mode; 0=normal mode
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// control I/O
input wire sgn_i, // 1=signed
input wire ext_i, // 1=extended result
input wire shl_i, // 1=shift left
input wire pow_i, // 1=power of 2
// data I/O
input wire [DATA_W-1:0] a_i, // operand
input wire [DATA_W-1:0] b_i, // operand
output wire [DATA_W-1:0] result_o, // result
// debug
output wire debug_o // 1=bad match
);
 
/*
----------------------
-- internal signals --
----------------------
*/
`include "functions.h" // for clog2()
localparam integer SH_SEL_W = clog2( DATA_W );
localparam integer ZSX_W = DATA_W+1; // +1 extra bit
localparam integer DBL_W = DATA_W*2; // double width
//
wire [DATA_W-1:0] a, b;
wire ext, pow, shl, sgn;
wire b_neg;
wire [DATA_W-1:0] b_pow;
wire [ZSX_W-1:0] a_sex, b_sex;
reg [ZSX_W-1:0] a_mux, b_mux;
reg ext_mux;
wire ext_mux_r;
wire [DBL_W-1:0] res_dbl;
reg [DATA_W-1:0] result;
 
 
/*
================
== code start ==
================
*/
 
 
// optional input data regs
pipe
#(
.DEPTH ( REGS_IN ),
.WIDTH ( DATA_W+DATA_W ),
.RESET_VAL ( 0 )
)
in_data_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { b_i, a_i } ),
.data_o ( { b, a } )
);
 
// optional input control regs
pipe
#(
.DEPTH ( REGS_IN ),
.WIDTH ( 4 ),
.RESET_VAL ( 0 )
)
in_ctrl_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { ext_i, pow_i, shl_i, sgn_i } ),
.data_o ( { ext, pow, shl, sgn } )
);
 
 
// some results pre-mux
assign a_sex = { a[DATA_W-1], a };
assign b_sex = { b[DATA_W-1], b };
assign b_pow = 1'b1 << b[SH_SEL_W-1:0];
assign b_neg = b[DATA_W-1];
 
 
// mux inputs and extended result selector
always @ ( * ) begin
case ( { pow, shl, sgn } )
'b000 : begin // unsigned multiply
a_mux <= a;
b_mux <= b;
ext_mux <= ext;
end
'b001 : begin // signed multiply
a_mux <= a_sex;
b_mux <= b_sex;
ext_mux <= ext;
end
'b010 : begin // unsigned shift
a_mux <= a;
b_mux <= b_pow;
ext_mux <= b_neg;
end
'b011 : begin // signed shift
a_mux <= a_sex;
b_mux <= b_pow;
ext_mux <= b_neg;
end
'b100, 'b101 : begin // pow (sign is don't care)
a_mux <= 1'b1;
b_mux <= b_pow;
ext_mux <= 1'b0; // modulo rather than zero for negative shift values
end
'b110 : begin // pow (0,+b) | unsigned shift (-b)
a_mux <= ( b_neg ) ? a : 1'b1;
b_mux <= b_pow;
ext_mux <= b_neg;
end
'b111 : begin // pow (0,+b) | signed shift (-b)
a_mux <= ( b_neg ) ? a_sex : 1'b1;
b_mux <= b_pow;
ext_mux <= b_neg;
end
endcase
end
 
 
// signed multiplier (4 registers deep)
alu_multiply
#(
.DATA_W ( ZSX_W ),
.DEBUG_MODE ( DEBUG_MODE )
)
alu_multiply
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.a_i ( a_mux ),
.b_i ( b_mux ),
.result_o ( res_dbl ),
.debug_o ( debug_o )
);
 
 
// pipeline extended result selector to match multiply
pipe
#(
.DEPTH ( 4 ),
.WIDTH ( 1 ),
.RESET_VAL ( 0 )
)
regs_ext
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( ext_mux ),
.data_o ( ext_mux_r )
);
 
 
// multiplex
always @ ( * ) begin
case ( ext_mux_r )
'b1 : result <= res_dbl[DBL_W-1:DATA_W];
default : result <= res_dbl[DATA_W-1:0];
endcase
end
 
// optional output regs
pipe
#(
.DEPTH ( REGS_OUT ),
.WIDTH ( DATA_W ),
.RESET_VAL ( 0 )
)
out_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( result ),
.data_o ( result_o )
);
 
 
endmodule
/trunk/v04.05/boot_code.h
0,0 → 1,172
/*
--------------------------------------------------------------------------------
 
Module : boot_code.h
 
--------------------------------------------------------------------------------
 
Function:
- Boot code for a processor core.
 
Instantiates:
- Nothing.
 
Notes:
- For testing (@ core.v):
CLR_BASE = 'h0;
CLR_SPAN = 2; // gives 4 instructions
INTR_BASE = 'h20; // 'd32
INTR_SPAN = 2; // gives 4 instructions
 
 
--------------------------------------------------------------------------------
*/
 
/*
--------------------
-- external stuff --
--------------------
*/
`include "boot_code_defs.h"
/*
----------------------------------------
-- initialize: fill with default data --
----------------------------------------
*/
integer i;
 
initial begin
 
/* // fill with nop (some compilers need this)
for ( i = 0; i < CAPACITY; i = i+1 ) begin
ram[i] = { `nop, `__, `__ };
end
*/
 
/*
---------------
-- boot code --
---------------
*/
 
 
// Thread 0 : do LED PWM action
// All other threads : loop forever
 
///////////////
// clr space //
///////////////
 
// thread 0
i='h00; ram[i] = { `lit_u, `__, `s2 }; // s2=dat
i=i+1; ram[i] = 16'h0100 ; // addr
i=i+1; ram[i] = { `gto, `P2, `__ }; // goto, pop s2 (addr)
// and the rest
i='h04; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h08; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h0c; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h10; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h14; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h18; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h1c; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
 
////////////////
// intr space //
////////////////
 
///////////////////////
// code & data space //
///////////////////////
 
/*
// simple binary count LED display
i='h100; ram[i] = { `dat_is, 6'd0, `s0 }; // s0=0
i=i+1; ram[i] = { `dat_is, `IO_LO, `s1 }; // s1=reg addr
// loop start
i=i+1; ram[i] = { `add_is, 6'd1, `P0 }; // s0++
i=i+1; ram[i] = { `psu_i, -6'd20, `s0 }; // s0=s0>>20
i=i+1; ram[i] = { `reg_w, `s1, `P0 }; // (s1)=s0, pop s0
i=i+1; ram[i] = { `jmp_ie, -4'd4, `s0, `s0 }; // loop forever
// loop end
*/
 
/*
// simple sequential LED display
i='h100; ram[i] = { `dat_is, 6'd0, `s0 }; // s0=0
i=i+1; ram[i] = { `dat_is, `IO_LO, `s1 }; // s1=reg addr
// loop start
i=i+1; ram[i] = { `add_is, 6'd1, `P0 }; // s0++
i=i+1; ram[i] = { `shl_is, 6'd10, `s0 }; // s0=s0<<10
i=i+1; ram[i] = { `psu_i, -6'd30, `P0 }; // s0=s0>>30, pop s0
i=i+1; ram[i] = { `pow, `P0, `s0 }; // s0=1<<s0, pop s0
i=i+1; ram[i] = { `reg_w, `s1, `P0 }; // (s1)=s0, pop s0
i=i+1; ram[i] = { `jmp_ie, -4'd6, `s0, `s0 }; // loop forever
// loop end
*/
 
/*
// sequential LED display w/ PWM - moving "dark spot"
i='h100; ram[i] = { `dat_is, 6'd0, `s0 }; // s0=0
i=i+1; ram[i] = { `dat_is, `IO_LO, `s1 }; // s1=reg addr
i=i+1; ram[i] = { `dat_is, 6'd0, `s2 }; // s2=pwm
// loop start
i=i+1; ram[i] = { `shl_is, 6'd13, `s0 }; // s0=s0<<13 - isolate decimal
i=i+1; ram[i] = { `add, `P0, `P2 }; // s2+=s0, pop s0 - add to pwm counter
i=i+1; ram[i] = { `add_is, 6'd1, `P0 }; // s0++ - get next value
i=i+1; ram[i] = { `shl_is, 6'd13, `s0 }; // s0=s0<<13 - isolate decimal
i=i+1; ram[i] = { `add_xu, `P0, `s2 }; // s2=s2+s0, pop s0 - see if it will cause pwm counter overflow
i=i+1; ram[i] = { `shl_is, 6'd19, `P2 }; // s2<<=19 - shift up to ones place
i=i+1; ram[i] = { `add, `P2, `s0 }; // s0+=s2, pop s2 - add pwm bit
i=i+1; ram[i] = { `shl_is, 6'd11, `P0 }; // s0<<=11 - isolate integer
i=i+1; ram[i] = { `psu_i, -6'd30, `P0 }; // s0>>=30
i=i+1; ram[i] = { `pow, `s0, `P0 }; // s0=1<<s0, pop s0 - do one hot
i=i+1; ram[i] = { `not, `s0, `P0 }; // s0~=s0 - invert
i=i+1; ram[i] = { `reg_w, `s1, `P0 }; // (s1)=s0, pop s0
i=i+1; ram[i] = { `jmp_inz, -6'd13, `s1 }; // loop forever
// loop end
*/
 
// "bouncing ball" 4 LED display w/ PWM
//
// s0 : sin
// s1 : cos
// s2 : alpha (attenuation factor = speed)
// s3 : rectified sin, val, one-hot(val)
// s4 :
// s5 : pwm counter
// s6 :
// s7 : i/o register address
i='h100; ram[i] = { `dat_is, 6'd0, `s0 }; // s0=0 (sin init)
i=i+1; ram[i] = { `lit_u, `__, `s1 }; // s1=0x3000,0000 (cos init)
i=i+1; ram[i] = 16'h3000 ; //
i=i+1; ram[i] = { `shl_is, 6'd16, `P1 }; //
i=i+1; ram[i] = { `lit_u, `__, `s2 }; // s2=0x3000 (alpha init)
i=i+1; ram[i] = 16'h3000 ; //
i=i+1; ram[i] = { `dat_is, 6'd0, `s5 }; // s5=0 (pwm init)
i=i+1; ram[i] = { `dat_is, `IO_LO, `s7 }; // s7=reg addr
// loop start
// sin & cos
i=i+1; ram[i] = { `mul_xs, `s2, `s0 }; // s0=s0*s2 (sin*alpha)
i=i+1; ram[i] = { `sub, `P0, `P1 }; // s1-=s0 (cos-=sin*alpha)
i=i+1; ram[i] = { `mul_xs, `s2, `s1 }; // s1=s1*s2 (cos*alpha)
i=i+1; ram[i] = { `add, `P1, `P0 }; // s0-=s1 (sin+=cos*alpha)
// |sin|
i=i+1; ram[i] = { `cpy, `s0, `s3 }; // s3=s0
i=i+1; ram[i] = { `jmp_inlz, 6'd1, `s3 }; // (s3!<0) ? jmp +1
i=i+1; ram[i] = { `not, `s3, `P3 }; // s3~=s3
// decimal( |sin| ) + pwm to update, + pwm to get ofl
i=i+1; ram[i] = { `shl_is, 6'd4, `s3 }; // s3=s3<<4
i=i+1; ram[i] = { `add, `s3, `P5 }; // s5+=s3 (update pwm count)
i=i+1; ram[i] = { `add_xu, `P3, `s5 }; // s5=s5+s3, pop s3 (get pwm ofl)
// one-hot( int( |sin| ) + pwm ofl )
i=i+1; ram[i] = { `shl_is, -6'd28, `P3 }; // s3>>=28
i=i+1; ram[i] = { `add, `P5, `P3 }; // s3+=s5, pop s5 (add pwm ofl)
i=i+1; ram[i] = { `pow, `s3, `P3 }; // s3=1<<s3, pop s3 (one-hot)
// output
i=i+1; ram[i] = { `reg_w, `s7, `P3 }; // (s7)=s3, pop s3
i=i+1; ram[i] = { `jmp_inz, -6'd15, `s7 }; // loop forever
// loop end
end
/trunk/v04.05/alu_multiply.v
0,0 → 1,155
/*
--------------------------------------------------------------------------------
 
Module : alu_multiply
 
--------------------------------------------------------------------------------
 
Function:
- Signed multiply unit for a processor ALU.
 
Instantiates:
- (1x) pipe.v (debug mode only)
 
Notes:
- 3 stage 4 register pipeline.
- Multiply stage I/O registers are likely free (part of multiplier fabric).
- Debug mode for comparison to native signed multiplication, only use for
simulation / verification as it consumes resources and negatively impacts
top speed.
 
--------------------------------------------------------------------------------
*/
 
module alu_multiply
#(
parameter integer DATA_W = 33, // data width
parameter integer DEBUG_MODE = 0 // 1=debug mode; 0=normal mode
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// data I/O
input wire [DATA_W-1:0] a_i, // operand
input wire [DATA_W-1:0] b_i, // operand
output reg [DATA_W*2-1:0] result_o, // = ( a_i * b_i )
// debug
output wire debug_o // 1=bad match
);
 
/*
----------------------
-- internal signals --
----------------------
*/
localparam integer HI_W = DATA_W/2; // 16
localparam integer LO_W = DATA_W-HI_W; // 17
localparam integer MULT_W = LO_W*2; // 34
localparam integer DBL_W = DATA_W*2; // 66
//
reg signed [DATA_W-1:0] a, b;
wire signed [HI_W-1:0] a_hi, b_hi;
wire signed [LO_W:0] a_lo_ze, b_lo_ze; // 35 (extra zero MSB)
reg signed [MULT_W-1:0] mult_hi_hi, mult_hi_lo, mult_lo_hi, mult_lo_lo;
reg signed [DBL_W-1:0] inner_sum, outer_cat;
 
 
/*
================
== code start ==
================
*/
 
 
// input registering (likely free)
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
a <= 'b0;
b <= 'b0;
end else begin
a <= a_i;
b <= b_i;
end
end
// select & extend inputs
assign a_hi = a[DATA_W-1:LO_W];
assign b_hi = b[DATA_W-1:LO_W];
assign a_lo_ze = { 1'b0, a[LO_W-1:0] };
assign b_lo_ze = { 1'b0, b[LO_W-1:0] };
 
// do all multiplies & register (registers are likely free)
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
mult_hi_hi <= 'b0;
mult_hi_lo <= 'b0;
mult_lo_hi <= 'b0;
mult_lo_lo <= 'b0;
end else begin
mult_hi_hi <= a_hi * b_hi;
mult_hi_lo <= a_hi * b_lo_ze;
mult_lo_hi <= a_lo_ze * b_hi;
mult_lo_lo <= a_lo_ze * b_lo_ze;
end
end
 
// add and shift inner terms, concatenate outer terms, register
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
inner_sum <= 'b0;
outer_cat <= 'b0;
end else begin
inner_sum <= ( mult_hi_lo + mult_lo_hi ) << LO_W;
outer_cat <= { mult_hi_hi[HI_W*2-1:0], mult_lo_lo };
end
end
 
// final add & register
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
result_o <= 'b0;
end else begin
result_o <= outer_cat + inner_sum;
end
end
 
 
// optional debug mode
generate
if ( DEBUG_MODE ) begin
wire signed [DBL_W-1:0] debug_mult, debug_mult_r;
reg debug;
assign debug_mult = a * b;
// delay regs
pipe
#(
.REGS ( 3 ),
.DATA_W ( DBL_W ),
.RESET_VAL ( 0 )
)
regs_debug
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( debug_mult ),
.data_o ( debug_mult_r )
);
// compare & register
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
debug <= 'b0;
end else begin
debug <= ( debug_mult_r != result_o );
end
end
//
assign debug_o = debug;
end else begin
assign debug_o = 'b0;
end
endgenerate
 
 
endmodule
/trunk/v04.05/boot_code_defs.h
0,0 → 1,100
`include "reg_set_addr.h"
`include "op_encode.h"
 
localparam IM_W = 6;
 
// defines that make programming code more human readable
`define __ 4'h0
`define s0 4'h0
`define s1 4'h1
`define s2 4'h2
`define s3 4'h3
`define s4 4'h4
`define s5 4'h5
`define s6 4'h6
`define s7 4'h7
`define P0 4'h8
`define P1 4'h9
`define P2 4'ha
`define P3 4'hb
`define P4 4'hc
`define P5 4'hd
`define P6 4'he
`define P7 4'hf
//
`define nop op_nop[DATA_W-1:8]
`define pop op_pop[DATA_W-1:8]
`define pgc op_pgc[DATA_W-1:8]
`define lit_s op_lit_s[DATA_W-1:8]
`define lit_h op_lit_h[DATA_W-1:8]
`define lit_u op_lit_u[DATA_W-1:8]
`define reg_rs op_reg_rs[DATA_W-1:8]
`define reg_rh op_reg_rh[DATA_W-1:8]
`define reg_w op_reg_w[DATA_W-1:8]
`define reg_wh op_reg_wh[DATA_W-1:8]
//
`define cpy op_cpy[DATA_W-1:8]
`define nsg op_nsg[DATA_W-1:8]
`define not op_not[DATA_W-1:8]
`define flp op_flp[DATA_W-1:8]
`define lzc op_lzc[DATA_W-1:8]
`define bra op_bra[DATA_W-1:8]
`define bro op_bro[DATA_W-1:8]
`define brx op_brx[DATA_W-1:8]
`define and op_and[DATA_W-1:8]
`define orr op_orr[DATA_W-1:8]
`define xor op_xor[DATA_W-1:8]
//
`define add op_add[DATA_W-1:8]
`define add_xs op_add_xs[DATA_W-1:8]
`define add_xu op_add_xu[DATA_W-1:8]
`define sub op_sub[DATA_W-1:8]
`define sub_xs op_sub_xs[DATA_W-1:8]
`define sub_xu op_sub_xu[DATA_W-1:8]
`define mul op_mul[DATA_W-1:8]
`define mul_xs op_mul_xs[DATA_W-1:8]
`define mul_xu op_mul_xu[DATA_W-1:8]
`define shl_s op_shl_s[DATA_W-1:8]
`define shl_u op_shl_u[DATA_W-1:8]
`define pow op_pow[DATA_W-1:8]
//
`define jmp_z op_jmp_z[DATA_W-1:8]
`define jmp_nz op_jmp_nz[DATA_W-1:8]
`define jmp_lz op_jmp_lz[DATA_W-1:8]
`define jmp_nlz op_jmp_nlz[DATA_W-1:8]
`define jmp op_jmp[DATA_W-1:8]
`define gto op_gto[DATA_W-1:8]
`define gsb op_gsb[DATA_W-1:8]
//
`define mem_irs op_mem_irs[DATA_W-1:12]
`define mem_irh op_mem_irh[DATA_W-1:12]
`define mem_iw op_mem_iw[DATA_W-1:12]
`define mem_iwh op_mem_iwh[DATA_W-1:12]
//
`define jmp_ie op_jmp_ie[DATA_W-1:12]
`define jmp_ine op_jmp_ine[DATA_W-1:12]
`define jmp_ils op_jmp_ils[DATA_W-1:12]
`define jmp_inls op_jmp_inls[DATA_W-1:12]
`define jmp_ilu op_jmp_ilu[DATA_W-1:12]
`define jmp_inlu op_jmp_inlu[DATA_W-1:12]
//
`define jmp_iz op_jmp_iz[DATA_W-1:10]
`define jmp_inz op_jmp_inz[DATA_W-1:10]
`define jmp_ilz op_jmp_ilz[DATA_W-1:10]
`define jmp_inlz op_jmp_inlz[DATA_W-1:10]
//
`define dat_is op_dat_is[DATA_W-1:10]
`define add_is op_add_is[DATA_W-1:10]
`define shl_is op_shl_is[DATA_W-1:10]
`define psu_i op_psu_i[DATA_W-1:10]
//
`define VER VER_ADDR[IM_W-1:0]
`define THRD_ID THRD_ID_ADDR[IM_W-1:0]
`define CLR CLR_ADDR[IM_W-1:0]
`define INTR_EN INTR_EN_ADDR[IM_W-1:0]
`define OP_ER OP_ER_ADDR[IM_W-1:0]
`define STK_ER STK_ER_ADDR[IM_W-1:0]
`define IO_LO IO_LO_ADDR[IM_W-1:0]
`define IO_HI IO_HI_ADDR[IM_W-1:0]
`define UART_RX UART_RX_ADDR[IM_W-1:0]
`define UART_TX UART_TX_ADDR[IM_W-1:0]
/trunk/v04.05/dds_static.v
0,0 → 1,64
/*
--------------------------------------------------------------------------------
 
Module: dds_static.v
 
Function:
- Forms a simple static DDS source.
 
Instantiates:
- Nothing.
 
Notes:
- Employs phase accumulation, phase increment is multiplication factor.
- clk_o = clk_i * INC_VAL * 2^-ACCUM_W
- Output is roughly square, long-term avg of duty cycle is generally 50/50.
- For correct operation, INC_VAL < 2^(ACCUM_W-1).
--------------------------------------------------------------------------------
*/
 
module dds_static
#(
parameter integer ACCUM_W = 8, // phase accumulator width (bits)
parameter [ACCUM_W-1:0] INC_VAL = 8 // phase increment value
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async reset, active high
//
output wire clk_o // output clock
);
 
 
/*
----------------------
-- internal signals --
----------------------
*/
reg [ACCUM_W-1:0] accum;
 
 
 
/*
================
== code start ==
================
*/
 
// accumulate
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
accum <= 'b0;
end else begin
accum <= accum + INC_VAL;
end
end
 
// assign output
assign clk_o = accum[ACCUM_W-1];
 
endmodule
/trunk/v04.05/stacks_mux.v
0,0 → 1,121
/*
--------------------------------------------------------------------------------
 
Module : stacks_mux.v
 
--------------------------------------------------------------------------------
 
Function:
- Output multiplexer for processor stacks.
 
Instantiates:
- (1x) pipe.v
 
Notes:
- Purely combinatorial.
 
--------------------------------------------------------------------------------
*/
 
module stacks_mux
#(
parameter integer DATA_W = 32, // data width
parameter integer ADDR_W = 16, // address width (bits)
parameter integer IM_W = 8, // immediate width
parameter integer STK_W = 3 // stack selector width
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// control I/O
input wire [STK_W-1:0] data_sel_a_i, // stack selector
input wire [STK_W-1:0] data_sel_b_i, // stack selector
input wire [STK_W-1:0] addr_sel_b_i, // stack selector
input wire imda_i, // 1=immediate data
input wire imad_i, // 1=immediate address
// data I/O
input wire [DATA_W-1:0] pop_data0_i, // stack data
input wire [DATA_W-1:0] pop_data1_i, // stack data
input wire [DATA_W-1:0] pop_data2_i, // stack data
input wire [DATA_W-1:0] pop_data3_i, // stack data
input wire [DATA_W-1:0] pop_data4_i, // stack data
input wire [DATA_W-1:0] pop_data5_i, // stack data
input wire [DATA_W-1:0] pop_data6_i, // stack data
input wire [DATA_W-1:0] pop_data7_i, // stack data
input wire [IM_W-1:0] im_i, // immediate
//
output wire [DATA_W-1:0] a_data_o, // results
output wire [DATA_W-1:0] b_data_o,
output wire [ADDR_W-1:0] b_addr_o
);
 
 
/*
----------------------
-- internal signals --
----------------------
*/
reg [DATA_W-1:0] a_data, b_data;
reg [ADDR_W-1:0] b_addr;
 
 
 
/*
================
== code start ==
================
*/
 
 
// a data mux
always @ ( * ) begin
case ( data_sel_a_i )
'd0 : a_data <= pop_data0_i;
'd1 : a_data <= pop_data1_i;
'd2 : a_data <= pop_data2_i;
'd3 : a_data <= pop_data3_i;
'd4 : a_data <= pop_data4_i;
'd5 : a_data <= pop_data5_i;
'd6 : a_data <= pop_data6_i;
'd7 : a_data <= pop_data7_i;
endcase
end
// b data mux
always @ ( * ) begin
case ( data_sel_b_i )
'd0 : b_data <= pop_data0_i;
'd1 : b_data <= pop_data1_i;
'd2 : b_data <= pop_data2_i;
'd3 : b_data <= pop_data3_i;
'd4 : b_data <= pop_data4_i;
'd5 : b_data <= pop_data5_i;
'd6 : b_data <= pop_data6_i;
'd7 : b_data <= pop_data7_i;
endcase
end
// b address mux
always @ ( * ) begin
case ( addr_sel_b_i )
'd0 : b_addr <= pop_data0_i[ADDR_W-1:0];
'd1 : b_addr <= pop_data1_i[ADDR_W-1:0];
'd2 : b_addr <= pop_data2_i[ADDR_W-1:0];
'd3 : b_addr <= pop_data3_i[ADDR_W-1:0];
'd4 : b_addr <= pop_data4_i[ADDR_W-1:0];
'd5 : b_addr <= pop_data5_i[ADDR_W-1:0];
'd6 : b_addr <= pop_data6_i[ADDR_W-1:0];
'd7 : b_addr <= pop_data7_i[ADDR_W-1:0];
endcase
end
 
// data
assign a_data_o = a_data;
assign b_data_o = ( imda_i ) ? $signed( im_i ) : $signed( b_data );
 
// address
assign b_addr_o = ( imad_i ) ? $signed( im_i ) : $signed( b_addr );
 
 
endmodule
/trunk/v04.05/hive_core.qpf
0,0 → 1,30
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2010 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
# Date created = 19:35:46 December 06, 2013
#
# -------------------------------------------------------------------------- #
 
QUARTUS_VERSION = "9.1"
DATE = "19:35:46 December 06, 2013"
 
# Revisions
 
PROJECT_REVISION = "hive_core"
/trunk/v04.05/uart_rx.v
0,0 → 1,246
/*
--------------------------------------------------------------------------------
 
Module: uart_rx.v
 
Function:
- Forms the RX side of a DATA_W,n,1 RS232 UART.
 
Instantiates:
- functions.h
 
Notes:
- Rising edge of baud_clk_i is employed.
- baud_clk_i / BAUD_OSR = uart baud (bit) rate.
- baud_clk_i must be synchronous to clk_i.
- Serial data is non-inverted; quiescent serial state is high (assumes
external inverting buffer).
- Bits are in this order (@ serial port of this module, line s/b inverted):
- 1 start bit (low),
- DATA_W data bits (LSB first, MSB last),
- 1 or more stop bits (high).
- The parallel data interface may be connected to a FIFO or similar.
- Start & stop errors, if presented, are simultaneous with the write pulse so
external logic can decide whether or not to accept the data.
- Start & stop errors are an indication of noise on the line / incorrect baud
rate.
- Bad buffer error happens when external data store doesn't take RX data
before another byte arrives.
- Parameterized data width.
- Parameterized oversampling rate.
 
--------------------------------------------------------------------------------
*/
 
module uart_rx
#(
parameter integer DATA_W = 8, // parallel data width (bits)
parameter integer BAUD_OSR = 16 // BAUD oversample rate (3 or larger)
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active hi
// timing interface
input wire baud_clk_i, // baud clock
// parallel interface
output reg [DATA_W-1:0] rx_data_o, // data
output reg rx_rdy_o, // ready with data, active hi
input wire rx_rd_i, // data read, active hi
// serial interface
input wire rx_i, // serial data
// debug
output reg rx_bad_start_o, // bad start bit, active hi
output reg rx_bad_stop_o, // bad stop bit, active hi
output reg rx_bad_buffer_o // bad buffering, active hi
);
 
 
/*
----------------------
-- internal signals --
----------------------
*/
`include "functions.h" // for clog2()
//
localparam integer BIT_PHASE_W = clog2( BAUD_OSR );
localparam integer BIT_PHASE_MID = BAUD_OSR/2;
localparam integer BIT_PHASE_MAX = BAUD_OSR-1;
localparam integer BIT_COUNT_MAX = DATA_W+1;
localparam integer BIT_COUNT_W = clog2( BIT_COUNT_MAX );
//
reg [1:0] rx_sr;
reg baud_clk_reg;
wire baud_flg;
//
reg [BIT_PHASE_W-1:0] bit_phase;
wire bit_sample_flg, bit_done_flg;
//
reg [BIT_COUNT_W-1:0] bit_count;
wire word_done_flg;
//
reg [DATA_W+1:0] rx_data_sr;
//
localparam integer STATE_W = 2; // state width (bits)
reg [STATE_W-1:0] state_sel, state;
localparam [STATE_W-1:0]
st_idle = 0,
st_data = 1,
st_load = 2,
st_wait = 3;
 
 
/*
================
== code start ==
================
*/
 
 
/*
-----------
-- input --
-----------
*/
// register rx_i twice to resync
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
rx_sr <= 2'b11; // note: preset!
end else begin
rx_sr <= { rx_sr[0], rx_i };
end
end
 
// register to detect edges
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
baud_clk_reg <= 'b0;
end else begin
baud_clk_reg <= baud_clk_i;
end
end
 
// decode rising edge
assign baud_flg = ( ~baud_clk_reg & baud_clk_i );
 
/*
--------------
-- counters --
--------------
*/
 
// form the bit_phase & bit_count up-counters
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
bit_phase <= 'b0;
bit_count <= 'b0;
end else begin
if ( state_sel != st_data ) begin
bit_phase <= 'b0;
bit_count <= 'b0;
end else if ( bit_done_flg ) begin
bit_phase <= 'b0;
bit_count <= bit_count + 1'b1;
end else if ( baud_flg ) begin
bit_phase <= bit_phase + 1'b1;
end
end
end
 
// decode flags
assign bit_sample_flg = ( ( bit_phase == BIT_PHASE_MID[BIT_PHASE_W-1:0] ) & baud_flg );
assign bit_done_flg = ( ( bit_phase == BIT_PHASE_MAX[BIT_PHASE_W-1:0] ) & baud_flg );
assign word_done_flg = ( ( bit_count == BIT_COUNT_MAX[BIT_COUNT_W-1:0] ) & bit_sample_flg );
 
 
/*
-------------------
-- state machine --
-------------------
*/
 
// select next state
always @ ( * ) begin
state_sel <= state; // default: stay in current state
case ( state )
st_idle : begin // idle
if ( ~rx_sr[1] ) begin
state_sel <= st_data; // proceed
end
end
st_data : begin // data bits
if ( word_done_flg ) begin
state_sel <= st_load; // load
end
end
st_load, st_wait : begin
if ( rx_sr[1] ) begin
state_sel <= st_idle; // done
end else begin
state_sel <= st_wait; // bad stop bit
end
end
default : begin // for fault tolerance
state_sel <= st_idle;
end
endcase
end
 
// register state
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
state <= st_idle;
end else begin
state <= state_sel;
end
end
 
 
/*
---------------------
-- data conversion --
---------------------
*/
// serial => parallel conversion
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
rx_data_sr <= 'b0;
end else begin
if ( bit_sample_flg ) begin
rx_data_sr <= { rx_sr[1], rx_data_sr[DATA_W+1:1] };
end
end
end
 
 
/*
------------
-- output --
------------
*/
 
// register outputs
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
rx_data_o <= 'b0;
rx_rdy_o <= 'b0;
rx_bad_start_o <= 'b0;
rx_bad_stop_o <= 'b0;
rx_bad_buffer_o <= 'b0;
end else begin
if ( state == st_load ) begin
rx_data_o <= rx_data_sr[DATA_W:1];
rx_rdy_o <= 'b1;
rx_bad_start_o <= rx_data_sr[0];
rx_bad_stop_o <= ~rx_data_sr[DATA_W+1];
rx_bad_buffer_o <= ( ~rx_rd_i & rx_rdy_o );
end else begin
rx_rdy_o <= ~rx_rd_i & rx_rdy_o;
end
end
end
 
endmodule
/trunk/v04.05/dp_ram_infer.v
0,0 → 1,139
/*
--------------------------------------------------------------------------------
 
Module: dp_ram_infer.v
 
Function:
- Infers a parameterized dual port synchronous RAM.
 
Instantiates:
- Nothing (block RAM will most likely be synthesized).
 
Notes:
- A & B sides are separate clock domains.
- Writes accept data after the address & write enable on the clock.
- Reads present data after the address on the clock.
- Configurable read-during-write mode (for the same port).
- Optional output data registering (likely an internal BRAM resource).
 
--------------------------------------------------------------------------------
*/
 
module dp_ram_infer
#(
parameter integer REG_A_OUT = 1, // 1=enable A output registering
parameter integer REG_B_OUT = 1, // 1=enable B output registering
parameter integer DATA_W = 16,
parameter integer ADDR_W = 8,
parameter MODE = "RAW" // options here are "WAR" and "RAW"
)
(
// A side
input wire a_clk_i, // A clock
input wire [ADDR_W-1:0] a_addr_i, // A address
input wire a_wr_i, // A write enable, active high
input wire [DATA_W-1:0] a_data_i, // A write data
output wire [DATA_W-1:0] a_data_o, // A read data
// B side
input wire b_clk_i, // B clock
input wire [ADDR_W-1:0] b_addr_i, // B address
input wire b_wr_i, // B write enable, active high
input wire [DATA_W-1:0] b_data_i, // B write data
output wire [DATA_W-1:0] b_data_o // B read data
);
 
/*
----------------------
-- internal signals --
----------------------
*/
localparam integer CAPACITY = 2**ADDR_W; // total words possible to store
reg [DATA_W-1:0] ram[0:CAPACITY-1]; // memory
reg [DATA_W-1:0] a_data, b_data;
//
localparam integer MEM_DATA_W = DATA_W;
`include "boot_code.h"
 
 
 
/*
================
== code start ==
================
*/
 
 
 
/*
------------
-- side A --
------------
*/
 
// write
always @ ( posedge a_clk_i ) begin
if ( a_wr_i ) begin
ram[a_addr_i] <= a_data_i;
end
end
 
// read
always @ ( posedge a_clk_i ) begin
if ( a_wr_i & MODE == "RAW" ) begin
a_data <= a_data_i; // read after write
end else begin
a_data <= ram[a_addr_i]; // write after read
end
end
 
// optional output reg
generate
if ( REG_A_OUT ) begin
reg [DATA_W-1:0] a_data_r;
always @ ( posedge a_clk_i ) begin
a_data_r <= a_data;
end
assign a_data_o = a_data_r;
end else begin
assign a_data_o = a_data;
end
endgenerate
 
 
/*
------------
-- side B --
------------
*/
 
// write
always @ ( posedge b_clk_i ) begin
if ( b_wr_i ) begin
ram[b_addr_i] <= b_data_i;
end
end
 
// read
always @ ( posedge b_clk_i ) begin
if ( b_wr_i & MODE == "RAW" ) begin
b_data <= b_data_i; // read after write
end else begin
b_data <= ram[b_addr_i]; // write after read
end
end
 
// optional output reg
generate
if ( REG_B_OUT ) begin
reg [DATA_W-1:0] b_data_r;
always @ ( posedge b_clk_i ) begin
b_data_r <= b_data;
end
assign b_data_o = b_data_r;
end else begin
assign b_data_o = b_data;
end
endgenerate
 
 
endmodule
/trunk/v04.05/ep4ce6e22c8_demo_board.qpf
0,0 → 1,30
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2011 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition
# Date created = 11:55:43 November 11, 2013
#
# -------------------------------------------------------------------------- #
 
QUARTUS_VERSION = "10.1"
DATE = "11:55:43 November 11, 2013"
 
# Revisions
 
PROJECT_REVISION = "ep4ce6e22c8_demo_board"
/trunk/v04.05/dq_ram_infer.v
0,0 → 1,85
/*
--------------------------------------------------------------------------------
 
Module: dq_ram_infer.v
 
Function:
- Infers a parameterized simple DQ synchronous RAM.
 
Instantiates:
- Nothing (block RAM will most likely be synthesized).
 
Notes:
- Writes accept data after the address & write enable on the clock.
- Reads present data after the address on the clock.
- Configurable read-during-write mode.
- Optional output data registering (likely an internal BRAM resource).
 
--------------------------------------------------------------------------------
*/
 
module dq_ram_infer
#(
parameter integer REG_OUT = 1, // 1=enable output registering
parameter integer DATA_W = 16,
parameter integer ADDR_W = 8,
parameter MODE = "RAW" // options here are "WAR" and "RAW"
)
(
input wire clk_i, // clock
input wire [ADDR_W-1:0] addr_i, // address
input wire wr_i, // write enable, active high
input wire [DATA_W-1:0] data_i, // write data
output wire [DATA_W-1:0] data_o // read data
);
 
/*
----------------------
-- internal signals --
----------------------
*/
localparam integer CAPACITY = 2**ADDR_W; // total words possible to store
reg [DATA_W-1:0] ram[0:CAPACITY-1]; // memory
reg [DATA_W-1:0] data;
 
 
 
/*
================
== code start ==
================
*/
 
 
 
// write
always @ ( posedge clk_i ) begin
if ( wr_i ) begin
ram[addr_i] <= data_i;
end
end
 
// read
always @ ( posedge clk_i ) begin
if ( wr_i & MODE == "RAW" ) begin
data <= data_i; // read after write
end else begin
data <= ram[addr_i]; // write after read
end
end
 
// optional output reg
generate
if ( REG_OUT == 1 ) begin
reg [DATA_W-1:0] data_r;
always @ ( posedge clk_i ) begin
data_r <= data;
end
assign data_o = data_r;
end else begin
assign data_o = data;
end
endgenerate
 
 
endmodule
/trunk/v04.05/thread_ring.v
0,0 → 1,84
/*
--------------------------------------------------------------------------------
 
Module : thread_ring.v
 
--------------------------------------------------------------------------------
 
Function:
- Processor thread pipeline.
 
Instantiates:
- Nothing.
 
Notes:
- 8 stage pipeline.
- Counter in stage 0 ensures long-term correct operation.
 
--------------------------------------------------------------------------------
*/
 
module thread_ring
#(
parameter integer THREADS = 8, // threads
parameter integer THRD_W = 3 // thread width
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// threads
output wire [THRD_W-1:0] thrd_0_o,
output wire [THRD_W-1:0] thrd_1_o,
output wire [THRD_W-1:0] thrd_2_o,
output wire [THRD_W-1:0] thrd_3_o,
output wire [THRD_W-1:0] thrd_4_o,
output wire [THRD_W-1:0] thrd_5_o,
output wire [THRD_W-1:0] thrd_6_o,
output wire [THRD_W-1:0] thrd_7_o
);
 
/*
----------------------
-- internal signals --
----------------------
*/
reg [THRD_W-1:0] thrd[0:THREADS-1];
localparam [THRD_W-1:0] THRD_OS = 'd5;
 
 
/*
================
== code start ==
================
*/
 
 
// pipeline thread
integer j;
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
for ( j = 0; j < THREADS; j = j + 1 ) begin
thrd[j] <= THRD_OS - j[THRD_W-1:0];
end
end else begin
for ( j = 0; j < THREADS; j = j + 1 ) begin
if ( j == 0 ) thrd[j] <= thrd[j] + 1'b1; // note: counter terminus
else thrd[j] <= thrd[j-1];
end
end
end
 
// output thrd
assign thrd_0_o = thrd[0];
assign thrd_1_o = thrd[1];
assign thrd_2_o = thrd[2];
assign thrd_3_o = thrd[3];
assign thrd_4_o = thrd[4];
assign thrd_5_o = thrd[5];
assign thrd_6_o = thrd[6];
assign thrd_7_o = thrd[7];
 
endmodule
/trunk/v04.05/uart_tx.v
0,0 → 1,236
/*
--------------------------------------------------------------------------------
 
Module: uart_tx.v
 
Function:
- Forms the TX side of a DATA_W,n,STOP_BITS RS232 UART.
 
Instantiates:
- functions.h
 
Notes:
- Rising edge of baud_clk_i is employed.
- baud_clk_i / BAUD_OSR = uart baud (bit) rate.
- baud_clk_i mist be synchronous to clk_i.
- Serial data is non-inverted; quiescent serial state is high (assumes
external inverting buffer).
- Bits are in this order (@ serial port of this module, line s/b inverted):
- 1 start bit (low),
- DATA_W data bits (LSB first, MSB last),
- 1 or more stop bits (high).
- The parallel data interface may be connected to a FIFO or similar.
- Parameterized data width.
- Parameterized oversampling rate.
- Parameterized stop bits.
 
--------------------------------------------------------------------------------
*/
 
module uart_tx
#(
parameter integer DATA_W = 8, // parallel data width (bits)
parameter integer BAUD_OSR = 16, // BAUD clock oversample rate (3 or larger)
parameter integer STOP_BITS = 1 // number of stop bits
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active hi
// timing interface
input wire baud_clk_i, // baud clock
// parallel interface
input wire [DATA_W-1:0] tx_data_i, // data
output reg tx_rdy_o, // ready for data, active hi
input wire tx_wr_i, // data write, active high
// serial interface
output wire tx_o // serial data
);
 
 
/*
----------------------
-- internal signals --
----------------------
*/
`include "functions.h" // for clog2()
//
localparam integer BIT_PHASE_W = clog2( BAUD_OSR );
localparam integer BIT_PHASE_MAX = BAUD_OSR-1;
localparam integer BIT_COUNT_MAX = DATA_W+STOP_BITS;
localparam integer BIT_COUNT_W = clog2( BIT_COUNT_MAX );
//
reg baud_clk_reg;
wire baud_flg;
reg [DATA_W-1:0] tx_data_reg;
//
reg [BIT_PHASE_W-1:0] bit_phase;
wire bit_done_flg;
//
reg [BIT_COUNT_W-1:0] bit_count;
wire word_done_flg;
//
reg [DATA_W:0] tx_data_sr;
wire load_flg;
//
localparam integer STATE_W = 2; // state width (bits)
reg [STATE_W-1:0] state_sel, state;
localparam [STATE_W-1:0]
st_idle = 0,
st_wait = 1,
st_load = 2,
st_data = 3;
 
 
/*
================
== code start ==
================
*/
 
 
/*
-----------
-- input --
-----------
*/
// register to detect edges
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
baud_clk_reg <= 'b0;
end else begin
baud_clk_reg <= baud_clk_i;
end
end
 
// decode rising edge
assign baud_flg = ( ~baud_clk_reg & baud_clk_i );
// register parallel data
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
tx_data_reg <= 'b0;
tx_rdy_o <= 'b1;
end else begin
if ( tx_wr_i ) begin
tx_data_reg <= tx_data_i;
tx_rdy_o <= 'b0;
end else if ( load_flg ) begin
tx_rdy_o <= 'b1;
end
end
end
 
 
/*
--------------
-- counters --
--------------
*/
 
// form the bit_phase & bit_count up-counters
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
bit_phase <= 'b0;
bit_count <= 'b0;
end else begin
if ( state_sel != st_data ) begin
bit_phase <= 'b0;
bit_count <= 'b0;
end else if ( bit_done_flg ) begin
bit_phase <= 'b0;
bit_count <= bit_count + 1'b1;
end else if ( baud_flg ) begin
bit_phase <= bit_phase + 1'b1;
end
end
end
 
// decode flags
assign bit_done_flg = ( ( bit_phase == BIT_PHASE_MAX[BIT_PHASE_W-1:0] ) & baud_flg );
assign word_done_flg = ( ( bit_count == BIT_COUNT_MAX[BIT_COUNT_W-1:0] ) & bit_done_flg );
 
 
/*
-------------------
-- state machine --
-------------------
*/
 
// select next state
always @ ( * ) begin
state_sel <= state; // default: stay in current state
case ( state )
st_idle : begin // idle
if ( ~tx_rdy_o ) begin
state_sel <= st_wait; // proceed
end
end
st_wait : begin // wait for baud sync
if ( baud_flg ) begin
state_sel <= st_load; // proceed
end
end
st_load : begin // load
state_sel <= st_data; // proceed
end
st_data : begin // data bits
if ( word_done_flg ) begin
if ( ~tx_rdy_o ) begin
state_sel <= st_load; // do again
end else begin
state_sel <= st_idle; // done
end
end
end
default : begin // for fault tolerance
state_sel <= st_idle;
end
endcase
end
 
// register state
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
state <= st_idle;
end else begin
state <= state_sel;
end
end
// decode flags
assign load_flg = ( state_sel == st_load );
 
 
/*
---------------------
-- data conversion --
---------------------
*/
// parallel => serial conversion
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
tx_data_sr <= { (DATA_W+1){1'b1} };
end else begin
if ( load_flg ) begin
tx_data_sr <= { tx_data_reg, 1'b0 };
end else if ( bit_done_flg ) begin
tx_data_sr <= { 1'b1, tx_data_sr[DATA_W:1] };
end
end
end
 
 
/*
------------
-- output --
------------
*/
 
// outputs
assign tx_o = tx_data_sr[0];
 
 
endmodule
/trunk/v04.05/data_ring.v
0,0 → 1,338
/*
--------------------------------------------------------------------------------
 
Module : data_ring.v
 
--------------------------------------------------------------------------------
 
Function:
- Processor data path & data stacks.
 
Instantiates:
- (1x) stacks_mux.v
- (1x) alu_top.v
- (1x) pointer_ring.v
- (8x) dq_ram_infer.v
 
Notes:
- 8 stage data pipeline beginning and ending on 8 BRAM based LIFOs.
 
--------------------------------------------------------------------------------
*/
 
module data_ring
#(
parameter integer DATA_W = 32, // data width
parameter integer ADDR_W = 16, // address width
parameter integer THREADS = 8, // threads
parameter integer THRD_W = 3, // thread selector width
parameter integer STACKS = 8, // stacks
parameter integer STK_W = 3, // stack selector width
parameter integer PNTR_W = 5, // stack pointer width
parameter integer IM_W = 6, // immediate width
parameter integer LG_SEL_W = 4, // operation width
parameter integer PROT_POP = 1, // 1=error protection, 0=none
parameter integer PROT_PUSH = 1 // 1=error protection, 0=none
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// control I/O
input wire [STK_W-1:0] data_sel_a_i, // stack selector
input wire [STK_W-1:0] data_sel_b_i, // stack selector
input wire [STK_W-1:0] addr_sel_b_i, // stack selector
input wire imda_i, // 1=immediate data
input wire imad_i, // 1=immediate address
input wire sgn_i, // 1=signed
input wire ext_i, // 1=extended result
input wire hgh_i, // 1=high
input wire [LG_SEL_W-1:0] lg_sel_i, // logic operation (see lg_sel_encode.h)
input wire add_i, // 1=add
input wire sub_i, // 1=subtract
input wire mul_i, // 1=multiply
input wire shl_i, // 1=shift left
input wire pow_i, // 1=power of 2
input wire rtn_i, // 1=return pc
input wire dm_rd_i, // 1=read
input wire rg_rd_i, // 1=read
// stack I/O
input wire stk_clr_i, // stacks clear
input wire [STACKS-1:0] pop_i, // stacks pop
input wire [STACKS-1:0] push_i, // stacks push
input wire [THRD_W-1:0] thrd_6_i, // thread
// data I/O
input wire [IM_W-1:0] im_i, // immediate
input wire [DATA_W/2-1:0] dm_rd_data_4_i, // dmem read data
input wire [DATA_W/2-1:0] rg_rd_data_4_i, // regs read data
input wire [ADDR_W-1:0] pc_3_i, // program counter
output wire [DATA_W-1:0] a_data_o, // a
output wire [ADDR_W-1:0] b_addr_o, // b
// flags
output wire flg_nz_2_o, // a != 0
output wire flg_lz_2_o, // a < 0
output wire flg_ne_2_o, // a != b
output wire flg_lt_2_o, // a < b
// errors
output wire [STACKS-1:0] pop_er_2_o, // pop when empty, active high
output wire [STACKS-1:0] push_er_3_o // push when full, active high
);
 
 
/*
----------------------
-- internal signals --
----------------------
*/
wire [DATA_W-1:0] b_data;
wire [DATA_W-1:0] pop_data0, pop_data1, pop_data2, pop_data3, pop_data4, pop_data5, pop_data6, pop_data7, push_data_6;
wire [PNTR_W-1:0] pntr0_6, pntr1_6, pntr2_6, pntr3_6, pntr4_6, pntr5_6, pntr6_6, pntr7_6;
wire [STACKS-1:0] stk_wr_6;
 
 
 
/*
================
== code start ==
================
*/
 
 
 
// stacks output mux
stacks_mux
#(
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W ),
.IM_W ( IM_W ),
.STK_W ( STK_W )
)
stacks_mux
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_sel_a_i ( data_sel_a_i ),
.data_sel_b_i ( data_sel_b_i ),
.addr_sel_b_i ( addr_sel_b_i ),
.imda_i ( imda_i ),
.imad_i ( imad_i ),
.pop_data0_i ( pop_data0 ),
.pop_data1_i ( pop_data1 ),
.pop_data2_i ( pop_data2 ),
.pop_data3_i ( pop_data3 ),
.pop_data4_i ( pop_data4 ),
.pop_data5_i ( pop_data5 ),
.pop_data6_i ( pop_data6 ),
.pop_data7_i ( pop_data7 ),
.im_i ( im_i ),
.a_data_o ( a_data_o ),
.b_data_o ( b_data ),
.b_addr_o ( b_addr_o )
);
 
 
// ALU
alu_top
#(
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W ),
.LG_SEL_W ( LG_SEL_W )
)
alu_top
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.sgn_i ( sgn_i ),
.ext_i ( ext_i ),
.hgh_i ( hgh_i ),
.lg_sel_i ( lg_sel_i ),
.add_i ( add_i ),
.sub_i ( sub_i ),
.mul_i ( mul_i ),
.shl_i ( shl_i ),
.pow_i ( pow_i ),
.rtn_i ( rtn_i ),
.dm_rd_i ( dm_rd_i ),
.rg_rd_i ( rg_rd_i ),
.a_i ( a_data_o ),
.b_i ( b_data ),
.dm_rd_data_4_i ( dm_rd_data_4_i ),
.rg_rd_data_4_i ( rg_rd_data_4_i ),
.pc_3_i ( pc_3_i ),
.result_6_o ( push_data_6 ),
.flg_nz_2_o ( flg_nz_2_o ),
.flg_lz_2_o ( flg_lz_2_o ),
.flg_ne_2_o ( flg_ne_2_o ),
.flg_lt_2_o ( flg_lt_2_o )
);
 
 
// stack pointer generation & storage
pointer_ring
#(
.THREADS ( THREADS ),
.STACKS ( STACKS ),
.PNTR_W ( PNTR_W ),
.PROT_POP ( PROT_POP ),
.PROT_PUSH ( PROT_PUSH )
)
pointer_ring
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.clr_i ( stk_clr_i ),
.pop_i ( pop_i ),
.push_i ( push_i ),
.pntr0_6_o ( pntr0_6 ),
.pntr1_6_o ( pntr1_6 ),
.pntr2_6_o ( pntr2_6 ),
.pntr3_6_o ( pntr3_6 ),
.pntr4_6_o ( pntr4_6 ),
.pntr5_6_o ( pntr5_6 ),
.pntr6_6_o ( pntr6_6 ),
.pntr7_6_o ( pntr7_6 ),
.wr_6_o ( stk_wr_6 ),
.pop_er_2_o ( pop_er_2_o ),
.push_er_3_o ( push_er_3_o )
);
 
 
// LIFO stacks memory
dq_ram_infer
#(
.REG_OUT ( 1 ),
.DATA_W ( DATA_W ),
.ADDR_W ( THRD_W+PNTR_W ),
.MODE ( "RAW" )
)
stack0_dq_ram
(
.clk_i ( clk_i ),
.addr_i ( { thrd_6_i, pntr0_6 } ),
.wr_i ( stk_wr_6[0] ),
.data_i ( push_data_6 ),
.data_o ( pop_data0 )
);
 
dq_ram_infer
#(
.REG_OUT ( 1 ),
.DATA_W ( DATA_W ),
.ADDR_W ( THRD_W+PNTR_W ),
.MODE ( "RAW" )
)
stack1_dq_ram
(
.clk_i ( clk_i ),
.addr_i ( { thrd_6_i, pntr1_6 } ),
.wr_i ( stk_wr_6[1] ),
.data_i ( push_data_6 ),
.data_o ( pop_data1 )
);
 
 
dq_ram_infer
#(
.REG_OUT ( 1 ),
.DATA_W ( DATA_W ),
.ADDR_W ( THRD_W+PNTR_W ),
.MODE ( "RAW" )
)
stack2_dq_ram
(
.clk_i ( clk_i ),
.addr_i ( { thrd_6_i, pntr2_6 } ),
.wr_i ( stk_wr_6[2] ),
.data_i ( push_data_6 ),
.data_o ( pop_data2 )
);
 
 
dq_ram_infer
#(
.REG_OUT ( 1 ),
.DATA_W ( DATA_W ),
.ADDR_W ( THRD_W+PNTR_W ),
.MODE ( "RAW" )
)
stack3_dq_ram
(
.clk_i ( clk_i ),
.addr_i ( { thrd_6_i, pntr3_6 } ),
.wr_i ( stk_wr_6[3] ),
.data_i ( push_data_6 ),
.data_o ( pop_data3 )
);
 
 
dq_ram_infer
#(
.REG_OUT ( 1 ),
.DATA_W ( DATA_W ),
.ADDR_W ( THRD_W+PNTR_W ),
.MODE ( "RAW" )
)
stack4_dq_ram
(
.clk_i ( clk_i ),
.addr_i ( { thrd_6_i, pntr4_6 } ),
.wr_i ( stk_wr_6[4] ),
.data_i ( push_data_6 ),
.data_o ( pop_data4 )
);
 
 
dq_ram_infer
#(
.REG_OUT ( 1 ),
.DATA_W ( DATA_W ),
.ADDR_W ( THRD_W+PNTR_W ),
.MODE ( "RAW" )
)
stack5_dq_ram
(
.clk_i ( clk_i ),
.addr_i ( { thrd_6_i, pntr5_6 } ),
.wr_i ( stk_wr_6[5] ),
.data_i ( push_data_6 ),
.data_o ( pop_data5 )
);
 
 
dq_ram_infer
#(
.REG_OUT ( 1 ),
.DATA_W ( DATA_W ),
.ADDR_W ( THRD_W+PNTR_W ),
.MODE ( "RAW" )
)
stack6_dq_ram
(
.clk_i ( clk_i ),
.addr_i ( { thrd_6_i, pntr6_6 } ),
.wr_i ( stk_wr_6[6] ),
.data_i ( push_data_6 ),
.data_o ( pop_data6 )
);
 
 
dq_ram_infer
#(
.REG_OUT ( 1 ),
.DATA_W ( DATA_W ),
.ADDR_W ( THRD_W+PNTR_W ),
.MODE ( "RAW" )
)
stack7_dq_ram
(
.clk_i ( clk_i ),
.addr_i ( { thrd_6_i, pntr7_6 } ),
.wr_i ( stk_wr_6[7] ),
.data_i ( push_data_6 ),
.data_o ( pop_data7 )
);
 
 
endmodule
/trunk/v04.05/functions.h
0,0 → 1,95
/*
--------------------------------------------------------------------------------
--
-- Module : functions.h
--
--------------------------------------------------------------------------------
--
-- Function:
-- - A bunch of functions for a stack processor.
--
-- Instantiates:
-- - Nothing.
--
--------------------------------------------------------------------------------
*/
 
 
/*
---------------
-- functions --
---------------
*/
 
 
// returns safe ceiling value of log2(n)
// (for vector sizing we never want less than 1)
// examples:
// clog2(0 thru 2) = 1,
// clog2(3 & 4) = 2,
// clog2(5 thru 8) = 3,
// clog2(9 thru 16) = 4, etc.
function integer clog2;
input integer in;
begin
clog2 = 1;
while ( in > 2 ) begin
in = ( in + 1 ) / 2;
clog2 = clog2 + 1;
end
end
endfunction
 
 
// flip 32 bit value
function [31:0] flip_32;
input [31:0] in;
integer i;
begin
for ( i=0; i<32; i=i+1 ) begin
flip_32[i] = in[31-i];
end
end
endfunction
 
 
// return leading zero count of 32 bit value
// examples:
// lzc_32(32'b000...000) = 32
// lzc_32(32'b000...001) = 31
// lzc_32(32'b000...01x) = 30
// ...
// lzc_32(32'b001...xxx) = 2
// lzc_32(32'b01x...xxx) = 1
// lzc_32(32'b1xx...xxx) = 0
function [5:0] lzc_32;
input [31:0] in;
integer j, hi_1, all_0;
begin
hi_1 = 31;
all_0 = 1;
// priority encoder (find MSB 1 position)
for ( j = 0; j < 32; j = j + 1 ) begin
if ( in[j] ) begin
hi_1 = j;
all_0 = 0;
end
end
end
// invert & concat to get zero count
lzc_32 = { all_0[0], ~hi_1[4:0] };
endfunction
 
 
// returns the max of 2 integers
function integer max_of_2;
input integer a, b;
begin
if ( a > b ) begin
max_of_2 = a;
end else begin
max_of_2 = b;
end
end
endfunction
 
/trunk/v04.05/pipe.v
0,0 → 1,71
/*
--------------------------------------------------------------------------------
 
Module: pipe.v
 
Function:
- Vector I/O shift register.
 
Instantiates:
- Nothing.
 
Notes:
- Parameters for depth (register stages), data width, and async reset value.
- DEPTH=0 generates a wire.
 
--------------------------------------------------------------------------------
*/
 
 
module pipe
#(
parameter integer DEPTH = 4, // register stages
parameter integer WIDTH = 2, // I/O data width
parameter [WIDTH-1:0] RESET_VAL = 0 // regs async reset value
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// I/O
input wire [WIDTH-1:0] data_i, // data in
output wire [WIDTH-1:0] data_o // data out
);
 
 
/*
----------------------
-- internal signals --
----------------------
*/
genvar i;
 
 
/*
================
== code start ==
================
*/
 
 
// generate regs pipeline
generate
if ( DEPTH == 0 ) begin
assign data_o = data_i;
end else begin
reg [WIDTH-1:0] stage[0:DEPTH-1];
for ( i=0; i<DEPTH; i=i+1 ) begin : loop
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
stage[i] <= RESET_VAL;
end else begin
stage[i] <= ( i == DEPTH-1 ) ? data_i : stage[i+1];
end
end
end // endfor : loop
assign data_o = stage[0];
end
endgenerate
 
 
endmodule
/trunk/v04.05/pointer_ring.v
0,0 → 1,191
/*
--------------------------------------------------------------------------------
 
Module : pointer_ring.v
 
--------------------------------------------------------------------------------
 
Function:
- Processor stack pointer storage ring.
 
Instantiates:
- (1x) pipe.v
 
Notes:
- 8 stage pointer storage ring for 8 BRAM based LIFOs:
0 : clear applied (& all inputs)
1 : pop applied
2 : push applied; pop errors output
3 : push errors output
6 : pointers & writes output
- Logic assumes pop | push will not be issued simultaneously with clear.
- Externally concatenate thread 6 & pointers to form stack memory addresses.
- Level width is PTR_W+1 to accomodate 0 to 2^n levels (1 + 2n states).
- Empty push is to address 1, full push is to address 0.
- Combo pop/push is accomodated with no net fullness/pointer change.
- Pop when empty is a pop error.
- Push when full is a push error.
- Pop/push when full is NOT an error.
- Pop/push when empty is a pop error ONLY.
- Parameterized stack error handling. If the associated protection is turned on
then pop/push errors are reported but otherwise not acted upon, i.e. errors
will not corrupt fullness/pointers. If the associated protection is turned
off then errors are still reported, but fullness/pointers will be corrupted.
 
--------------------------------------------------------------------------------
*/
 
module pointer_ring
#(
parameter integer THREADS = 8, // threads
parameter integer STACKS = 8, // stacks
parameter integer PNTR_W = 5, // stack pointer width
parameter integer PROT_POP = 1, // 1=error protection, 0=none
parameter integer PROT_PUSH = 1 // 1=error protection, 0=none
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// control I/O
input wire clr_i, // stacks clear
input wire [STACKS-1:0] pop_i, // stacks pop
input wire [STACKS-1:0] push_i, // stacks push
// pointers
output wire [PNTR_W-1:0] pntr0_6_o, // stack pointer
output wire [PNTR_W-1:0] pntr1_6_o, // stack pointer
output wire [PNTR_W-1:0] pntr2_6_o, // stack pointer
output wire [PNTR_W-1:0] pntr3_6_o, // stack pointer
output wire [PNTR_W-1:0] pntr4_6_o, // stack pointer
output wire [PNTR_W-1:0] pntr5_6_o, // stack pointer
output wire [PNTR_W-1:0] pntr6_6_o, // stack pointer
output wire [PNTR_W-1:0] pntr7_6_o, // stack pointer
// write enables
output wire [STACKS-1:0] wr_6_o, // write enables
// errors
output wire [STACKS-1:0] pop_er_2_o, // pop when empty, active high
output wire [STACKS-1:0] push_er_3_o // push when full, active high
);
 
/*
----------------------
-- internal signals --
----------------------
*/
localparam integer LEVEL_W = PNTR_W+1; // +1 extra bit
localparam [LEVEL_W-1:0] EMPTY_VAL = 'b0; // empty value
localparam [LEVEL_W-1:0] FULL_VAL = 1'b1 << PNTR_W; // full value
//
integer s, t;
//
reg [LEVEL_W-1:0] level[0:STACKS-1][0:THREADS-1];
//
reg [STACKS-1:0] pop_1, push_1, push_2;
reg [STACKS-1:0] empty_1, full_2;
wire [STACKS-1:0] dec_1, inc_2;
wire [STACKS-1:0] pop_er_1, push_er_2;
 
 
/*
================
== code start ==
================
*/
 
 
// pipeline control signals
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
pop_1 <= 'b0;
push_1 <= 'b0;
push_2 <= 'b0;
end else begin
pop_1 <= pop_i;
push_1 <= push_i;
push_2 <= push_1;
end
end
 
// decode watermarks
always @ ( * ) begin
for ( s=0; s<STACKS; s=s+1 ) begin
empty_1[s] <= ( level[s][1] == EMPTY_VAL );
full_2[s] <= ( level[s][2] == FULL_VAL );
end
end
// prohibit pointer changes @ errors if configured to do so
assign dec_1 = ( PROT_POP ) ? pop_1 & ~empty_1 : pop_1;
assign inc_2 = ( PROT_PUSH ) ? push_2 & ~full_2 : push_2;
 
// decode errors - pop when empty, push when full
assign pop_er_1 = pop_1 & empty_1;
assign push_er_2 = push_2 & full_2;
 
// decode & pipeline levels
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
for ( s=0; s<STACKS; s=s+1 ) begin
for ( t=0; t<THREADS; t=t+1 ) begin
level[s][t] <= 'b0;
end
end
end else begin
for ( s=0; s<STACKS; s=s+1 ) begin
for ( t=0; t<THREADS; t=t+1 ) begin
if ( t == 0 ) level[s][t] <= level[s][THREADS-1]; // wrap around
else if ( t == 1 ) level[s][t] <= ( clr_i ) ? 1'b0 : level[s][t-1]; // clear
else if ( t == 2 ) level[s][t] <= ( dec_1[s] ) ? level[s][t-1] - 1'b1 : level[s][t-1]; // pop
else if ( t == 3 ) level[s][t] <= ( inc_2[s] ) ? level[s][t-1] + 1'b1 : level[s][t-1]; // push
else level[s][t] <= level[s][t-1];
end
end
end
end
 
 
// decode & pipeline write enables
pipe
#(
.DEPTH ( 4 ),
.WIDTH ( STACKS ),
.RESET_VAL ( 0 )
)
wr_pipe
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( inc_2 ),
.data_o ( wr_6_o )
);
 
 
// register output errors
pipe
#(
.DEPTH ( 1 ),
.WIDTH ( STACKS+STACKS ),
.RESET_VAL ( 0 )
)
reg_errors
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { pop_er_1, push_er_2 } ),
.data_o ( { pop_er_2_o, push_er_3_o } )
);
 
 
// output pointers
assign pntr0_6_o = level[0][6][PNTR_W-1:0];
assign pntr1_6_o = level[1][6][PNTR_W-1:0];
assign pntr2_6_o = level[2][6][PNTR_W-1:0];
assign pntr3_6_o = level[3][6][PNTR_W-1:0];
assign pntr4_6_o = level[4][6][PNTR_W-1:0];
assign pntr5_6_o = level[5][6][PNTR_W-1:0];
assign pntr6_6_o = level[6][6][PNTR_W-1:0];
assign pntr7_6_o = level[7][6][PNTR_W-1:0];
 
endmodule
/trunk/v04.05/control_ring.v
0,0 → 1,294
/*
--------------------------------------------------------------------------------
 
Module : control_ring.v
 
--------------------------------------------------------------------------------
 
Function:
- Processor control path.
 
Instantiates:
- (1x) thread_ring.v
- (2x) event_ctrl.v
- (1x) tst_decode.v
- (1x) op_decode.v
- (1x) pc_ring.v
 
Notes:
- 8 stage pipeline consisting of several storage rings.
 
--------------------------------------------------------------------------------
*/
 
module control_ring
#(
parameter integer DATA_W = 32, // data width
parameter integer ADDR_W = 16, // address width
parameter integer THREADS = 8, // threads
parameter integer THRD_W = 3, // thread width
parameter integer STACKS = 8, // number of stacks
parameter integer STK_W = 3, // stack selector width
parameter integer IM_W = 6, // immediate width
parameter integer MEM_DATA_W = 16, // opcode width
parameter integer LG_SEL_W = 4, // logical operation width
parameter [ADDR_W-1:0] CLR_BASE = 'h0, // clear address base (concat)
parameter integer CLR_SPAN = 2, // clear address span (2^n)
parameter [ADDR_W-1:0] INTR_BASE = 'h20, // interrupt address base (concat)
parameter integer INTR_SPAN = 2 // interrupt address span (2^n)
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// control I/O
input wire [THREADS-1:0] clr_req_i, // clear request, active high
output wire [THREADS-1:0] clr_ack_o, // clear ack, active high until serviced
input wire [THREADS-1:0] intr_en_i, // interrupt enable, active high
input wire [THREADS-1:0] intr_req_i, // interrupt request, active high
output wire [THREADS-1:0] intr_ack_o, // interrupt ack, active high until serviced
input wire [MEM_DATA_W-1:0] op_code_i, // opcode
output wire op_code_er_o, // 1=illegal op code encountered
// ALU I/O
input wire [ADDR_W-1:0] b_addr_i, // b | im
output wire [IM_W-1:0] im_o, // immediate
output wire [STK_W-1:0] data_sel_a_o, // stack selector
output wire [STK_W-1:0] data_sel_b_o, // stack selector
output wire [STK_W-1:0] addr_sel_b_o, // b stack selector
output wire imda_o, // 1=immediate data
output wire imad_o, // 1=immediate address
output wire sgn_o, // 1=signed
output wire ext_o, // 1=extended
output wire hgh_o, // 1=high
output wire [LG_SEL_W-1:0] lg_sel_o, // see decode in notes
output wire add_o, // 1=add
output wire sub_o, // 1=subtract
output wire mul_o, // 1=multiply
output wire shl_o, // 1=shift left
output wire pow_o, // 1=power of 2
output wire rtn_o, // 1=return pc
output wire lit_o, // 1=literal data
output wire dm_rd_o, // 1=read
output wire dm_wr_o, // 1=write
output wire rg_rd_o, // 1=read
output wire rg_wr_o, // 1=write
// stack I/O
output wire stk_clr_o, // stacks clear
output wire [STACKS-1:0] pop_o, // stacks pop
output wire [STACKS-1:0] push_o, // stacks push
// flags
input wire flg_nz_2_i, // a != 0
input wire flg_lz_2_i, // a < 0
input wire flg_ne_2_i, // a != b
input wire flg_lt_2_i, // a < b
// threads
output wire [THRD_W-1:0] thrd_0_o,
output wire [THRD_W-1:0] thrd_2_o,
output wire [THRD_W-1:0] thrd_3_o,
output wire [THRD_W-1:0] thrd_6_o,
// addresses
output wire [ADDR_W-1:0] pc_1_o,
output wire [ADDR_W-1:0] pc_3_o,
output wire [ADDR_W-1:0] pc_4_o
);
 
 
/*
----------------------
-- internal signals --
----------------------
*/
localparam integer TST_W = 4;
//
wire pc_clr, cnd, zro, jmp, gto, intr, res_tst_3;
wire stk_clr;
wire [STACKS-1:0] pop, push;
wire [TST_W-1:0] tst;
wire thrd_clr, thrd_intr;
wire [THRD_W-1:0] thrd_4, thrd_5;
 
 
 
/*
================
== code start ==
================
*/
 
 
// establish threads
thread_ring
#(
.THREADS ( THREADS ),
.THRD_W ( THRD_W )
)
thread_ring
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.thrd_0_o ( thrd_0_o ),
.thrd_1_o ( ),
.thrd_2_o ( thrd_2_o ),
.thrd_3_o ( thrd_3_o ),
.thrd_4_o ( thrd_4 ),
.thrd_5_o ( thrd_5 ),
.thrd_6_o ( thrd_6_o ),
.thrd_7_o ( )
);
 
 
// handle external thread clear requests
event_ctrl
#(
.REGS_REQ ( 0 ), // don't resync
.EDGE_REQ ( 1 ), // edge sensitive
.RESET_VAL ( { THREADS{ 1'b1 } } ), // clear threads @ power-up
.THREADS ( THREADS ),
.THRD_W ( THRD_W )
)
clr_event_ctrl
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.thrd_i ( thrd_5 ),
.en_i ( { THREADS{ 1'b1 } } ), // always enable
.req_i ( clr_req_i ),
.ack_o ( clr_ack_o ),
.event_o ( thrd_clr )
);
 
 
// handle external thread interrupt requests
event_ctrl
#(
.REGS_REQ ( 2 ), // resync
.EDGE_REQ ( 1 ), // edge sensitive
.RESET_VAL ( 0 ),
.THREADS ( THREADS ),
.THRD_W ( THRD_W )
)
intr_event_ctrl
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.thrd_i ( thrd_5 ),
.en_i ( intr_en_i ),
.req_i ( intr_req_i ),
.ack_o ( intr_ack_o ),
.event_o ( thrd_intr )
);
 
 
// conditional jump etc. testing
tst_decode
#(
.REGS_TST ( 2 ),
.REGS_OUT ( 1 ),
.TST_W ( TST_W )
)
tst_decode
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.flg_nz_i ( flg_nz_2_i ),
.flg_lz_i ( flg_lz_2_i ),
.flg_ne_i ( flg_ne_2_i ),
.flg_lt_i ( flg_lt_2_i ),
.cnd_i ( cnd ),
.tst_i ( tst ),
.result_o ( res_tst_3 )
);
 
 
// op_code decoding
op_decode
#(
.REGS_IN ( 0 ),
.REGS_OUT ( 1 ),
.STACKS ( STACKS ),
.STK_W ( STK_W ),
.DATA_W ( DATA_W ),
.IM_W ( IM_W ),
.MEM_DATA_W ( MEM_DATA_W ),
.LG_SEL_W ( LG_SEL_W ),
.TST_W ( TST_W )
)
op_decode
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.thrd_clr_i ( thrd_clr ),
.thrd_intr_i ( thrd_intr ),
.op_code_i ( op_code_i ),
.op_code_er_o ( op_code_er_o ),
.im_o ( im_o ),
.pc_clr_o ( pc_clr ),
.cnd_o ( cnd ),
.lit_o ( lit_o ),
.jmp_o ( jmp ),
.gto_o ( gto ),
.intr_o ( intr ),
.tst_o ( tst ),
.stk_clr_o ( stk_clr_o ),
.pop_o ( pop_o ),
.push_o ( push_o ),
.data_sel_a_o ( data_sel_a_o ),
.data_sel_b_o ( data_sel_b_o ),
.addr_sel_b_o ( addr_sel_b_o ),
.imda_o ( imda_o ),
.imad_o ( imad_o ),
.sgn_o ( sgn_o ),
.ext_o ( ext_o ),
.hgh_o ( hgh_o ),
.lg_sel_o ( lg_sel_o ),
.add_o ( add_o ),
.sub_o ( sub_o ),
.mul_o ( mul_o ),
.shl_o ( shl_o ),
.pow_o ( pow_o ),
.rtn_o ( rtn_o ),
.dm_rd_o ( dm_rd_o ),
.dm_wr_o ( dm_wr_o ),
.rg_rd_o ( rg_rd_o ),
.rg_wr_o ( rg_wr_o )
);
 
 
// pc generation & storage
pc_ring
#(
.THREADS ( THREADS ),
.THRD_W ( THRD_W ),
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W ),
.CLR_BASE ( CLR_BASE ),
.CLR_SPAN ( CLR_SPAN ),
.INTR_BASE ( INTR_BASE ),
.INTR_SPAN ( INTR_SPAN )
)
pc_ring
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.thrd_0_i ( thrd_0_o ),
.thrd_4_i ( thrd_4 ),
.clr_i ( pc_clr ),
.lit_i ( lit_o ),
.jmp_i ( jmp ),
.gto_i ( gto ),
.intr_i ( intr ),
.res_tst_3_i ( res_tst_3 ),
.b_addr_i ( b_addr_i ),
.pc_0_o ( ),
.pc_1_o ( pc_1_o ),
.pc_2_o ( ),
.pc_3_o ( pc_3_o ),
.pc_4_o ( pc_4_o ),
.pc_5_o ( ),
.pc_6_o ( ),
.pc_7_o ( )
);
 
 
endmodule
/trunk/v04.05/alu_top.v
0,0 → 1,215
/*
--------------------------------------------------------------------------------
 
Module : alu_top.v
 
--------------------------------------------------------------------------------
 
Function:
- Processor ALU top level.
 
Instantiates:
- (2x) pipe.v
- (1x) alu_logical.v
- (4x) pipe.v
- (1x) alu_add_sub.v
- (4x) pipe.v
- (1x) alu_mult_shift.v
- (3x) pipe.v
- (1x) alu_multiply.v
- (1x) pipe.v (debug mode only)
- (1x) alu_mux.v
- (4x) pipe.v
 
Notes:
- I/O registered.
- Multi-stage pipeline w/ 5 mid registers.
 
--------------------------------------------------------------------------------
*/
 
module alu_top
#(
parameter integer DATA_W = 32, // data width
parameter integer ADDR_W = 16, // address width
parameter integer LG_SEL_W = 4 // operation width
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// control I/O
input wire sgn_i, // 1=signed
input wire ext_i, // 1=extended result
input wire hgh_i, // 1=high
input wire [LG_SEL_W-1:0] lg_sel_i, // logic operation (see lg_sel_encode.h)
input wire add_i, // 1=add
input wire sub_i, // 1=subtract
input wire mul_i, // 1=multiply
input wire shl_i, // 1=shift left
input wire pow_i, // 1=power of 2
input wire rtn_i, // 1=return pc
input wire dm_rd_i, // 1=read
input wire rg_rd_i, // 1=read
// data I/O
input wire [DATA_W-1:0] a_i, // operand
input wire [DATA_W-1:0] b_i, // operand
input wire [DATA_W/2-1:0] dm_rd_data_4_i, // dmem read data
input wire [DATA_W/2-1:0] rg_rd_data_4_i, // regs read data
input wire [ADDR_W-1:0] pc_3_i, // program counter
output wire [DATA_W-1:0] result_6_o, // result
// flags
output wire flg_nz_2_o, // a != 0
output wire flg_lz_2_o, // a < 0
output wire flg_ne_2_o, // a != b
output wire flg_lt_2_o // a < b
);
 
/*
----------------------
-- internal signals --
----------------------
*/
wire rg_rd_1, dm_rd_1, rtn_1, pow_1, shl_1, mul_1, sub_1, add_1, hgh_1, ext_1, sgn_1;
wire [LG_SEL_W-1:0] lg_sel_1;
wire [DATA_W-1:0] a_1, b_1;
wire [DATA_W-1:0] res_lg_2, res_as_2, res_ms_5;
 
 
/*
================
== code start ==
================
*/
 
 
// input ctrl regs
pipe
#(
.DEPTH ( 1 ),
.WIDTH ( 11+LG_SEL_W ),
.RESET_VAL ( 0 )
)
in_regs_ctrl
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { rg_rd_i, dm_rd_i, rtn_i, pow_i, shl_i, mul_i, sub_i, add_i, hgh_i, ext_i, sgn_i, lg_sel_i } ),
.data_o ( { rg_rd_1, dm_rd_1, rtn_1, pow_1, shl_1, mul_1, sub_1, add_1, hgh_1, ext_1, sgn_1, lg_sel_1 } )
);
 
 
// input data regs
pipe
#(
.DEPTH ( 1 ),
.WIDTH ( DATA_W+DATA_W ),
.RESET_VAL ( 0 )
)
in_regs_data
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { b_i, a_i } ),
.data_o ( { b_1, a_1 } )
);
 
 
// logical unit
alu_logical
#(
.REGS_IN ( 0 ),
.REGS_MID ( 1 ),
.REGS_OUT ( 0 ),
.REGS_FLG ( 1 ),
.DATA_W ( DATA_W ),
.LG_SEL_W ( LG_SEL_W )
)
alu_logical
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.lg_sel_i ( lg_sel_1 ),
.a_i ( a_1 ),
.b_i ( b_1 ),
.result_o ( res_lg_2 ),
.flg_nz_o ( flg_nz_2_o ),
.flg_lz_o ( flg_lz_2_o )
);
 
 
// add & subtract unit
alu_add_sub
#(
.REGS_IN ( 0 ),
.REGS_MID ( 1 ),
.REGS_OUT ( 0 ),
.REGS_FLG ( 1 ),
.DATA_W ( DATA_W )
)
alu_add_sub
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.sgn_i ( sgn_1 ),
.ext_i ( ext_1 ),
.sub_i ( sub_1 ),
.a_i ( a_1 ),
.b_i ( b_1 ),
.result_o ( res_as_2 ),
.flg_ne_o ( flg_ne_2_o ),
.flg_lt_o ( flg_lt_2_o )
);
 
 
// multiply & shift unit
alu_mult_shift
#(
.REGS_IN ( 0 ),
.REGS_OUT ( 0 ),
.DATA_W ( DATA_W ),
.DEBUG_MODE ( 0 )
)
alu_mult_shift
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.sgn_i ( sgn_1 ),
.ext_i ( ext_1 ),
.shl_i ( shl_1 ),
.pow_i ( pow_1 ),
.a_i ( a_1 ),
.b_i ( b_1 ),
.result_o ( res_ms_5 )
);
 
 
// multiplexer
alu_mux
#(
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W )
)
alu_mux
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.sgn_1_i ( sgn_1 ),
.hgh_1_i ( hgh_1 ),
.as_1_i ( add_1 | sub_1 ),
.ms_1_i ( mul_1 | shl_1 | pow_1 ),
.rtn_1_i ( rtn_1 ),
.dm_rd_1_i ( dm_rd_1 ),
.rg_rd_1_i ( rg_rd_1 ),
.res_lg_2_i ( res_lg_2 ),
.res_as_2_i ( res_as_2 ),
.pc_3_i ( pc_3_i ),
.dm_rd_data_4_i ( dm_rd_data_4_i ),
.rg_rd_data_4_i ( rg_rd_data_4_i ),
.res_ms_5_i ( res_ms_5 ),
.data_6_o ( result_6_o )
);
 
 
endmodule
/trunk/v04.05/reg_set_addr.h
0,0 → 1,16
// `ifndef _reg_set_addr_h_
// `define _reg_set_addr_h_
 
// internal register addresses
localparam integer VER_ADDR = 'h0;
localparam integer THRD_ID_ADDR = 'h1;
localparam integer CLR_ADDR = 'h2;
localparam integer INTR_EN_ADDR = 'h3;
localparam integer OP_ER_ADDR = 'h4;
localparam integer STK_ER_ADDR = 'h5;
localparam integer IO_LO_ADDR = 'h8;
localparam integer IO_HI_ADDR = 'h9;
localparam integer UART_RX_ADDR = 'hc;
localparam integer UART_TX_ADDR = 'hd;
 
// `endif // _reg_set_addr_h_
/trunk/v04.05/lg_sel_encode.h
0,0 → 1,16
`ifndef _lg_sel_encode_h_
`define _lg_sel_encode_h_
 
`define lg_cpy 4'h0
`define lg_nsg 4'h1
`define lg_not 4'h2
`define lg_flp 4'h4
`define lg_lzc 4'h5
`define lg_bra 4'h8
`define lg_bro 4'h9
`define lg_brx 4'ha
`define lg_and 4'hc
`define lg_orr 4'hd
`define lg_xor 4'he
 
`endif // _lg_sel_encode_h_
/trunk/v04.05/reg_base.v
0,0 → 1,242
/*
--------------------------------------------------------------------------------
 
Module: reg_base.v
 
Function:
- Single base processor register w/ multiple type & input options (synchronous).
 
Instantiates:
- Nothing.
 
Notes:
- Init value for each latched bit.
- LIVE_MASK[i]=1 indicates live bit.
- LIVE_MASK[i]=0 indicates dead bit, reads zero.
- Optional resync (2x registering) of inputs.
- Optional edge detection (rising) of inputs.
- rd_data_o is driven non-zero if there is an address match, regardless of
state of rd_i.
- Use large OR gate to combine multiple register set read data.
 
OUT_MODE:
- "ZERO" : zero out
- "THRU" : no latch, direct connect
- "LTCH" : write latch
- "LOOP" : no latch, output selected read data
 
READ_MODE:
- "THRU" : no latch, direct connect
- "CORD" : set on input one, clear on read
- "COW1" : set on input one, clear on write one
- "DFFE" : D type flip flop with enable
- "LOOP" : no latch, read selected output data
 
--------------------------------------------------------------------------------
*/
 
 
module reg_base
#(
parameter integer DATA_W = 8, // data width (bits)
parameter integer ADDR_W = 4, // address width (bits)
parameter [ADDR_W-1:0] ADDRESS = 0, // address this register responds to
parameter OUT_MODE = "LOOP", // modes are: "ZERO", "THRU", "LTCH", "LOOP"
parameter READ_MODE = "COW1", // modes are: "THRU", "CORD", "COW1", "DFFE", "LOOP"
parameter [DATA_W-1:0] LIVE_MASK = { DATA_W{ 1'b1 } }, // 1=live data bit, 0=dead (0)
parameter IN_RESYNC = 0, // 1=resync (double clock) input, 0=no resync
parameter IN_EDGE = 0, // 1=edge (rising) sensitive, 0=level sensitive
parameter [DATA_W-1:0] RESET_VAL = 0 // reset value of latched data
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// bus interface
input wire [ADDR_W-1:0] addr_i, // address
input wire wr_i, // data write enable, active high
input wire rd_i, // data read enable, active high
input wire [DATA_W-1:0] wr_data_i, // write data
output wire [DATA_W-1:0] rd_data_o, // read data
// register interface
output wire reg_wr_o, // reg write active, active high
output wire reg_rd_o, // reg read active, active high
input wire reg_en_i, // reg enable, active high ("DFFE" mode only)
input wire [DATA_W-1:0] reg_data_i, // reg data in
output wire [DATA_W-1:0] reg_data_o // reg data out
);
 
 
/*
----------------------
-- internal signals --
----------------------
*/
wire addr_match;
genvar i;
wire [DATA_W-1:0] in_data, out_data, rd_data;
 
 
/*
================
== code start ==
================
*/
 
 
// check for address match
assign addr_match = ( addr_i == ADDRESS[ADDR_W-1:0] );
 
// decode read & write
assign reg_rd_o = ( rd_i & addr_match );
assign reg_wr_o = ( wr_i & addr_match );
 
 
// generate output logic based on mode
generate
for ( i=0; i<DATA_W; i=i+1 ) begin : output_loop
if ( LIVE_MASK[i] ) begin // live bit
case ( OUT_MODE )
"ZERO" : begin
assign out_data[i] = 1'b0;
end
"THRU" : begin
assign out_data[i] = wr_data_i[i];
end
"LTCH" : begin
reg reg_bit;
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
reg_bit <= RESET_VAL[i];
end else begin
if ( reg_wr_o ) begin
reg_bit <= wr_data_i[i];
end
end
end
assign out_data[i] = reg_bit;
end
"LOOP" : begin
assign out_data[i] = rd_data[i];
end
default : begin // unknown mode!
initial $display ( "OUT_MODE %s does not exist!", OUT_MODE );
end
endcase
end else begin // dead bit
assign out_data[i] = 1'b0;
end
end
endgenerate
 
 
// generate optional input resync & edge detect logic
generate
for ( i=0; i<DATA_W; i=i+1 ) begin : input_processing_loop
if ( LIVE_MASK[i] ) begin // live bit
wire in_2;
if ( IN_RESYNC ) begin
reg in_0, in_1;
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
in_0 <= 1'b0;
in_1 <= 1'b0;
end else begin
in_0 <= reg_data_i[i];
in_1 <= in_0;
end
end
assign in_2 = in_1;
end else begin
assign in_2 = reg_data_i[i];
end
//
if ( IN_EDGE ) begin
reg in_3;
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
in_3 <= 1'b0;
end else begin
in_3 <= in_2;
end
end
assign in_data[i] = ( in_2 & ~in_3 );
end else begin
assign in_data[i] = in_2;
end
end else begin // dead bit
assign in_data[i] = 1'b0;
end // endif
end // endfor
endgenerate
 
 
// generate read logic based on mode
generate
for ( i=0; i<DATA_W; i=i+1 ) begin : read_loop
if ( LIVE_MASK[i] ) begin // live bit
case ( READ_MODE )
"THRU" : begin
assign rd_data[i] = in_data[i];
end
"CORD" : begin
reg reg_bit;
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
reg_bit <= RESET_VAL[i];
end else begin
if ( reg_rd_o ) begin
reg_bit <= 1'b0;
end else begin
reg_bit <= reg_bit | in_data[i];
end
end
end
assign rd_data[i] = reg_bit;
end
"COW1" : begin
reg reg_bit;
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
reg_bit <= RESET_VAL[i];
end else begin
if ( reg_wr_o ) begin
reg_bit <= reg_bit & ~wr_data_i[i];
end else begin
reg_bit <= reg_bit | in_data[i];
end
end
end
assign rd_data[i] = reg_bit;
end
"DFFE" : begin
reg reg_bit;
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
reg_bit <= RESET_VAL[i];
end else if ( reg_en_i ) begin
reg_bit <= in_data[i];
end
end
assign rd_data[i] = reg_bit;
end
"LOOP" : begin
assign rd_data[i] = out_data[i];
end
default : begin // unknown mode!
initial $display ( "RD_MODE %s does not exist!", RD_MODE );
end
endcase
end else begin // dead bit
assign rd_data[i] = 1'b0;
end
end
endgenerate
 
 
// drive outputs
assign rd_data_o = ( addr_match ) ? rd_data : 1'b0;
assign reg_data_o = out_data;
 
 
endmodule
/trunk/v04.05/ep4ce6e22c8_demo_board.cof
0,0 → 1,20
<?xml version="1.0" encoding="US-ASCII" standalone="yes"?>
<cof>
<eprom_name>EPCS16</eprom_name>
<flash_loader_device>EP4CE6</flash_loader_device>
<output_filename>output_file.jic</output_filename>
<n_pages>1</n_pages>
<width>1</width>
<mode>7</mode>
<sof_data>
<user_name>Page_0</user_name>
<page_flags>1</page_flags>
<bit0>
<sof_filename>ep4ce6e22c8_demo_board.sof</sof_filename>
</bit0>
</sof_data>
<version>4</version>
<options>
<map_file>1</map_file>
</options>
</cof>
/trunk/v04.05/alu_mux.v
0,0 → 1,189
/*
--------------------------------------------------------------------------------
 
Module : alu_mux.v
 
--------------------------------------------------------------------------------
 
Function:
- Multiplexer for processor ALU.
 
Instantiates:
- (5x) pipe.v
 
Notes:
- Inputs at stage 1, outputs at stage 6.
- Default behavior is pass-thru.
 
--------------------------------------------------------------------------------
*/
 
module alu_mux
#(
parameter integer DATA_W = 8, // data width
parameter integer ADDR_W = 4 // address width
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// control I/O
input wire sgn_1_i, // 1=signed
input wire hgh_1_i, // 1=high
input wire as_1_i, // 1=add/subtract
input wire ms_1_i, // 1=multiply/shift
input wire rtn_1_i, // 1=return pc
input wire dm_rd_1_i, // 1=read
input wire rg_rd_1_i, // 1=read
// data I/O
input wire [DATA_W-1:0] res_lg_2_i, // logical result
input wire [DATA_W-1:0] res_as_2_i, // add/subtract result
input wire [ADDR_W-1:0] pc_3_i, // program counter
input wire [DATA_W/2-1:0] dm_rd_data_4_i, // dmem read data
input wire [DATA_W/2-1:0] rg_rd_data_4_i, // regs read data
input wire [DATA_W-1:0] res_ms_5_i, // multiply/shift result
output wire [DATA_W-1:0] data_6_o // data out
);
 
/*
----------------------
-- internal signals --
----------------------
*/
wire as_2, rtn_2, sgn_2, rg_rd_2, dm_rd_2, hgh_2, ms_2;
wire rtn_3, sgn_3, rg_rd_3, dm_rd_3, hgh_3, ms_3;
wire sgn_4, rg_rd_4, dm_rd_4, hgh_4, ms_4;
wire ms_5;
wire [DATA_W-1:0] data_3, data_4, data_5;
reg [DATA_W-1:0] mux_2, mux_3, mux_4, mux_5;
 
 
/*
================
== code start ==
================
*/
 
 
// 1 to 2 regs
pipe
#(
.DEPTH ( 1 ),
.WIDTH ( 7 ),
.RESET_VAL ( 0 )
)
regs_1_2
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { as_1_i, rtn_1_i, sgn_1_i, rg_rd_1_i, dm_rd_1_i, hgh_1_i, ms_1_i } ),
.data_o ( { as_2, rtn_2, sgn_2, rg_rd_2, dm_rd_2, hgh_2, ms_2 } )
);
 
 
// mux 2
always @ ( * ) begin
casex ( as_2 )
'b1 : mux_2 <= res_as_2_i;
default : mux_2 <= res_lg_2_i; // default is thru
endcase
end
 
 
// 2 to 3 regs
pipe
#(
.DEPTH ( 1 ),
.WIDTH ( 6+DATA_W ),
.RESET_VAL ( 0 )
)
regs_2_3
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { rtn_2, sgn_2, rg_rd_2, dm_rd_2, hgh_2, ms_2, mux_2 } ),
.data_o ( { rtn_3, sgn_3, rg_rd_3, dm_rd_3, hgh_3, ms_3, data_3 } )
);
 
 
// mux 3
always @ ( * ) begin
casex ( rtn_3 )
'b1 : mux_3 <= pc_3_i; // unsigned
default : mux_3 <= data_3; // default is thru
endcase
end
 
 
// 3 to 4 regs
pipe
#(
.DEPTH ( 1 ),
.WIDTH ( 5+DATA_W ),
.RESET_VAL ( 0 )
)
regs_3_4
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { sgn_3, rg_rd_3, dm_rd_3, hgh_3, ms_3, mux_3 } ),
.data_o ( { sgn_4, rg_rd_4, dm_rd_4, hgh_4, ms_4, data_4 } )
);
 
 
// mux 4
always @ ( * ) begin
casex ( { rg_rd_4, dm_rd_4, hgh_4, sgn_4 } )
'b0100 : mux_4 <= dm_rd_data_4_i;
'b0101 : mux_4 <= $signed( dm_rd_data_4_i );
'b011x : mux_4 <= { dm_rd_data_4_i, data_4[DATA_W/2-1:0] };
'b1x0x : mux_4 <= $signed( rg_rd_data_4_i );
'b1x1x : mux_4 <= { rg_rd_data_4_i, data_4[DATA_W/2-1:0] };
default : mux_4 <= data_4; // default is thru
endcase
end
 
 
// 4 to 5 regs
pipe
#(
.DEPTH ( 1 ),
.WIDTH ( 1+DATA_W ),
.RESET_VAL ( 0 )
)
regs_4_5
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { ms_4, mux_4 } ),
.data_o ( { ms_5, data_5 } )
);
 
 
// mux 5
always @ ( * ) begin
casex ( ms_5 )
'b1 : mux_5 <= res_ms_5_i;
default : mux_5 <= data_5; // default is thru
endcase
end
 
 
// 5 to 6 regs
pipe
#(
.DEPTH ( 1 ),
.WIDTH ( DATA_W ),
.RESET_VAL ( 0 )
)
d_out_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( mux_5 ),
.data_o ( data_6_o )
);
 
endmodule
/trunk/v04.05/alu_logical.v
0,0 → 1,181
/*
--------------------------------------------------------------------------------
 
Module : alu_logical.v
 
--------------------------------------------------------------------------------
 
Function:
- Logic unit for a processor ALU.
 
Instantiates:
- (4x) pipe.v
- (1x) lg_sel_encode.h
 
Notes:
- IN/MID/OUT/FLG optionally registered.
- Default path through is copy.
 
--------------------------------------------------------------------------------
*/
 
module alu_logical
#(
parameter integer REGS_IN = 1, // register option for inputs
parameter integer REGS_MID = 1, // mid register option
parameter integer REGS_OUT = 1, // register option for outputs
parameter integer REGS_FLG = 1, // register option for flag outputs
parameter integer DATA_W = 32, // data width
parameter integer LG_SEL_W = 4 // operation width
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// control I/O
input wire [LG_SEL_W-1:0] lg_sel_i, // operation (see lg_sel_encode.h)
// data I/O
input wire [DATA_W-1:0] a_i, // operand
input wire [DATA_W-1:0] b_i, // operand
output wire [DATA_W-1:0] result_o, // logical result
// flags
output wire flg_nz_o, // a != 0
output wire flg_lz_o // a < 0
);
 
/*
----------------------
-- internal signals --
----------------------
*/
`include "lg_sel_encode.h"
`include "functions.h" // for clog2(), flip_32(), lzc_32()
localparam integer LZC_W = clog2( DATA_W ) + 1;
//
wire [LG_SEL_W-1:0] lg_sel, lg_sel_m;
wire [DATA_W-1:0] a, b;
reg [DATA_W-1:0] res_1op, res_2op;
wire [DATA_W-1:0] res_1op_m, res_2op_m;
reg res_br;
wire res_br_m;
reg [DATA_W-1:0] result;
wire flg_nz, flg_lz;
 
 
/*
================
== code start ==
================
*/
 
 
// optional input registers
pipe
#(
.DEPTH ( REGS_IN ),
.WIDTH ( LG_SEL_W+DATA_W+DATA_W ),
.RESET_VAL ( 0 )
)
in_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { lg_sel_i, b_i, a_i, } ),
.data_o ( { lg_sel, b, a } )
);
 
 
// flags
assign flg_nz = |a;
assign flg_lz = a[DATA_W-1];
 
// multiplex one operand results
always @ ( * ) begin
case ( lg_sel )
`lg_nsg : res_1op <= { ~b[DATA_W-1], b[DATA_W-2:0] };
`lg_not : res_1op <= ~b;
`lg_flp : res_1op <= flip_32( b );
`lg_lzc : res_1op <= lzc_32( b );
default : res_1op <= b; // default is copy
endcase
end
 
// multiplex one operand bit reduction results
always @ ( * ) begin
case ( lg_sel )
`lg_bro : res_br <= |b;
`lg_brx : res_br <= ^b;
default : res_br <= &b;
endcase
end
 
// multiplex two operand results
always @ ( * ) begin
case ( lg_sel )
`lg_orr : res_2op <= a | b;
`lg_xor : res_2op <= a ^ b;
default : res_2op <= a & b;
endcase
end
 
 
// optional flag regs
pipe
#(
.DEPTH ( REGS_FLG ),
.WIDTH ( 2 ),
.RESET_VAL ( 0 )
)
regs_flags
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { flg_nz, flg_lz, } ),
.data_o ( { flg_nz_o, flg_lz_o } )
);
 
 
// optional mid regs
pipe
#(
.DEPTH ( REGS_MID ),
.WIDTH ( LG_SEL_W+1+DATA_W+DATA_W ),
.RESET_VAL ( 0 )
)
mid_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { lg_sel, res_br, res_2op, res_1op } ),
.data_o ( { lg_sel_m, res_br_m, res_2op_m, res_1op_m } )
);
 
 
// multiplex
always @ ( * ) begin
case ( lg_sel_m )
`lg_bra, `lg_bro, `lg_brx : result <= { DATA_W{ res_br_m } };
`lg_and, `lg_orr, `lg_xor : result <= res_2op_m;
default : result <= res_1op_m; // default is copy
endcase
end
 
 
// optional output regs
pipe
#(
.DEPTH ( REGS_OUT ),
.WIDTH ( DATA_W ),
.RESET_VAL ( 0 )
)
out_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( result ),
.data_o ( result_o )
);
 
 
endmodule
/trunk/v04.05/tst_decode.v
0,0 → 1,118
/*
--------------------------------------------------------------------------------
 
Module : tst_decode.v
 
--------------------------------------------------------------------------------
 
Function:
- Processor test decoding for conditional jumps, etc.
 
Instantiates:
- (2x) pipe.v
- (1x) tst_encode.h
 
Notes:
- Parameterized register(s) @ test inputs.
- Parameterized register(s) @ output.
 
--------------------------------------------------------------------------------
*/
 
module tst_decode
#(
parameter integer REGS_TST = 0, // reg option input to test
parameter integer REGS_OUT = 0, // reg option test to output
parameter integer TST_W = 4 // test field width
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// flags (combinatorial)
input wire flg_nz_i, // a != 0
input wire flg_lz_i, // a < 0
input wire flg_ne_i, // a != b
input wire flg_lt_i, // a < b
// tests (optionally registered)
input wire cnd_i, // 1=conditional
input wire [TST_W-1:0] tst_i, // test field (see tst_encode.h)
// output (optionally registered)
output wire result_o // 1=true; 0=false
);
 
/*
----------------------
-- internal signals --
----------------------
*/
`include "tst_encode.h"
wire cnd, zro;
wire [TST_W-1:0] tst;
reg res;
wire result;
 
 
/*
================
== code start ==
================
*/
 
 
// input to test regs
pipe
#(
.DEPTH ( REGS_TST ),
.WIDTH ( 1+TST_W ),
.RESET_VAL ( 0 )
)
tst_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { cnd_i, tst_i } ),
.data_o ( { cnd, tst } )
);
 
 
// mux
always @ ( * ) begin
case ( tst )
`z : res <= ~flg_nz_i;
`nz : res <= flg_nz_i;
`lz : res <= flg_lz_i;
`nlz : res <= ~flg_lz_i;
`e : res <= ~flg_ne_i;
`ne : res <= flg_ne_i;
`ls : res <= flg_lt_i;
`nls : res <= ~flg_lt_i;
`lu : res <= flg_lt_i;
`nlu : res <= ~flg_lt_i;
default : res <= 1'b1; // benign default
endcase
end
 
// output result if conditional, output 1 if not
assign result = ( cnd ) ? res : 1'b1;
 
// result to output regs
pipe
#(
.DEPTH ( REGS_OUT ),
.WIDTH ( 1 ),
.RESET_VAL ( 0 )
)
out_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( result ),
.data_o ( result_o )
);
 
 
endmodule
/trunk/v04.05/pc_ring.v
0,0 → 1,202
/*
--------------------------------------------------------------------------------
 
Module : pc_ring.v
 
--------------------------------------------------------------------------------
 
Function:
- Processor PC storage ring.
 
Instantiates:
- (2x) pipe.v
 
Notes:
- 8 stages.
- Loop feedback, so PC interstage pipe registering forms a storage ring.
 
--------------------------------------------------------------------------------
*/
 
module pc_ring
#(
parameter integer THREADS = 8, // threads
parameter integer THRD_W = 3, // thread width
parameter integer DATA_W = 32, // data width
parameter integer ADDR_W = 16, // address width
parameter [ADDR_W-1:0] CLR_BASE = 'h0, // clear address base (concat)
parameter integer CLR_SPAN = 2, // clear address span (2^n)
parameter [ADDR_W-1:0] INTR_BASE = 'h20, // interrupt address base (concat)
parameter integer INTR_SPAN = 2 // interrupt address span (2^n)
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// control I/O
input wire [THRD_W-1:0] thrd_0_i, // thread
input wire [THRD_W-1:0] thrd_4_i, // thread
input wire clr_i, // 1=pc clear
input wire lit_i, // 1 : pc=pc++ for literal data
input wire jmp_i, // 1 : pc=pc+B|I for jump (cond)
input wire gto_i, // 1 : pc=B for goto | gosub (cond)
input wire intr_i, // 1 : pc=int
input wire res_tst_3_i, // 1=true (or disabled); 0=false
// address I/O
input wire [ADDR_W-1:0] b_addr_i, // b | im
output wire [ADDR_W-1:0] pc_0_o,
output wire [ADDR_W-1:0] pc_1_o,
output wire [ADDR_W-1:0] pc_2_o,
output wire [ADDR_W-1:0] pc_3_o,
output wire [ADDR_W-1:0] pc_4_o,
output wire [ADDR_W-1:0] pc_5_o,
output wire [ADDR_W-1:0] pc_6_o,
output wire [ADDR_W-1:0] pc_7_o
);
 
/*
----------------------
-- internal signals --
----------------------
*/
reg [ADDR_W-1:0] pc[0:THREADS-1];
//
wire [ADDR_W-1:0] clr_addr_0, intr_addr_4;
wire intr_2, gto_2, jmp_2, lit_2;
wire intr_3, gto_3, jmp_3;
wire intr_4;
wire signed [ADDR_W-1:0] b_addr_2, b_addr_3;
reg [ADDR_W-1:0] mux_0, mux_2, mux_3, mux_4;
 
 
/*
================
== code start ==
================
*/
 
// form the clear address
assign clr_addr_0[ADDR_W-1:THRD_W+CLR_SPAN] = CLR_BASE[ADDR_W-1:THRD_W+CLR_SPAN];
assign clr_addr_0[THRD_W+CLR_SPAN-1:0] = thrd_0_i << CLR_SPAN;
 
// mux for clear, next instruction
always @ ( * ) begin
casex ( { clr_i, intr_i } )
'b01 : mux_0 <= pc[0]; // no change for int
'b1x : mux_0 <= clr_addr_0; // clear
default : mux_0 <= pc[0] + 1'b1; // inc for next
endcase
end
 
// 0 to 2 regs
pipe
#(
.DEPTH ( 2 ),
.WIDTH ( 4+ADDR_W ),
.RESET_VAL ( 0 )
)
regs_0_2
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { lit_i, jmp_i, gto_i, intr_i, b_addr_i } ),
.data_o ( { lit_2, jmp_2, gto_2, intr_2, b_addr_2 } )
);
 
 
// mux for literal data
always @ ( * ) begin
casex ( lit_2 )
'b1 : mux_2 <= pc[2] + 1'b1; // literal data
default : mux_2 <= pc[2]; // no change
endcase
end
 
 
// 2 to 3 regs
pipe
#(
.DEPTH ( 1 ),
.WIDTH ( 3+ADDR_W ),
.RESET_VAL ( 0 )
)
regs_2_3
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { jmp_2, gto_2, intr_2, b_addr_2 } ),
.data_o ( { jmp_3, gto_3, intr_3, b_addr_3 } )
);
 
 
// mux for jmp, gto, gsb
always @ ( * ) begin
casex ( { res_tst_3_i, gto_3, jmp_3 } )
'b101 : mux_3 <= pc[3] + b_addr_3; // jmp | jmp_i
'b11x : mux_3 <= b_addr_3; // gto | gsb
default : mux_3 <= pc[3]; // no change
endcase
end
 
 
// 3 to 4 regs
pipe
#(
.DEPTH ( 1 ),
.WIDTH ( 1 ),
.RESET_VAL ( 0 )
)
regs_3_4
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( intr_3 ),
.data_o ( intr_4 )
);
 
 
// form the interrupt address
assign intr_addr_4[ADDR_W-1:THRD_W+INTR_SPAN] = INTR_BASE[ADDR_W-1:THRD_W+INTR_SPAN];
assign intr_addr_4[THRD_W+INTR_SPAN-1:0] = thrd_4_i << INTR_SPAN;
 
// mux for interrupt
always @ ( * ) begin
casex ( intr_4 )
'b1 : mux_4 <= intr_addr_4; // interrupt
default : mux_4 <= pc[4]; // no change
endcase
end
 
// pc storage ring
integer j;
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
for ( j = 0; j < THREADS; j = j + 1 ) begin
pc[j] <= 'b0;
end
end else begin
for ( j = 0; j < THREADS; j = j + 1 ) begin
if ( j == 0 ) pc[j] <= pc[THREADS-1]; // wrap around
else if ( j == 1 ) pc[j] <= mux_0;
else if ( j == 3 ) pc[j] <= mux_2;
else if ( j == 4 ) pc[j] <= mux_3;
else if ( j == 5 ) pc[j] <= mux_4;
else pc[j] <= pc[j-1];
end
end
end
 
// output pc
assign pc_0_o = pc[0];
assign pc_1_o = pc[1];
assign pc_2_o = pc[2];
assign pc_3_o = pc[3];
assign pc_4_o = mux_4; // note: async!
assign pc_5_o = pc[5];
assign pc_6_o = pc[6];
assign pc_7_o = pc[7];
 
 
endmodule
/trunk/v04.05/op_decode.v
0,0 → 1,683
/*
--------------------------------------------------------------------------------
 
Module : op_decode.v
 
--------------------------------------------------------------------------------
 
Function:
- Opcode decoder for processor.
 
Instantiates:
- (2x) pipe.v
- (1x) op_encode.h
 
Notes:
- I/O optionally registered.
- Middle register is always present.
- Operates on the current thread in the stage.
 
--------------------------------------------------------------------------------
*/
 
module op_decode
#(
parameter integer REGS_IN = 1, // register option for inputs
parameter integer REGS_OUT = 1, // register option for outputs
parameter integer STACKS = 8, // number of stacks
parameter integer STK_W = 3, // stack selector width
parameter integer DATA_W = 32, // data width
parameter integer IM_W = 6, // immediate width
parameter integer MEM_DATA_W = 16, // op code width
parameter integer LG_SEL_W = 4, // logical operation width
parameter integer TST_W = 4 // test field width
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// state I/O
input wire thrd_clr_i, // thread clear
input wire thrd_intr_i, // thread interrupt
input wire [MEM_DATA_W-1:0] op_code_i, // op_code
output wire op_code_er_o, // 1=illegal op code encountered
// data I/O
output wire [IM_W-1:0] im_o, // immediate
// pc pipe control
output wire pc_clr_o, // 1 : pc clear
output wire cnd_o, // 1 : conditional
output wire lit_o, // 1 : pc=pc++ for literal data
output wire jmp_o, // 1 : pc=pc+B|I for jump (cond)
output wire gto_o, // 1 : pc=B for goto / gosub
output wire intr_o, // 1 : pc=intr
// conditional masks
output wire [TST_W-1:0] tst_o, // test field (see tst_encode.h)
// stacks control
output wire stk_clr_o, // stacks clear
output wire [STACKS-1:0] pop_o, // stacks pop
output wire [STACKS-1:0] push_o, // stacks push
// alu control
output wire [STK_W-1:0] data_sel_a_o, // a stack selector
output wire [STK_W-1:0] data_sel_b_o, // b stack selector
output wire [STK_W-1:0] addr_sel_b_o, // b stack selector
output wire imda_o, // 1=immediate data
output wire imad_o, // 1=immediate address
output wire sgn_o, // 1=signed
output wire ext_o, // 1=extended
output wire hgh_o, // 1=high
output wire [LG_SEL_W-1:0] lg_sel_o, // logic operation (see lg_sel_encode.h)
output wire add_o, // 1=add
output wire sub_o, // 1=subtract
output wire mul_o, // 1=multiply
output wire shl_o, // 1=shift left
output wire pow_o, // 1=power of 2
output wire rtn_o, // 1=return pc
output wire dm_rd_o, // 1=read
output wire dm_wr_o, // 1=write
output wire rg_rd_o, // 1=read
output wire rg_wr_o // 1=write
);
 
/*
----------------------
-- internal signals --
----------------------
*/
`include "lg_sel_encode.h"
`include "tst_encode.h"
`include "op_encode.h"
//
wire thrd_clr, thrd_intr;
wire [MEM_DATA_W-1:0] op_code;
reg op_ok;
reg [4:0] op_code_ok;
wire op_code_er;
//
reg [IM_W-1:0] im;
reg pc_clr;
reg intr, gto, jmp, lit, cnd;
reg [TST_W-1:0] tst;
reg stk_clr;
reg [4:0] push_a;
reg [4:0] pop_a, pop_b;
wire [STACKS-1:0] pop, push;
reg [STK_W-1:0] data_sel_a, data_sel_b, addr_sel_b;
reg imda;
reg imad;
reg rtn, pow, shl, mul, sub, add, hgh, ext, sgn;
reg [LG_SEL_W-1:0] lg_sel;
reg dm_rd, dm_wr, rg_rd, rg_wr;
reg [STACKS-1:0] pop_all;
 
 
 
/*
================
== code start ==
================
*/
 
 
// optional input registers
pipe
#(
.DEPTH ( REGS_IN ),
.WIDTH ( 2+MEM_DATA_W ),
.RESET_VAL ( 0 )
)
in_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { thrd_clr_i, thrd_intr_i, op_code_i } ),
.data_o ( { thrd_clr, thrd_intr, op_code } )
);
 
 
// instantiate & split out op_code fields
wire [2:0] op_code_sa = op_code[2:0];
wire op_code_pa = op_code[3];
wire [2:0] op_code_sb = op_code[6:4];
wire op_code_pb = op_code[7];
wire [3:0] op_code_th = op_code[15:12];
wire [3:0] op_code_tm = { 2'b00, op_code[11:10] };
wire [3:0] op_code_tl = { 2'b00, op_code[9:8] };
wire [5:0] op_code_i4 = $signed( op_code[11:8] );
wire [5:0] op_code_i6 = op_code[9:4];
wire [7:0] op_code_pf = op_code[7:0];
//
reg [2:0] sa_reg, sb_reg;
 
 
// mid register if & case: clear, interrupt, and op_code decode
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
op_ok <= 'b0;
op_code_ok <= 'b0;
pc_clr <= 'b0;
cnd <= 'b0;
lit <= 'b0;
jmp <= 'b0;
gto <= 'b0;
intr <= 'b0;
tst <= 'b0;
stk_clr <= 'b0;
pop_all <= 'b0;
pop_a <= 'b0;
pop_b <= 'b0;
push_a <= 'b0;
data_sel_a <= 'b0;
data_sel_b <= 'b0;
addr_sel_b <= 'b0;
imda <= 'b0;
imad <= 'b0;
im <= 'b0;
sgn <= 'b0;
ext <= 'b0;
hgh <= 'b0;
lg_sel <= `lg_cpy;
add <= 'b0;
sub <= 'b0;
mul <= 'b0;
shl <= 'b0;
pow <= 'b0;
rtn <= 'b0;
dm_rd <= 'b0;
dm_wr <= 'b0;
rg_rd <= 'b0;
rg_wr <= 'b0;
sa_reg <= 'b0;
sb_reg <= 'b0;
end else begin
// default values
op_ok <= 'b0; // default is bad op
op_code_ok <= 'b0; // default is bad opcode
pc_clr <= 'b0; // default is no pc clear
cnd <= 'b0; // default is unconditional
lit <= 'b0; // default is no follow
jmp <= 'b0; // default is no jump
gto <= 'b0; // default is no goto
intr <= 'b0; // default is no interrupt
tst <= op_code_tl; // default is low test field
stk_clr <= 'b0; // default is no stack clear
pop_all <= 'b0; // default is no pop
pop_a <= 'b0; // default is no pop
pop_b <= 'b0; // default is no pop
push_a <= 'b0; // default is no push
data_sel_a <= op_code_sa; // default is op_code directive
data_sel_b <= op_code_sb; // default is op_code directive
addr_sel_b <= op_code_sb; // default is op_code directive
imda <= 'b0; // default is not immediate data
imad <= 'b0; // default is not immediate address
im <= op_code_i6; // default is full width
sgn <= 'b0; // default is unsigned
hgh <= 'b0; // default is not high
ext <= 'b0; // default is unextended
lg_sel <= `lg_cpy; // default is thru
add <= 'b0; // default is thru
sub <= 'b0; // default is thru
mul <= 'b0; // default is thru
shl <= 'b0; // default is thru
pow <= 'b0; // default is thru
rtn <= 'b0; // default is thru
dm_rd <= 'b0; // default is don't read
dm_wr <= 'b0; // default is don't write
rg_rd <= 'b0; // default is don't read
rg_wr <= 'b0; // default is don't write
sa_reg <= op_code_sa; // default is follow op_code
sb_reg <= op_code_sb; // default is follow op_code
if ( thrd_clr ) begin
op_ok <= 'b1; // good op
pc_clr <= 'b1; // clear pc
stk_clr <= 'b1; // clear stacks
end else if ( thrd_intr ) begin
op_ok <= 'b1; // good op
intr <= 'b1; // don't inc PC
push_a[0] <= 'b1; // push
data_sel_a <= 'b0; // push return address to stack 0
rtn <= 'b1; // push pc
end else begin
casex ( op_code )
////////////////////
// group 0 - misc //
////////////////////
op_nop : begin
op_code_ok[0] <= 'b1;
end
op_pop : begin
op_code_ok[0] <= 'b1;
pop_all <= op_code_pf;
end
op_pgc : begin
op_code_ok[0] <= 'b1;
pop_a[0] <= op_code_pa;
pop_b[0] <= op_code_pb;
push_a[0] <= 'b1; // push
rtn <= 'b1; // push pc
end
op_lit_s : begin
op_code_ok[0] <= 'b1;
pop_a[0] <= op_code_pa;
pop_b[0] <= op_code_pb;
push_a[0] <= 'b1; // push
lit <= 'b1; // lit
dm_rd <= 'b1; // dm
sgn <= 'b1; // signed
end
op_lit_h : begin
op_code_ok[0] <= 'b1;
pop_a[0] <= op_code_pa;
pop_b[0] <= op_code_pb;
push_a[0] <= 'b1; // push
data_sel_b <= op_code_sa; // route A thru ALU bypass
lit <= 'b1; // lit
dm_rd <= 'b1; // dm
hgh <= 'b1; // high
end
op_lit_u : begin
op_code_ok[0] <= 'b1;
pop_a[0] <= op_code_pa;
pop_b[0] <= op_code_pb;
push_a[0] <= 'b1; // push
lit <= 'b1; // lit
dm_rd <= 'b1; // dm
end
op_reg_rs : begin
op_code_ok[0] <= 'b1;
pop_a[0] <= op_code_pa;
pop_b[0] <= op_code_pb;
push_a[0] <= 'b1; // push
rg_rd <= 'b1; // read
sgn <= 'b1; // signed
end
op_reg_rh : begin
op_code_ok[0] <= 'b1;
pop_a[0] <= op_code_pa;
pop_b[0] <= op_code_pb;
push_a[0] <= 'b1; // push
data_sel_b <= op_code_sa; // route A thru ALU bypass
rg_rd <= 'b1; // read
hgh <= 'b1; // high
end
op_reg_w : begin
op_code_ok[0] <= 'b1;
pop_a[0] <= op_code_pa;
pop_b[0] <= op_code_pb;
rg_wr <= 'b1; // write
end
op_reg_wh : begin
op_code_ok[0] <= 'b1;
pop_a[0] <= op_code_pa;
pop_b[0] <= op_code_pb;
rg_wr <= 'b1; // write
hgh <= 'b1; // high
end
///////////////////////
// group 1 - logical //
///////////////////////
op_cpy : begin
op_code_ok[1] <= 'b1;
pop_a[1] <= op_code_pa;
pop_b[1] <= op_code_pb;
push_a[1] <= 'b1; // push
lg_sel <= `lg_cpy;
end
op_nsg : begin
op_code_ok[1] <= 'b1;
pop_a[1] <= op_code_pa;
pop_b[1] <= op_code_pb;
push_a[1] <= 'b1; // push
lg_sel <= `lg_nsg;
end
op_not : begin
op_code_ok[1] <= 'b1;
pop_a[1] <= op_code_pa;
pop_b[1] <= op_code_pb;
push_a[1] <= 'b1; // push
lg_sel <= `lg_not;
end
op_flp : begin
op_code_ok[1] <= 'b1;
pop_a[1] <= op_code_pa;
pop_b[1] <= op_code_pb;
push_a[1] <= 'b1; // push
lg_sel <= `lg_flp;
end
op_lzc : begin
op_code_ok[1] <= 'b1;
pop_a[1] <= op_code_pa;
pop_b[1] <= op_code_pb;
push_a[1] <= 'b1; // push
lg_sel <= `lg_lzc;
end
op_bra : begin
op_code_ok[1] <= 'b1;
pop_a[1] <= op_code_pa;
pop_b[1] <= op_code_pb;
push_a[1] <= 'b1; // push
lg_sel <= `lg_bra;
end
op_bro : begin
op_code_ok[1] <= 'b1;
pop_a[1] <= op_code_pa;
pop_b[1] <= op_code_pb;
push_a[1] <= 'b1; // push
lg_sel <= `lg_bro;
end
op_brx : begin
op_code_ok[1] <= 'b1;
pop_a[1] <= op_code_pa;
pop_b[1] <= op_code_pb;
push_a[1] <= 'b1; // push
lg_sel <= `lg_brx;
end
op_and : begin
op_code_ok[1] <= 'b1;
pop_a[1] <= op_code_pa;
pop_b[1] <= op_code_pb;
push_a[1] <= 'b1; // push
lg_sel <= `lg_and;
end
op_orr : begin
op_code_ok[1] <= 'b1;
pop_a[1] <= op_code_pa;
pop_b[1] <= op_code_pb;
push_a[1] <= 'b1; // push
lg_sel <= `lg_orr;
end
op_xor : begin
op_code_ok[1] <= 'b1;
pop_a[1] <= op_code_pa;
pop_b[1] <= op_code_pb;
push_a[1] <= 'b1; // push
lg_sel <= `lg_xor;
end
//////////////////////////
// group 2 - arithmetic //
//////////////////////////
op_add : begin
op_code_ok[2] <= 'b1;
pop_a[2] <= op_code_pa;
pop_b[2] <= op_code_pb;
push_a[2] <= 'b1; // push
add <= 'b1; // add
end
op_add_xs : begin
op_code_ok[2] <= 'b1;
pop_a[2] <= op_code_pa;
pop_b[2] <= op_code_pb;
push_a[2] <= 'b1; // push
add <= 'b1; // add
ext <= 'b1; // extended
sgn <= 'b1; // signed
end
op_add_xu : begin
op_code_ok[2] <= 'b1;
pop_a[2] <= op_code_pa;
pop_b[2] <= op_code_pb;
push_a[2] <= 'b1; // push
add <= 'b1; // add
ext <= 'b1; // extended
end
op_sub : begin
op_code_ok[2] <= 'b1;
pop_a[2] <= op_code_pa;
pop_b[2] <= op_code_pb;
push_a[2] <= 'b1; // push
sub <= 'b1; // sub
end
op_sub_xs : begin
op_code_ok[2] <= 'b1;
pop_a[2] <= op_code_pa;
pop_b[2] <= op_code_pb;
push_a[2] <= 'b1; // push
sub <= 'b1; // sub
ext <= 'b1; // extended
sgn <= 'b1; // signed
end
op_sub_xu : begin
op_code_ok[2] <= 'b1;
pop_a[2] <= op_code_pa;
pop_b[2] <= op_code_pb;
push_a[2] <= 'b1; // push
sub <= 'b1; // sub
ext <= 'b1; // extended
end
op_mul : begin
op_code_ok[2] <= 'b1;
pop_a[2] <= op_code_pa;
pop_b[2] <= op_code_pb;
push_a[2] <= 'b1; // push
mul <= 'b1; // multiply
end
op_mul_xs : begin
op_code_ok[2] <= 'b1;
pop_a[2] <= op_code_pa;
pop_b[2] <= op_code_pb;
push_a[2] <= 'b1; // push
mul <= 'b1; // multiply
ext <= 'b1; // extended
sgn <= 'b1; // signed
end
op_mul_xu : begin
op_code_ok[2] <= 'b1;
pop_a[2] <= op_code_pa;
pop_b[2] <= op_code_pb;
push_a[2] <= 'b1; // push
mul <= 'b1; // multiply
ext <= 'b1; // extended
end
op_shl_s : begin
op_code_ok[2] <= 'b1;
pop_a[2] <= op_code_pa;
pop_b[2] <= op_code_pb;
push_a[2] <= 'b1; // push
shl <= 'b1; // shift left
sgn <= 'b1; // signed
end
op_shl_u : begin
op_code_ok[2] <= 'b1;
pop_a[2] <= op_code_pa;
pop_b[2] <= op_code_pb;
push_a[2] <= 'b1; // push
shl <= 'b1; // shift left
end
op_pow : begin
op_code_ok[2] <= 'b1;
pop_a[2] <= op_code_pa;
pop_b[2] <= op_code_pb;
push_a[2] <= 'b1; // push
pow <= 'b1; // power of 2
end
////////////////////////
// group 3 - branches //
////////////////////////
op_jmp_z, op_jmp_nz, op_jmp_lz, op_jmp_nlz : begin
op_code_ok[3] <= 'b1;
pop_a[3] <= op_code_pa;
pop_b[3] <= op_code_pb;
jmp <= 'b1; // jump
cnd <= 'b1; // conditional
tst <= op_code_tl; // lo test field
end
op_jmp : begin
op_code_ok[3] <= 'b1;
pop_a[3] <= op_code_pa;
pop_b[3] <= op_code_pb;
jmp <= 'b1; // jump
end
op_gto : begin
op_code_ok[3] <= 'b1;
pop_a[3] <= op_code_pa;
pop_b[3] <= op_code_pb;
gto <= 'b1; // goto
end
op_gsb : begin
op_code_ok[3] <= 'b1;
pop_a[3] <= op_code_pa;
pop_b[3] <= op_code_pb;
push_a[3] <= 'b1; // push
gto <= 'b1; // goto
rtn <= 'b1; // push pc
end
//////////////////////////
// group 4 - immediates //
//////////////////////////
///////////////////////////////////
// immediate memory read & write //
///////////////////////////////////
op_mem_irs : begin
op_code_ok[4] <= 'b1;
pop_a[4] <= op_code_pa;
pop_b[4] <= op_code_pb;
push_a[4] <= 'b1; // push
im <= op_code_i4; // small im
dm_rd <= 'b1; // read
sgn <= 'b1; // signed
end
op_mem_irh : begin
op_code_ok[4] <= 'b1;
pop_a[4] <= op_code_pa;
pop_b[4] <= op_code_pb;
push_a[4] <= 'b1; // push
im <= op_code_i4; // small im
data_sel_b <= op_code_sa; // route A thru ALU bypass
dm_rd <= 'b1; // read
hgh <= 'b1; // high
end
op_mem_iw : begin
op_code_ok[4] <= 'b1;
pop_a[4] <= op_code_pa;
pop_b[4] <= op_code_pb;
im <= op_code_i4; // small im
dm_wr <= 'b1; // write
end
op_mem_iwh : begin
op_code_ok[4] <= 'b1;
pop_a[4] <= op_code_pa;
pop_b[4] <= op_code_pb;
im <= op_code_i4; // small im
dm_wr <= 'b1; // write
hgh <= 'b1; // high
end
/////////////////////////////////
// immediate conditional jumps //
/////////////////////////////////
op_jmp_ie, op_jmp_ine, op_jmp_ilu, op_jmp_inlu : begin
op_code_ok[4] <= 'b1;
pop_a[4] <= op_code_pa;
pop_b[4] <= op_code_pb;
jmp <= 'b1; // jump
cnd <= 'b1; // conditional
imad <= 'b1; // immediate address
im <= op_code_i4; // small im
tst <= op_code_th; // hi test field
end
op_jmp_ils, op_jmp_inls : begin
op_code_ok[4] <= 'b1;
pop_a[4] <= op_code_pa;
pop_b[4] <= op_code_pb;
jmp <= 'b1; // jump
cnd <= 'b1; // conditional
imad <= 'b1; // immediate address
im <= op_code_i4; // small im
tst <= op_code_th; // hi test field
sgn <= 'b1; // signed
end
op_jmp_iz, op_jmp_inz, op_jmp_ilz, op_jmp_inlz : begin
op_code_ok[4] <= 'b1;
pop_a[4] <= op_code_pa;
jmp <= 'b1; // jump
cnd <= 'b1; // conditional
imad <= 'b1; // immediate address
tst <= op_code_tm; // mid test field
end
////////////////////
// immediate data //
////////////////////
op_dat_is : begin
op_code_ok[4] <= 'b1;
pop_a[4] <= op_code_pa;
push_a[4] <= 'b1; // push
imda <= 'b1; // immediate b data
sgn <= 'b1; // signed
end
///////////////////
// immediate add //
///////////////////
op_add_is : begin
op_code_ok[4] <= 'b1;
pop_a[4] <= op_code_pa;
push_a[4] <= 'b1; // push
imda <= 'b1; // immediate b data
add <= 'b1; // add
sgn <= 'b1; // signed
end
//////////////////////
// immediate shifts //
//////////////////////
op_shl_is : begin
op_code_ok[4] <= 'b1;
pop_a[4] <= op_code_pa;
push_a[4] <= 'b1; // push
imda <= 'b1; // immediate b data
shl <= 'b1; // shift left
sgn <= 'b1; // signed
end
op_psu_i : begin
op_code_ok[4] <= 'b1;
pop_a[4] <= op_code_pa;
push_a[4] <= 'b1; // push
imda <= 'b1; // immediate b data
shl <= 'b1; // shift left
pow <= 'b1; // power of 2
end
default: begin
// nothing here
end
endcase
end
end
end
 
// decode pop & push (note: use registered select fields here)
assign pop = ( ( |pop_a ) << sa_reg ) | ( ( |pop_b ) << sb_reg ) | pop_all;
assign push = ( |push_a ) << sa_reg;
// decode errors
assign op_code_er = ~( op_ok | ( |op_code_ok ) );
 
 
// optional output registers
pipe
#(
.DEPTH ( REGS_OUT ),
.WIDTH ( TST_W+LG_SEL_W+STACKS+STACKS+STK_W+STK_W+STK_W+IM_W ),
.RESET_VAL ( 0 )
)
out_regs_vectors
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { tst, lg_sel, push, pop, addr_sel_b, data_sel_b, data_sel_a, im } ),
.data_o ( { tst_o, lg_sel_o, push_o, pop_o, addr_sel_b_o, data_sel_b_o, data_sel_a_o, im_o } )
);
 
 
pipe
#(
.DEPTH ( REGS_OUT ),
.WIDTH ( 23 ),
.RESET_VAL ( 0 )
)
out_regs_singles
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { op_code_er, pc_clr, cnd, lit, jmp, gto, intr, stk_clr, imda, imad, sgn, ext, hgh, add, sub, mul, shl, pow, rtn, dm_rd, dm_wr, rg_rd, rg_wr } ),
.data_o ( { op_code_er_o, pc_clr_o, cnd_o, lit_o, jmp_o, gto_o, intr_o, stk_clr_o, imda_o, imad_o, sgn_o, ext_o, hgh_o, add_o, sub_o, mul_o, shl_o, pow_o, rtn_o, dm_rd_o, dm_wr_o, rg_rd_o, rg_wr_o } )
);
 
 
endmodule
/trunk/v04.05/COPYRIGHT.txt
0,0 → 1,2
Copyright (c) Eric David Wallin, 2013, 2014.
Permission to use, copy, modify, and/or distribute this design for any purpose without fee is hereby granted, provided it is not used for spying or "surveillance" uses, military or "defense" projects, weaponry, or other nefarious purposes. Furthermore the above copyright and this permission notice must appear in all copies.
/trunk/v04.05/uart_core.v
0,0 → 1,138
/*
--------------------------------------------------------------------------------
 
Module: uart_core.v
 
Function:
- TX/RX DATA_W,n,1 RS232 UART.
 
Instantiates:
- (1x) dds_static.v
- (1x) uart_tx.v
- (1x) uart_rx.v
 
Notes:
- See individual components for details.
- Serial loopback does not disconnect serial TX interface.
- Baud rate is fixed, baud clock is calculated from the input parameters.
- Common baud rates are 2400, 3600, and 2x multiples of these:
- 2400, 4800, 9600, 19200, 38400, 76800, 153600
- 3600, 7200, 14400, 28800, 57600, 115200
 
--------------------------------------------------------------------------------
*/
 
module uart_core
#(
parameter integer CLK_HZ = 160000000, // clk_i rate (Hz)
parameter integer BAUD_RATE = 115200, // baud rate (Hz)
parameter integer DATA_W = 8 // parallel data width (bits)
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active hi
// parallel interface
input wire [DATA_W-1:0] tx_data_i, // data
output wire tx_rdy_o, // ready for data, active hi
input wire tx_wr_i, // data write, active high
//
output wire [DATA_W-1:0] rx_data_o, // data
output wire rx_rdy_o, // ready with data, active hi
input wire rx_rd_i, // data read, active hi
// serial interface
output wire tx_o, // serial data
input wire rx_i, // serial data
// debug
input wire loop_i, // serial loopback enable, active hi
output wire rx_error_o, // 1=bad start/stop bit; 0=OK
output wire rx_bad_buffer_o, // bad rx buffering, active hi
output wire baud_clk_o // baud clock
);
 
 
/*
----------------------
-- internal signals --
----------------------
*/
`include "functions.h" // for clog2()
//
localparam integer STOP_BITS = 1; // Number of stop bits (1 or larger)
localparam integer BAUD_OSR = 16; // baud oversample rate (3 or larger)
//
// calculations to set DDS parameters
//
localparam integer INC_W = 8; // sets maximum error
localparam real BAUD_HZ = BAUD_RATE*BAUD_OSR;
localparam real N = CLK_HZ/BAUD_HZ;
localparam integer ACCUM_W = clog2(N)+INC_W-1;
localparam integer INC_VAL = (2**ACCUM_W)/N;
//
wire rx_bad_start, rx_bad_stop;
 
 
/*
================
== code start ==
================
*/
 
 
dds_static
#(
.ACCUM_W ( ACCUM_W ),
.INC_VAL ( INC_VAL )
)
dds_static_inst
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.clk_o ( baud_clk_o )
);
 
 
uart_tx
#(
.DATA_W ( DATA_W ),
.BAUD_OSR ( BAUD_OSR ),
.STOP_BITS ( STOP_BITS )
)
uart_tx_inst
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.baud_clk_i ( baud_clk_o ),
.tx_data_i ( tx_data_i ),
.tx_rdy_o ( tx_rdy_o ),
.tx_wr_i ( tx_wr_i ),
.tx_o ( tx_o )
);
 
 
uart_rx
#(
.DATA_W ( DATA_W ),
.BAUD_OSR ( BAUD_OSR )
)
uart_rx_inst
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.baud_clk_i ( baud_clk_o ),
.rx_data_o ( rx_data_o ),
.rx_rdy_o ( rx_rdy_o ),
.rx_rd_i ( rx_rd_i ),
.rx_i ( loop_i ? tx_o : rx_i ),
.rx_bad_start_o ( rx_bad_start ),
.rx_bad_stop_o ( rx_bad_stop ),
.rx_bad_buffer_o ( rx_bad_buffer_o )
);
 
// combine errors
assign rx_error_o = ( rx_bad_start | rx_bad_stop );
 
endmodule
/trunk/v04.05/hive_core.qsf
0,0 → 1,71
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2010 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
# Date created = 09:56:16 September 30, 2013
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# hive_core_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
 
 
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name DEVICE EP3C5E144C8
set_global_assignment -name TOP_LEVEL_ENTITY hive_core
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.1 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:56:16 SEPTEMBER 30, 2013"
set_global_assignment -name LAST_QUARTUS_VERSION "9.1 SP2"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name VECTOR_WAVEFORM_FILE hive_core.vwf
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE hive_core.vwf
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name MAX_RAM_BLOCKS_M4K 24
set_global_assignment -name SEED 2
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
/trunk/v04.05/pll.v
0,0 → 1,301
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
 
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Build 197 01/19/2011 SP 1 SJ Web Edition
// ************************************************************
 
 
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
inclk0,
c0);
 
input inclk0;
output c0;
 
wire [4:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
 
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 5,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 16,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
 
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "5"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "160.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "16"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "160.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
/trunk/v04.05/reg_set.v
0,0 → 1,625
/*
--------------------------------------------------------------------------------
 
Module: reg_set.v
 
Function:
- Internal register set for a processor.
 
Instantiates:
- (8x) reg_base.v
- (2x) pipe.v
 
 
Notes:
- Processor bus IN/OUT optionally registered.
 
Decode:
- 0x0 : Core version register - ver_reg
- 0x1 : Thread ID register - thrd_id_reg
- 0x2 : Clear register - clr_reg
- 0x3 : Interrupt enable register - intr_en_reg
- 0x4 : Opcode error register - op_er_reg
- 0x5 : Stack error register - stk_er_reg
- 0x6 - 0x7 : UNUSED
- 0x8 : I/O low register - io_lo_reg
- 0x9 : I/O high register - io_hi_reg
- 0xA - 0xB : UNUSED
- 0xC : UART RX register - uart_rx_reg
- 0xD : UART TX register - uart_tx_reg
- 0xE - 0xF : UNUSED
 
 
================================================================================
- 0x0 : Core version register - ver_reg
--------------------------------------------------------------------------------
 
bit name description
----- ---- -----------
7-0 ver_min[7:0] minor version info
15-8 ver_maj[7:0] major version info
 
Notes:
- Read-only.
- Nibbles S/B BCD (0-9; no A-F) to be easily human readable,
and to eliminate confusion between decimal and hex here.
- Major version changes when op_code binary decode changes (incompatibilty).
 
================================================================================
- 0x1 : Thread ID register - thrd_id_reg
--------------------------------------------------------------------------------
 
bit name description
----- ---- -----------
2-0 thrd_id[2:0] thread ID
15-3 - 0000000000000
 
Notes:
- Read-only.
- Threads can read this to discover their thread ID.
 
================================================================================
- 0x2 : Clear register - clr_reg
--------------------------------------------------------------------------------
 
bit name description
----- ---- -----------
7-0 clr[7:0] 0=>1 clear thread; 1=>0 no effect;
15-8 - 00000000
 
Notes:
- Read / write.
- Per thread clearing.
- All bits cleared on async reset.
 
================================================================================
- 0x3 : Interrupt enable register - intr_en_reg
--------------------------------------------------------------------------------
 
bit name description
----- ---- -----------
7-0 intr_en[7:0] 1=thread interrupt enable; 0=disable
15-8 - 00000000
 
Notes:
- Read / write.
- Per thread enabling of interrupts.
- All bits cleared on async reset.
 
================================================================================
- 0x4 : Opcode error register - op_er_reg
--------------------------------------------------------------------------------
 
bit name description
----- ---- -----------
7-0 op_er[7:0] 1=opcode error; 0=OK
15-8 - 00000000
 
Notes:
- Clear on write one.
- Per thread opcode error reporting.
 
================================================================================
- 0x5 : Stack error register - stk_er_reg
--------------------------------------------------------------------------------
 
bit name description
----- ---- -----------
7-0 pop_er[7:0] 1=lifo pop when empty; 0=OK
15-8 push_er[7:0] 1=lifo push when full; 0=OK
 
Notes:
- Clear on write one.
- Per thread LIFO stack error reporting.
 
================================================================================
- 0x6 - 0x7 : UNUSED
================================================================================
- 0x8 : I/O low register - io_lo_reg
--------------------------------------------------------------------------------
 
bit name description
----- ---- -----------
15-0 io_lo[15:0] I/O data
 
Notes:
- Separate read / write.
- Reads of io_lo_reg freeze data in io_hi_reg, so read io_lo_reg first then
read io_hi_reg for contiguous wide (32 bit) data reads.
- Writes function normally.
 
================================================================================
- 0x9 : I/O high register - io_hi_reg
--------------------------------------------------------------------------------
 
bit name description
----- ---- -----------
15-0 io_hi[15:0] I/O data
 
Notes:
- Separate read / write.
- Reads of io_lo_reg freeze data in io_hi_reg, so read io_lo_reg first then
read io_hi_reg for contiguous wide (32 bit) data reads.
- Writes function normally.
 
================================================================================
- 0xA - 0xB : UNUSED
================================================================================
- 0xC : UART RX register - uart_rx_reg
--------------------------------------------------------------------------------
 
bit name description
----- ---- -----------
7-0 uart_rx_data[7:0] RX UART data
8 rx_rdy 1=RX UART ready (has new data); 0=not ready
15-9 - 0000000
 
Notes:
- Reads from this register pop data from the RX UART.
- To avoid RX data loss, read soon after RX UART is ready.
- UART ready bit will self clear after associated register operation.
 
================================================================================
- 0xD : UART TX register - uart_tx_reg
--------------------------------------------------------------------------------
 
bit name description
----- ---- -----------
7-0 uart_tx_data[7:0] TX UART data
8 tx_rdy 1=TX UART ready (for new data); 0=not ready
15-9 - 0000000
 
Notes:
- Writes to this register push data to the TX UART.
- To avoid TX data loss, restrict writes to when TX UART is ready.
- UART ready bit will self clear after associated register operation.
 
================================================================================
- 0xE - 0xF : UNUSED
================================================================================
*/
 
module reg_set
#(
parameter integer REGS_IN = 1, // bus in register option
parameter integer REGS_OUT = 1, // bus out register option
parameter integer DATA_W = 16, // data width (bits)
parameter integer ADDR_W = 4, // address width (bits)
parameter integer THREADS = 8, // threads
parameter integer THRD_W = 3, // thread selector width
parameter integer STACKS = 8, // stacks
parameter integer STK_W = 3, // stack selector width
//
parameter [DATA_W/2-1:0] VER_MAJ = 'h1, // core version
parameter [DATA_W/2-1:0] VER_MIN = 'h0,
//
parameter integer UART_DATA_W = 8, // uart data width (bits)
parameter integer CLK_HZ = 160000000, // master clk_i rate (Hz)
parameter integer UART_BAUD_RATE = 115200 // uart baud rate (Hz)
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// bus interface
input wire [ADDR_W-1:0] addr_i, // address
input wire wr_i, // data write enable, active high
input wire rd_i, // data read enable, active high
input wire [DATA_W-1:0] data_i, // write data
output wire [DATA_W-1:0] data_o, // read data
// clear
output wire [THREADS-1:0] clr_req_o, // clr request, active high
// interrupt
output wire [THREADS-1:0] intr_en_o, // interrupt enable, active high
// errors
input wire [THRD_W-1:0] thrd_0_i, // thread
input wire op_code_er_i, // 1=illegal op code encountered
input wire [THRD_W-1:0] thrd_2_i, // thread
input wire [STACKS-1:0] pop_er_2_i, // pop when empty, active high
input wire [THRD_W-1:0] thrd_3_i, // thread
input wire [STACKS-1:0] push_er_3_i, // push when full, active high
// I/O
input wire [DATA_W-1:0] io_lo_i, // gpio linked to io_hi_i
input wire [DATA_W-1:0] io_hi_i,
output wire [DATA_W-1:0] io_lo_o, // unlinked gpio
output wire [DATA_W-1:0] io_hi_o,
// serial interface
input wire uart_rx_i, // serial data
output wire uart_tx_o // serial data
);
 
 
/*
----------------------
-- internal signals --
----------------------
*/
`include "reg_set_addr.h"
//
wire [ADDR_W-1:0] addr;
wire reg_en, wr, rd;
wire [DATA_W-1:0] rd_data, wr_data, reg_rd_data;
wire [DATA_W-1:0] ver_rd_data,
thrd_id_rd_data,
clr_rd_data,
intr_en_rd_data,
op_er_rd_data,
stk_er_data,
io_lo_rd_data,
io_hi_rd_data,
uart_rx_rd_data,
uart_tx_rd_data;
//
wire io_lo_reg_rd;
wire [THREADS-1:0] op_code_errors, push_errors, pop_errors;
wire [UART_DATA_W-1:0] uart_tx_data, uart_rx_data;
wire uart_tx_rdy, uart_rx_rdy;
wire uart_tx_wr, uart_rx_rd;
 
 
 
/*
================
== code start ==
================
*/
 
 
 
// optional bus input regs
pipe
#(
.DEPTH ( REGS_IN ),
.WIDTH ( 2+ADDR_W+DATA_W ),
.RESET_VAL ( 0 )
)
in_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { wr_i, rd_i, addr_i, data_i } ),
.data_o ( { wr, rd, addr, wr_data } )
);
 
 
// big ORing of read data
assign rd_data =
ver_rd_data |
thrd_id_rd_data |
clr_rd_data |
intr_en_rd_data |
op_er_rd_data |
stk_er_data |
io_lo_rd_data |
io_hi_rd_data |
uart_rx_rd_data |
uart_tx_rd_data;
 
 
// optional output regs
pipe
#(
.DEPTH ( REGS_OUT ),
.WIDTH ( DATA_W ),
.RESET_VAL ( 0 )
)
out_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( rd_data ),
.data_o ( data_o )
);
 
 
/*
-------------
-- ver_reg --
-------------
*/
 
reg_base
#(
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W ),
.ADDRESS ( VER_ADDR[ADDR_W-1:0] ),
.OUT_MODE ( "ZERO" ),
.READ_MODE ( "THRU" )
)
ver_reg
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.addr_i ( addr ),
.wr_i ( wr ),
.rd_i ( rd ),
.wr_data_i ( wr_data ),
.rd_data_o ( ver_rd_data ),
.reg_data_i ( { VER_MAJ, VER_MIN } )
);
 
 
/*
-----------------
-- thrd_id_reg --
-----------------
*/
 
reg_base
#(
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W ),
.ADDRESS ( THRD_ID_ADDR[ADDR_W-1:0] ),
.OUT_MODE ( "ZERO" ),
.READ_MODE ( "THRU" ),
.LIVE_MASK ( { THRD_W{ 1'b1 } } )
)
thrd_id_reg
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.addr_i ( addr ),
.wr_i ( wr ),
.rd_i ( rd ),
.wr_data_i ( wr_data ),
.rd_data_o ( thrd_id_rd_data ),
.reg_data_i ( thrd_3_i )
);
 
 
/*
-------------
-- clr_reg --
-------------
*/
reg_base
#(
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W ),
.ADDRESS ( CLR_ADDR[ADDR_W-1:0] ),
.OUT_MODE ( "LTCH" ),
.READ_MODE ( "LOOP" ),
.LIVE_MASK ( { THREADS{ 1'b1 } } )
)
clr_reg
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.addr_i ( addr ),
.wr_i ( wr ),
.rd_i ( rd ),
.wr_data_i ( wr_data ),
.rd_data_o ( clr_rd_data ),
.reg_data_o ( clr_req_o )
);
 
/*
-----------------
-- intr_en_reg --
-----------------
*/
reg_base
#(
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W ),
.ADDRESS ( INTR_EN_ADDR[ADDR_W-1:0] ),
.OUT_MODE ( "LTCH" ),
.READ_MODE ( "LOOP" ),
.LIVE_MASK ( { THREADS{ 1'b1 } } )
)
intr_en_reg
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.addr_i ( addr ),
.wr_i ( wr ),
.rd_i ( rd ),
.wr_data_i ( wr_data ),
.rd_data_o ( intr_en_rd_data ),
.reg_data_o ( intr_en_o )
);
 
/*
---------------
-- op_er_reg --
---------------
*/
reg_base
#(
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W ),
.ADDRESS ( OP_ER_ADDR[ADDR_W-1:0] ),
.OUT_MODE ( "ZERO" ),
.READ_MODE ( "COW1" ),
.LIVE_MASK ( { THREADS{ 1'b1 } } )
)
op_er_reg
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.addr_i ( addr ),
.wr_i ( wr ),
.rd_i ( rd ),
.wr_data_i ( wr_data ),
.rd_data_o ( op_er_rd_data ),
.reg_data_i ( op_code_errors )
);
 
// decode errors
assign op_code_errors = op_code_er_i << thrd_0_i;
 
 
/*
----------------
-- stk_er_reg --
----------------
*/
reg_base
#(
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W ),
.ADDRESS ( STK_ER_ADDR[ADDR_W-1:0] ),
.OUT_MODE ( "ZERO" ),
.READ_MODE ( "COW1" ),
.LIVE_MASK ( { (THREADS+THREADS){ 1'b1 } } )
)
stk_er_reg
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.addr_i ( addr ),
.wr_i ( wr ),
.rd_i ( rd ),
.wr_data_i ( wr_data ),
.rd_data_o ( stk_er_data ),
.reg_data_i ( { push_errors, pop_errors } )
);
 
// decode errors
assign push_errors = |push_er_3_i << thrd_3_i;
assign pop_errors = |pop_er_2_i << thrd_2_i;
 
/*
---------------
-- io_lo_reg --
---------------
*/
reg_base
#(
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W ),
.ADDRESS ( IO_LO_ADDR[ADDR_W-1:0] ),
.OUT_MODE ( "LTCH" ),
.READ_MODE ( "THRU" )
)
io_lo_reg
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.addr_i ( addr ),
.wr_i ( wr ),
.rd_i ( rd ),
.wr_data_i ( wr_data ),
.rd_data_o ( io_lo_rd_data ),
.reg_rd_o ( io_lo_reg_rd ),
.reg_data_i ( io_lo_i ),
.reg_data_o ( io_lo_o )
);
 
 
/*
---------------
-- io_hi_reg --
---------------
*/
reg_base
#(
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W ),
.ADDRESS ( IO_HI_ADDR[ADDR_W-1:0] ),
.OUT_MODE ( "LTCH" ),
.READ_MODE ( "DFFE" )
)
io_hi_reg
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.addr_i ( addr ),
.wr_i ( wr ),
.rd_i ( rd ),
.wr_data_i ( wr_data ),
.rd_data_o ( io_hi_rd_data ),
.reg_en_i ( io_lo_reg_rd ), // enable on lo read
.reg_data_i ( io_hi_i ),
.reg_data_o ( io_hi_o )
);
 
 
/*
-----------------
-- uart_rx_reg --
-----------------
*/
reg_base
#(
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W ),
.ADDRESS ( UART_RX_ADDR[ADDR_W-1:0] ),
.OUT_MODE ( "ZERO" ),
.READ_MODE ( "THRU" ),
.LIVE_MASK ( { 1+UART_DATA_W{ 1'b1 } } )
)
uart_rx_reg
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.addr_i ( addr ),
.wr_i ( wr ),
.rd_i ( rd ),
.wr_data_i ( wr_data ),
.rd_data_o ( uart_rx_rd_data ),
.reg_rd_o ( uart_rx_rd ),
.reg_data_i ( { uart_rx_rdy, uart_rx_data } ),
.reg_data_o ( )
);
 
 
/*
-----------------
-- uart_tx_reg --
-----------------
*/
reg_base
#(
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W ),
.ADDRESS ( UART_TX_ADDR[ADDR_W-1:0] ),
.OUT_MODE ( "THRU" ),
.READ_MODE ( "THRU" ),
.LIVE_MASK ( { 1+UART_DATA_W{ 1'b1 } } )
)
uart_tx_reg
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.addr_i ( addr ),
.wr_i ( wr ),
.rd_i ( rd ),
.wr_data_i ( wr_data ),
.rd_data_o ( uart_tx_rd_data ),
.reg_wr_o ( uart_tx_wr ),
.reg_data_i ( { uart_tx_rdy, { UART_DATA_W{ 1'b0 } } } ),
.reg_data_o ( uart_tx_data )
);
 
 
uart_core
#(
.CLK_HZ ( CLK_HZ ),
.BAUD_RATE ( UART_BAUD_RATE ),
.DATA_W ( UART_DATA_W )
)
uart_core_inst
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.tx_data_i ( uart_tx_data ),
.tx_rdy_o ( uart_tx_rdy ),
.tx_wr_i ( uart_tx_wr ),
.rx_data_o ( uart_rx_data ),
.rx_rdy_o ( uart_rx_rdy ),
.rx_rd_i ( uart_rx_rd ),
.tx_o ( uart_tx_o ),
.rx_i ( uart_rx_i ),
.loop_i ( 1'b0 ), // unused
.rx_error_o ( ), // unused
.rx_bad_buffer_o ( ), // unused
.baud_clk_o ( ) // unused
);
 
 
endmodule
/trunk/v04.05/ep4ce6e22c8_demo_board.qsf
0,0 → 1,94
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2011 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 11.0 Build 157 04/27/2011 SJ Full Version
# Date created = 17:14:01 April 10, 2012
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# LED_4_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
 
 
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE6E22C8
set_global_assignment -name TOP_LEVEL_ENTITY ep4ce6e22c8_demo_board
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 11.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:14:01 APRIL 10, 2012"
set_global_assignment -name LAST_QUARTUS_VERSION "10.1 SP1"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name VERILOG_FILE ep4ce6e22c8_demo_board.v
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_3 -to led_o[0]
set_location_assignment PIN_7 -to led_o[1]
set_location_assignment PIN_10 -to led_o[2]
set_location_assignment PIN_11 -to led_o[3]
set_location_assignment PIN_23 -to clk_50m_i
set_location_assignment PIN_125 -to rstn_i
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS16
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS PROGRAMMING PIN"
set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS16
set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "COMPILER CONFIGURED"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "COMPILER CONFIGURED"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "COMPILER CONFIGURED"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "COMPILER CONFIGURED"
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name SDC_FILE ep4ce6e22c8_demo_board.sdc
set_global_assignment -name MAX_RAM_BLOCKS_M4K 24
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name SEED 2
set_global_assignment -name MISC_FILE "F:/Docs/Eric/VERILOG/THRASH/HIVE88/ep4ce6e22c8_demo_board.dpf"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
/trunk/v04.05/boot_code/boot_code_v_io.h
0,0 → 1,236
/*
--------------------------------------------------------------------------------
 
Module : boot_code.h
 
--------------------------------------------------------------------------------
 
Function:
- Boot code for a processor core.
 
Instantiates:
- Nothing.
 
Notes:
- For testing (@ core.v):
CLR_BASE = 'h0;
CLR_SPAN = 2; // gives 4 instructions
INTR_BASE = 'h20; // 'd32
INTR_SPAN = 2; // gives 4 instructions
 
 
--------------------------------------------------------------------------------
*/
 
/*
--------------------
-- external stuff --
--------------------
*/
`include "op_encode.h"
`include "reg_set_addr.h"
`include "boot_code_defs.h"
/*
----------------------------------------
-- initialize: fill with default data --
----------------------------------------
*/
integer i;
 
initial begin
 
/* // fill with nop (some compilers need this)
for ( i = 0; i < CAPACITY; i = i+1 ) begin
ram[i] = { `nop, `__, `__ };
end
*/
 
/*
---------------
-- boot code --
---------------
*/
 
 
// Thread 0 : test I/O functions
// All other threads : loop forever
 
///////////////
// clr space //
///////////////
 
// thread 0
i='h0; ram[i] = { `lit_u, `__, `s2 }; // s2='h0100
i=i+1; ram[i] = 16'h0100 ; //
i=i+1; ram[i] = { `gto, `P2, `__ }; // goto, pop s2 (addr)
// thread 1
i='h4; ram[i] = { `lit_u, `__, `s2 }; // s2='h0200
i=i+1; ram[i] = 16'h0200 ; //
i=i+1; ram[i] = { `gto, `P2, `__ }; // goto, pop s2 (addr)
// and the rest
i='h08; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h0c; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h10; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h14; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h18; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h1c; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
 
 
////////////////
// intr space //
////////////////
 
///////////////////////
// code & data space //
///////////////////////
 
 
// test I/O functions, result in s0
// Correct functioning is s0 = 'd8 ('h8).
//
// s0 : final test result
// s1 : test value
// s2 : test value
// s3 : running test result, subroutine return address
//
// setup running test result:
i='h100; ram[i] = { `dat_is, 6'd0, `s3 }; // s3=0
// PGC
i=i+1; ram[i] = { `pgc, `__, `s1 }; // s1=PC
i=i+1; ram[i] = { `lit_u, `__, `s0 }; // s0='h0102
i=i+1; ram[i] = 16'h0102 ; //
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// setup test value:
i=i+1; ram[i] = { `lit_u, `__, `s1 }; // s1='h36c9,a53c
i=i+1; ram[i] = 16'ha53c ; //
i=i+1; ram[i] = { `lit_h, `__, `P1 }; //
i=i+1; ram[i] = 16'h36c9 ; //
// MEM_IWH & MEM_IRH
i=i+1; ram[i] = { `lit_u, `__, `s2 }; // s2='h0a00
i=i+1; ram[i] = 16'h0a00 ; //
i=i+1; ram[i] = { `mem_iw, 4'd0, `s2, `s1 }; // (s2+offset)=s1
i=i+1; ram[i] = { `mem_iwh, 4'd1, `s2, `s1 }; //
i=i+1; ram[i] = { `mem_irs, 4'd0, `s2, `s0 }; // s0=(s2+offset)
i=i+1; ram[i] = { `mem_irh, 4'd1, `P2, `P0 }; //
i=i+1; ram[i] = { `jmp_ie, 4'd1, `s1, `P0 }; // (s0==s1) ? skip, pop s0
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// MEM_IRS (signed)
i=i+1; ram[i] = { `lit_u, `__, `s2 }; // s2='h0a00
i=i+1; ram[i] = 16'h0a10 ; //
i=i+1; ram[i] = { `mem_iw, 4'd0, `s2, `s1 }; // (s2+offset)=s1
i=i+1; ram[i] = { `mem_irs, 4'd0, `P2, `s0 }; // s0=(s2+offset), pop s2
i=i+1; ram[i] = { `shl_is, 6'd16, `s1 }; // s1<<=16
i=i+1; ram[i] = { `shl_is, -6'd16, `P1 }; // s1>>=16
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// MEM_IRS (unsigned)
i=i+1; ram[i] = { `lit_u, `__, `s2 }; // s2='h0a00
i=i+1; ram[i] = 16'h0a20 ; //
i=i+1; ram[i] = { `mem_iwh, 4'd0, `s2, `s1 }; // (s2+offset)=s1
i=i+1; ram[i] = { `mem_irs, 4'd0, `P2, `s0 }; // s0=(s2+offset), pop s2
i=i+1; ram[i] = { `psu_i, -6'd16, `s1 }; // s1>>=16
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// REG_RS, REG_RH, REG_W & REG_WH (check manually for I/O loopback)
i=i+1; ram[i] = { `dat_is, `IO_LO, `s2 }; // s2=reg addr
i=i+1; ram[i] = { `reg_rs, `s2, `s1 }; // s1=(s2)
i=i+1; ram[i] = { `reg_w, `P2, `P1 }; // (s2)=s1, pop both
i=i+1; ram[i] = { `dat_is, `IO_HI, `s2 }; // s2=reg addr
i=i+1; ram[i] = { `reg_rh, `s2, `s1 }; // s1=(s2)
i=i+1; ram[i] = { `reg_wh, `P2, `P1 }; // (s2)=s1, pop s2
// LIT_S
i=i+1; ram[i] = { `lit_s, `__, `s0 }; // s0='ha53c
i=i+1; ram[i] = 16'ha53c ; //
i=i+1; ram[i] = { `shl_is, 6'd16, `s1 }; // s1<<=16
i=i+1; ram[i] = { `shl_is, -6'd16, `P1 }; // s1>>=16, pop s1
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// LIT_U
i=i+1; ram[i] = { `lit_u, `__, `s0 }; // s0='ha53c
i=i+1; ram[i] = 16'ha53c ; //
i=i+1; ram[i] = { `shl_is, 6'd16, `s1 }; // s1<<=16
i=i+1; ram[i] = { `psu_i, -6'd16, `P1 }; // s1>>=16, pop s1
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// check for no opcode errors
i=i+1; ram[i] = { `lit_u, `__, `s7 }; // s7='h0900
i=i+1; ram[i] = 16'h0900 ; //
i=i+1; ram[i] = { `gsb, `P7, `s7 }; // gsb, pop s7 (addr)
i=i+1; ram[i] = { `jmp_iz, 6'd1, `P4 }; // (s4==0) ? skip, pop s4
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// check for no stack errors
i=i+1; ram[i] = { `lit_u, `__, `s7 }; // s7='h0910
i=i+1; ram[i] = 16'h0910 ; //
i=i+1; ram[i] = { `gsb, `P7, `s7 }; // gsb, pop s2 (addr)
i=i+1; ram[i] = { `jmp_iz, 6'd1, `P4 }; // (s4==0) ? skip, pop s4
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// copy result to s0
i=i+1; ram[i] = { `cpy, `P3, `s0 }; // s0=s3, pop s3
// loop forever
i=i+1; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
// end sub
 
 
// test UART
//
// s0 : TX value
// s1 :
// s2 : reg addr
// s3 :
// s4 : TX ready
//
//
i='h200; ram[i] = { `lit_u, `__, `s0 }; // s0='h00a5
i=i+1; ram[i] = 16'h00a5 ; //
i=i+1; ram[i] = { `dat_is, `UART_TX, `s2 }; // s2=reg addr
i=i+1; ram[i] = { `reg_rs, `s2, `s4 }; // s4=(s2)
i=i+1; ram[i] = { `jmp_iz, 6'd1, `P4 }; // (s4==0) ? skip, pop s4
i=i+1; ram[i] = { `reg_w, `s2, `s0 }; // (s2)=s0
// loop forever
i=i+1; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
// end sub
 
 
/////////////////
// subroutines //
/////////////////
 
 
// sub : read & clear opcode errors for this thread => s4, return to (s7)
// avoid the use of s1!
i='h900; ram[i] = { `dat_is, `THRD_ID, `s6 }; // s6=reg addr
i=i+1; ram[i] = { `reg_rs, `P6, `s5 }; // s5=(s6), pop s6
i=i+1; ram[i] = { `pow, `P5, `s4 }; // s4=1<<s5, pop s5
i=i+1; ram[i] = { `dat_is, `OP_ER, `s6 }; // s6=reg addr
i=i+1; ram[i] = { `reg_rs, `s6, `s5 }; // s5=(s6)
i=i+1; ram[i] = { `and, `P5, `P4 }; // s4&=s5, pop s5
i=i+1; ram[i] = { `reg_w, `P6, `s4 }; // (s6)=s4, pop s6
i=i+1; ram[i] = { `gto, `P7, `__ }; // return to (s7), pop s7
 
 
// sub : read & clear stack errors for this thread => s4, return to (s7)
// avoid the use of s1!
i='h910; ram[i] = { `dat_is, `THRD_ID, `s6 }; // s6=reg addr
i=i+1; ram[i] = { `reg_rs, `P6, `s5 }; // s5=(s6), pop s6
i=i+1; ram[i] = { `pow, `P5, `s4 }; // s4=1<<s5, pop s5
i=i+1; ram[i] = { `cpy, `s4, `s5 }; // s5=s4
i=i+1; ram[i] = { `shl_is, 6'd8, `P5 }; // s5<<=8
i=i+1; ram[i] = { `orr, `P5, `P4 }; // s4|=s5, pop s5
i=i+1; ram[i] = { `dat_is, `STK_ER, `s6 }; // s6=reg addr
i=i+1; ram[i] = { `reg_rs, `s6, `s5 }; // s5=(s6)
i=i+1; ram[i] = { `and, `P5, `P4 }; // s4&=s5, pop s5
i=i+1; ram[i] = { `reg_w, `P6, `s4 }; // (s6)=s4, pop s6
i=i+1; ram[i] = { `gto, `P7, `__ }; // return to (s7), pop s7
 
 
end
/trunk/v04.05/boot_code/boot_code_v_stacks.h
0,0 → 1,236
/*
--------------------------------------------------------------------------------
 
Module : boot_code.h
 
--------------------------------------------------------------------------------
 
Function:
- Boot code for a processor core.
 
Instantiates:
- Nothing.
 
Notes:
- For testing (@ core.v):
CLR_BASE = 'h0;
CLR_SPAN = 2; // gives 4 instructions
INTR_BASE = 'h20; // 'd32
INTR_SPAN = 2; // gives 4 instructions
 
 
--------------------------------------------------------------------------------
*/
 
/*
--------------------
-- external stuff --
--------------------
*/
`include "op_encode.h"
`include "reg_set_addr.h"
`include "boot_code_defs.h"
/*
----------------------------------------
-- initialize: fill with default data --
----------------------------------------
*/
integer i;
 
initial begin
 
/* // fill with nop (some compilers need this)
for ( i = 0; i < CAPACITY; i = i+1 ) begin
ram[i] = { `nop, `__, `__ };
end
*/
 
/*
---------------
-- boot code --
---------------
*/
 
 
// Thread 0 : test stack 1 for depth and error reporting
// All other threads : loop forever
 
///////////////
// clr space //
///////////////
 
// thread 0
i='h0; ram[i] = { `lit_u, `__, `s2 }; // s2='h0100
i=i+1; ram[i] = 16'h0100 ; //
i=i+1; ram[i] = { `gto, `P2, `__ }; // goto, pop s2 (addr)
// and the rest
i='h04; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h08; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h0c; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h10; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h14; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h18; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h1c; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
 
 
////////////////
// intr space //
////////////////
 
///////////////////////
// code & data space //
///////////////////////
 
 
// test s1 for correct stack depth and error reporting, result in s0
// Correct functioning is s0 = 'd7 ('h7).
//
// s0 : final test result
// s1 : test stack
// s2 : sub addr
// s3 : running test result, subroutine return address
//
// setup running test result:
i='h100; ram[i] = { `dat_is, 6'd0, `s7 }; // s7=0
// check for no stack errors
i=i+1; ram[i] = { `lit_u, `__, `s7 }; // s7=addr
i=i+1; ram[i] = 16'h0910 ; // addr
i=i+1; ram[i] = { `gsb, `P7, `s7 }; // gsb, pop s7 (addr), return to s7
i=i+1; ram[i] = { `jmp_iz, 6'd1, `P4 }; // (s4==0) ? skip, pop s4
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// fill s1
i=i+1; ram[i] = { `lit_u, `__, `s7 }; // s7=addr
i=i+1; ram[i] = 16'h0940 ; // addr
i=i+1; ram[i] = { `gsb, `P7, `s7 }; // gsb, pop s7 (addr), return to s7
// check for push error
i=i+1; ram[i] = { `lit_u, `__, `s7 }; // s7=addr
i=i+1; ram[i] = 16'h0910 ; // addr
i=i+1; ram[i] = { `gsb, `P7, `s7 }; // gsb, pop s7 (addr), return to s7
i=i+1; ram[i] = { `psu_i, -6'd8, `P4 }; // s4>>=8
i=i+1; ram[i] = { `jmp_iz, 6'd1, `P4 }; // (s4==0) ? skip, pop s4
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// pop&push s/b OK
i=i+1; ram[i] = { `add_is, 6'd0, `P1 }; // s1=s1
// check for no stack errors
i=i+1; ram[i] = { `lit_u, `__, `s7 }; // s7=addr
i=i+1; ram[i] = 16'h0910 ; // addr
i=i+1; ram[i] = { `gsb, `P7, `s7 }; // gsb, pop s7 (addr), return to s7
i=i+1; ram[i] = { `jmp_iz, 6'd1, `P4 }; // (s4==0) ? skip, pop s4
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// s/b one push over the line
i=i+1; ram[i] = { `add_is, 6'd0, `s1 }; // s1=>s1
// check for a push error
i=i+1; ram[i] = { `lit_u, `__, `s7 }; // s7=addr
i=i+1; ram[i] = 16'h0910 ; // addr
i=i+1; ram[i] = { `gsb, `P7, `s7 }; // gsb, pop s7 (addr), return to s7
i=i+1; ram[i] = { `psu_i, -6'd8, `P4 }; // s4>>=8
i=i+1; ram[i] = { `jmp_inz, 6'd1, `P4 }; // (s4!=0) ? skip, pop s4
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// empty s1
i=i+1; ram[i] = { `lit_u, `__, `s7 }; // s7=addr
i=i+1; ram[i] = 16'h0950 ; // addr
i=i+1; ram[i] = { `gsb, `P7, `s7 }; // gsb, pop s7 (addr), return to s7
// check for no stack errors
i=i+1; ram[i] = { `lit_u, `__, `s7 }; // s7=addr
i=i+1; ram[i] = 16'h0910 ; // addr
i=i+1; ram[i] = { `gsb, `P7, `s7 }; // gsb, pop s7 (addr), return to s7
i=i+1; ram[i] = { `jmp_iz, 6'd1, `P4 }; // (s4==0) ? skip, pop s4
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// s/b one pop under the line
i=i+1; ram[i] = { `pop, 8'b00000010 }; // pop s1
// check for a pop error
i=i+1; ram[i] = { `lit_u, `__, `s7 }; // s7=addr
i=i+1; ram[i] = 16'h0910 ; // addr
i=i+1; ram[i] = { `gsb, `P7, `s7 }; // gsb, pop s7 (addr), return to s7
i=i+1; ram[i] = { `shl_is, 6'd24, `P4 }; // s4<<=24
i=i+1; ram[i] = { `jmp_inz, 6'd1, `P4 }; // (s4!=0) ? skip, pop s4
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// check for no opcode errors
i=i+1; ram[i] = { `lit_u, `__, `s7 }; // s7=addr
i=i+1; ram[i] = 16'h0900 ; // addr
i=i+1; ram[i] = { `gsb, `P7, `s7 }; // gsb, pop s7 (addr), return to s7
i=i+1; ram[i] = { `jmp_iz, 6'd1, `P4 }; // (s4==0) ? skip, pop s4
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// copy result to s0
i=i+1; ram[i] = { `cpy, `P3, `s0 }; // s0=s3, pop s3
// loop forever
i=i+1; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
 
 
 
/////////////////
// subroutines //
/////////////////
 
 
// sub : read & clear opcode errors for this thread => s4, return to (s7)
// avoid the use of s1!
i='h900; ram[i] = { `dat_is, `THRD_ID, `s6 }; // s6=reg addr
i=i+1; ram[i] = { `reg_rs, `P6, `s5 }; // s5=(s6), pop s6
i=i+1; ram[i] = { `pow, `P5, `s4 }; // s4=1<<s5, pop s5
i=i+1; ram[i] = { `dat_is, `OP_ER, `s6 }; // s6=reg addr
i=i+1; ram[i] = { `reg_rs, `s6, `s5 }; // s5=(s6)
i=i+1; ram[i] = { `and, `P5, `P4 }; // s4&=s5, pop s5
i=i+1; ram[i] = { `reg_w, `P6, `s4 }; // (s6)=s4, pop s6
i=i+1; ram[i] = { `gto, `P7, `__ }; // return to (s7), pop s7
 
 
// sub : read & clear stack errors for this thread => s4, return to (s7)
// avoid the use of s1!
i='h910; ram[i] = { `dat_is, `THRD_ID, `s6 }; // s6=reg addr
i=i+1; ram[i] = { `reg_rs, `P6, `s5 }; // s5=(s6), pop s6
i=i+1; ram[i] = { `pow, `P5, `s4 }; // s4=1<<s5, pop s5
i=i+1; ram[i] = { `cpy, `s4, `s5 }; // s5=s4
i=i+1; ram[i] = { `shl_is, 6'd8, `P5 }; // s5<<=8
i=i+1; ram[i] = { `orr, `P5, `P4 }; // s4|=s5, pop s5
i=i+1; ram[i] = { `dat_is, `STK_ER, `s6 }; // s6=reg addr
i=i+1; ram[i] = { `reg_rs, `s6, `s5 }; // s5=(s6)
i=i+1; ram[i] = { `and, `P5, `P4 }; // s4&=s5, pop s5
i=i+1; ram[i] = { `reg_w, `P6, `s4 }; // (s6)=s4, pop s6
i=i+1; ram[i] = { `gto, `P7, `__ }; // return to (s7), pop s7
 
 
// sub : read 32 bit GPIO => s0, return to (s7)
i='h920; ram[i] = { `dat_is, `IO_LO, `s3 }; // s3=reg addr
i=i+1; ram[i] = { `reg_rs, `P3, `s0 }; // s0=(s3), pop s3
i=i+1; ram[i] = { `dat_is, `IO_HI, `s3 }; // s3=reg addr
i=i+1; ram[i] = { `reg_rh, `P3, `P0 }; // s0=(s3), pop both
i=i+1; ram[i] = { `gto, `P7, `__ }; // return, pop s7
 
 
// sub : write s0 => 32 bit GPIO, return to (s7)
i='h930; ram[i] = { `dat_is, `IO_LO, `s3 }; // s3=reg addr
i=i+1; ram[i] = { `reg_w, `P3, `s0 }; // (s3)=s0, pop s3
i=i+1; ram[i] = { `dat_is, `IO_HI, `s3 }; // s3=reg addr
i=i+1; ram[i] = { `reg_wh, `P3, `s0 }; // (s3)=s0, pop s3
i=i+1; ram[i] = { `gto, `P7, `__ }; // return, pop s7
 
 
// sub : push 32x to s1, return to (s7)
// loop setup:
i='h940; ram[i] = { `dat_is, 6'd31, `s1 }; // s1=31 // first push (& loop index)
// loop
i=i+1; ram[i] = { `add_is, -6'd1, `s1 }; // s1=s1-1
i=i+1; ram[i] = { `jmp_inz, -6'd2, `s1 }; // (s1!=0) ? do again
i=i+1; ram[i] = { `gto, `P7, `__ }; // return, pop s7
 
 
// sub : pop 32x from s1, return to (s7)
// loop setup:
i='h950; ram[i] = { `dat_is, 6'd31, `s2 }; // s2=31
// loop
i=i+1; ram[i] = { `pop, 8'b00000010 }; // pop s1
i=i+1; ram[i] = { `add_is, -6'd1, `P2 }; // s2--
i=i+1; ram[i] = { `jmp_inlz, -6'd3, `s2 }; // (s2>=0) ? do again
i=i+1; ram[i] = { `gto, `P7, `P2 }; // return, pop s7 & s2
 
 
end
/trunk/v04.05/boot_code/boot_code_exp2.h
0,0 → 1,184
/*
--------------------------------------------------------------------------------
 
Module : boot_code.h
 
--------------------------------------------------------------------------------
 
Function:
- Boot code for a processor core.
 
Instantiates:
- Nothing.
 
Notes:
- For testing (@ core.v):
CLR_BASE = 'h0;
CLR_SPAN = 2; // gives 4 instructions
INTR_BASE = 'h20; // 'd32
INTR_SPAN = 2; // gives 4 instructions
 
 
--------------------------------------------------------------------------------
*/
 
/*
--------------------
-- external stuff --
--------------------
*/
`include "boot_code_defs.h"
`include "op_encode.h"
`include "reg_set_addr.h"
/*
----------------------------------------
-- initialize: fill with default data --
----------------------------------------
*/
integer i;
 
initial begin
 
/* // fill with nop (some compilers need this)
for ( i = 0; i < CAPACITY; i = i+1 ) begin
ram[i] = { `nop, `s0, `s0 };
end
*/
 
/*
---------------
-- boot code --
---------------
*/
 
 
/*
------------
-- TEST 0 --
------------
*/
 
// Log base 2
// Thread 0 : Get input 32 bit GPIO, calculate log2, output 32 bit GPIO.
// Other threads : do nothing, loop forever
 
///////////////
// clr space //
///////////////
 
i='h0; ram[i] = { `lit_u, `__, `s1 }; // s1=addr
i=i+1; ram[i] = 16'h0040 ; //
i=i+1; ram[i] = { `gto, `P1, `__ }; // goto, pop s1 (addr)
//
i='h04; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h08; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h0c; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h10; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h14; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h18; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h1c; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
 
////////////////
// intr space //
////////////////
 
///////////////////////
// code & data space //
///////////////////////
 
// read & write 32 bit GPIO data to & from s0
i='h40; ram[i] = { `lit_u, `__, `s3 }; // s3=addr
i=i+1; ram[i] = 16'h0080 ; //
i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
// do s0=exp2(s0)
i=i+1; ram[i] = { `lit_u, `__, `s3 }; // s3=addr
i=i+1; ram[i] = 16'h0090 ; //
i=i+1; ram[i] = { `gsb, `P3, `s7 }; // gsb, pop s3 (addr)
// write s0 data to 32 bit GPIO
i=i+1; ram[i] = { `lit_u, `__, `s3 }; // s3=addr
i=i+1; ram[i] = 16'h0070 ; //
i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
// loop forever
i=i+1; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
 
 
// sub : read 32 bit GPIO => s0, return to (s3)
i='h60; ram[i] = { `dat_is, `IO_LO, `s1 }; // s1=reg addr
i=i+1; ram[i] = { `reg_rs, `P1, `s0 }; // s0=(s1), pop s1
i=i+1; ram[i] = { `dat_is, `IO_HI, `s1 }; // s1=reg addr
i=i+1; ram[i] = { `reg_rh, `P1, `P0 }; // s0=(s1), pop both
i=i+1; ram[i] = { `gto, `P3, `__ }; // return, pop s3
 
 
// sub : write s0 => 32 bit GPIO, return to (s3)
i='h70; ram[i] = { `dat_is, `IO_LO, `s1 }; // s1=reg addr
i=i+1; ram[i] = { `reg_w, `P1, `s0 }; // (s1)=s0, pop s1
i=i+1; ram[i] = { `dat_is, `IO_HI, `s1 }; // s1=reg addr
i=i+1; ram[i] = { `reg_wh, `P1, `s0 }; // (s1)=s0, pop s1
i=i+1; ram[i] = { `gto, `P3, `__ }; // return, pop s3
 
 
// sub : read & write 32 bit GPIO => s0, return to (s3)
i='h80; ram[i] = { `dat_is, `IO_LO, `s1 }; // s1=reg addr
i=i+1; ram[i] = { `reg_rs, `s1, `s0 }; // s0=(s1)
i=i+1; ram[i] = { `reg_w, `P1, `s0 }; // (s1)=s0, pop s1
i=i+1; ram[i] = { `dat_is, `IO_HI, `s1 }; // s1=reg addr
i=i+1; ram[i] = { `reg_rh, `s1, `P0 }; // s0=(s1), pop s0
i=i+1; ram[i] = { `reg_wh, `P1, `s0 }; // (s1)=s0, pop s1
i=i+1; ram[i] = { `gto, `P3, `__ }; // return, pop s3
 
 
 
// sub : s0=exp2(s0), return to (s7)
//
// input is c[31:27].m[26:0] unsigned fixed decimal
// output is out[31:0] an unsigned 32 bit integer
//
// s0 : input, output
// s1 : running multiply
// s2 : running root
// s3 : fudge factor
// s4 :
// s5 :
// s6 : loop index
// s7 : sub return addr
//
// setup
i='h90; ram[i] = { `flp, `s0, `P0 }; // flp(s0) (to examine lsbs via msb)
i=i+1; ram[i] = { `psu_i, 6'd31, `s1 }; // s1=0x8000,0000 (starting value = 1)
i=i+1; ram[i] = { `cpy, `s1, `s2 }; // s2=0x8000,000b (starting root = 2^2^-27)
i=i+1; ram[i] = { `add_is, 6'hb, `P2 }; //
i=i+1; ram[i] = { `lit_u, `__, `s3 }; // s3=0x173c,e500 (fudge factor bits)
i=i+1; ram[i] = 16'he500 ; //
i=i+1; ram[i] = { `lit_h, `__, `P3 }; //
i=i+1; ram[i] = 16'h173c ; //
i=i+1; ram[i] = { `dat_is, 6'd26, `s6 }; // s6=26 (loop index)
// loop start
// jump 0 start
i=i+1; ram[i] = { `jmp_inlz, 6'd2, `s0 }; // (s0[31]==0) ? jump +2 (skip running mult)
i=i+1; ram[i] = { `mul_xu, `s2, `P1 }; // s1*=s2
i=i+1; ram[i] = { `shl_is, 6'd1, `P1 }; // s1<<=1 (so msb=1)
// jump 0 end
i=i+1; ram[i] = { `mul_xu, `s2, `P2 }; // s2*=s2 (square to get next root)
i=i+1; ram[i] = { `shl_is, 6'd1, `P2 }; // s2<<=1 (so msb=1 & lsb=0)
// jump 1 start
i=i+1; ram[i] = { `jmp_inlz, 6'd1, `s3 }; // (s3[31]==0) ? jump +1 (no fudge bit)
i=i+1; ram[i] = { `add_is, 6'd1, `P2 }; // s2++ (set lsb of running root)
// jump 1 end
i=i+1; ram[i] = { `shl_is, 6'd1, `P0 }; // s0<<=1 (get next input bit)
i=i+1; ram[i] = { `shl_is, 6'd1, `P3 }; // s2<<=1 (get next fudge bit)
i=i+1; ram[i] = { `add_is, -6'd1, `P6 }; // s6-- (loop index--)
i=i+1; ram[i] = { `jmp_inlz, -6'd11, `s6 }; // (s6>=0) ? jump -11 (loop again)
// loop end
// final shift
i=i+1; ram[i] = { `flp, `s0, `P0 }; // flp(s0) (flip remaining bits)
i=i+1; ram[i] = { `add_is, -6'd31, `P0 }; // s0-=31
i=i+1; ram[i] = { `shl_u, `P0, `P1 }; // s1<<=s0, pop s0
// cleanup, return
i=i+1; ram[i] = { `cpy, `P1, `s0 }; // s0=s1, pop s1 (move)
i=i+1; ram[i] = { `pop, 8'b01000110 }; // pop s2, s3, s6
i=i+1; ram[i] = { `gto, `P7, `__ }; // return, pop s7
// end sub
 
end
/trunk/v04.05/boot_code/boot_code_defs.h
0,0 → 1,97
localparam MEM_DATA_W = 16;
localparam IM_W = 6;
// defines that make programming code more human readable
`define __ 4'h0
`define _0 4'h0
`define _1 4'h1
`define _2 4'h2
`define _3 4'h3
`define _4 4'h4
`define _5 4'h5
`define _6 4'h6
`define _7 4'h7
`define P0 4'h8
`define P1 4'h9
`define P2 4'ha
`define P3 4'hb
`define P4 4'hc
`define P5 4'hd
`define P6 4'he
`define P7 4'hf
//
`define nop op_nop[MEM_DATA_W-1:8]
`define pop op_pop[MEM_DATA_W-1:8]
`define pgc op_pgc[MEM_DATA_W-1:8]
`define lit_s op_lit_s[MEM_DATA_W-1:8]
`define lit_h op_lit_h[MEM_DATA_W-1:8]
`define lit_u op_lit_u[MEM_DATA_W-1:8]
`define reg_rs op_reg_rs[MEM_DATA_W-1:8]
`define reg_rh op_reg_rh[MEM_DATA_W-1:8]
`define reg_w op_reg_w[MEM_DATA_W-1:8]
`define reg_wh op_reg_wh[MEM_DATA_W-1:8]
//
`define cpy op_cpy[MEM_DATA_W-1:8]
`define nsg op_nsg[MEM_DATA_W-1:8]
`define not op_not[MEM_DATA_W-1:8]
`define flp op_flp[MEM_DATA_W-1:8]
`define lzc op_lzc[MEM_DATA_W-1:8]
`define bra op_bra[MEM_DATA_W-1:8]
`define bro op_bro[MEM_DATA_W-1:8]
`define brx op_brx[MEM_DATA_W-1:8]
`define and op_and[MEM_DATA_W-1:8]
`define orr op_orr[MEM_DATA_W-1:8]
`define xor op_xor[MEM_DATA_W-1:8]
//
`define add op_add[MEM_DATA_W-1:8]
`define add_xs op_add_xs[MEM_DATA_W-1:8]
`define add_xu op_add_xu[MEM_DATA_W-1:8]
`define sub op_sub[MEM_DATA_W-1:8]
`define sub_xs op_sub_xs[MEM_DATA_W-1:8]
`define sub_xu op_sub_xu[MEM_DATA_W-1:8]
`define mul op_mul[MEM_DATA_W-1:8]
`define mul_xs op_mul_xs[MEM_DATA_W-1:8]
`define mul_xu op_mul_xu[MEM_DATA_W-1:8]
`define shl_s op_shl_s[MEM_DATA_W-1:8]
`define shl_u op_shl_u[MEM_DATA_W-1:8]
`define pow op_pow[MEM_DATA_W-1:8]
//
`define jmp_z op_jmp_z[MEM_DATA_W-1:8]
`define jmp_nz op_jmp_nz[MEM_DATA_W-1:8]
`define jmp_lz op_jmp_lz[MEM_DATA_W-1:8]
`define jmp_nlz op_jmp_nlz[MEM_DATA_W-1:8]
`define jmp op_jmp[MEM_DATA_W-1:8]
`define gto op_gto[MEM_DATA_W-1:8]
`define gsb op_gsb[MEM_DATA_W-1:8]
//
`define mem_irs op_mem_irs[MEM_DATA_W-1:12]
`define mem_irh op_mem_irh[MEM_DATA_W-1:12]
`define mem_iw op_mem_iw[MEM_DATA_W-1:12]
`define mem_iwh op_mem_iwh[MEM_DATA_W-1:12]
//
`define jmp_ie op_jmp_ie[MEM_DATA_W-1:12]
`define jmp_ine op_jmp_ine[MEM_DATA_W-1:12]
`define jmp_ils op_jmp_ils[MEM_DATA_W-1:12]
`define jmp_inls op_jmp_inls[MEM_DATA_W-1:12]
`define jmp_ilu op_jmp_ilu[MEM_DATA_W-1:12]
`define jmp_inlu op_jmp_inlu[MEM_DATA_W-1:12]
//
`define jmp_iz op_jmp_iz[MEM_DATA_W-1:10]
`define jmp_inz op_jmp_inz[MEM_DATA_W-1:10]
`define jmp_ilz op_jmp_ilz[MEM_DATA_W-1:10]
`define jmp_inlz op_jmp_inlz[MEM_DATA_W-1:10]
//
`define dat_is op_dat_is[MEM_DATA_W-1:10]
`define add_is op_add_is[MEM_DATA_W-1:10]
`define shl_is op_shl_is[MEM_DATA_W-1:10]
`define psu_i op_psu_i[MEM_DATA_W-1:10]
//
`define VER VER_ADDR[IM_W-1:0]
`define THRD_ID THRD_ID_ADDR[IM_W-1:0]
`define CLR CLR_ADDR[IM_W-1:0]
`define INTR_EN INTR_EN_ADDR[IM_W-1:0]
`define OP_ER OP_ER_ADDR[IM_W-1:0]
`define STK_ER STK_ER_ADDR[IM_W-1:0]
`define IO_LO IO_LO_ADDR[IM_W-1:0]
`define IO_HI IO_HI_ADDR[IM_W-1:0]
`define UART_RX UART_RX_ADDR[IM_W-1:0]
`define UART_TX UART_TX_ADDR[IM_W-1:0]
/trunk/v04.05/boot_code/boot_code_v_ints.h
0,0 → 1,150
/*
--------------------------------------------------------------------------------
 
Module : boot_code.h
 
--------------------------------------------------------------------------------
 
Function:
- Boot code for a processor core.
 
Instantiates:
- Nothing.
 
Notes:
- For testing (@ core.v):
CLR_BASE = 'h0;
CLR_SPAN = 2; // gives 4 instructions
INTR_BASE = 'h20; // 'd32
INTR_SPAN = 2; // gives 4 instructions
 
 
--------------------------------------------------------------------------------
*/
 
/*
--------------------
-- external stuff --
--------------------
*/
`include "op_encode.h"
`include "reg_set_addr.h"
`include "boot_code_defs.h"
 
/*
----------------------------------------
-- initialize: fill with default data --
----------------------------------------
*/
integer i;
 
initial begin
 
/* // fill with nop (some compilers need this)
for ( i = 0; i < CAPACITY; i = i+1 ) begin
ram[i] = { `nop, `__, `__ };
end
*/
 
/*
---------------
-- boot code --
---------------
*/
 
 
// Thread 0 : enable interrupts
// All threads : output thread ID @ interrupt
 
///////////////
// clr space //
///////////////
 
// thread 0 : enable interrupts & loop forever
i='h0; ram[i] = { `lit_u, `__, `s3 }; // s3='h0100
i=i+1; ram[i] = 16'h0100 ; //
i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3
i=i+1; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
// all others : loop forever
i='h04; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h08; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h0c; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h10; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h14; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h18; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h1c; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
 
////////////////
// intr space //
////////////////
 
// all threads : read and output thread ID
i='h20; ram[i] = { `lit_u, `__, `s3 }; // s3='h0110
i=i+1; ram[i] = 16'h0110 ; //
i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
i=i+1; ram[i] = { `gto, `P0, `__ }; // return, pop s0
//
i='h24; ram[i] = { `lit_u, `__, `s3 }; // s3='h0110
i=i+1; ram[i] = 16'h0110 ; //
i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
i=i+1; ram[i] = { `gto, `P0, `__ }; // return, pop s0
//
i='h28; ram[i] = { `lit_u, `__, `s3 }; // s3='h0110
i=i+1; ram[i] = 16'h0110 ; //
i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
i=i+1; ram[i] = { `gto, `P0, `__ }; // return, pop s0
//
i='h2c; ram[i] = { `lit_u, `__, `s3 }; // s3='h0110
i=i+1; ram[i] = 16'h0110 ; //
i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
i=i+1; ram[i] = { `gto, `P0, `__ }; // return, pop s0
//
i='h30; ram[i] = { `lit_u, `__, `s3 }; // s3='h0110
i=i+1; ram[i] = 16'h0110 ; //
i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
i=i+1; ram[i] = { `gto, `P0, `__ }; // return, pop s0
//
i='h34; ram[i] = { `lit_u, `__, `s3 }; // s3='h0110
i=i+1; ram[i] = 16'h0110 ; //
i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
i=i+1; ram[i] = { `gto, `P0, `__ }; // return, pop s0
//
i='h38; ram[i] = { `lit_u, `__, `s3 }; // s3='h0110
i=i+1; ram[i] = 16'h0110 ; //
i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
i=i+1; ram[i] = { `gto, `P0, `__ }; // return, pop s0
//
i='h3c; ram[i] = { `lit_u, `__, `s3 }; // s3='h0110
i=i+1; ram[i] = 16'h0110 ; //
i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
i=i+1; ram[i] = { `gto, `P0, `__ }; // return, pop s0
 
 
 
///////////////////////
// code & data space //
///////////////////////
 
 
 
/////////////////
// subroutines //
/////////////////
 
 
// sub : enable all ints, return to (s3)
i='h100; ram[i] = { `dat_is, `INTR_EN, `s1 }; // s1=reg addr
i=i+1; ram[i] = { `dat_is, -6'd1, `s0 }; // s0=-1
i=i+1; ram[i] = { `reg_w, `P1, `P0 }; // (s1)=s0, pop both
i=i+1; ram[i] = { `gto, `P3, `__ }; // return, pop s3
 
// sub : read thread ID & write to GPIO, return to (s3)
i='h110; ram[i] = { `dat_is, `THRD_ID, `s1 }; // s1=reg addr
i=i+1; ram[i] = { `reg_rs, `P1, `s0 }; // s0=(s1), pop s1
i=i+1; ram[i] = { `dat_is, `IO_LO, `s1 }; // s1=reg addr
i=i+1; ram[i] = { `reg_w, `P1, `P0 }; // (s1)=s0, pop both
i=i+1; ram[i] = { `gto, `P3, `__ }; // return, pop s3
 
 
end
/trunk/v04.05/boot_code/boot_code_log2.h
0,0 → 1,171
/*
--------------------------------------------------------------------------------
 
Module : boot_code.h
 
--------------------------------------------------------------------------------
 
Function:
- Boot code for a processor core.
 
Instantiates:
- Nothing.
 
Notes:
- For testing (@ core.v):
CLR_BASE = 'h0;
CLR_SPAN = 2; // gives 4 instructions
INTR_BASE = 'h20; // 'd32
INTR_SPAN = 2; // gives 4 instructions
 
 
--------------------------------------------------------------------------------
*/
 
/*
--------------------
-- external stuff --
--------------------
*/
`include "op_encode.h"
`include "reg_set_addr.h"
`include "boot_code_defs.h"
/*
----------------------------------------
-- initialize: fill with default data --
----------------------------------------
*/
integer i;
 
initial begin
 
/* // fill with nop (some compilers need this)
for ( i = 0; i < CAPACITY; i = i+1 ) begin
ram[i] = { `nop, `s0, `s0 };
end
*/
 
/*
---------------
-- boot code --
---------------
*/
 
 
/*
------------
-- TEST 0 --
------------
*/
 
// Log base 2
// Thread 0 : Get input 32 bit GPIO, calculate log2, output 32 bit GPIO.
// Other threads : do nothing, loop forever
 
///////////////
// clr space //
///////////////
 
i='h0; ram[i] = { `lit_u, `__, `s1 }; // s1=addr
i=i+1; ram[i] = 16'h0040 ; //
i=i+1; ram[i] = { `gto, `P1, `__ }; // goto, pop s1 (addr)
//
i='h04; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h08; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h0c; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h10; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h14; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h18; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h1c; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
 
////////////////
// intr space //
////////////////
 
///////////////////////
// code & data space //
///////////////////////
 
// read & write 32 bit GPIO data to & from s0
i='h40; ram[i] = { `lit_u, `__, `s3 }; // s3=addr
i=i+1; ram[i] = 16'h0080 ; //
i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
// do s0=log2(s0)
i=i+1; ram[i] = { `lit_u, `__, `s3 }; // s3=addr
i=i+1; ram[i] = 16'h0090 ; //
i=i+1; ram[i] = { `gsb, `P3, `s7 }; // gsb, pop s3 (addr)
// write s0 data to 32 bit GPIO
i=i+1; ram[i] = { `lit_u, `__, `s3 }; // s3=addr
i=i+1; ram[i] = 16'h0070 ; //
i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
// loop forever
i=i+1; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
 
 
// sub : read 32 bit GPIO => s0, return to (s3)
i='h60; ram[i] = { `dat_is, `IO_LO, `s1 }; // s1=reg addr
i=i+1; ram[i] = { `reg_rs, `P1, `s0 }; // s0=(s1), pop s1
i=i+1; ram[i] = { `dat_is, `IO_HI, `s1 }; // s1=reg addr
i=i+1; ram[i] = { `reg_rh, `P1, `P0 }; // s0=(s1), pop both
i=i+1; ram[i] = { `gto, `P3, `__ }; // return, pop s3
 
 
// sub : write s0 => 32 bit GPIO, return to (s3)
i='h70; ram[i] = { `dat_is, `IO_LO, `s1 }; // s1=reg addr
i=i+1; ram[i] = { `reg_w, `P1, `s0 }; // (s1)=s0, pop s1
i=i+1; ram[i] = { `dat_is, `IO_HI, `s1 }; // s1=reg addr
i=i+1; ram[i] = { `reg_wh, `P1, `s0 }; // (s1)=s0, pop s1
i=i+1; ram[i] = { `gto, `P3, `__ }; // return, pop s3
 
 
// sub : read & write 32 bit GPIO => s0, return to (s3)
i='h80; ram[i] = { `dat_is, `IO_LO, `s1 }; // s1=reg addr
i=i+1; ram[i] = { `reg_rs, `s1, `s0 }; // s0=(s1)
i=i+1; ram[i] = { `reg_w, `P1, `s0 }; // (s1)=s0, pop s1
i=i+1; ram[i] = { `dat_is, `IO_HI, `s1 }; // s1=reg addr
i=i+1; ram[i] = { `reg_rh, `s1, `P0 }; // s0=(s1), pop s0
i=i+1; ram[i] = { `reg_wh, `P1, `s0 }; // (s1)=s0, pop s1
i=i+1; ram[i] = { `gto, `P3, `__ }; // return, pop s3
 
 
 
// sub : s0=log2(s0), return to (s7)
//
// input is in[31:0] an unsigned 32 bit integer
// output is c[31:27].m[26:0] unsigned fixed decimal
//
// s0 : input, normalize, square, output
// s1 : lzc, result
// s2 :
// s3 :
// s4 :
// s5 :
// s6 : loop index
// s7 : sub return address
//
// (input=0)? is an error, return
i='h90; ram[i] = { `jmp_inz, 6'd1, `s0 }; // (s0!=0) ? skip return
i=i+1; ram[i] = { `gto, `P7, `__ }; // return to (s7), pop s7
// normalize
i=i+1; ram[i] = { `lzc, `s0, `s1 }; // s1=lzc(s0)
i=i+1; ram[i] = { `shl_s, `s1, `P0 }; // s0<<=s1 (normalize)
// loop setup
i=i+1; ram[i] = { `dat_is, 6'd26, `s6 }; // s6=26 (loop index)
// loop start
i=i+1; ram[i] = { `mul_xu, `s0, `P0 }; // s0*=s0
i=i+1; ram[i] = { `shl_is, 6'd1, `P1 }; // s1<<=1
// jump start
i=i+1; ram[i] = { `jmp_ilz, 6'd2, `s0 }; // (s0[31]==1) ? jump
i=i+1; ram[i] = { `shl_is, 6'd1, `P0 }; // s0<<=1
i=i+1; ram[i] = { `add_is, 6'd1, `P1 }; // s1++
// jump end
i=i+1; ram[i] = { `add_is, -6'd1, `P6 }; // s6--
i=i+1; ram[i] = { `jmp_inlz, -6'd7, `s6 }; // (s6>=0) ? do again
// loop end
// cleanup, return
i=i+1; ram[i] = { `not, `P1, `P0 }; // s0=~s1, pop both
i=i+1; ram[i] = { `gto, `P7, `P6 }; // return, pop s7 & s6
// end sub
 
end
/trunk/v04.05/boot_code/boot_code_divide.h
0,0 → 1,176
/*
--------------------------------------------------------------------------------
 
Module : boot_code.h
 
--------------------------------------------------------------------------------
 
Function:
- Boot code for a processor core.
 
Instantiates:
- Nothing.
 
Notes:
- For testing (@ core.v):
CLR_BASE = 'h0;
CLR_SPAN = 2; // gives 4 instructions
INTR_BASE = 'h20; // 'd32
INTR_SPAN = 2; // gives 4 instructions
 
 
--------------------------------------------------------------------------------
*/
 
/*
--------------------
-- external stuff --
--------------------
*/
`include "op_encode.h"
`include "reg_set_addr.h"
`include "boot_code_defs.h"
 
 
/*
----------------------------------------
-- initialize: fill with default data --
----------------------------------------
*/
integer i;
 
initial begin
 
/* // fill with nop (some compilers need this)
for ( i = 0; i < CAPACITY; i = i+1 ) begin
ram[i] = { `nop, `s0, `s0 };
end
*/
 
/*
---------------
-- boot code --
---------------
*/
 
 
/*
------------
-- TEST 0 --
------------
*/
 
// Divide - both inputs positive.
// Thread 0 : Get input 32 bit GPIO 2x, divide, output 32 bit GPIO 2x.
// Other threads : do nothing, loop forever
 
///////////////
// clr space //
///////////////
 
i='h0; ram[i] = { `lit_u, `__, `s1 }; // s1=addr
i=i+1; ram[i] = 16'h0040 ; //
i=i+1; ram[i] = { `gto, `P1, `__ }; // goto, pop s1 (addr)
//
i='h04; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h08; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h0c; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h10; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h14; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h18; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h1c; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
 
////////////////
// intr space //
////////////////
 
///////////////////////
// code & data space //
///////////////////////
 
// read & write 32 bit GPIO data to & from s0 2x
i='h40; ram[i] = { `lit_u, `__, `s3 }; // s3=addr
i=i+1; ram[i] = 16'h0080 ; //
i=i+1; ram[i] = { `gsb, `s3, `s3 }; // gsb
i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
// do s0/s1
i=i+1; ram[i] = { `lit_u, `__, `s3 }; // s3=addr
i=i+1; ram[i] = 16'h0090 ; //
i=i+1; ram[i] = { `gsb, `P3, `s7 }; // gsb, pop s3 (addr)
// write s0 data to 32 bit GPIO 2x
i=i+1; ram[i] = { `lit_u, `__, `s3 }; // s3=addr
i=i+1; ram[i] = 16'h0070 ; //
i=i+1; ram[i] = { `gsb, `s3, `s3 }; // gsb
i=i+1; ram[i] = { `pop, 8'b00000001 }; // pop s0
i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
// loop forever
i=i+1; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
 
 
// sub : read 32 bit GPIO => s0, return to (s3)
i='h60; ram[i] = { `dat_is, `IO_LO, `s1 }; // s1=reg addr
i=i+1; ram[i] = { `reg_rs, `P1, `s0 }; // s0=(s1), pop s1
i=i+1; ram[i] = { `dat_is, `IO_HI, `s1 }; // s1=reg addr
i=i+1; ram[i] = { `reg_rh, `P1, `P0 }; // s0=(s1), pop both
i=i+1; ram[i] = { `gto, `P3, `__ }; // return, pop s3
 
 
// sub : write s0 => 32 bit GPIO, return to (s3)
i='h70; ram[i] = { `dat_is, `IO_LO, `s1 }; // s1=reg addr
i=i+1; ram[i] = { `reg_w, `P1, `s0 }; // (s1)=s0, pop s1
i=i+1; ram[i] = { `dat_is, `IO_HI, `s1 }; // s1=reg addr
i=i+1; ram[i] = { `reg_wh, `P1, `s0 }; // (s1)=s0, pop s1
i=i+1; ram[i] = { `gto, `P3, `__ }; // return, pop s3
 
 
// sub : read & write 32 bit GPIO => s0, return to (s3)
i='h80; ram[i] = { `dat_is, `IO_LO, `s1 }; // s1=reg addr
i=i+1; ram[i] = { `reg_rs, `s1, `s0 }; // s0=(s1)
i=i+1; ram[i] = { `reg_w, `P1, `s0 }; // (s1)=s0, pop s1
i=i+1; ram[i] = { `dat_is, `IO_HI, `s1 }; // s1=reg addr
i=i+1; ram[i] = { `reg_rh, `s1, `P0 }; // s0=(s1), pop s0
i=i+1; ram[i] = { `reg_wh, `P1, `s0 }; // (s1)=s0, pop s1
i=i+1; ram[i] = { `gto, `P3, `__ }; // return, pop s3
 
 
// sub : unsigned divide & modulo remainder, return to (s7)
//
// algorithm: binary search
//
// s0 : N, D(top)/N(under) input, Q(top)/R(under) output
// s1 : D
// s2 : Q
// s3 :
// s4 :
// s5 :
// s6 : one-hot (& loop test)
// s7 : sub return address
//
// (D=0)? is an error, return
i='h90; ram[i] = { `jmp_inz, 6'd1, `s0 }; // (s0!=0) ? skip return
i=i+1; ram[i] = { `gto, `P7, `__ }; // return to (s7), pop s7
// loop setup
i=i+1; ram[i] = { `cpy, `P0, `s1 }; // s0=>s1 (s1=D, s0=N)
i=i+1; ram[i] = { `dat_is, 6'd0, `s2 }; // s2=0 (s2=init Q)
i=i+1; ram[i] = { `lzc, `s1, `s6 }; // s6=lzc(s1)
i=i+1; ram[i] = { `pow, `s6, `P6 }; // s6=1<<s6, pop s6 (s6=init OH)
// loop start
i=i+1; ram[i] = { `add, `s6, `P2 }; // s2+=s6 (s2=new trial Q)
i=i+1; ram[i] = { `mul, `s2, `s1 }; // s1=s1*s2 (s1=D*Q)
// jump start
i=i+1; ram[i] = { `jmp_inlu, 4'd1, `P1, `s0 }; // (s0>=s1) ? skip restore, pop s1 (N>=D*Q)
i=i+1; ram[i] = { `sub, `s6, `P2 }; // s2-=s6 (s2=restored Q)
// jump end
i=i+1; ram[i] = { `psu_i, -6'd1, `P6 }; // s6>>=1 (new OH)
i=i+1; ram[i] = { `jmp_inz, -6'd6, `s6 }; // (s6!=0) ? do again
// loop end
// calc remainder, move Q
i=i+1; ram[i] = { `mul, `s2, `P1 }; // s1*=s2 (s1=D*Q)
i=i+1; ram[i] = { `sub, `P1, `P0 }; // s0-=s1, pop both (s0=N-D*Q=R)
i=i+1; ram[i] = { `cpy, `P2, `s0 }; // s0=s2, pop s2 (s0=Q)
// return
i=i+1; ram[i] = { `gto, `P7, `P6 }; // return to (s7), pop s7 & s6
// end sub
 
end
/trunk/v04.05/boot_code/boot_code_v_alu.h
0,0 → 1,514
/*
--------------------------------------------------------------------------------
 
Module : boot_code.h
 
--------------------------------------------------------------------------------
 
Function:
- Boot code for a processor core.
 
Instantiates:
- Nothing.
 
Notes:
- For testing (@ core.v):
CLR_BASE = 'h0;
CLR_SPAN = 2; // gives 4 instructions
INTR_BASE = 'h20; // 'd32
INTR_SPAN = 2; // gives 4 instructions
 
 
--------------------------------------------------------------------------------
*/
 
/*
--------------------
-- external stuff --
--------------------
*/
`include "op_encode.h"
`include "reg_set_addr.h"
`include "boot_code_defs.h"
/*
----------------------------------------
-- initialize: fill with default data --
----------------------------------------
*/
integer i;
 
initial begin
 
/* // fill with nop (some compilers need this)
for ( i = 0; i < CAPACITY; i = i+1 ) begin
ram[i] = { `nop, `__, `__ };
end
*/
 
/*
---------------
-- boot code --
---------------
*/
 
 
// Thread 0 : test ALU logical functions
// Thread 1 : test ALU arithmetic functions
// Thread 2 : test ALU shift functions
// All other threads : loop forever
 
///////////////
// clr space //
///////////////
 
// thread 0
i='h00; ram[i] = { `lit_u, `__, `s2 }; // s2=dat
i=i+1; ram[i] = 16'h0100 ; // addr
i=i+1; ram[i] = { `gto, `P2, `__ }; // goto, pop s2 (addr)
// thread 1
i='h04; ram[i] = { `lit_u, `__, `s2 }; // s2=dat
i=i+1; ram[i] = 16'h0200 ; // addr
i=i+1; ram[i] = { `gto, `P2, `__ }; // goto, pop s2 (addr)
// thread 2
i='h08; ram[i] = { `lit_u, `__, `s2 }; // s2=dat
i=i+1; ram[i] = 16'h0300 ; // addr
i=i+1; ram[i] = { `gto, `P2, `__ }; // goto, pop s2 (addr)
// and the rest (are here on Gilligan's Isle)
i='h0c; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h10; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h14; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h18; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h1c; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
 
////////////////
// intr space //
////////////////
 
///////////////////////
// code & data space //
///////////////////////
 
 
// test ALU logical functions, result in s0
// Correct functioning is s0 = 'd14 ('he).
//
// s0 : final test result
// s1 : test value
// s2 : test value
// s3 : running test result, subroutine return address
//
// setup running test result:
i='h100; ram[i] = { `dat_is, 6'd0, `s3 }; // s3=0
// load s1 & s2 values
i=i+1; ram[i] = { `dat_is, 6'd1, `s1 }; // s1=1
i=i+1; ram[i] = { `dat_is, -6'd1, `s2 }; // s2=-1
// BRA ( &(1)= 0; &(-1)=-1 )
i=i+1; ram[i] = { `bra, `s1, `s0 }; // s0=&s1
i=i+1; ram[i] = { `jmp_iz, 6'd1, `P0 }; // (s0==0) ? skip, pop s0
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
//
i=i+1; ram[i] = { `bra, `s2, `s0 }; // s0=&s2
i=i+1; ram[i] = { `jmp_inz, 6'd1, `P0 }; // (s0!=0) ? skip, pop s0
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// BRO ( |(1)=-1; |(-1)=-1 )
i=i+1; ram[i] = { `bro, `s1, `s0 }; // s0=|s1
i=i+1; ram[i] = { `jmp_inz, 6'd1, `P0 }; // (s0!=0) ? skip, pop s0
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
//
i=i+1; ram[i] = { `bro, `s2, `s0 }; // s0=|s2
i=i+1; ram[i] = { `jmp_inz, 6'd1, `P0 }; // (s0!=0) ? skip, pop s0
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// BRX ( ^(1)=-1; ^(-1)=0 )
i=i+1; ram[i] = { `brx, `s1, `s0 }; // s0=^s1
i=i+1; ram[i] = { `jmp_inz, 6'd1, `P0 }; // (s0!=0) ? skip, pop s0
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
//
i=i+1; ram[i] = { `brx, `s2, `s0 }; // s0=^s2
i=i+1; ram[i] = { `jmp_iz, 6'd1, `P0 }; // (s0==0) ? skip, pop s0
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// clean up
i=i+1; ram[i] = { `pop, 8'b00000110 }; // pop s2 & s1
// load s1 & s2 values
i=i+1; ram[i] = { `lit_u, `__, `s1 }; // s1='h36c9,a53c
i=i+1; ram[i] = 16'ha53c ; //
i=i+1; ram[i] = { `lit_h, `__, `P1 }; //
i=i+1; ram[i] = 16'h36c9 ; //
//
i=i+1; ram[i] = { `lit_u, `__, `s2 }; // s2='h5ca3,c396
i=i+1; ram[i] = 16'hc396 ; //
i=i+1; ram[i] = { `lit_h, `__, `P2 }; //
i=i+1; ram[i] = 16'h5ca3 ; //
// AND (s/b 'h1481,8114)
i=i+1; ram[i] = { `and, `s2, `s1 }; // s1=s1&s2
i=i+1; ram[i] = { `lit_u, `__, `s0 }; // s0='h1481,8114
i=i+1; ram[i] = 16'h8114 ; //
i=i+1; ram[i] = { `lit_h, `__, `P0 }; //
i=i+1; ram[i] = 16'h1481 ; //
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// OR (s/b 'h7eeb,e7be)
i=i+1; ram[i] = { `orr, `s2, `s1 }; // s1=s1|s2
i=i+1; ram[i] = { `lit_u, `__, `s0 }; // s0='h7eeb,e7be
i=i+1; ram[i] = 16'he7be ; //
i=i+1; ram[i] = { `lit_h, `__, `P0 }; //
i=i+1; ram[i] = 16'h7eeb ; //
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// XOR (s/b 'h6a6a,66aa)
i=i+1; ram[i] = { `xor, `s2, `s1 }; // s1=s1^s2
i=i+1; ram[i] = { `lit_u, `__, `s0 }; // s0='h6a6a,66aa
i=i+1; ram[i] = 16'h66aa ; //
i=i+1; ram[i] = { `lit_h, `__, `P0 }; //
i=i+1; ram[i] = 16'h6a6a ; //
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// NOT (s/b 'hc936,5ac3)
i=i+1; ram[i] = { `not, `s1, `s1 }; // s1=~s1
i=i+1; ram[i] = { `lit_u, `__, `s0 }; // s0='hc936,5ac3
i=i+1; ram[i] = 16'h5ac3 ; //
i=i+1; ram[i] = { `lit_h, `__, `P0 }; //
i=i+1; ram[i] = 16'hc936 ; //
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// FLP (s/b 'h3ca5,936c)
i=i+1; ram[i] = { `flp, `s1, `s1 }; // s1=flip(s1)
i=i+1; ram[i] = { `lit_u, `__, `s0 }; // s0='h3ca5,936c
i=i+1; ram[i] = 16'h936c ; //
i=i+1; ram[i] = { `lit_h, `__, `P0 }; //
i=i+1; ram[i] = 16'h3ca5 ; //
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// LZC (s/b 'h0000,0002)
i=i+1; ram[i] = { `lzc, `s1, `s1 }; // s1=lzc(s1)
i=i+1; ram[i] = { `lit_u, `__, `s0 }; // s0='h0000,0002
i=i+1; ram[i] = 16'h0002 ; //
i=i+1; ram[i] = { `lit_h, `__, `P0 }; //
i=i+1; ram[i] = 16'h0000 ; //
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// check for no opcode errors
i=i+1; ram[i] = { `lit_u, `__, `s7 }; // s7='h0900
i=i+1; ram[i] = 16'h0900 ; //
i=i+1; ram[i] = { `gsb, `P7, `s7 }; // gsb, pop s7 (addr)
i=i+1; ram[i] = { `jmp_iz, 6'd1, `P4 }; // (s4==0) ? skip, pop s4
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// check for no stack errors
i=i+1; ram[i] = { `lit_u, `__, `s7 }; // s7='h0910
i=i+1; ram[i] = 16'h0910 ; //
i=i+1; ram[i] = { `gsb, `P7, `s7 }; // gsb, pop s7 (addr)
i=i+1; ram[i] = { `jmp_iz, 6'd1, `P4 }; // (s4==0) ? skip, pop s4
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// copy result to s0
i=i+1; ram[i] = { `cpy, `P3, `s0 }; // s0=s3, pop s3
// loop forever
i=i+1; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
 
 
// test ALU arithmetic functions, result in s0
// Correct functioning is s0 = 'd13 ('hd).
//
// s0 : final test result
// s1 : test value
// s2 : test value
// s3 : running test result, subroutine return address
//
// setup running test result:
i='h200; ram[i] = { `dat_is, 6'd0, `s3 }; // s3=0
// load s1 & s2 values
i=i+1; ram[i] = { `lit_u, `__, `s1 }; // s1='ha53c,36c9
i=i+1; ram[i] = 16'h36c9 ; //
i=i+1; ram[i] = { `lit_h, `__, `P1 }; //
i=i+1; ram[i] = 16'ha53c ; //
//
i=i+1; ram[i] = { `lit_u, `__, `s2 }; // s2='h5ca3,c396
i=i+1; ram[i] = 16'hc396 ; //
i=i+1; ram[i] = { `lit_h, `__, `P2 }; //
i=i+1; ram[i] = 16'h5ca3 ; //
// ADD_I -32 (s/b 'ha53c,36a9)
i=i+1; ram[i] = { `add_is, -6'd32, `s1 }; // s1=s1-32
i=i+1; ram[i] = { `lit_u, `__, `s0 }; // s0='ha53c,36a9
i=i+1; ram[i] = 16'h36a9 ; //
i=i+1; ram[i] = { `lit_h, `__, `P0 }; //
i=i+1; ram[i] = 16'ha53c ; //
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// ADD_I +31 (s/b 'ha53c,36e8)
i=i+1; ram[i] = { `add_is, 6'd31, `s1 }; // s1=s1+31
i=i+1; ram[i] = { `lit_u, `__, `s0 }; // s0='ha53c,36e8
i=i+1; ram[i] = 16'h36e8 ; //
i=i+1; ram[i] = { `lit_h, `__, `P0 }; //
i=i+1; ram[i] = 16'ha53c ; //
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// ADD (s/b 'h01df,fa5f)
i=i+1; ram[i] = { `add, `s2, `s1 }; // s1=s1+s2
i=i+1; ram[i] = { `lit_u, `__, `s0 }; // s0='h01df,fa5f
i=i+1; ram[i] = 16'hfa5f ; //
i=i+1; ram[i] = { `lit_h, `__, `P0 }; //
i=i+1; ram[i] = 16'h01df ; //
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// ADD_XS (s/b 0)
i=i+1; ram[i] = { `add_xs, `s2, `s1 }; // s1=s1+s2
i=i+1; ram[i] = { `dat_is, 6'd0, `s0 }; // s0=0
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// ADD_XU (s/b 1)
i=i+1; ram[i] = { `add_xu, `s2, `s1 }; // s1=s1+s2
i=i+1; ram[i] = { `dat_is, 6'd1, `s0 }; // s0=1
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// SUB (s/b 'h4898,7333)
i=i+1; ram[i] = { `sub, `s2, `s1 }; // s1=s1-s2
i=i+1; ram[i] = { `lit_u, `__, `s0 }; // s0='h4898,7333
i=i+1; ram[i] = 16'h7333 ; //
i=i+1; ram[i] = { `lit_h, `__, `P0 }; //
i=i+1; ram[i] = 16'h4898 ; //
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// SUB_XS (s/b -1)
i=i+1; ram[i] = { `sub_xs, `s2, `s1 }; // s1=s1-s2
i=i+1; ram[i] = { `dat_is, -6'd1, `s0 }; // s0=-1
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// SUB_XU (s/b 0)
i=i+1; ram[i] = { `sub_xu, `s2, `s1 }; // s1=s1-s2
i=i+1; ram[i] = { `dat_is, 6'd0, `s0 }; // s0=0
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// MUL (s/b 'hccfe,34c6)
i=i+1; ram[i] = { `mul, `s2, `s1 }; // s1=s1*s2
i=i+1; ram[i] = { `lit_u, `__, `s0 }; // s0='hccfe,34c6
i=i+1; ram[i] = 16'h34c6 ; //
i=i+1; ram[i] = { `lit_h, `__, `P0 }; //
i=i+1; ram[i] = 16'hccfe ; //
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// MUL_XS (s/b 'hdf27,93ae)
i=i+1; ram[i] = { `mul_xs, `s2, `s1 }; // s1=s1*s2
i=i+1; ram[i] = { `lit_u, `__, `s0 }; // s0='hdf27,93ae
i=i+1; ram[i] = 16'h93ae ; //
i=i+1; ram[i] = { `lit_h, `__, `P0 }; //
i=i+1; ram[i] = 16'hdf27 ; //
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// MUL_XU (s/b 'h3bcb,5744)
i=i+1; ram[i] = { `mul_xu, `s2, `s1 }; // s1=s1*s2
i=i+1; ram[i] = { `lit_u, `__, `s0 }; // s0='h3bcb,5744
i=i+1; ram[i] = 16'h5744 ; //
i=i+1; ram[i] = { `lit_h, `__, `P0 }; //
i=i+1; ram[i] = 16'h3bcb ; //
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// check for no opcode errors
i=i+1; ram[i] = { `lit_u, `__, `s7 }; // s7='h0900
i=i+1; ram[i] = 16'h0900 ; //
i=i+1; ram[i] = { `gsb, `P7, `s7 }; // gsb, pop s7 (addr)
i=i+1; ram[i] = { `jmp_iz, 6'd1, `P4 }; // (s4==0) ? skip, pop s4
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// check for no stack errors
i=i+1; ram[i] = { `lit_u, `__, `s7 }; // s7='h0910
i=i+1; ram[i] = 16'h0910 ; //
i=i+1; ram[i] = { `gsb, `P7, `s7 }; // gsb, pop s7 (addr)
i=i+1; ram[i] = { `jmp_iz, 6'd1, `P4 }; // (s4==0) ? skip, pop s4
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// copy result to s0
i=i+1; ram[i] = { `cpy, `P3, `s0 }; // s0=s3, pop s3
// loop forever
i=i+1; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
 
 
// test ALU shift functions, result in s0
// Correct functioning is s0 = 'd12 ('hc).
//
// s0 : final test result
// s1 : test value
// s2 : test value
// s3 : running test result, subroutine return address
//
// setup running test result:
i='h300; ram[i] = { `dat_is, 6'd0, `s3 }; // s3=0
// load s1 test value
i=i+1; ram[i] = { `lit_u, `__, `s1 }; // s1='ha53c,36c9
i=i+1; ram[i] = 16'h36c9 ; // hi data
i=i+1; ram[i] = { `lit_h, `__, `P1 }; // lit => s1, pop combine
i=i+1; ram[i] = 16'ha53c ; // lo data
// SHL_IS -28 (s/b 'hffff,fffa)
i=i+1; ram[i] = { `shl_is, -6'd28, `s1 }; // s1>>=28
i=i+1; ram[i] = { `lit_u, `__, `s0 }; // s0='hffff,fffa
i=i+1; ram[i] = 16'hfffa ; //
i=i+1; ram[i] = { `lit_h, `__, `P0 }; //
i=i+1; ram[i] = 16'hffff ; //
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// SHL_IS +28 (s/b 'h9000,0000)
i=i+1; ram[i] = { `shl_is, 6'd28, `s1 }; // s1<<=28
i=i+1; ram[i] = { `lit_u, `__, `s0 }; // s0='h9000,0000
i=i+1; ram[i] = 16'h0000 ; //
i=i+1; ram[i] = { `lit_h, `__, `P0 }; //
i=i+1; ram[i] = 16'h9000 ; //
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// PSU_I -28 (s/b 'h0000,000a)
i=i+1; ram[i] = { `psu_i, -6'd28, `s1 }; // s1>>=28
i=i+1; ram[i] = { `lit_u, `__, `s0 }; // s0='h0000,000a
i=i+1; ram[i] = 16'h000a ; //
i=i+1; ram[i] = { `lit_h, `__, `P0 }; //
i=i+1; ram[i] = 16'h0000 ; //
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// PSU_I +28 (s/b 'h1000,0000)
i=i+1; ram[i] = { `psu_i, 6'd28, `s1 }; // s1=1<<28
i=i+1; ram[i] = { `lit_u, `__, `s0 }; // s0='h1000,0000
i=i+1; ram[i] = 16'h0000 ; //
i=i+1; ram[i] = { `lit_h, `__, `P0 }; //
i=i+1; ram[i] = 16'h1000 ; //
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// SHL_S -4 (s/b 'hfa53,c36c)
i=i+1; ram[i] = { `dat_is, -6'd4, `s2 }; // s2=-4
i=i+1; ram[i] = { `shl_s, `P2, `s1 }; // s1<<=s2, pop s2
i=i+1; ram[i] = { `lit_u, `__, `s0 }; // s0='hfa53,c36c
i=i+1; ram[i] = 16'hc36c ; //
i=i+1; ram[i] = { `lit_h, `__, `P0 }; //
i=i+1; ram[i] = 16'hfa53 ; //
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// SHL_S +4 (s/b 'h53c3,6c90)
i=i+1; ram[i] = { `dat_is, 6'd4, `s2 }; // s2=4
i=i+1; ram[i] = { `shl_s, `P2, `s1 }; // s1<<=s2, pop s2
i=i+1; ram[i] = { `lit_u, `__, `s0 }; // s0='h53c3,6c90
i=i+1; ram[i] = 16'h6c90 ; //
i=i+1; ram[i] = { `lit_h, `__, `P0 }; //
i=i+1; ram[i] = 16'h53c3 ; //
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// SHL_U -4 (s/b 'h0a53,c36c)
i=i+1; ram[i] = { `dat_is, -6'd4, `s2 }; // s2=-4
i=i+1; ram[i] = { `shl_u, `P2, `s1 }; // s1<<=s2, pop s2
i=i+1; ram[i] = { `lit_u, `__, `s0 }; // s0='h0a53,c36c
i=i+1; ram[i] = 16'hc36c ; //
i=i+1; ram[i] = { `lit_h, `__, `P0 }; //
i=i+1; ram[i] = 16'h0a53 ; //
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// SHL_U +4 (s/b 'h53c3,6c90)
i=i+1; ram[i] = { `dat_is, 6'd4, `s2 }; // s2=4
i=i+1; ram[i] = { `shl_u, `P2, `s1 }; // s1<<=s2, pop s2
i=i+1; ram[i] = { `lit_u, `__, `s0 }; // s0='h53c3,6c90
i=i+1; ram[i] = 16'h6c90 ; //
i=i+1; ram[i] = { `lit_h, `__, `P0 }; //
i=i+1; ram[i] = 16'h53c3 ; //
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// POW -4 (s/b 'h1000,0000)
i=i+1; ram[i] = { `dat_is, -6'd4, `s2 }; // s2=-4
i=i+1; ram[i] = { `pow, `P2, `s1 }; // s1=1<<s2, pop s2
i=i+1; ram[i] = { `lit_u, `__, `s0 }; // s0='h0000,0000
i=i+1; ram[i] = 16'h0000 ; //
i=i+1; ram[i] = { `lit_h, `__, `P0 }; //
i=i+1; ram[i] = 16'h1000 ; //
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// POW +4 (s/b 'h0000,0010)
i=i+1; ram[i] = { `dat_is, 6'd4, `s2 }; // s2=4
i=i+1; ram[i] = { `pow, `P2, `s1 }; // s1=1<<s2, pop s2
i=i+1; ram[i] = { `lit_u, `__, `s0 }; // s0='h0000,0010
i=i+1; ram[i] = 16'h0010 ; //
i=i+1; ram[i] = { `lit_h, `__, `P0 }; //
i=i+1; ram[i] = 16'h0000 ; //
i=i+1; ram[i] = { `jmp_ie, 4'd1, `P1, `P0 }; // (s0==s1) ? skip, pop both
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// check for no opcode errors
i=i+1; ram[i] = { `lit_u, `__, `s7 }; // s7='h0900
i=i+1; ram[i] = 16'h0900 ; //
i=i+1; ram[i] = { `gsb, `P7, `s7 }; // gsb, pop s7 (addr)
i=i+1; ram[i] = { `jmp_iz, 6'd1, `P4 }; // (s4==0) ? skip, pop s4
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// check for no stack errors
i=i+1; ram[i] = { `lit_u, `__, `s7 }; // s7='h0910
i=i+1; ram[i] = 16'h0910 ; //
i=i+1; ram[i] = { `gsb, `P7, `s7 }; // gsb, pop s7 (addr)
i=i+1; ram[i] = { `jmp_iz, 6'd1, `P4 }; // (s4==0) ? skip, pop s4
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// copy result to s0
i=i+1; ram[i] = { `cpy, `P3, `s0 }; // s0=s3, pop s3
// loop forever
i=i+1; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
 
 
 
 
/////////////////
// subroutines //
/////////////////
 
 
// sub : read & clear opcode errors for this thread => s4, return to (s7)
// avoid the use of s1!
i='h900; ram[i] = { `dat_is, `THRD_ID, `s6 }; // s6=reg addr
i=i+1; ram[i] = { `reg_rs, `P6, `s5 }; // s5=(s6), pop s6
i=i+1; ram[i] = { `pow, `P5, `s4 }; // s4=1<<s5, pop s5
i=i+1; ram[i] = { `dat_is, `OP_ER, `s6 }; // s6=reg addr
i=i+1; ram[i] = { `reg_rs, `s6, `s5 }; // s5=(s6)
i=i+1; ram[i] = { `and, `P5, `P4 }; // s4&=s5, pop s5
i=i+1; ram[i] = { `reg_w, `P6, `s4 }; // (s6)=s4, pop s6
i=i+1; ram[i] = { `gto, `P7, `__ }; // return to (s7), pop s7
 
 
// sub : read & clear stack errors for this thread => s4, return to (s7)
// avoid the use of s1!
i='h910; ram[i] = { `dat_is, `THRD_ID, `s6 }; // s6=reg addr
i=i+1; ram[i] = { `reg_rs, `P6, `s5 }; // s5=(s6), pop s6
i=i+1; ram[i] = { `pow, `P5, `s4 }; // s4=1<<s5, pop s5
i=i+1; ram[i] = { `cpy, `s4, `s5 }; // s5=s4
i=i+1; ram[i] = { `shl_is, 6'd8, `P5 }; // s5<<=8
i=i+1; ram[i] = { `orr, `P5, `P4 }; // s4|=s5, pop s5
i=i+1; ram[i] = { `dat_is, `STK_ER, `s6 }; // s6=reg addr
i=i+1; ram[i] = { `reg_rs, `s6, `s5 }; // s5=(s6)
i=i+1; ram[i] = { `and, `P5, `P4 }; // s4&=s5, pop s5
i=i+1; ram[i] = { `reg_w, `P6, `s4 }; // (s6)=s4, pop s6
i=i+1; ram[i] = { `gto, `P7, `__ }; // return to (s7), pop s7
 
 
end
/trunk/v04.05/boot_code/boot_code_led_pwm.h
0,0 → 1,172
/*
--------------------------------------------------------------------------------
 
Module : boot_code.h
 
--------------------------------------------------------------------------------
 
Function:
- Boot code for a processor core.
 
Instantiates:
- Nothing.
 
Notes:
- For testing (@ core.v):
CLR_BASE = 'h0;
CLR_SPAN = 2; // gives 4 instructions
INTR_BASE = 'h20; // 'd32
INTR_SPAN = 2; // gives 4 instructions
 
 
--------------------------------------------------------------------------------
*/
 
/*
--------------------
-- external stuff --
--------------------
*/
`include "boot_code_defs.h"
/*
----------------------------------------
-- initialize: fill with default data --
----------------------------------------
*/
integer i;
 
initial begin
 
/* // fill with nop (some compilers need this)
for ( i = 0; i < CAPACITY; i = i+1 ) begin
ram[i] = { `nop, `__, `__ };
end
*/
 
/*
---------------
-- boot code --
---------------
*/
 
 
// Thread 0 : do LED PWM action
// All other threads : loop forever
 
///////////////
// clr space //
///////////////
 
// thread 0
i='h00; ram[i] = { `lit_u, `__, `s2 }; // s2=dat
i=i+1; ram[i] = 16'h0100 ; // addr
i=i+1; ram[i] = { `gto, `P2, `__ }; // goto, pop s2 (addr)
// and the rest
i='h04; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h08; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h0c; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h10; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h14; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h18; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h1c; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
 
////////////////
// intr space //
////////////////
 
///////////////////////
// code & data space //
///////////////////////
 
/*
// simple binary count LED display
i='h100; ram[i] = { `dat_is, 6'd0, `s0 }; // s0=0
i=i+1; ram[i] = { `dat_is, `IO_LO, `s1 }; // s1=reg addr
// loop start
i=i+1; ram[i] = { `add_is, 6'd1, `P0 }; // s0++
i=i+1; ram[i] = { `psu_i, -6'd20, `s0 }; // s0=s0>>20
i=i+1; ram[i] = { `reg_w, `s1, `P0 }; // (s1)=s0, pop s0
i=i+1; ram[i] = { `jmp_ie, -4'd4, `s0, `s0 }; // loop forever
// loop end
*/
 
/*
// simple sequential LED display
i='h100; ram[i] = { `dat_is, 6'd0, `s0 }; // s0=0
i=i+1; ram[i] = { `dat_is, `IO_LO, `s1 }; // s1=reg addr
// loop start
i=i+1; ram[i] = { `add_is, 6'd1, `P0 }; // s0++
i=i+1; ram[i] = { `shl_is, 6'd10, `s0 }; // s0=s0<<10
i=i+1; ram[i] = { `psu_i, -6'd30, `P0 }; // s0=s0>>30, pop s0
i=i+1; ram[i] = { `pow, `P0, `s0 }; // s0=1<<s0, pop s0
i=i+1; ram[i] = { `reg_w, `s1, `P0 }; // (s1)=s0, pop s0
i=i+1; ram[i] = { `jmp_ie, -4'd6, `s0, `s0 }; // loop forever
// loop end
*/
 
/*
// sequential LED display w/ PWM - moving "dark spot"
i='h100; ram[i] = { `dat_is, 6'd0, `s0 }; // s0=0
i=i+1; ram[i] = { `dat_is, `IO_LO, `s1 }; // s1=reg addr
i=i+1; ram[i] = { `dat_is, 6'd0, `s2 }; // s2=pwm
// loop start
i=i+1; ram[i] = { `shl_is, 6'd13, `s0 }; // s0=s0<<13 - isolate decimal
i=i+1; ram[i] = { `add, `P0, `P2 }; // s2+=s0, pop s0 - add to pwm counter
i=i+1; ram[i] = { `add_is, 6'd1, `P0 }; // s0++ - get next value
i=i+1; ram[i] = { `shl_is, 6'd13, `s0 }; // s0=s0<<13 - isolate decimal
i=i+1; ram[i] = { `add_xu, `P0, `s2 }; // s2=s2+s0, pop s0 - see if it will cause pwm counter overflow
i=i+1; ram[i] = { `shl_is, 6'd19, `P2 }; // s2<<=19 - shift up to ones place
i=i+1; ram[i] = { `add, `P2, `s0 }; // s0+=s2, pop s2 - add pwm bit
i=i+1; ram[i] = { `shl_is, 6'd11, `P0 }; // s0<<=11 - isolate integer
i=i+1; ram[i] = { `psu_i, -6'd30, `P0 }; // s0>>=30
i=i+1; ram[i] = { `pow, `s0, `P0 }; // s0=1<<s0, pop s0 - do one hot
i=i+1; ram[i] = { `not, `s0, `P0 }; // s0~=s0 - invert
i=i+1; ram[i] = { `reg_w, `s1, `P0 }; // (s1)=s0, pop s0
i=i+1; ram[i] = { `jmp_inz, -6'd13, `s1 }; // loop forever
// loop end
*/
 
// "bouncing ball" 4 LED display w/ PWM
//
// s0 : sin
// s1 : cos
// s2 : alpha (attenuation factor = speed)
// s3 : rectified sin, val, one-hot(val)
// s4 :
// s5 : pwm counter
// s6 :
// s7 : i/o register address
i='h100; ram[i] = { `dat_is, 6'd0, `s0 }; // s0=0 (sin init)
i=i+1; ram[i] = { `lit_u, `__, `s1 }; // s1=0x3000,0000 (cos init)
i=i+1; ram[i] = 16'h3000 ; //
i=i+1; ram[i] = { `shl_is, 6'd16, `P1 }; //
i=i+1; ram[i] = { `lit_u, `__, `s2 }; // s2=0x3000 (alpha init)
i=i+1; ram[i] = 16'h3000 ; //
i=i+1; ram[i] = { `dat_is, 6'd0, `s5 }; // s5=0 (pwm init)
i=i+1; ram[i] = { `dat_is, `IO_LO, `s7 }; // s7=reg addr
// loop start
// sin & cos
i=i+1; ram[i] = { `mul_xs, `s2, `s0 }; // s0=s0*s2 (sin*alpha)
i=i+1; ram[i] = { `sub, `P0, `P1 }; // s1-=s0 (cos-=sin*alpha)
i=i+1; ram[i] = { `mul_xs, `s2, `s1 }; // s1=s1*s2 (cos*alpha)
i=i+1; ram[i] = { `add, `P1, `P0 }; // s0-=s1 (sin+=cos*alpha)
// |sin|
i=i+1; ram[i] = { `cpy, `s0, `s3 }; // s3=s0
i=i+1; ram[i] = { `jmp_inlz, 6'd1, `s3 }; // (s3!<0) ? jmp +1
i=i+1; ram[i] = { `not, `s3, `P3 }; // s3~=s3
// decimal( |sin| ) + pwm to update, + pwm to get ofl
i=i+1; ram[i] = { `shl_is, 6'd4, `s3 }; // s3=s3<<4
i=i+1; ram[i] = { `add, `s3, `P5 }; // s5+=s3 (update pwm count)
i=i+1; ram[i] = { `add_xu, `P3, `s5 }; // s5=s5+s3, pop s3 (get pwm ofl)
// one-hot( int( |sin| ) + pwm ofl )
i=i+1; ram[i] = { `shl_is, -6'd28, `P3 }; // s3>>=28
i=i+1; ram[i] = { `add, `P5, `P3 }; // s3+=s5, pop s5 (add pwm ofl)
i=i+1; ram[i] = { `pow, `s3, `P3 }; // s3=1<<s3, pop s3 (one-hot)
// output
i=i+1; ram[i] = { `reg_w, `s7, `P3 }; // (s7)=s3, pop s3
i=i+1; ram[i] = { `jmp_inz, -6'd15, `s7 }; // loop forever
// loop end
end
/trunk/v04.05/boot_code/boot_code_sqrt.h
0,0 → 1,172
/*
--------------------------------------------------------------------------------
 
Module : boot_code.h
 
--------------------------------------------------------------------------------
 
Function:
- Boot code for a processor core.
 
Instantiates:
- Nothing.
 
Notes:
- For testing (@ core.v):
CLR_BASE = 'h0;
CLR_SPAN = 2; // gives 4 instructions
INTR_BASE = 'h20; // 'd32
INTR_SPAN = 2; // gives 4 instructions
 
 
--------------------------------------------------------------------------------
*/
 
/*
--------------------
-- external stuff --
--------------------
*/
`include "op_encode.h"
`include "reg_set_addr.h"
`include "boot_code_defs.h"
/*
----------------------------------------
-- initialize: fill with default data --
----------------------------------------
*/
integer i;
 
initial begin
 
/* // fill with nop (some compilers need this)
for ( i = 0; i < CAPACITY; i = i+1 ) begin
ram[i] = { `nop, `s0, `s0 };
end
*/
 
/*
---------------
-- boot code --
---------------
*/
 
 
/*
------------
-- TEST 0 --
------------
*/
 
// Square root
// Thread 0 : Get input 32 bit GPIO, calculate square root, output 32 bit GPIO.
// Other threads : do nothing, loop forever
 
///////////////
// clr space //
///////////////
 
i='h0; ram[i] = { `lit_u, `__, `s1 }; // s1=addr
i=i+1; ram[i] = 16'h0040 ; //
i=i+1; ram[i] = { `gto, `P1, `__ }; // goto, pop s1 (addr)
//
i='h04; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h08; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h0c; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h10; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h14; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h18; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h1c; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
 
////////////////
// intr space //
////////////////
 
///////////////////////
// code & data space //
///////////////////////
 
// read & write 32 bit GPIO data to & from s0
i='h40; ram[i] = { `lit_u, `__, `s3 }; // s3=addr
i=i+1; ram[i] = 16'h0080 ; //
i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
// do s0=sqrt(s0)
i=i+1; ram[i] = { `lit_u, `__, `s3 }; // s3=addr
i=i+1; ram[i] = 16'h0090 ; //
i=i+1; ram[i] = { `gsb, `P3, `s7 }; // gsb, pop s3 (addr)
// write s0 data to 32 bit GPIO
i=i+1; ram[i] = { `lit_u, `__, `s3 }; // s3=addr
i=i+1; ram[i] = 16'h0070 ; //
i=i+1; ram[i] = { `gsb, `P3, `s3 }; // gsb, pop s3 (addr)
// loop forever
i=i+1; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
 
 
// sub : read 32 bit GPIO => s0, return to (s3)
i='h60; ram[i] = { `dat_is, `IO_LO, `s1 }; // s1=reg addr
i=i+1; ram[i] = { `reg_rs, `P1, `s0 }; // s0=(s1), pop s1
i=i+1; ram[i] = { `dat_is, `IO_HI, `s1 }; // s1=reg addr
i=i+1; ram[i] = { `reg_rh, `P1, `P0 }; // s0=(s1), pop both
i=i+1; ram[i] = { `gto, `P3, `__ }; // return, pop s3
 
 
// sub : write s0 => 32 bit GPIO, return to (s3)
i='h70; ram[i] = { `dat_is, `IO_LO, `s1 }; // s1=reg addr
i=i+1; ram[i] = { `reg_w, `P1, `s0 }; // (s1)=s0, pop s1
i=i+1; ram[i] = { `dat_is, `IO_HI, `s1 }; // s1=reg addr
i=i+1; ram[i] = { `reg_wh, `P1, `s0 }; // (s1)=s0, pop s1
i=i+1; ram[i] = { `gto, `P3, `__ }; // return, pop s3
 
 
// sub : read & write 32 bit GPIO => s0, return to (s3)
i='h80; ram[i] = { `dat_is, `IO_LO, `s1 }; // s1=reg addr
i=i+1; ram[i] = { `reg_rs, `s1, `s0 }; // s0=(s1)
i=i+1; ram[i] = { `reg_w, `P1, `s0 }; // (s1)=s0, pop s1
i=i+1; ram[i] = { `dat_is, `IO_HI, `s1 }; // s1=reg addr
i=i+1; ram[i] = { `reg_rh, `s1, `P0 }; // s0=(s1), pop s0
i=i+1; ram[i] = { `reg_wh, `P1, `s0 }; // (s1)=s0, pop s1
i=i+1; ram[i] = { `gto, `P3, `__ }; // return, pop s3
 
 
// sub : s0=sqrt(s0), return to (s7)
//
// input is unsigned 32 integer
// output is unsigned 16.16 integer
//
// algorithm: binary search
// iterate 32 times
//
// s0 : input (x), output (Q)
// s1 : running q
// s2 : temp: q^2 + q
// s3 :
// s4 :
// s5 :
// s6 : one-hot (& loop test)
// s7 : sub return address
//
// loop setup
i='h90; ram[i] = { `dat_is, 6'd0, `s1 }; // s1=0 (init Q)
i=i+1; ram[i] = { `psu_i, 6'd31, `s6 }; // s6 MSB=1 (init OH)
// loop start
i=i+1; ram[i] = { `add, `s6, `P1 }; // s1+=s6
i=i+1; ram[i] = { `mul_xu, `s1, `s1 }; // s1=s1*s1 (square, integer portion)
// jump start
i=i+1; ram[i] = { `jmp_ilu, 4'd1, `s0, `P1 }; // (s1<s0) ? jump 1 pop s1 (skip restore)
i=i+1; ram[i] = { `sub, `s6, `P1 }; // s1-=s6 (restore)
// jump end
i=i+1; ram[i] = { `psu_i, -6'd1, `P6 }; // s6>>=1 (new OH)
i=i+1; ram[i] = { `jmp_inz, -6'd6, `s6 }; // (s6!=0) ? do again
// loop end
i=i+1; ram[i] = { `mul_xu, `s1, `s1 }; // s1=s1*s1 (square, integer portion)
i=i+1; ram[i] = { `sub, `P1, `P0 }; // s0-=s1, pop s1 : x -= q^2
i=i+1; ram[i] = { `add, `s1, `P0 }; // s0+=s1 : Q = q + x - q^2
i=i+1; ram[i] = { `mul, `s1, `s1 }; // s1=s1*s1 (square, decimal portion) : (q>>n)^2
i=i+1; ram[i] = { `cpy, `P1, `s2 }; // s2=s1, move
i=i+1; ram[i] = { `add_xu, `P1, `P2 }; // s2+=s1 (carry out, integer portion), pop s1 : int[q>>n + (q>>n)^2]
i=i+1; ram[i] = { `sub, `P2, `P0 }; // s0+=s2, pop s2 : Q = q + (x - q^2) - int[q>>n + (q>>n)^2]
i=i+1; ram[i] = { `gto, `P7, `P6 }; // return, pop s7 & s6
// end sub
 
end
/trunk/v04.05/boot_code/boot_code_v_branches.h
0,0 → 1,584
/*
--------------------------------------------------------------------------------
 
Module : boot_code.h
 
--------------------------------------------------------------------------------
 
Function:
- Boot code for a processor core.
 
Instantiates:
- Nothing.
 
Notes:
- For testing (@ core.v):
CLR_BASE = 'h0;
CLR_SPAN = 2; // gives 4 instructions
INTR_BASE = 'h20; // 'd32
INTR_SPAN = 2; // gives 4 instructions
 
 
--------------------------------------------------------------------------------
*/
 
/*
--------------------
-- external stuff --
--------------------
*/
`include "op_encode.h"
`include "reg_set_addr.h"
`include "boot_code_defs.h"
/*
----------------------------------------
-- initialize: fill with default data --
----------------------------------------
*/
integer i;
 
initial begin
 
/* // fill with nop (some compilers need this)
for ( i = 0; i < CAPACITY; i = i+1 ) begin
ram[i] = { `nop, `__, `__ };
end
*/
 
/*
---------------
-- boot code --
---------------
*/
 
 
// Thread 0 : test all jmp_i (A?B) instructions
// Thread 1 : test all jmp_i (A?0) instructions
// Thread 2 : test all jmp instructions
// Thread 3 : test all gto instructions
// Other threads : do nothing, loop forever
 
///////////////
// clr space //
///////////////
 
i='h0; ram[i] = { `lit_u, `__, `s1 }; // s1=addr
i=i+1; ram[i] = 16'h0200 ; //
i=i+1; ram[i] = { `gto, `P1, `__ }; // goto, pop s1 (addr)
//
i='h4; ram[i] = { `lit_u, `__, `s1 }; // s1=addr
i=i+1; ram[i] = 16'h0400 ; //
i=i+1; ram[i] = { `gto, `P1, `__ }; // goto, pop s1 (addr)
//
i='h8; ram[i] = { `lit_u, `__, `s1 }; // s1=addr
i=i+1; ram[i] = 16'h0500 ; //
i=i+1; ram[i] = { `gto, `P1, `__ }; // goto, pop s1 (addr)
//
i='hc; ram[i] = { `lit_u, `__, `s1 }; // s1=addr
i=i+1; ram[i] = 16'h0600 ; //
i=i+1; ram[i] = { `gto, `P1, `__ }; // goto, pop s1 (addr)
//
i='h10; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h14; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h18; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
i='h1c; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
 
 
////////////////
// intr space //
////////////////
 
 
///////////////////////
// code & data space //
///////////////////////
 
 
/////////////////
// subroutines //
/////////////////
 
 
// test all jmp_i (A?B) instructions, result in s0.
// Correct functioning is s0 = 'd58 ('h3A).
//
// s0 : 0 & final test result
// s1 : +1
// s2 : -2
// s3 : running test result
//
// setup test values and running test result:
i='h200; ram[i] = { `dat_is, 6'd0, `s0 }; // s0=0
i=i+1; ram[i] = { `dat_is, 6'd1, `s1 }; // s1=1
i=i+1; ram[i] = { `dat_is, -6'd2, `s2 }; // s2=-2
i=i+1; ram[i] = { `dat_is, 6'd0, `s3 }; // s3=0
//
// distance testing
//
i=i+1; ram[i] = { `jmp_ie, 4'd7, `s0, `s0 }; // jump forward
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // (+0,-9) s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // (+1,-8) s3++ (backward jump lands here)
i=i+1; ram[i] = { `jmp_ie, 4'd6, `s0, `s0 }; // (+2,-7) jump forward (and out)
// 3 don't cares here
i=i+4; ram[i] = { `add_is, -6'd1, `P3 }; // (+6,-3) s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // (+7,-2) s3++ (forward jump lands here)
i=i+1; ram[i] = { `jmp_ie, -4'd8, `s0, `s0 }; // (+8,-1) jump back
//
// (A?B) testing
//
// ie
i=i+1; ram[i] = { `jmp_ie, 4'd1, `s0, `s0 }; // (s0==s0) ? jump (YNN)
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `jmp_ie, 4'd1, `s0, `s1 }; // (s1==s0) ? jump
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
i=i+1; ram[i] = { `jmp_ie, 4'd1, `s0, `s2 }; // (s2==s0) ? jump
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
//
i=i+1; ram[i] = { `jmp_ie, 4'd1, `s1, `s0 }; // (s0==s1) ? jump (NYN)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
i=i+1; ram[i] = { `jmp_ie, 4'd1, `s1, `s1 }; // (s1==s1) ? jump
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `jmp_ie, 4'd1, `s1, `s2 }; // (s2==s1) ? jump
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
//
i=i+1; ram[i] = { `jmp_ie, 4'd1, `s2, `s0 }; // (s0==s2) ? jump (NNY)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
i=i+1; ram[i] = { `jmp_ie, 4'd1, `s2, `s1 }; // (s1==s2) ? jump
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
i=i+1; ram[i] = { `jmp_ie, 4'd1, `s2, `s2 }; // (s2==s2) ? jump
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// ine
i=i+1; ram[i] = { `jmp_ine, 4'd1, `s0, `s0 }; // (s0!=s0) ? jump (NYY)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
i=i+1; ram[i] = { `jmp_ine, 4'd1, `s0, `s1 }; // (s1!=s0) ? jump
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `jmp_ine, 4'd1, `s0, `s2 }; // (s2!=s0) ? jump
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
//
i=i+1; ram[i] = { `jmp_ine, 4'd1, `s1, `s0 }; // (s0!=s1) ? jump (YNY)
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `jmp_ine, 4'd1, `s1, `s1 }; // (s1!=s1) ? jump
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
i=i+1; ram[i] = { `jmp_ine, 4'd1, `s1, `s2 }; // (s2!=s1) ? jump
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
//
i=i+1; ram[i] = { `jmp_ine, 4'd1, `s2, `s0 }; // (s0!=s2) ? jump (YYN)
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `jmp_ine, 4'd1, `s2, `s1 }; // (s1!=s2) ? jump
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `jmp_ine, 4'd1, `s2, `s2 }; // (s2!=s2) ? jump
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
// ilu
i=i+1; ram[i] = { `jmp_ilu, 4'd1, `s0, `s0 }; // (s0<s0) ? jump (NNN)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
i=i+1; ram[i] = { `jmp_ilu, 4'd1, `s0, `s1 }; // (s1<s0) ? jump
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
i=i+1; ram[i] = { `jmp_ilu, 4'd1, `s0, `s2 }; // (s2<s0) ? jump
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
//
i=i+1; ram[i] = { `jmp_ilu, 4'd1, `s1, `s0 }; // (s0<s1) ? jump (YNN)
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `jmp_ilu, 4'd1, `s1, `s1 }; // (s1<s1) ? jump
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
i=i+1; ram[i] = { `jmp_ilu, 4'd1, `s1, `s2 }; // (s2<s1) ? jump
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
//
i=i+1; ram[i] = { `jmp_ilu, 4'd1, `s2, `s0 }; // (s0<s2) ? jump (YYN)
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `jmp_ilu, 4'd1, `s2, `s1 }; // (s1<s2) ? jump
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `jmp_ilu, 4'd1, `s2, `s2 }; // (s2<s2) ? jump
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
// inlu
i=i+1; ram[i] = { `jmp_inlu, 4'd1, `s0, `s0 }; // (s0>=s0) ? jump (YYY)
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `jmp_inlu, 4'd1, `s0, `s1 }; // (s1>=s0) ? jump
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `jmp_inlu, 4'd1, `s0, `s2 }; // (s2>=s0) ? jump
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
//
i=i+1; ram[i] = { `jmp_inlu, 4'd1, `s1, `s0 }; // (s0>=s1) ? jump (NYY)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
i=i+1; ram[i] = { `jmp_inlu, 4'd1, `s1, `s1 }; // (s1>=s1) ? jump
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `jmp_inlu, 4'd1, `s1, `s2 }; // (s2>=s1) ? jump
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
//
i=i+1; ram[i] = { `jmp_inlu, 4'd1, `s2, `s0 }; // (s0>=s2) ? jump (NNY)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
i=i+1; ram[i] = { `jmp_inlu, 4'd1, `s2, `s1 }; // (s1>=s2) ? jump
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
i=i+1; ram[i] = { `jmp_inlu, 4'd1, `s2, `s2 }; // (s2>=s2) ? jump
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// ils
i=i+1; ram[i] = { `jmp_ils, 4'd1, `s0, `s0 }; // (s0<s0) ? jump (NNY)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
i=i+1; ram[i] = { `jmp_ils, 4'd1, `s0, `s1 }; // (s1<s0) ? jump
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
i=i+1; ram[i] = { `jmp_ils, 4'd1, `s0, `s2 }; // (s2<s0) ? jump
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
//
i=i+1; ram[i] = { `jmp_ils, 4'd1, `s1, `s0 }; // (s0<s1) ? jump (YNY)
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `jmp_ils, 4'd1, `s1, `s1 }; // (s1<s1) ? jump
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
i=i+1; ram[i] = { `jmp_ils, 4'd1, `s1, `s2 }; // (s2<s1) ? jump
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
//
i=i+1; ram[i] = { `jmp_ils, 4'd1, `s2, `s0 }; // (s0<s2) ? jump (NNN)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
i=i+1; ram[i] = { `jmp_ils, 4'd1, `s2, `s1 }; // (s1<s2) ? jump
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
i=i+1; ram[i] = { `jmp_ils, 4'd1, `s2, `s2 }; // (s2<s2) ? jump
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
// inls
i=i+1; ram[i] = { `jmp_inls, 4'd1, `s0, `s0 }; // (s0>=s0) ? jump (YYN)
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `jmp_inls, 4'd1, `s0, `s1 }; // (s1>=s0) ? jump
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `jmp_inls, 4'd1, `s0, `s2 }; // (s2>=s0) ? jump
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
//
i=i+1; ram[i] = { `jmp_inls, 4'd1, `s1, `s0 }; // (s0>=s1) ? jump (NYN)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
i=i+1; ram[i] = { `jmp_inls, 4'd1, `s1, `s1 }; // (s1>=s1) ? jump
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `jmp_inls, 4'd1, `s1, `s2 }; // (s2>=s1) ? jump
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
//
i=i+1; ram[i] = { `jmp_inls, 4'd1, `s2, `s0 }; // (s0>=s2) ? jump (YYY)
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `jmp_inls, 4'd1, `s2, `s1 }; // (s1>=s2) ? jump
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `jmp_inls, 4'd1, `s2, `s2 }; // (s2>=s2) ? jump
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// cleanup
i=i+1; ram[i] = { `pop, 8'b00000111 }; // pop s0, s1, s2
// check for no opcode errors
i=i+1; ram[i] = { `lit_u, `__, `s7 }; // s7='h0900
i=i+1; ram[i] = 16'h0900 ; //
i=i+1; ram[i] = { `gsb, `P7, `s7 }; // gsb, pop s7 (addr)
i=i+1; ram[i] = { `jmp_iz, 6'd1, `P4 }; // (s4==0) ? skip, pop s4
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// check for no stack errors
i=i+1; ram[i] = { `lit_u, `__, `s7 }; // s7='h0910
i=i+1; ram[i] = 16'h0910 ; //
i=i+1; ram[i] = { `gsb, `P7, `s7 }; // gsb, pop s7 (addr)
i=i+1; ram[i] = { `jmp_iz, 6'd1, `P4 }; // (s4==0) ? skip, pop s4
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// copy result to s0
i=i+1; ram[i] = { `cpy, `P3, `s0 }; // s0=s3, pop s3
// loop forever
i=i+1; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
 
 
 
// test all jmp_i (A?0) instructions, result in s0.
// Correct functioning is s0 = 'd16 ('h10).
//
// s0 : 0 & final test result
// s1 : +1
// s2 : -2
// s3 : running test result
//
// setup test values and running test result:
i='h400; ram[i] = { `dat_is, 6'd0, `s0 }; // s0=0
i=i+1; ram[i] = { `dat_is, 6'd1, `s1 }; // s1=1
i=i+1; ram[i] = { `dat_is, -6'd2, `s2 }; // s2=-2
i=i+1; ram[i] = { `dat_is, 6'd0, `s3 }; // s3=0
//
// distance testing
//
i=i+1; ram[i] = { `jmp_iz, 6'd31, `s0 }; // jump forward
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // (+0,-33) s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // (+1,-32) s3++ (backward jump lands here)
i=i+1; ram[i] = { `jmp_iz, 6'd30, `s0 }; // (+2,-31) jump forward (and out)
// 27 don't cares here
i=i+28; ram[i] = { `add_is, -6'd1, `P3 }; // (+30,-3) s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // (+31,-2) s3++ (forward jump lands here)
i=i+1; ram[i] = { `jmp_iz, -6'd32, `s0 }; // jump back
//
// (A?0) testing
//
// z
i=i+1; ram[i] = { `jmp_iz, 6'd1, `s0 }; // (s0==0) ? jump (YNN)
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `jmp_iz, 6'd1, `s1 }; // (s1==0) ? jump
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
i=i+1; ram[i] = { `jmp_iz, 6'd1, `s2 }; // (s2==0) ? jump
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
// nz
i=i+1; ram[i] = { `jmp_inz, 6'd1, `s0 }; // (s0!=0) ? jump (NYY)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
i=i+1; ram[i] = { `jmp_inz, 6'd1, `s1 }; // (s1!=0) ? jump
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `jmp_inz, 6'd1, `s2 }; // (s2!=0) ? jump
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// lz
i=i+1; ram[i] = { `jmp_ilz, 6'd1, `s0 }; // (s0<0) ? jump (NNY)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
i=i+1; ram[i] = { `jmp_ilz, 6'd1, `s1 }; // (s1<0) ? jump
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
i=i+1; ram[i] = { `jmp_ilz, 6'd1, `s2 }; // (s2<0) ? jump
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// nlz
i=i+1; ram[i] = { `jmp_inlz, 6'd1, `s0 }; // (s0>=0) ? jump (YYN)
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `jmp_inlz, 6'd1, `s1 }; // (s1>=0) ? jump
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `jmp_inlz, 6'd1, `s2 }; // (s2>=0) ? jump
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
// cleanup
i=i+1; ram[i] = { `pop, 8'b00000111 }; // pop s0, s1, s2
// check for no opcode errors
i=i+1; ram[i] = { `lit_u, `__, `s7 }; // s7='h0900
i=i+1; ram[i] = 16'h0900 ; //
i=i+1; ram[i] = { `gsb, `P7, `s7 }; // gsb, pop s7 (addr)
i=i+1; ram[i] = { `jmp_iz, 6'd1, `P4 }; // (s4==0) ? skip, pop s4
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// check for no stack errors
i=i+1; ram[i] = { `lit_u, `__, `s7 }; // s7='h0910
i=i+1; ram[i] = 16'h0910 ; //
i=i+1; ram[i] = { `gsb, `P7, `s7 }; // gsb, pop s7 (addr)
i=i+1; ram[i] = { `jmp_iz, 6'd1, `P4 }; // (s4==0) ? skip, pop s4
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// copy result to s0
i=i+1; ram[i] = { `cpy, `P3, `s0 }; // s0=s3, pop s3
// loop forever
i=i+1; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
 
 
// test all jmp instructions, result in s0.
// Correct functioning is s0 = 'd19 ('h13).
//
// s0 : 0 & final test result
// s1 : +1
// s2 : -2
// s3 : running test result
//
// setup test values and running test result:
i='h500; ram[i] = { `dat_is, 6'd0, `s0 }; // s0=0
i=i+1; ram[i] = { `dat_is, 6'd1, `s1 }; // s1=1
i=i+1; ram[i] = { `dat_is, -6'd2, `s2 }; // s2=-2
i=i+1; ram[i] = { `dat_is, 6'd0, `s3 }; // s3=0
//
// distance testing
//
i=i+1; ram[i] = { `dat_is, 6'd30, `s0 }; // s0=30
i=i+1; ram[i] = { `dat_is, -6'd32, `s0 }; // s0=-32
i=i+1; ram[i] = { `dat_is, 6'd31, `s0 }; // s0=31
i=i+1; ram[i] = { `jmp, `P0, `__ }; // jump forward 31, pop s0
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // (+0,-33) s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // (+1,-32) s3++ (backward jump lands here)
i=i+1; ram[i] = { `jmp, `P0, `s0 }; // (+2,-31) jump forward 30 (and out)
// 27 don't cares here
i=i+28; ram[i] = { `add_is, -6'd1, `P3 }; // (+30,-3) s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // (+31,-2) s3++ (forward jump lands here)
i=i+1; ram[i] = { `jmp, `P0, `__ }; // jump back -32, pop s1
//
// unconditional testing
//
i=i+1; ram[i] = { `jmp, `s1, `s0 }; // jump (s0?0)
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `jmp, `s1, `s1 }; // jump (s1?0)
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `jmp, `s1, `s2 }; // jump (s2?0)
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
//
// (A?0) testing
// z
i=i+1; ram[i] = { `jmp_z, `s1, `s0 }; // (s0==0) ? jump (YNN)
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `jmp_z, `s1, `s1 }; // (s1==0) ? jump
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
i=i+1; ram[i] = { `jmp_z, `s1, `s2 }; // (s2==0) ? jump
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
// nz
i=i+1; ram[i] = { `jmp_nz, `s1, `s0 }; // (s0!=0) ? jump (NYY)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
i=i+1; ram[i] = { `jmp_nz, `s1, `s1 }; // (s1!=0) ? jump
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `jmp_nz, `s1, `s2 }; // (s2!=0) ? jump
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// lz
i=i+1; ram[i] = { `jmp_lz, `s1, `s0 }; // (s0<0) ? jump (NNY)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
i=i+1; ram[i] = { `jmp_lz, `s1, `s1 }; // (s1<0) ? jump
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
i=i+1; ram[i] = { `jmp_lz, `s1, `s2 }; // (s2<0) ? jump
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// nlz
i=i+1; ram[i] = { `jmp_nlz, `s1, `s0 }; // (s0>=0) ? jump (YYN)
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `jmp_nlz, `s1, `s1 }; // (s1>=0) ? jump
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `jmp_nlz, `s1, `s2 }; // (s2>=0) ? jump
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++ (N)
// cleanup
i=i+1; ram[i] = { `pop, 8'b00000111 }; // pop s0, s1, s2
// check for no opcode errors
i=i+1; ram[i] = { `lit_u, `__, `s7 }; // s7='h0900
i=i+1; ram[i] = 16'h0900 ; //
i=i+1; ram[i] = { `gsb, `P7, `s7 }; // gsb, pop s7 (addr)
i=i+1; ram[i] = { `jmp_iz, 6'd1, `P4 }; // (s4==0) ? skip, pop s4
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// check for no stack errors
i=i+1; ram[i] = { `lit_u, `__, `s7 }; // s7='h0910
i=i+1; ram[i] = 16'h0910 ; //
i=i+1; ram[i] = { `gsb, `P7, `s7 }; // gsb, pop s7 (addr)
i=i+1; ram[i] = { `jmp_iz, 6'd1, `P4 }; // (s4==0) ? skip, pop s4
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// copy result to s0
i=i+1; ram[i] = { `cpy, `P3, `s0 }; // s0=s3, pop s3
// loop forever
i=i+1; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
 
 
// test all gto instructions, result in s0.
// Correct functioning is s0 = 'd7 ('h7).
//
// s0 : 0 & final test result
// s1 : PC
// s2 : -2
// s3 : running test result
//
// setup test values and running test result:
i='h600; ram[i] = { `dat_is, 6'd0, `s0 }; // s0=0
i=i+1; ram[i] = { `dat_is, -6'd2, `s2 }; // s2=-2
i=i+1; ram[i] = { `dat_is, 6'd0, `s3 }; // s3=0
//
// distance testing
//
i=i+1; ram[i] = { `pgc, `__, `s1 }; // s1=pc
i=i+1; ram[i] = { `add_is, 6'd6, `P1 }; // s1+=6
i=i+1; ram[i] = { `gto, `P1, `__ }; // go forward, pop s1
//
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `pgc, `__, `s1 }; // s1=pc
i=i+1; ram[i] = { `add_is, 6'd6, `P1 }; // s1+=6
i=i+1; ram[i] = { `gto, `P1, `__ }; // go forward, pop s1
//
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
i=i+1; ram[i] = { `pgc, `__, `s1 }; // pc => s1
i=i+1; ram[i] = { `add_is, -6'd6, `P1 }; // s1-=6
i=i+1; ram[i] = { `gto, `P1, `__ }; // go back, pop s1
//
// unconditional testing
//
i=i+1; ram[i] = { `pgc, `__, `s1 }; // s1=pc
i=i+1; ram[i] = { `add_is, 6'd3, `P1 }; // s1+=3
i=i+1; ram[i] = { `gto, `P1, `s0 }; // go, pop s1 (YYY)
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
//
i=i+1; ram[i] = { `pgc, `__, `s1 }; // s1=pc
i=i+1; ram[i] = { `add_is, 6'd3, `P1 }; // s1+=3
i=i+1; ram[i] = { `gto, `P1, `s1 }; // go, pop s1
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
//
i=i+1; ram[i] = { `pgc, `__, `s1 }; // s1=pc
i=i+1; ram[i] = { `add_is, 6'd3, `P1 }; // s1+=3
i=i+1; ram[i] = { `gto, `P1, `s2 }; // go, pop s1
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3-- (Y)
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// cleanup
i=i+1; ram[i] = { `pop, 8'b00000101 }; // pop s0, s2
// check for no opcode errors
i=i+1; ram[i] = { `lit_u, `__, `s7 }; // s7='h0900
i=i+1; ram[i] = 16'h0900 ; //
i=i+1; ram[i] = { `gsb, `P7, `s7 }; // gsb, pop s7 (addr)
i=i+1; ram[i] = { `jmp_iz, 6'd1, `P4 }; // (s4==0) ? skip, pop s4
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// check for no stack errors
i=i+1; ram[i] = { `lit_u, `__, `s7 }; // s7='h0910
i=i+1; ram[i] = 16'h0910 ; //
i=i+1; ram[i] = { `gsb, `P7, `s7 }; // gsb, pop s7 (addr)
i=i+1; ram[i] = { `jmp_iz, 6'd1, `P4 }; // (s4==0) ? skip, pop s4
i=i+1; ram[i] = { `add_is, -6'd1, `P3 }; // s3--
i=i+1; ram[i] = { `add_is, 6'd1, `P3 }; // s3++
// copy result to s0
i=i+1; ram[i] = { `cpy, `P3, `s0 }; // s0=s3, pop s3
// loop forever
i=i+1; ram[i] = { `jmp_ie, -4'd1, `s0, `s0 }; // loop forever
 
 
 
// sub : read & clear opcode errors for this thread => s4, return to (s7)
// avoid the use of s1!
i='h900; ram[i] = { `dat_is, `THRD_ID, `s6 }; // s6=reg addr
i=i+1; ram[i] = { `reg_rs, `P6, `s5 }; // s5=(s6), pop s6
i=i+1; ram[i] = { `pow, `P5, `s4 }; // s4=1<<s5, pop s5
i=i+1; ram[i] = { `dat_is, `OP_ER, `s6 }; // s6=reg addr
i=i+1; ram[i] = { `reg_rs, `s6, `s5 }; // s5=(s6)
i=i+1; ram[i] = { `and, `P5, `P4 }; // s4&=s5, pop s5
i=i+1; ram[i] = { `reg_w, `P6, `s4 }; // (s6)=s4, pop s6
i=i+1; ram[i] = { `gto, `P7, `__ }; // return to (s7), pop s7
 
 
// sub : read & clear stack errors for this thread => s4, return to (s7)
// avoid the use of s1!
i='h910; ram[i] = { `dat_is, `THRD_ID, `s6 }; // s6=reg addr
i=i+1; ram[i] = { `reg_rs, `P6, `s5 }; // s5=(s6), pop s6
i=i+1; ram[i] = { `pow, `P5, `s4 }; // s4=1<<s5, pop s5
i=i+1; ram[i] = { `cpy, `s4, `s5 }; // s5=s4
i=i+1; ram[i] = { `shl_is, 6'd8, `P5 }; // s5<<=8
i=i+1; ram[i] = { `orr, `P5, `P4 }; // s4|=s5, pop s5
i=i+1; ram[i] = { `dat_is, `STK_ER, `s6 }; // s6=reg addr
i=i+1; ram[i] = { `reg_rs, `s6, `s5 }; // s5=(s6)
i=i+1; ram[i] = { `and, `P5, `P4 }; // s4&=s5, pop s5
i=i+1; ram[i] = { `reg_w, `P6, `s4 }; // (s6)=s4, pop s6
i=i+1; ram[i] = { `gto, `P7, `__ }; // return to (s7), pop s7
 
 
end
/trunk/v04.05/reg_mem_shim.v
0,0 → 1,174
/*
--------------------------------------------------------------------------------
 
Module: reg_mem_shim.v
 
Function:
- Shim for internal register set and main memory r/w accesses.
 
Instantiates:
- (6x) pipe.v
 
Notes:
- I/O registered.
 
--------------------------------------------------------------------------------
*/
 
module reg_mem_shim
#(
parameter integer DATA_W = 32, // data width (bits)
parameter integer ADDR_W = 16, // address width (bits)
parameter integer IM_W = 8 // immediate width
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// control I/O
input wire hgh_i, // 1=high
input wire lit_i, // 1=literal data
//
input wire dm_wr_i, // 1=write
input wire rg_rd_i, // 1=read
input wire rg_wr_i, // 1=write
//
output wire dm_wr_o, // 1=write
output wire rg_rd_o, // 1=read
output wire rg_wr_o, // 1=write
// data I/O
input wire [DATA_W-1:0] a_data_i, // operand
output wire [DATA_W/2-1:0] wr_data_o, // write data
// address I/O
input wire [ADDR_W-1:0] b_addr_i, // b
input wire [IM_W-1:0] im_i, // immediate
input wire [ADDR_W-1:0] pc_1_i, // program counter
output wire [ADDR_W-1:0] rg_addr_o, // address
output wire [ADDR_W-1:0] dm_addr_o // address
);
 
 
/*
----------------------
-- internal signals --
----------------------
*/
wire hgh, lit, dm_wr, rg_rd, rg_wr;
wire [ADDR_W-1:0] b_addr, rg_addr, dm_addr;
wire [IM_W-1:0] im;
wire [DATA_W-1:0] a_data, wr_data;
 
 
 
/*
================
== code start ==
================
*/
 
 
// input ctrl regs
pipe
#(
.DEPTH ( 1 ),
.WIDTH ( 5 ),
.RESET_VAL ( 0 )
)
in_regs_ctrl
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { hgh_i, lit_i, dm_wr_i, rg_rd_i, rg_wr_i } ),
.data_o ( { hgh, lit, dm_wr, rg_rd, rg_wr } )
);
 
 
// input addr regs
pipe
#(
.DEPTH ( 1 ),
.WIDTH ( IM_W+ADDR_W ),
.RESET_VAL ( 0 )
)
in_regs_addr
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { im_i, b_addr_i } ),
.data_o ( { im, b_addr } )
);
 
 
// input data regs
pipe
#(
.DEPTH ( 1 ),
.WIDTH ( DATA_W ),
.RESET_VAL ( 0 )
)
in_regs_data
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( a_data_i ),
.data_o ( a_data )
);
 
 
// decode write data
assign wr_data = ( hgh ) ? a_data[DATA_W-1:DATA_W/2] : a_data[DATA_W/2-1:0];
 
// decode address
assign rg_addr = b_addr;
assign dm_addr = ( lit ) ? pc_1_i : b_addr + im;
 
 
// output ctrl regs
pipe
#(
.DEPTH ( 1 ),
.WIDTH ( 3 ),
.RESET_VAL ( 0 )
)
out_regs_ctrl
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { dm_wr, rg_rd, rg_wr } ),
.data_o ( { dm_wr_o, rg_rd_o, rg_wr_o } )
);
 
 
// output addr regs
pipe
#(
.DEPTH ( 1 ),
.WIDTH ( ADDR_W+ADDR_W ),
.RESET_VAL ( 0 )
)
out_regs_addr
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { rg_addr, dm_addr } ),
.data_o ( { rg_addr_o, dm_addr_o } )
);
 
 
// output data regs
pipe
#(
.DEPTH ( 1 ),
.WIDTH ( DATA_W/2 ),
.RESET_VAL ( 0 )
)
out_regs_data
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( wr_data ),
.data_o ( wr_data_o )
);
 
 
endmodule
/trunk/v04.05/ep4ce6e22c8_demo_board.cdf
0,0 → 1,13
/* Quartus II Version 10.1 Build 197 01/19/2011 Service Pack 1 SJ Web Edition */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
 
P ActionCode(Cfg)
Device PartName(EP4CE6) Path("F:/Docs/Eric/VERILOG/THRASH/HIVE88/") File("output_file.jic") MfrSpec(OpMask(1) SEC_Device(EPCS16) Child_OpMask(1 3));
 
ChainEnd;
 
AlteraBegin;
ChainType(JTAG);
AlteraEnd;
/trunk/v04.05/hive_core.vwf
0,0 → 1,2807
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
 
/*
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
 
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 150000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 50.0;
GRID_DUTY_CYCLE = 50;
}
 
SIGNAL("clk_i")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("intr_req_i")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 8;
LSB_INDEX = 0;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("intr_req_i[7]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "intr_req_i";
}
 
SIGNAL("intr_req_i[6]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "intr_req_i";
}
 
SIGNAL("intr_req_i[5]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "intr_req_i";
}
 
SIGNAL("intr_req_i[4]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "intr_req_i";
}
 
SIGNAL("intr_req_i[3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "intr_req_i";
}
 
SIGNAL("intr_req_i[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "intr_req_i";
}
 
SIGNAL("intr_req_i[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "intr_req_i";
}
 
SIGNAL("intr_req_i[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "intr_req_i";
}
 
SIGNAL("io_i")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 32;
LSB_INDEX = 0;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("io_i[31]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[30]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[29]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[28]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[27]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[26]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[25]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[24]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[23]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[22]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[21]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[20]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[19]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[18]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[17]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[16]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[15]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[14]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[13]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[12]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[11]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[10]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[9]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[8]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[7]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[6]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[5]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[4]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_i[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "io_i";
}
 
SIGNAL("io_o")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = BUS;
WIDTH = 32;
LSB_INDEX = 0;
DIRECTION = OUTPUT;
PARENT = "";
}
 
SIGNAL("io_o[31]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[30]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[29]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[28]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[27]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[26]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[25]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[24]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[23]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[22]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[21]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[20]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[19]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[18]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[17]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[16]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[15]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[14]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[13]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[12]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[11]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[10]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[9]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[8]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[7]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[6]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[5]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[4]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[3]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[2]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[1]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("io_o[0]")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "io_o";
}
 
SIGNAL("rst_i")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("divider 681")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("divider 477")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("divider 1788")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("divider 2870")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
 
GROUP("io_o_char")
{
MEMBERS = "io_o[31]", "io_o[30]", "io_o[29]", "io_o[28]", "io_o[27]";
}
 
GROUP("io_o_mant")
{
MEMBERS = "io_o[26]", "io_o[25]", "io_o[24]", "io_o[23]", "io_o[22]", "io_o[21]", "io_o[20]", "io_o[19]", "io_o[18]", "io_o[17]", "io_o[16]", "io_o[15]", "io_o[14]", "io_o[13]", "io_o[12]", "io_o[11]", "io_o[10]", "io_o[9]", "io_o[8]", "io_o[7]", "io_o[6]", "io_o[5]", "io_o[4]", "io_o[3]", "io_o[2]", "io_o[1]", "io_o[0]";
}
 
SIGNAL("uart_rx_i")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
 
SIGNAL("uart_tx_o")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
 
SIGNAL("divider 2733")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
 
TRANSITION_LIST("clk_i")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 3000;
LEVEL 0 FOR 25.0;
LEVEL 1 FOR 25.0;
}
}
}
 
TRANSITION_LIST("intr_req_i[7]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 12800.0;
LEVEL 1 FOR 49600.0;
LEVEL 0 FOR 25600.0;
LEVEL 1 FOR 1600.0;
LEVEL 0 FOR 60400.0;
}
}
 
TRANSITION_LIST("intr_req_i[6]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 38400.0;
LEVEL 1 FOR 24000.0;
LEVEL 0 FOR 22400.0;
LEVEL 1 FOR 1600.0;
LEVEL 0 FOR 63600.0;
}
}
 
TRANSITION_LIST("intr_req_i[5]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 57600.0;
LEVEL 1 FOR 4800.0;
LEVEL 0 FOR 19200.0;
LEVEL 1 FOR 1600.0;
LEVEL 0 FOR 66800.0;
}
}
 
TRANSITION_LIST("intr_req_i[4]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 51200.0;
LEVEL 1 FOR 11200.0;
LEVEL 0 FOR 16000.0;
LEVEL 1 FOR 1600.0;
LEVEL 0 FOR 70000.0;
}
}
 
TRANSITION_LIST("intr_req_i[3]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 25600.0;
LEVEL 1 FOR 36800.0;
LEVEL 0 FOR 12800.0;
LEVEL 1 FOR 1600.0;
LEVEL 0 FOR 73200.0;
}
}
 
TRANSITION_LIST("intr_req_i[2]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 32000.0;
LEVEL 1 FOR 30400.0;
LEVEL 0 FOR 9600.0;
LEVEL 1 FOR 1600.0;
LEVEL 0 FOR 76400.0;
}
}
 
TRANSITION_LIST("intr_req_i[1]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 44800.0;
LEVEL 1 FOR 17600.0;
LEVEL 0 FOR 6400.0;
LEVEL 1 FOR 1600.0;
LEVEL 0 FOR 79600.0;
}
}
 
TRANSITION_LIST("intr_req_i[0]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 19200.0;
LEVEL 1 FOR 43200.0;
LEVEL 0 FOR 3200.0;
LEVEL 1 FOR 1600.0;
LEVEL 0 FOR 82800.0;
}
}
 
TRANSITION_LIST("io_i[31]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 4800.0;
LEVEL 0 FOR 145200.0;
}
}
 
TRANSITION_LIST("io_i[30]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 4800.0;
LEVEL 0 FOR 145200.0;
}
}
 
TRANSITION_LIST("io_i[29]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 150000.0;
}
}
 
TRANSITION_LIST("io_i[28]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 4800.0;
LEVEL 0 FOR 145200.0;
}
}
 
TRANSITION_LIST("io_i[27]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 150000.0;
}
}
 
TRANSITION_LIST("io_i[26]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 150000.0;
}
}
 
TRANSITION_LIST("io_i[25]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 150000.0;
}
}
 
TRANSITION_LIST("io_i[24]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 150000.0;
}
}
 
TRANSITION_LIST("io_i[23]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 4800.0;
LEVEL 0 FOR 145200.0;
}
}
 
TRANSITION_LIST("io_i[22]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 4800.0;
LEVEL 0 FOR 145200.0;
}
}
 
TRANSITION_LIST("io_i[21]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 150000.0;
}
}
 
TRANSITION_LIST("io_i[20]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 150000.0;
}
}
 
TRANSITION_LIST("io_i[19]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 4800.0;
LEVEL 0 FOR 145200.0;
}
}
 
TRANSITION_LIST("io_i[18]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 4800.0;
LEVEL 0 FOR 145200.0;
}
}
 
TRANSITION_LIST("io_i[17]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 150000.0;
}
}
 
TRANSITION_LIST("io_i[16]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 150000.0;
}
}
 
TRANSITION_LIST("io_i[15]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 4800.0;
LEVEL 0 FOR 145200.0;
}
}
 
TRANSITION_LIST("io_i[14]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 4800.0;
LEVEL 0 FOR 145200.0;
}
}
 
TRANSITION_LIST("io_i[13]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 150000.0;
}
}
 
TRANSITION_LIST("io_i[12]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 150000.0;
}
}
 
TRANSITION_LIST("io_i[11]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 4800.0;
LEVEL 0 FOR 145200.0;
}
}
 
TRANSITION_LIST("io_i[10]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 4800.0;
LEVEL 0 FOR 5000.0;
LEVEL 1 FOR 140200.0;
}
}
 
TRANSITION_LIST("io_i[9]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 150000.0;
}
}
 
TRANSITION_LIST("io_i[8]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 150000.0;
}
}
 
TRANSITION_LIST("io_i[7]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 4800.0;
LEVEL 0 FOR 145200.0;
}
}
 
TRANSITION_LIST("io_i[6]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 4800.0;
LEVEL 0 FOR 145200.0;
}
}
 
TRANSITION_LIST("io_i[5]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 150000.0;
}
}
 
TRANSITION_LIST("io_i[4]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 9800.0;
LEVEL 1 FOR 140200.0;
}
}
 
TRANSITION_LIST("io_i[3]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 150000.0;
}
}
 
TRANSITION_LIST("io_i[2]")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 4800.0;
LEVEL 0 FOR 5000.0;
LEVEL 1 FOR 140200.0;
}
}
 
TRANSITION_LIST("io_i[1]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 4800.0;
LEVEL 1 FOR 145200.0;
}
}
 
TRANSITION_LIST("io_i[0]")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 9800.0;
LEVEL 1 FOR 140200.0;
}
}
 
TRANSITION_LIST("io_o[31]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[30]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[29]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[28]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[27]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[26]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[25]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[24]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[23]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[22]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[21]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[20]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[19]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[18]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[17]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[16]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[15]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[14]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[13]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[12]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[11]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[10]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[9]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[8]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[7]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[6]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[5]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[4]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[3]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[2]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[1]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("io_o[0]")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
TRANSITION_LIST("rst_i")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 50.0;
LEVEL 0 FOR 149950.0;
}
}
 
TRANSITION_LIST("uart_rx_i")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 150000.0;
}
}
 
TRANSITION_LIST("uart_tx_o")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 150000.0;
}
}
 
DISPLAY_LINE
{
CHANNEL = "rst_i";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
 
DISPLAY_LINE
{
CHANNEL = "clk_i";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
 
DISPLAY_LINE
{
CHANNEL = "divider 681";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 0;
IS_DIVIDER = ON;
}
 
DISPLAY_LINE
{
CHANNEL = "intr_req_i";
EXPAND_STATUS = EXPANDED;
RADIX = Unsigned;
TREE_INDEX = 3;
TREE_LEVEL = 0;
CHILDREN = 4, 5, 6, 7, 8, 9, 10, 11;
}
 
DISPLAY_LINE
{
CHANNEL = "intr_req_i[7]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 4;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "intr_req_i[6]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 5;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "intr_req_i[5]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 6;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "intr_req_i[4]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 7;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "intr_req_i[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 8;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "intr_req_i[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 9;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "intr_req_i[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 10;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "intr_req_i[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 11;
TREE_LEVEL = 1;
PARENT = 3;
}
 
DISPLAY_LINE
{
CHANNEL = "divider 477";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 12;
TREE_LEVEL = 0;
IS_DIVIDER = ON;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 13;
TREE_LEVEL = 0;
CHILDREN = 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[31]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 14;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[30]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 15;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[29]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 16;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[28]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 17;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[27]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 18;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[26]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 19;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[25]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 20;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[24]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 21;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[23]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 22;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[22]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 23;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[21]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 24;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[20]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 25;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[19]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 26;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[18]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 27;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[17]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 28;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[16]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 29;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[15]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 30;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[14]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 31;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[13]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 32;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[12]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 33;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[11]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 34;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[10]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 35;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[9]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 36;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[8]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 37;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[7]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 38;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[6]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 39;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[5]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 40;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[4]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 41;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 42;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 43;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 44;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "io_i[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 45;
TREE_LEVEL = 1;
PARENT = 13;
}
 
DISPLAY_LINE
{
CHANNEL = "divider 1788";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 46;
TREE_LEVEL = 0;
IS_DIVIDER = ON;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 47;
TREE_LEVEL = 0;
CHILDREN = 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[31]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 48;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[30]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 49;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[29]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 50;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[28]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 51;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[27]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 52;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[26]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 53;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[25]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 54;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[24]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 55;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[23]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 56;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[22]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 57;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[21]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 58;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[20]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 59;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[19]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 60;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[18]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 61;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[17]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 62;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[16]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 63;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[15]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 64;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[14]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 65;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[13]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 66;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[12]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 67;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[11]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 68;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[10]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 69;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[9]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 70;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[8]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 71;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[7]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 72;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[6]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 73;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[5]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 74;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[4]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 75;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 76;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 77;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 78;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 79;
TREE_LEVEL = 1;
PARENT = 47;
}
 
DISPLAY_LINE
{
CHANNEL = "divider 2870";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 80;
TREE_LEVEL = 0;
IS_DIVIDER = ON;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o_char";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 81;
TREE_LEVEL = 0;
CHILDREN = 82, 83, 84, 85, 86;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[31]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 82;
TREE_LEVEL = 1;
PARENT = 81;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[30]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 83;
TREE_LEVEL = 1;
PARENT = 81;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[29]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 84;
TREE_LEVEL = 1;
PARENT = 81;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[28]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 85;
TREE_LEVEL = 1;
PARENT = 81;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[27]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 86;
TREE_LEVEL = 1;
PARENT = 81;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o_mant";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 87;
TREE_LEVEL = 0;
CHILDREN = 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[26]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 88;
TREE_LEVEL = 1;
PARENT = 87;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[25]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 89;
TREE_LEVEL = 1;
PARENT = 87;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[24]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 90;
TREE_LEVEL = 1;
PARENT = 87;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[23]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 91;
TREE_LEVEL = 1;
PARENT = 87;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[22]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 92;
TREE_LEVEL = 1;
PARENT = 87;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[21]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 93;
TREE_LEVEL = 1;
PARENT = 87;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[20]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 94;
TREE_LEVEL = 1;
PARENT = 87;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[19]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 95;
TREE_LEVEL = 1;
PARENT = 87;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[18]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 96;
TREE_LEVEL = 1;
PARENT = 87;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[17]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 97;
TREE_LEVEL = 1;
PARENT = 87;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[16]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 98;
TREE_LEVEL = 1;
PARENT = 87;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[15]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 99;
TREE_LEVEL = 1;
PARENT = 87;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[14]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 100;
TREE_LEVEL = 1;
PARENT = 87;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[13]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 101;
TREE_LEVEL = 1;
PARENT = 87;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[12]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 102;
TREE_LEVEL = 1;
PARENT = 87;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[11]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 103;
TREE_LEVEL = 1;
PARENT = 87;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[10]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 104;
TREE_LEVEL = 1;
PARENT = 87;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[9]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 105;
TREE_LEVEL = 1;
PARENT = 87;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[8]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 106;
TREE_LEVEL = 1;
PARENT = 87;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[7]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 107;
TREE_LEVEL = 1;
PARENT = 87;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[6]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 108;
TREE_LEVEL = 1;
PARENT = 87;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[5]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 109;
TREE_LEVEL = 1;
PARENT = 87;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[4]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 110;
TREE_LEVEL = 1;
PARENT = 87;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[3]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 111;
TREE_LEVEL = 1;
PARENT = 87;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[2]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 112;
TREE_LEVEL = 1;
PARENT = 87;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[1]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 113;
TREE_LEVEL = 1;
PARENT = 87;
}
 
DISPLAY_LINE
{
CHANNEL = "io_o[0]";
EXPAND_STATUS = COLLAPSED;
RADIX = Unsigned;
TREE_INDEX = 114;
TREE_LEVEL = 1;
PARENT = 87;
}
 
DISPLAY_LINE
{
CHANNEL = "divider 2733";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 115;
TREE_LEVEL = 0;
IS_DIVIDER = ON;
}
 
DISPLAY_LINE
{
CHANNEL = "uart_rx_i";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 116;
TREE_LEVEL = 0;
}
 
DISPLAY_LINE
{
CHANNEL = "uart_tx_o";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 117;
TREE_LEVEL = 0;
}
 
TIME_BAR
{
TIME = 16850;
MASTER = TRUE;
}
;
/trunk/v04.05/alu_add_sub.v
0,0 → 1,165
/*
--------------------------------------------------------------------------------
 
Module : alu_add_sub.v
 
--------------------------------------------------------------------------------
 
Function:
- Add & subtract unit for a processor ALU.
 
Instantiates:
- (4x) pipe.v
 
Notes:
- IN/MID/OUT/FLG optionally registered.
 
--------------------------------------------------------------------------------
*/
 
module alu_add_sub
#(
parameter integer REGS_IN = 1, // in register option
parameter integer REGS_MID = 1, // mid register option
parameter integer REGS_OUT = 1, // out register option
parameter integer REGS_FLG = 1, // flag register option
parameter integer DATA_W = 3 // data width
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// control I/O
input wire sgn_i, // 1=signed
input wire ext_i, // 1=extended result
input wire sub_i, // 1=subtract; 0=add
// data I/O
input wire [DATA_W-1:0] a_i, // operand
input wire [DATA_W-1:0] b_i, // operand
output wire [DATA_W-1:0] result_o, // = ( a +/- b )
// flags
output wire flg_ne_o, // a != b
output wire flg_lt_o // a < b
);
 
/*
----------------------
-- internal signals --
----------------------
*/
localparam integer ZSX_W = DATA_W+1; // +1 extra bit
localparam integer ADD_SUB_W = DATA_W+2; // +2 extra bits
localparam integer DBL_W = DATA_W*2; // double width
//
wire sgn, sub, ext, sub_m, ext_m;
wire signed [DATA_W-1:0] a, b;
wire signed [ZSX_W-1:0] a_zsx, b_zsx;
wire signed [ADD_SUB_W-1:0] ab_add, ab_sub, ab_add_m, ab_sub_m;
reg signed [DBL_W-1:0] res_dbl;
reg signed [DATA_W-1:0] result;
wire flg_ne, flg_lt;
 
 
/*
================
== code start ==
================
*/
 
 
// optional input regs
pipe
#(
.DEPTH ( REGS_IN ),
.WIDTH ( 3+DATA_W+DATA_W ),
.RESET_VAL ( 0 )
)
in_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { sub_i, ext_i, sgn_i, b_i, a_i } ),
.data_o ( { sub, ext, sgn, b, a } )
);
 
// zero|sign extend results
assign a_zsx = { ( sgn & a[DATA_W-1] ), a };
assign b_zsx = { ( sgn & b[DATA_W-1] ), b };
 
// arithmetic results (signed)
assign ab_add = a_zsx + b_zsx;
assign ab_sub = a_zsx - b_zsx;
// flags
assign flg_ne = ( a != b );
assign flg_lt = ab_sub[ZSX_W-1];
 
 
// optional flag regs
pipe
#(
.DEPTH ( REGS_FLG ),
.WIDTH ( 2 ),
.RESET_VAL ( 0 )
)
regs_flags
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { flg_ne, flg_lt } ),
.data_o ( { flg_ne_o, flg_lt_o } )
);
 
 
// optional mid regs
pipe
#(
.DEPTH ( REGS_MID ),
.WIDTH ( 2+ADD_SUB_W+ADD_SUB_W ),
.RESET_VAL ( 0 )
)
mid_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( { sub, ext, ab_sub, ab_add } ),
.data_o ( { sub_m, ext_m, ab_sub_m, ab_add_m } )
);
 
 
// multiplex
always @ ( * ) begin
case ( sub_m )
'b1 : res_dbl <= ab_sub_m;
default : res_dbl <= ab_add_m;
endcase
end
 
// multiplex & extend
always @ ( * ) begin
case ( ext_m )
'b1 : result <= res_dbl[DBL_W-1:DATA_W];
default : result <= res_dbl[DATA_W-1:0];
endcase
end
 
 
// optional output regs
pipe
#(
.DEPTH ( REGS_OUT ),
.WIDTH ( DATA_W ),
.RESET_VAL ( 0 )
)
out_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( result ),
.data_o ( result_o )
);
 
 
endmodule
/trunk/v04.05/hive_core.v
0,0 → 1,397
/*
--------------------------------------------------------------------------------
 
Module : hive_core.v
 
--------------------------------------------------------------------------------
 
Function:
- General purpose barrel processor FPGA core with:
- 8 threads & 8 stage pipeline
- 8 simple stacks per thread
- 32 bit data
- 16 bit opcode
- 16 bit address
 
Instantiates (at this level):
- control_ring.v
- data_ring.v
- reg_set.v
- reg_mem_shim.v
- dp_ram_infer.v
 
--------------------
- Revision History -
--------------------
 
v04.05 - 2014-01-02
- Note main version jump.
- Branched design back into main line.
- OP_CODE_W is now MEM_DATA_W.
 
v01.04 - 2014-01-01
- Moved register set and main memory data port one pipeline stage later.
- op_pow is back and is now sign neutral.
- Op renaming: psh_iu => psu_i.
- `_0, `_1, etc. is now `s* in all boot code.
- Added header blocking statements to some *.h files (didn't work for all).
- Use of real rather than integer types in UART calculations for clarity.
- EP3C5E144C: 2662 LEs, 198MHz (w/o DSE, synthesis optimized for speed).
- Passes all boot code verification & functional tests.
 
v01.03 - 2013-12-23
- Short 4 bit (+7/-8) immediate (A?B) jumps have replaced all following jumps.
- Removed unconditional immediate jump (use op_jmp_ie).
- Immediate (A?0) jumps, data, and add IM value reduced to 6 bits.
- Removed op_pow_i, op_shl_iu is op_psh_iu: combo pow2 and right shift,
op_shl_u is strictly unsigned shift.
- UART added to register set.
- Op renaming:
dat_f* => lit_*
shl_iu => psh_iu
- Small changes to register set base component parameters & I/O.
- Opcode encode/decode now over full opcode width.
- EP3C5E144C: 2650 LEs, 189MHz (w/o DSE).
- Passes all boot code verification & functional tests.
 
v01.02 - 2013-12-06
- Following jumps (jmp_f) have replaced all skips.
- Added op_pow & op_pow_i opcodes.
- A odd testing removed (lack of opcode space).
- op_pop now covers all stacks at once via {pb, sb, pa, sa} binary field.
- op_reg_r now signed, added read and write high register ops (_wh is ~free).
- Added op_lit_u to accomodate 16 bit addresses & such.
- Op renaming:
lit => dat_f
byt => dat_i
*_sx => *_xs
*_ux => *_xu
- Moved PC interrupt & jmp_f address loads to stage 4 of PC pipe.
- op_dat_fh now uses A as source of low data rather than B,
which is more consistent and allows unrelated pop.
- Register set addresses now defined as 8 bits wide.
- EP3C5E144C: ~2500 LEs, 185MHz (w/o DSE).
- Passes all boot code verification tests.
- Passes boot code functional tests: divide, sqrt, log2, exp2.
 
v01.01 - 2013-11-19
- Born. Based on Hive v3.10. Has 8 stacks per thread.
- Skips are back for A odd and (A?B) testing.
- Removed op_cls as it seems too dangerous. May put back in register set.
- Lots of op renaming:
dat_f => lit
dat_i => byt
or_br => bro, etc.
or => orr
pc => pgc (to make all op bases 3 letters)
- Reg access now unsigned low with no immediate offset.
- Added register to flag decode output, moved all PC changes to stage 3.
- EP3C5E144C: ~2400 LEs, 178MHz (w/o DSE).
- BROKEN: reg_mem_shim.v has bad decoding for dmem addr.
 
--------------------------------------------------------------------------------
*/
 
module hive_core
#(
parameter integer CLK_HZ = 160000000, // master clk_i rate (Hz)
parameter integer DATA_W = 32, // data width
parameter integer THREADS = 8, // threads (don't change!)
parameter [DATA_W/4-1:0] VER_MAJ = 'h04, // core version
parameter [DATA_W/4-1:0] VER_MIN = 'h05 // core version
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
//
input wire [THREADS-1:0] intr_req_i, // event request, active high
//
input wire [DATA_W-1:0] io_i, // gpio
output wire [DATA_W-1:0] io_o,
//
input wire uart_rx_i, // serial data
output wire uart_tx_o // serial data
);
 
/*
----------------------
-- internal signals --
----------------------
*/
`include "functions.h" // for clog2()
//
localparam integer ADDR_W = DATA_W/2; // address width
localparam integer PNTR_W = 5; // stack pointer width
localparam integer MEM_ADDR_W = 13; // main memory address width
localparam integer MEM_DATA_W = DATA_W/2; // main memory data width
localparam [ADDR_W-1:0] CLR_BASE = 'h0; // clear address base (concat)
localparam integer CLR_SPAN = 2; // clear address span (2^n)
localparam [ADDR_W-1:0] INTR_BASE = 'h20; // interrupt address base (concat)
localparam integer INTR_SPAN = 2; // interrupt address span (2^n)
localparam integer THRD_W = clog2( THREADS );
localparam integer STACKS = 8; // number of stacks
localparam integer STK_W = clog2( STACKS );
localparam integer IM_W = 6; // immediate width
localparam integer LG_SEL_W = 4;
localparam integer REG_ADDR_W = 4;
localparam integer DM_OFFS_W = 4;
localparam integer PROT_POP = 1; // 1=error protection, 0=none
localparam integer PROT_PUSH = 1; // 1=error protection, 0=none
localparam integer UART_DATA_W = 8; // uart data width (bits)
localparam integer UART_BAUD_RATE = 115200; // uart baud rate (Hz)
//
wire [THREADS-1:0] clr_req;
wire [THREADS-1:0] intr_en;
wire [MEM_DATA_W-1:0] op_code;
wire op_code_er;
wire [STK_W-1:0] data_sel_a, data_sel_b, addr_sel_b;
wire imda;
wire imad;
wire sgn, ext, hgh;
wire lg;
wire [LG_SEL_W-1:0] lg_sel;
wire add, sub, mul, shl, pow, rtn;
wire stk_clr;
wire [STACKS-1:0] pop, push, pop_er_2, push_er_3;
wire [DATA_W-1:0] a_data;
wire [ADDR_W-1:0] b_addr;
wire [IM_W-1:0] im;
wire flg_od_2, flg_nz_2, flg_lz_2, flg_ne_2, flg_lt_2;
wire [THRD_W-1:0] thrd_0, thrd_2, thrd_3, thrd_6;
wire [ADDR_W-1:0] pc_1, pc_3, pc_4;
wire [MEM_DATA_W-1:0] dm_rd_data_4, rg_rd_data_4;
wire [MEM_DATA_W-1:0] wr_data_2;
wire [ADDR_W-1:0] dm_addr_2, rg_addr_2;
wire dm_rd, dm_wr, rg_rd, rg_wr;
wire dm_wr_2, rg_rd_2, rg_wr_2;
wire lit;
 
 
/*
================
== code start ==
================
*/
 
 
// the control ring
control_ring
#(
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W ),
.THREADS ( THREADS ),
.THRD_W ( THRD_W ),
.STACKS ( STACKS ),
.STK_W ( STK_W ),
.IM_W ( IM_W ),
.MEM_DATA_W ( MEM_DATA_W ),
.LG_SEL_W ( LG_SEL_W ),
.CLR_BASE ( CLR_BASE ),
.CLR_SPAN ( CLR_SPAN ),
.INTR_BASE ( INTR_BASE ),
.INTR_SPAN ( INTR_SPAN )
)
control_ring
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.clr_req_i ( clr_req ),
.clr_ack_o ( ), // unused
.intr_en_i ( intr_en ),
.intr_req_i ( intr_req_i ),
.intr_ack_o ( ), // unused
.op_code_i ( op_code ),
.op_code_er_o ( op_code_er ),
.b_addr_i ( b_addr ),
.im_o ( im ),
.data_sel_a_o ( data_sel_a ),
.data_sel_b_o ( data_sel_b ),
.addr_sel_b_o ( addr_sel_b ),
.imda_o ( imda ),
.imad_o ( imad ),
.sgn_o ( sgn ),
.hgh_o ( hgh ),
.ext_o ( ext ),
.lg_sel_o ( lg_sel ),
.add_o ( add ),
.sub_o ( sub ),
.mul_o ( mul ),
.shl_o ( shl ),
.pow_o ( pow ),
.rtn_o ( rtn ),
.lit_o ( lit ),
.dm_rd_o ( dm_rd ),
.dm_wr_o ( dm_wr ),
.rg_rd_o ( rg_rd ),
.rg_wr_o ( rg_wr ),
.stk_clr_o ( stk_clr ),
.pop_o ( pop ),
.push_o ( push ),
.flg_nz_2_i ( flg_nz_2 ),
.flg_lz_2_i ( flg_lz_2 ),
.flg_ne_2_i ( flg_ne_2 ),
.flg_lt_2_i ( flg_lt_2 ),
.thrd_0_o ( thrd_0 ),
.thrd_2_o ( thrd_2 ),
.thrd_3_o ( thrd_3 ),
.thrd_6_o ( thrd_6 ),
.pc_1_o ( pc_1 ),
.pc_3_o ( pc_3 ),
.pc_4_o ( pc_4 )
);
 
 
// the data ring
data_ring
#(
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W ),
.THREADS ( THREADS ),
.THRD_W ( THRD_W ),
.STACKS ( STACKS ),
.STK_W ( STK_W ),
.PNTR_W ( PNTR_W ),
.IM_W ( IM_W ),
.LG_SEL_W ( LG_SEL_W ),
.PROT_POP ( PROT_POP ),
.PROT_PUSH ( PROT_PUSH )
)
data_ring
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_sel_a_i ( data_sel_a ),
.data_sel_b_i ( data_sel_b ),
.addr_sel_b_i ( addr_sel_b ),
.imda_i ( imda ),
.imad_i ( imad ),
.sgn_i ( sgn ),
.ext_i ( ext ),
.hgh_i ( hgh ),
.lg_sel_i ( lg_sel ),
.add_i ( add ),
.sub_i ( sub ),
.mul_i ( mul ),
.shl_i ( shl ),
.pow_i ( pow ),
.rtn_i ( rtn ),
.dm_rd_i ( dm_rd ),
.rg_rd_i ( rg_rd ),
.stk_clr_i ( stk_clr ),
.pop_i ( pop ),
.push_i ( push ),
.thrd_6_i ( thrd_6 ),
.im_i ( im ),
.dm_rd_data_4_i ( dm_rd_data_4 ),
.rg_rd_data_4_i ( rg_rd_data_4 ),
.pc_3_i ( pc_3 ),
.a_data_o ( a_data ),
.b_addr_o ( b_addr ),
.flg_nz_2_o ( flg_nz_2 ),
.flg_lz_2_o ( flg_lz_2 ),
.flg_ne_2_o ( flg_ne_2 ),
.flg_lt_2_o ( flg_lt_2 ),
.pop_er_2_o ( pop_er_2 ),
.push_er_3_o ( push_er_3 )
);
 
 
// shim for memory and register set access
reg_mem_shim
#(
.DATA_W ( DATA_W ),
.ADDR_W ( ADDR_W ),
.IM_W ( DM_OFFS_W )
)
reg_mem_shim
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.hgh_i ( hgh ),
.lit_i ( lit ),
.dm_wr_i ( dm_wr ),
.rg_rd_i ( rg_rd ),
.rg_wr_i ( rg_wr ),
.dm_wr_o ( dm_wr_2 ),
.rg_rd_o ( rg_rd_2 ),
.rg_wr_o ( rg_wr_2 ),
.a_data_i ( a_data ),
.wr_data_o ( wr_data_2 ),
.b_addr_i ( b_addr ),
.im_i ( im[DM_OFFS_W-1:0] ),
.pc_1_i ( pc_1 ),
.rg_addr_o ( rg_addr_2 ),
.dm_addr_o ( dm_addr_2 )
);
 
 
// internal register set
reg_set
#(
.REGS_IN ( 1 ),
.REGS_OUT ( 1 ),
.DATA_W ( DATA_W/2 ),
.ADDR_W ( REG_ADDR_W ),
.THREADS ( THREADS ),
.THRD_W ( THRD_W ),
.STACKS ( STACKS ),
.STK_W ( STK_W ),
.VER_MAJ ( VER_MAJ ),
.VER_MIN ( VER_MIN ),
.UART_DATA_W ( UART_DATA_W ),
.CLK_HZ ( CLK_HZ ),
.UART_BAUD_RATE ( UART_BAUD_RATE )
)
reg_set
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.addr_i ( rg_addr_2[REG_ADDR_W-1:0] ),
.wr_i ( rg_wr_2 ),
.rd_i ( rg_rd_2 ),
.data_i ( wr_data_2 ),
.data_o ( rg_rd_data_4 ),
.clr_req_o ( clr_req ),
.intr_en_o ( intr_en ),
.thrd_0_i ( thrd_0 ),
.op_code_er_i ( op_code_er ),
.thrd_2_i ( thrd_2 ),
.pop_er_2_i ( pop_er_2 ),
.thrd_3_i ( thrd_3 ),
.push_er_3_i ( push_er_3 ),
.io_lo_i ( io_i[DATA_W/2-1:0] ),
.io_hi_i ( io_i[DATA_W-1:DATA_W/2] ),
.io_lo_o ( io_o[DATA_W/2-1:0] ),
.io_hi_o ( io_o[DATA_W-1:DATA_W/2] ),
.uart_rx_i ( uart_rx_i ),
.uart_tx_o ( uart_tx_o )
);
 
 
// instruction and data memory
dp_ram_infer
#(
.REG_A_OUT ( 1 ),
.REG_B_OUT ( 1 ),
.DATA_W ( MEM_DATA_W ),
.ADDR_W ( MEM_ADDR_W ),
.MODE ( "RAW" ) // functional don't care
)
main_mem
(
.a_clk_i ( clk_i ),
.a_addr_i ( dm_addr_2 ),
.a_wr_i ( dm_wr_2 ),
.a_data_i ( wr_data_2 ),
.a_data_o ( dm_rd_data_4 ),
.b_clk_i ( clk_i ),
.b_addr_i ( pc_4 ),
.b_wr_i ( 1'b0 ), // unused
.b_data_i ( ), // unused
.b_data_o ( op_code )
);
 
 
endmodule
/trunk/v04.05/event_ctrl.v
0,0 → 1,114
/*
--------------------------------------------------------------------------------
 
Module: event_ctrl.v
 
Function:
- Event (clear & interrupt) controller for multi-threaded processor.
 
Instantiates:
- (1x) pipe.v
 
Notes:
- Request is latched and acked until serviced.
- Event output is valid for the stage following this one.
- Optional req regs & resync.
- Optional req level / edge operation.
- For automatic clearing @ async reset, set RESET_VAL to 1.
 
--------------------------------------------------------------------------------
*/
 
module event_ctrl
#(
parameter integer REGS_REQ = 2, // input registers option
parameter integer EDGE_REQ = 0, // edge/level input option
parameter integer RESET_VAL = 1, // async reset value option
parameter integer THREADS = 4, // number of threads
parameter integer THRD_W = 2 // thread width
)
(
// clocks & resets
input wire clk_i, // clock
input wire rst_i, // async. reset, active high
// I/O
input wire [THRD_W-1:0] thrd_i, // thread
input wire [THREADS-1:0] en_i, // event enable, active high
input wire [THREADS-1:0] req_i, // event request, active high
output reg [THREADS-1:0] ack_o, // event ack, active high until serviced
output reg event_o // event, active high for one clock
);
 
 
/*
----------------------
-- internal signals --
----------------------
*/
wire [THREADS-1:0] req_0, req_2, thread_flag;
 
 
 
/*
================
== code start ==
================
*/
 
 
// optional input req regs
pipe
#(
.DEPTH ( REGS_REQ ),
.WIDTH ( THREADS ),
.RESET_VAL ( 0 )
)
req_regs
(
.clk_i ( clk_i ),
.rst_i ( rst_i ),
.data_i ( req_i ),
.data_o ( req_0 )
);
 
 
// optional input req edge detect
generate
if ( EDGE_REQ ) begin
reg [THREADS-1:0] req_1;
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
req_1 <= 'b0;
end else begin
req_1 <= req_0;
end
end
assign req_2 = req_0 & ~req_1;
end else begin
assign req_2 = req_0;
end
endgenerate
 
// decode thread flags (one hot)
assign thread_flag = 1'b1 << thrd_i;
 
// register & latch events
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
ack_o <= { THREADS{ RESET_VAL[0] } };
end else begin
ack_o <= ( en_i & req_2 ) | ( ack_o & ~thread_flag );
end
end
 
// output event (use in following stage)
always @ ( posedge clk_i or posedge rst_i ) begin
if ( rst_i ) begin
event_o <= 'b0;
end else begin
event_o <= |( ack_o & thread_flag );
end
end
 
 
endmodule
/trunk/v04.05/ep4ce6e22c8_demo_board.v
0,0 → 1,70
/*
--------------------------------------------------------------------------------
 
Module : ep4ce6e22c8_demo_board.v
 
--------------------------------------------------------------------------------
 
Function:
- Processor core with PLL & LED outputs.
 
Instantiates:
- hive_core.v
- pll.v
 
Notes:
 
 
--------------------------------------------------------------------------------
*/
 
module ep4ce6e22c8_demo_board
#(
parameter integer LED_W = 4
)
(
// clocks & resets
input wire clk_50m_i, // clock
input wire rstn_i, // async. reset, active low
//
output wire [LED_W-1:0] led_o // LEDs, active low
);
 
 
/*
----------------------
-- internal signals --
----------------------
*/
wire [31:0] io_o;
wire clk_pll;
 
 
/*
================
== code start ==
================
*/
 
 
pll pll_inst (
.inclk0 ( clk_50m_i ),
.c0 ( clk_pll )
);
 
hive_core hive_core_inst
(
.clk_i ( clk_pll ),
.rst_i ( ~rstn_i ),
.intr_req_i ( ), // unused
.io_i ( ), // unused
.io_o ( io_o )
);
 
// the LEDs are active low
assign led_o = ~io_o[3:0];
 
 
endmodule
/trunk/v04.05/hive_core.sdc
0,0 → 1,108
## Generated SDC file "hive_core.sdc"
 
## Copyright (C) 1991-2010 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
 
 
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition"
 
## DATE "Wed May 15 09:26:03 2013"
 
##
## DEVICE "EP3C5E144C8"
##
 
 
#**************************************************************
# Time Information
#**************************************************************
 
set_time_format -unit ns -decimal_places 3
 
 
 
#**************************************************************
# Create Clock
#**************************************************************
 
create_clock -name clk_i clk_i -period "200 MHz"
 
 
#**************************************************************
# Create Generated Clock
#**************************************************************
 
 
 
#**************************************************************
# Set Clock Latency
#**************************************************************
 
 
 
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
 
derive_clock_uncertainty
 
 
#**************************************************************
# Set Input Delay
#**************************************************************
 
 
 
#**************************************************************
# Set Output Delay
#**************************************************************
 
 
 
#**************************************************************
# Set Clock Groups
#**************************************************************
 
 
 
#**************************************************************
# Set False Path
#**************************************************************
 
 
 
#**************************************************************
# Set Multicycle Path
#**************************************************************
 
 
 
#**************************************************************
# Set Maximum Delay
#**************************************************************
 
 
 
#**************************************************************
# Set Minimum Delay
#**************************************************************
 
 
 
#**************************************************************
# Set Input Transition
#**************************************************************
 
/trunk/v04.05/README.txt
0,0 → 1,16
* Hive soft processor core readme file *
 
- All *.v verilog and include *.h files are in a single directory,
where "hive_core.v" is the top level entry.
- There are several boot code files in the "boot_code" directory,
to use one, bring it into the main directory and rename it
"boot_code.h".
- There may also an "unused" directory containing files that aren't
currently part of the project but may be of interest.
- There is a "hive_core.qpf" project file for Altera Quartus II9.1sp2 Web Edition.
With this tool you can compile to a target, and with the file "hive_core.vwf" you
can simulate. I recommend functional simulation when fiddling around
because the compile is much faster.
- There is also a "hive_core.sdc" file which sets the target top speed to
200 MHz in Quartus, and "hive_core.qsf" which is a project settings file.
- Don't forget to assign pins when doing a real project!
/trunk/v04.05/hive_core.qws
0,0 → 1,27
[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
ptn_Child2=Document-1
[ProjectWorkspace.Frames.ChildFrames.Document-0]
ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
DocPathName=boot_code/boot_code_divide.h
DocumentCLSID={0b720e69-67da-11d0-bf4f-0000c08cb0c0}
IsChildFrameDetached=False
IsActiveChildFrame=False
ptn_Child1=StateMap
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0.StateMap]
AFC_IN_REPORT=False
[ProjectWorkspace.Frames.ChildFrames.Document-1]
ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0]
DocPathName=boot_code.h
DocumentCLSID={0b720e69-67da-11d0-bf4f-0000c08cb0c0}
IsChildFrameDetached=False
IsActiveChildFrame=True
ptn_Child1=StateMap
[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0.StateMap]
AFC_IN_REPORT=False
/trunk/v04.05/ep4ce6e22c8_demo_board.sdc
0,0 → 1,2
create_clock -name clk_50m_i clk_50m_i -period "50 MHz"
derive_pll_clocks
/trunk/v04.05/tst_encode.h
0,0 → 1,18
`ifndef _tst_encode_h_
`define _tst_encode_h_
 
//
`define z 2'h0
`define nz 2'h1
`define lz 2'h2
`define nlz 2'h3
//
`define e 4'h8
`define ne 4'h9
`define ls 4'ha
`define nls 4'hb
`define lu 4'hc
`define nlu 4'hd
//
 
`endif // _tst_encode_h_
/trunk/v04.05/ep4ce6e22c8_demo_board.qws
0,0 → 1,18
[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
ptn_Child2=Document-1
ptn_Child3=Document-2
[ProjectWorkspace.Frames.ChildFrames.Document-2]
ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-2.ViewFrame-0]
DocPathName=pll.v
DocumentCLSID={84678d98-dc76-11d0-a0d8-0020affa5bde}
IsChildFrameDetached=False
IsActiveChildFrame=True
ptn_Child1=StateMap
[ProjectWorkspace.Frames.ChildFrames.Document-2.ViewFrame-0.StateMap]
AFC_IN_REPORT=False

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