URL
https://opencores.org/ocsvn/hpc-16/hpc-16/trunk
Subversion Repositories hpc-16
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- This comparison shows the changes necessary to convert path
/hpc-16
- from Rev 17 to Rev 18
- ↔ Reverse comparison
Rev 17 → Rev 18
/trunk/impl0/asm/MyHPC16ListenerUtil.py
0,0 → 1,216
#-------------------------------------------------------------- |
#-- HPC-16 Assembler |
#-------------------------------------------------------------- |
#-- project: HPC-16 Microprocessor |
#-- |
#-- ANTLR4 parser Listener Util |
#-- |
#-- |
#-- |
#-- Author: M. Umair Siddiqui (umairsiddiqui@opencores.org) |
#--------------------------------------------------------------- |
#------------------------------------------------------------------------------------ |
#-- -- |
#-- Copyright (c) 2015, M. Umair Siddiqui all rights reserved -- |
#-- -- |
#-- This file is part of HPC-16. -- |
#-- -- |
#-- HPC-16 is free software; you can redistribute it and/or modify -- |
#-- it under the terms of the GNU Lesser General Public License as published by -- |
#-- the Free Software Foundation; either version 2.1 of the License, or -- |
#-- (at your option) any later version. -- |
#-- -- |
#-- HPC-16 is distributed in the hope that it will be useful, -- |
#-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- |
#-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- |
#-- GNU Lesser General Public License for more details. -- |
#-- -- |
#-- You should have received a copy of the GNU Lesser General Public License -- |
#-- along with HPC-16; if not, write to the Free Software -- |
#-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- |
#-- -- |
#------------------------------------------------------------------------------------ |
|
from __future__ import print_function |
import sys |
import re |
import math |
from antlr4.error.Errors import * |
|
class MyHPC16ListenerUtil: |
|
def __init__(self, fout): |
self.fout = fout |
self.opcode = dict() |
self.regcode = dict() |
self.jcc_opcode = dict() |
self.alu_opcode = dict() |
self.shift_opcode = dict() |
self.setup_opcode() |
self.setup_regcode() |
self.setup_jcc_opcode() |
self.setup_alu_opcode() |
self.setup_shift_opcode() |
|
def setup_shift_opcode(self): |
self.shift_opcode["sll"] = '0b000' |
self.shift_opcode["slr"] = '0b001' |
self.shift_opcode["sal"] = '0b010' |
self.shift_opcode["sar"] = '0b011' |
self.shift_opcode["rol"] = '0b100' |
self.shift_opcode["ror"] = '0b101' |
self.shift_opcode["rcl"] = '0b110' |
self.shift_opcode["rcr"] = '0b111' |
|
def setup_alu_opcode(self): |
self.alu_opcode["sub"] = '0b000' |
self.alu_opcode["add"] = '0b001' |
self.alu_opcode["sbb"] = '0b010' |
self.alu_opcode["adc"] = '0b011' |
self.alu_opcode["not"] = '0b100' |
self.alu_opcode["and"] = '0b101' |
self.alu_opcode["or "] = '0b110' |
self.alu_opcode["xor"] = '0b111' |
|
def setup_regcode(self): |
for i in range(16): |
self.regcode['R'+str(i)] = bin(i) |
self.regcode['r'+str(i)] = bin(i) |
|
def setup_jcc_opcode(self): |
self.jcc_opcode ["jo"] = '0b0000' |
self.jcc_opcode ["jno"] = '0b0001' |
self.jcc_opcode ["jb"] = '0b0010' |
self.jcc_opcode ["jnae"] = '0b0010' |
self.jcc_opcode ["jnb"] = '0b0011' |
self.jcc_opcode ["jae"] = '0b0011' |
self.jcc_opcode ["je"] = '0b0100' |
self.jcc_opcode ["jz"] = '0b0100' |
self.jcc_opcode ["jne"] = '0b0101' |
self.jcc_opcode ["jnz"] = '0b0101' |
self.jcc_opcode ["jbe"] = '0b0110' |
self.jcc_opcode ["jna"] = '0b0110' |
self.jcc_opcode ["jnbe"] = '0b0111' |
self.jcc_opcode ["ja"] = '0b0111' |
self.jcc_opcode ["js"] = '0b1000' |
self.jcc_opcode ["jns"] = '0b1001' |
self.jcc_opcode ["jl"] = '0b1100' |
self.jcc_opcode ["jnge"] = '0b1100' |
self.jcc_opcode ["jnl"] = '0b1101' |
self.jcc_opcode ["jge"] = '0b1101' |
self.jcc_opcode ["jle"] = '0b1110' |
self.jcc_opcode ["jng"] = '0b1110' |
self.jcc_opcode ["jnle"] = '0b1111' |
self.jcc_opcode ["jg"] = '0b1111' |
|
|
def setup_opcode(self): |
self.opcode["mov_reg_reg"] = '0b00000001' |
self.opcode["mov_sp_reg"] = '0b00000010' |
self.opcode["mov_reg_sp"] = '0b00000100' |
|
self.opcode["ld_reg_reg"] = '0b00001000' |
self.opcode["ld_reg_reg_imm16"] = '0b00001001' |
self.opcode["ld_reg_sp"] = '0b00001010' |
self.opcode["ld_reg_sp_imm16"] = '0b00001100' |
|
self.opcode["st_reg_reg"] = '0b00010000' |
self.opcode["st_reg_reg_imm16"] = '0b00010001' |
self.opcode["st_reg_sp"] = '0b00010010' |
self.opcode["st_reg_sp_imm16"] = '0b00010100' |
|
self.opcode["lbzx_reg_reg"] = '0b00011000' |
self.opcode["lbzx_reg_reg_imm16"] = '0b00011100' |
self.opcode["lbsx_reg_reg"] = '0b00011001' |
self.opcode["lbsx_reg_reg_imm16"] = '0b00011101' |
|
self.opcode["sb_reg_reg"] = '0b00100001' |
self.opcode["sb_reg_reg_imm16"] = '0b00100010' |
|
self.opcode["inc_reg"] = '0b00101000' |
self.opcode["dec_reg"] = '0b00101001' |
|
self.opcode["alur"] = '0b00110' |
self.opcode["shiftr"] = '0b00111' |
|
self.opcode["cmp_reg_reg"] = '0b01000000' |
self.opcode["test_reg_reg"] = '0b01000101' |
|
self.opcode["li_reg_imm16"] = '0b01001001' |
self.opcode["li_sp_imm16"] = '0b01001010' |
|
self.opcode["alui"] = '0b01010' |
self.opcode["shifti"] = '0b01011' |
|
self.opcode["cmp_reg_imm16"] = '0b01100000' |
self.opcode["test_reg_imm16"] = '0b01100101' |
|
self.opcode["sub_sp_imm16"] = '0b01101000' |
self.opcode["add_sp_imm16"] = '0b01101001' |
|
self.opcode["push_reg"] = '0b01110000' |
self.opcode["pushf"] = '0b01110001' |
self.opcode["pop_reg"] = '0b01110100' |
self.opcode["popf"] = '0b01110101' |
|
self.opcode["acall_reg"] = '0b01111001' |
self.opcode["call_reg"] = '0b01111010' |
self.opcode["call_imm11"] = '0b10000' |
|
self.opcode["ret"] = '0b10001' |
self.opcode["int_imm4"] = '0b10010' |
self.opcode["into"] = '0b10011' |
self.opcode["iret"] = '0b10100' |
|
self.opcode["ajmp"] = '0b10101001' |
|
self.opcode["jmp_reg"] = '0b10101010' |
|
self.opcode["jmp_imm11"] = '0b10110' |
|
self.opcode["jcc"] = '0b10111' |
|
self.opcode["clc"] = '0b11000000' |
self.opcode["stc"] = '0b11000001' |
self.opcode["cmc"] = '0b11000010' |
self.opcode["cli"] = '0b11000100' |
self.opcode["sti"] = '0b11000101' |
|
self.opcode["nop"] = '0b11110' |
self.opcode["halt"] = '0b11111' |
|
def log_error(self, s): |
print("# ERROR", s, "\n", file=self.fout) |
print(s, "\n", file=sys.stderr) |
raise ParseCancellationException(s) |
|
def vld_reg(self, r): |
if not r in self.regcode: |
self.log_error("invalid register ===> %s\n" % dest) |
return False |
else : |
return True |
|
def vld_imm_val(self, imm_val, imm_max): |
if imm_val < imm_max: |
return True |
else: |
s = "invalid immediate operand ===> %s\n required a %d-bit value" % (hex(imm_val), int(math.log(imm_max,2))) |
self.log_error(s) |
return False |
|
def get_imm_val(self, imm): |
if re.match("0x", imm): |
return int(imm, 16) |
else: |
return int(imm) |
|
def write_ins(self, ins): |
print(hex(ins), file=self.fout) |
|
def write_info(self, info): |
print(info, file=self.fout) |
|
def cleanup(self): |
self.fout.close() |
|
/trunk/impl0/asm/MyHPC16Listener.py
0,0 → 1,1364
#-------------------------------------------------------------- |
#-- HPC-16 Assembler |
#-------------------------------------------------------------- |
#-- project: HPC-16 Microprocessor |
#-- |
#-- ANTLR4 parser Listener |
#-- |
#-- |
#-- |
#-- Author: M. Umair Siddiqui (umairsiddiqui@opencores.org) |
#--------------------------------------------------------------- |
#------------------------------------------------------------------------------------ |
#-- -- |
#-- Copyright (c) 2015, M. Umair Siddiqui all rights reserved -- |
#-- -- |
#-- This file is part of HPC-16. -- |
#-- -- |
#-- HPC-16 is free software; you can redistribute it and/or modify -- |
#-- it under the terms of the GNU Lesser General Public License as published by -- |
#-- the Free Software Foundation; either version 2.1 of the License, or -- |
#-- (at your option) any later version. -- |
#-- -- |
#-- HPC-16 is distributed in the hope that it will be useful, -- |
#-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- |
#-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- |
#-- GNU Lesser General Public License for more details. -- |
#-- -- |
#-- You should have received a copy of the GNU Lesser General Public License -- |
#-- along with HPC-16; if not, write to the Free Software -- |
#-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- |
#-- -- |
#------------------------------------------------------------------------------------ |
|
import sys |
import re |
import math |
from antlr4 import * |
from HPC16Listener import HPC16Listener |
from MyHPC16ListenerUtil import MyHPC16ListenerUtil |
|
class MyHPC16Listener(HPC16Listener): |
|
def __init__(self, fout): |
self.debug = 1 |
self.util = MyHPC16ListenerUtil(fout) |
super(MyHPC16Listener, self).__init__() |
|
# Enter a parse tree produced by HPC16Parser#prog. |
def enterProg(self, ctx): |
pass |
|
# Exit a parse tree produced by HPC16Parser#prog. |
def exitProg(self, ctx): |
self.util.cleanup() |
|
def enterStat(self, ctx): |
if self.debug: |
st = "#" |
for i in range(ctx.getChildCount()): |
st = st + " " + ctx.getChild(i).getText() |
self.util.write_info(st.rstrip()) |
|
# Exit a parse tree produced by HPC16Parser#mov_reg_reg. |
def exitMov_reg_reg(self, ctx): |
err = False |
dest = ctx.REG(0).getText() |
src = ctx.REG(1).getText() |
err = not self.util.vld_reg(dest) or not self.util.vld_reg(src) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["mov_reg_reg"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | int(self.util.regcode[src], 2) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#mov_sp_reg. |
def exitMov_sp_reg(self, ctx): |
err = False |
src = ctx.REG().getText() |
err = not self.util.vld_reg(src) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["mov_sp_reg"], 2) << 8 |
ins = ins | int(self.util.regcode[src], 2) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#mov_reg_sp. |
def exitMov_reg_sp(self, ctx): |
err = False |
dest = ctx.REG().getText() |
err = not self.util.vld_reg(dest) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["mov_reg_sp"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#ld_reg_reg. |
def exitLd_reg_reg(self, ctx): |
err = False |
dest = ctx.REG(0).getText() |
src = ctx.REG(1).getText() |
err = not self.util.vld_reg(dest) or not self.util.vld_reg(src) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["ld_reg_reg"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | int(self.util.regcode[src], 2) |
self.util.write_ins(ins) |
|
def enterLd_reg_reg_imm16(self, ctx): |
if self.debug: |
self.util.write_info("# ld %s, (%s + %s)" % |
(ctx.REG(0).getText(), ctx.REG(1).getText()), ) |
|
# Exit a parse tree produced by HPC16Parser#ld_reg_reg_imm16. |
def exitLd_reg_reg_imm16(self, ctx): |
err = False |
dest = ctx.REG(0).getText() |
src = ctx.REG(1).getText() |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_reg(dest) or not self.util.vld_reg(src) or not self.util.vld_imm_val(imm, 2**16) |
|
if not err: |
ins = 0 |
ins = int(self.util.opcode["ld_reg_reg_imm16"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | int(self.util.regcode[src], 2) |
self.util.write_ins(ins) |
self.util.write_ins(imm) |
|
|
# Exit a parse tree produced by HPC16Parser#ld_reg_sp. |
def exitLd_reg_sp(self, ctx): |
err = False |
dest = ctx.REG().getText() |
err = not self.util.vld_reg(dest) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["ld_reg_sp"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#ld_reg_sp_imm16. |
def exitLd_reg_sp_imm16(self, ctx): |
err = False |
dest = ctx.REG().getText() |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_reg(dest) or not self.util.vld_imm_val(imm, 2**16) |
|
if not err: |
ins = 0 |
ins = int(self.util.opcode["ld_reg_sp_imm16"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
self.util.write_ins(ins) |
self.util.write_ins(imm) |
|
# Exit a parse tree produced by HPC16Parser#st_reg_reg. |
def exitSt_reg_reg(self, ctx): |
err = False |
src = ctx.REG(0).getText() |
dest = ctx.REG(1).getText() |
err = not self.util.vld_reg(dest) or not self.util.vld_reg(src) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["st_reg_reg"], 2) << 8 |
ins = ins | int(self.util.regcode[src], 2) << 4 |
ins = ins | int(self.util.regcode[dest], 2) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#st_reg_reg_imm16. |
def exitSt_reg_reg_imm16(self, ctx): |
err = False |
src = ctx.REG(0).getText() |
dest = ctx.REG(1).getText() |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_reg(dest) or not self.util.vld_reg(src) or not self.util.vld_imm_val(imm, 2**16) |
|
if not err: |
ins = 0 |
ins = int(self.util.opcode["st_reg_reg_imm16"], 2) << 8 |
ins = ins | int(self.util.regcode[src], 2) << 4 |
ins = ins | int(self.util.regcode[dest], 2) |
self.util.write_ins(ins) |
self.util.write_ins(imm) |
|
# Exit a parse tree produced by HPC16Parser#st_reg_sp. |
def exitSt_reg_sp(self, ctx): |
err = False |
src = ctx.REG().getText() |
err = not self.util.vld_reg(src) |
|
if not err: |
ins = 0 |
ins = int(self.util.opcode["st_reg_sp"], 2) << 8 |
ins = ins | int(self.util.regcode[src], 2) << 4 |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#st_reg_sp_imm16. |
def exitSt_reg_sp_imm16(self, ctx): |
err = False |
src = ctx.REG().getText() |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_reg(src) or not self.util.vld_imm_val(imm, 2**16) |
|
if not err: |
ins = 0 |
ins = int(self.util.opcode["st_reg_sp_imm16"], 2) << 8 |
ins = ins | int(self.util.regcode[src], 2) << 4 |
self.util.write_ins(ins) |
self.util.write_ins(imm) |
|
|
# Exit a parse tree produced by HPC16Parser#lbzx_reg_reg. |
def exitLbzx_reg_reg(self, ctx): |
err = False |
dest = ctx.REG(0).getText() |
src = ctx.REG(1).getText() |
err = not self.util.vld_reg(dest) or not self.util.vld_reg(src) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["lbzx_reg_reg"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | int(self.util.regcode[src], 2) |
self.util.write_ins(ins) |
|
|
# Exit a parse tree produced by HPC16Parser#lbzx_reg_reg_imm16. |
def exitLbzx_reg_reg_imm16(self, ctx): |
err = False |
dest = ctx.REG(0).getText() |
src = ctx.REG(1).getText() |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_reg(dest) or not self.util.vld_reg(src) or not self.util.vld_imm_val(imm, 2**16) |
|
if not err: |
ins = 0 |
ins = int(self.util.opcode["lbzx_reg_reg_imm16"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | int(self.util.regcode[src], 2) |
self.util.write_ins(ins) |
self.util.write_ins(imm) |
|
# Exit a parse tree produced by HPC16Parser#lbsx_reg_reg. |
def exitLbsx_reg_reg(self, ctx): |
err = False |
dest = ctx.REG(0).getText() |
src = ctx.REG(1).getText() |
err = not self.util.vld_reg(dest) or not self.util.vld_reg(src) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["lbsx_reg_reg"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | int(self.util.regcode[src], 2) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#lbsx_reg_reg_imm16. |
def exitLbsx_reg_reg_imm16(self, ctx): |
err = False |
dest = ctx.REG(0).getText() |
src = ctx.REG(1).getText() |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_reg(dest) or not self.util.vld_reg(src) or not self.util.vld_imm_val(imm, 2**16) |
|
if not err: |
ins = 0 |
ins = int(self.util.opcode["lbsx_reg_reg_imm16"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | int(self.util.regcode[src], 2) |
self.util.write_ins(ins) |
self.util.write_ins(imm) |
|
# Exit a parse tree produced by HPC16Parser#sb_reg_reg. |
def exitSb_reg_reg(self, ctx): |
err = False |
src = ctx.REG(0).getText() |
dest = ctx.REG(1).getText() |
err = not self.util.vld_reg(dest) or not self.util.vld_reg(src) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["sb_reg_reg"], 2) << 8 |
ins = ins | int(self.util.regcode[src], 2) << 4 |
ins = ins | int(self.util.regcode[dest], 2) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#sb_reg_reg_imm16. |
def exitSb_reg_reg_imm16(self, ctx): |
err = False |
src = ctx.REG(0).getText() |
dest = ctx.REG(1).getText() |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_reg(dest) or not self.util.vld_reg(src) or not self.util.vld_imm_val(imm, 2**16) |
|
if not err: |
ins = 0 |
ins = int(self.util.opcode["sb_reg_reg_imm16"], 2) << 8 |
ins = ins | int(self.util.regcode[src], 2) << 4 |
ins = ins | int(self.util.regcode[dest], 2) |
self.util.write_ins(ins) |
self.util.write_ins(imm) |
|
# Exit a parse tree produced by HPC16Parser#li_reg_imm16. |
def exitLi_reg_imm16(self, ctx): |
err = False |
dest = ctx.REG().getText() |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_reg(dest) or not self.util.vld_imm_val(imm, 2**16) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["li_reg_imm16"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
self.util.write_ins(ins) |
self.util.write_ins(imm) |
|
|
# Exit a parse tree produced by HPC16Parser#li_sp_imm16. |
def exitLi_sp_imm16(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**16) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["li_sp_imm16"], 2) << 8 |
self.util.write_ins(ins) |
self.util.write_ins(imm) |
|
|
# Exit a parse tree produced by HPC16Parser#inc_reg. |
def exitInc_reg(self, ctx): |
err = False |
dest = ctx.REG().getText() |
err = not self.util.vld_reg(dest) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["inc_reg"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#dec_reg. |
def exitDec_reg(self, ctx): |
err = False |
dest = ctx.REG().getText() |
err = not self.util.vld_reg(dest) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["dec_reg"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#sub_reg_reg. |
def exitSub_reg_reg(self, ctx): |
err = False |
dest = ctx.REG(0).getText() |
src = ctx.REG(1).getText() |
err = not self.util.vld_reg(dest) and not self.util.vld_reg(src) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["alur"], 2) << 11 |
ins = ins | int(self.util.alu_opcode["sub"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | int(self.util.regcode[src], 2) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#and_reg_reg. |
def exitAnd_reg_reg(self, ctx): |
err = False |
dest = ctx.REG(0).getText() |
src = ctx.REG(1).getText() |
err = not self.util.vld_reg(dest) and not self.util.vld_reg(src) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["alur"], 2) << 11 |
ins = ins | int(self.util.alu_opcode["and"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | int(self.util.regcode[src], 2) |
self.util.write_ins(ins) |
|
|
# Exit a parse tree produced by HPC16Parser#add_reg_reg. |
def exitAdd_reg_reg(self, ctx): |
err = False |
dest = ctx.REG(0).getText() |
src = ctx.REG(1).getText() |
err = not self.util.vld_reg(dest) and not self.util.vld_reg(src) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["alur"], 2) << 11 |
ins = ins | int(self.util.alu_opcode["add"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | int(self.util.regcode[src], 2) |
self.util.write_ins(ins) |
|
|
# Exit a parse tree produced by HPC16Parser#adc_reg_reg. |
def exitAdc_reg_reg(self, ctx): |
err = False |
dest = ctx.REG(0).getText() |
src = ctx.REG(1).getText() |
err = not self.util.vld_reg(dest) and not self.util.vld_reg(src) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["alur"], 2) << 11 |
ins = ins | int(self.util.alu_opcode["adc"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | int(self.util.regcode[src], 2) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#sbb_reg_reg. |
def exitSbb_reg_reg(self, ctx): |
err = False |
dest = ctx.REG(0).getText() |
src = ctx.REG(1).getText() |
err = not self.util.vld_reg(dest) and not self.util.vld_reg(src) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["alur"], 2) << 11 |
ins = ins | int(self.util.alu_opcode["sbb"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | int(self.util.regcode[src], 2) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#or_reg_reg. |
def exitOr_reg_reg(self, ctx): |
err = False |
dest = ctx.REG(0).getText() |
src = ctx.REG(1).getText() |
err = not self.util.vld_reg(dest) and not self.util.vld_reg(src) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["alur"], 2) << 11 |
ins = ins | int(self.util.alu_opcode["or"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | int(self.util.regcode[src], 2) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#xor_reg_reg. |
def exitXor_reg_reg(self, ctx): |
err = False |
dest = ctx.REG(0).getText() |
src = ctx.REG(1).getText() |
err = not self.util.vld_reg(dest) and not self.util.vld_reg(src) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["alur"], 2) << 11 |
ins = ins | int(self.util.alu_opcode["xor"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | int(self.util.regcode[src], 2) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#not_reg. |
def exitNot_reg(self, ctx): |
err = False |
dest = ctx.REG().getText() |
err = not self.util.vld_reg(dest) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["alur"], 2) << 11 |
ins = ins | int(self.util.alu_opcode["not"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#sub_reg_imm16. |
def exitSub_reg_imm16(self, ctx): |
err = False |
dest = ctx.REG().getText() |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_reg(dest) or not self.util.vld_imm_val(imm, 2**16) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["alui"], 2) << 11 |
ins = ins | int(self.util.alu_opcode["sub"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
self.util.write_ins(ins) |
self.util.write_ins(imm) |
|
# Exit a parse tree produced by HPC16Parser#and_reg_imm16. |
def exitAnd_reg_imm16(self, ctx): |
err = False |
dest = ctx.REG().getText() |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_reg(dest) or not self.util.vld_imm_val(imm, 2**16) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["alui"], 2) << 11 |
ins = ins | int(self.util.alu_opcode["and"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
self.util.write_ins(ins) |
self.util.write_ins(imm) |
|
# Exit a parse tree produced by HPC16Parser#add_reg_imm16. |
def exitAdd_reg_imm16(self, ctx): |
err = False |
dest = ctx.REG().getText() |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_reg(dest) or not self.util.vld_imm_val(imm, 2**16) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["alui"], 2) << 11 |
ins = ins | int(self.util.alu_opcode["add"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
self.util.write_ins(ins) |
self.util.write_ins(imm) |
|
# Exit a parse tree produced by HPC16Parser#adc_reg_imm16. |
def exitAdc_reg_imm16(self, ctx): |
err = False |
dest = ctx.REG().getText() |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_reg(dest) or not self.util.vld_imm_val(imm, 2**16) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["alui"], 2) << 11 |
ins = ins | int(self.util.alu_opcode["adc"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
self.util.write_ins(ins) |
self.util.write_ins(imm) |
|
# Exit a parse tree produced by HPC16Parser#sbb_reg_imm16. |
def exitSbb_reg_imm16(self, ctx): |
err = False |
dest = ctx.REG().getText() |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_reg(dest) or not self.util.vld_imm_val(imm, 2**16) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["alui"], 2) << 11 |
ins = ins | int(self.util.alu_opcode["sbb"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
self.util.write_ins(ins) |
self.util.write_ins(imm) |
|
|
# Exit a parse tree produced by HPC16Parser#or_reg_imm16. |
def exitOr_reg_imm16(self, ctx): |
err = False |
dest = ctx.REG().getText() |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_reg(dest) or not self.util.vld_imm_val(imm, 2**16) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["alui"], 2) << 11 |
ins = ins | int(self.util.alu_opcode["or"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
self.util.write_ins(ins) |
self.util.write_ins(imm) |
|
# Exit a parse tree produced by HPC16Parser#xor_reg_imm16. |
def exitXor_reg_imm16(self, ctx): |
err = False |
dest = ctx.REG().getText() |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_reg(dest) or not self.util.vld_imm_val(imm, 2**16) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["alui"], 2) << 11 |
ins = ins | int(self.util.alu_opcode["xor"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
self.util.write_ins(ins) |
self.util.write_ins(imm) |
|
|
# Exit a parse tree produced by HPC16Parser#add_sp_imm16. |
def exitAdd_sp_imm16(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**16) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["add_sp_imm16"], 2) << 8 |
self.util.write_ins(ins) |
self.util.write_ins(imm) |
|
# Exit a parse tree produced by HPC16Parser#sub_sp_imm16. |
def exitSub_sp_imm16(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**16) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["sub_sp_imm16"], 2) << 8 |
self.util.write_ins(ins) |
self.util.write_ins(imm) |
|
# Exit a parse tree produced by HPC16Parser#cmp_reg_reg. |
def exitCmp_reg_reg(self, ctx): |
err = False |
dest = ctx.REG(0).getText() |
src = ctx.REG(1).getText() |
err = not self.util.vld_reg(dest) or not self.util.vld_reg(src) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["cmp_reg_reg"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | int(self.util.regcode[src], 2) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#test_reg_reg. |
def exitTest_reg_reg(self, ctx): |
err = False |
dest = ctx.REG(0).getText() |
src = ctx.REG(1).getText() |
err = not self.util.vld_reg(dest) or not self.util.vld_reg(src) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["test_reg_reg"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | int(self.util.regcode[src], 2) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#cmp_reg_imm16. |
def exitCmp_reg_imm16(self, ctx): |
err = False |
dest = ctx.REG().getText() |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_reg(dest) or not self.util.vld_imm_val(imm, 2**16) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["cmp_reg_imm16"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
self.util.write_ins(ins) |
self.util.write_ins(imm) |
|
# Exit a parse tree produced by HPC16Parser#test_reg_imm16. |
def exitTest_reg_imm16(self, ctx): |
err = False |
dest = ctx.REG().getText() |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_reg(dest) or not self.util.vld_imm_val(imm, 2**16) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["test_reg_imm16"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
self.util.write_ins(ins) |
self.util.write_ins(imm) |
|
|
# Exit a parse tree produced by HPC16Parser#sll_reg_reg. |
def exitSll_reg_reg(self, ctx): |
err = False |
dest = ctx.REG(0).getText() |
src = ctx.REG(1).getText() |
err = not self.util.vld_reg(dest) and not self.util.vld_reg(src) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["shiftr"], 2) << 11 |
ins = ins | int(self.util.shift_opcode["sll"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | int(self.util.regcode[src], 2) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#slr_reg_reg. |
def exitSlr_reg_reg(self, ctx): |
err = False |
dest = ctx.REG(0).getText() |
src = ctx.REG(1).getText() |
err = not self.util.vld_reg(dest) and not self.util.vld_reg(src) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["shiftr"], 2) << 11 |
ins = ins | int(self.util.shift_opcode["slr"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | int(self.util.regcode[src], 2) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#sal_reg_reg. |
def exitSal_reg_reg(self, ctx): |
err = False |
dest = ctx.REG(0).getText() |
src = ctx.REG(1).getText() |
err = not self.util.vld_reg(dest) and not self.util.vld_reg(src) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["shiftr"], 2) << 11 |
ins = ins | int(self.util.shift_opcode["sal"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | int(self.util.regcode[src], 2) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#sar_reg_reg. |
def exitSar_reg_reg(self, ctx): |
err = False |
dest = ctx.REG(0).getText() |
src = ctx.REG(1).getText() |
err = not self.util.vld_reg(dest) and not self.util.vld_reg(src) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["shiftr"], 2) << 11 |
ins = ins | int(self.util.shift_opcode["sar"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | int(self.util.regcode[src], 2) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#rol_reg_reg. |
def exitRol_reg_reg(self, ctx): |
err = False |
dest = ctx.REG(0).getText() |
src = ctx.REG(1).getText() |
err = not self.util.vld_reg(dest) and not self.util.vld_reg(src) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["shiftr"], 2) << 11 |
ins = ins | int(self.util.shift_opcode["rol"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | int(self.util.regcode[src], 2) |
self.util.write_ins(ins) |
|
|
# Exit a parse tree produced by HPC16Parser#ror_reg_reg. |
def exitRor_reg_reg(self, ctx): |
err = False |
dest = ctx.REG(0).getText() |
src = ctx.REG(1).getText() |
err = not self.util.vld_reg(dest) and not self.util.vld_reg(src) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["shiftr"], 2) << 11 |
ins = ins | int(self.util.shift_opcode["ror"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | int(self.util.regcode[src], 2) |
self.util.write_ins(ins) |
|
|
# Exit a parse tree produced by HPC16Parser#rcl_reg_reg. |
def exitRcl_reg_reg(self, ctx): |
err = False |
dest = ctx.REG(0).getText() |
src = ctx.REG(1).getText() |
err = not self.util.vld_reg(dest) and not self.util.vld_reg(src) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["shiftr"], 2) << 11 |
ins = ins | int(self.util.shift_opcode["rcl"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | int(self.util.regcode[src], 2) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#rcr_reg_reg. |
def exitRcr_reg_reg(self, ctx): |
err = False |
dest = ctx.REG(0).getText() |
src = ctx.REG(1).getText() |
err = not self.util.vld_reg(dest) and not self.util.vld_reg(src) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["shiftr"], 2) << 11 |
ins = ins | int(self.util.shift_opcode["rcr"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | int(self.util.regcode[src], 2) |
self.util.write_ins(ins) |
|
|
# Exit a parse tree produced by HPC16Parser#sll_reg_imm4. |
def exitSll_reg_imm4(self, ctx): |
err = False |
dest = ctx.REG().getText() |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_reg(dest) or not self.util.vld_imm_val(imm, 2**4) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["shifti"], 2) << 11 |
ins = ins | int(self.util.shift_opcode["sll"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | imm |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#slr_reg_imm4. |
def exitSlr_reg_imm4(self, ctx): |
err = False |
dest = ctx.REG().getText() |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_reg(dest) or not self.util.vld_imm_val(imm, 2**4) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["shifti"], 2) << 11 |
ins = ins | int(self.util.shift_opcode["slr"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | imm |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#sal_reg_imm4. |
def exitSal_reg_imm4(self, ctx): |
err = False |
dest = ctx.REG().getText() |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_reg(dest) or not self.util.vld_imm_val(imm, 2**4) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["shifti"], 2) << 11 |
ins = ins | int(self.util.shift_opcode["sal"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | imm |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#sar_reg_imm4. |
def exitSar_reg_imm4(self, ctx): |
err = False |
dest = ctx.REG().getText() |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_reg(dest) or not self.util.vld_imm_val(imm, 2**4) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["shifti"], 2) << 11 |
ins = ins | int(self.util.shift_opcode["sar"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | imm |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#rol_reg_imm4. |
def exitRol_reg_imm4(self, ctx): |
err = False |
dest = ctx.REG().getText() |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_reg(dest) or not self.util.vld_imm_val(imm, 2**4) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["shifti"], 2) << 11 |
ins = ins | int(self.util.shift_opcode["rol"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | imm |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#ror_reg_imm4. |
def exitRor_reg_imm4(self, ctx): |
err = False |
dest = ctx.REG().getText() |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_reg(dest) or not self.util.vld_imm_val(imm, 2**4) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["shifti"], 2) << 11 |
ins = ins | int(self.util.shift_opcode["ror"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | imm |
self.util.write_ins(ins) |
|
|
# Exit a parse tree produced by HPC16Parser#rcl_reg_imm4. |
def exitRcl_reg_imm4(self, ctx): |
err = False |
dest = ctx.REG().getText() |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_reg(dest) or not self.util.vld_imm_val(imm, 2**4) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["shifti"], 2) << 11 |
ins = ins | int(self.util.shift_opcode["rcl"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | imm |
self.util.write_ins(ins) |
|
|
# Exit a parse tree produced by HPC16Parser#rcr_reg_imm4. |
def exitRcr_reg_imm4(self, ctx): |
err = False |
dest = ctx.REG().getText() |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_reg(dest) or not self.util.vld_imm_val(imm, 2**4) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["shifti"], 2) << 11 |
ins = ins | int(self.util.shift_opcode["rcr"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
ins = ins | imm |
self.util.write_ins(ins) |
|
|
# Exit a parse tree produced by HPC16Parser#push_reg. |
def exitPush_reg(self, ctx): |
err = False |
dest = ctx.REG().getText() |
err = not self.util.vld_reg(dest) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["push_reg"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#pushf. |
def exitPushf(self, ctx): |
ins = 0 |
ins = int(self.util.opcode["pushf"], 2) << 8 |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#pop_reg. |
def exitPop_reg(self, ctx): |
err = False |
dest = ctx.REG().getText() |
err = not self.util.vld_reg(dest) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["pop_reg"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) << 4 |
self.util.write_ins(ins) |
|
|
# Exit a parse tree produced by HPC16Parser#popf. |
def exitPopf(self, ctx): |
ins = 0 |
ins = int(self.util.opcode["popf"], 2) << 8 |
self.util.write_ins(ins) |
|
|
# Exit a parse tree produced by HPC16Parser#acall_reg. |
def exitAcall_reg(self, ctx): |
err = False |
dest = ctx.REG().getText() |
err = not self.util.vld_reg(dest) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["acall_reg"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) |
self.util.write_ins(ins) |
|
|
# Exit a parse tree produced by HPC16Parser#call_reg. |
def exitCall_reg(self, ctx): |
err = False |
dest = ctx.REG().getText() |
err = not self.util.vld_reg(dest) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["call_reg"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) |
self.util.write_ins(ins) |
|
|
|
# Exit a parse tree produced by HPC16Parser#call_imm11. |
def exitCall_imm11(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**11) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["call_imm11"], 2) << 11 |
ins = ins | imm |
self.util.write_ins(ins) |
|
|
# Exit a parse tree produced by HPC16Parser#ret. |
def exitRet(self, ctx): |
ins = 0 |
ins = int(self.util.opcode["ret"], 2) << 11 |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#iret. |
def exitIret(self, ctx): |
ins = 0 |
ins = int(self.util.opcode["iret"], 2) << 11 |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#clc. |
def exitClc(self, ctx): |
ins = 0 |
ins = int(self.util.opcode["clc"], 2) << 8 |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#slc. |
def exitStc(self, ctx): |
ins = 0 |
ins = int(self.util.opcode["stc"], 2) << 8 |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#cmc. |
def exitCmc(self, ctx): |
ins = 0 |
ins = int(self.util.opcode["cmc"], 2) << 8 |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#cli. |
def exitCli(self, ctx): |
ins = 0 |
ins = int(self.util.opcode["cli"], 2) << 8 |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#sti. |
def exitSti(self, ctx): |
ins = 0 |
ins = int(self.util.opcode["sti"], 2) << 8 |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#int_imm4. |
def exitInt_imm4(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**4) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["int_imm4"], 2) << 11 |
ins = ins | imm |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#into. |
def exitInto(self, ctx): |
ins = 0 |
ins = int(self.util.opcode["into"], 2) << 11 |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#ajmp. |
def exitAjmp(self, ctx): |
err = False |
dest = ctx.REG().getText() |
err = not self.util.vld_reg(dest) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["ajmp"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) |
self.util.write_ins(ins) |
|
|
# Exit a parse tree produced by HPC16Parser#jmp_reg. |
def exitJmp_reg(self, ctx): |
err = False |
dest = ctx.REG().getText() |
err = not self.util.vld_reg(dest) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["jmp_reg"], 2) << 8 |
ins = ins | int(self.util.regcode[dest], 2) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#jmp_imm11. |
def exitJmp_imm11(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**11) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["jmp_imm11"], 2) << 11 |
ins = ins | imm |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#nop. |
def exitNop(self, ctx): |
ins = 0 |
ins = int(self.util.opcode["nop"], 2) << 11 |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#halt. |
def exitHalt(self, ctx): |
ins = 0 |
ins = int(self.util.opcode["halt"], 2) << 11 |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#jo_imm7. |
def exitJo_imm7(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**7) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["jcc"], 2) << 11 |
ins = ins | (imm >> 4) << 8 |
ins = ins | int(self.util.jcc_opcode["jo"], 2) << 4 |
ins = ins | (imm & 0x0f) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#jno_imm7. |
def exitJno_imm7(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**7) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["jcc"], 2) << 11 |
ins = ins | (imm >> 4) << 8 |
ins = ins | int(self.util.jcc_opcode["jno"], 2) << 4 |
ins = ins | (imm & 0x0f) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#jb_imm7. |
def exitJb_imm7(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**7) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["jcc"], 2) << 11 |
ins = ins | (imm >> 4) << 8 |
ins = ins | int(self.util.jcc_opcode["jb"], 2) << 4 |
ins = ins | (imm & 0x0f) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#jnae_imm7. |
def exitJnae_imm7(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**7) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["jcc"], 2) << 11 |
ins = ins | (imm >> 4) << 8 |
ins = ins | int(self.util.jcc_opcode["jnae"], 2) << 4 |
ins = ins | (imm & 0x0f) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#jnb_imm7. |
def exitJnb_imm7(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**7) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["jcc"], 2) << 11 |
ins = ins | (imm >> 4) << 8 |
ins = ins | int(self.util.jcc_opcode["jnb"], 2) << 4 |
ins = ins | (imm & 0x0f) |
self.util.write_ins(ins) |
|
|
# Exit a parse tree produced by HPC16Parser#jae_imm7. |
def exitJae_imm7(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**7) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["jcc"], 2) << 11 |
ins = ins | (imm >> 4) << 8 |
ins = ins | int(self.util.jcc_opcode["jae"], 2) << 4 |
ins = ins | (imm & 0x0f) |
self.util.write_ins(ins) |
|
|
|
# Exit a parse tree produced by HPC16Parser#je_imm7. |
def exitJe_imm7(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**7) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["jcc"], 2) << 11 |
ins = ins | (imm >> 4) << 8 |
ins = ins | int(self.util.jcc_opcode["je"], 2) << 4 |
ins = ins | (imm & 0x0f) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#jz_imm7. |
def exitJz_imm7(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**7) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["jcc"], 2) << 11 |
ins = ins | (imm >> 4) << 8 |
ins = ins | int(self.util.jcc_opcode["jz"], 2) << 4 |
ins = ins | (imm & 0x0f) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#jne_imm7. |
def exitJne_imm7(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**7) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["jcc"], 2) << 11 |
ins = ins | (imm >> 4) << 8 |
ins = ins | int(self.util.jcc_opcode["jne"], 2) << 4 |
ins = ins | (imm & 0x0f) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#jnz_imm7. |
def exitJnz_imm7(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**7) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["jcc"], 2) << 11 |
ins = ins | (imm >> 4) << 8 |
ins = ins | int(self.util.jcc_opcode["jnz"], 2) << 4 |
ins = ins | (imm & 0x0f) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#jbe_imm7. |
def exitJbe_imm7(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**7) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["jcc"], 2) << 11 |
ins = ins | (imm >> 4) << 8 |
ins = ins | int(self.util.jcc_opcode["jbe"], 2) << 4 |
ins = ins | (imm & 0x0f) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#jna_imm7. |
def exitJna_imm7(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**7) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["jcc"], 2) << 11 |
ins = ins | (imm >> 4) << 8 |
ins = ins | int(self.util.jcc_opcode["jna"], 2) << 4 |
ins = ins | (imm & 0x0f) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#jnbe_imm7. |
def exitJnbe_imm7(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**7) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["jcc"], 2) << 11 |
ins = ins | (imm >> 4) << 8 |
ins = ins | int(self.util.jcc_opcode["jnbe"], 2) << 4 |
ins = ins | (imm & 0x0f) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#ja_imm7. |
def exitJa_imm7(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**7) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["jcc"], 2) << 11 |
ins = ins | (imm >> 4) << 8 |
ins = ins | int(self.util.jcc_opcode["ja"], 2) << 4 |
ins = ins | (imm & 0x0f) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#js_imm7. |
def exitJs_imm7(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**7) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["jcc"], 2) << 11 |
ins = ins | (imm >> 4) << 8 |
ins = ins | int(self.util.jcc_opcode["js"], 2) << 4 |
ins = ins | (imm & 0x0f) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#jns_imm7. |
def exitJns_imm7(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**7) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["jcc"], 2) << 11 |
ins = ins | (imm >> 4) << 8 |
ins = ins | int(self.util.jcc_opcode["jns"], 2) << 4 |
ins = ins | (imm & 0x0f) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#jl_imm7. |
def exitJl_imm7(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**7) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["jcc"], 2) << 11 |
ins = ins | (imm >> 4) << 8 |
ins = ins | int(self.util.jcc_opcode["jl"], 2) << 4 |
ins = ins | (imm & 0x0f) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#jnge_imm7. |
def exitJnge_imm7(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**7) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["jcc"], 2) << 11 |
ins = ins | (imm >> 4) << 8 |
ins = ins | int(self.util.jcc_opcode["jnge"], 2) << 4 |
ins = ins | (imm & 0x0f) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#jnl_imm7. |
def exitJnl_imm7(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**7) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["jcc"], 2) << 11 |
ins = ins | (imm >> 4) << 8 |
ins = ins | int(self.util.jcc_opcode["jnl"], 2) << 4 |
ins = ins | (imm & 0x0f) |
self.util.write_ins(ins) |
|
|
# Exit a parse tree produced by HPC16Parser#jge_imm7. |
def exitJge_imm7(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**7) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["jcc"], 2) << 11 |
ins = ins | (imm >> 4) << 8 |
ins = ins | int(self.util.jcc_opcode["jge"], 2) << 4 |
ins = ins | (imm & 0x0f) |
self.util.write_ins(ins) |
|
|
# Exit a parse tree produced by HPC16Parser#jle_imm7. |
def exitJle_imm7(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**7) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["jcc"], 2) << 11 |
ins = ins | (imm >> 4) << 8 |
ins = ins | int(self.util.jcc_opcode["jle"], 2) << 4 |
ins = ins | (imm & 0x0f) |
self.util.write_ins(ins) |
|
|
# Exit a parse tree produced by HPC16Parser#jng_imm7. |
def exitJng_imm7(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**7) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["jcc"], 2) << 11 |
ins = ins | (imm >> 4) << 8 |
ins = ins | int(self.util.jcc_opcode["jng"], 2) << 4 |
ins = ins | (imm & 0x0f) |
self.util.write_ins(ins) |
|
|
# Exit a parse tree produced by HPC16Parser#jnle_imm7. |
def exitJnle_imm7(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**7) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["jcc"], 2) << 11 |
ins = ins | (imm >> 4) << 8 |
ins = ins | int(self.util.jcc_opcode["jnle"], 2) << 4 |
ins = ins | (imm & 0x0f) |
self.util.write_ins(ins) |
|
# Exit a parse tree produced by HPC16Parser#jg_imm7. |
def exitJg_imm7(self, ctx): |
err = False |
imm = self.util.get_imm_val(ctx.IMM().getText()) |
err = not self.util.vld_imm_val(imm, 2**7) |
if not err: |
ins = 0 |
ins = int(self.util.opcode["jcc"], 2) << 11 |
ins = ins | (imm >> 4) << 8 |
ins = ins | int(self.util.jcc_opcode["jg"], 2) << 4 |
ins = ins | (imm & 0x0f) |
self.util.write_ins(ins) |
|
|
/trunk/impl0/asm/HPC16Parser.py
0,0 → 1,3695
# Generated from HPC16.g4 by ANTLR 4.5.1 |
# encoding: utf-8 |
from __future__ import print_function |
from antlr4 import * |
from io import StringIO |
|
def serializedATN(): |
with StringIO() as buf: |
buf.write(u"\3\u0430\ud6d1\u8206\uad2d\u4417\uaef1\u8d80\uaadd\3") |
buf.write(u"R\u017b\4\2\t\2\4\3\t\3\4\4\t\4\3\2\6\2\n\n\2\r\2\16") |
buf.write(u"\2\13\3\3\5\3\17\n\3\3\3\3\3\3\4\3\4\3\4\3\4\3\4\3\4") |
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4") |
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4") |
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4") |
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4") |
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4") |
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4") |
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4") |
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4") |
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4") |
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4") |
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4") |
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4") |
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4") |
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4") |
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4") |
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4") |
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4") |
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4") |
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4") |
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4") |
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4") |
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4") |
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4") |
buf.write(u"\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4\3\4") |
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buf.write(u"\2\u0178\u014a\3\2\2\2\u0178\u014c\3\2\2\2\u0178\u014e") |
buf.write(u"\3\2\2\2\u0178\u0150\3\2\2\2\u0178\u0152\3\2\2\2\u0178") |
buf.write(u"\u0154\3\2\2\2\u0178\u0156\3\2\2\2\u0178\u0158\3\2\2") |
buf.write(u"\2\u0178\u015a\3\2\2\2\u0178\u015c\3\2\2\2\u0178\u015e") |
buf.write(u"\3\2\2\2\u0178\u0160\3\2\2\2\u0178\u0162\3\2\2\2\u0178") |
buf.write(u"\u0164\3\2\2\2\u0178\u0166\3\2\2\2\u0178\u0168\3\2\2") |
buf.write(u"\2\u0178\u016a\3\2\2\2\u0178\u016c\3\2\2\2\u0178\u016e") |
buf.write(u"\3\2\2\2\u0178\u0170\3\2\2\2\u0178\u0172\3\2\2\2\u0178") |
buf.write(u"\u0174\3\2\2\2\u0178\u0176\3\2\2\2\u0179\7\3\2\2\2\5") |
buf.write(u"\13\16\u0178") |
return buf.getvalue() |
|
|
class HPC16Parser ( Parser ): |
|
grammarFileName = "HPC16.g4" |
|
atn = ATNDeserializer().deserialize(serializedATN()) |
|
decisionsToDFA = [ DFA(ds, i) for i, ds in enumerate(atn.decisionToState) ] |
|
sharedContextCache = PredictionContextCache() |
|
literalNames = [ u"<INVALID>", u"'mov'", u"','", u"'ld'", u"'('", u"')'", |
u"'+'", u"'st'", u"'lbzx'", u"'lbsx'", u"'sb'", u"'li'", |
u"'inc'", u"'dec'", u"'sub'", u"'and'", u"'add'", u"'adc'", |
u"'sbb'", u"'or'", u"'xor'", u"'not'", u"'cmp'", u"'test'", |
u"'sll'", u"'slr'", u"'sal'", u"'sar'", u"'rol'", u"'ror'", |
u"'rcl'", u"'rcr'", u"'push'", u"'pushf'", u"'pop'", |
u"'popf'", u"'acall'", u"'call'", u"'ret'", u"'iret'", |
u"'clc'", u"'stc'", u"'cmc'", u"'cli'", u"'sti'", u"'int'", |
u"'into'", u"'ajmp'", u"'jmp'", u"'nop'", u"'hlt'", |
u"'jo'", u"'jno'", u"'jb'", u"'jnae'", u"'jnb'", u"'jae'", |
u"'je'", u"'jz'", u"'jne'", u"'jnz'", u"'jbe'", u"'jna'", |
u"'jnbe'", u"'ja'", u"'js'", u"'jns'", u"'jl'", u"'jnge'", |
u"'jnl'", u"'jge'", u"'jle'", u"'jng'", u"'jnle'", |
u"'jg'" ] |
|
symbolicNames = [ u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>", |
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>", |
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>", |
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>", |
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>", |
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>", |
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>", |
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>", |
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>", |
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>", |
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>", |
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>", |
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>", |
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>", |
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>", |
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>", |
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>", |
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"<INVALID>", |
u"<INVALID>", u"<INVALID>", u"<INVALID>", u"REG", |
u"IMM", u"STK_PTR", u"WS", u"LINE_COMMENT", u"NEWLINE" ] |
|
RULE_prog = 0 |
RULE_stat = 1 |
RULE_asm_inst = 2 |
|
ruleNames = [ u"prog", u"stat", u"asm_inst" ] |
|
EOF = Token.EOF |
T__0=1 |
T__1=2 |
T__2=3 |
T__3=4 |
T__4=5 |
T__5=6 |
T__6=7 |
T__7=8 |
T__8=9 |
T__9=10 |
T__10=11 |
T__11=12 |
T__12=13 |
T__13=14 |
T__14=15 |
T__15=16 |
T__16=17 |
T__17=18 |
T__18=19 |
T__19=20 |
T__20=21 |
T__21=22 |
T__22=23 |
T__23=24 |
T__24=25 |
T__25=26 |
T__26=27 |
T__27=28 |
T__28=29 |
T__29=30 |
T__30=31 |
T__31=32 |
T__32=33 |
T__33=34 |
T__34=35 |
T__35=36 |
T__36=37 |
T__37=38 |
T__38=39 |
T__39=40 |
T__40=41 |
T__41=42 |
T__42=43 |
T__43=44 |
T__44=45 |
T__45=46 |
T__46=47 |
T__47=48 |
T__48=49 |
T__49=50 |
T__50=51 |
T__51=52 |
T__52=53 |
T__53=54 |
T__54=55 |
T__55=56 |
T__56=57 |
T__57=58 |
T__58=59 |
T__59=60 |
T__60=61 |
T__61=62 |
T__62=63 |
T__63=64 |
T__64=65 |
T__65=66 |
T__66=67 |
T__67=68 |
T__68=69 |
T__69=70 |
T__70=71 |
T__71=72 |
T__72=73 |
T__73=74 |
REG=75 |
IMM=76 |
STK_PTR=77 |
WS=78 |
LINE_COMMENT=79 |
NEWLINE=80 |
|
def __init__(self, input): |
super(HPC16Parser, self).__init__(input) |
self.checkVersion("4.5.1") |
self._interp = ParserATNSimulator(self, self.atn, self.decisionsToDFA, self.sharedContextCache) |
self._predicates = None |
|
|
|
class ProgContext(ParserRuleContext): |
|
def __init__(self, parser, parent=None, invokingState=-1): |
super(HPC16Parser.ProgContext, self).__init__(parent, invokingState) |
self.parser = parser |
|
def stat(self, i=None): |
if i is None: |
return self.getTypedRuleContexts(HPC16Parser.StatContext) |
else: |
return self.getTypedRuleContext(HPC16Parser.StatContext,i) |
|
|
def getRuleIndex(self): |
return HPC16Parser.RULE_prog |
|
def enterRule(self, listener): |
if hasattr(listener, "enterProg"): |
listener.enterProg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitProg"): |
listener.exitProg(self) |
|
|
|
|
def prog(self): |
|
localctx = HPC16Parser.ProgContext(self, self._ctx, self.state) |
self.enterRule(localctx, 0, self.RULE_prog) |
self._la = 0 # Token type |
try: |
self.enterOuterAlt(localctx, 1) |
self.state = 7 |
self._errHandler.sync(self) |
_la = self._input.LA(1) |
while True: |
self.state = 6 |
self.stat() |
self.state = 9 |
self._errHandler.sync(self) |
_la = self._input.LA(1) |
if not ((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << HPC16Parser.T__0) | (1 << HPC16Parser.T__2) | (1 << HPC16Parser.T__6) | (1 << HPC16Parser.T__7) | (1 << HPC16Parser.T__8) | (1 << HPC16Parser.T__9) | (1 << HPC16Parser.T__10) | (1 << HPC16Parser.T__11) | (1 << HPC16Parser.T__12) | (1 << HPC16Parser.T__13) | (1 << HPC16Parser.T__14) | (1 << HPC16Parser.T__15) | (1 << HPC16Parser.T__16) | (1 << HPC16Parser.T__17) | (1 << HPC16Parser.T__18) | (1 << HPC16Parser.T__19) | (1 << HPC16Parser.T__20) | (1 << HPC16Parser.T__21) | (1 << HPC16Parser.T__22) | (1 << HPC16Parser.T__23) | (1 << HPC16Parser.T__24) | (1 << HPC16Parser.T__25) | (1 << HPC16Parser.T__26) | (1 << HPC16Parser.T__27) | (1 << HPC16Parser.T__28) | (1 << HPC16Parser.T__29) | (1 << HPC16Parser.T__30) | (1 << HPC16Parser.T__31) | (1 << HPC16Parser.T__32) | (1 << HPC16Parser.T__33) | (1 << HPC16Parser.T__34) | (1 << HPC16Parser.T__35) | (1 << HPC16Parser.T__36) | (1 << HPC16Parser.T__37) | (1 << HPC16Parser.T__38) | (1 << HPC16Parser.T__39) | (1 << HPC16Parser.T__40) | (1 << HPC16Parser.T__41) | (1 << HPC16Parser.T__42) | (1 << HPC16Parser.T__43) | (1 << HPC16Parser.T__44) | (1 << HPC16Parser.T__45) | (1 << HPC16Parser.T__46) | (1 << HPC16Parser.T__47) | (1 << HPC16Parser.T__48) | (1 << HPC16Parser.T__49) | (1 << HPC16Parser.T__50) | (1 << HPC16Parser.T__51) | (1 << HPC16Parser.T__52) | (1 << HPC16Parser.T__53) | (1 << HPC16Parser.T__54) | (1 << HPC16Parser.T__55) | (1 << HPC16Parser.T__56) | (1 << HPC16Parser.T__57) | (1 << HPC16Parser.T__58) | (1 << HPC16Parser.T__59) | (1 << HPC16Parser.T__60) | (1 << HPC16Parser.T__61) | (1 << HPC16Parser.T__62))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (HPC16Parser.T__63 - 64)) | (1 << (HPC16Parser.T__64 - 64)) | (1 << (HPC16Parser.T__65 - 64)) | (1 << (HPC16Parser.T__66 - 64)) | (1 << (HPC16Parser.T__67 - 64)) | (1 << (HPC16Parser.T__68 - 64)) | (1 << (HPC16Parser.T__69 - 64)) | (1 << (HPC16Parser.T__70 - 64)) | (1 << (HPC16Parser.T__71 - 64)) | (1 << (HPC16Parser.T__72 - 64)) | (1 << (HPC16Parser.T__73 - 64)) | (1 << (HPC16Parser.NEWLINE - 64)))) != 0)): |
break |
|
except RecognitionException as re: |
localctx.exception = re |
self._errHandler.reportError(self, re) |
self._errHandler.recover(self, re) |
finally: |
self.exitRule() |
return localctx |
|
class StatContext(ParserRuleContext): |
|
def __init__(self, parser, parent=None, invokingState=-1): |
super(HPC16Parser.StatContext, self).__init__(parent, invokingState) |
self.parser = parser |
|
def NEWLINE(self): |
return self.getToken(HPC16Parser.NEWLINE, 0) |
|
def asm_inst(self): |
return self.getTypedRuleContext(HPC16Parser.Asm_instContext,0) |
|
|
def getRuleIndex(self): |
return HPC16Parser.RULE_stat |
|
def enterRule(self, listener): |
if hasattr(listener, "enterStat"): |
listener.enterStat(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitStat"): |
listener.exitStat(self) |
|
|
|
|
def stat(self): |
|
localctx = HPC16Parser.StatContext(self, self._ctx, self.state) |
self.enterRule(localctx, 2, self.RULE_stat) |
self._la = 0 # Token type |
try: |
self.enterOuterAlt(localctx, 1) |
self.state = 12 |
_la = self._input.LA(1) |
if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << HPC16Parser.T__0) | (1 << HPC16Parser.T__2) | (1 << HPC16Parser.T__6) | (1 << HPC16Parser.T__7) | (1 << HPC16Parser.T__8) | (1 << HPC16Parser.T__9) | (1 << HPC16Parser.T__10) | (1 << HPC16Parser.T__11) | (1 << HPC16Parser.T__12) | (1 << HPC16Parser.T__13) | (1 << HPC16Parser.T__14) | (1 << HPC16Parser.T__15) | (1 << HPC16Parser.T__16) | (1 << HPC16Parser.T__17) | (1 << HPC16Parser.T__18) | (1 << HPC16Parser.T__19) | (1 << HPC16Parser.T__20) | (1 << HPC16Parser.T__21) | (1 << HPC16Parser.T__22) | (1 << HPC16Parser.T__23) | (1 << HPC16Parser.T__24) | (1 << HPC16Parser.T__25) | (1 << HPC16Parser.T__26) | (1 << HPC16Parser.T__27) | (1 << HPC16Parser.T__28) | (1 << HPC16Parser.T__29) | (1 << HPC16Parser.T__30) | (1 << HPC16Parser.T__31) | (1 << HPC16Parser.T__32) | (1 << HPC16Parser.T__33) | (1 << HPC16Parser.T__34) | (1 << HPC16Parser.T__35) | (1 << HPC16Parser.T__36) | (1 << HPC16Parser.T__37) | (1 << HPC16Parser.T__38) | (1 << HPC16Parser.T__39) | (1 << HPC16Parser.T__40) | (1 << HPC16Parser.T__41) | (1 << HPC16Parser.T__42) | (1 << HPC16Parser.T__43) | (1 << HPC16Parser.T__44) | (1 << HPC16Parser.T__45) | (1 << HPC16Parser.T__46) | (1 << HPC16Parser.T__47) | (1 << HPC16Parser.T__48) | (1 << HPC16Parser.T__49) | (1 << HPC16Parser.T__50) | (1 << HPC16Parser.T__51) | (1 << HPC16Parser.T__52) | (1 << HPC16Parser.T__53) | (1 << HPC16Parser.T__54) | (1 << HPC16Parser.T__55) | (1 << HPC16Parser.T__56) | (1 << HPC16Parser.T__57) | (1 << HPC16Parser.T__58) | (1 << HPC16Parser.T__59) | (1 << HPC16Parser.T__60) | (1 << HPC16Parser.T__61) | (1 << HPC16Parser.T__62))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (HPC16Parser.T__63 - 64)) | (1 << (HPC16Parser.T__64 - 64)) | (1 << (HPC16Parser.T__65 - 64)) | (1 << (HPC16Parser.T__66 - 64)) | (1 << (HPC16Parser.T__67 - 64)) | (1 << (HPC16Parser.T__68 - 64)) | (1 << (HPC16Parser.T__69 - 64)) | (1 << (HPC16Parser.T__70 - 64)) | (1 << (HPC16Parser.T__71 - 64)) | (1 << (HPC16Parser.T__72 - 64)) | (1 << (HPC16Parser.T__73 - 64)))) != 0): |
self.state = 11 |
self.asm_inst() |
|
|
self.state = 14 |
self.match(HPC16Parser.NEWLINE) |
except RecognitionException as re: |
localctx.exception = re |
self._errHandler.reportError(self, re) |
self._errHandler.recover(self, re) |
finally: |
self.exitRule() |
return localctx |
|
class Asm_instContext(ParserRuleContext): |
|
def __init__(self, parser, parent=None, invokingState=-1): |
super(HPC16Parser.Asm_instContext, self).__init__(parent, invokingState) |
self.parser = parser |
|
|
def getRuleIndex(self): |
return HPC16Parser.RULE_asm_inst |
|
|
def copyFrom(self, ctx): |
super(HPC16Parser.Asm_instContext, self).copyFrom(ctx) |
|
|
|
class Mov_reg_spContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Mov_reg_spContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
def STK_PTR(self): |
return self.getToken(HPC16Parser.STK_PTR, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterMov_reg_sp"): |
listener.enterMov_reg_sp(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitMov_reg_sp"): |
listener.exitMov_reg_sp(self) |
|
|
class Sb_reg_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Sb_reg_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self, i=None): |
if i is None: |
return self.getTokens(HPC16Parser.REG) |
else: |
return self.getToken(HPC16Parser.REG, i) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterSb_reg_reg"): |
listener.enterSb_reg_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitSb_reg_reg"): |
listener.exitSb_reg_reg(self) |
|
|
class PopfContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.PopfContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
|
def enterRule(self, listener): |
if hasattr(listener, "enterPopf"): |
listener.enterPopf(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitPopf"): |
listener.exitPopf(self) |
|
|
class Ld_reg_spContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Ld_reg_spContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
def STK_PTR(self): |
return self.getToken(HPC16Parser.STK_PTR, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterLd_reg_sp"): |
listener.enterLd_reg_sp(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitLd_reg_sp"): |
listener.exitLd_reg_sp(self) |
|
|
class Call_imm11Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Call_imm11Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterCall_imm11"): |
listener.enterCall_imm11(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitCall_imm11"): |
listener.exitCall_imm11(self) |
|
|
class Jge_imm7Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Jge_imm7Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterJge_imm7"): |
listener.enterJge_imm7(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitJge_imm7"): |
listener.exitJge_imm7(self) |
|
|
class St_reg_reg_imm16Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.St_reg_reg_imm16Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self, i=None): |
if i is None: |
return self.getTokens(HPC16Parser.REG) |
else: |
return self.getToken(HPC16Parser.REG, i) |
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterSt_reg_reg_imm16"): |
listener.enterSt_reg_reg_imm16(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitSt_reg_reg_imm16"): |
listener.exitSt_reg_reg_imm16(self) |
|
|
class Li_reg_imm16Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Li_reg_imm16Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterLi_reg_imm16"): |
listener.enterLi_reg_imm16(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitLi_reg_imm16"): |
listener.exitLi_reg_imm16(self) |
|
|
class Je_imm7Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Je_imm7Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterJe_imm7"): |
listener.enterJe_imm7(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitJe_imm7"): |
listener.exitJe_imm7(self) |
|
|
class Push_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Push_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterPush_reg"): |
listener.enterPush_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitPush_reg"): |
listener.exitPush_reg(self) |
|
|
class Sll_reg_imm4Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Sll_reg_imm4Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterSll_reg_imm4"): |
listener.enterSll_reg_imm4(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitSll_reg_imm4"): |
listener.exitSll_reg_imm4(self) |
|
|
class Slr_reg_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Slr_reg_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self, i=None): |
if i is None: |
return self.getTokens(HPC16Parser.REG) |
else: |
return self.getToken(HPC16Parser.REG, i) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterSlr_reg_reg"): |
listener.enterSlr_reg_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitSlr_reg_reg"): |
listener.exitSlr_reg_reg(self) |
|
|
class ClcContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.ClcContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
|
def enterRule(self, listener): |
if hasattr(listener, "enterClc"): |
listener.enterClc(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitClc"): |
listener.exitClc(self) |
|
|
class Jnae_imm7Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Jnae_imm7Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterJnae_imm7"): |
listener.enterJnae_imm7(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitJnae_imm7"): |
listener.exitJnae_imm7(self) |
|
|
class CliContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.CliContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
|
def enterRule(self, listener): |
if hasattr(listener, "enterCli"): |
listener.enterCli(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitCli"): |
listener.exitCli(self) |
|
|
class Jae_imm7Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Jae_imm7Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterJae_imm7"): |
listener.enterJae_imm7(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitJae_imm7"): |
listener.exitJae_imm7(self) |
|
|
class StcContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.StcContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
|
def enterRule(self, listener): |
if hasattr(listener, "enterStc"): |
listener.enterStc(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitStc"): |
listener.exitStc(self) |
|
|
class Jnl_imm7Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Jnl_imm7Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterJnl_imm7"): |
listener.enterJnl_imm7(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitJnl_imm7"): |
listener.exitJnl_imm7(self) |
|
|
class Ror_reg_imm4Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Ror_reg_imm4Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterRor_reg_imm4"): |
listener.enterRor_reg_imm4(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitRor_reg_imm4"): |
listener.exitRor_reg_imm4(self) |
|
|
class StiContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.StiContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
|
def enterRule(self, listener): |
if hasattr(listener, "enterSti"): |
listener.enterSti(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitSti"): |
listener.exitSti(self) |
|
|
class Cmp_reg_imm16Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Cmp_reg_imm16Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterCmp_reg_imm16"): |
listener.enterCmp_reg_imm16(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitCmp_reg_imm16"): |
listener.exitCmp_reg_imm16(self) |
|
|
class Jnle_imm7Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Jnle_imm7Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterJnle_imm7"): |
listener.enterJnle_imm7(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitJnle_imm7"): |
listener.exitJnle_imm7(self) |
|
|
class Rol_reg_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Rol_reg_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self, i=None): |
if i is None: |
return self.getTokens(HPC16Parser.REG) |
else: |
return self.getToken(HPC16Parser.REG, i) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterRol_reg_reg"): |
listener.enterRol_reg_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitRol_reg_reg"): |
listener.exitRol_reg_reg(self) |
|
|
class Slr_reg_imm4Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Slr_reg_imm4Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterSlr_reg_imm4"): |
listener.enterSlr_reg_imm4(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitSlr_reg_imm4"): |
listener.exitSlr_reg_imm4(self) |
|
|
class Mov_reg_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Mov_reg_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self, i=None): |
if i is None: |
return self.getTokens(HPC16Parser.REG) |
else: |
return self.getToken(HPC16Parser.REG, i) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterMov_reg_reg"): |
listener.enterMov_reg_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitMov_reg_reg"): |
listener.exitMov_reg_reg(self) |
|
|
class Li_sp_imm16Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Li_sp_imm16Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def STK_PTR(self): |
return self.getToken(HPC16Parser.STK_PTR, 0) |
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterLi_sp_imm16"): |
listener.enterLi_sp_imm16(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitLi_sp_imm16"): |
listener.exitLi_sp_imm16(self) |
|
|
class Rol_reg_imm4Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Rol_reg_imm4Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterRol_reg_imm4"): |
listener.enterRol_reg_imm4(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitRol_reg_imm4"): |
listener.exitRol_reg_imm4(self) |
|
|
class And_reg_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.And_reg_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self, i=None): |
if i is None: |
return self.getTokens(HPC16Parser.REG) |
else: |
return self.getToken(HPC16Parser.REG, i) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterAnd_reg_reg"): |
listener.enterAnd_reg_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitAnd_reg_reg"): |
listener.exitAnd_reg_reg(self) |
|
|
class CmcContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.CmcContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
|
def enterRule(self, listener): |
if hasattr(listener, "enterCmc"): |
listener.enterCmc(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitCmc"): |
listener.exitCmc(self) |
|
|
class Js_imm7Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Js_imm7Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterJs_imm7"): |
listener.enterJs_imm7(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitJs_imm7"): |
listener.exitJs_imm7(self) |
|
|
class Acall_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Acall_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterAcall_reg"): |
listener.enterAcall_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitAcall_reg"): |
listener.exitAcall_reg(self) |
|
|
class Dec_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Dec_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterDec_reg"): |
listener.enterDec_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitDec_reg"): |
listener.exitDec_reg(self) |
|
|
class Test_reg_imm16Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Test_reg_imm16Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterTest_reg_imm16"): |
listener.enterTest_reg_imm16(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitTest_reg_imm16"): |
listener.exitTest_reg_imm16(self) |
|
|
class And_reg_imm16Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.And_reg_imm16Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterAnd_reg_imm16"): |
listener.enterAnd_reg_imm16(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitAnd_reg_imm16"): |
listener.exitAnd_reg_imm16(self) |
|
|
class Sbb_reg_imm16Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Sbb_reg_imm16Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterSbb_reg_imm16"): |
listener.enterSbb_reg_imm16(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitSbb_reg_imm16"): |
listener.exitSbb_reg_imm16(self) |
|
|
class Jbe_imm7Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Jbe_imm7Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterJbe_imm7"): |
listener.enterJbe_imm7(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitJbe_imm7"): |
listener.exitJbe_imm7(self) |
|
|
class Xor_reg_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Xor_reg_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self, i=None): |
if i is None: |
return self.getTokens(HPC16Parser.REG) |
else: |
return self.getToken(HPC16Parser.REG, i) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterXor_reg_reg"): |
listener.enterXor_reg_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitXor_reg_reg"): |
listener.exitXor_reg_reg(self) |
|
|
class Jmp_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Jmp_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterJmp_reg"): |
listener.enterJmp_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitJmp_reg"): |
listener.exitJmp_reg(self) |
|
|
class Sbb_reg_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Sbb_reg_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self, i=None): |
if i is None: |
return self.getTokens(HPC16Parser.REG) |
else: |
return self.getToken(HPC16Parser.REG, i) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterSbb_reg_reg"): |
listener.enterSbb_reg_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitSbb_reg_reg"): |
listener.exitSbb_reg_reg(self) |
|
|
class IntoContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.IntoContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
|
def enterRule(self, listener): |
if hasattr(listener, "enterInto"): |
listener.enterInto(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitInto"): |
listener.exitInto(self) |
|
|
class Lbsx_reg_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Lbsx_reg_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self, i=None): |
if i is None: |
return self.getTokens(HPC16Parser.REG) |
else: |
return self.getToken(HPC16Parser.REG, i) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterLbsx_reg_reg"): |
listener.enterLbsx_reg_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitLbsx_reg_reg"): |
listener.exitLbsx_reg_reg(self) |
|
|
class St_reg_sp_imm16Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.St_reg_sp_imm16Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
def STK_PTR(self): |
return self.getToken(HPC16Parser.STK_PTR, 0) |
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterSt_reg_sp_imm16"): |
listener.enterSt_reg_sp_imm16(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitSt_reg_sp_imm16"): |
listener.exitSt_reg_sp_imm16(self) |
|
|
class Ld_reg_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Ld_reg_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self, i=None): |
if i is None: |
return self.getTokens(HPC16Parser.REG) |
else: |
return self.getToken(HPC16Parser.REG, i) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterLd_reg_reg"): |
listener.enterLd_reg_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitLd_reg_reg"): |
listener.exitLd_reg_reg(self) |
|
|
class Jnb_imm7Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Jnb_imm7Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterJnb_imm7"): |
listener.enterJnb_imm7(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitJnb_imm7"): |
listener.exitJnb_imm7(self) |
|
|
class Sar_reg_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Sar_reg_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self, i=None): |
if i is None: |
return self.getTokens(HPC16Parser.REG) |
else: |
return self.getToken(HPC16Parser.REG, i) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterSar_reg_reg"): |
listener.enterSar_reg_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitSar_reg_reg"): |
listener.exitSar_reg_reg(self) |
|
|
class Jo_imm7Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Jo_imm7Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterJo_imm7"): |
listener.enterJo_imm7(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitJo_imm7"): |
listener.exitJo_imm7(self) |
|
|
class Jl_imm7Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Jl_imm7Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterJl_imm7"): |
listener.enterJl_imm7(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitJl_imm7"): |
listener.exitJl_imm7(self) |
|
|
class Inc_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Inc_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterInc_reg"): |
listener.enterInc_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitInc_reg"): |
listener.exitInc_reg(self) |
|
|
class Jmp_imm11Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Jmp_imm11Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterJmp_imm11"): |
listener.enterJmp_imm11(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitJmp_imm11"): |
listener.exitJmp_imm11(self) |
|
|
class HaltContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.HaltContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
|
def enterRule(self, listener): |
if hasattr(listener, "enterHalt"): |
listener.enterHalt(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitHalt"): |
listener.exitHalt(self) |
|
|
class Rcr_reg_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Rcr_reg_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self, i=None): |
if i is None: |
return self.getTokens(HPC16Parser.REG) |
else: |
return self.getToken(HPC16Parser.REG, i) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterRcr_reg_reg"): |
listener.enterRcr_reg_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitRcr_reg_reg"): |
listener.exitRcr_reg_reg(self) |
|
|
class Lbzx_reg_reg_imm16Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Lbzx_reg_reg_imm16Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self, i=None): |
if i is None: |
return self.getTokens(HPC16Parser.REG) |
else: |
return self.getToken(HPC16Parser.REG, i) |
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterLbzx_reg_reg_imm16"): |
listener.enterLbzx_reg_reg_imm16(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitLbzx_reg_reg_imm16"): |
listener.exitLbzx_reg_reg_imm16(self) |
|
|
class Int_imm4Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Int_imm4Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterInt_imm4"): |
listener.enterInt_imm4(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitInt_imm4"): |
listener.exitInt_imm4(self) |
|
|
class Rcl_reg_imm4Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Rcl_reg_imm4Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterRcl_reg_imm4"): |
listener.enterRcl_reg_imm4(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitRcl_reg_imm4"): |
listener.exitRcl_reg_imm4(self) |
|
|
class Sll_reg_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Sll_reg_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self, i=None): |
if i is None: |
return self.getTokens(HPC16Parser.REG) |
else: |
return self.getToken(HPC16Parser.REG, i) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterSll_reg_reg"): |
listener.enterSll_reg_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitSll_reg_reg"): |
listener.exitSll_reg_reg(self) |
|
|
class Jne_imm7Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Jne_imm7Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterJne_imm7"): |
listener.enterJne_imm7(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitJne_imm7"): |
listener.exitJne_imm7(self) |
|
|
class Lbzx_reg_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Lbzx_reg_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self, i=None): |
if i is None: |
return self.getTokens(HPC16Parser.REG) |
else: |
return self.getToken(HPC16Parser.REG, i) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterLbzx_reg_reg"): |
listener.enterLbzx_reg_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitLbzx_reg_reg"): |
listener.exitLbzx_reg_reg(self) |
|
|
class Rcr_reg_imm4Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Rcr_reg_imm4Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterRcr_reg_imm4"): |
listener.enterRcr_reg_imm4(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitRcr_reg_imm4"): |
listener.exitRcr_reg_imm4(self) |
|
|
class Sar_reg_imm4Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Sar_reg_imm4Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterSar_reg_imm4"): |
listener.enterSar_reg_imm4(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitSar_reg_imm4"): |
listener.exitSar_reg_imm4(self) |
|
|
class Call_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Call_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterCall_reg"): |
listener.enterCall_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitCall_reg"): |
listener.exitCall_reg(self) |
|
|
class Lbsx_reg_reg_imm16Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Lbsx_reg_reg_imm16Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self, i=None): |
if i is None: |
return self.getTokens(HPC16Parser.REG) |
else: |
return self.getToken(HPC16Parser.REG, i) |
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterLbsx_reg_reg_imm16"): |
listener.enterLbsx_reg_reg_imm16(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitLbsx_reg_reg_imm16"): |
listener.exitLbsx_reg_reg_imm16(self) |
|
|
class Add_reg_imm16Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Add_reg_imm16Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterAdd_reg_imm16"): |
listener.enterAdd_reg_imm16(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitAdd_reg_imm16"): |
listener.exitAdd_reg_imm16(self) |
|
|
class Ror_reg_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Ror_reg_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self, i=None): |
if i is None: |
return self.getTokens(HPC16Parser.REG) |
else: |
return self.getToken(HPC16Parser.REG, i) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterRor_reg_reg"): |
listener.enterRor_reg_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitRor_reg_reg"): |
listener.exitRor_reg_reg(self) |
|
|
class Add_reg_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Add_reg_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self, i=None): |
if i is None: |
return self.getTokens(HPC16Parser.REG) |
else: |
return self.getToken(HPC16Parser.REG, i) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterAdd_reg_reg"): |
listener.enterAdd_reg_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitAdd_reg_reg"): |
listener.exitAdd_reg_reg(self) |
|
|
class Or_reg_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Or_reg_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self, i=None): |
if i is None: |
return self.getTokens(HPC16Parser.REG) |
else: |
return self.getToken(HPC16Parser.REG, i) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterOr_reg_reg"): |
listener.enterOr_reg_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitOr_reg_reg"): |
listener.exitOr_reg_reg(self) |
|
|
class Add_sp_imm16Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Add_sp_imm16Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def STK_PTR(self): |
return self.getToken(HPC16Parser.STK_PTR, 0) |
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterAdd_sp_imm16"): |
listener.enterAdd_sp_imm16(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitAdd_sp_imm16"): |
listener.exitAdd_sp_imm16(self) |
|
|
class Ld_reg_reg_imm16Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Ld_reg_reg_imm16Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self, i=None): |
if i is None: |
return self.getTokens(HPC16Parser.REG) |
else: |
return self.getToken(HPC16Parser.REG, i) |
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterLd_reg_reg_imm16"): |
listener.enterLd_reg_reg_imm16(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitLd_reg_reg_imm16"): |
listener.exitLd_reg_reg_imm16(self) |
|
|
class Cmp_reg_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Cmp_reg_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self, i=None): |
if i is None: |
return self.getTokens(HPC16Parser.REG) |
else: |
return self.getToken(HPC16Parser.REG, i) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterCmp_reg_reg"): |
listener.enterCmp_reg_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitCmp_reg_reg"): |
listener.exitCmp_reg_reg(self) |
|
|
class RetContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.RetContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
|
def enterRule(self, listener): |
if hasattr(listener, "enterRet"): |
listener.enterRet(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitRet"): |
listener.exitRet(self) |
|
|
class Adc_reg_imm16Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Adc_reg_imm16Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterAdc_reg_imm16"): |
listener.enterAdc_reg_imm16(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitAdc_reg_imm16"): |
listener.exitAdc_reg_imm16(self) |
|
|
class AjmpContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.AjmpContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterAjmp"): |
listener.enterAjmp(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitAjmp"): |
listener.exitAjmp(self) |
|
|
class Jno_imm7Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Jno_imm7Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterJno_imm7"): |
listener.enterJno_imm7(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitJno_imm7"): |
listener.exitJno_imm7(self) |
|
|
class Sub_sp_imm16Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Sub_sp_imm16Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def STK_PTR(self): |
return self.getToken(HPC16Parser.STK_PTR, 0) |
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterSub_sp_imm16"): |
listener.enterSub_sp_imm16(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitSub_sp_imm16"): |
listener.exitSub_sp_imm16(self) |
|
|
class IretContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.IretContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
|
def enterRule(self, listener): |
if hasattr(listener, "enterIret"): |
listener.enterIret(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitIret"): |
listener.exitIret(self) |
|
|
class Sub_reg_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Sub_reg_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self, i=None): |
if i is None: |
return self.getTokens(HPC16Parser.REG) |
else: |
return self.getToken(HPC16Parser.REG, i) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterSub_reg_reg"): |
listener.enterSub_reg_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitSub_reg_reg"): |
listener.exitSub_reg_reg(self) |
|
|
class Jnz_imm7Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Jnz_imm7Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterJnz_imm7"): |
listener.enterJnz_imm7(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitJnz_imm7"): |
listener.exitJnz_imm7(self) |
|
|
class Sal_reg_imm4Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Sal_reg_imm4Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterSal_reg_imm4"): |
listener.enterSal_reg_imm4(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitSal_reg_imm4"): |
listener.exitSal_reg_imm4(self) |
|
|
class Jnbe_imm7Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Jnbe_imm7Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterJnbe_imm7"): |
listener.enterJnbe_imm7(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitJnbe_imm7"): |
listener.exitJnbe_imm7(self) |
|
|
class Test_reg_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Test_reg_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self, i=None): |
if i is None: |
return self.getTokens(HPC16Parser.REG) |
else: |
return self.getToken(HPC16Parser.REG, i) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterTest_reg_reg"): |
listener.enterTest_reg_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitTest_reg_reg"): |
listener.exitTest_reg_reg(self) |
|
|
class Sal_reg_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Sal_reg_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self, i=None): |
if i is None: |
return self.getTokens(HPC16Parser.REG) |
else: |
return self.getToken(HPC16Parser.REG, i) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterSal_reg_reg"): |
listener.enterSal_reg_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitSal_reg_reg"): |
listener.exitSal_reg_reg(self) |
|
|
class Jle_imm7Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Jle_imm7Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterJle_imm7"): |
listener.enterJle_imm7(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitJle_imm7"): |
listener.exitJle_imm7(self) |
|
|
class St_reg_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.St_reg_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self, i=None): |
if i is None: |
return self.getTokens(HPC16Parser.REG) |
else: |
return self.getToken(HPC16Parser.REG, i) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterSt_reg_reg"): |
listener.enterSt_reg_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitSt_reg_reg"): |
listener.exitSt_reg_reg(self) |
|
|
class Xor_reg_imm16Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Xor_reg_imm16Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterXor_reg_imm16"): |
listener.enterXor_reg_imm16(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitXor_reg_imm16"): |
listener.exitXor_reg_imm16(self) |
|
|
class Jns_imm7Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Jns_imm7Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterJns_imm7"): |
listener.enterJns_imm7(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitJns_imm7"): |
listener.exitJns_imm7(self) |
|
|
class Not_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Not_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterNot_reg"): |
listener.enterNot_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitNot_reg"): |
listener.exitNot_reg(self) |
|
|
class NopContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.NopContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
|
def enterRule(self, listener): |
if hasattr(listener, "enterNop"): |
listener.enterNop(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitNop"): |
listener.exitNop(self) |
|
|
class Jb_imm7Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Jb_imm7Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterJb_imm7"): |
listener.enterJb_imm7(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitJb_imm7"): |
listener.exitJb_imm7(self) |
|
|
class Or_reg_imm16Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Or_reg_imm16Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterOr_reg_imm16"): |
listener.enterOr_reg_imm16(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitOr_reg_imm16"): |
listener.exitOr_reg_imm16(self) |
|
|
class Ja_imm7Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Ja_imm7Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterJa_imm7"): |
listener.enterJa_imm7(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitJa_imm7"): |
listener.exitJa_imm7(self) |
|
|
class Jg_imm7Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Jg_imm7Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterJg_imm7"): |
listener.enterJg_imm7(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitJg_imm7"): |
listener.exitJg_imm7(self) |
|
|
class Adc_reg_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Adc_reg_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self, i=None): |
if i is None: |
return self.getTokens(HPC16Parser.REG) |
else: |
return self.getToken(HPC16Parser.REG, i) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterAdc_reg_reg"): |
listener.enterAdc_reg_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitAdc_reg_reg"): |
listener.exitAdc_reg_reg(self) |
|
|
class Pop_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Pop_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterPop_reg"): |
listener.enterPop_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitPop_reg"): |
listener.exitPop_reg(self) |
|
|
class Rcl_reg_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Rcl_reg_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self, i=None): |
if i is None: |
return self.getTokens(HPC16Parser.REG) |
else: |
return self.getToken(HPC16Parser.REG, i) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterRcl_reg_reg"): |
listener.enterRcl_reg_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitRcl_reg_reg"): |
listener.exitRcl_reg_reg(self) |
|
|
class Sub_reg_imm16Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Sub_reg_imm16Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterSub_reg_imm16"): |
listener.enterSub_reg_imm16(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitSub_reg_imm16"): |
listener.exitSub_reg_imm16(self) |
|
|
class Jna_imm7Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Jna_imm7Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterJna_imm7"): |
listener.enterJna_imm7(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitJna_imm7"): |
listener.exitJna_imm7(self) |
|
|
class Ld_reg_sp_imm16Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Ld_reg_sp_imm16Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
def STK_PTR(self): |
return self.getToken(HPC16Parser.STK_PTR, 0) |
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterLd_reg_sp_imm16"): |
listener.enterLd_reg_sp_imm16(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitLd_reg_sp_imm16"): |
listener.exitLd_reg_sp_imm16(self) |
|
|
class PushfContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.PushfContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
|
def enterRule(self, listener): |
if hasattr(listener, "enterPushf"): |
listener.enterPushf(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitPushf"): |
listener.exitPushf(self) |
|
|
class Jz_imm7Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Jz_imm7Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterJz_imm7"): |
listener.enterJz_imm7(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitJz_imm7"): |
listener.exitJz_imm7(self) |
|
|
class Jng_imm7Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Jng_imm7Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterJng_imm7"): |
listener.enterJng_imm7(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitJng_imm7"): |
listener.exitJng_imm7(self) |
|
|
class Jnge_imm7Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Jnge_imm7Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterJnge_imm7"): |
listener.enterJnge_imm7(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitJnge_imm7"): |
listener.exitJnge_imm7(self) |
|
|
class St_reg_spContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.St_reg_spContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
def STK_PTR(self): |
return self.getToken(HPC16Parser.STK_PTR, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterSt_reg_sp"): |
listener.enterSt_reg_sp(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitSt_reg_sp"): |
listener.exitSt_reg_sp(self) |
|
|
class Sb_reg_reg_imm16Context(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Sb_reg_reg_imm16Context, self).__init__(parser) |
self.copyFrom(ctx) |
|
def REG(self, i=None): |
if i is None: |
return self.getTokens(HPC16Parser.REG) |
else: |
return self.getToken(HPC16Parser.REG, i) |
def IMM(self): |
return self.getToken(HPC16Parser.IMM, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterSb_reg_reg_imm16"): |
listener.enterSb_reg_reg_imm16(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitSb_reg_reg_imm16"): |
listener.exitSb_reg_reg_imm16(self) |
|
|
class Mov_sp_regContext(Asm_instContext): |
|
def __init__(self, parser, ctx): # actually a HPC16Parser.Asm_instContext) |
super(HPC16Parser.Mov_sp_regContext, self).__init__(parser) |
self.copyFrom(ctx) |
|
def STK_PTR(self): |
return self.getToken(HPC16Parser.STK_PTR, 0) |
def REG(self): |
return self.getToken(HPC16Parser.REG, 0) |
|
def enterRule(self, listener): |
if hasattr(listener, "enterMov_sp_reg"): |
listener.enterMov_sp_reg(self) |
|
def exitRule(self, listener): |
if hasattr(listener, "exitMov_sp_reg"): |
listener.exitMov_sp_reg(self) |
|
|
|
def asm_inst(self): |
|
localctx = HPC16Parser.Asm_instContext(self, self._ctx, self.state) |
self.enterRule(localctx, 4, self.RULE_asm_inst) |
try: |
self.state = 374 |
la_ = self._interp.adaptivePredict(self._input,2,self._ctx) |
if la_ == 1: |
localctx = HPC16Parser.Mov_reg_regContext(self, localctx) |
self.enterOuterAlt(localctx, 1) |
self.state = 16 |
self.match(HPC16Parser.T__0) |
self.state = 17 |
self.match(HPC16Parser.REG) |
self.state = 18 |
self.match(HPC16Parser.T__1) |
self.state = 19 |
self.match(HPC16Parser.REG) |
pass |
|
elif la_ == 2: |
localctx = HPC16Parser.Mov_sp_regContext(self, localctx) |
self.enterOuterAlt(localctx, 2) |
self.state = 20 |
self.match(HPC16Parser.T__0) |
self.state = 21 |
self.match(HPC16Parser.STK_PTR) |
self.state = 22 |
self.match(HPC16Parser.T__1) |
self.state = 23 |
self.match(HPC16Parser.REG) |
pass |
|
elif la_ == 3: |
localctx = HPC16Parser.Mov_reg_spContext(self, localctx) |
self.enterOuterAlt(localctx, 3) |
self.state = 24 |
self.match(HPC16Parser.T__0) |
self.state = 25 |
self.match(HPC16Parser.REG) |
self.state = 26 |
self.match(HPC16Parser.T__1) |
self.state = 27 |
self.match(HPC16Parser.STK_PTR) |
pass |
|
elif la_ == 4: |
localctx = HPC16Parser.Ld_reg_regContext(self, localctx) |
self.enterOuterAlt(localctx, 4) |
self.state = 28 |
self.match(HPC16Parser.T__2) |
self.state = 29 |
self.match(HPC16Parser.REG) |
self.state = 30 |
self.match(HPC16Parser.T__1) |
self.state = 31 |
self.match(HPC16Parser.T__3) |
self.state = 32 |
self.match(HPC16Parser.REG) |
self.state = 33 |
self.match(HPC16Parser.T__4) |
pass |
|
elif la_ == 5: |
localctx = HPC16Parser.Ld_reg_reg_imm16Context(self, localctx) |
self.enterOuterAlt(localctx, 5) |
self.state = 34 |
self.match(HPC16Parser.T__2) |
self.state = 35 |
self.match(HPC16Parser.REG) |
self.state = 36 |
self.match(HPC16Parser.T__1) |
self.state = 37 |
self.match(HPC16Parser.T__3) |
self.state = 38 |
self.match(HPC16Parser.REG) |
self.state = 39 |
self.match(HPC16Parser.T__5) |
self.state = 40 |
self.match(HPC16Parser.IMM) |
self.state = 41 |
self.match(HPC16Parser.T__4) |
pass |
|
elif la_ == 6: |
localctx = HPC16Parser.Ld_reg_spContext(self, localctx) |
self.enterOuterAlt(localctx, 6) |
self.state = 42 |
self.match(HPC16Parser.T__2) |
self.state = 43 |
self.match(HPC16Parser.REG) |
self.state = 44 |
self.match(HPC16Parser.T__1) |
self.state = 45 |
self.match(HPC16Parser.T__3) |
self.state = 46 |
self.match(HPC16Parser.STK_PTR) |
self.state = 47 |
self.match(HPC16Parser.T__4) |
pass |
|
elif la_ == 7: |
localctx = HPC16Parser.Ld_reg_sp_imm16Context(self, localctx) |
self.enterOuterAlt(localctx, 7) |
self.state = 48 |
self.match(HPC16Parser.T__2) |
self.state = 49 |
self.match(HPC16Parser.REG) |
self.state = 50 |
self.match(HPC16Parser.T__1) |
self.state = 51 |
self.match(HPC16Parser.T__3) |
self.state = 52 |
self.match(HPC16Parser.STK_PTR) |
self.state = 53 |
self.match(HPC16Parser.T__5) |
self.state = 54 |
self.match(HPC16Parser.IMM) |
self.state = 55 |
self.match(HPC16Parser.T__4) |
pass |
|
elif la_ == 8: |
localctx = HPC16Parser.St_reg_regContext(self, localctx) |
self.enterOuterAlt(localctx, 8) |
self.state = 56 |
self.match(HPC16Parser.T__6) |
self.state = 57 |
self.match(HPC16Parser.REG) |
self.state = 58 |
self.match(HPC16Parser.T__1) |
self.state = 59 |
self.match(HPC16Parser.T__3) |
self.state = 60 |
self.match(HPC16Parser.REG) |
self.state = 61 |
self.match(HPC16Parser.T__4) |
pass |
|
elif la_ == 9: |
localctx = HPC16Parser.St_reg_reg_imm16Context(self, localctx) |
self.enterOuterAlt(localctx, 9) |
self.state = 62 |
self.match(HPC16Parser.T__6) |
self.state = 63 |
self.match(HPC16Parser.REG) |
self.state = 64 |
self.match(HPC16Parser.T__1) |
self.state = 65 |
self.match(HPC16Parser.T__3) |
self.state = 66 |
self.match(HPC16Parser.REG) |
self.state = 67 |
self.match(HPC16Parser.T__5) |
self.state = 68 |
self.match(HPC16Parser.IMM) |
self.state = 69 |
self.match(HPC16Parser.T__4) |
pass |
|
elif la_ == 10: |
localctx = HPC16Parser.St_reg_spContext(self, localctx) |
self.enterOuterAlt(localctx, 10) |
self.state = 70 |
self.match(HPC16Parser.T__6) |
self.state = 71 |
self.match(HPC16Parser.REG) |
self.state = 72 |
self.match(HPC16Parser.T__1) |
self.state = 73 |
self.match(HPC16Parser.T__3) |
self.state = 74 |
self.match(HPC16Parser.STK_PTR) |
self.state = 75 |
self.match(HPC16Parser.T__4) |
pass |
|
elif la_ == 11: |
localctx = HPC16Parser.St_reg_sp_imm16Context(self, localctx) |
self.enterOuterAlt(localctx, 11) |
self.state = 76 |
self.match(HPC16Parser.T__6) |
self.state = 77 |
self.match(HPC16Parser.REG) |
self.state = 78 |
self.match(HPC16Parser.T__1) |
self.state = 79 |
self.match(HPC16Parser.T__3) |
self.state = 80 |
self.match(HPC16Parser.STK_PTR) |
self.state = 81 |
self.match(HPC16Parser.T__5) |
self.state = 82 |
self.match(HPC16Parser.IMM) |
self.state = 83 |
self.match(HPC16Parser.T__4) |
pass |
|
elif la_ == 12: |
localctx = HPC16Parser.Lbzx_reg_regContext(self, localctx) |
self.enterOuterAlt(localctx, 12) |
self.state = 84 |
self.match(HPC16Parser.T__7) |
self.state = 85 |
self.match(HPC16Parser.REG) |
self.state = 86 |
self.match(HPC16Parser.T__1) |
self.state = 87 |
self.match(HPC16Parser.T__3) |
self.state = 88 |
self.match(HPC16Parser.REG) |
self.state = 89 |
self.match(HPC16Parser.T__4) |
pass |
|
elif la_ == 13: |
localctx = HPC16Parser.Lbzx_reg_reg_imm16Context(self, localctx) |
self.enterOuterAlt(localctx, 13) |
self.state = 90 |
self.match(HPC16Parser.T__7) |
self.state = 91 |
self.match(HPC16Parser.REG) |
self.state = 92 |
self.match(HPC16Parser.T__1) |
self.state = 93 |
self.match(HPC16Parser.T__3) |
self.state = 94 |
self.match(HPC16Parser.REG) |
self.state = 95 |
self.match(HPC16Parser.T__5) |
self.state = 96 |
self.match(HPC16Parser.IMM) |
self.state = 97 |
self.match(HPC16Parser.T__4) |
pass |
|
elif la_ == 14: |
localctx = HPC16Parser.Lbsx_reg_regContext(self, localctx) |
self.enterOuterAlt(localctx, 14) |
self.state = 98 |
self.match(HPC16Parser.T__8) |
self.state = 99 |
self.match(HPC16Parser.REG) |
self.state = 100 |
self.match(HPC16Parser.T__1) |
self.state = 101 |
self.match(HPC16Parser.T__3) |
self.state = 102 |
self.match(HPC16Parser.REG) |
self.state = 103 |
self.match(HPC16Parser.T__4) |
pass |
|
elif la_ == 15: |
localctx = HPC16Parser.Lbsx_reg_reg_imm16Context(self, localctx) |
self.enterOuterAlt(localctx, 15) |
self.state = 104 |
self.match(HPC16Parser.T__8) |
self.state = 105 |
self.match(HPC16Parser.REG) |
self.state = 106 |
self.match(HPC16Parser.T__1) |
self.state = 107 |
self.match(HPC16Parser.T__3) |
self.state = 108 |
self.match(HPC16Parser.REG) |
self.state = 109 |
self.match(HPC16Parser.T__5) |
self.state = 110 |
self.match(HPC16Parser.IMM) |
self.state = 111 |
self.match(HPC16Parser.T__4) |
pass |
|
elif la_ == 16: |
localctx = HPC16Parser.Sb_reg_regContext(self, localctx) |
self.enterOuterAlt(localctx, 16) |
self.state = 112 |
self.match(HPC16Parser.T__9) |
self.state = 113 |
self.match(HPC16Parser.REG) |
self.state = 114 |
self.match(HPC16Parser.T__1) |
self.state = 115 |
self.match(HPC16Parser.T__3) |
self.state = 116 |
self.match(HPC16Parser.REG) |
self.state = 117 |
self.match(HPC16Parser.T__4) |
pass |
|
elif la_ == 17: |
localctx = HPC16Parser.Sb_reg_reg_imm16Context(self, localctx) |
self.enterOuterAlt(localctx, 17) |
self.state = 118 |
self.match(HPC16Parser.T__9) |
self.state = 119 |
self.match(HPC16Parser.REG) |
self.state = 120 |
self.match(HPC16Parser.T__1) |
self.state = 121 |
self.match(HPC16Parser.T__3) |
self.state = 122 |
self.match(HPC16Parser.REG) |
self.state = 123 |
self.match(HPC16Parser.T__5) |
self.state = 124 |
self.match(HPC16Parser.IMM) |
self.state = 125 |
self.match(HPC16Parser.T__4) |
pass |
|
elif la_ == 18: |
localctx = HPC16Parser.Li_reg_imm16Context(self, localctx) |
self.enterOuterAlt(localctx, 18) |
self.state = 126 |
self.match(HPC16Parser.T__10) |
self.state = 127 |
self.match(HPC16Parser.REG) |
self.state = 128 |
self.match(HPC16Parser.T__1) |
self.state = 129 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 19: |
localctx = HPC16Parser.Li_sp_imm16Context(self, localctx) |
self.enterOuterAlt(localctx, 19) |
self.state = 130 |
self.match(HPC16Parser.T__10) |
self.state = 131 |
self.match(HPC16Parser.STK_PTR) |
self.state = 132 |
self.match(HPC16Parser.T__1) |
self.state = 133 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 20: |
localctx = HPC16Parser.Inc_regContext(self, localctx) |
self.enterOuterAlt(localctx, 20) |
self.state = 134 |
self.match(HPC16Parser.T__11) |
self.state = 135 |
self.match(HPC16Parser.REG) |
pass |
|
elif la_ == 21: |
localctx = HPC16Parser.Dec_regContext(self, localctx) |
self.enterOuterAlt(localctx, 21) |
self.state = 136 |
self.match(HPC16Parser.T__12) |
self.state = 137 |
self.match(HPC16Parser.REG) |
pass |
|
elif la_ == 22: |
localctx = HPC16Parser.Sub_reg_regContext(self, localctx) |
self.enterOuterAlt(localctx, 22) |
self.state = 138 |
self.match(HPC16Parser.T__13) |
self.state = 139 |
self.match(HPC16Parser.REG) |
self.state = 140 |
self.match(HPC16Parser.T__1) |
self.state = 141 |
self.match(HPC16Parser.REG) |
pass |
|
elif la_ == 23: |
localctx = HPC16Parser.And_reg_regContext(self, localctx) |
self.enterOuterAlt(localctx, 23) |
self.state = 142 |
self.match(HPC16Parser.T__14) |
self.state = 143 |
self.match(HPC16Parser.REG) |
self.state = 144 |
self.match(HPC16Parser.T__1) |
self.state = 145 |
self.match(HPC16Parser.REG) |
pass |
|
elif la_ == 24: |
localctx = HPC16Parser.Add_reg_regContext(self, localctx) |
self.enterOuterAlt(localctx, 24) |
self.state = 146 |
self.match(HPC16Parser.T__15) |
self.state = 147 |
self.match(HPC16Parser.REG) |
self.state = 148 |
self.match(HPC16Parser.T__1) |
self.state = 149 |
self.match(HPC16Parser.REG) |
pass |
|
elif la_ == 25: |
localctx = HPC16Parser.Adc_reg_regContext(self, localctx) |
self.enterOuterAlt(localctx, 25) |
self.state = 150 |
self.match(HPC16Parser.T__16) |
self.state = 151 |
self.match(HPC16Parser.REG) |
self.state = 152 |
self.match(HPC16Parser.T__1) |
self.state = 153 |
self.match(HPC16Parser.REG) |
pass |
|
elif la_ == 26: |
localctx = HPC16Parser.Sbb_reg_regContext(self, localctx) |
self.enterOuterAlt(localctx, 26) |
self.state = 154 |
self.match(HPC16Parser.T__17) |
self.state = 155 |
self.match(HPC16Parser.REG) |
self.state = 156 |
self.match(HPC16Parser.T__1) |
self.state = 157 |
self.match(HPC16Parser.REG) |
pass |
|
elif la_ == 27: |
localctx = HPC16Parser.Or_reg_regContext(self, localctx) |
self.enterOuterAlt(localctx, 27) |
self.state = 158 |
self.match(HPC16Parser.T__18) |
self.state = 159 |
self.match(HPC16Parser.REG) |
self.state = 160 |
self.match(HPC16Parser.T__1) |
self.state = 161 |
self.match(HPC16Parser.REG) |
pass |
|
elif la_ == 28: |
localctx = HPC16Parser.Xor_reg_regContext(self, localctx) |
self.enterOuterAlt(localctx, 28) |
self.state = 162 |
self.match(HPC16Parser.T__19) |
self.state = 163 |
self.match(HPC16Parser.REG) |
self.state = 164 |
self.match(HPC16Parser.T__1) |
self.state = 165 |
self.match(HPC16Parser.REG) |
pass |
|
elif la_ == 29: |
localctx = HPC16Parser.Not_regContext(self, localctx) |
self.enterOuterAlt(localctx, 29) |
self.state = 166 |
self.match(HPC16Parser.T__20) |
self.state = 167 |
self.match(HPC16Parser.REG) |
pass |
|
elif la_ == 30: |
localctx = HPC16Parser.Sub_reg_imm16Context(self, localctx) |
self.enterOuterAlt(localctx, 30) |
self.state = 168 |
self.match(HPC16Parser.T__13) |
self.state = 169 |
self.match(HPC16Parser.REG) |
self.state = 170 |
self.match(HPC16Parser.T__1) |
self.state = 171 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 31: |
localctx = HPC16Parser.And_reg_imm16Context(self, localctx) |
self.enterOuterAlt(localctx, 31) |
self.state = 172 |
self.match(HPC16Parser.T__14) |
self.state = 173 |
self.match(HPC16Parser.REG) |
self.state = 174 |
self.match(HPC16Parser.T__1) |
self.state = 175 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 32: |
localctx = HPC16Parser.Add_reg_imm16Context(self, localctx) |
self.enterOuterAlt(localctx, 32) |
self.state = 176 |
self.match(HPC16Parser.T__15) |
self.state = 177 |
self.match(HPC16Parser.REG) |
self.state = 178 |
self.match(HPC16Parser.T__1) |
self.state = 179 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 33: |
localctx = HPC16Parser.Adc_reg_imm16Context(self, localctx) |
self.enterOuterAlt(localctx, 33) |
self.state = 180 |
self.match(HPC16Parser.T__16) |
self.state = 181 |
self.match(HPC16Parser.REG) |
self.state = 182 |
self.match(HPC16Parser.T__1) |
self.state = 183 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 34: |
localctx = HPC16Parser.Sbb_reg_imm16Context(self, localctx) |
self.enterOuterAlt(localctx, 34) |
self.state = 184 |
self.match(HPC16Parser.T__17) |
self.state = 185 |
self.match(HPC16Parser.REG) |
self.state = 186 |
self.match(HPC16Parser.T__1) |
self.state = 187 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 35: |
localctx = HPC16Parser.Or_reg_imm16Context(self, localctx) |
self.enterOuterAlt(localctx, 35) |
self.state = 188 |
self.match(HPC16Parser.T__18) |
self.state = 189 |
self.match(HPC16Parser.REG) |
self.state = 190 |
self.match(HPC16Parser.T__1) |
self.state = 191 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 36: |
localctx = HPC16Parser.Xor_reg_imm16Context(self, localctx) |
self.enterOuterAlt(localctx, 36) |
self.state = 192 |
self.match(HPC16Parser.T__19) |
self.state = 193 |
self.match(HPC16Parser.REG) |
self.state = 194 |
self.match(HPC16Parser.T__1) |
self.state = 195 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 37: |
localctx = HPC16Parser.Add_sp_imm16Context(self, localctx) |
self.enterOuterAlt(localctx, 37) |
self.state = 196 |
self.match(HPC16Parser.T__15) |
self.state = 197 |
self.match(HPC16Parser.STK_PTR) |
self.state = 198 |
self.match(HPC16Parser.T__1) |
self.state = 199 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 38: |
localctx = HPC16Parser.Sub_sp_imm16Context(self, localctx) |
self.enterOuterAlt(localctx, 38) |
self.state = 200 |
self.match(HPC16Parser.T__13) |
self.state = 201 |
self.match(HPC16Parser.STK_PTR) |
self.state = 202 |
self.match(HPC16Parser.T__1) |
self.state = 203 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 39: |
localctx = HPC16Parser.Cmp_reg_regContext(self, localctx) |
self.enterOuterAlt(localctx, 39) |
self.state = 204 |
self.match(HPC16Parser.T__21) |
self.state = 205 |
self.match(HPC16Parser.REG) |
self.state = 206 |
self.match(HPC16Parser.T__1) |
self.state = 207 |
self.match(HPC16Parser.REG) |
pass |
|
elif la_ == 40: |
localctx = HPC16Parser.Test_reg_regContext(self, localctx) |
self.enterOuterAlt(localctx, 40) |
self.state = 208 |
self.match(HPC16Parser.T__22) |
self.state = 209 |
self.match(HPC16Parser.REG) |
self.state = 210 |
self.match(HPC16Parser.T__1) |
self.state = 211 |
self.match(HPC16Parser.REG) |
pass |
|
elif la_ == 41: |
localctx = HPC16Parser.Cmp_reg_imm16Context(self, localctx) |
self.enterOuterAlt(localctx, 41) |
self.state = 212 |
self.match(HPC16Parser.T__21) |
self.state = 213 |
self.match(HPC16Parser.REG) |
self.state = 214 |
self.match(HPC16Parser.T__1) |
self.state = 215 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 42: |
localctx = HPC16Parser.Test_reg_imm16Context(self, localctx) |
self.enterOuterAlt(localctx, 42) |
self.state = 216 |
self.match(HPC16Parser.T__22) |
self.state = 217 |
self.match(HPC16Parser.REG) |
self.state = 218 |
self.match(HPC16Parser.T__1) |
self.state = 219 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 43: |
localctx = HPC16Parser.Sll_reg_regContext(self, localctx) |
self.enterOuterAlt(localctx, 43) |
self.state = 220 |
self.match(HPC16Parser.T__23) |
self.state = 221 |
self.match(HPC16Parser.REG) |
self.state = 222 |
self.match(HPC16Parser.T__1) |
self.state = 223 |
self.match(HPC16Parser.REG) |
pass |
|
elif la_ == 44: |
localctx = HPC16Parser.Slr_reg_regContext(self, localctx) |
self.enterOuterAlt(localctx, 44) |
self.state = 224 |
self.match(HPC16Parser.T__24) |
self.state = 225 |
self.match(HPC16Parser.REG) |
self.state = 226 |
self.match(HPC16Parser.T__1) |
self.state = 227 |
self.match(HPC16Parser.REG) |
pass |
|
elif la_ == 45: |
localctx = HPC16Parser.Sal_reg_regContext(self, localctx) |
self.enterOuterAlt(localctx, 45) |
self.state = 228 |
self.match(HPC16Parser.T__25) |
self.state = 229 |
self.match(HPC16Parser.REG) |
self.state = 230 |
self.match(HPC16Parser.T__1) |
self.state = 231 |
self.match(HPC16Parser.REG) |
pass |
|
elif la_ == 46: |
localctx = HPC16Parser.Sar_reg_regContext(self, localctx) |
self.enterOuterAlt(localctx, 46) |
self.state = 232 |
self.match(HPC16Parser.T__26) |
self.state = 233 |
self.match(HPC16Parser.REG) |
self.state = 234 |
self.match(HPC16Parser.T__1) |
self.state = 235 |
self.match(HPC16Parser.REG) |
pass |
|
elif la_ == 47: |
localctx = HPC16Parser.Rol_reg_regContext(self, localctx) |
self.enterOuterAlt(localctx, 47) |
self.state = 236 |
self.match(HPC16Parser.T__27) |
self.state = 237 |
self.match(HPC16Parser.REG) |
self.state = 238 |
self.match(HPC16Parser.T__1) |
self.state = 239 |
self.match(HPC16Parser.REG) |
pass |
|
elif la_ == 48: |
localctx = HPC16Parser.Ror_reg_regContext(self, localctx) |
self.enterOuterAlt(localctx, 48) |
self.state = 240 |
self.match(HPC16Parser.T__28) |
self.state = 241 |
self.match(HPC16Parser.REG) |
self.state = 242 |
self.match(HPC16Parser.T__1) |
self.state = 243 |
self.match(HPC16Parser.REG) |
pass |
|
elif la_ == 49: |
localctx = HPC16Parser.Rcl_reg_regContext(self, localctx) |
self.enterOuterAlt(localctx, 49) |
self.state = 244 |
self.match(HPC16Parser.T__29) |
self.state = 245 |
self.match(HPC16Parser.REG) |
self.state = 246 |
self.match(HPC16Parser.T__1) |
self.state = 247 |
self.match(HPC16Parser.REG) |
pass |
|
elif la_ == 50: |
localctx = HPC16Parser.Rcr_reg_regContext(self, localctx) |
self.enterOuterAlt(localctx, 50) |
self.state = 248 |
self.match(HPC16Parser.T__30) |
self.state = 249 |
self.match(HPC16Parser.REG) |
self.state = 250 |
self.match(HPC16Parser.T__1) |
self.state = 251 |
self.match(HPC16Parser.REG) |
pass |
|
elif la_ == 51: |
localctx = HPC16Parser.Sll_reg_imm4Context(self, localctx) |
self.enterOuterAlt(localctx, 51) |
self.state = 252 |
self.match(HPC16Parser.T__23) |
self.state = 253 |
self.match(HPC16Parser.REG) |
self.state = 254 |
self.match(HPC16Parser.T__1) |
self.state = 255 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 52: |
localctx = HPC16Parser.Slr_reg_imm4Context(self, localctx) |
self.enterOuterAlt(localctx, 52) |
self.state = 256 |
self.match(HPC16Parser.T__24) |
self.state = 257 |
self.match(HPC16Parser.REG) |
self.state = 258 |
self.match(HPC16Parser.T__1) |
self.state = 259 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 53: |
localctx = HPC16Parser.Sal_reg_imm4Context(self, localctx) |
self.enterOuterAlt(localctx, 53) |
self.state = 260 |
self.match(HPC16Parser.T__25) |
self.state = 261 |
self.match(HPC16Parser.REG) |
self.state = 262 |
self.match(HPC16Parser.T__1) |
self.state = 263 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 54: |
localctx = HPC16Parser.Sar_reg_imm4Context(self, localctx) |
self.enterOuterAlt(localctx, 54) |
self.state = 264 |
self.match(HPC16Parser.T__26) |
self.state = 265 |
self.match(HPC16Parser.REG) |
self.state = 266 |
self.match(HPC16Parser.T__1) |
self.state = 267 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 55: |
localctx = HPC16Parser.Rol_reg_imm4Context(self, localctx) |
self.enterOuterAlt(localctx, 55) |
self.state = 268 |
self.match(HPC16Parser.T__27) |
self.state = 269 |
self.match(HPC16Parser.REG) |
self.state = 270 |
self.match(HPC16Parser.T__1) |
self.state = 271 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 56: |
localctx = HPC16Parser.Ror_reg_imm4Context(self, localctx) |
self.enterOuterAlt(localctx, 56) |
self.state = 272 |
self.match(HPC16Parser.T__28) |
self.state = 273 |
self.match(HPC16Parser.REG) |
self.state = 274 |
self.match(HPC16Parser.T__1) |
self.state = 275 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 57: |
localctx = HPC16Parser.Rcl_reg_imm4Context(self, localctx) |
self.enterOuterAlt(localctx, 57) |
self.state = 276 |
self.match(HPC16Parser.T__29) |
self.state = 277 |
self.match(HPC16Parser.REG) |
self.state = 278 |
self.match(HPC16Parser.T__1) |
self.state = 279 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 58: |
localctx = HPC16Parser.Rcr_reg_imm4Context(self, localctx) |
self.enterOuterAlt(localctx, 58) |
self.state = 280 |
self.match(HPC16Parser.T__30) |
self.state = 281 |
self.match(HPC16Parser.REG) |
self.state = 282 |
self.match(HPC16Parser.T__1) |
self.state = 283 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 59: |
localctx = HPC16Parser.Push_regContext(self, localctx) |
self.enterOuterAlt(localctx, 59) |
self.state = 284 |
self.match(HPC16Parser.T__31) |
self.state = 285 |
self.match(HPC16Parser.REG) |
pass |
|
elif la_ == 60: |
localctx = HPC16Parser.PushfContext(self, localctx) |
self.enterOuterAlt(localctx, 60) |
self.state = 286 |
self.match(HPC16Parser.T__32) |
pass |
|
elif la_ == 61: |
localctx = HPC16Parser.Pop_regContext(self, localctx) |
self.enterOuterAlt(localctx, 61) |
self.state = 287 |
self.match(HPC16Parser.T__33) |
self.state = 288 |
self.match(HPC16Parser.REG) |
pass |
|
elif la_ == 62: |
localctx = HPC16Parser.PopfContext(self, localctx) |
self.enterOuterAlt(localctx, 62) |
self.state = 289 |
self.match(HPC16Parser.T__34) |
pass |
|
elif la_ == 63: |
localctx = HPC16Parser.Acall_regContext(self, localctx) |
self.enterOuterAlt(localctx, 63) |
self.state = 290 |
self.match(HPC16Parser.T__35) |
self.state = 291 |
self.match(HPC16Parser.T__3) |
self.state = 292 |
self.match(HPC16Parser.REG) |
self.state = 293 |
self.match(HPC16Parser.T__4) |
pass |
|
elif la_ == 64: |
localctx = HPC16Parser.Call_regContext(self, localctx) |
self.enterOuterAlt(localctx, 64) |
self.state = 294 |
self.match(HPC16Parser.T__36) |
self.state = 295 |
self.match(HPC16Parser.T__3) |
self.state = 296 |
self.match(HPC16Parser.REG) |
self.state = 297 |
self.match(HPC16Parser.T__4) |
pass |
|
elif la_ == 65: |
localctx = HPC16Parser.Call_imm11Context(self, localctx) |
self.enterOuterAlt(localctx, 65) |
self.state = 298 |
self.match(HPC16Parser.T__36) |
self.state = 299 |
self.match(HPC16Parser.T__3) |
self.state = 300 |
self.match(HPC16Parser.IMM) |
self.state = 301 |
self.match(HPC16Parser.T__4) |
pass |
|
elif la_ == 66: |
localctx = HPC16Parser.RetContext(self, localctx) |
self.enterOuterAlt(localctx, 66) |
self.state = 302 |
self.match(HPC16Parser.T__37) |
pass |
|
elif la_ == 67: |
localctx = HPC16Parser.IretContext(self, localctx) |
self.enterOuterAlt(localctx, 67) |
self.state = 303 |
self.match(HPC16Parser.T__38) |
pass |
|
elif la_ == 68: |
localctx = HPC16Parser.ClcContext(self, localctx) |
self.enterOuterAlt(localctx, 68) |
self.state = 304 |
self.match(HPC16Parser.T__39) |
pass |
|
elif la_ == 69: |
localctx = HPC16Parser.StcContext(self, localctx) |
self.enterOuterAlt(localctx, 69) |
self.state = 305 |
self.match(HPC16Parser.T__40) |
pass |
|
elif la_ == 70: |
localctx = HPC16Parser.CmcContext(self, localctx) |
self.enterOuterAlt(localctx, 70) |
self.state = 306 |
self.match(HPC16Parser.T__41) |
pass |
|
elif la_ == 71: |
localctx = HPC16Parser.CliContext(self, localctx) |
self.enterOuterAlt(localctx, 71) |
self.state = 307 |
self.match(HPC16Parser.T__42) |
pass |
|
elif la_ == 72: |
localctx = HPC16Parser.StiContext(self, localctx) |
self.enterOuterAlt(localctx, 72) |
self.state = 308 |
self.match(HPC16Parser.T__43) |
pass |
|
elif la_ == 73: |
localctx = HPC16Parser.Int_imm4Context(self, localctx) |
self.enterOuterAlt(localctx, 73) |
self.state = 309 |
self.match(HPC16Parser.T__44) |
self.state = 310 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 74: |
localctx = HPC16Parser.IntoContext(self, localctx) |
self.enterOuterAlt(localctx, 74) |
self.state = 311 |
self.match(HPC16Parser.T__45) |
pass |
|
elif la_ == 75: |
localctx = HPC16Parser.AjmpContext(self, localctx) |
self.enterOuterAlt(localctx, 75) |
self.state = 312 |
self.match(HPC16Parser.T__46) |
self.state = 313 |
self.match(HPC16Parser.T__3) |
self.state = 314 |
self.match(HPC16Parser.REG) |
self.state = 315 |
self.match(HPC16Parser.T__4) |
pass |
|
elif la_ == 76: |
localctx = HPC16Parser.Jmp_regContext(self, localctx) |
self.enterOuterAlt(localctx, 76) |
self.state = 316 |
self.match(HPC16Parser.T__47) |
self.state = 317 |
self.match(HPC16Parser.T__3) |
self.state = 318 |
self.match(HPC16Parser.REG) |
self.state = 319 |
self.match(HPC16Parser.T__4) |
pass |
|
elif la_ == 77: |
localctx = HPC16Parser.Jmp_imm11Context(self, localctx) |
self.enterOuterAlt(localctx, 77) |
self.state = 320 |
self.match(HPC16Parser.T__47) |
self.state = 321 |
self.match(HPC16Parser.T__3) |
self.state = 322 |
self.match(HPC16Parser.IMM) |
self.state = 323 |
self.match(HPC16Parser.T__4) |
pass |
|
elif la_ == 78: |
localctx = HPC16Parser.NopContext(self, localctx) |
self.enterOuterAlt(localctx, 78) |
self.state = 324 |
self.match(HPC16Parser.T__48) |
pass |
|
elif la_ == 79: |
localctx = HPC16Parser.HaltContext(self, localctx) |
self.enterOuterAlt(localctx, 79) |
self.state = 325 |
self.match(HPC16Parser.T__49) |
pass |
|
elif la_ == 80: |
localctx = HPC16Parser.Jo_imm7Context(self, localctx) |
self.enterOuterAlt(localctx, 80) |
self.state = 326 |
self.match(HPC16Parser.T__50) |
self.state = 327 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 81: |
localctx = HPC16Parser.Jno_imm7Context(self, localctx) |
self.enterOuterAlt(localctx, 81) |
self.state = 328 |
self.match(HPC16Parser.T__51) |
self.state = 329 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 82: |
localctx = HPC16Parser.Jb_imm7Context(self, localctx) |
self.enterOuterAlt(localctx, 82) |
self.state = 330 |
self.match(HPC16Parser.T__52) |
self.state = 331 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 83: |
localctx = HPC16Parser.Jnae_imm7Context(self, localctx) |
self.enterOuterAlt(localctx, 83) |
self.state = 332 |
self.match(HPC16Parser.T__53) |
self.state = 333 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 84: |
localctx = HPC16Parser.Jnb_imm7Context(self, localctx) |
self.enterOuterAlt(localctx, 84) |
self.state = 334 |
self.match(HPC16Parser.T__54) |
self.state = 335 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 85: |
localctx = HPC16Parser.Jae_imm7Context(self, localctx) |
self.enterOuterAlt(localctx, 85) |
self.state = 336 |
self.match(HPC16Parser.T__55) |
self.state = 337 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 86: |
localctx = HPC16Parser.Je_imm7Context(self, localctx) |
self.enterOuterAlt(localctx, 86) |
self.state = 338 |
self.match(HPC16Parser.T__56) |
self.state = 339 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 87: |
localctx = HPC16Parser.Jz_imm7Context(self, localctx) |
self.enterOuterAlt(localctx, 87) |
self.state = 340 |
self.match(HPC16Parser.T__57) |
self.state = 341 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 88: |
localctx = HPC16Parser.Jne_imm7Context(self, localctx) |
self.enterOuterAlt(localctx, 88) |
self.state = 342 |
self.match(HPC16Parser.T__58) |
self.state = 343 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 89: |
localctx = HPC16Parser.Jnz_imm7Context(self, localctx) |
self.enterOuterAlt(localctx, 89) |
self.state = 344 |
self.match(HPC16Parser.T__59) |
self.state = 345 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 90: |
localctx = HPC16Parser.Jbe_imm7Context(self, localctx) |
self.enterOuterAlt(localctx, 90) |
self.state = 346 |
self.match(HPC16Parser.T__60) |
self.state = 347 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 91: |
localctx = HPC16Parser.Jna_imm7Context(self, localctx) |
self.enterOuterAlt(localctx, 91) |
self.state = 348 |
self.match(HPC16Parser.T__61) |
self.state = 349 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 92: |
localctx = HPC16Parser.Jnbe_imm7Context(self, localctx) |
self.enterOuterAlt(localctx, 92) |
self.state = 350 |
self.match(HPC16Parser.T__62) |
self.state = 351 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 93: |
localctx = HPC16Parser.Ja_imm7Context(self, localctx) |
self.enterOuterAlt(localctx, 93) |
self.state = 352 |
self.match(HPC16Parser.T__63) |
self.state = 353 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 94: |
localctx = HPC16Parser.Js_imm7Context(self, localctx) |
self.enterOuterAlt(localctx, 94) |
self.state = 354 |
self.match(HPC16Parser.T__64) |
self.state = 355 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 95: |
localctx = HPC16Parser.Jns_imm7Context(self, localctx) |
self.enterOuterAlt(localctx, 95) |
self.state = 356 |
self.match(HPC16Parser.T__65) |
self.state = 357 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 96: |
localctx = HPC16Parser.Jl_imm7Context(self, localctx) |
self.enterOuterAlt(localctx, 96) |
self.state = 358 |
self.match(HPC16Parser.T__66) |
self.state = 359 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 97: |
localctx = HPC16Parser.Jnge_imm7Context(self, localctx) |
self.enterOuterAlt(localctx, 97) |
self.state = 360 |
self.match(HPC16Parser.T__67) |
self.state = 361 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 98: |
localctx = HPC16Parser.Jnl_imm7Context(self, localctx) |
self.enterOuterAlt(localctx, 98) |
self.state = 362 |
self.match(HPC16Parser.T__68) |
self.state = 363 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 99: |
localctx = HPC16Parser.Jge_imm7Context(self, localctx) |
self.enterOuterAlt(localctx, 99) |
self.state = 364 |
self.match(HPC16Parser.T__69) |
self.state = 365 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 100: |
localctx = HPC16Parser.Jle_imm7Context(self, localctx) |
self.enterOuterAlt(localctx, 100) |
self.state = 366 |
self.match(HPC16Parser.T__70) |
self.state = 367 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 101: |
localctx = HPC16Parser.Jng_imm7Context(self, localctx) |
self.enterOuterAlt(localctx, 101) |
self.state = 368 |
self.match(HPC16Parser.T__71) |
self.state = 369 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 102: |
localctx = HPC16Parser.Jnle_imm7Context(self, localctx) |
self.enterOuterAlt(localctx, 102) |
self.state = 370 |
self.match(HPC16Parser.T__72) |
self.state = 371 |
self.match(HPC16Parser.IMM) |
pass |
|
elif la_ == 103: |
localctx = HPC16Parser.Jg_imm7Context(self, localctx) |
self.enterOuterAlt(localctx, 103) |
self.state = 372 |
self.match(HPC16Parser.T__73) |
self.state = 373 |
self.match(HPC16Parser.IMM) |
pass |
|
|
except RecognitionException as re: |
localctx.exception = re |
self._errHandler.reportError(self, re) |
self._errHandler.recover(self, re) |
finally: |
self.exitRule() |
return localctx |
|
|
|
|
|
/trunk/impl0/asm/prog1.asm
0,0 → 1,10
################################ |
## this program test: |
## mov, li and hlt instructions |
## |
################################ |
li r0, 0x5555 |
mov r1, r0 |
mov sp, r1 |
mov r5, sp |
hlt |
/trunk/impl0/asm/HPC16Lexer.py
0,0 → 1,358
# Generated from HPC16.g4 by ANTLR 4.5.1 |
# encoding: utf-8 |
from __future__ import print_function |
from antlr4 import * |
from io import StringIO |
|
|
def serializedATN(): |
with StringIO() as buf: |
buf.write(u"\3\u0430\ud6d1\u8206\uad2d\u4417\uaef1\u8d80\uaadd\2") |
buf.write(u"R\u01fc\b\1\4\2\t\2\4\3\t\3\4\4\t\4\4\5\t\5\4\6\t\6\4") |
buf.write(u"\7\t\7\4\b\t\b\4\t\t\t\4\n\t\n\4\13\t\13\4\f\t\f\4\r") |
buf.write(u"\t\r\4\16\t\16\4\17\t\17\4\20\t\20\4\21\t\21\4\22\t\22") |
buf.write(u"\4\23\t\23\4\24\t\24\4\25\t\25\4\26\t\26\4\27\t\27\4") |
buf.write(u"\30\t\30\4\31\t\31\4\32\t\32\4\33\t\33\4\34\t\34\4\35") |
buf.write(u"\t\35\4\36\t\36\4\37\t\37\4 \t \4!\t!\4\"\t\"\4#\t#\4") |
buf.write(u"$\t$\4%\t%\4&\t&\4\'\t\'\4(\t(\4)\t)\4*\t*\4+\t+\4,\t") |
buf.write(u",\4-\t-\4.\t.\4/\t/\4\60\t\60\4\61\t\61\4\62\t\62\4\63") |
buf.write(u"\t\63\4\64\t\64\4\65\t\65\4\66\t\66\4\67\t\67\48\t8\4") |
buf.write(u"9\t9\4:\t:\4;\t;\4<\t<\4=\t=\4>\t>\4?\t?\4@\t@\4A\tA") |
buf.write(u"\4B\tB\4C\tC\4D\tD\4E\tE\4F\tF\4G\tG\4H\tH\4I\tI\4J\t") |
buf.write(u"J\4K\tK\4L\tL\4M\tM\4N\tN\4O\tO\4P\tP\4Q\tQ\3\2\3\2\3") |
buf.write(u"\2\3\2\3\3\3\3\3\4\3\4\3\4\3\5\3\5\3\6\3\6\3\7\3\7\3") |
buf.write(u"\b\3\b\3\b\3\t\3\t\3\t\3\t\3\t\3\n\3\n\3\n\3\n\3\n\3") |
buf.write(u"\13\3\13\3\13\3\f\3\f\3\f\3\r\3\r\3\r\3\r\3\16\3\16\3") |
buf.write(u"\16\3\16\3\17\3\17\3\17\3\17\3\20\3\20\3\20\3\20\3\21") |
buf.write(u"\3\21\3\21\3\21\3\22\3\22\3\22\3\22\3\23\3\23\3\23\3") |
buf.write(u"\23\3\24\3\24\3\24\3\25\3\25\3\25\3\25\3\26\3\26\3\26") |
buf.write(u"\3\26\3\27\3\27\3\27\3\27\3\30\3\30\3\30\3\30\3\30\3") |
buf.write(u"\31\3\31\3\31\3\31\3\32\3\32\3\32\3\32\3\33\3\33\3\33") |
buf.write(u"\3\33\3\34\3\34\3\34\3\34\3\35\3\35\3\35\3\35\3\36\3") |
buf.write(u"\36\3\36\3\36\3\37\3\37\3\37\3\37\3 \3 \3 \3 \3!\3!\3") |
buf.write(u"!\3!\3!\3\"\3\"\3\"\3\"\3\"\3\"\3#\3#\3#\3#\3$\3$\3$") |
buf.write(u"\3$\3$\3%\3%\3%\3%\3%\3%\3&\3&\3&\3&\3&\3\'\3\'\3\'\3") |
buf.write(u"\'\3(\3(\3(\3(\3(\3)\3)\3)\3)\3*\3*\3*\3*\3+\3+\3+\3") |
buf.write(u"+\3,\3,\3,\3,\3-\3-\3-\3-\3.\3.\3.\3.\3/\3/\3/\3/\3/") |
buf.write(u"\3\60\3\60\3\60\3\60\3\60\3\61\3\61\3\61\3\61\3\62\3") |
buf.write(u"\62\3\62\3\62\3\63\3\63\3\63\3\63\3\64\3\64\3\64\3\65") |
buf.write(u"\3\65\3\65\3\65\3\66\3\66\3\66\3\67\3\67\3\67\3\67\3") |
buf.write(u"\67\38\38\38\38\39\39\39\39\3:\3:\3:\3;\3;\3;\3<\3<\3") |
buf.write(u"<\3<\3=\3=\3=\3=\3>\3>\3>\3>\3?\3?\3?\3?\3@\3@\3@\3@") |
buf.write(u"\3@\3A\3A\3A\3B\3B\3B\3C\3C\3C\3C\3D\3D\3D\3E\3E\3E\3") |
buf.write(u"E\3E\3F\3F\3F\3F\3G\3G\3G\3G\3H\3H\3H\3H\3I\3I\3I\3I") |
buf.write(u"\3J\3J\3J\3J\3J\3K\3K\3K\3L\3L\6L\u01ca\nL\rL\16L\u01cb") |
buf.write(u"\3M\6M\u01cf\nM\rM\16M\u01d0\3M\3M\3M\3M\6M\u01d7\nM") |
buf.write(u"\rM\16M\u01d8\5M\u01db\nM\3N\3N\3N\3N\5N\u01e1\nN\3O") |
buf.write(u"\6O\u01e4\nO\rO\16O\u01e5\3O\3O\3P\3P\7P\u01ec\nP\fP") |
buf.write(u"\16P\u01ef\13P\3P\5P\u01f2\nP\3P\3P\3P\3P\3Q\5Q\u01f9") |
buf.write(u"\nQ\3Q\3Q\3\u01ed\2R\3\3\5\4\7\5\t\6\13\7\r\b\17\t\21") |
buf.write(u"\n\23\13\25\f\27\r\31\16\33\17\35\20\37\21!\22#\23%\24") |
buf.write(u"\'\25)\26+\27-\30/\31\61\32\63\33\65\34\67\359\36;\37") |
buf.write(u"= ?!A\"C#E$G%I&K\'M(O)Q*S+U,W-Y.[/]\60_\61a\62c\63e\64") |
buf.write(u"g\65i\66k\67m8o9q:s;u<w=y>{?}@\177A\u0081B\u0083C\u0085") |
buf.write(u"D\u0087E\u0089F\u008bG\u008dH\u008fI\u0091J\u0093K\u0095") |
buf.write(u"L\u0097M\u0099N\u009bO\u009dP\u009fQ\u00a1R\3\2\6\4\2") |
buf.write(u"TTtt\3\2\62;\5\2\62;CHch\4\2\13\13\"\"\u0204\2\3\3\2") |
buf.write(u"\2\2\2\5\3\2\2\2\2\7\3\2\2\2\2\t\3\2\2\2\2\13\3\2\2\2") |
buf.write(u"\2\r\3\2\2\2\2\17\3\2\2\2\2\21\3\2\2\2\2\23\3\2\2\2\2") |
buf.write(u"\25\3\2\2\2\2\27\3\2\2\2\2\31\3\2\2\2\2\33\3\2\2\2\2") |
buf.write(u"\35\3\2\2\2\2\37\3\2\2\2\2!\3\2\2\2\2#\3\2\2\2\2%\3\2") |
buf.write(u"\2\2\2\'\3\2\2\2\2)\3\2\2\2\2+\3\2\2\2\2-\3\2\2\2\2/") |
buf.write(u"\3\2\2\2\2\61\3\2\2\2\2\63\3\2\2\2\2\65\3\2\2\2\2\67") |
buf.write(u"\3\2\2\2\29\3\2\2\2\2;\3\2\2\2\2=\3\2\2\2\2?\3\2\2\2") |
buf.write(u"\2A\3\2\2\2\2C\3\2\2\2\2E\3\2\2\2\2G\3\2\2\2\2I\3\2\2") |
buf.write(u"\2\2K\3\2\2\2\2M\3\2\2\2\2O\3\2\2\2\2Q\3\2\2\2\2S\3\2") |
buf.write(u"\2\2\2U\3\2\2\2\2W\3\2\2\2\2Y\3\2\2\2\2[\3\2\2\2\2]\3") |
buf.write(u"\2\2\2\2_\3\2\2\2\2a\3\2\2\2\2c\3\2\2\2\2e\3\2\2\2\2") |
buf.write(u"g\3\2\2\2\2i\3\2\2\2\2k\3\2\2\2\2m\3\2\2\2\2o\3\2\2\2") |
buf.write(u"\2q\3\2\2\2\2s\3\2\2\2\2u\3\2\2\2\2w\3\2\2\2\2y\3\2\2") |
buf.write(u"\2\2{\3\2\2\2\2}\3\2\2\2\2\177\3\2\2\2\2\u0081\3\2\2") |
buf.write(u"\2\2\u0083\3\2\2\2\2\u0085\3\2\2\2\2\u0087\3\2\2\2\2") |
buf.write(u"\u0089\3\2\2\2\2\u008b\3\2\2\2\2\u008d\3\2\2\2\2\u008f") |
buf.write(u"\3\2\2\2\2\u0091\3\2\2\2\2\u0093\3\2\2\2\2\u0095\3\2") |
buf.write(u"\2\2\2\u0097\3\2\2\2\2\u0099\3\2\2\2\2\u009b\3\2\2\2") |
buf.write(u"\2\u009d\3\2\2\2\2\u009f\3\2\2\2\2\u00a1\3\2\2\2\3\u00a3") |
buf.write(u"\3\2\2\2\5\u00a7\3\2\2\2\7\u00a9\3\2\2\2\t\u00ac\3\2") |
buf.write(u"\2\2\13\u00ae\3\2\2\2\r\u00b0\3\2\2\2\17\u00b2\3\2\2") |
buf.write(u"\2\21\u00b5\3\2\2\2\23\u00ba\3\2\2\2\25\u00bf\3\2\2\2") |
buf.write(u"\27\u00c2\3\2\2\2\31\u00c5\3\2\2\2\33\u00c9\3\2\2\2\35") |
buf.write(u"\u00cd\3\2\2\2\37\u00d1\3\2\2\2!\u00d5\3\2\2\2#\u00d9") |
buf.write(u"\3\2\2\2%\u00dd\3\2\2\2\'\u00e1\3\2\2\2)\u00e4\3\2\2") |
buf.write(u"\2+\u00e8\3\2\2\2-\u00ec\3\2\2\2/\u00f0\3\2\2\2\61\u00f5") |
buf.write(u"\3\2\2\2\63\u00f9\3\2\2\2\65\u00fd\3\2\2\2\67\u0101\3") |
buf.write(u"\2\2\29\u0105\3\2\2\2;\u0109\3\2\2\2=\u010d\3\2\2\2?") |
buf.write(u"\u0111\3\2\2\2A\u0115\3\2\2\2C\u011a\3\2\2\2E\u0120\3") |
buf.write(u"\2\2\2G\u0124\3\2\2\2I\u0129\3\2\2\2K\u012f\3\2\2\2M") |
buf.write(u"\u0134\3\2\2\2O\u0138\3\2\2\2Q\u013d\3\2\2\2S\u0141\3") |
buf.write(u"\2\2\2U\u0145\3\2\2\2W\u0149\3\2\2\2Y\u014d\3\2\2\2[") |
buf.write(u"\u0151\3\2\2\2]\u0155\3\2\2\2_\u015a\3\2\2\2a\u015f\3") |
buf.write(u"\2\2\2c\u0163\3\2\2\2e\u0167\3\2\2\2g\u016b\3\2\2\2i") |
buf.write(u"\u016e\3\2\2\2k\u0172\3\2\2\2m\u0175\3\2\2\2o\u017a\3") |
buf.write(u"\2\2\2q\u017e\3\2\2\2s\u0182\3\2\2\2u\u0185\3\2\2\2w") |
buf.write(u"\u0188\3\2\2\2y\u018c\3\2\2\2{\u0190\3\2\2\2}\u0194\3") |
buf.write(u"\2\2\2\177\u0198\3\2\2\2\u0081\u019d\3\2\2\2\u0083\u01a0") |
buf.write(u"\3\2\2\2\u0085\u01a3\3\2\2\2\u0087\u01a7\3\2\2\2\u0089") |
buf.write(u"\u01aa\3\2\2\2\u008b\u01af\3\2\2\2\u008d\u01b3\3\2\2") |
buf.write(u"\2\u008f\u01b7\3\2\2\2\u0091\u01bb\3\2\2\2\u0093\u01bf") |
buf.write(u"\3\2\2\2\u0095\u01c4\3\2\2\2\u0097\u01c7\3\2\2\2\u0099") |
buf.write(u"\u01da\3\2\2\2\u009b\u01e0\3\2\2\2\u009d\u01e3\3\2\2") |
buf.write(u"\2\u009f\u01e9\3\2\2\2\u00a1\u01f8\3\2\2\2\u00a3\u00a4") |
buf.write(u"\7o\2\2\u00a4\u00a5\7q\2\2\u00a5\u00a6\7x\2\2\u00a6\4") |
buf.write(u"\3\2\2\2\u00a7\u00a8\7.\2\2\u00a8\6\3\2\2\2\u00a9\u00aa") |
buf.write(u"\7n\2\2\u00aa\u00ab\7f\2\2\u00ab\b\3\2\2\2\u00ac\u00ad") |
buf.write(u"\7*\2\2\u00ad\n\3\2\2\2\u00ae\u00af\7+\2\2\u00af\f\3") |
buf.write(u"\2\2\2\u00b0\u00b1\7-\2\2\u00b1\16\3\2\2\2\u00b2\u00b3") |
buf.write(u"\7u\2\2\u00b3\u00b4\7v\2\2\u00b4\20\3\2\2\2\u00b5\u00b6") |
buf.write(u"\7n\2\2\u00b6\u00b7\7d\2\2\u00b7\u00b8\7|\2\2\u00b8\u00b9") |
buf.write(u"\7z\2\2\u00b9\22\3\2\2\2\u00ba\u00bb\7n\2\2\u00bb\u00bc") |
buf.write(u"\7d\2\2\u00bc\u00bd\7u\2\2\u00bd\u00be\7z\2\2\u00be\24") |
buf.write(u"\3\2\2\2\u00bf\u00c0\7u\2\2\u00c0\u00c1\7d\2\2\u00c1") |
buf.write(u"\26\3\2\2\2\u00c2\u00c3\7n\2\2\u00c3\u00c4\7k\2\2\u00c4") |
buf.write(u"\30\3\2\2\2\u00c5\u00c6\7k\2\2\u00c6\u00c7\7p\2\2\u00c7") |
buf.write(u"\u00c8\7e\2\2\u00c8\32\3\2\2\2\u00c9\u00ca\7f\2\2\u00ca") |
buf.write(u"\u00cb\7g\2\2\u00cb\u00cc\7e\2\2\u00cc\34\3\2\2\2\u00cd") |
buf.write(u"\u00ce\7u\2\2\u00ce\u00cf\7w\2\2\u00cf\u00d0\7d\2\2\u00d0") |
buf.write(u"\36\3\2\2\2\u00d1\u00d2\7c\2\2\u00d2\u00d3\7p\2\2\u00d3") |
buf.write(u"\u00d4\7f\2\2\u00d4 \3\2\2\2\u00d5\u00d6\7c\2\2\u00d6") |
buf.write(u"\u00d7\7f\2\2\u00d7\u00d8\7f\2\2\u00d8\"\3\2\2\2\u00d9") |
buf.write(u"\u00da\7c\2\2\u00da\u00db\7f\2\2\u00db\u00dc\7e\2\2\u00dc") |
buf.write(u"$\3\2\2\2\u00dd\u00de\7u\2\2\u00de\u00df\7d\2\2\u00df") |
buf.write(u"\u00e0\7d\2\2\u00e0&\3\2\2\2\u00e1\u00e2\7q\2\2\u00e2") |
buf.write(u"\u00e3\7t\2\2\u00e3(\3\2\2\2\u00e4\u00e5\7z\2\2\u00e5") |
buf.write(u"\u00e6\7q\2\2\u00e6\u00e7\7t\2\2\u00e7*\3\2\2\2\u00e8") |
buf.write(u"\u00e9\7p\2\2\u00e9\u00ea\7q\2\2\u00ea\u00eb\7v\2\2\u00eb") |
buf.write(u",\3\2\2\2\u00ec\u00ed\7e\2\2\u00ed\u00ee\7o\2\2\u00ee") |
buf.write(u"\u00ef\7r\2\2\u00ef.\3\2\2\2\u00f0\u00f1\7v\2\2\u00f1") |
buf.write(u"\u00f2\7g\2\2\u00f2\u00f3\7u\2\2\u00f3\u00f4\7v\2\2\u00f4") |
buf.write(u"\60\3\2\2\2\u00f5\u00f6\7u\2\2\u00f6\u00f7\7n\2\2\u00f7") |
buf.write(u"\u00f8\7n\2\2\u00f8\62\3\2\2\2\u00f9\u00fa\7u\2\2\u00fa") |
buf.write(u"\u00fb\7n\2\2\u00fb\u00fc\7t\2\2\u00fc\64\3\2\2\2\u00fd") |
buf.write(u"\u00fe\7u\2\2\u00fe\u00ff\7c\2\2\u00ff\u0100\7n\2\2\u0100") |
buf.write(u"\66\3\2\2\2\u0101\u0102\7u\2\2\u0102\u0103\7c\2\2\u0103") |
buf.write(u"\u0104\7t\2\2\u01048\3\2\2\2\u0105\u0106\7t\2\2\u0106") |
buf.write(u"\u0107\7q\2\2\u0107\u0108\7n\2\2\u0108:\3\2\2\2\u0109") |
buf.write(u"\u010a\7t\2\2\u010a\u010b\7q\2\2\u010b\u010c\7t\2\2\u010c") |
buf.write(u"<\3\2\2\2\u010d\u010e\7t\2\2\u010e\u010f\7e\2\2\u010f") |
buf.write(u"\u0110\7n\2\2\u0110>\3\2\2\2\u0111\u0112\7t\2\2\u0112") |
buf.write(u"\u0113\7e\2\2\u0113\u0114\7t\2\2\u0114@\3\2\2\2\u0115") |
buf.write(u"\u0116\7r\2\2\u0116\u0117\7w\2\2\u0117\u0118\7u\2\2\u0118") |
buf.write(u"\u0119\7j\2\2\u0119B\3\2\2\2\u011a\u011b\7r\2\2\u011b") |
buf.write(u"\u011c\7w\2\2\u011c\u011d\7u\2\2\u011d\u011e\7j\2\2\u011e") |
buf.write(u"\u011f\7h\2\2\u011fD\3\2\2\2\u0120\u0121\7r\2\2\u0121") |
buf.write(u"\u0122\7q\2\2\u0122\u0123\7r\2\2\u0123F\3\2\2\2\u0124") |
buf.write(u"\u0125\7r\2\2\u0125\u0126\7q\2\2\u0126\u0127\7r\2\2\u0127") |
buf.write(u"\u0128\7h\2\2\u0128H\3\2\2\2\u0129\u012a\7c\2\2\u012a") |
buf.write(u"\u012b\7e\2\2\u012b\u012c\7c\2\2\u012c\u012d\7n\2\2\u012d") |
buf.write(u"\u012e\7n\2\2\u012eJ\3\2\2\2\u012f\u0130\7e\2\2\u0130") |
buf.write(u"\u0131\7c\2\2\u0131\u0132\7n\2\2\u0132\u0133\7n\2\2\u0133") |
buf.write(u"L\3\2\2\2\u0134\u0135\7t\2\2\u0135\u0136\7g\2\2\u0136") |
buf.write(u"\u0137\7v\2\2\u0137N\3\2\2\2\u0138\u0139\7k\2\2\u0139") |
buf.write(u"\u013a\7t\2\2\u013a\u013b\7g\2\2\u013b\u013c\7v\2\2\u013c") |
buf.write(u"P\3\2\2\2\u013d\u013e\7e\2\2\u013e\u013f\7n\2\2\u013f") |
buf.write(u"\u0140\7e\2\2\u0140R\3\2\2\2\u0141\u0142\7u\2\2\u0142") |
buf.write(u"\u0143\7v\2\2\u0143\u0144\7e\2\2\u0144T\3\2\2\2\u0145") |
buf.write(u"\u0146\7e\2\2\u0146\u0147\7o\2\2\u0147\u0148\7e\2\2\u0148") |
buf.write(u"V\3\2\2\2\u0149\u014a\7e\2\2\u014a\u014b\7n\2\2\u014b") |
buf.write(u"\u014c\7k\2\2\u014cX\3\2\2\2\u014d\u014e\7u\2\2\u014e") |
buf.write(u"\u014f\7v\2\2\u014f\u0150\7k\2\2\u0150Z\3\2\2\2\u0151") |
buf.write(u"\u0152\7k\2\2\u0152\u0153\7p\2\2\u0153\u0154\7v\2\2\u0154") |
buf.write(u"\\\3\2\2\2\u0155\u0156\7k\2\2\u0156\u0157\7p\2\2\u0157") |
buf.write(u"\u0158\7v\2\2\u0158\u0159\7q\2\2\u0159^\3\2\2\2\u015a") |
buf.write(u"\u015b\7c\2\2\u015b\u015c\7l\2\2\u015c\u015d\7o\2\2\u015d") |
buf.write(u"\u015e\7r\2\2\u015e`\3\2\2\2\u015f\u0160\7l\2\2\u0160") |
buf.write(u"\u0161\7o\2\2\u0161\u0162\7r\2\2\u0162b\3\2\2\2\u0163") |
buf.write(u"\u0164\7p\2\2\u0164\u0165\7q\2\2\u0165\u0166\7r\2\2\u0166") |
buf.write(u"d\3\2\2\2\u0167\u0168\7j\2\2\u0168\u0169\7n\2\2\u0169") |
buf.write(u"\u016a\7v\2\2\u016af\3\2\2\2\u016b\u016c\7l\2\2\u016c") |
buf.write(u"\u016d\7q\2\2\u016dh\3\2\2\2\u016e\u016f\7l\2\2\u016f") |
buf.write(u"\u0170\7p\2\2\u0170\u0171\7q\2\2\u0171j\3\2\2\2\u0172") |
buf.write(u"\u0173\7l\2\2\u0173\u0174\7d\2\2\u0174l\3\2\2\2\u0175") |
buf.write(u"\u0176\7l\2\2\u0176\u0177\7p\2\2\u0177\u0178\7c\2\2\u0178") |
buf.write(u"\u0179\7g\2\2\u0179n\3\2\2\2\u017a\u017b\7l\2\2\u017b") |
buf.write(u"\u017c\7p\2\2\u017c\u017d\7d\2\2\u017dp\3\2\2\2\u017e") |
buf.write(u"\u017f\7l\2\2\u017f\u0180\7c\2\2\u0180\u0181\7g\2\2\u0181") |
buf.write(u"r\3\2\2\2\u0182\u0183\7l\2\2\u0183\u0184\7g\2\2\u0184") |
buf.write(u"t\3\2\2\2\u0185\u0186\7l\2\2\u0186\u0187\7|\2\2\u0187") |
buf.write(u"v\3\2\2\2\u0188\u0189\7l\2\2\u0189\u018a\7p\2\2\u018a") |
buf.write(u"\u018b\7g\2\2\u018bx\3\2\2\2\u018c\u018d\7l\2\2\u018d") |
buf.write(u"\u018e\7p\2\2\u018e\u018f\7|\2\2\u018fz\3\2\2\2\u0190") |
buf.write(u"\u0191\7l\2\2\u0191\u0192\7d\2\2\u0192\u0193\7g\2\2\u0193") |
buf.write(u"|\3\2\2\2\u0194\u0195\7l\2\2\u0195\u0196\7p\2\2\u0196") |
buf.write(u"\u0197\7c\2\2\u0197~\3\2\2\2\u0198\u0199\7l\2\2\u0199") |
buf.write(u"\u019a\7p\2\2\u019a\u019b\7d\2\2\u019b\u019c\7g\2\2\u019c") |
buf.write(u"\u0080\3\2\2\2\u019d\u019e\7l\2\2\u019e\u019f\7c\2\2") |
buf.write(u"\u019f\u0082\3\2\2\2\u01a0\u01a1\7l\2\2\u01a1\u01a2\7") |
buf.write(u"u\2\2\u01a2\u0084\3\2\2\2\u01a3\u01a4\7l\2\2\u01a4\u01a5") |
buf.write(u"\7p\2\2\u01a5\u01a6\7u\2\2\u01a6\u0086\3\2\2\2\u01a7") |
buf.write(u"\u01a8\7l\2\2\u01a8\u01a9\7n\2\2\u01a9\u0088\3\2\2\2") |
buf.write(u"\u01aa\u01ab\7l\2\2\u01ab\u01ac\7p\2\2\u01ac\u01ad\7") |
buf.write(u"i\2\2\u01ad\u01ae\7g\2\2\u01ae\u008a\3\2\2\2\u01af\u01b0") |
buf.write(u"\7l\2\2\u01b0\u01b1\7p\2\2\u01b1\u01b2\7n\2\2\u01b2\u008c") |
buf.write(u"\3\2\2\2\u01b3\u01b4\7l\2\2\u01b4\u01b5\7i\2\2\u01b5") |
buf.write(u"\u01b6\7g\2\2\u01b6\u008e\3\2\2\2\u01b7\u01b8\7l\2\2") |
buf.write(u"\u01b8\u01b9\7n\2\2\u01b9\u01ba\7g\2\2\u01ba\u0090\3") |
buf.write(u"\2\2\2\u01bb\u01bc\7l\2\2\u01bc\u01bd\7p\2\2\u01bd\u01be") |
buf.write(u"\7i\2\2\u01be\u0092\3\2\2\2\u01bf\u01c0\7l\2\2\u01c0") |
buf.write(u"\u01c1\7p\2\2\u01c1\u01c2\7n\2\2\u01c2\u01c3\7g\2\2\u01c3") |
buf.write(u"\u0094\3\2\2\2\u01c4\u01c5\7l\2\2\u01c5\u01c6\7i\2\2") |
buf.write(u"\u01c6\u0096\3\2\2\2\u01c7\u01c9\t\2\2\2\u01c8\u01ca") |
buf.write(u"\t\3\2\2\u01c9\u01c8\3\2\2\2\u01ca\u01cb\3\2\2\2\u01cb") |
buf.write(u"\u01c9\3\2\2\2\u01cb\u01cc\3\2\2\2\u01cc\u0098\3\2\2") |
buf.write(u"\2\u01cd\u01cf\t\3\2\2\u01ce\u01cd\3\2\2\2\u01cf\u01d0") |
buf.write(u"\3\2\2\2\u01d0\u01ce\3\2\2\2\u01d0\u01d1\3\2\2\2\u01d1") |
buf.write(u"\u01db\3\2\2\2\u01d2\u01d3\7\62\2\2\u01d3\u01d4\7z\2") |
buf.write(u"\2\u01d4\u01d6\3\2\2\2\u01d5\u01d7\t\4\2\2\u01d6\u01d5") |
buf.write(u"\3\2\2\2\u01d7\u01d8\3\2\2\2\u01d8\u01d6\3\2\2\2\u01d8") |
buf.write(u"\u01d9\3\2\2\2\u01d9\u01db\3\2\2\2\u01da\u01ce\3\2\2") |
buf.write(u"\2\u01da\u01d2\3\2\2\2\u01db\u009a\3\2\2\2\u01dc\u01dd") |
buf.write(u"\7U\2\2\u01dd\u01e1\7R\2\2\u01de\u01df\7u\2\2\u01df\u01e1") |
buf.write(u"\7r\2\2\u01e0\u01dc\3\2\2\2\u01e0\u01de\3\2\2\2\u01e1") |
buf.write(u"\u009c\3\2\2\2\u01e2\u01e4\t\5\2\2\u01e3\u01e2\3\2\2") |
buf.write(u"\2\u01e4\u01e5\3\2\2\2\u01e5\u01e3\3\2\2\2\u01e5\u01e6") |
buf.write(u"\3\2\2\2\u01e6\u01e7\3\2\2\2\u01e7\u01e8\bO\2\2\u01e8") |
buf.write(u"\u009e\3\2\2\2\u01e9\u01ed\7%\2\2\u01ea\u01ec\13\2\2") |
buf.write(u"\2\u01eb\u01ea\3\2\2\2\u01ec\u01ef\3\2\2\2\u01ed\u01ee") |
buf.write(u"\3\2\2\2\u01ed\u01eb\3\2\2\2\u01ee\u01f1\3\2\2\2\u01ef") |
buf.write(u"\u01ed\3\2\2\2\u01f0\u01f2\7\17\2\2\u01f1\u01f0\3\2\2") |
buf.write(u"\2\u01f1\u01f2\3\2\2\2\u01f2\u01f3\3\2\2\2\u01f3\u01f4") |
buf.write(u"\7\f\2\2\u01f4\u01f5\3\2\2\2\u01f5\u01f6\bP\2\2\u01f6") |
buf.write(u"\u00a0\3\2\2\2\u01f7\u01f9\7\17\2\2\u01f8\u01f7\3\2\2") |
buf.write(u"\2\u01f8\u01f9\3\2\2\2\u01f9\u01fa\3\2\2\2\u01fa\u01fb") |
buf.write(u"\7\f\2\2\u01fb\u00a2\3\2\2\2\f\2\u01cb\u01d0\u01d8\u01da") |
buf.write(u"\u01e0\u01e5\u01ed\u01f1\u01f8\3\b\2\2") |
return buf.getvalue() |
|
|
class HPC16Lexer(Lexer): |
|
atn = ATNDeserializer().deserialize(serializedATN()) |
|
decisionsToDFA = [ DFA(ds, i) for i, ds in enumerate(atn.decisionToState) ] |
|
|
T__0 = 1 |
T__1 = 2 |
T__2 = 3 |
T__3 = 4 |
T__4 = 5 |
T__5 = 6 |
T__6 = 7 |
T__7 = 8 |
T__8 = 9 |
T__9 = 10 |
T__10 = 11 |
T__11 = 12 |
T__12 = 13 |
T__13 = 14 |
T__14 = 15 |
T__15 = 16 |
T__16 = 17 |
T__17 = 18 |
T__18 = 19 |
T__19 = 20 |
T__20 = 21 |
T__21 = 22 |
T__22 = 23 |
T__23 = 24 |
T__24 = 25 |
T__25 = 26 |
T__26 = 27 |
T__27 = 28 |
T__28 = 29 |
T__29 = 30 |
T__30 = 31 |
T__31 = 32 |
T__32 = 33 |
T__33 = 34 |
T__34 = 35 |
T__35 = 36 |
T__36 = 37 |
T__37 = 38 |
T__38 = 39 |
T__39 = 40 |
T__40 = 41 |
T__41 = 42 |
T__42 = 43 |
T__43 = 44 |
T__44 = 45 |
T__45 = 46 |
T__46 = 47 |
T__47 = 48 |
T__48 = 49 |
T__49 = 50 |
T__50 = 51 |
T__51 = 52 |
T__52 = 53 |
T__53 = 54 |
T__54 = 55 |
T__55 = 56 |
T__56 = 57 |
T__57 = 58 |
T__58 = 59 |
T__59 = 60 |
T__60 = 61 |
T__61 = 62 |
T__62 = 63 |
T__63 = 64 |
T__64 = 65 |
T__65 = 66 |
T__66 = 67 |
T__67 = 68 |
T__68 = 69 |
T__69 = 70 |
T__70 = 71 |
T__71 = 72 |
T__72 = 73 |
T__73 = 74 |
REG = 75 |
IMM = 76 |
STK_PTR = 77 |
WS = 78 |
LINE_COMMENT = 79 |
NEWLINE = 80 |
|
modeNames = [ u"DEFAULT_MODE" ] |
|
literalNames = [ u"<INVALID>", |
u"'mov'", u"','", u"'ld'", u"'('", u"')'", u"'+'", u"'st'", |
u"'lbzx'", u"'lbsx'", u"'sb'", u"'li'", u"'inc'", u"'dec'", |
u"'sub'", u"'and'", u"'add'", u"'adc'", u"'sbb'", u"'or'", u"'xor'", |
u"'not'", u"'cmp'", u"'test'", u"'sll'", u"'slr'", u"'sal'", |
u"'sar'", u"'rol'", u"'ror'", u"'rcl'", u"'rcr'", u"'push'", |
u"'pushf'", u"'pop'", u"'popf'", u"'acall'", u"'call'", u"'ret'", |
u"'iret'", u"'clc'", u"'stc'", u"'cmc'", u"'cli'", u"'sti'", |
u"'int'", u"'into'", u"'ajmp'", u"'jmp'", u"'nop'", u"'hlt'", |
u"'jo'", u"'jno'", u"'jb'", u"'jnae'", u"'jnb'", u"'jae'", u"'je'", |
u"'jz'", u"'jne'", u"'jnz'", u"'jbe'", u"'jna'", u"'jnbe'", |
u"'ja'", u"'js'", u"'jns'", u"'jl'", u"'jnge'", u"'jnl'", u"'jge'", |
u"'jle'", u"'jng'", u"'jnle'", u"'jg'" ] |
|
symbolicNames = [ u"<INVALID>", |
u"REG", u"IMM", u"STK_PTR", u"WS", u"LINE_COMMENT", u"NEWLINE" ] |
|
ruleNames = [ u"T__0", u"T__1", u"T__2", u"T__3", u"T__4", u"T__5", |
u"T__6", u"T__7", u"T__8", u"T__9", u"T__10", u"T__11", |
u"T__12", u"T__13", u"T__14", u"T__15", u"T__16", u"T__17", |
u"T__18", u"T__19", u"T__20", u"T__21", u"T__22", u"T__23", |
u"T__24", u"T__25", u"T__26", u"T__27", u"T__28", u"T__29", |
u"T__30", u"T__31", u"T__32", u"T__33", u"T__34", u"T__35", |
u"T__36", u"T__37", u"T__38", u"T__39", u"T__40", u"T__41", |
u"T__42", u"T__43", u"T__44", u"T__45", u"T__46", u"T__47", |
u"T__48", u"T__49", u"T__50", u"T__51", u"T__52", u"T__53", |
u"T__54", u"T__55", u"T__56", u"T__57", u"T__58", u"T__59", |
u"T__60", u"T__61", u"T__62", u"T__63", u"T__64", u"T__65", |
u"T__66", u"T__67", u"T__68", u"T__69", u"T__70", u"T__71", |
u"T__72", u"T__73", u"REG", u"IMM", u"STK_PTR", u"WS", |
u"LINE_COMMENT", u"NEWLINE" ] |
|
grammarFileName = u"HPC16.g4" |
|
def __init__(self, input=None): |
super(HPC16Lexer, self).__init__(input) |
self.checkVersion("4.5.1") |
self._interp = LexerATNSimulator(self, self.atn, self.decisionsToDFA, PredictionContextCache()) |
self._actions = None |
self._predicates = None |
|
|
/trunk/impl0/asm/HPC16_asm.py
0,0 → 1,100
#!/usr/bin/python |
#-------------------------------------------------------------- |
#-- HPC-16 Assembler |
#-------------------------------------------------------------- |
#-- project: HPC-16 Microprocessor |
#-- |
#-- usage: HPC16_asm.py <input_file> |
#-- |
#-- |
#-- |
#-- Author: M. Umair Siddiqui (umairsiddiqui@opencores.org) |
#--------------------------------------------------------------- |
#------------------------------------------------------------------------------------ |
#-- -- |
#-- Copyright (c) 2015, M. Umair Siddiqui all rights reserved -- |
#-- -- |
#-- This file is part of HPC-16. -- |
#-- -- |
#-- HPC-16 is free software; you can redistribute it and/or modify -- |
#-- it under the terms of the GNU Lesser General Public License as published by -- |
#-- the Free Software Foundation; either version 2.1 of the License, or -- |
#-- (at your option) any later version. -- |
#-- -- |
#-- HPC-16 is distributed in the hope that it will be useful, -- |
#-- but WITHOUT ANY WARRANTY; without even the implied warranty of -- |
#-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- |
#-- GNU Lesser General Public License for more details. -- |
#-- -- |
#-- You should have received a copy of the GNU Lesser General Public License -- |
#-- along with HPC-16; if not, write to the Free Software -- |
#-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -- |
#-- -- |
#------------------------------------------------------------------------------------ |
|
from __future__ import print_function |
import sys |
import os |
import re |
from antlr4 import * |
from HPC16Lexer import HPC16Lexer |
from HPC16Parser import HPC16Parser |
from MyHPC16Listener import MyHPC16Listener |
from antlr4.error.ErrorStrategy import BailErrorStrategy |
from antlr4.error.Errors import * |
|
def start(): |
if len(sys.argv) < 2: |
usage() |
sys.exit(1) |
input_stream = FileStream(sys.argv[1]) |
a, _ = os.path.splitext(os.path.basename(sys.argv[1])) |
fout_name = a + "_asm_out.txt" |
|
fout = open(fout_name, 'w') |
|
lexer = HPC16Lexer(input_stream) |
|
token_stream = CommonTokenStream(lexer) |
parser = HPC16Parser(token_stream) |
parser._errHandler = BailErrorStrategy() |
|
try : |
tree = parser.prog() |
walker = ParseTreeWalker() |
walker.walk(MyHPC16Listener(fout), tree) |
except ParseCancellationException, e: |
print(sys.argv[0], "\nERROR Found invalid instruction\n in:", sys.argv[1], file=sys.stderr) |
fout.close() |
else: |
fout.close() |
mkrom_vhdl_sim(fout_name, a + "_init_ram.txt") |
|
|
|
def mkrom_vhdl_sim(fin_name , fout_name): |
fin = open(fin_name, 'r') |
fout = open(fout_name, 'w') |
lc = 0 |
for line in fin: |
if not re.match("^#", line): |
b = "{:#018b}".format(int(line, 16)) |
s = str(lc) + ":" + b[2:] |
print(s, file=fout) |
lc = lc + 1 |
|
fin.close() |
fout.close() |
|
|
def usage(): |
print("usage:\n", sys.argv[0], "<input file>\n", file=sys.stderr) |
|
|
|
if __name__ == '__main__': |
start() |
|
|
|
|
trunk/impl0/asm/HPC16_asm.py
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/impl0/asm/HPC16.g4
===================================================================
--- trunk/impl0/asm/HPC16.g4 (nonexistent)
+++ trunk/impl0/asm/HPC16.g4 (revision 18)
@@ -0,0 +1,162 @@
+/*
+#--------------------------------------------------------------
+#-- HPC-16 Assembler
+#--------------------------------------------------------------
+#-- project: HPC-16 Microprocessor
+#--
+#-- ANTLR4 grammar on HPC-16 Assembler
+#--
+#--
+#--
+#-- Author: M. Umair Siddiqui (umairsiddiqui@opencores.org)
+#---------------------------------------------------------------
+#------------------------------------------------------------------------------------
+#-- --
+#-- Copyright (c) 2015, M. Umair Siddiqui all rights reserved --
+#-- --
+#-- This file is part of HPC-16. --
+#-- --
+#-- HPC-16 is free software; you can redistribute it and/or modify --
+#-- it under the terms of the GNU Lesser General Public License as published by --
+#-- the Free Software Foundation; either version 2.1 of the License, or --
+#-- (at your option) any later version. --
+#-- --
+#-- HPC-16 is distributed in the hope that it will be useful, --
+#-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
+#-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
+#-- GNU Lesser General Public License for more details. --
+#-- --
+#-- You should have received a copy of the GNU Lesser General Public License --
+#-- along with HPC-16; if not, write to the Free Software --
+#-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
+#-- --
+#------------------------------------------------------------------------------------
+*/
+
+grammar HPC16;
+
+prog : stat+;
+
+stat : asm_inst? NEWLINE;
+
+asm_inst : 'mov' REG ',' REG # mov_reg_reg
+ | 'mov' STK_PTR ',' REG # mov_sp_reg
+ | 'mov' REG ',' STK_PTR # mov_reg_sp
+ | 'ld' REG ',' '(' REG ')' # ld_reg_reg
+ | 'ld' REG ',' '(' REG '+' IMM ')' # ld_reg_reg_imm16
+ | 'ld' REG ',' '(' STK_PTR ')' # ld_reg_sp
+ | 'ld' REG ',' '(' STK_PTR '+' IMM ')' # ld_reg_sp_imm16
+ | 'st' REG ',' '(' REG ')' # st_reg_reg
+ | 'st' REG ',' '(' REG '+' IMM ')' # st_reg_reg_imm16
+ | 'st' REG ',' '(' STK_PTR ')' # st_reg_sp
+ | 'st' REG ',' '(' STK_PTR '+' IMM ')' # st_reg_sp_imm16
+ | 'lbzx' REG ',' '(' REG ')' # lbzx_reg_reg
+ | 'lbzx' REG ',' '(' REG '+' IMM ')' # lbzx_reg_reg_imm16
+ | 'lbsx' REG ',' '(' REG ')' # lbsx_reg_reg
+ | 'lbsx' REG ',' '(' REG '+' IMM ')' # lbsx_reg_reg_imm16
+ | 'sb' REG ',' '(' REG ')' # sb_reg_reg
+ | 'sb' REG ',' '(' REG '+' IMM ')' # sb_reg_reg_imm16
+ | 'li' REG ',' IMM # li_reg_imm16
+ | 'li' STK_PTR ',' IMM # li_sp_imm16
+ | 'inc' REG # inc_reg
+ | 'dec' REG # dec_reg
+ | 'sub' REG ',' REG # sub_reg_reg
+ | 'and' REG ',' REG # and_reg_reg
+ | 'add' REG ',' REG # add_reg_reg
+ | 'adc' REG ',' REG # adc_reg_reg
+ | 'sbb' REG ',' REG # sbb_reg_reg
+ | 'or' REG ',' REG # or_reg_reg
+ | 'xor' REG ',' REG # xor_reg_reg
+ | 'not' REG # not_reg
+ | 'sub' REG ',' IMM # sub_reg_imm16
+ | 'and' REG ',' IMM # and_reg_imm16
+ | 'add' REG ',' IMM # add_reg_imm16
+ | 'adc' REG ',' IMM # adc_reg_imm16
+ | 'sbb' REG ',' IMM # sbb_reg_imm16
+ | 'or' REG ',' IMM # or_reg_imm16
+ | 'xor' REG ',' IMM # xor_reg_imm16
+ | 'add' STK_PTR ',' IMM # add_sp_imm16
+ | 'sub' STK_PTR ',' IMM # sub_sp_imm16
+ | 'cmp' REG ',' REG # cmp_reg_reg
+ | 'test' REG ',' REG # test_reg_reg
+ | 'cmp' REG ',' IMM # cmp_reg_imm16
+ | 'test' REG ',' IMM # test_reg_imm16
+ | 'sll' REG ',' REG # sll_reg_reg
+ | 'slr' REG ',' REG # slr_reg_reg
+ | 'sal' REG ',' REG # sal_reg_reg
+ | 'sar' REG ',' REG # sar_reg_reg
+ | 'rol' REG ',' REG # rol_reg_reg
+ | 'ror' REG ',' REG # ror_reg_reg
+ | 'rcl' REG ',' REG # rcl_reg_reg
+ | 'rcr' REG ',' REG # rcr_reg_reg
+ | 'sll' REG ',' IMM # sll_reg_imm4
+ | 'slr' REG ',' IMM # slr_reg_imm4
+ | 'sal' REG ',' IMM # sal_reg_imm4
+ | 'sar' REG ',' IMM # sar_reg_imm4
+ | 'rol' REG ',' IMM # rol_reg_imm4
+ | 'ror' REG ',' IMM # ror_reg_imm4
+ | 'rcl' REG ',' IMM # rcl_reg_imm4
+ | 'rcr' REG ',' IMM # rcr_reg_imm4
+ | 'push' REG # push_reg
+ | 'pushf' # pushf
+ | 'pop' REG # pop_reg
+ | 'popf' # popf
+ | 'acall' '(' REG ')' # acall_reg
+ | 'call' '(' REG ')' # call_reg
+ | 'call' '(' IMM ')' # call_imm11
+ | 'ret' # ret
+ | 'iret' # iret
+ | 'clc' # clc
+ | 'stc' # stc
+ | 'cmc' # cmc
+ | 'cli' # cli
+ | 'sti' # sti
+ | 'int' IMM # int_imm4
+ | 'into' # into
+ | 'ajmp' '(' REG ')' # ajmp
+ | 'jmp' '(' REG ')' # jmp_reg
+ | 'jmp' '(' IMM ')' # jmp_imm11
+ | 'nop' # nop
+ | 'hlt' # halt
+ | 'jo' IMM # jo_imm7
+ | 'jno' IMM # jno_imm7
+ | 'jb' IMM # jb_imm7
+ | 'jnae' IMM # jnae_imm7
+ | 'jnb' IMM # jnb_imm7
+ | 'jae' IMM # jae_imm7
+ | 'je' IMM # je_imm7
+ | 'jz' IMM # jz_imm7
+ | 'jne' IMM # jne_imm7
+ | 'jnz' IMM # jnz_imm7
+ | 'jbe' IMM # jbe_imm7
+ | 'jna' IMM # jna_imm7
+ | 'jnbe' IMM # jnbe_imm7
+ | 'ja' IMM # ja_imm7
+ | 'js' IMM # js_imm7
+ | 'jns' IMM # jns_imm7
+ | 'jl' IMM # jl_imm7
+ | 'jnge' IMM # jnge_imm7
+ | 'jnl' IMM # jnl_imm7
+ | 'jge' IMM # jge_imm7
+ | 'jle' IMM # jle_imm7
+ | 'jng' IMM # jng_imm7
+ | 'jnle' IMM # jnle_imm7
+ | 'jg' IMM # jg_imm7
+ ;
+
+REG : [Rr][0-9]+;
+
+IMM : [0-9]+
+ | '0x'[0-9a-fA-F]+
+ ;
+
+STK_PTR : 'SP'
+ | 'sp'
+ ;
+
+WS : [ \t]+ -> skip ;
+LINE_COMMENT : '#' .*? '\r'? '\n' -> skip ; // Match "#" stuff '\n'
+NEWLINE : '\r'?'\n';
+
+
+
Index: trunk/impl0/asm/readme.txt
===================================================================
--- trunk/impl0/asm/readme.txt (revision 17)
+++ trunk/impl0/asm/readme.txt (revision 18)
@@ -1,2 +1,43 @@
in this directory, i will put assembly programs.
-correspoinding "_init_ram.txt" will be in /sim directory
\ No newline at end of file
+put corresponding "_init_ram.txt" in /sim directory for VHDL simulation
+
+=============================================================
+HPC-16 Assembler
+-------------------
+HPC-16 Assembler written in python, so to run it you will need to install Python 2.7.
+also it will requires following python module:
+
+antlr4-python2-runtime
+
+(for both linux & windows)
+pip install antlr4-python2-runtime
+
+
+usage:
+
+./HPC16_asm.py
+
+generates
+
+1) *_init_ram.txt --- For VHDL simulation
+2) *_asm_out.txt --- For Debugging
+
+
+
+TODO:
+assembler is very basic. need to add more features
+
+
+The antlr4 grammar file (HPC16.g4) is also committed.
+
+basic setup is following
+
+export CLASSPATH=".:/antlr_jar_path/antlr-4.5.1-complete.jar:$CLASSPATH"
+
+java -jar /antlr_jar_path/antlr-4.5.1-complete.jar -Dlanguage=Python2 HPC16.g4
+
+See further info at http://www.antlr.org
+
+=====================================================================================
+
+
Index: trunk/impl0/asm/HPC16Listener.py
===================================================================
--- trunk/impl0/asm/HPC16Listener.py (nonexistent)
+++ trunk/impl0/asm/HPC16Listener.py (revision 18)
@@ -0,0 +1,951 @@
+# Generated from HPC16.g4 by ANTLR 4.5.1
+from antlr4 import *
+
+# This class defines a complete listener for a parse tree produced by HPC16Parser.
+class HPC16Listener(ParseTreeListener):
+
+ # Enter a parse tree produced by HPC16Parser#prog.
+ def enterProg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#prog.
+ def exitProg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#stat.
+ def enterStat(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#stat.
+ def exitStat(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#mov_reg_reg.
+ def enterMov_reg_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#mov_reg_reg.
+ def exitMov_reg_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#mov_sp_reg.
+ def enterMov_sp_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#mov_sp_reg.
+ def exitMov_sp_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#mov_reg_sp.
+ def enterMov_reg_sp(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#mov_reg_sp.
+ def exitMov_reg_sp(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#ld_reg_reg.
+ def enterLd_reg_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#ld_reg_reg.
+ def exitLd_reg_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#ld_reg_reg_imm16.
+ def enterLd_reg_reg_imm16(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#ld_reg_reg_imm16.
+ def exitLd_reg_reg_imm16(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#ld_reg_sp.
+ def enterLd_reg_sp(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#ld_reg_sp.
+ def exitLd_reg_sp(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#ld_reg_sp_imm16.
+ def enterLd_reg_sp_imm16(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#ld_reg_sp_imm16.
+ def exitLd_reg_sp_imm16(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#st_reg_reg.
+ def enterSt_reg_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#st_reg_reg.
+ def exitSt_reg_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#st_reg_reg_imm16.
+ def enterSt_reg_reg_imm16(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#st_reg_reg_imm16.
+ def exitSt_reg_reg_imm16(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#st_reg_sp.
+ def enterSt_reg_sp(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#st_reg_sp.
+ def exitSt_reg_sp(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#st_reg_sp_imm16.
+ def enterSt_reg_sp_imm16(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#st_reg_sp_imm16.
+ def exitSt_reg_sp_imm16(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#lbzx_reg_reg.
+ def enterLbzx_reg_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#lbzx_reg_reg.
+ def exitLbzx_reg_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#lbzx_reg_reg_imm16.
+ def enterLbzx_reg_reg_imm16(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#lbzx_reg_reg_imm16.
+ def exitLbzx_reg_reg_imm16(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#lbsx_reg_reg.
+ def enterLbsx_reg_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#lbsx_reg_reg.
+ def exitLbsx_reg_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#lbsx_reg_reg_imm16.
+ def enterLbsx_reg_reg_imm16(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#lbsx_reg_reg_imm16.
+ def exitLbsx_reg_reg_imm16(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#sb_reg_reg.
+ def enterSb_reg_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#sb_reg_reg.
+ def exitSb_reg_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#sb_reg_reg_imm16.
+ def enterSb_reg_reg_imm16(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#sb_reg_reg_imm16.
+ def exitSb_reg_reg_imm16(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#li_reg_imm16.
+ def enterLi_reg_imm16(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#li_reg_imm16.
+ def exitLi_reg_imm16(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#li_sp_imm16.
+ def enterLi_sp_imm16(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#li_sp_imm16.
+ def exitLi_sp_imm16(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#inc_reg.
+ def enterInc_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#inc_reg.
+ def exitInc_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#dec_reg.
+ def enterDec_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#dec_reg.
+ def exitDec_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#sub_reg_reg.
+ def enterSub_reg_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#sub_reg_reg.
+ def exitSub_reg_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#and_reg_reg.
+ def enterAnd_reg_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#and_reg_reg.
+ def exitAnd_reg_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#add_reg_reg.
+ def enterAdd_reg_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#add_reg_reg.
+ def exitAdd_reg_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#adc_reg_reg.
+ def enterAdc_reg_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#adc_reg_reg.
+ def exitAdc_reg_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#sbb_reg_reg.
+ def enterSbb_reg_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#sbb_reg_reg.
+ def exitSbb_reg_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#or_reg_reg.
+ def enterOr_reg_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#or_reg_reg.
+ def exitOr_reg_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#xor_reg_reg.
+ def enterXor_reg_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#xor_reg_reg.
+ def exitXor_reg_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#not_reg.
+ def enterNot_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#not_reg.
+ def exitNot_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#sub_reg_imm16.
+ def enterSub_reg_imm16(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#sub_reg_imm16.
+ def exitSub_reg_imm16(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#and_reg_imm16.
+ def enterAnd_reg_imm16(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#and_reg_imm16.
+ def exitAnd_reg_imm16(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#add_reg_imm16.
+ def enterAdd_reg_imm16(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#add_reg_imm16.
+ def exitAdd_reg_imm16(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#adc_reg_imm16.
+ def enterAdc_reg_imm16(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#adc_reg_imm16.
+ def exitAdc_reg_imm16(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#sbb_reg_imm16.
+ def enterSbb_reg_imm16(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#sbb_reg_imm16.
+ def exitSbb_reg_imm16(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#or_reg_imm16.
+ def enterOr_reg_imm16(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#or_reg_imm16.
+ def exitOr_reg_imm16(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#xor_reg_imm16.
+ def enterXor_reg_imm16(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#xor_reg_imm16.
+ def exitXor_reg_imm16(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#add_sp_imm16.
+ def enterAdd_sp_imm16(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#add_sp_imm16.
+ def exitAdd_sp_imm16(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#sub_sp_imm16.
+ def enterSub_sp_imm16(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#sub_sp_imm16.
+ def exitSub_sp_imm16(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#cmp_reg_reg.
+ def enterCmp_reg_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#cmp_reg_reg.
+ def exitCmp_reg_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#test_reg_reg.
+ def enterTest_reg_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#test_reg_reg.
+ def exitTest_reg_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#cmp_reg_imm16.
+ def enterCmp_reg_imm16(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#cmp_reg_imm16.
+ def exitCmp_reg_imm16(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#test_reg_imm16.
+ def enterTest_reg_imm16(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#test_reg_imm16.
+ def exitTest_reg_imm16(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#sll_reg_reg.
+ def enterSll_reg_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#sll_reg_reg.
+ def exitSll_reg_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#slr_reg_reg.
+ def enterSlr_reg_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#slr_reg_reg.
+ def exitSlr_reg_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#sal_reg_reg.
+ def enterSal_reg_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#sal_reg_reg.
+ def exitSal_reg_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#sar_reg_reg.
+ def enterSar_reg_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#sar_reg_reg.
+ def exitSar_reg_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#rol_reg_reg.
+ def enterRol_reg_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#rol_reg_reg.
+ def exitRol_reg_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#ror_reg_reg.
+ def enterRor_reg_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#ror_reg_reg.
+ def exitRor_reg_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#rcl_reg_reg.
+ def enterRcl_reg_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#rcl_reg_reg.
+ def exitRcl_reg_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#rcr_reg_reg.
+ def enterRcr_reg_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#rcr_reg_reg.
+ def exitRcr_reg_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#sll_reg_imm4.
+ def enterSll_reg_imm4(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#sll_reg_imm4.
+ def exitSll_reg_imm4(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#slr_reg_imm4.
+ def enterSlr_reg_imm4(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#slr_reg_imm4.
+ def exitSlr_reg_imm4(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#sal_reg_imm4.
+ def enterSal_reg_imm4(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#sal_reg_imm4.
+ def exitSal_reg_imm4(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#sar_reg_imm4.
+ def enterSar_reg_imm4(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#sar_reg_imm4.
+ def exitSar_reg_imm4(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#rol_reg_imm4.
+ def enterRol_reg_imm4(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#rol_reg_imm4.
+ def exitRol_reg_imm4(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#ror_reg_imm4.
+ def enterRor_reg_imm4(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#ror_reg_imm4.
+ def exitRor_reg_imm4(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#rcl_reg_imm4.
+ def enterRcl_reg_imm4(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#rcl_reg_imm4.
+ def exitRcl_reg_imm4(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#rcr_reg_imm4.
+ def enterRcr_reg_imm4(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#rcr_reg_imm4.
+ def exitRcr_reg_imm4(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#push_reg.
+ def enterPush_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#push_reg.
+ def exitPush_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#pushf.
+ def enterPushf(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#pushf.
+ def exitPushf(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#pop_reg.
+ def enterPop_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#pop_reg.
+ def exitPop_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#popf.
+ def enterPopf(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#popf.
+ def exitPopf(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#acall_reg.
+ def enterAcall_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#acall_reg.
+ def exitAcall_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#call_reg.
+ def enterCall_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#call_reg.
+ def exitCall_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#call_imm11.
+ def enterCall_imm11(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#call_imm11.
+ def exitCall_imm11(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#ret.
+ def enterRet(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#ret.
+ def exitRet(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#iret.
+ def enterIret(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#iret.
+ def exitIret(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#clc.
+ def enterClc(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#clc.
+ def exitClc(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#stc.
+ def enterStc(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#stc.
+ def exitStc(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#cmc.
+ def enterCmc(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#cmc.
+ def exitCmc(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#cli.
+ def enterCli(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#cli.
+ def exitCli(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#sti.
+ def enterSti(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#sti.
+ def exitSti(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#int_imm4.
+ def enterInt_imm4(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#int_imm4.
+ def exitInt_imm4(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#into.
+ def enterInto(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#into.
+ def exitInto(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#ajmp.
+ def enterAjmp(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#ajmp.
+ def exitAjmp(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#jmp_reg.
+ def enterJmp_reg(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#jmp_reg.
+ def exitJmp_reg(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#jmp_imm11.
+ def enterJmp_imm11(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#jmp_imm11.
+ def exitJmp_imm11(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#nop.
+ def enterNop(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#nop.
+ def exitNop(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#halt.
+ def enterHalt(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#halt.
+ def exitHalt(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#jo_imm7.
+ def enterJo_imm7(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#jo_imm7.
+ def exitJo_imm7(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#jno_imm7.
+ def enterJno_imm7(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#jno_imm7.
+ def exitJno_imm7(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#jb_imm7.
+ def enterJb_imm7(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#jb_imm7.
+ def exitJb_imm7(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#jnae_imm7.
+ def enterJnae_imm7(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#jnae_imm7.
+ def exitJnae_imm7(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#jnb_imm7.
+ def enterJnb_imm7(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#jnb_imm7.
+ def exitJnb_imm7(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#jae_imm7.
+ def enterJae_imm7(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#jae_imm7.
+ def exitJae_imm7(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#je_imm7.
+ def enterJe_imm7(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#je_imm7.
+ def exitJe_imm7(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#jz_imm7.
+ def enterJz_imm7(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#jz_imm7.
+ def exitJz_imm7(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#jne_imm7.
+ def enterJne_imm7(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#jne_imm7.
+ def exitJne_imm7(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#jnz_imm7.
+ def enterJnz_imm7(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#jnz_imm7.
+ def exitJnz_imm7(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#jbe_imm7.
+ def enterJbe_imm7(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#jbe_imm7.
+ def exitJbe_imm7(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#jna_imm7.
+ def enterJna_imm7(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#jna_imm7.
+ def exitJna_imm7(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#jnbe_imm7.
+ def enterJnbe_imm7(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#jnbe_imm7.
+ def exitJnbe_imm7(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#ja_imm7.
+ def enterJa_imm7(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#ja_imm7.
+ def exitJa_imm7(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#js_imm7.
+ def enterJs_imm7(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#js_imm7.
+ def exitJs_imm7(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#jns_imm7.
+ def enterJns_imm7(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#jns_imm7.
+ def exitJns_imm7(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#jl_imm7.
+ def enterJl_imm7(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#jl_imm7.
+ def exitJl_imm7(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#jnge_imm7.
+ def enterJnge_imm7(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#jnge_imm7.
+ def exitJnge_imm7(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#jnl_imm7.
+ def enterJnl_imm7(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#jnl_imm7.
+ def exitJnl_imm7(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#jge_imm7.
+ def enterJge_imm7(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#jge_imm7.
+ def exitJge_imm7(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#jle_imm7.
+ def enterJle_imm7(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#jle_imm7.
+ def exitJle_imm7(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#jng_imm7.
+ def enterJng_imm7(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#jng_imm7.
+ def exitJng_imm7(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#jnle_imm7.
+ def enterJnle_imm7(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#jnle_imm7.
+ def exitJnle_imm7(self, ctx):
+ pass
+
+
+ # Enter a parse tree produced by HPC16Parser#jg_imm7.
+ def enterJg_imm7(self, ctx):
+ pass
+
+ # Exit a parse tree produced by HPC16Parser#jg_imm7.
+ def exitJg_imm7(self, ctx):
+ pass
+
+
Index: trunk/common/docs/HPC-16_instruction_ref_manual.doc
===================================================================
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