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  • This comparison shows the changes necessary to convert path 
    /i650/trunk
    from Rev 9 to Rev 10
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Rev 9 → Rev 10

/rtl/xlate5to7.v
34,20 → 34,20
output reg[0:6] out_7
);
 
always @(*) begin
case (in_5)
`drum2of5_0 : out_7 = `biq_0;
`drum2of5_1 : out_7 = `biq_1;
`drum2of5_2 : out_7 = `biq_2;
`drum2of5_3 : out_7 = `biq_3;
`drum2of5_4 : out_7 = `biq_4;
`drum2of5_5 : out_7 = `biq_5;
`drum2of5_6 : out_7 = `biq_6;
`drum2of5_7 : out_7 = `biq_7;
`drum2of5_8 : out_7 = `biq_8;
`drum2of5_9 : out_7 = `biq_9;
default : out_7 = `biq_blank; // invalid codes become all zeroes
endcase;
end;
always @(*) begin
case (in_5)
`drum2of5_0 : out_7 = `biq_0;
`drum2of5_1 : out_7 = `biq_1;
`drum2of5_2 : out_7 = `biq_2;
`drum2of5_3 : out_7 = `biq_3;
`drum2of5_4 : out_7 = `biq_4;
`drum2of5_5 : out_7 = `biq_5;
`drum2of5_6 : out_7 = `biq_6;
`drum2of5_7 : out_7 = `biq_7;
`drum2of5_8 : out_7 = `biq_8;
`drum2of5_9 : out_7 = `biq_9;
default : out_7 = `biq_blank; // invalid codes become all zeroes
endcase;
end;
 
endmodule
/rtl/xlate7to5.v
34,19 → 34,19
output reg[0:4] out_5
);
 
always @(*) begin
case (in_7)
`biq_0 : out_5 = `drum2of5_0;
`biq_1 : out_5 = `drum2of5_1;
`biq_2 : out_5 = `drum2of5_2;
`biq_3 : out_5 = `drum2of5_3;
`biq_4 : out_5 = `drum2of5_4;
`biq_5 : out_5 = `drum2of5_5;
`biq_6 : out_5 = `drum2of5_6;
`biq_7 : out_5 = `drum2of5_7;
`biq_8 : out_5 = `drum2of5_8;
`biq_9 : out_5 = `drum2of5_9;
default : out_5 = `drum2of5_blank; // invalid codes become zeroes
endcase;
end;
always @(*) begin
case (in_7)
`biq_0 : out_5 = `drum2of5_0;
`biq_1 : out_5 = `drum2of5_1;
`biq_2 : out_5 = `drum2of5_2;
`biq_3 : out_5 = `drum2of5_3;
`biq_4 : out_5 = `drum2of5_4;
`biq_5 : out_5 = `drum2of5_5;
`biq_6 : out_5 = `drum2of5_6;
`biq_7 : out_5 = `drum2of5_7;
`biq_8 : out_5 = `drum2of5_8;
`biq_9 : out_5 = `drum2of5_9;
default : out_5 = `drum2of5_blank; // invalid codes become zeroes
endcase;
end;
endmodule
/rtl/operator_ctl.v
43,7 → 43,7
output reg[0:6] data_out, addr_out,
output reg console_to_addr,
output reg[0:14] gs_ram_addr,
output reg read_gs, write_gs,
output reg read_gs, write_gs,
output reg pgm_start, pgm_stop, err_reset, err_sense_reset,
output run_control, half_or_pgm_stop, ri_storage, ro_storage,
storage_control,
77,7 → 77,7
reg [0:6] gs_addr_th, gs_addr_h, gs_addr_t, gs_addr_u;
wire [0:14] gs_band_addr;
wire [0:9] gs_word_offset;
wire [0:9] gs_word_offset;
ram_band_addr rba(gs_addr_th, gs_addr_h, gs_addr_t, gs_band_addr);
ram_word_offset rwo(gs_addr_t, gs_addr_u, gs_word_offset);
wire [0:14] gs_word_addr = gs_band_addr + gs_word_offset;
111,7 → 111,7
`define state_read_gs_2 6'd32
`define state_read_gs_3 6'd33
`define state_read_gs_4 6'd34
`define state_read_gs_5 6'd35
`define state_read_gs_5 6'd35
//-----------------------------------------------------------------------------
// Operator console state machine
159,7 → 159,7
gs_ram_addr <= 15'd0;
read_gs <= 0;
write_gs <= 0;
write_gs <= 0;
end else begin
case (state)
`state_idle: begin
397,44 → 397,44
state <= `state_read_gs_1;
end
end
 
`cmd_write_gs: begin
end
end
`cmd_read_acc: begin
end
end
`cmd_read_dist: begin
end
end
`cmd_read_prog: begin
end
// 0 : Ignore if not in manual
// Clear gs_ram_addr
// 1 : Synchronize with d10
// Turn on console_write_gs
// 2 : Put a digit:
// dx: blank
// d0: minus
// d1-d10: zero
// gs_ram_addr++
end
// 0 : Ignore if not in manual
// Clear gs_ram_addr
// 1 : Synchronize with d10
// Turn on console_write_gs
// 2 : Put a digit:
// dx: blank
// d0: minus
// d1-d10: zero
// gs_ram_addr++
`cmd_clear_gs: begin
end
end
`cmd_load_gs: begin
end
end
`cmd_dump_gs: begin
end
end
`cmd_power_on_reset: begin
end
end
`cmd_reset_console: begin
end
end
endcase;
end
620,12 → 620,12
gs_ram_addr <= gs_word_addr;
state <= `state_read_gs_4;
end
`state_read_gs_4: begin
state <= `state_read_gs_5;
end
`state_read_gs_4: begin
state <= `state_read_gs_5;
end
endcase;
end
end;
/rtl/gen_store.v
8,9 → 8,9
// Description: General storage.
//
// Additional Comments: Drum storage is implemented as an array of 24000 5-bit
// digits. An array address is formed by decoding the static portion of the
// bi-quinary address into an origin (a multiple of 600), then adding the
// dynamic portion of the address (range 0..599).
// digits. An array address is formed by decoding the static portion of the
// bi-quinary address into an origin (a multiple of 600), then adding the
// dynamic portion of the address (range 0..599).
//
// Copyright (c) 2015 Robert Abeles
//
33,43 → 33,43
`include "defines.v"
 
module gen_store (
input rst,
input ap, dp,
input rst,
input ap, dp,
input write_gate,
input [0:6] addr_th, addr_h, addr_t,
input [0:9] dynamic_addr,
input [0:6] addr_th, addr_h, addr_t,
input [0:9] dynamic_addr,
input [0:4] gs_in,
input [0:14] console_ram_addr,
input console_read_gs, console_write_gs,
input [0:14] console_ram_addr,
input console_read_gs, console_write_gs,
output reg[0:4] gs_out,
output double_write, no_write
);
 
reg [0:4] gs_mem [0:32767]; // Rounded size up from 24000 to next 2^n.
reg [0:4] gs_mem [0:32767]; // Rounded size up from 24000 to next 2^n.
//-----------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
wire [0:14] band_addr, gs_addr, gs_addr_early;
ram_band_addr rba(addr_th, addr_h, addr_t, band_addr);
wire console_access = console_read_gs | console_write_gs;
assign gs_addr = console_access? console_ram_addr : (band_addr + dynamic_addr);
assign gs_addr_early = (band_addr + ((dynamic_addr + 1) % 600)) % 32768;
assign double_write = 0;
assign no_write = 0;
always @(posedge ap) begin
if (rst) begin
gs_out <= `biq_blank;
end else begin
gs_out <= gs_mem[gs_addr];
end
end;
always @(posedge dp) begin
if (write_gate)
gs_mem[gs_addr_early] <= gs_in;
end;
wire [0:14] band_addr, gs_addr, gs_addr_early;
ram_band_addr rba(addr_th, addr_h, addr_t, band_addr);
wire console_access = console_read_gs | console_write_gs;
assign gs_addr = console_access? console_ram_addr : (band_addr + dynamic_addr);
assign gs_addr_early = (band_addr + ((dynamic_addr + 1) % 600)) % 32768;
assign double_write = 0;
assign no_write = 0;
always @(posedge ap) begin
if (rst) begin
gs_out <= `biq_blank;
end else begin
gs_out <= gs_mem[gs_addr];
end
end;
always @(posedge dp) begin
if (write_gate)
gs_mem[gs_addr_early] <= gs_in;
end;
endmodule

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