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  • This comparison shows the changes necessary to convert path 
    /i650/trunk
    from Rev 12 to Rev 13
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Rev 12 → Rev 13

/rtl/operator_ctl.v
121,11 → 121,17
`define state_read_gs_4 6'd33
`define state_read_gs_5 6'd34
`define state_read_gs_6 6'd35
`define state_write_gs_1 6'd36
`define state_write_gs_2 6'd37
`define state_write_gs_3 6'd38
`define state_write_gs_4 6'd39
`define state_write_gs_5 6'd40
`define state_clear_drum_1 6'd41
`define state_clear_drum_2 6'd42
`define state_clear_drum_3 6'd43
`define state_load_gs_1 6'd44
`define state_load_gs_1 6'd45
`define state_clear_drum_1 6'd50
`define state_clear_drum_2 6'd51
`define state_clear_drum_3 6'd52
always @(posedge clk) begin
if (rst) begin
console_to_addr <= 0;
199,7 → 205,6
state <= `state_reset_console_1;
end else if (do_clear_drum) begin
do_clear_drum <= 0;
gs_ram_addr <= 15'd0;
state <= `state_clear_drum_1;
end else if (do_pgm_reset) begin
do_pgm_reset <= 0;
429,11 → 434,28
end
end
 
// Write word to general storage:
// --> 4 digits address, little-endian
// <-- dx digit, sign digit, d1-d10
// 0: Ignore if not in manual
// 1: Readin low-order addr digit
// 2: Readin remaining addr digits
// 3: Synchronize with d10
// digit_ready <- 1
// 4: Readin first digit
// 5: Write digit
// Readin next digit
// 6: Cleanup
`cmd_write_gs: begin
if (ctl_sw_manual) begin
busy <= 1;
state <= `state_write_gs_1;
end
end
end
`cmd_read_acc: begin
end
`cmd_read_dist: begin
459,6 → 481,11
end
`cmd_load_gs: begin
if (ctl_sw_manual) begin
busy <= 1;
state <= `state_load_gs_1;
digit_ready <= 1;
end
end
`cmd_dump_gs: begin
465,9 → 492,13
end
`cmd_power_on_reset: begin
busy <= 1;
do_power_on_reset <= 1;
end
`cmd_reset_console: begin
busy <= 1;
do_reset_console <= 1;
end
`cmd_hard_reset: begin
690,6 → 721,60
state <= `state_idle;
end
// Write word to general storage:
// --> 4 digits address, little-endian
// <-- dx digit, sign digit, d1-d10
// 0: Ignore if not in manual
// 1: Readin low-order addr digit
// 2: Readin remaining addr digits
// 3: Synchronize with d10
// digit_ready <- 1
// 4: Readin and write digit
// 5: Write digit
// Readin next digit
// 6: Cleanup
`state_write_gs_1: begin
if (dx) begin
state <= `state_write_gs_2;
digit_ready <= 1;
gs_addr_u <= cmd_digit_in;
end
end
`state_write_gs_2: begin
if (d0) gs_addr_t <= cmd_digit_in;
else if (d1) gs_addr_h <= cmd_digit_in;
else if (d2) begin
gs_addr_th <= cmd_digit_in;
state <= `state_write_gs_3;
digit_ready <= 0;
end
end
`state_write_gs_3: begin
if (d10) begin
gs_ram_addr <= gs_word_addr;
digit_ready <= 1;
state <= `state_write_gs_4;
end
end
`state_write_gs_4: begin
write_gs <= 1;
console_out <= cmd_digit_in;
gs_ram_addr <= gs_ram_addr + 1;
if (d10) begin
digit_ready <= 0;
state <= `state_write_gs_5;
end
end
`state_write_gs_5: begin
write_gs <= 0;
state <= `state_idle;
end
// 0 : Ignore if not in manual
// Clear gs_ram_addr
// 1 : Synchronize with d10
701,17 → 786,18
// gs_ram_addr++
`state_clear_drum_1: begin
if (d10) begin
console_out <= `biq_blank;
gs_ram_addr <= 15'd0;
write_gs <= 1;
state <= `state_clear_drum_2;
end
end
`state_clear_drum_2: begin
write_gs <= 1;
console_out <= dx? `biq_blank
: d0? `biq_minus
: `biq_0;
if (write_gs)
gs_ram_addr <= gs_ram_addr + 1;
gs_ram_addr <= gs_ram_addr + 1;
if (gs_ram_addr == 15'd23999) begin
write_gs <= 0;
state <= `state_idle;
718,6 → 804,23
end
end
`state_load_gs_1: begin
gs_ram_addr <= 15'd0;
write_gs <= 1;
console_out <= cmd_digit_in;
state <= `state_load_gs_2;
end
`state_load_gs_2: begin
gs_ram_addr <= gs_ram_addr + 1;
console_out <= cmd_digit_in;
if (gs_ram_addr == 15d'23999) begin
write_gs <= 0;
digit_ready <= 0;
state <= `state_idle;
end
end
endcase;
end
end;
/rtl/toplev.v
34,27 → 34,27
input clk,
input rst,
 
input [0:6] cmd_digit_in, io_buffer_in,
input [0:5] command,
input [0:6] cmd_digit_in, io_buffer_in,
input [0:5] command,
 
output [0:6] cmd_digit_out,
output busy, digit_ready, punch_card, read_card, card_digit_ready,
output [0:6] cmd_digit_out,
output busy, digit_ready, punch_card, read_card, card_digit_ready,
output synch
);
wire ap, bp, cp, dp;
wire dx, d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10,
d1_d5, d5_dx, d5_d10, d1_dx, d5_d9, d10_d1_d5,
dxl, dxu, d0l, d0u, d1l, d1u, d2l, d10u;
wire w0, w1, w2, w3, w4, w5, w6, w7, w8, w9,
wl, wu, ewl;
wire s0, s1, s2, s3, s4, hp;
wire [0:9] digit_idx;
wire [0:3] early_idx, ontime_idx;
wire ap, bp, cp, dp;
wire dx, d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10,
d1_d5, d5_dx, d5_d10, d1_dx, d5_d9, d10_d1_d5,
dxl, dxu, d0l, d0u, d1l, d1u, d2l, d10u;
wire w0, w1, w2, w3, w4, w5, w6, w7, w8, w9,
wl, wu, ewl;
wire s0, s1, s2, s3, s4, hp;
wire [0:9] digit_idx;
wire [0:3] early_idx, ontime_idx;
assign synch = bp;
timing tm (
timing tm (
.clk(clk),
.rst(rst),
.ap(ap),
110,34 → 110,34
.early_idx(early_idx),
.ontime_idx(ontime_idx)
);
//-----------------------------------------------------------------------------
// General storage
//-----------------------------------------------------------------------------
wire [0:4] gs_out;
wire gs_double_write, gs_no_write;
wire [0:4] gs_out;
wire gs_double_write, gs_no_write;
//-----------------------------------------------------------------------------
// Operator controls
//-----------------------------------------------------------------------------
wire [0:6] oc_data_out, oc_addr_out, oc_console_out;
wire oc_console_to_addr;
wire [0:14] oc_gs_ram_addr;
wire oc_read_gs, oc_write_gs;
wire oc_pgm_start, oc_pgm_stop, oc_err_reset, oc_err_sense_reset;
wire oc_run_control, oc_half_or_pgm_stop, oc_ri_storage, oc_ro_storage,
oc_storage_control;
wire oc_man_pgm_reset, oc_man_acc_reset, oc_set_8000, oc_reset_8000,
wire [0:6] oc_data_out, oc_addr_out, oc_console_out;
wire oc_console_to_addr;
wire [0:14] oc_gs_ram_addr;
wire oc_read_gs, oc_write_gs;
wire oc_pgm_start, oc_pgm_stop, oc_err_reset, oc_err_sense_reset;
wire oc_run_control, oc_half_or_pgm_stop, oc_ri_storage, oc_ro_storage,
oc_storage_control;
wire oc_man_pgm_reset, oc_man_acc_reset, oc_set_8000, oc_reset_8000,
oc_hard_reset;
//-----------------------------------------------------------------------------
// Translators
//-----------------------------------------------------------------------------
wire tr_gs_write;
wire [0:4] tr_gs_in;
wire [0:6] tr_select_out;
wire tr_gs_write;
wire [0:4] tr_gs_in;
wire [0:6] tr_select_out;
 
gen_store gs (
gen_store gs (
.rst(oc_hard_reset),
.ap(ap),
.dp(dp),
149,13 → 149,13
.gs_in(tr_gs_in),
.console_ram_addr(oc_gs_ram_addr),
.console_read_gs(oc_read_gs),
.console_write_gs(oc_write_gs),
.console_write_gs(oc_write_gs),
.gs_out(gs_out),
.double_write(gs_double_write),
.no_write(gs_no_write)
);
 
operator_ctl oc (
operator_ctl oc (
.rst(rst),
.clk(clk),
.ap(ap),
182,8 → 182,8
.console_out(oc_console_out),
.console_to_addr(oc_console_to_addr),
.gs_ram_addr(oc_gs_ram_addr),
.read_gs(oc_read_gs),
.write_gs(oc_write_gs),
.read_gs(oc_read_gs),
.write_gs(oc_write_gs),
.pgm_start(oc_pgm_start),
.pgm_stop(oc_pgm_stop),
.err_reset(oc_err_reset),
206,7 → 206,7
.card_digit_ready(card_digit_ready)
);
 
translators tr (
translators tr (
.dist_early_out(`biq_blank),
.bs_out(`biq_blank),
.console_out(oc_console_out),

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