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    /i650/trunk
    from Rev 15 to Rev 16
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Rev 15 → Rev 16

/rtl/operator_ctl.v
33,8 → 33,8
module operator_ctl (
input rst, clk,
input ap, dp,
input dx, d0, d1, d2, d3, d4, d5, d6, d10,
input wu, hp,
input dx, d0, d1, d2, d3, d4, d5, d6, d9, d10,
input wu, wl, hp,
input [0:3] early_idx, ontime_idx,
input [0:6] cmd_digit_in, io_buffer_in, gs_in, acc_ontime, dist_ontime,
49,8 → 49,8
output reg pgm_start, pgm_stop, err_reset, err_sense_reset,
output run_control, half_or_pgm_stop, ri_storage, ro_storage,
storage_control,
output reg man_pgm_reset, man_acc_reset, set_8000, reset_8000,
hard_reset,
output reg man_pgm_reset, man_acc_reset, hard_reset,
output set_8000, reset_8000,
output reg[0:6] cmd_digit_out,
output reg busy, digit_ready,
77,6 → 77,8
: (disp_sw_dist | disp_sw_ri | disp_sw_ro)? dist_ontime
: disp_sw_pgm? prog_ontime
: `biq_blank;
assign set_8000 = man_pgm_reset & (ctl_sw_addr_stop | ctl_sw_run);
assign reset_8000 = man_pgm_reset & ctl_sw_manual;
//-----------------------------------------------------------------------------
// Calculate the RAM address of the general storage word at address gs_addr_.
129,18 → 131,28
`define state_read_gs_6 6'd35
`define state_write_gs_1 6'd36
`define state_write_gs_2 6'd37
`define state_write_gs_2a 6'd63
`define state_write_gs_3 6'd38
`define state_write_gs_4 6'd39
`define state_write_gs_5 6'd40
`define state_clear_drum_1 6'd41
`define state_clear_drum_2 6'd42
`define state_clear_drum_3 6'd43
`define state_load_gs_1 6'd44
`define state_load_gs_2 6'd45
`define state_dump_gs_1 6'd46
`define state_dump_gs_2 6'd47
`define state_dump_gs_3 6'd48
`define state_dump_gs_4 6'd49
`define state_read_acc_1 6'd41
`define state_read_acc_2 6'd42
`define state_read_acc_3 6'd43
`define state_read_dist_1 6'd44
`define state_read_dist_2 6'd45
`define state_read_dist_3 6'd46
`define state_read_prog_1 6'd47
`define state_read_prog_2 6'd48
`define state_read_prog_3 6'd49
`define state_clear_drum_1 6'd50
`define state_clear_drum_2 6'd51
`define state_clear_drum_3 6'd52
`define state_load_gs_1 6'd53
`define state_load_gs_2 6'd54
`define state_dump_gs_1 6'd55
`define state_dump_gs_2 6'd56
`define state_dump_gs_3 6'd57
`define state_dump_gs_4 6'd58
always @(posedge clk) begin
if (rst) begin
151,8 → 163,6
err_sense_reset <= 0;
man_pgm_reset <= 0;
man_acc_reset <= 0;
set_8000 <= 0;
reset_8000 <= 0;
hard_reset <= 0;
// reset console switches
464,13 → 474,18
end
`cmd_read_acc: begin
busy <= 1;
state <= `state_read_acc_1;
end
`cmd_read_dist: begin
busy <= 1;
state <= `state_read_dist_1;
end
`cmd_read_prog: begin
busy <= 1;
state <= `state_read_prog_1;
end
// 0 : Ignore if not in manual
765,6 → 780,13
end
end
`state_write_gs_2a: begin
if (d9) begin
digit_ready <= 1;
state <= `state_write_gs_3;
end
end
`state_write_gs_3: begin
if (d10) begin
gs_ram_addr <= gs_word_addr;
776,7 → 798,8
`state_write_gs_4: begin
write_gs <= 1;
console_out <= cmd_digit_in;
gs_ram_addr <= (gs_ram_addr + 1) % 32768;
if (write_gs)
gs_ram_addr <= (gs_ram_addr + 1) % 32768;
if (d10) begin
digit_ready <= 0;
state <= `state_write_gs_5;
788,6 → 811,63
state <= `state_idle;
end
`state_read_acc_1: begin
if (wl & d10) begin
state <= `state_read_acc_2;
end
end
`state_read_acc_2: begin
digit_ready <= 1;
cmd_digit_out <= acc_ontime;
if (wu & d10) begin
state <= `state_read_acc_3;
end
end
`state_read_acc_3: begin
digit_ready <= 0;
state <= `state_idle;
end
`state_read_dist_1: begin
if (d10) begin
state <= `state_read_dist_2;
end
end
`state_read_dist_2: begin
digit_ready <= 1;
cmd_digit_out <= dist_ontime;
if (d10) begin
state <= `state_read_dist_3;
end
end
`state_read_dist_3: begin
digit_ready <= 0;
state <= `state_idle;
end
`state_read_prog_1: begin
if (d10) begin
state <= `state_read_prog_2;
end
end
`state_read_prog_2: begin
digit_ready <= 1;
cmd_digit_out <= prog_ontime;
if (d10) begin
state <= `state_read_prog_3;
end
end
`state_read_prog_3: begin
digit_ready <= 0;
state <= `state_idle;
end
// 0 : Ignore if not in manual
// 1 : Synchronize with dx
// Put first dx digit
/rtl/biq_9s_comp.v
0,0 → 1,45
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// IBM 650 Reconstruction in Verilog (i650)
//
// This file is part of the IBM 650 Reconstruction in Verilog (i650) project
// http:////www.opencores.org/project,i650
//
// Description: 9's complement of a bi-quinary number.
//
// Additional Comments:
//
// Copyright (c) 2015 Robert Abeles
//
// This source file is free software; you can redistribute it
// and/or modify it under the terms of the GNU Lesser General
// Public License as published by the Free Software Foundation;
// either version 2.1 of the License, or (at your option) any
// later version.
//
// This source is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
// PURPOSE. See the GNU Lesser General Public License for more
// details.
//
// You should have received a copy of the GNU Lesser General
// Public License along with this source; if not, download it
// from http://www.opencores.org/lgpl.shtml
//////////////////////////////////////////////////////////////////////////////////
`include "defines.v"
 
module biq_9s_comp (
input [0:6] biq_in,
output [0:6] biq_out
);
 
//-----------------------------------------------------------------------------
// 9's complement swaps binary bits and reverses order of quinary bits.
//-----------------------------------------------------------------------------
assign biq_out = {biq_in[`biq_b0], biq_in[`biq_b5],
biq_in[`biq_q0], biq_in[`biq_q1],
biq_in[`biq_q2], biq_in[`biq_q3],
biq_in[`biq_q4]};
 
endmodule
rtl/biq_9s_comp.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rtl/digit_pulse.v =================================================================== --- rtl/digit_pulse.v (nonexistent) +++ rtl/digit_pulse.v (revision 16) @@ -0,0 +1,57 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// IBM 650 Reconstruction in Verilog (i650) +// +// This file is part of the IBM 650 Reconstruction in Verilog (i650) project +// http:////www.opencores.org/project,i650 +// +// Description: Digit time pulse generator. Emits a pulse lasting 1 digit time +// beginning at the first rising clk edge at/after in_pulse becomes true, +// approximating rising-edge triggering by in_pulse. +// +// Additional Comments: Input init_history is a 0 for rising egde tiggering. +// For falling edge triggering, set in_pulse to the complement of the signal +// and set init_history to 1. +// +// Copyright (c) 2015 Robert Abeles +// +// This source file is free software; you can redistribute it +// and/or modify it under the terms of the GNU Lesser General +// Public License as published by the Free Software Foundation; +// either version 2.1 of the License, or (at your option) any +// later version. +// +// This source is distributed in the hope that it will be +// useful, but WITHOUT ANY WARRANTY; without even the implied +// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +// PURPOSE. See the GNU Lesser General Public License for more +// details. +// +// You should have received a copy of the GNU Lesser General +// Public License along with this source; if not, download it +// from http://www.opencores.org/lgpl.shtml +////////////////////////////////////////////////////////////////////////////////// + +module digit_pulse ( + input rst, clk, + input in_pulse, + input init_history, + output reg out_pulse + ); + + reg history; + + always @(posedge clk) begin + if (rst) begin + out_pulse <= 0; + history <= init_history; + end else if (out_pulse) begin + out_pulse <= 0; + end else if (in_pulse) begin + out_pulse <= ~history; + history <= 1; + end else begin + history <= 0; + end + end; +endmodule
rtl/digit_pulse.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rtl/toplev.v =================================================================== --- rtl/toplev.v (revision 15) +++ rtl/toplev.v (revision 16) @@ -202,9 +202,11 @@ .d3(d3), .d4(d4), .d5(d5), - .d6(d6), + .d6(d6), + .d9(d9), .d10(d10), - .wu(wu), + .wu(wu), + .wl(wl), .hp(hp), .early_idx(early_idx), .ontime_idx(ontime_idx),

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