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    /i650/trunk
    from Rev 16 to Rev 17
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Rev 16 → Rev 17

/rtl/biq_9s_comp.v
34,12 → 34,12
output [0:6] biq_out
);
 
//-----------------------------------------------------------------------------
// 9's complement swaps binary bits and reverses order of quinary bits.
//-----------------------------------------------------------------------------
assign biq_out = {biq_in[`biq_b0], biq_in[`biq_b5],
biq_in[`biq_q0], biq_in[`biq_q1],
biq_in[`biq_q2], biq_in[`biq_q3],
biq_in[`biq_q4]};
//-----------------------------------------------------------------------------
// 9's complement swaps binary bits and reverses order of quinary bits.
//-----------------------------------------------------------------------------
assign biq_out = {biq_in[`biq_b0], biq_in[`biq_b5],
biq_in[`biq_q0], biq_in[`biq_q1],
biq_in[`biq_q2], biq_in[`biq_q3],
biq_in[`biq_q4]};
 
endmodule
/rtl/digit_pulse.v
39,19 → 39,19
output reg out_pulse
);
 
reg history;
always @(posedge clk) begin
if (rst) begin
out_pulse <= 0;
history <= init_history;
end else if (out_pulse) begin
out_pulse <= 0;
end else if (in_pulse) begin
out_pulse <= ~history;
history <= 1;
end else begin
history <= 0;
end
end;
reg history;
always @(posedge clk) begin
if (rst) begin
out_pulse <= 0;
history <= init_history;
end else if (out_pulse) begin
out_pulse <= 0;
end else if (in_pulse) begin
out_pulse <= ~history;
history <= 1;
end else begin
history <= 0;
end
end;
endmodule

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