Subversion Repositories i650

/rtl/op_reg.v

rtl/op_reg.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rtl/translators.v =================================================================== --- rtl/translators.v (revision 20) +++ rtl/translators.v (revision 21) @@ -7,7 +7,7 @@ // // Description: Drum code translators. // -// Additional Comments: +// Additional Comments: See US 2959351, Fig. 72. // // Copyright (c) 2015 Robert Abeles // @@ -32,11 +32,11 @@ module translators ( input [0:6] dist_early_out, bs_out, console_out, input ri_gs, ri_bs, ri_console, - input n800x, + input n800x, console_read_gs, input [0:4] gs_out, output gs_write, output [0:4] gs_in, - output reg[0:6] select_out + output reg[0:6] gs_biq_out ); reg [0:6] sel_in7; @@ -51,7 +51,7 @@ : ri_gs? dist_early_out : ri_bs? bs_out : `biq_blank; - select_out = (n800x)? sel_out7 : `biq_blank; + gs_biq_out = (n800x | console_read_gs)? sel_out7 : `biq_blank; end; endmodule

/rtl/defines.v

/rtl/add_in_a.v

rtl/add_in_a.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rtl/adder.v =================================================================== --- rtl/adder.v (nonexistent) +++ rtl/adder.v (revision 21) @@ -0,0 +1,193 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// IBM 650 Reconstruction in Verilog (i650) +// +// This file is part of the IBM 650 Reconstruction in Verilog (i650) project +// http:////www.opencores.org/project,i650 +// +// Description: Bi-quinary adder. +// +// Additional Comments: +// +// Copyright (c) 2015 Robert Abeles +// +// This source file is free software; you can redistribute it +// and/or modify it under the terms of the GNU Lesser General +// Public License as published by the Free Software Foundation; +// either version 2.1 of the License, or (at your option) any +// later version. +// +// This source is distributed in the hope that it will be +// useful, but WITHOUT ANY WARRANTY; without even the implied +// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +// PURPOSE. See the GNU Lesser General Public License for more +// details. +// +// You should have received a copy of the GNU Lesser General +// Public License along with this source; if not, download it +// from http://www.opencores.org/lgpl.shtml +////////////////////////////////////////////////////////////////////////////////// +`include "defines.v" + +module adder ( + input rst, + input bp, dp, c_a, edxu, dx, ed0u, d1, ed1l, d10, d10u, wl, + input [0:6] entry_a, entry_b, + input tlu_on, left_shift_off, left_shift_on, + input no_carry_insert, no_carry_blank, carry_insert, carry_blank, + input zero_insert, + + input error_reset, + input quotient_digit_on, overflow_stop_sw, overflow_sense_sw, + input mult_div_off, dist_true_add_gate, acc_true_add_latch, + input shift_overflow, + + output reg[0:6] adder_out, + output reg carry_test, no_carry_test, + output d0l_carry_sig, + + output overflow_stop, overflow_light, overflow_sense_sig + ); + + //----------------------------------------------------------------------------- + // The 650 adder operates like this: + // The adder output latches are normally reset by AP except when + // suppressed by reset_cntrl. reset_cntrl is turned + // off by (plate pullover): + // tlu_on | (cp & d1 & lt_sh_on) | (cp & ed0u & lt_sh_off) + // and on by: + // (bp & wl & d10 & lt_sh_off) | (bp & edxu & lt_sh_on) + // The carry and no_carry signals are gated by DP, which + // in turn gates the adder output. The falling edge of DP triggers + // the output latches, the pulse lasting past the reset action of + // AP. + // + // Schedule for this implementation: + // A : -- + // B : Combinational logic begins forming new sum and carry + // Previous sum and carry brought to adder output + // Setup reset_cntrl + // Setup overflow_stop_latch + // C : -- + // D : Save combinational logic new sum and carry + //----------------------------------------------------------------------------- + + reg [0:6] sum_hold; + reg carry_hold, no_carry_hold, carry_test_hold, no_carry_test_hold; + reg reset_cntrl; + reg carry, no_carry; + reg overflow_stop_latch; + assign d0l_carry_sig = c_a & wl & dx & carry; + assign overflow_stop = overflow_stop_latch; + assign overflow_light = overflow_stop_latch; + + //----------------------------------------------------------------------------- + // Bi-quinary adder, forms biq sum of two biq digits with carry in and out. + // Hand captured from 650 patent fig. 68. + //----------------------------------------------------------------------------- + wire b0_and_b5 = (entry_a[`biq_b0] & entry_b[`biq_b5]) + | (entry_a[`biq_b5] & entry_b[`biq_b0]); + wire q4_a_or_b = entry_a[`biq_q4] | entry_b[`biq_q4]; + wire q3_a_or_b = entry_a[`biq_q3] | entry_b[`biq_q3]; + wire q2_a_or_b = entry_a[`biq_q2] | entry_b[`biq_q2]; + wire q1_a_or_b = entry_a[`biq_q1] | entry_b[`biq_q1]; + wire q0_a_or_b = entry_a[`biq_q0] | entry_b[`biq_q0]; + wire qsum_8 = entry_a[`biq_q4] & entry_b[`biq_q4]; + wire qsum_7 = q4_a_or_b & q3_a_or_b; + wire qsum_6 = (entry_a[`biq_q3] & entry_b[`biq_q3]) + | (q4_a_or_b & q2_a_or_b); + wire qsum_5 = (q4_a_or_b & q3_a_or_b) + | (q3_a_or_b & q2_a_or_b); + wire qsum_4 = (entry_a[`biq_q2] & entry_b[`biq_q2]) + | (q3_a_or_b & q1_a_or_b) + | (q4_a_or_b & q0_a_or_b); + wire qsum_3 = (q3_a_or_b & q0_a_or_b) + | (q2_a_or_b & q1_a_or_b); + wire qsum_2 = (entry_a[`biq_q1] & entry_b[`biq_q1]) + | (q2_a_or_b & q0_a_or_b); + wire qsum_1 = q1_a_or_b & q0_a_or_b; + wire qsum_0 = (entry_a[`biq_q0] & entry_b[`biq_q0]); + wire three_or_eight = qsum_3 | qsum_8; + wire two_or_seven = qsum_2 | qsum_7; + wire six_or_one = qsum_6 | qsum_1; + wire zero_or_five = qsum_0 | qsum_5; + wire five_and_up = qsum_8 | qsum_7 | qsum_6 | qsum_5 | (qsum_4 & carry); + wire below_five = (qsum_4 & no_carry) | qsum_3 | qsum_2 | qsum_1 | qsum_0; + wire b5_carry = five_and_up & entry_a[`biq_b5] & entry_b[`biq_b5]; + wire b5_no_carry = (five_and_up & entry_a[`biq_b0] & entry_b[`biq_b0]) + | (below_five & b0_and_b5); + wire b0_carry = (five_and_up & b0_and_b5) + | (below_five & entry_a[`biq_b5] & entry_b[`biq_b5]); + wire b0_no_carry = below_five & entry_a[`biq_b0] & entry_b[`biq_b0]; + wire sum_q0 = (carry & qsum_4) | (no_carry & zero_or_five); + wire sum_q1 = (carry & zero_or_five) | (no_carry & six_or_one); + wire sum_q2 = (carry & six_or_one) | (no_carry & two_or_seven); + wire sum_q3 = (carry & two_or_seven) | (no_carry & three_or_eight); + wire sum_q4 = (carry & three_or_eight) | (no_carry & qsum_4); + wire sum_b0 = b0_no_carry | b0_carry; + wire sum_b5 = b5_no_carry | b5_carry; + wire [0:6] sum_out = {sum_b5, sum_b0, sum_q4, sum_q3, sum_q2, sum_q1, sum_q0}; + wire carry_out = b0_carry | b5_carry; + wire no_carry_out = b0_no_carry | b5_no_carry; + + wire overflow = shift_overflow + | (carry_test & d10u & dist_true_add_gate + & acc_true_add_latch & mult_div_off); + assign overflow_sense_sig = overflow & overflow_sense_sw; + + //----------------------------------------------------------------------------- + // B -- + //----------------------------------------------------------------------------- + always @(posedge rst, posedge bp) begin + if (rst) begin + adder_out <= `biq_blank; + reset_cntrl <= 0; + carry_test <= 0; + no_carry_test <= 0; + carry <= 0; + no_carry <= 0; + overflow_stop_latch <= 0; + end else begin + adder_out <= sum_hold; + carry_test <= carry_test_hold; + no_carry_test <= no_carry_test_hold; + carry <= carry_hold; + no_carry <= no_carry_hold; + if (tlu_on | (d1 & left_shift_on) | (ed0u & left_shift_off)) begin + reset_cntrl <= 0; + end else if ((wl & d10 & left_shift_off) | (edxu & left_shift_on)) begin + reset_cntrl <= 1; + end + if (error_reset) begin + overflow_stop_latch <= 0; + end else if ((ed1l & carry_test & quotient_digit_on) + | (overflow & overflow_stop_sw)) begin + overflow_stop_latch <= 1; + end + end + end; + + always @(posedge rst, posedge dp) begin + if (rst) begin + sum_hold <= `biq_blank; + carry_hold <= 0; + no_carry_hold <= 0; + carry_test_hold <= 0; + no_carry_test_hold <= 0; + end else begin + sum_hold <= zero_insert? `biq_0 + : reset_cntrl? sum_hold + : sum_out; + carry_hold <= (reset_cntrl | carry_blank)? 1'b0 + : carry_insert? 1'b1 + : carry_out; + no_carry_hold <= (reset_cntrl | no_carry_blank)? 1'b0 + : no_carry_insert? 1'b1 + : no_carry_out; + carry_test_hold <= reset_cntrl? 1'b0 : carry_out; + no_carry_test_hold <= reset_cntrl? 1'b0 : no_carry_out; + end + end; + + +endmodule

rtl/adder.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rtl/add_in_b.v =================================================================== --- rtl/add_in_b.v (nonexistent) +++ rtl/add_in_b.v (revision 21) @@ -0,0 +1,64 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// IBM 650 Reconstruction in Verilog (i650) +// +// This file is part of the IBM 650 Reconstruction in Verilog (i650) project +// http:////www.opencores.org/project,i650 +// +// Description: Adder input B. +// +// Additional Comments: See US 2959351, Fig. 67. +// +// Copyright (c) 2015 Robert Abeles +// +// This source file is free software; you can redistribute it +// and/or modify it under the terms of the GNU Lesser General +// Public License as published by the Free Software Foundation; +// either version 2.1 of the License, or (at your option) any +// later version. +// +// This source is distributed in the hope that it will be +// useful, but WITHOUT ANY WARRANTY; without even the implied +// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR +// PURPOSE. See the GNU Lesser General Public License for more +// details. +// +// You should have received a copy of the GNU Lesser General +// Public License along with this source; if not, download it +// from http://www.opencores.org/lgpl.shtml +////////////////////////////////////////////////////////////////////////////////// +`include "defines.v" + +module add_in_b ( + input [0:6] dist_early_out, dist_ontime_out, + input [0:9] special_int_entry, + input ontime_dist_add_gate_tlu, dist_compl_add_gate, upper_lower_check, + dist_blank_gate, early_dist_zero_entry, //early_dist_zero_ctrl, + dist_true_add_gate, + + output [0:6] adder_entry_b + ); + + wire [0:6] special_int_biq = special_int_entry[0]? `biq_0 + : special_int_entry[1]? `biq_1 + : special_int_entry[2]? `biq_2 + : special_int_entry[3]? `biq_3 + : special_int_entry[4]? `biq_4 + : special_int_entry[5]? `biq_5 + : special_int_entry[6]? `biq_6 + : special_int_entry[7]? `biq_7 + : special_int_entry[8]? `biq_8 + : special_int_entry[9]? `biq_9 + : `biq_blank; + wire [0:6] dist_early_compl; + biq_9s_comp bc1 (dist_early_out, dist_early_compl); + wire dist_true_add = dist_true_add_gate & upper_lower_check & dist_blank_gate; + wire dist_compl_add = dist_compl_add_gate & upper_lower_check & dist_blank_gate; + + assign adder_entry_b = early_dist_zero_entry? `biq_0 + : dist_true_add? dist_early_out + : dist_compl_add? dist_early_compl + : ontime_dist_add_gate_tlu? dist_ontime_out + : special_int_biq; + +endmodule

rtl/add_in_b.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rtl/accumulator.v =================================================================== --- rtl/accumulator.v (revision 20) +++ rtl/accumulator.v (revision 21) @@ -32,12 +32,12 @@ module accumulator ( input rst, input ap, bp, dp, - input dx, d1, d2, + input dx, d1, d2, d10, input dxu, d0u, input wu, wl, - input [0:6] adder_out, - input acc_regen_gate, right_shift_gate, acc_ri_gate, - zero_shift_count, man_acc_reset, reset_op_latch, + input [0:6] adder_out, console_out, + input acc_regen_gate, right_shift_gate, acc_ri_gate, acc_ri_console, + zero_shift_count, man_acc_reset, reset_op, input [0:3] early_idx, ontime_idx, output reg [0:6] early_out, ontime_out, ped_out ); @@ -47,7 +47,7 @@ //----------------------------------------------------------------------------- reg [0:6] digits [0:31]; - wire [0:4] acc_early_idx = {(dx? ~wu : wu), early_idx}; + wire [0:4] acc_early_idx = {(d10? ~wu : wu), early_idx}; wire [0:4] acc_ontime_idx = {wu, ontime_idx}; //----------------------------------------------------------------------------- @@ -54,7 +54,7 @@ // A -- Read into early_out from RAM // Read into ontime_out //----------------------------------------------------------------------------- - wire acc_reset = reset_op_latch | man_acc_reset + wire acc_reset = reset_op | man_acc_reset | (zero_shift_count & wl & (d1 | d2)); always @(posedge ap) if (rst) begin @@ -61,8 +61,9 @@ early_out <= `biq_blank; ontime_out <= `biq_blank; end else begin - early_out <= reset_op_latch? `biq_0 - : digits[acc_early_idx]; + early_out <= reset_op? `biq_0 + : ((wl & d10) | dxu)? early_out + : digits[acc_early_idx]; ontime_out <= (acc_reset | d0u | dxu)? `biq_0 : early_out; end; @@ -73,7 +74,8 @@ if (rst) begin ped_out <= `biq_blank; end else begin - ped_out <= right_shift_gate? early_out + ped_out <= acc_ri_console? console_out + : right_shift_gate? early_out : acc_ri_gate? adder_out : acc_regen_gate? ontime_out : `biq_blank;

/rtl/store_select.v

rtl/store_select.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rtl/operator_ctl.v =================================================================== --- rtl/operator_ctl.v (revision 20) +++ rtl/operator_ctl.v (revision 21) @@ -43,7 +43,7 @@ output reg[0:6] data_out, addr_out, console_out, output [0:6] display_digit, - output reg console_to_addr, + output reg console_to_addr, acc_ri_console, output reg[0:14] gs_ram_addr, output reg read_gs, write_gs, output reg pgm_start, pgm_stop, err_reset, err_sense_reset, @@ -143,15 +143,18 @@ `define state_read_prog_1 6'd47 `define state_read_prog_2 6'd48 `define state_read_prog_3 6'd49 - `define state_clear_drum_1 6'd50 - `define state_clear_drum_2 6'd51 - `define state_clear_drum_3 6'd52 - `define state_load_gs_1 6'd53 - `define state_load_gs_2 6'd54 - `define state_dump_gs_1 6'd55 - `define state_dump_gs_2 6'd56 - `define state_dump_gs_3 6'd57 - `define state_dump_gs_4 6'd58 + `define state_write_acc_1 6'd50 + `define state_write_acc_2 6'd51 + `define state_write_acc_3 6'd52 + `define state_clear_drum_1 6'd53 + `define state_clear_drum_2 6'd54 + `define state_clear_drum_3 6'd55 + `define state_load_gs_1 6'd56 + `define state_load_gs_2 6'd57 + `define state_dump_gs_1 6'd58 + `define state_dump_gs_2 6'd59 + `define state_dump_gs_3 6'd60 + `define state_dump_gs_4 6'd61 always @(posedge clk) if (rst) begin @@ -200,6 +203,7 @@ gs_ram_addr <= 15'd0; read_gs <= 0; write_gs <= 0; + acc_ri_console <= 0; console_out <= `biq_blank; end else if (dp) begin case (state) @@ -222,9 +226,6 @@ end else if (do_reset_console) begin do_reset_console <= 0; state <= `state_reset_console_1; - end else if (do_clear_drum) begin - do_clear_drum <= 0; - state <= `state_clear_drum_1; end else if (do_pgm_reset) begin do_pgm_reset <= 0; state <= `state_pgm_reset_1; @@ -240,6 +241,9 @@ do_err_sense_reset <= 0; err_sense_reset <= 1; state <= `state_err_sense_reset_1; + end else if (do_clear_drum) begin + do_clear_drum <= 0; + state <= `state_clear_drum_1; end else begin busy <= 0; digit_ready <= 0; @@ -487,6 +491,11 @@ state <= `state_read_prog_1; end + `cmd_write_acc: begin + busy <= 1; + state <= `state_write_acc_1; + end + // 0 : Ignore if not in manual // Clear gs_ram_addr // 1 : Synchronize with d10 @@ -860,6 +869,28 @@ state <= `state_idle; end + `state_write_acc_1: begin + if (wu & d10) begin + console_out <= cmd_digit_in; + acc_ri_console <= 1; + digit_ready <= 1; + state <= `state_write_acc_2; + end + end + + `state_write_acc_2: begin + console_out <= cmd_digit_in; + if (wu & d10) begin + digit_ready <= 0; + state <= `state_write_acc_3; + end + end + + `state_write_acc_3: begin + acc_ri_console <= 0; + state <= `state_idle; + end + // 0 : Ignore if not in manual // 1 : Synchronize with dx // Put first dx digit

/rtl/addr_reg.v

rtl/addr_reg.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: rtl/toplev.v =================================================================== --- rtl/toplev.v (revision 20) +++ rtl/toplev.v (revision 21) @@ -115,11 +115,23 @@ ); //----------------------------------------------------------------------------- + // Adder input muxes + //----------------------------------------------------------------------------- + wire [0:6] aa_entry_a, ab_entry_b; + + //----------------------------------------------------------------------------- // Accumulator //----------------------------------------------------------------------------- wire [0:6] ac_early_out, ac_ontime_out, ac_ped_out; //----------------------------------------------------------------------------- + // Address register + //----------------------------------------------------------------------------- + wire [0:6] ar_addr_th, ar_addr_h, ar_addr_t, ar_addr_u; + wire ar_dynamic_addr_hit, ar_addr_no_800x, ar_addr_8000, ar_addr_8001, + ar_addr_8002, ar_addr_8003, ar_addr_8002_8003, ar_invalid_addr; + + //----------------------------------------------------------------------------- // Distributor //----------------------------------------------------------------------------- wire [0:6] ds_early_out, ds_ontime_out; @@ -138,10 +150,16 @@ wire gs_double_write, gs_no_write; //----------------------------------------------------------------------------- + // Opcode register + //----------------------------------------------------------------------------- + wire [0:6] op_opreg_t, op_opreg_u; + wire op_ri_addr_reg; + + //----------------------------------------------------------------------------- // Operator controls //----------------------------------------------------------------------------- wire [0:6] oc_data_out, oc_addr_out, oc_console_out, oc_display_digit; - wire oc_console_to_addr; + wire oc_console_to_addr, oc_acc_ri_console; wire [0:14] oc_gs_ram_addr; wire oc_read_gs, oc_write_gs; wire oc_pgm_start, oc_pgm_stop, oc_err_reset, oc_err_sense_reset; @@ -156,6 +174,11 @@ //----------------------------------------------------------------------------- wire [0:6] ps_early_out, ps_ontime_out, ps_ped_out; wire ps_restart_sig; + + //----------------------------------------------------------------------------- + // Storage select + //----------------------------------------------------------------------------- + wire [0:6] ss_selected_out; //----------------------------------------------------------------------------- // Translators @@ -162,10 +185,38 @@ //----------------------------------------------------------------------------- wire tr_gs_write; wire [0:4] tr_gs_in; - wire [0:6] tr_select_out; + wire [0:6] tr_gs_out; + add_in_a aa ( + .acc_early_out(ac_early_out), + .acc_ontime_out(ac_ontime_out), + .prog_step_early_out(ps_early_out), + .select_storage_out(ss_selected_out), + .addr_u(ar_addr_u), + .acc_true_add_gate(1'b0), + .acc_compl_add_gate(1'b0), + .left_shift_gate(1'b0), + .prog_step_add_gate(1'b0), + .shift_num_gate(1'b0), + .select_stor_add_gate(1'b0), + .adder_entry_a(aa_entry_a) + ); + + add_in_b ab ( + .dist_early_out(ds_early_out), + .dist_ontime_out(ds_ontime_out), + .special_int_entry(10'd0), + .ontime_dist_add_gate_tlu(1'b0), + .dist_compl_add_gate(1'b0), + .upper_lower_check(1'b0), + .dist_blank_gate(1'b0), + .early_dist_zero_entry(1'b0), + .dist_true_add_gate(1'b0), + .adder_entry_b(ab_entry_b) + ); + accumulator ac ( - .rst(rst), + .rst(oc_hard_reset), .ap(ap), .bp(bp), .dp(dp), @@ -172,17 +223,20 @@ .dx(dx), .d1(d1), .d2(d2), + .d10(d10), .dxu(dxu), .d0u(d0u), .wu(wu), .wl(wl), .adder_out(`biq_0), + .console_out(oc_console_out), .acc_regen_gate(1'b1), .right_shift_gate(1'b0), - .acc_ri_gate(1'b0), + .acc_ri_gate(1'b0), + .acc_ri_console(oc_acc_ri_console), .zero_shift_count(1'b0), .man_acc_reset(oc_man_acc_reset), - .reset_op_latch(1'b0), + .reset_op(1'b0), .early_idx(early_idx), .ontime_idx(ontime_idx), .early_out(ac_early_out), @@ -190,9 +244,65 @@ .ped_out(ac_ped_out) ); - checking ck ( + addr_reg ar ( .rst(rst), + .ap(ap), .bp(bp), + .dx(dx), + .d1(d1), + .d2(d2), + .d3(d3), + .d4(d4), + .d5(d5), + .d6(d6), + .d7(d7), + .d8(d8), + .d9(d9), + .w0(w0), + .w1(w1), + .w2(w2), + .w3(w3), + .w4(w4), + .w5(w5), + .w6(w6), + .w7(w7), + .w8(w8), + .w9(w9), + .s0(s0), + .s1(s1), + .s2(s2), + .s3(s3), + .s4(s4), + .error_reset(oc_err_reset), + .restart_a(1'b0), + .set_8000(oc_set_8000), + .reset_8000(oc_reset_8000), + .tlu_band_change(1'b0), + .double_write(gs_double_write), + .no_write(gs_no_write), + .bs_to_gs(1'b0), + .ri_gs(1'b0), + .ps_reg_in(ps_ontime_out), + .console_in(oc_addr_out), + .ri_addr_reg(op_ri_addr_reg), + .console_to_addr_reg(oc_console_to_addr), + .addr_th(ar_addr_th), + .addr_h(ar_addr_h), + .addr_t(ar_addr_t), + .addr_u(ar_addr_u), + .dynamic_addr_hit(ar_dynamic_addr_hit), + .addr_no_800x(ar_addr_no_800x), + .addr_8000(ar_addr_8000), + .addr_8001(ar_addr_8001), + .addr_8002(ar_addr_8002), + .addr_8003(ar_addr_8003), + .addr_8002_8003(ar_addr_8002_8003), + .invalid_addr(ar_invalid_addr) + ); + + checking ck ( + .rst(oc_hard_reset), + .bp(bp), .d1_dx(d1_dx), .acc_ontime(ac_ontime_out), .prog_ontime(ps_ontime_out), @@ -206,7 +316,7 @@ ); distributor ds ( - .rst(rst), + .rst(oc_hard_reset), .ap(ap), .cp(cp), .dp(dp), @@ -213,7 +323,7 @@ .dx(dx), .d0(d0), .d10(d10), - .selected_storage(7'd0), + .selected_storage(ss_selected_out), .ri_dist(1'd0), .acc_ontime(ac_ontime_out), .start_acc_dist_ri(1'd0), @@ -232,9 +342,9 @@ .ap(ap), .dp(dp), .write_gate(tr_gs_write), - .addr_th(`biq_blank), - .addr_h(`biq_blank), - .addr_t(`biq_blank), + .addr_th(ar_addr_th), + .addr_h(ar_addr_h), + .addr_t(ar_addr_t), .dynamic_addr(digit_idx), .gs_in(tr_gs_in), .console_ram_addr(oc_gs_ram_addr), @@ -267,7 +377,7 @@ .ontime_idx(ontime_idx), .cmd_digit_in(cmd_digit_in), .io_buffer_in(io_buffer_in), - .gs_in(tr_select_out), + .gs_in(tr_gs_out), .acc_ontime(ac_ontime_out), .dist_ontime(ds_ontime_out), .prog_ontime(ps_ontime_out), @@ -276,7 +386,8 @@ .addr_out(oc_addr_out), .console_out(oc_console_out), .display_digit(oc_display_digit), - .console_to_addr(oc_console_to_addr), + .console_to_addr(oc_console_to_addr), + .acc_ri_console(oc_acc_ri_console), .gs_ram_addr(oc_gs_ram_addr), .read_gs(oc_read_gs), .write_gs(oc_write_gs), @@ -302,8 +413,28 @@ .card_digit_ready(card_digit_ready) ); + op_reg op ( + .rst(oc_hard_reset), + .cp(cp), + .d0(d0), + .d9(d9), + .d10(d10), + .d1_d5(d1_d5), + .d5_dx(d5_dx), + .restart_a(1'b0), + .restart_b(1'b0), + .d_alt(1'b0), + .i_alt(1'b0), + .tlu_band_change(1'b0), + .man_prog_reset(oc_man_pgm_reset), + .prog_step_ped(ps_ped_out), + .opreg_t(op_opreg_t), + .opreg_u(op_opreg_u), + .ri_addr_reg(op_ri_addr_reg) + ); + prog_step ps ( - .rst(rst), + .rst(oc_hard_reset), .ap(ap), .dp(dp), .dx(dx), @@ -323,6 +454,23 @@ .prog_restart_sig(ps_restart_sig) ); + store_select ss ( + .d0(d0), + .d1_dx(d1_dx), + .addr_no_800x(ar_addr_no_800x), + .addr_8000(ar_addr_8000), + .addr_8001(ar_addr_8001), + .addr_8002_8003(ar_addr_8002_8003), + .addr_hot_8000(1'b0), + .acc_ontime(ac_ontime_out), + .dist_ontime(ds_ontime_out), + .gs_out(tr_gs_out), + .console_switches(oc_data_out), + .acc_plus(1'b0), + .acc_minus(1'b0), + .selected_out(ss_selected_out) + ); + translators tr ( .dist_early_out(`biq_blank), .bs_out(`biq_blank), @@ -330,11 +478,12 @@ .ri_gs(1'b0), .ri_bs(1'b0), .ri_console(oc_write_gs), - .n800x(1'b1), + .n800x(ar_addr_no_800x), + .console_read_gs(oc_read_gs), .gs_out(gs_out), .gs_write(tr_gs_write), .gs_in(tr_gs_in), - .select_out(tr_select_out) + .gs_biq_out(tr_gs_out) ); endmodule \ No newline at end of file