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  • This comparison shows the changes necessary to convert path 
    /i650/trunk
    from Rev 21 to Rev 22
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Rev 21 → Rev 22

/rtl/translators.v
34,24 → 34,22
input ri_gs, ri_bs, ri_console,
input n800x, console_read_gs,
input [0:4] gs_out,
output gs_write,
output gs_write,
output [0:4] gs_in,
output reg[0:6] gs_biq_out
output [0:6] gs_biq_out
);
 
reg [0:6] sel_in7;
wire [0:6] sel_out7;
xlate7to5 x75 (sel_in7, gs_in);
xlate5to7 x57 (gs_out, sel_out7);
assign gs_write = ri_gs | ri_bs | ri_console;
always @(*) begin
sel_in7 = ri_console? console_out
: ri_gs? dist_early_out
: ri_bs? bs_out
: `biq_blank;
gs_biq_out = (n800x | console_read_gs)? sel_out7 : `biq_blank;
end;
wire [0:6] sel_in7;
wire [0:6] sel_out7;
xlate7to5 x75 (sel_in7, gs_in);
xlate5to7 x57 (gs_out, sel_out7);
assign gs_write = ri_gs | ri_bs | ri_console;
assign sel_in7 = ri_console? console_out
: ri_gs? dist_early_out
: ri_bs? bs_out
: `biq_blank;
assign gs_biq_out = (n800x | console_read_gs)? sel_out7 : `biq_blank;
 
endmodule
/rtl/adder.v
31,7 → 31,8
 
module adder (
input rst,
input bp, dp, c_a, edxu, dx, ed0u, d1, ed1l, d10, d10u, wl,
input ap, bp, dp,
dxu, dx, d0u, d1, d1l, d10, d10u, wl,
input [0:6] entry_a, entry_b,
input tlu_on, left_shift_off, left_shift_on,
input no_carry_insert, no_carry_blank, carry_insert, carry_blank,
43,47 → 44,28
input shift_overflow,
output reg[0:6] adder_out,
output reg carry_test, no_carry_test,
output d0l_carry_sig,
output reg carry_test, no_carry_test, d0l_carry_sig, overflow_stop,
output overflow_stop, overflow_light, overflow_sense_sig
output overflow_light, overflow_sense_sig
);
//-----------------------------------------------------------------------------
// The 650 adder operates like this:
// The adder output latches are normally reset by AP except when
// suppressed by reset_cntrl. reset_cntrl is turned
// off by (plate pullover):
// tlu_on | (cp & d1 & lt_sh_on) | (cp & ed0u & lt_sh_off)
// and on by:
// (bp & wl & d10 & lt_sh_off) | (bp & edxu & lt_sh_on)
// The carry and no_carry signals are gated by DP, which
// in turn gates the adder output. The falling edge of DP triggers
// the output latches, the pulse lasting past the reset action of
// AP.
//
// Schedule for this implementation:
// A : --
// B : Combinational logic begins forming new sum and carry
// Previous sum and carry brought to adder output
// Setup reset_cntrl
// Setup overflow_stop_latch
// C : --
// D : Save combinational logic new sum and carry
// The 650 bi-quinary adder accepts its inputs early (i.e., one clock ahead),
// producing a result during the next digit time. This implementation retains
// sum and carries in _hold flip-flops, the 650 used other tricky means.
//-----------------------------------------------------------------------------
 
reg [0:6] sum_hold;
reg carry_hold, no_carry_hold, carry_test_hold, no_carry_test_hold;
reg reset_cntrl;
reg carry, no_carry;
reg overflow_stop_latch;
assign d0l_carry_sig = c_a & wl & dx & carry;
assign overflow_stop = overflow_stop_latch;
assign overflow_light = overflow_stop_latch;
reg reset_ctl;
reg carry, no_carry;
//-----------------------------------------------------------------------------
// Bi-quinary adder, forms biq sum of two biq digits with carry in and out.
// Hand captured from 650 patent fig. 68.
// Hand captured from 650 patent fig. 68.
//
// By design, this logic produces a sum of all zeroes with zero carry_out and
// no_carry_out whenever entry_a or entry_b or both carry and no_carry are
// zero.
//-----------------------------------------------------------------------------
wire b0_and_b5 = (entry_a[`biq_b0] & entry_b[`biq_b5])
| (entry_a[`biq_b5] & entry_b[`biq_b0]);
129,46 → 111,59
wire [0:6] sum_out = {sum_b5, sum_b0, sum_q4, sum_q3, sum_q2, sum_q1, sum_q0};
wire carry_out = b0_carry | b5_carry;
wire no_carry_out = b0_no_carry | b5_no_carry;
wire overflow = shift_overflow
| (carry_test & d10u & dist_true_add_gate
& acc_true_add_latch & mult_div_off);
assign overflow_sense_sig = overflow & overflow_sense_sw;
//-----------------------------------------------------------------------------
// B --
// A : Supply sum and carries from previous digit time
//-----------------------------------------------------------------------------
always @(posedge rst, posedge bp) begin
always @(posedge ap)
if (rst) begin
adder_out <= `biq_blank;
reset_cntrl <= 0;
carry_test <= 0;
adder_out <= `biq_blank;
carry_test <= 0;
no_carry_test <= 0;
carry <= 0;
no_carry <= 0;
overflow_stop_latch <= 0;
carry <= 0;
no_carry <= 0;
end else begin
adder_out <= sum_hold;
carry_test <= carry_test_hold;
adder_out <= sum_hold;
carry_test <= carry_test_hold;
no_carry_test <= no_carry_test_hold;
carry <= carry_hold;
no_carry <= no_carry_hold;
if (tlu_on | (d1 & left_shift_on) | (ed0u & left_shift_off)) begin
reset_cntrl <= 0;
end else if ((wl & d10 & left_shift_off) | (edxu & left_shift_on)) begin
reset_cntrl <= 1;
end
if (error_reset) begin
overflow_stop_latch <= 0;
end else if ((ed1l & carry_test & quotient_digit_on)
| (overflow & overflow_stop_sw)) begin
overflow_stop_latch <= 1;
end
carry <= carry_hold;
no_carry <= no_carry_hold;
end
end;
always @(posedge rst, posedge dp) begin
wire reset_ctl_on_p = (wl & d10 & left_shift_off) | (dxu & left_shift_on);
wire reset_ctl_off_p = tlu_on | (d1 & left_shift_on) | (d0u & left_shift_off);
always @(posedge ap)
if (rst) begin
reset_ctl <= 0;
end else if (reset_ctl_on_p) begin
reset_ctl <= 1;
end else if (reset_ctl_off_p) begin
reset_ctl <= 0;
end;
wire overflow = shift_overflow
| (carry_test & d10u & dist_true_add_gate
& acc_true_add_latch & mult_div_off);
assign overflow_sense_sig = overflow & overflow_sense_sw;
wire overflow_stop_p = (d1l & carry_test & quotient_digit_on)
| (overflow & overflow_stop_sw);
assign overflow_light = overflow_stop;
always @(posedge bp)
if (rst) begin
overflow_stop <= 1;
end else if (error_reset) begin
overflow_stop <= 0;
end else if (overflow_stop_p) begin
overflow_stop <= 1;
end;
always @(posedge dp)
if (rst) d0l_carry_sig <= 0;
else if (wl & d1) d0l_carry_sig <= 0;
else if (wl & dx & carry_out) d0l_carry_sig <= 1;
always @(posedge dp)
if (rst) begin
sum_hold <= `biq_blank;
carry_hold <= 0;
no_carry_hold <= 0;
175,19 → 170,18
carry_test_hold <= 0;
no_carry_test_hold <= 0;
end else begin
sum_hold <= zero_insert? `biq_0
: reset_cntrl? sum_hold
sum_hold <= zero_insert? `biq_0
: reset_ctl? sum_hold
: sum_out;
carry_hold <= (reset_cntrl | carry_blank)? 1'b0
carry_hold <= (reset_ctl | carry_blank)? 1'b0
: carry_insert? 1'b1
: carry_out;
no_carry_hold <= (reset_cntrl | no_carry_blank)? 1'b0
no_carry_hold <= (reset_ctl | no_carry_blank)? 1'b0
: no_carry_insert? 1'b1
: no_carry_out;
carry_test_hold <= reset_cntrl? 1'b0 : carry_out;
no_carry_test_hold <= reset_cntrl? 1'b0 : no_carry_out;
end
end;
carry_test_hold <= reset_ctl? 1'b0 : carry_out;
no_carry_test_hold <= reset_ctl? 1'b0 : no_carry_out;
end;
 
endmodule
/rtl/operator_ctl.v
40,6 → 40,7
input [0:6] cmd_digit_in, io_buffer_in, gs_in, acc_ontime, dist_ontime,
prog_ontime,
input [0:5] command,
input restart_reset,
output reg[0:6] data_out, addr_out, console_out,
output [0:6] display_digit,
53,7 → 54,7
output set_8000, reset_8000,
output reg[0:6] cmd_digit_out,
output reg busy, digit_ready,
output reg busy, digit_ready, restart_reset_busy,
output reg punch_card, read_card, card_digit_ready
);
178,7 → 179,7
disp_sw_lacc <= 0;
disp_sw_uacc <= 0;
disp_sw_dist <= 1;
disp_sw_pgm <= 0;
disp_sw_pgm <= 0;
disp_sw_ri <= 0;
disp_sw_ro <= 0;
ovflw_sw_stop <= 1;
190,6 → 191,7
busy <= 1;
digit_ready <= 0;
cmd_digit_out <= `biq_blank;
restart_reset_busy <= 0;
do_power_on_reset <= 1;
do_reset_console <= 0;
210,7 → 212,12
`state_idle: begin
case (command)
`cmd_none: begin
if (do_power_on_reset) begin
if (restart_reset) begin
do_pgm_reset <= 1;
do_acc_reset <= 1;
do_err_reset <= 1;
restart_reset_busy <= 1;
end else if (do_power_on_reset) begin
do_power_on_reset <= 0;
do_reset_console <= 1;
do_pgm_reset <= 1;
220,8 → 227,8
do_hard_reset <= 1;
do_clear_drum <= 1;
end else if (do_hard_reset) begin
do_hard_reset <= 0;
hard_reset <= 1;
do_hard_reset <= 0;
hard_reset <= 1;
state <= `state_hard_reset_1;
end else if (do_reset_console) begin
do_reset_console <= 0;
239,14 → 246,15
state <= `state_err_reset_1;
end else if (do_err_sense_reset) begin
do_err_sense_reset <= 0;
err_sense_reset <= 1;
err_sense_reset <= 1;
state <= `state_err_sense_reset_1;
end else if (do_clear_drum) begin
do_clear_drum <= 0;
do_clear_drum <= 0;
state <= `state_clear_drum_1;
end else begin
busy <= 0;
digit_ready <= 0;
restart_reset_busy <= 0;
end
end
300,7 → 308,7
disp_sw_lacc <= 1;
disp_sw_uacc <= 0;
disp_sw_dist <= 0;
disp_sw_pgm <= 0;
disp_sw_pgm <= 0;
disp_sw_ri <= 0;
disp_sw_ro <= 0;
end
870,7 → 878,7
end
`state_write_acc_1: begin
if (wu & d10) begin
if (wl & dx) begin
console_out <= cmd_digit_in;
acc_ri_console <= 1;
digit_ready <= 1;
/rtl/addr_reg.v
106,7 → 106,6
// Test address register validity
// Test address == 0xxx or == 1xxx or == 800[0..3]
// Sample at d9:ap
assign inv1_p = (addr_th[2] | addr_th[4]) | (addr_th[3] & addr_th[1])
| (addr_th[6] & addr_th[0]) | (addr_th[5] & addr_th[0]); // 0xxx or 1xxx or 8xxx
assign inv2_p = (addr_th[3] & addr_th[0]) & ~(addr_h[1] & addr_h[6]); // 80xx
116,10 → 115,10
// Decode 8xxx addresses
assign addr_8xxx_p = (addr_th[`biq_b5] & addr_th[`biq_q3]);
assign addr_8xx0_p = addr_8xxx_p & addr_u[6];
assign addr_8xx1_p = addr_8xxx_p & addr_u[5];
assign addr_8xx2_p = addr_8xxx_p & addr_u[4];
assign addr_8xx3_p = addr_8xxx_p & addr_u[3];
assign addr_8xx0_p = addr_8xxx_p & addr_u[`biq_q0];
assign addr_8xx1_p = addr_8xxx_p & addr_u[`biq_q1];
assign addr_8xx2_p = addr_8xxx_p & addr_u[`biq_q2];
assign addr_8xx3_p = addr_8xxx_p & addr_u[`biq_q3];
// Memory access error
assign mem_error_p = double_write | ((bs_to_gs | ri_gs) & ~dx & no_write);
/rtl/toplev.v
123,6 → 123,13
// Accumulator
//-----------------------------------------------------------------------------
wire [0:6] ac_early_out, ac_ontime_out, ac_ped_out;
//-----------------------------------------------------------------------------
// Adder
//-----------------------------------------------------------------------------
wire [0:6] ad_adder_out;
wire ad_carry_test, ad_no_carry_test, ad_d0l_carry_sig, ad_overflow_stop,
ad_overflow_light, ad_overflow_sense_sig;
 
//-----------------------------------------------------------------------------
// Address register
167,6 → 174,7
oc_storage_control;
wire oc_man_pgm_reset, oc_man_acc_reset, oc_set_8000, oc_reset_8000,
oc_hard_reset;
wire oc_restart_reset_busy;
assign display_digit = oc_display_digit;
//-----------------------------------------------------------------------------
228,7 → 236,7
.d0u(d0u),
.wu(wu),
.wl(wl),
.adder_out(`biq_0),
.adder_out(ad_adder_out),
.console_out(oc_console_out),
.acc_regen_gate(1'b1),
.right_shift_gate(1'b0),
244,6 → 252,46
.ped_out(ac_ped_out)
);
 
adder ad (
.rst(rst),
.ap(ap),
.bp(bp),
.dp(dp),
.dxu(dxu),
.dx(dx),
.d0u(d0u),
.d1(d1),
.d1l(d1l),
.d10(d10),
.d10u(d10u),
.wl(wl),
.entry_a(aa_entry_a),
.entry_b(ab_entry_b),
.tlu_on(1'b0),
.left_shift_off(1'b1),
.left_shift_on(1'b0),
.no_carry_insert(1'b0),
.no_carry_blank(1'b0),
.carry_insert(1'b0),
.carry_blank(1'b0),
.zero_insert(1'b0),
.error_reset(oc_err_reset),
.quotient_digit_on(1'b0),
.overflow_stop_sw(1'b1), // missing from oc_
.overflow_sense_sw(1'b0), // ditto
.mult_div_off(1'b0),
.dist_true_add_gate(1'b0),
.acc_true_add_latch(1'b0),
.shift_overflow(1'b0),
.adder_out(ad_adder_out),
.carry_test(ad_carry_test),
.no_carry_test(ad_no_carry_test),
.d0l_carry_sig(ad_d0l_carry_sig),
.overflow_stop(ad_overflow_stop),
.overflow_light(ad_overflow_light),
.overflow_sense_sig(ad_overflow_sense_sig)
);
addr_reg ar (
.rst(rst),
.ap(ap),
382,6 → 430,7
.dist_ontime(ds_ontime_out),
.prog_ontime(ps_ontime_out),
.command(command),
.restart_reset(1'b0),
.data_out(oc_data_out),
.addr_out(oc_addr_out),
.console_out(oc_console_out),
407,7 → 456,8
.hard_reset(oc_hard_reset),
.cmd_digit_out(cmd_digit_out),
.busy(busy),
.digit_ready(digit_ready),
.digit_ready(digit_ready),
.restart_reset_busy(oc_restart_reset_busy),
.punch_card(punch_card),
.read_card(read_card),
.card_digit_ready(card_digit_ready)

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