OpenCores

0,0 → 1,99

trunk/doc/src/opencores_logo.eps Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/doc/src/iicmb_mb.odt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/src/iicmb_mb.odt =================================================================== --- trunk/doc/src/iicmb_mb.odt (nonexistent) +++ trunk/doc/src/iicmb_mb.odt (revision 2)

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trunk/doc/src/wishbone_compatible.svg Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/doc/iicmb_mb.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/iicmb_mb.pdf =================================================================== --- trunk/doc/iicmb_mb.pdf (nonexistent) +++ trunk/doc/iicmb_mb.pdf (revision 2)

trunk/doc/iicmb_mb.pdf Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: trunk/src/iicmb_m.vhd =================================================================== --- trunk/src/iicmb_m.vhd (nonexistent) +++ trunk/src/iicmb_m.vhd (revision 2) @@ -0,0 +1,354 @@ + +--============================================================================== +-- | +-- Project: IIC Multiple Bus Controller (IICMB) | +-- | +-- Module: I2C master controller with 'Generic Interface'. | +-- Version: | +-- 1.0, April 29, 2016 | +-- | +-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | +-- | +--============================================================================== +--============================================================================== +-- Copyright (c) 2016, Sergey Shuvalkin | +-- All rights reserved. | +-- | +-- Redistribution and use in source and binary forms, with or without | +-- modification, are permitted provided that the following conditions are met: | +-- | +-- 1. Redistributions of source code must retain the above copyright notice, | +-- this list of conditions and the following disclaimer. | +-- 2. Redistributions in binary form must reproduce the above copyright | +-- notice, this list of conditions and the following disclaimer in the | +-- documentation and/or other materials provided with the distribution. | +-- | +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | +-- POSSIBILITY OF SUCH DAMAGE. | +--============================================================================== + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.iicmb_pkg.all; +use work.iicmb_int_pkg.all; + + +--============================================================================== +entity iicmb_m is + generic + ( + ------------------------------------ + g_bus_num : positive range 1 to 16 := 1; -- Number of separate I2C buses + g_f_clk : real := 100000.0; -- Frequency of system clock 'clk' (in kHz) + g_f_scl_0 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #0 (in kHz) + g_f_scl_1 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #1 (in kHz) + g_f_scl_2 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #2 (in kHz) + g_f_scl_3 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #3 (in kHz) + g_f_scl_4 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #4 (in kHz) + g_f_scl_5 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #5 (in kHz) + g_f_scl_6 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #6 (in kHz) + g_f_scl_7 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #7 (in kHz) + g_f_scl_8 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #8 (in kHz) + g_f_scl_9 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #9 (in kHz) + g_f_scl_a : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #10 (in kHz) + g_f_scl_b : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #11 (in kHz) + g_f_scl_c : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #12 (in kHz) + g_f_scl_d : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #13 (in kHz) + g_f_scl_e : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #14 (in kHz) + g_f_scl_f : real := 100.0 -- Frequency of 'SCL' clock of I2C bus #15 (in kHz) + ------------------------------------ + ); + port + ( + ------------------------------------ + clk : in std_logic; -- Clock + s_rst : in std_logic; -- Synchronous reset (active high) + ------------------------------------ + ------------------------------------ + -- Status: + busy : out std_logic; -- Bus busy status + captured : out std_logic; -- Bus captured status + bus_id : out std_logic_vector(3 downto 0); -- ID of selected I2C bus + bit_state : out std_logic_vector(3 downto 0); -- State of bit level FSM + byte_state : out std_logic_vector(3 downto 0); -- State of byte level FSM + ------------------------------------ + ------------------------------------ + -- 'Generic interface' signals: + mcmd_wr : in std_logic; -- Byte command write (active high) + mcmd_id : in std_logic_vector(2 downto 0); -- Byte command ID + mcmd_data : in std_logic_vector(7 downto 0); -- Command data + -- + mrsp_wr : out std_logic; -- Byte response write (active high) + mrsp_id : out std_logic_vector(2 downto 0); -- Byte response ID + mrsp_data : out std_logic_vector(7 downto 0); -- Byte Response data + ------------------------------------ + ------------------------------------ + -- I2C buses: + scl_i : in std_logic_vector(0 to g_bus_num - 1); -- I2C Clock inputs + sda_i : in std_logic_vector(0 to g_bus_num - 1); -- I2C Data inputs + scl_o : out std_logic_vector(0 to g_bus_num - 1); -- I2C Clock outputs + sda_o : out std_logic_vector(0 to g_bus_num - 1) -- I2C Data outputs + ------------------------------------ + ); +end entity iicmb_m; +--============================================================================== + +--============================================================================== +architecture str of iicmb_m is + + ------------------------------------------------------------------------------ + component conditioner_mux is + generic + ( + g_bus_num : positive range 1 to 16 := 1; + g_f_clk : real := 100000.0; + g_f_scl_0 : real := 100.0; + g_f_scl_1 : real := 100.0; + g_f_scl_2 : real := 100.0; + g_f_scl_3 : real := 100.0; + g_f_scl_4 : real := 100.0; + g_f_scl_5 : real := 100.0; + g_f_scl_6 : real := 100.0; + g_f_scl_7 : real := 100.0; + g_f_scl_8 : real := 100.0; + g_f_scl_9 : real := 100.0; + g_f_scl_a : real := 100.0; + g_f_scl_b : real := 100.0; + g_f_scl_c : real := 100.0; + g_f_scl_d : real := 100.0; + g_f_scl_e : real := 100.0; + g_f_scl_f : real := 100.0 + ); + port + ( + clk : in std_logic; + s_rst : in std_logic; + bus_id : in natural range 0 to g_bus_num - 1; + busy : out std_logic := '0'; + scl_rx : out std_logic := '1'; + sda_rx : out std_logic := '1'; + scl_d_rx : out std_logic := '1'; + scl_tx : in std_logic; + sda_tx : in std_logic; + scl_i : in std_logic_vector(0 to g_bus_num - 1); + sda_i : in std_logic_vector(0 to g_bus_num - 1); + scl_o : out std_logic_vector(0 to g_bus_num - 1); + sda_o : out std_logic_vector(0 to g_bus_num - 1) + ); + end component conditioner_mux; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + component mbit is + generic + ( + g_bus_num : positive range 1 to 16 := 1; + g_f_clk : real := 100000.0; + g_f_scl_0 : real := 100.0; + g_f_scl_1 : real := 100.0; + g_f_scl_2 : real := 100.0; + g_f_scl_3 : real := 100.0; + g_f_scl_4 : real := 100.0; + g_f_scl_5 : real := 100.0; + g_f_scl_6 : real := 100.0; + g_f_scl_7 : real := 100.0; + g_f_scl_8 : real := 100.0; + g_f_scl_9 : real := 100.0; + g_f_scl_a : real := 100.0; + g_f_scl_b : real := 100.0; + g_f_scl_c : real := 100.0; + g_f_scl_d : real := 100.0; + g_f_scl_e : real := 100.0; + g_f_scl_f : real := 100.0 + ); + port + ( + clk : in std_logic; + s_rst : in std_logic; + fsm_state : out std_logic_vector(3 downto 0); + bus_id : in natural range 0 to g_bus_num - 1; + mbc_wr : in std_logic; + mbc : in mbc_type; + mbr_wr : out std_logic := '0'; + mbr : out mbr_type := mbr_done; + scl_i : in std_logic; + sda_i : in std_logic; + scl_i_d : in std_logic; + scl_o : out std_logic := '1'; + sda_o : out std_logic := '1' + ); + end component mbit; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + component mbyte is + generic + ( + g_bus_num : positive range 1 to 16 := 1; + g_f_clk : real := 100000.0 + ); + port + ( + clk : in std_logic; + s_rst : in std_logic; + captured : out std_logic; + busy : in std_logic; + bus_id : out natural range 0 to g_bus_num - 1 := 0; + fsm_state : out std_logic_vector(3 downto 0); + mcmd_wr : in std_logic; + mcmd_id : in std_logic_vector(2 downto 0); + mcmd_data : in std_logic_vector(7 downto 0); + mrsp_wr : out std_logic := '0'; + mrsp_id : out std_logic_vector(2 downto 0) := mrsp_done; + mrsp_data : out std_logic_vector(7 downto 0); + mbc_wr : out std_logic := '0'; + mbc : out mbc_type := mbc_stop; + mbr_wr : in std_logic; + mbr : in mbr_type + ); + end component mbyte; + ------------------------------------------------------------------------------ + + signal bus_id_y : natural range 0 to g_bus_num - 1; + signal busy_y : std_logic; + signal scl_rx : std_logic; + signal sda_rx : std_logic; + signal scl_d_rx : std_logic; + signal scl_tx : std_logic; + signal sda_tx : std_logic; + + signal mbc_wr : std_logic; + signal mbc : mbc_type; + signal mbr_wr : std_logic; + signal mbr : mbr_type; + +begin + + busy <= busy_y; + bus_id <= std_logic_vector(to_unsigned(bus_id_y, 4)); + + ------------------------------------------------------------------------------ + mbyte_inst0 : mbyte + generic map + ( + g_bus_num => g_bus_num, + g_f_clk => g_f_clk + ) + port map + ( + clk => clk, + s_rst => s_rst, + captured => captured, + busy => busy_y, + bus_id => bus_id_y, + fsm_state => byte_state, + mcmd_wr => mcmd_wr, + mcmd_id => mcmd_id, + mcmd_data => mcmd_data, + mrsp_wr => mrsp_wr, + mrsp_id => mrsp_id, + mrsp_data => mrsp_data, + mbc_wr => mbc_wr, + mbc => mbc, + mbr_wr => mbr_wr, + mbr => mbr + ); + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + mbit_inst0 : mbit + generic map + ( + g_bus_num => g_bus_num, + g_f_clk => g_f_clk, + g_f_scl_0 => g_f_scl_0, + g_f_scl_1 => g_f_scl_1, + g_f_scl_2 => g_f_scl_2, + g_f_scl_3 => g_f_scl_3, + g_f_scl_4 => g_f_scl_4, + g_f_scl_5 => g_f_scl_5, + g_f_scl_6 => g_f_scl_6, + g_f_scl_7 => g_f_scl_7, + g_f_scl_8 => g_f_scl_8, + g_f_scl_9 => g_f_scl_9, + g_f_scl_a => g_f_scl_a, + g_f_scl_b => g_f_scl_b, + g_f_scl_c => g_f_scl_c, + g_f_scl_d => g_f_scl_d, + g_f_scl_e => g_f_scl_e, + g_f_scl_f => g_f_scl_f + ) + port map + ( + clk => clk, + s_rst => s_rst, + fsm_state => bit_state, + bus_id => bus_id_y, + mbc_wr => mbc_wr, + mbc => mbc, + mbr_wr => mbr_wr, + mbr => mbr, + scl_i => scl_rx, + sda_i => sda_rx, + scl_i_d => scl_d_rx, + scl_o => scl_tx, + sda_o => sda_tx + ); + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + conditioner_mux_inst0 : conditioner_mux + generic map + ( + g_bus_num => g_bus_num, + g_f_clk => g_f_clk, + g_f_scl_0 => g_f_scl_0, + g_f_scl_1 => g_f_scl_1, + g_f_scl_2 => g_f_scl_2, + g_f_scl_3 => g_f_scl_3, + g_f_scl_4 => g_f_scl_4, + g_f_scl_5 => g_f_scl_5, + g_f_scl_6 => g_f_scl_6, + g_f_scl_7 => g_f_scl_7, + g_f_scl_8 => g_f_scl_8, + g_f_scl_9 => g_f_scl_9, + g_f_scl_a => g_f_scl_a, + g_f_scl_b => g_f_scl_b, + g_f_scl_c => g_f_scl_c, + g_f_scl_d => g_f_scl_d, + g_f_scl_e => g_f_scl_e, + g_f_scl_f => g_f_scl_f + ) + port map + ( + clk => clk, + s_rst => s_rst, + bus_id => bus_id_y, + busy => busy_y, + scl_rx => scl_rx, + sda_rx => sda_rx, + scl_d_rx => scl_d_rx, + scl_tx => scl_tx, + sda_tx => sda_tx, + scl_i => scl_i, + sda_i => sda_i, + scl_o => scl_o, + sda_o => sda_o + ); + ------------------------------------------------------------------------------ + +end architecture str; +--============================================================================== +

trunk/src/iicmb_m.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/iicmb_m_sq.vhd =================================================================== --- trunk/src/iicmb_m_sq.vhd (nonexistent) +++ trunk/src/iicmb_m_sq.vhd (revision 2) @@ -0,0 +1,263 @@ + +--============================================================================== +-- | +-- Project: IIC Multiple Bus Controller (IICMB) | +-- | +-- Module: Top level of IICMB controller with sequencer. | +-- Version: | +-- 1.0, April 29, 2016 | +-- | +-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | +-- | +--============================================================================== +--============================================================================== +-- Copyright (c) 2016, Sergey Shuvalkin | +-- All rights reserved. | +-- | +-- Redistribution and use in source and binary forms, with or without | +-- modification, are permitted provided that the following conditions are met: | +-- | +-- 1. Redistributions of source code must retain the above copyright notice, | +-- this list of conditions and the following disclaimer. | +-- 2. Redistributions in binary form must reproduce the above copyright | +-- notice, this list of conditions and the following disclaimer in the | +-- documentation and/or other materials provided with the distribution. | +-- | +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | +-- POSSIBILITY OF SUCH DAMAGE. | +--============================================================================== + + +library ieee; +use ieee.std_logic_1164.all; + +use work.iicmb_pkg.all; + + +--============================================================================== +entity iicmb_m_sq is + generic + ( + ------------------------------------ + g_bus_num : positive range 1 to 16 := 1; -- Number of separate I2C buses + g_f_clk : real := 100000.0; -- Frequency of system clock 'clk' (in kHz) + g_f_scl_0 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #0 (in kHz) + g_f_scl_1 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #1 (in kHz) + g_f_scl_2 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #2 (in kHz) + g_f_scl_3 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #3 (in kHz) + g_f_scl_4 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #4 (in kHz) + g_f_scl_5 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #5 (in kHz) + g_f_scl_6 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #6 (in kHz) + g_f_scl_7 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #7 (in kHz) + g_f_scl_8 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #8 (in kHz) + g_f_scl_9 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #9 (in kHz) + g_f_scl_a : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #10 (in kHz) + g_f_scl_b : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #11 (in kHz) + g_f_scl_c : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #12 (in kHz) + g_f_scl_d : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #13 (in kHz) + g_f_scl_e : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #14 (in kHz) + g_f_scl_f : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #15 (in kHz) + g_cmd : seq_cmd_type_array := c_empty_array -- Sequence of commands (supported: WAIT, SET_BUS and WRITE_BYTE) + ------------------------------------ + ); + port + ( + ------------------------------------ + clk : in std_logic; -- Clock + s_rst : in std_logic; -- Synchronous reset (active high) + ------------------------------------ + ------------------------------------ + cs_start : in std_logic; -- Start executing command sequence + cs_busy : out std_logic; -- Command sequence is being executed + cs_status : out std_logic_vector(2 downto 0); -- Execution status + ------------------------------------ + ------------------------------------ + -- I2C interfaces: + scl_i : in std_logic_vector(0 to g_bus_num - 1); -- I2C Clock inputs + sda_i : in std_logic_vector(0 to g_bus_num - 1); -- I2C Data inputs + scl_o : out std_logic_vector(0 to g_bus_num - 1); -- I2C Clock outputs + sda_o : out std_logic_vector(0 to g_bus_num - 1) -- I2C Data outputs + ------------------------------------ + ); +end entity iicmb_m_sq; +--============================================================================== + +--============================================================================== +architecture str of iicmb_m_sq is + + ------------------------------------------------------------------------------ + component sequencer is + generic + ( + g_cmd : seq_cmd_type_array := c_empty_array + ); + port + ( + clk : in std_logic; + s_rst : in std_logic; + cs_start : in std_logic; + cs_busy : out std_logic; + cs_status : out std_logic_vector(2 downto 0); + busy : in std_logic; + captured : in std_logic; + bus_id : in std_logic_vector(3 downto 0); + bit_state : in std_logic_vector(3 downto 0); + byte_state : in std_logic_vector(3 downto 0); + mcmd_wr : out std_logic; + mcmd_id : out std_logic_vector(2 downto 0); + mcmd_data : out std_logic_vector(7 downto 0); + mrsp_wr : in std_logic; + mrsp_id : in std_logic_vector(2 downto 0); + mrsp_data : in std_logic_vector(7 downto 0) + ); + end component sequencer; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + component iicmb_m is + generic + ( + g_bus_num : positive range 1 to 16 := 1; + g_f_clk : real := 100000.0; + g_f_scl_0 : real := 100.0; + g_f_scl_1 : real := 100.0; + g_f_scl_2 : real := 100.0; + g_f_scl_3 : real := 100.0; + g_f_scl_4 : real := 100.0; + g_f_scl_5 : real := 100.0; + g_f_scl_6 : real := 100.0; + g_f_scl_7 : real := 100.0; + g_f_scl_8 : real := 100.0; + g_f_scl_9 : real := 100.0; + g_f_scl_a : real := 100.0; + g_f_scl_b : real := 100.0; + g_f_scl_c : real := 100.0; + g_f_scl_d : real := 100.0; + g_f_scl_e : real := 100.0; + g_f_scl_f : real := 100.0 + ); + port + ( + clk : in std_logic; + s_rst : in std_logic; + busy : out std_logic; + captured : out std_logic; + bus_id : out std_logic_vector(3 downto 0); + bit_state : out std_logic_vector(3 downto 0); + byte_state : out std_logic_vector(3 downto 0); + mcmd_wr : in std_logic; + mcmd_id : in std_logic_vector(2 downto 0); + mcmd_data : in std_logic_vector(7 downto 0); + mrsp_wr : out std_logic; + mrsp_id : out std_logic_vector(2 downto 0); + mrsp_data : out std_logic_vector(7 downto 0); + scl_i : in std_logic_vector(0 to g_bus_num - 1); + sda_i : in std_logic_vector(0 to g_bus_num - 1); + scl_o : out std_logic_vector(0 to g_bus_num - 1); + sda_o : out std_logic_vector(0 to g_bus_num - 1) + ); + end component iicmb_m; + ------------------------------------------------------------------------------ + + signal busy : std_logic; + signal captured : std_logic; + signal bus_id : std_logic_vector( 3 downto 0); + signal bit_state : std_logic_vector( 3 downto 0); + signal byte_state : std_logic_vector( 3 downto 0); + + -- Signals of 'Generic Interface': + -- Command: + signal mcmd_wr : std_logic; + signal mcmd_id : std_logic_vector( 2 downto 0); + signal mcmd_data : std_logic_vector( 7 downto 0); + -- Response: + signal mrsp_wr : std_logic; + signal mrsp_id : std_logic_vector( 2 downto 0); + signal mrsp_data : std_logic_vector( 7 downto 0); + +begin + + ------------------------------------------------------------------------------ + sequencer_inst0 : sequencer + generic map + ( + g_cmd => g_cmd + ) + port map + ( + clk => clk, + s_rst => s_rst, + cs_start => cs_start, + cs_busy => cs_busy, + cs_status => cs_status, + busy => busy, + captured => captured, + bus_id => bus_id, + bit_state => bit_state, + byte_state => byte_state, + mcmd_wr => mcmd_wr, + mcmd_id => mcmd_id, + mcmd_data => mcmd_data, + mrsp_wr => mrsp_wr, + mrsp_id => mrsp_id, + mrsp_data => mrsp_data + ); + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + iicmb_m_inst0 : iicmb_m + generic map + ( + g_bus_num => g_bus_num, + g_f_clk => g_f_clk, + g_f_scl_0 => g_f_scl_0, + g_f_scl_1 => g_f_scl_1, + g_f_scl_2 => g_f_scl_2, + g_f_scl_3 => g_f_scl_3, + g_f_scl_4 => g_f_scl_4, + g_f_scl_5 => g_f_scl_5, + g_f_scl_6 => g_f_scl_6, + g_f_scl_7 => g_f_scl_7, + g_f_scl_8 => g_f_scl_8, + g_f_scl_9 => g_f_scl_9, + g_f_scl_a => g_f_scl_a, + g_f_scl_b => g_f_scl_b, + g_f_scl_c => g_f_scl_c, + g_f_scl_d => g_f_scl_d, + g_f_scl_e => g_f_scl_e, + g_f_scl_f => g_f_scl_f + ) + port map + ( + clk => clk, + s_rst => s_rst, + busy => busy, + captured => captured, + bus_id => bus_id, + bit_state => bit_state, + byte_state => byte_state, + mcmd_wr => mcmd_wr, + mcmd_id => mcmd_id, + mcmd_data => mcmd_data, + mrsp_wr => mrsp_wr, + mrsp_id => mrsp_id, + mrsp_data => mrsp_data, + scl_i => scl_i, + sda_i => sda_i, + scl_o => scl_o, + sda_o => sda_o + ); + ------------------------------------------------------------------------------ + +end architecture str; +--============================================================================== +

trunk/src/iicmb_m_sq.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/conditioner_mux.vhd =================================================================== --- trunk/src/conditioner_mux.vhd (nonexistent) +++ trunk/src/conditioner_mux.vhd (revision 2) @@ -0,0 +1,213 @@ + +--============================================================================== +-- | +-- Project: IIC Multiple Bus Controller (IICMB) | +-- | +-- Module: Multiplexer of I2C buses. | +-- Version: | +-- 1.0, April 29, 2016 | +-- | +-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | +-- | +--============================================================================== +--============================================================================== +-- Copyright (c) 2016, Sergey Shuvalkin | +-- All rights reserved. | +-- | +-- Redistribution and use in source and binary forms, with or without | +-- modification, are permitted provided that the following conditions are met: | +-- | +-- 1. Redistributions of source code must retain the above copyright notice, | +-- this list of conditions and the following disclaimer. | +-- 2. Redistributions in binary form must reproduce the above copyright | +-- notice, this list of conditions and the following disclaimer in the | +-- documentation and/or other materials provided with the distribution. | +-- | +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | +-- POSSIBILITY OF SUCH DAMAGE. | +--============================================================================== + + +library ieee; +use ieee.std_logic_1164.all; + + +--============================================================================== +entity conditioner_mux is + generic + ( + ------------------------------------ + g_bus_num : positive range 1 to 16 := 1; -- Number of separate I2C busses + g_f_clk : real := 100000.0; -- Frequency of 'clk' clock (in kHz) + g_f_scl_0 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #0 (in kHz) + g_f_scl_1 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #1 (in kHz) + g_f_scl_2 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #2 (in kHz) + g_f_scl_3 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #3 (in kHz) + g_f_scl_4 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #4 (in kHz) + g_f_scl_5 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #5 (in kHz) + g_f_scl_6 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #6 (in kHz) + g_f_scl_7 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #7 (in kHz) + g_f_scl_8 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #8 (in kHz) + g_f_scl_9 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #9 (in kHz) + g_f_scl_a : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #10 (in kHz) + g_f_scl_b : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #11 (in kHz) + g_f_scl_c : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #12 (in kHz) + g_f_scl_d : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #13 (in kHz) + g_f_scl_e : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #14 (in kHz) + g_f_scl_f : real := 100.0 -- Frequency of 'SCL' clock of I2C bus #15 (in kHz) + ------------------------------------ + ); + port + ( + ------------------------------------ + clk : in std_logic; -- Clock + s_rst : in std_logic; -- Synchronous reset (active high) + ------------------------------------ + ------------------------------------ + -- Interface to controller: + bus_id : in natural range 0 to g_bus_num - 1; + -- + busy : out std_logic := '0'; -- Bus busy indication (busy = high) + -- + scl_rx : out std_logic := '1'; -- Conditioned I2C Clock + sda_rx : out std_logic := '1'; -- Conditioned I2C Data + -- + scl_d_rx : out std_logic := '1'; -- Conditioned I2C Clock delayed for 1 'clk' cycle + -- + scl_tx : in std_logic; -- I2C Clock from bit controller + sda_tx : in std_logic; -- I2C Data from bit controller + ------------------------------------ + ------------------------------------ + -- I2C interfaces: + scl_i : in std_logic_vector(0 to g_bus_num - 1); -- I2C Clock inputs + sda_i : in std_logic_vector(0 to g_bus_num - 1); -- I2C Data inputs + scl_o : out std_logic_vector(0 to g_bus_num - 1); -- I2C Clock outputs + sda_o : out std_logic_vector(0 to g_bus_num - 1) -- I2C Data outputs + ------------------------------------ + ); +end entity conditioner_mux; +--============================================================================== + +--============================================================================== +architecture str of conditioner_mux is + + type real_array is array (natural range <>) of real; + constant c_f_scl : real_array(0 to 15) := (g_f_scl_0, g_f_scl_1, g_f_scl_2, g_f_scl_3, + g_f_scl_4, g_f_scl_5, g_f_scl_6, g_f_scl_7, + g_f_scl_8, g_f_scl_9, g_f_scl_a, g_f_scl_b, + g_f_scl_c, g_f_scl_d, g_f_scl_e, g_f_scl_f); + + ------------------------------------------------------------------------------ + component conditioner is + generic + ( + g_f_clk : real := 100000.0; + g_f_scl : real := 100.0 + ); + port + ( + clk : in std_logic; + s_rst : in std_logic; + busy : out std_logic; + scl_rx : out std_logic; + sda_rx : out std_logic; + scl_d_rx : out std_logic; + scl_tx : in std_logic; + sda_tx : in std_logic; + scl_i : in std_logic; + sda_i : in std_logic; + scl_o : out std_logic; + sda_o : out std_logic + ); + end component conditioner; + ------------------------------------------------------------------------------ + + signal scl_rx_y : std_logic_vector(0 to g_bus_num - 1); + signal sda_rx_y : std_logic_vector(0 to g_bus_num - 1); + signal scl_d_rx_y : std_logic_vector(0 to g_bus_num - 1); + signal busy_y : std_logic_vector(0 to g_bus_num - 1); + signal scl_tx_y : std_logic_vector(0 to g_bus_num - 1) := (others => '1'); + signal sda_tx_y : std_logic_vector(0 to g_bus_num - 1) := (others => '1'); + +begin + + ------------------------------------------------------------------------------ + process(clk) + begin + if rising_edge(clk) then + if (s_rst = '1') then + busy <= '0'; + scl_rx <= '1'; + sda_rx <= '1'; + scl_d_rx <= '1'; + else + busy <= busy_y(bus_id); + scl_rx <= scl_rx_y(bus_id); + sda_rx <= sda_rx_y(bus_id); + scl_d_rx <= scl_d_rx_y(bus_id); + end if; + end if; + end process; + ------------------------------------------------------------------------------ + + --**************************************************************************** + scl_sda_gen: + for i in 0 to g_bus_num - 1 generate + ---------------------------------------------------------------------------- + conditioner_inst0 : conditioner + generic map + ( + g_f_clk => g_f_clk, + g_f_scl => c_f_scl(i) + ) + port map + ( + clk => clk, + s_rst => s_rst, + busy => busy_y(i), + scl_rx => scl_rx_y(i), + sda_rx => sda_rx_y(i), + scl_d_rx => scl_d_rx_y(i), + scl_tx => scl_tx_y(i), + sda_tx => sda_tx_y(i), + scl_i => scl_i(i), + sda_i => sda_i(i), + scl_o => scl_o(i), + sda_o => sda_o(i) + ); + ---------------------------------------------------------------------------- + + ---------------------------------------------------------------------------- + process(clk) + begin + if rising_edge(clk) then + if (s_rst = '1') then + scl_tx_y(i) <= '1'; + sda_tx_y(i) <= '1'; + else + if (i = bus_id) then + scl_tx_y(i) <= scl_tx; + sda_tx_y(i) <= sda_tx; + else + scl_tx_y(i) <= '1'; + sda_tx_y(i) <= '1'; + end if; + end if; + end if; + end process; + ---------------------------------------------------------------------------- + end generate scl_sda_gen; + --**************************************************************************** + +end architecture str; +--============================================================================== +

trunk/src/conditioner_mux.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/avalon_mm.vhd =================================================================== --- trunk/src/avalon_mm.vhd (nonexistent) +++ trunk/src/avalon_mm.vhd (revision 2) @@ -0,0 +1,101 @@ + +--============================================================================== +-- | +-- Project: IIC Multiple Bus Controller (IICMB) | +-- | +-- Module: Avalon-MM adapter. | +-- Version: | +-- 1.0, April 29, 2016 | +-- | +-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | +-- | +--============================================================================== +--============================================================================== +-- Copyright (c) 2016, Sergey Shuvalkin | +-- All rights reserved. | +-- | +-- Redistribution and use in source and binary forms, with or without | +-- modification, are permitted provided that the following conditions are met: | +-- | +-- 1. Redistributions of source code must retain the above copyright notice, | +-- this list of conditions and the following disclaimer. | +-- 2. Redistributions in binary form must reproduce the above copyright | +-- notice, this list of conditions and the following disclaimer in the | +-- documentation and/or other materials provided with the distribution. | +-- | +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | +-- POSSIBILITY OF SUCH DAMAGE. | +--============================================================================== + + +library ieee; +use ieee.std_logic_1164.all; + + +--============================================================================== +entity avalon_mm is + port + ( + ------------------------------------ + clk : in std_logic; -- Clock input + s_rst : in std_logic; -- Synchronous reset (active high) + ------------------------------------ + ------------------------------------ + -- Avalon-MM slave interface: + waitrequest : out std_logic; + readdata : out std_logic_vector(31 downto 0); + readdatavalid : out std_logic; + writedata : in std_logic_vector(31 downto 0); + write : in std_logic; + read : in std_logic; + byteenable : in std_logic_vector( 3 downto 0); + ------------------------------------ + ------------------------------------ + -- Regblock interface: + wr : out std_logic_vector( 3 downto 0); -- Write (active high) + rd : out std_logic_vector( 3 downto 0); -- Read (active high) + idata : out std_logic_vector(31 downto 0); -- Data from System Bus + odata : in std_logic_vector(31 downto 0) -- Data to System Bus + ------------------------------------ + ); +end entity avalon_mm; +--============================================================================== + +--============================================================================== +architecture rtl of avalon_mm is + +begin + + waitrequest <= '0'; + wr <= (3 downto 0 => write) and byteenable; + rd <= (3 downto 0 => read ) and byteenable; + idata <= writedata; + + ------------------------------------------------------------------------------ + readdata_proc: + process(clk) + begin + if rising_edge(clk) then + if (s_rst = '1') then + readdata <= (others => '0'); + readdatavalid <= '0'; + else + readdata <= odata; + readdatavalid <= read; + end if; + end if; + end process readdata_proc; + ------------------------------------------------------------------------------ + +end architecture rtl; +--============================================================================== +

trunk/src/avalon_mm.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/conditioner.vhd =================================================================== --- trunk/src/conditioner.vhd (nonexistent) +++ trunk/src/conditioner.vhd (revision 2) @@ -0,0 +1,221 @@ + +--============================================================================== +-- | +-- Project: IIC Multiple Bus Controller (IICMB) | +-- | +-- Module: Signal conditioner. | +-- Version: | +-- 1.0, April 29, 2016 | +-- | +-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | +-- | +--============================================================================== +--============================================================================== +-- Copyright (c) 2016, Sergey Shuvalkin | +-- All rights reserved. | +-- | +-- Redistribution and use in source and binary forms, with or without | +-- modification, are permitted provided that the following conditions are met: | +-- | +-- 1. Redistributions of source code must retain the above copyright notice, | +-- this list of conditions and the following disclaimer. | +-- 2. Redistributions in binary form must reproduce the above copyright | +-- notice, this list of conditions and the following disclaimer in the | +-- documentation and/or other materials provided with the distribution. | +-- | +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | +-- POSSIBILITY OF SUCH DAMAGE. | +--============================================================================== + + +library ieee; +use ieee.std_logic_1164.all; + + +--============================================================================== +entity conditioner is + generic + ( + ------------------------------------ + g_f_clk : real := 100000.0; -- Frequency of 'clk' input (in kHz) + g_f_scl : real := 100.0 -- Frequency of 'scl_i' input (in kHz) + ------------------------------------ + ); + port + ( + ------------------------------------ + clk : in std_logic; -- Clock + s_rst : in std_logic; -- Synchronous reset (active high) + ------------------------------------ + ------------------------------------ + -- Interface to I2C FSMs: + busy : out std_logic; -- Bus busy indication (busy = high) + -- + scl_rx : out std_logic; -- Filtered I2C Clock + sda_rx : out std_logic; -- Filtered I2C Data + -- + scl_d_rx : out std_logic; -- Filtered and delayed I2C Clock + -- + scl_tx : in std_logic; -- I2C Clock from FSMs + sda_tx : in std_logic; -- I2C Data from FSMs + ------------------------------------ + ------------------------------------ + -- I2C bus signals: + scl_i : in std_logic; -- I2C Clock input + sda_i : in std_logic; -- I2C Data input + scl_o : out std_logic; -- I2C Clock output + sda_o : out std_logic -- I2C Data output + ------------------------------------ + ); +end entity conditioner; +--============================================================================== + +--============================================================================== +architecture str of conditioner is + + ------------------------------------------------------------------------------ + component bus_state is + generic + ( + g_f_clk : real := 100000.0; + g_f_scl : real := 100.0 + ); + port + ( + clk : in std_logic; + s_rst : in std_logic; + busy : out std_logic; + scl_d : out std_logic; + scl : in std_logic; + sda : in std_logic + ); + end component bus_state; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + component filter is + generic + ( + g_cycles : positive := 10 + ); + port + ( + clk : in std_logic; + s_rst : in std_logic; + sig_in : in std_logic; + sig_out : out std_logic + ); + end component filter; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + function get_cycles(a : real) return positive is + variable ret : positive; + begin + ret := 4 + integer((4.0*a)/50000.0); + return ret; + end function get_cycles; + ------------------------------------------------------------------------------ + + constant c_cycles : positive := get_cycles(g_f_clk); + + signal scl_i_ndeb_1 : std_logic; + signal sda_i_ndeb_1 : std_logic; + signal scl_i_ndeb_2 : std_logic; + signal sda_i_ndeb_2 : std_logic; + signal scl_i_deb : std_logic; + signal sda_i_deb : std_logic; + +begin + + -- ########################################################################### + -- # Debouncing SCL and SDA signals # + -- ########################################################################### + ------------------------------------------------------------------------------ + -- Metastability elimination: + process(clk) + begin + if rising_edge(clk) then + if (s_rst = '1') then + scl_i_ndeb_1 <= '1'; + scl_i_ndeb_2 <= '1'; + sda_i_ndeb_1 <= '1'; + sda_i_ndeb_2 <= '1'; + else + scl_i_ndeb_1 <= to_x01(scl_i); + scl_i_ndeb_2 <= scl_i_ndeb_1; + sda_i_ndeb_1 <= to_x01(sda_i); + sda_i_ndeb_2 <= sda_i_ndeb_1; + end if; + end if; + end process; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + scl_filter : filter + generic map + ( + g_cycles => c_cycles + ) + port map + ( + clk => clk, + s_rst => s_rst, + sig_in => scl_i_ndeb_2, + sig_out => scl_i_deb + ); + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + sda_filter : filter + generic map + ( + g_cycles => c_cycles + ) + port map + ( + clk => clk, + s_rst => s_rst, + sig_in => sda_i_ndeb_2, + sig_out => sda_i_deb + ); + ------------------------------------------------------------------------------ + -- ########################################################################### + -- # End of debouncing SCL and SDA signals # + -- ########################################################################### + + ------------------------------------------------------------------------------ + bus_state_inst0 : bus_state + generic map + ( + g_f_clk => g_f_clk, + g_f_scl => g_f_scl + ) + port map + ( + clk => clk, + s_rst => s_rst, + busy => busy, + scl_d => scl_d_rx, + scl => scl_i_deb, + sda => sda_i_deb + ); + ------------------------------------------------------------------------------ + + scl_rx <= scl_i_deb; + sda_rx <= sda_i_deb; + scl_o <= scl_tx; + sda_o <= sda_tx; + +end architecture str; +--============================================================================== +

trunk/src/conditioner.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/wishbone.vhd =================================================================== --- trunk/src/wishbone.vhd (nonexistent) +++ trunk/src/wishbone.vhd (revision 2) @@ -0,0 +1,133 @@ + +--============================================================================== +-- | +-- Project: IIC Multiple Bus Controller (IICMB) | +-- | +-- Module: Wishbone adapter. | +-- Version: | +-- 1.0, April 29, 2016 | +-- | +-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | +-- | +--============================================================================== +--============================================================================== +-- Copyright (c) 2016, Sergey Shuvalkin | +-- All rights reserved. | +-- | +-- Redistribution and use in source and binary forms, with or without | +-- modification, are permitted provided that the following conditions are met: | +-- | +-- 1. Redistributions of source code must retain the above copyright notice, | +-- this list of conditions and the following disclaimer. | +-- 2. Redistributions in binary form must reproduce the above copyright | +-- notice, this list of conditions and the following disclaimer in the | +-- documentation and/or other materials provided with the distribution. | +-- | +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | +-- POSSIBILITY OF SUCH DAMAGE. | +--============================================================================== + + +library ieee; +use ieee.std_logic_1164.all; + + +--============================================================================== +entity wishbone is + port + ( + ------------------------------------ + clk_i : in std_logic; -- Clock input + rst_i : in std_logic; -- Synchronous reset (active high) + ------------------------------------ + ------------------------------------ + -- Wishbone slave interface: + cyc_i : in std_logic; -- + stb_i : in std_logic; -- + ack_o : out std_logic; -- + adr_i : in std_logic_vector( 1 downto 0); -- Low bits of Wishbone address + we_i : in std_logic; -- + dat_i : in std_logic_vector( 7 downto 0); -- Data input + dat_o : out std_logic_vector( 7 downto 0); -- Data output + ------------------------------------ + ------------------------------------ + -- Regblock interface: + wr : out std_logic_vector( 3 downto 0); -- Write (active high) + rd : out std_logic_vector( 3 downto 0); -- Read (active high) + idata : out std_logic_vector(31 downto 0); -- Data from System Bus + odata : in std_logic_vector(31 downto 0) -- Data to System Bus + ------------------------------------ + ); +end entity wishbone; +--============================================================================== + +--============================================================================== +architecture rtl of wishbone is + + signal ack_o_y : std_logic := '0'; + signal dat_o_y : std_logic_vector(7 downto 0) := (others => '0'); + +begin + + ack_o <= ack_o_y; + dat_o <= dat_o_y; + + ------------------------------------------------------------------------------ + ack_o_proc: + process(clk_i) + begin + if rising_edge(clk_i) then + if (rst_i = '1') then + ack_o_y <= '0'; + else + if (ack_o_y = '0') then + ack_o_y <= stb_i and cyc_i; + else + ack_o_y <= '0'; + end if; + end if; + end if; + end process ack_o_proc; + ------------------------------------------------------------------------------ + + wr(0) <= stb_i and cyc_i and we_i and not(ack_o_y) when (adr_i = "00") else '0'; + wr(1) <= stb_i and cyc_i and we_i and not(ack_o_y) when (adr_i = "01") else '0'; + wr(2) <= stb_i and cyc_i and we_i and not(ack_o_y) when (adr_i = "10") else '0'; + wr(3) <= stb_i and cyc_i and we_i and not(ack_o_y) when (adr_i = "11") else '0'; + rd(0) <= stb_i and cyc_i and not(we_i) and not(ack_o_y) when (adr_i = "00") else '0'; + rd(1) <= stb_i and cyc_i and not(we_i) and not(ack_o_y) when (adr_i = "01") else '0'; + rd(2) <= stb_i and cyc_i and not(we_i) and not(ack_o_y) when (adr_i = "10") else '0'; + rd(3) <= stb_i and cyc_i and not(we_i) and not(ack_o_y) when (adr_i = "11") else '0'; + idata <= dat_i & dat_i & dat_i & dat_i; + + ------------------------------------------------------------------------------ + dat_o_proc: + process(clk_i) + begin + if rising_edge(clk_i) then + if (rst_i = '1') then + dat_o_y <= (others => '0'); + else + case (adr_i) is + when "00" => dat_o_y <= odata( 7 downto 0); + when "01" => dat_o_y <= odata(15 downto 8); + when "10" => dat_o_y <= odata(23 downto 16); + when others => dat_o_y <= odata(31 downto 24); + end case; + end if; + end if; + end process dat_o_proc; + ------------------------------------------------------------------------------ + +end architecture rtl; +--============================================================================== +

trunk/src/wishbone.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/mbyte.vhd =================================================================== --- trunk/src/mbyte.vhd (nonexistent) +++ trunk/src/mbyte.vhd (revision 2) @@ -0,0 +1,406 @@ + +--============================================================================== +-- | +-- Project: IIC Multiple Bus Controller (IICMB) | +-- | +-- Module: Byte layer FSM (master mode). | +-- Version: | +-- 1.0, April 29, 2016 | +-- | +-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | +-- | +--============================================================================== +--============================================================================== +-- Copyright (c) 2016, Sergey Shuvalkin | +-- All rights reserved. | +-- | +-- Redistribution and use in source and binary forms, with or without | +-- modification, are permitted provided that the following conditions are met: | +-- | +-- 1. Redistributions of source code must retain the above copyright notice, | +-- this list of conditions and the following disclaimer. | +-- 2. Redistributions in binary form must reproduce the above copyright | +-- notice, this list of conditions and the following disclaimer in the | +-- documentation and/or other materials provided with the distribution. | +-- | +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | +-- POSSIBILITY OF SUCH DAMAGE. | +--============================================================================== + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +use work.iicmb_pkg.all; +use work.iicmb_int_pkg.all; + + +--============================================================================== +entity mbyte is + generic + ( + ------------------------------------ + g_bus_num : positive range 1 to 16 := 1; -- Number of separate I2C buses + g_f_clk : real := 100000.0 -- Frequency of system clock 'clk' (in kHz) + ------------------------------------ + ); + port + ( + ------------------------------------ + clk : in std_logic; -- Clock + s_rst : in std_logic; -- Synchronous reset (active high) + ------------------------------------ + ------------------------------------ + captured : out std_logic := '0'; -- 'Bus is captured' indication (captured = high) + busy : in std_logic; -- 'Bus is busy' indication (busy = high) + bus_id : out natural range 0 to g_bus_num - 1 := 0; -- Bus selector + fsm_state : out std_logic_vector(3 downto 0); -- FSM state + ------------------------------------ + ------------------------------------ + mcmd_wr : in std_logic; -- Byte command write (active high) + mcmd_id : in std_logic_vector(2 downto 0); -- Byte command ID + mcmd_data : in std_logic_vector(7 downto 0); -- Byte command data + ------------------------------------ + ------------------------------------ + mrsp_wr : out std_logic := '0'; -- Byte command response write (active high) + mrsp_id : out std_logic_vector(2 downto 0) := mrsp_done; -- Byte command response control bit + mrsp_data : out std_logic_vector(7 downto 0); -- Byte command response data + ------------------------------------ + ------------------------------------ + mbc_wr : out std_logic := '0'; -- Bit command write (active high) + mbc : out mbc_type := mbc_stop; -- Bit command + ------------------------------------ + ------------------------------------ + mbr_wr : in std_logic; -- Bit command response write (active high) + mbr : in mbr_type -- Bit command response + ------------------------------------ + ); +end entity mbyte; +--============================================================================== + +--============================================================================== +architecture rtl of mbyte is + + constant c_cycle_cnt_inc : integer := 1; + constant c_cycle_cnt_max : integer := integer(g_f_clk); + constant c_cycle_cnt_thr : integer := c_cycle_cnt_max - c_cycle_cnt_inc; + + type state_type is + ( + s_idle, -- Idle + s_bus_taken, -- Bus is taken + s_start_pending, -- Waiting for right moment to capture bus + s_start, -- Sending Start Condition (Capturing the bus) + s_stop, -- Sending Stop Condition (Releasing the bus) + s_write, -- Sending a byte + s_read, -- Receiving a byte + s_wait -- Receiving a byte + ); + + ------------------------------------------------------------------------------ + -- Converting states to std_logic_vector + function to_std_logic_vector(a : state_type) return std_logic_vector is + begin + case (a) is + when s_idle => return "0000"; + when s_bus_taken => return "0001"; + when s_start_pending => return "0010"; + when s_start => return "0011"; + when s_stop => return "0100"; + when s_write => return "0101"; + when s_read => return "0110"; + when s_wait => return "0111"; + end case; + end function to_std_logic_vector; + ------------------------------------------------------------------------------ + + signal state : state_type := s_idle; + signal cnt : integer range 0 to 8 := 0; + signal sbuf : std_logic_vector(7 downto 0) := (others => '0'); + signal ack : std_logic := '0'; + signal cycle_cnt : integer range 0 to c_cycle_cnt_max := 0; + signal us_cnt : unsigned( 7 downto 0) := to_unsigned(0, 8); + +begin + + mrsp_data <= sbuf; + fsm_state <= to_std_logic_vector(state); + + ------------------------------------------------------------------------------ + -- Main FSM: + main_fsm_proc: + process(clk) + --------- + procedure bit_command(a : mbc_type) is + begin + mbc_wr <= '1'; + mbc <= a; + end procedure bit_command; + --------- + --------- + procedure bit_command(a : std_logic) is + begin + mbc_wr <= '1'; + if (a = '0') then + mbc <= mbc_write_0; + else + mbc <= mbc_write_1; + end if; + end procedure bit_command; + --------- + --------- + function get_bit(a : mbr_type) return std_logic is + begin + if (a = mbr_bit_0) then + return '0'; + else + return '1'; + end if; + end function get_bit; + --------- + --------- + procedure byte_response(a : std_logic_vector(2 downto 0)) is + begin + mrsp_wr <= '1'; + mrsp_id <= a; + end procedure byte_response; + --------- + variable v_bus_id : integer range 0 to 15; + begin + if rising_edge(clk) then + if (s_rst = '1') then + state <= s_idle; + cnt <= 0; + sbuf <= (others => '0'); + ack <= '0'; + mbc_wr <= '0'; + mbc <= mbc_stop; + mrsp_wr <= '0'; + mrsp_id <= mrsp_done; + bus_id <= 0; + captured <= '0'; + cycle_cnt <= 0; + us_cnt <= to_unsigned(0, 8); + else + -- Default: + mbc_wr <= '0'; + mrsp_wr <= '0'; + ------ + + case (state) is + -- 'Idle' state ---------------------------------- + when s_idle => + if (mcmd_wr = '1') then + case (mcmd_id) is + when mcmd_start => + -- Begin procedure of bus capturing + state <= s_start_pending; + when mcmd_set_bus => + -- Switch to another bus + state <= s_idle; + v_bus_id := to_integer(unsigned(mcmd_data(3 downto 0))); + if (v_bus_id > (g_bus_num - 1)) then + byte_response(mrsp_error); + else + bus_id <= v_bus_id; + byte_response(mrsp_done); + end if; + when mcmd_wait => + -- Wait for specified period: + state <= s_wait; + cycle_cnt <= 0; + us_cnt <= unsigned(mcmd_data); + when others => + -- Other commands are rejected in 'Idle' state + state <= s_idle; + byte_response(mrsp_error); + end case; + cnt <= 0; + end if; + captured <= '0'; + -- 'Idle' state ---------------------------------- + + -- 'Wait' state ---------------------------------- + when s_wait => + captured <= '0'; + if (us_cnt = 0) then + state <= s_idle; + byte_response(mrsp_done); + else + if (cycle_cnt < c_cycle_cnt_thr) then + cycle_cnt <= cycle_cnt + c_cycle_cnt_inc; + else + cycle_cnt <= cycle_cnt - c_cycle_cnt_thr; + us_cnt <= us_cnt - 1; + end if; + end if; + -- 'Wait' state ---------------------------------- + + -- 'Bus is Taken' state -------------------------- + when s_bus_taken => + if (mcmd_wr = '1') then + case (mcmd_id) is + when mcmd_start => + -- Generate Repeated Start condition + state <= s_start; + bit_command(mbc_start); + when mcmd_read_ack => + -- Byte reading with acknowledge + state <= s_read; + ack <= '0'; + bit_command(mbc_read); + when mcmd_read_nak => + -- Byte reading with not-acknowledge + state <= s_read; + ack <= '1'; + bit_command(mbc_read); + when mcmd_stop => + -- Issue Stop condition + state <= s_stop; + bit_command(mbc_stop); + when mcmd_write => + -- Byte writing + state <= s_write; + sbuf <= mcmd_data(6 downto 0) & '0'; + bit_command(mcmd_data(7)); + when others => + -- Other commands are rejected in 'Bus Is Taken' state + state <= s_bus_taken; + byte_response(mrsp_error); + end case; + cnt <= 0; + end if; + captured <= '1'; + -- 'Bus is Taken' state -------------------------- + + -- 'Start is Pending' state ---------------------- + when s_start_pending => + captured <= '0'; + if (busy = '0') then + state <= s_start; + bit_command(mbc_start); + end if; + -- 'Start is Pending' state ---------------------- + + -- 'Start' state --------------------------------- + when s_start => + if (mbr_wr = '1') then + if (mbr = mbr_done) then + state <= s_bus_taken; + captured <= '1'; + byte_response(mrsp_done); + else + -- (mbr = mbr_arb_lost) + state <= s_idle; + captured <= '0'; + byte_response(mrsp_arb_lost); + end if; + end if; + -- 'Start' state --------------------------------- + + -- 'Stop' state ---------------------------------- + when s_stop => + captured <= '1'; + if (mbr_wr = '1') then + state <= s_idle; + captured <= '0'; + byte_response(mrsp_done); + end if; + -- 'Stop' state ---------------------------------- + + -- 'Byte Reading' state -------------------------- + when s_read => + captured <= '1'; + if (mbr_wr = '1') then + case (cnt) is + when 8 => + if (mbr = mbr_done) then + -- Return to 'Bus Is Taken' state and + -- respond with a byte of data. + state <= s_bus_taken; + byte_response(mrsp_byte); + else + -- (mbr = mbr_arb_lost) + state <= s_idle; + captured <= '0'; + byte_response(mrsp_arb_lost); + end if; + when others => + if (mbr = mbr_error) then + state <= s_idle; + captured <= '0'; + byte_response(mrsp_error); + else + -- (mbr = mbr_bit_0)or(mbr = mbr_bit_1) + sbuf <= sbuf(6 downto 0) & get_bit(mbr); + cnt <= cnt + 1; + if (cnt = 7) then + -- Write Ack/Nak + bit_command(ack); + else + -- Read a bit + bit_command(mbc_read); + end if; + end if; + end case; + end if; + -- 'Byte Reading' state -------------------------- + + -- 'Byte Writing' state -------------------------- + when s_write => + captured <= '1'; + if (mbr_wr = '1') then + case (cnt) is + when 8 => + state <= s_bus_taken; + if (mbr = mbr_error) then + -- Something went wrong + state <= s_idle; + captured <= '0'; + byte_response(mrsp_error); + elsif (mbr = mbr_bit_0) then + -- Write is acknowledged + byte_response(mrsp_done); + else + -- Write is not acknowledged + byte_response(mrsp_nak); + end if; + when others => + if (mbr = mbr_done) then + sbuf <= sbuf(6 downto 0) & '0'; + cnt <= cnt + 1; + if (cnt = 7) then + -- Read Ack/Nak + bit_command(mbc_read); + else + -- Write a bit + bit_command(sbuf(7)); + end if; + else + -- (mbr = mbr_arb_lost) + state <= s_idle; + captured <= '0'; + byte_response(mrsp_arb_lost); + end if; + end case; + end if; + -- 'Byte Writing' state -------------------------- + end case; + end if; + end if; + end process main_fsm_proc; + ------------------------------------------------------------------------------ + +end architecture rtl; +--============================================================================== +

trunk/src/mbyte.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/iicmb_pkg.vhd =================================================================== --- trunk/src/iicmb_pkg.vhd (nonexistent) +++ trunk/src/iicmb_pkg.vhd (revision 2) @@ -0,0 +1,150 @@ + +--============================================================================== +-- | +-- Project: IIC Multiple Bus Controller (IICMB) | +-- | +-- Module: Main package. | +-- Version: | +-- 1.0, April 29, 2016 | +-- | +-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | +-- | +--============================================================================== +--============================================================================== +-- Copyright (c) 2016, Sergey Shuvalkin | +-- All rights reserved. | +-- | +-- Redistribution and use in source and binary forms, with or without | +-- modification, are permitted provided that the following conditions are met: | +-- | +-- 1. Redistributions of source code must retain the above copyright notice, | +-- this list of conditions and the following disclaimer. | +-- 2. Redistributions in binary form must reproduce the above copyright | +-- notice, this list of conditions and the following disclaimer in the | +-- documentation and/or other materials provided with the distribution. | +-- | +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | +-- POSSIBILITY OF SUCH DAMAGE. | +--============================================================================== + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +--============================================================================== +package iicmb_pkg is + + ------------------------------------------------------------------------------ + -- Byte level master mode commands' codes: + ------------------------------------------------------------------------------ + -- Start --> Done | Arbitration Lost + -- Byte Write --> Done | Write Not Acknowledged | Arbitration Lost | Error + -- Byte Read --> Byte Received | Error + -- Byte Read with Not-Acknowledge --> Byte Received | Arbitration Lost | Error + -- Stop --> Done + -- Set Bus --> Done | Error + -- Wait --> Done | Error + constant mcmd_wait : std_logic_vector(2 downto 0) := "000"; + constant mcmd_write : std_logic_vector(2 downto 0) := "001"; + constant mcmd_read_ack : std_logic_vector(2 downto 0) := "010"; + constant mcmd_read_nak : std_logic_vector(2 downto 0) := "011"; + constant mcmd_start : std_logic_vector(2 downto 0) := "100"; + constant mcmd_stop : std_logic_vector(2 downto 0) := "101"; + constant mcmd_set_bus : std_logic_vector(2 downto 0) := "110"; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + -- Byte level master mode responses' codes: + ------------------------------------------------------------------------------ + -- Done + -- Byte received + -- Write Not Acknowledged + -- Arbitration lost + -- Error + constant mrsp_done : std_logic_vector(2 downto 0) := "000"; + constant mrsp_nak : std_logic_vector(2 downto 0) := "001"; + constant mrsp_arb_lost : std_logic_vector(2 downto 0) := "010"; + constant mrsp_error : std_logic_vector(2 downto 0) := "011"; + constant mrsp_byte : std_logic_vector(2 downto 0) := "100"; + ------------------------------------------------------------------------------ + + + ------------------------------------------------------------------------------ + -- Sequencer related stuff --------------------------------------------------- + type seq_cmd_id is (seq_wait, seq_set_bus, seq_write_byte); + type seq_cmd_type is record + id : seq_cmd_id; + saddr : std_logic_vector(6 downto 0); + daddr : std_logic_vector(7 downto 0); + data : std_logic_vector(7 downto 0); + end record; + constant c_seq_cmd_default : seq_cmd_type := (id => seq_wait, others => (others => '0')); + type seq_cmd_type_array is array (natural range <>) of seq_cmd_type; + constant c_empty_array : seq_cmd_type_array(0 to 0) := (others => c_seq_cmd_default); -- not really empty + + function scmd_wait(a : integer range 0 to 255) return seq_cmd_type; + function scmd_set_bus(a : integer range 0 to 15) return seq_cmd_type; + function scmd_write_byte(sa : std_logic_vector(6 downto 0); + da : std_logic_vector(7 downto 0); + d : std_logic_vector(7 downto 0)) return seq_cmd_type; + -- End of sequencer related stuff -------------------------------------------- + ------------------------------------------------------------------------------ + +end package iicmb_pkg; +--============================================================================== + +--============================================================================== +package body iicmb_pkg is + + ------------------------------------------------------------------------------ + function scmd_wait(a : integer range 0 to 255) return seq_cmd_type is + variable ret : seq_cmd_type; + begin + ret.id := seq_wait; + ret.saddr := (others => '0'); + ret.daddr := (others => '0'); + ret.data := std_logic_vector(to_unsigned(a, 8)); + return ret; + end function scmd_wait; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + function scmd_set_bus(a : integer range 0 to 15) return seq_cmd_type is + variable ret : seq_cmd_type; + begin + ret.id := seq_set_bus; + ret.saddr := (others => '0'); + ret.daddr := (others => '0'); + ret.data := std_logic_vector(to_unsigned(a, 8)); + return ret; + end function scmd_set_bus; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + function scmd_write_byte(sa : std_logic_vector(6 downto 0); + da : std_logic_vector(7 downto 0); + d : std_logic_vector(7 downto 0)) return seq_cmd_type is + variable ret : seq_cmd_type; + begin + ret.id := seq_write_byte; + ret.saddr := sa; + ret.daddr := da; + ret.data := d; + return ret; + end function scmd_write_byte; + ------------------------------------------------------------------------------ + +end package body iicmb_pkg; +--============================================================================== +

trunk/src/iicmb_pkg.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/filter.vhd =================================================================== --- trunk/src/filter.vhd (nonexistent) +++ trunk/src/filter.vhd (revision 2) @@ -0,0 +1,109 @@ + +--============================================================================== +-- | +-- Project: IIC Multiple Bus Controller (IICMB) | +-- | +-- Module: Digital filter with hysteresis. | +-- Version: | +-- 1.0, April 29, 2016 | +-- | +-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | +-- | +--============================================================================== +--============================================================================== +-- Copyright (c) 2016, Sergey Shuvalkin | +-- All rights reserved. | +-- | +-- Redistribution and use in source and binary forms, with or without | +-- modification, are permitted provided that the following conditions are met: | +-- | +-- 1. Redistributions of source code must retain the above copyright notice, | +-- this list of conditions and the following disclaimer. | +-- 2. Redistributions in binary form must reproduce the above copyright | +-- notice, this list of conditions and the following disclaimer in the | +-- documentation and/or other materials provided with the distribution. | +-- | +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | +-- POSSIBILITY OF SUCH DAMAGE. | +--============================================================================== + + +library ieee; +use ieee.std_logic_1164.all; + + +--============================================================================== +entity filter is + generic + ( + g_cycles : positive := 10 -- Number of levels to receive before toggling output + ); + port + ( + ------------------------------------- + clk : in std_logic; -- Clock + s_rst : in std_logic; -- Synchronous reset + ------------------------------------- + ------------------------------------- + sig_in : in std_logic; -- Input signal + sig_out : out std_logic -- Output (filtered) signal + ------------------------------------- + ); +end entity filter; +--============================================================================== + +--============================================================================== +architecture rtl of filter is + + signal sig_out_y : std_logic := '1'; + signal cnt : integer range 0 to g_cycles := g_cycles; + +begin + + ------------------------------------------------------------------------------ + sig_out_y_proc: + process(clk) + begin + if rising_edge(clk) then + if (s_rst = '1') then + sig_out_y <= '1'; + cnt <= g_cycles; + else + if (sig_in = '1') then + if (cnt /= g_cycles) then + cnt <= cnt + 1; + end if; + else + if (cnt /= 0) then + cnt <= cnt - 1; + end if; + end if; + + if (sig_out_y = '1') then + if (sig_in = '0')and(cnt = 1) then + sig_out_y <= '0'; + end if; + else + if (sig_in = '1')and(cnt = (g_cycles - 1)) then + sig_out_y <= '1'; + end if; + end if; + end if; + end if; + end process sig_out_y_proc; + ------------------------------------------------------------------------------ + + sig_out <= sig_out_y; + +end rtl; +--============================================================================== +

trunk/src/filter.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/iicmb_m_av.vhd =================================================================== --- trunk/src/iicmb_m_av.vhd (nonexistent) +++ trunk/src/iicmb_m_av.vhd (revision 2) @@ -0,0 +1,313 @@ + +--============================================================================== +-- | +-- Project: IIC Multiple Bus Controller (IICMB) | +-- | +-- Module: Top level of IICMB controller with Avalon-MM interface. | +-- Version: | +-- 1.0, April 29, 2016 | +-- | +-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | +-- | +--============================================================================== +--============================================================================== +-- Copyright (c) 2016, Sergey Shuvalkin | +-- All rights reserved. | +-- | +-- Redistribution and use in source and binary forms, with or without | +-- modification, are permitted provided that the following conditions are met: | +-- | +-- 1. Redistributions of source code must retain the above copyright notice, | +-- this list of conditions and the following disclaimer. | +-- 2. Redistributions in binary form must reproduce the above copyright | +-- notice, this list of conditions and the following disclaimer in the | +-- documentation and/or other materials provided with the distribution. | +-- | +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | +-- POSSIBILITY OF SUCH DAMAGE. | +--============================================================================== + + +library ieee; +use ieee.std_logic_1164.all; + + +--============================================================================== +entity iicmb_m_av is + generic + ( + ------------------------------------ + g_bus_num : positive range 1 to 16 := 1; -- Number of separate I2C buses + g_f_clk : real := 100000.0; -- Frequency of system clock 'clk' (in kHz) + g_f_scl_0 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #0 (in kHz) + g_f_scl_1 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #1 (in kHz) + g_f_scl_2 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #2 (in kHz) + g_f_scl_3 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #3 (in kHz) + g_f_scl_4 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #4 (in kHz) + g_f_scl_5 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #5 (in kHz) + g_f_scl_6 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #6 (in kHz) + g_f_scl_7 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #7 (in kHz) + g_f_scl_8 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #8 (in kHz) + g_f_scl_9 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #9 (in kHz) + g_f_scl_a : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #10 (in kHz) + g_f_scl_b : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #11 (in kHz) + g_f_scl_c : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #12 (in kHz) + g_f_scl_d : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #13 (in kHz) + g_f_scl_e : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #14 (in kHz) + g_f_scl_f : real := 100.0 -- Frequency of 'SCL' clock of I2C bus #15 (in kHz) + ------------------------------------ + ); + port + ( + ------------------------------------ + -- Avalon-MM signals: + clk : in std_logic; -- Clock + s_rst : in std_logic; -- Synchronous reset (active high) + ------------- + waitrequest : out std_logic; + readdata : out std_logic_vector(31 downto 0); + readdatavalid : out std_logic; + writedata : in std_logic_vector(31 downto 0); + write : in std_logic; + read : in std_logic; + byteenable : in std_logic_vector( 3 downto 0); + ------------------------------------ + ------------------------------------ + -- Interrupt request: + irq : out std_logic; -- Interrupt request + ------------------------------------ + ------------------------------------ + -- I2C interfaces: + scl_i : in std_logic_vector(0 to g_bus_num - 1); -- I2C Clock inputs + sda_i : in std_logic_vector(0 to g_bus_num - 1); -- I2C Data inputs + scl_o : out std_logic_vector(0 to g_bus_num - 1); -- I2C Clock outputs + sda_o : out std_logic_vector(0 to g_bus_num - 1) -- I2C Data outputs + ------------------------------------ + ); +end entity iicmb_m_av; +--============================================================================== + +--============================================================================== +architecture str of iicmb_m_av is + + ------------------------------------------------------------------------------ + component avalon_mm is + port + ( + clk : in std_logic; + s_rst : in std_logic; + waitrequest : out std_logic; + readdata : out std_logic_vector(31 downto 0); + readdatavalid : out std_logic; + writedata : in std_logic_vector(31 downto 0); + write : in std_logic; + read : in std_logic; + byteenable : in std_logic_vector( 3 downto 0); + wr : out std_logic_vector( 3 downto 0); + rd : out std_logic_vector( 3 downto 0); + idata : out std_logic_vector(31 downto 0); + odata : in std_logic_vector(31 downto 0) + ); + end component avalon_mm; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + component regblock is + port + ( + clk : in std_logic; + s_rst : in std_logic; + wr : in std_logic_vector( 3 downto 0); + rd : in std_logic_vector( 3 downto 0); + idata : in std_logic_vector(31 downto 0); + odata : out std_logic_vector(31 downto 0); + irq : out std_logic; + busy : in std_logic; + captured : in std_logic; + bus_id : in std_logic_vector( 3 downto 0); + bit_state : in std_logic_vector( 3 downto 0); + byte_state : in std_logic_vector( 3 downto 0); + disable : out std_logic; + mcmd_wr : out std_logic; + mcmd_id : out std_logic_vector( 2 downto 0); + mcmd_data : out std_logic_vector( 7 downto 0); + mrsp_wr : in std_logic; + mrsp_id : in std_logic_vector( 2 downto 0); + mrsp_data : in std_logic_vector( 7 downto 0) + ); + end component regblock; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + component iicmb_m is + generic + ( + g_bus_num : positive range 1 to 16 := 1; + g_f_clk : real := 100000.0; + g_f_scl_0 : real := 100.0; + g_f_scl_1 : real := 100.0; + g_f_scl_2 : real := 100.0; + g_f_scl_3 : real := 100.0; + g_f_scl_4 : real := 100.0; + g_f_scl_5 : real := 100.0; + g_f_scl_6 : real := 100.0; + g_f_scl_7 : real := 100.0; + g_f_scl_8 : real := 100.0; + g_f_scl_9 : real := 100.0; + g_f_scl_a : real := 100.0; + g_f_scl_b : real := 100.0; + g_f_scl_c : real := 100.0; + g_f_scl_d : real := 100.0; + g_f_scl_e : real := 100.0; + g_f_scl_f : real := 100.0 + ); + port + ( + clk : in std_logic; + s_rst : in std_logic; + busy : out std_logic; + captured : out std_logic; + bus_id : out std_logic_vector(3 downto 0); + bit_state : out std_logic_vector(3 downto 0); + byte_state : out std_logic_vector(3 downto 0); + mcmd_wr : in std_logic; + mcmd_id : in std_logic_vector(2 downto 0); + mcmd_data : in std_logic_vector(7 downto 0); + mrsp_wr : out std_logic; + mrsp_id : out std_logic_vector(2 downto 0); + mrsp_data : out std_logic_vector(7 downto 0); + scl_i : in std_logic_vector(0 to g_bus_num - 1); + sda_i : in std_logic_vector(0 to g_bus_num - 1); + scl_o : out std_logic_vector(0 to g_bus_num - 1); + sda_o : out std_logic_vector(0 to g_bus_num - 1) + ); + end component iicmb_m; + ------------------------------------------------------------------------------ + + signal wr : std_logic_vector( 3 downto 0); + signal rd : std_logic_vector( 3 downto 0); + signal idata : std_logic_vector(31 downto 0); + signal odata : std_logic_vector(31 downto 0); + + signal busy : std_logic; + signal captured : std_logic; + signal bus_id : std_logic_vector( 3 downto 0); + signal bit_state : std_logic_vector( 3 downto 0); + signal byte_state : std_logic_vector( 3 downto 0); + signal disable : std_logic; -- used as synchronous reset for 'iicmb_m' + + -- Signals of 'Generic Interface': + -- Command: + signal mcmd_wr : std_logic; + signal mcmd_id : std_logic_vector( 2 downto 0); + signal mcmd_data : std_logic_vector( 7 downto 0); + -- Response: + signal mrsp_wr : std_logic; + signal mrsp_id : std_logic_vector( 2 downto 0); + signal mrsp_data : std_logic_vector( 7 downto 0); + +begin + + ------------------------------------------------------------------------------ + avalon_mm_inst0 : avalon_mm + port map + ( + clk => clk, + s_rst => s_rst, + waitrequest => waitrequest, + readdata => readdata, + readdatavalid => readdatavalid, + writedata => writedata, + write => write, + read => read, + byteenable => byteenable, + wr => wr, + rd => rd, + idata => idata, + odata => odata + ); + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + regblock_inst9 : regblock + port map + ( + clk => clk, + s_rst => s_rst, + wr => wr, + rd => rd, + idata => idata, + odata => odata, + irq => irq, + busy => busy, + captured => captured, + bus_id => bus_id, + bit_state => bit_state, + byte_state => byte_state, + disable => disable, + mcmd_wr => mcmd_wr, + mcmd_id => mcmd_id, + mcmd_data => mcmd_data, + mrsp_wr => mrsp_wr, + mrsp_id => mrsp_id, + mrsp_data => mrsp_data + ); + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + iicmb_m_inst0 : iicmb_m + generic map + ( + g_bus_num => g_bus_num, + g_f_clk => g_f_clk, + g_f_scl_0 => g_f_scl_0, + g_f_scl_1 => g_f_scl_1, + g_f_scl_2 => g_f_scl_2, + g_f_scl_3 => g_f_scl_3, + g_f_scl_4 => g_f_scl_4, + g_f_scl_5 => g_f_scl_5, + g_f_scl_6 => g_f_scl_6, + g_f_scl_7 => g_f_scl_7, + g_f_scl_8 => g_f_scl_8, + g_f_scl_9 => g_f_scl_9, + g_f_scl_a => g_f_scl_a, + g_f_scl_b => g_f_scl_b, + g_f_scl_c => g_f_scl_c, + g_f_scl_d => g_f_scl_d, + g_f_scl_e => g_f_scl_e, + g_f_scl_f => g_f_scl_f + ) + port map + ( + clk => clk, + s_rst => disable, + busy => busy, + captured => captured, + bus_id => bus_id, + bit_state => bit_state, + byte_state => byte_state, + mcmd_wr => mcmd_wr, + mcmd_id => mcmd_id, + mcmd_data => mcmd_data, + mrsp_wr => mrsp_wr, + mrsp_id => mrsp_id, + mrsp_data => mrsp_data, + scl_i => scl_i, + sda_i => sda_i, + scl_o => scl_o, + sda_o => sda_o + ); + ------------------------------------------------------------------------------ + +end architecture str; +--============================================================================== +

trunk/src/iicmb_m_av.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/iicmb_m_wb.vhd =================================================================== --- trunk/src/iicmb_m_wb.vhd (nonexistent) +++ trunk/src/iicmb_m_wb.vhd (revision 2) @@ -0,0 +1,313 @@ + +--============================================================================== +-- | +-- Project: IIC Multiple Bus Controller (IICMB) | +-- | +-- Module: Top level of IICMB controller with Wishbone interface. | +-- Version: | +-- 1.0, April 29, 2016 | +-- | +-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | +-- | +--============================================================================== +--============================================================================== +-- Copyright (c) 2016, Sergey Shuvalkin | +-- All rights reserved. | +-- | +-- Redistribution and use in source and binary forms, with or without | +-- modification, are permitted provided that the following conditions are met: | +-- | +-- 1. Redistributions of source code must retain the above copyright notice, | +-- this list of conditions and the following disclaimer. | +-- 2. Redistributions in binary form must reproduce the above copyright | +-- notice, this list of conditions and the following disclaimer in the | +-- documentation and/or other materials provided with the distribution. | +-- | +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | +-- POSSIBILITY OF SUCH DAMAGE. | +--============================================================================== + + +library ieee; +use ieee.std_logic_1164.all; + + +--============================================================================== +entity iicmb_m_wb is + generic + ( + ------------------------------------ + g_bus_num : positive range 1 to 16 := 1; -- Number of separate I2C buses + g_f_clk : real := 100000.0; -- Frequency of system clock 'clk_i' (in kHz) + g_f_scl_0 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #0 (in kHz) + g_f_scl_1 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #1 (in kHz) + g_f_scl_2 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #2 (in kHz) + g_f_scl_3 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #3 (in kHz) + g_f_scl_4 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #4 (in kHz) + g_f_scl_5 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #5 (in kHz) + g_f_scl_6 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #6 (in kHz) + g_f_scl_7 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #7 (in kHz) + g_f_scl_8 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #8 (in kHz) + g_f_scl_9 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #9 (in kHz) + g_f_scl_a : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #10 (in kHz) + g_f_scl_b : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #11 (in kHz) + g_f_scl_c : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #12 (in kHz) + g_f_scl_d : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #13 (in kHz) + g_f_scl_e : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #14 (in kHz) + g_f_scl_f : real := 100.0 -- Frequency of 'SCL' clock of I2C bus #15 (in kHz) + ------------------------------------ + ); + port + ( + ------------------------------------ + -- Wishbone signals: + clk_i : in std_logic; -- Clock + rst_i : in std_logic; -- Synchronous reset (active high) + ------------- + cyc_i : in std_logic; -- + stb_i : in std_logic; -- + ack_o : out std_logic; -- + adr_i : in std_logic_vector(1 downto 0); -- Low bits of Wishbone address + we_i : in std_logic; -- + dat_i : in std_logic_vector(7 downto 0); -- Data input + dat_o : out std_logic_vector(7 downto 0); -- Data output + ------------------------------------ + ------------------------------------ + -- Interrupt request: + irq : out std_logic; -- Interrupt request + ------------------------------------ + ------------------------------------ + -- I2C interfaces: + scl_i : in std_logic_vector(0 to g_bus_num - 1); -- I2C Clock inputs + sda_i : in std_logic_vector(0 to g_bus_num - 1); -- I2C Data inputs + scl_o : out std_logic_vector(0 to g_bus_num - 1); -- I2C Clock outputs + sda_o : out std_logic_vector(0 to g_bus_num - 1) -- I2C Data outputs + ------------------------------------ + ); +end entity iicmb_m_wb; +--============================================================================== + +--============================================================================== +architecture str of iicmb_m_wb is + + ------------------------------------------------------------------------------ + component wishbone is + port + ( + clk_i : in std_logic; + rst_i : in std_logic; + cyc_i : in std_logic; + stb_i : in std_logic; + ack_o : out std_logic; + adr_i : in std_logic_vector( 1 downto 0); + we_i : in std_logic; + dat_i : in std_logic_vector( 7 downto 0); + dat_o : out std_logic_vector( 7 downto 0); + wr : out std_logic_vector( 3 downto 0); + rd : out std_logic_vector( 3 downto 0); + idata : out std_logic_vector(31 downto 0); + odata : in std_logic_vector(31 downto 0) + ); + end component wishbone; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + component regblock is + port + ( + clk : in std_logic; + s_rst : in std_logic; + wr : in std_logic_vector( 3 downto 0); + rd : in std_logic_vector( 3 downto 0); + idata : in std_logic_vector(31 downto 0); + odata : out std_logic_vector(31 downto 0); + irq : out std_logic; + busy : in std_logic; + captured : in std_logic; + bus_id : in std_logic_vector( 3 downto 0); + bit_state : in std_logic_vector( 3 downto 0); + byte_state : in std_logic_vector( 3 downto 0); + disable : out std_logic; + mcmd_wr : out std_logic; + mcmd_id : out std_logic_vector( 2 downto 0); + mcmd_data : out std_logic_vector( 7 downto 0); + mrsp_wr : in std_logic; + mrsp_id : in std_logic_vector( 2 downto 0); + mrsp_data : in std_logic_vector( 7 downto 0) + ); + end component regblock; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + component iicmb_m is + generic + ( + g_bus_num : positive range 1 to 16 := 1; + g_f_clk : real := 100000.0; + g_f_scl_0 : real := 100.0; + g_f_scl_1 : real := 100.0; + g_f_scl_2 : real := 100.0; + g_f_scl_3 : real := 100.0; + g_f_scl_4 : real := 100.0; + g_f_scl_5 : real := 100.0; + g_f_scl_6 : real := 100.0; + g_f_scl_7 : real := 100.0; + g_f_scl_8 : real := 100.0; + g_f_scl_9 : real := 100.0; + g_f_scl_a : real := 100.0; + g_f_scl_b : real := 100.0; + g_f_scl_c : real := 100.0; + g_f_scl_d : real := 100.0; + g_f_scl_e : real := 100.0; + g_f_scl_f : real := 100.0 + ); + port + ( + clk : in std_logic; + s_rst : in std_logic; + busy : out std_logic; + captured : out std_logic; + bus_id : out std_logic_vector(3 downto 0); + bit_state : out std_logic_vector(3 downto 0); + byte_state : out std_logic_vector(3 downto 0); + mcmd_wr : in std_logic; + mcmd_id : in std_logic_vector(2 downto 0); + mcmd_data : in std_logic_vector(7 downto 0); + mrsp_wr : out std_logic; + mrsp_id : out std_logic_vector(2 downto 0); + mrsp_data : out std_logic_vector(7 downto 0); + scl_i : in std_logic_vector(0 to g_bus_num - 1); + sda_i : in std_logic_vector(0 to g_bus_num - 1); + scl_o : out std_logic_vector(0 to g_bus_num - 1); + sda_o : out std_logic_vector(0 to g_bus_num - 1) + ); + end component iicmb_m; + ------------------------------------------------------------------------------ + + signal wr : std_logic_vector( 3 downto 0); + signal rd : std_logic_vector( 3 downto 0); + signal idata : std_logic_vector(31 downto 0); + signal odata : std_logic_vector(31 downto 0); + + signal busy : std_logic; + signal captured : std_logic; + signal bus_id : std_logic_vector( 3 downto 0); + signal bit_state : std_logic_vector( 3 downto 0); + signal byte_state : std_logic_vector( 3 downto 0); + signal disable : std_logic; -- used as synchronous reset for 'iicmb_m' + + -- Signals of 'Generic Interface': + -- Command: + signal mcmd_wr : std_logic; + signal mcmd_id : std_logic_vector( 2 downto 0); + signal mcmd_data : std_logic_vector( 7 downto 0); + -- Response: + signal mrsp_wr : std_logic; + signal mrsp_id : std_logic_vector( 2 downto 0); + signal mrsp_data : std_logic_vector( 7 downto 0); + +begin + + ------------------------------------------------------------------------------ + wishbone_inst0 : wishbone + port map + ( + clk_i => clk_i, + rst_i => rst_i, + cyc_i => cyc_i, + stb_i => stb_i, + ack_o => ack_o, + adr_i => adr_i, + we_i => we_i, + dat_i => dat_i, + dat_o => dat_o, + wr => wr, + rd => rd, + idata => idata, + odata => odata + ); + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + regblock_inst9 : regblock + port map + ( + clk => clk_i, + s_rst => rst_i, + wr => wr, + rd => rd, + idata => idata, + odata => odata, + irq => irq, + busy => busy, + captured => captured, + bus_id => bus_id, + bit_state => bit_state, + byte_state => byte_state, + disable => disable, + mcmd_wr => mcmd_wr, + mcmd_id => mcmd_id, + mcmd_data => mcmd_data, + mrsp_wr => mrsp_wr, + mrsp_id => mrsp_id, + mrsp_data => mrsp_data + ); + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + iicmb_m_inst0 : iicmb_m + generic map + ( + g_bus_num => g_bus_num, + g_f_clk => g_f_clk, + g_f_scl_0 => g_f_scl_0, + g_f_scl_1 => g_f_scl_1, + g_f_scl_2 => g_f_scl_2, + g_f_scl_3 => g_f_scl_3, + g_f_scl_4 => g_f_scl_4, + g_f_scl_5 => g_f_scl_5, + g_f_scl_6 => g_f_scl_6, + g_f_scl_7 => g_f_scl_7, + g_f_scl_8 => g_f_scl_8, + g_f_scl_9 => g_f_scl_9, + g_f_scl_a => g_f_scl_a, + g_f_scl_b => g_f_scl_b, + g_f_scl_c => g_f_scl_c, + g_f_scl_d => g_f_scl_d, + g_f_scl_e => g_f_scl_e, + g_f_scl_f => g_f_scl_f + ) + port map + ( + clk => clk_i, + s_rst => disable, + busy => busy, + captured => captured, + bus_id => bus_id, + bit_state => bit_state, + byte_state => byte_state, + mcmd_wr => mcmd_wr, + mcmd_id => mcmd_id, + mcmd_data => mcmd_data, + mrsp_wr => mrsp_wr, + mrsp_id => mrsp_id, + mrsp_data => mrsp_data, + scl_i => scl_i, + sda_i => sda_i, + scl_o => scl_o, + sda_o => sda_o + ); + ------------------------------------------------------------------------------ + +end architecture str; +--============================================================================== +

trunk/src/iicmb_m_wb.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/regblock.vhd =================================================================== --- trunk/src/regblock.vhd (nonexistent) +++ trunk/src/regblock.vhd (revision 2) @@ -0,0 +1,312 @@ + +--============================================================================== +-- | +-- Project: IIC Multiple Bus Controller (IICMB) | +-- | +-- Module: Register block. | +-- Version: | +-- 1.0, April 29, 2016 | +-- | +-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | +-- | +--============================================================================== +--============================================================================== +-- Copyright (c) 2016, Sergey Shuvalkin | +-- All rights reserved. | +-- | +-- Redistribution and use in source and binary forms, with or without | +-- modification, are permitted provided that the following conditions are met: | +-- | +-- 1. Redistributions of source code must retain the above copyright notice, | +-- this list of conditions and the following disclaimer. | +-- 2. Redistributions in binary form must reproduce the above copyright | +-- notice, this list of conditions and the following disclaimer in the | +-- documentation and/or other materials provided with the distribution. | +-- | +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | +-- POSSIBILITY OF SUCH DAMAGE. | +--============================================================================== + + +-------------------------------------------------------------------------------- +-- Implemented registers: +-- +-- Control/Status register: +-- 7 6 5 4 3 2 1 0 +-- +-----+-----+-----+-----+-----+-----+-----+-----+ +-- 0x00 | E | IE | BB | BC | Bus ID | +-- +-----+-----+-----+-----+-----+-----+-----+-----+ +-- R/W R/W RO RO RO +-- '0' '0' '0' '0' "0000" +-- +-- E - Enable +-- IE - Interrupt Enable +-- BB - Bus Busy +-- RC - Bus Captured +-- +-- +-- Data register: +-- 7 6 5 4 3 2 1 0 +-- +-----+-----+-----+-----+-----+-----+-----+-----+ +-- 0x01 | Data | +-- +-----+-----+-----+-----+-----+-----+-----+-----+ +-- R/W +-- "00000000" +-- +-- Command register: +-- 7 6 5 4 3 2 1 0 +-- +-----+-----+-----+-----+-----+-----+-----+-----+ +-- 0x02 | DON | NAK | AL | ERR | '0' | Command Code | +-- +-----+-----+-----+-----+-----+-----+-----+-----+ +-- RO RO RO RO R/W +-- '1' '0' '0' '0' "000" +-- +-- DON - Command Done +-- NAK - Data write was not acknowledged +-- AL - Arbitration Lost +-- ERR - Error +-- +-- +-- Status register of FSM states: +-- 7 6 5 4 3 2 1 0 +-- +-----+-----+-----+-----+-----+-----+-----+-----+ +-- 0x03 | Byte State | Bit State | +-- +-----+-----+-----+-----+-----+-----+-----+-----+ +-- RO RO +-- "0000" "0000" +-------------------------------------------------------------------------------- + + +library ieee; +use ieee.std_logic_1164.all; + +use work.iicmb_pkg.all; + + +--============================================================================== +entity regblock is + port + ( + ------------------------------------ + clk : in std_logic; -- Clock input + s_rst : in std_logic; -- Synchronous reset (active high) + ------------------------------------ + ------------------------------------ + wr : in std_logic_vector( 3 downto 0); -- Write (active high) + rd : in std_logic_vector( 3 downto 0); -- Read (active high) + idata : in std_logic_vector(31 downto 0); -- Data from System Bus + odata : out std_logic_vector(31 downto 0); -- Data to System Bus + ------------------------------------ + ------------------------------------ + irq : out std_logic; -- Interrupt request + ------------------------------------ + + ------------------------------------ + busy : in std_logic; -- 'Bus is busy' indication (busy = high) + captured : in std_logic; -- 'Bus is captured' indication (captured = high) + bus_id : in std_logic_vector( 3 downto 0); -- ID of selected I2C bus + bit_state : in std_logic_vector( 3 downto 0); -- State of bit level FSM + byte_state : in std_logic_vector( 3 downto 0); -- State of byte level FSM + disable : out std_logic; -- Disable controller (used as synchronous reset) + ------------------------------------ + ------------------------------------ + -- 'Generic Interface' signals: + -- Byte command interface: + mcmd_wr : out std_logic; -- Byte command write (active high) + mcmd_id : out std_logic_vector( 2 downto 0); -- Byte command ID + mcmd_data : out std_logic_vector( 7 downto 0); -- Byte command data + ------------- + -- Byte response interface: + mrsp_wr : in std_logic; -- Byte response write (active high) + mrsp_id : in std_logic_vector( 2 downto 0); -- Byte response ID + mrsp_data : in std_logic_vector( 7 downto 0) -- Byte response data + ------------------------------------ + ); +end entity regblock; +--============================================================================== + +--============================================================================== +architecture rtl of regblock is + + signal irq_y : std_logic := '0'; + signal mcmd_wr_y : std_logic := '0'; + signal mcmd_id_y : std_logic_vector(2 downto 0) := mcmd_set_bus; + signal e_reg : std_logic := '0'; + signal ie_reg : std_logic := '0'; + signal tx_data_reg : std_logic_vector(7 downto 0) := "00000000"; + signal rx_data_reg : std_logic_vector(7 downto 0) := "00000000"; + signal don_reg : std_logic := '1'; + signal nak_reg : std_logic := '0'; + signal al_reg : std_logic := '0'; + signal err_reg : std_logic := '0'; + signal cmd_code_reg : std_logic_vector(2 downto 0) := "000"; + signal command_completed : std_logic; + +begin + + disable <= not(e_reg); + + odata(31 downto 28) <= byte_state; + odata(27 downto 24) <= bit_state; + -- + odata(23) <= don_reg; + odata(22) <= nak_reg; + odata(21) <= al_reg; + odata(20) <= err_reg; + odata(19) <= '0'; + odata(18 downto 16) <= cmd_code_reg; + -- + odata(15 downto 8) <= rx_data_reg; + -- + odata( 7) <= e_reg; + odata( 6) <= ie_reg; + odata( 5) <= busy; + odata( 4) <= captured; + odata( 3 downto 0) <= bus_id; + + ------------------------------------------------------------------------------ + process(clk) + begin + if rising_edge(clk) then + if (s_rst = '1') then + e_reg <= '0'; + ie_reg <= '0'; + else + if (wr(0) = '1') then + e_reg <= idata(7); + ie_reg <= idata(6); + end if; + end if; + end if; + end process; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + process(clk) + begin + if rising_edge(clk) then + if (s_rst = '1') then + tx_data_reg <= "00000000"; + else + if (wr(1) = '1') then + tx_data_reg <= idata(15 downto 8); + end if; + end if; + end if; + end process; + ------------------------------------------------------------------------------ + + command_completed <= don_reg or nak_reg or al_reg or err_reg; + + ------------------------------------------------------------------------------ + process(clk) + begin + if rising_edge(clk) then + if (s_rst = '1')or(e_reg = '0') then + cmd_code_reg <= "000"; + else + if (wr(2) = '1') then + if (command_completed = '1') then + cmd_code_reg <= idata(18 downto 16); + end if; + end if; + end if; + end if; + end process; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + -- Command status registers + process(clk) + begin + if rising_edge(clk) then + if (s_rst = '1')or(e_reg = '0') then + don_reg <= '1'; + nak_reg <= '0'; + al_reg <= '0'; + err_reg <= '0'; + rx_data_reg <= "00000000"; + else + if (wr(2) = '1') then + don_reg <= '0'; + nak_reg <= '0'; + al_reg <= '0'; + err_reg <= '0'; + end if; + if (mrsp_wr = '1') then + case (mrsp_id) is + when mrsp_done => don_reg <= '1'; + when mrsp_byte => + don_reg <= '1'; + rx_data_reg <= mrsp_data; + when mrsp_nak => nak_reg <= '1'; + when mrsp_arb_lost => al_reg <= '1'; + when others => err_reg <= '1'; + end case; + end if; + end if; + end if; + end process; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + -- Interrupt request + process(clk) + begin + if rising_edge(clk) then + if (s_rst = '1')or(e_reg = '0') then + irq_y <= '0'; + else + if (rd(2) = '1') then + irq_y <= '0'; + end if; + if (mrsp_wr = '1') then + irq_y <= '1'; + end if; + if (ie_reg = '0') then + irq_y <= '0'; + end if; + end if; + end if; + end process; + ------------------------------------------------------------------------------ + + irq <= irq_y; + + ------------------------------------------------------------------------------ + -- Generating a byte command + mcmd_proc: + process(clk) + begin + if rising_edge(clk) then + if (s_rst = '1')or(e_reg = '0') then + mcmd_wr_y <= '0'; + mcmd_id_y <= mcmd_wait; + else + if (wr(2) = '1')and(command_completed = '1') then + mcmd_wr_y <= '1'; + mcmd_id_y <= idata(18 downto 16); + else + mcmd_wr_y <= '0'; + end if; + end if; + end if; + end process mcmd_proc; + ------------------------------------------------------------------------------ + + mcmd_wr <= mcmd_wr_y; + mcmd_id <= mcmd_id_y; + mcmd_data <= tx_data_reg; + +end architecture rtl; +--============================================================================== +

trunk/src/regblock.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/bus_state.vhd =================================================================== --- trunk/src/bus_state.vhd (nonexistent) +++ trunk/src/bus_state.vhd (revision 2) @@ -0,0 +1,167 @@ + +--============================================================================== +-- | +-- Project: IIC Multiple Bus Controller (IICMB) | +-- | +-- Module: I2C Bus busy state monitoring. | +-- Version: | +-- 1.0, April 29, 2016 | +-- | +-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | +-- | +--============================================================================== +--============================================================================== +-- Copyright (c) 2016, Sergey Shuvalkin | +-- All rights reserved. | +-- | +-- Redistribution and use in source and binary forms, with or without | +-- modification, are permitted provided that the following conditions are met: | +-- | +-- 1. Redistributions of source code must retain the above copyright notice, | +-- this list of conditions and the following disclaimer. | +-- 2. Redistributions in binary form must reproduce the above copyright | +-- notice, this list of conditions and the following disclaimer in the | +-- documentation and/or other materials provided with the distribution. | +-- | +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | +-- POSSIBILITY OF SUCH DAMAGE. | +--============================================================================== + + +library ieee; +use ieee.std_logic_1164.all; + + +--============================================================================== +entity bus_state is + generic + ( + g_f_clk : real := 100000.0; -- Frequency of 'clk' input (in kHz) + g_f_scl : real := 100.0 -- Frequency of 'scl' input (in kHz) + ); + port + ( + ------------------------------------ + clk : in std_logic; -- Clock + s_rst : in std_logic; -- Synchronous reset (active high) + ------------------------------------ + ------------------------------------ + busy : out std_logic; -- Bus busy indication (busy = high) + scl_d : out std_logic; -- Delayed I2C Clock signal + ------------------------------------ + ------------------------------------ + -- Filtered I2C bus signals: + scl : in std_logic; -- I2C Clock input + sda : in std_logic -- I2C Data input + ------------------------------------ + ); +end entity bus_state; +--============================================================================== + +--============================================================================== +architecture rtl of bus_state is + + ------------------------------------------------------------------------------ + function get_t_buf(a : real) return real is + begin + if (a <= 100.0) then + return 4.7; + else + return 1.3; + end if; + end function get_t_buf; + ------------------------------------------------------------------------------ + + constant c_t_buf : real := get_t_buf(g_f_scl); -- in microseconds + constant c_t_buf_cnt : integer := integer((g_f_clk*(c_t_buf/1000.0)) + 0.4999); -- in 'clk' cycles + constant c_max_cnt : integer := c_t_buf_cnt; + + signal scl_d_y : std_logic := '1'; + signal scl_y : std_logic; + signal sda_d_y : std_logic := '1'; + signal sda_y : std_logic; + + signal sda_cnt : integer range 0 to c_max_cnt := 0; + + signal busy_y : std_logic := '0'; + + type state_type is (s_free, s_busy, s_guard); + signal state : state_type := s_free; + +begin + + scl_y <= to_x01(scl); + sda_y <= to_x01(sda); + + scl_d <= scl_d_y; + + ------------------------------------------------------------------------------ + -- Monitoring 'scl_i' and 'sda_i' inputs + process(clk) + begin + if rising_edge(clk) then + if (s_rst = '1') then + scl_d_y <= '1'; + sda_d_y <= '1'; + sda_cnt <= 0; + else + scl_d_y <= scl_y; + sda_d_y <= sda_y; + + if (sda_d_y /= sda_y) then + sda_cnt <= 1; + elsif (sda_cnt /= c_max_cnt) then + sda_cnt <= sda_cnt + 1; + end if; + end if; + end if; + end process; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + state_proc: + process(clk) + begin + if rising_edge(clk) then + if (s_rst = '1') then + state <= s_free; + busy_y <= '0'; + else + case state is + when s_free => + busy_y <= '0'; + if (scl_y = '1')and(sda_d_y = '1')and(sda_y = '0') then + state <= s_busy; + busy_y <= '1'; + end if; + when s_busy => + busy_y <= '1'; + if (scl_y = '1')and(sda_d_y = '0')and(sda_y = '1') then + state <= s_guard; + end if; + when s_guard => + busy_y <= '1'; + if (sda_d_y = '1')and(scl_d_y = '1')and(sda_cnt = c_t_buf_cnt) then + state <= s_free; + busy_y <= '0'; + end if; + end case; + end if; + end if; + end process state_proc; + ------------------------------------------------------------------------------ + + busy <= busy_y; + +end architecture rtl; +--============================================================================== +

trunk/src/bus_state.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/sequencer.vhd =================================================================== --- trunk/src/sequencer.vhd (nonexistent) +++ trunk/src/sequencer.vhd (revision 2) @@ -0,0 +1,213 @@ + +--============================================================================== +-- | +-- Project: IIC Multiple Bus Controller (IICMB) | +-- | +-- Module: Command sequencer for 'iicmb_m'. | +-- Version: | +-- 1.0, April 29, 2016 | +-- | +-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | +-- | +--============================================================================== +--============================================================================== +-- Copyright (c) 2016, Sergey Shuvalkin | +-- All rights reserved. | +-- | +-- Redistribution and use in source and binary forms, with or without | +-- modification, are permitted provided that the following conditions are met: | +-- | +-- 1. Redistributions of source code must retain the above copyright notice, | +-- this list of conditions and the following disclaimer. | +-- 2. Redistributions in binary form must reproduce the above copyright | +-- notice, this list of conditions and the following disclaimer in the | +-- documentation and/or other materials provided with the distribution. | +-- | +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | +-- POSSIBILITY OF SUCH DAMAGE. | +--============================================================================== + + +library ieee; +use ieee.std_logic_1164.all; + +use work.iicmb_pkg.all; + + +--============================================================================== +entity sequencer is + generic + ( + g_cmd : seq_cmd_type_array := c_empty_array -- Sequence of commands (supported: WAIT, SET_BUS and WRITE_BYTE) + ); + port + ( + ------------------------------------ + clk : in std_logic; -- Clock input + s_rst : in std_logic; -- Synchronous reset (active high) + ------------------------------------ + ------------------------------------ + cs_start : in std_logic; -- Start executing command sequence + cs_busy : out std_logic; -- Command sequence is being executed + cs_status : out std_logic_vector(2 downto 0); -- Execution status + ------------------------------------ + ------------------------------------ + -- Status: + busy : in std_logic; -- Bus busy status + captured : in std_logic; -- Bus captured status + bus_id : in std_logic_vector(3 downto 0); -- ID of selected I2C bus + bit_state : in std_logic_vector(3 downto 0); -- State of bit level FSM + byte_state : in std_logic_vector(3 downto 0); -- State of byte level FSM + ------------------------------------ + ------------------------------------ + -- 'Generic interface' signals: + mcmd_wr : out std_logic; -- Byte command write (active high) + mcmd_id : out std_logic_vector(2 downto 0); -- Byte command ID + mcmd_data : out std_logic_vector(7 downto 0); -- Command data + -- + mrsp_wr : in std_logic; -- Byte response write (active high) + mrsp_id : in std_logic_vector(2 downto 0); -- Byte response ID + mrsp_data : in std_logic_vector(7 downto 0) -- Response data + ------------------------------------ + ); +end entity sequencer; +--============================================================================== + +--============================================================================== +architecture rtl of sequencer is + + type cmd_type_array is array (natural range <>) of std_logic_vector(10 downto 0); + + ------------------------------------------------------------------------------ + function get_cmd_seq_length(a : seq_cmd_type_array) return natural is + variable v_ret : natural := 0; + begin + for i in a'range loop + case a(i).id is + when seq_wait => v_ret := v_ret + 1; + when seq_set_bus => v_ret := v_ret + 1; + when seq_write_byte => v_ret := v_ret + 5; + end case; + end loop; + return v_ret; + end function get_cmd_seq_length; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + function get_cmd_seq(a : seq_cmd_type_array) return cmd_type_array is + variable v_ret : cmd_type_array(0 to (get_cmd_seq_length(a) - 1)); + variable j : integer; + begin + j := 0; + for i in a'range loop + case a(i).id is + when seq_wait => + v_ret(j) := mcmd_wait & a(i).data; + j := j + 1; + when seq_set_bus => + v_ret(j) := mcmd_set_bus & a(i).data; + j := j + 1; + when seq_write_byte => + v_ret(j + 0) := mcmd_start & x"00"; + v_ret(j + 1) := mcmd_write & a(i).saddr & "0"; + v_ret(j + 2) := mcmd_write & a(i).daddr; + v_ret(j + 3) := mcmd_write & a(i).data; + v_ret(j + 4) := mcmd_stop & x"00"; + j := j + 5; + end case; + end loop; + return v_ret; + end function get_cmd_seq; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + -- Sequence of commands to execute: + constant cmd_seq : cmd_type_array := get_cmd_seq(g_cmd); + ------------------------------------------------------------------------------ + + type state_type is (s_idle, s_active); + signal state : state_type := s_idle; + signal cmd_cnt : integer range 0 to cmd_seq'length := 0; + +begin + + ------------------------------------------------------------------------------ + state_proc: + process(clk) + begin + if rising_edge(clk) then + if (s_rst = '1') then + state <= s_idle; + cmd_cnt <= 0; + cs_busy <= '0'; + cs_status <= mrsp_done; + mcmd_wr <= '0'; + mcmd_id <= "000"; + mcmd_data <= "00000000"; + else + -- Defaults: + mcmd_wr <= '0'; + + -- FSM: + case state is + -------------- 's_idle' state ------------------------ + when s_idle => + cs_busy <= '0'; + if (cs_start = '1') then + if (cmd_cnt = cmd_seq'length) then + cs_status <= mrsp_done; + cmd_cnt <= 0; + else + state <= s_active; + cmd_cnt <= cmd_cnt + 1; + cs_busy <= '1'; + mcmd_wr <= '1'; + mcmd_id <= cmd_seq(cmd_cnt)(10 downto 8); + mcmd_data <= cmd_seq(cmd_cnt)( 7 downto 0); + end if; + end if; + -------------- 's_idle' state ------------------------ + + -------------- 's_active' state ---------------------- + when s_active => + cs_busy <= '1'; + if (mrsp_wr = '1') then + case mrsp_id is + when mrsp_nak | mrsp_arb_lost | mrsp_error => + state <= s_idle; + cmd_cnt <= 0; + cs_busy <= '0'; + cs_status <= mrsp_id; + when others => + if (cmd_cnt = cmd_seq'length) then + state <= s_idle; + cmd_cnt <= 0; + cs_busy <= '0'; + cs_status <= mrsp_done; + else + cmd_cnt <= cmd_cnt + 1; + mcmd_wr <= '1'; + mcmd_id <= cmd_seq(cmd_cnt)(10 downto 8); + mcmd_data <= cmd_seq(cmd_cnt)( 7 downto 0); + end if; + end case; + end if; + -------------- 's_active' state ---------------------- + end case; + end if; + end if; + end process state_proc; + ------------------------------------------------------------------------------ + +end architecture rtl; +--============================================================================== +

trunk/src/sequencer.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/mbit.vhd =================================================================== --- trunk/src/mbit.vhd (nonexistent) +++ trunk/src/mbit.vhd (revision 2) @@ -0,0 +1,534 @@ + +--============================================================================== +-- | +-- Project: IIC Multiple Bus Controller (IICMB) | +-- | +-- Module: Bit layer FSM (master mode). | +-- Version: | +-- 1.0, April 29, 2016 | +-- | +-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | +-- | +--============================================================================== +--============================================================================== +-- Copyright (c) 2016, Sergey Shuvalkin | +-- All rights reserved. | +-- | +-- Redistribution and use in source and binary forms, with or without | +-- modification, are permitted provided that the following conditions are met: | +-- | +-- 1. Redistributions of source code must retain the above copyright notice, | +-- this list of conditions and the following disclaimer. | +-- 2. Redistributions in binary form must reproduce the above copyright | +-- notice, this list of conditions and the following disclaimer in the | +-- documentation and/or other materials provided with the distribution. | +-- | +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | +-- POSSIBILITY OF SUCH DAMAGE. | +--============================================================================== + + +library ieee; +use ieee.std_logic_1164.all; + +use work.iicmb_int_pkg.all; + + +--============================================================================== +entity mbit is + generic + ( + g_bus_num : positive range 1 to 16 := 1; -- Number of connected I2C buses + g_f_clk : real := 100000.0; -- Frequency of 'clk' clock (in kHz) + g_f_scl_0 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #0 (in kHz) + g_f_scl_1 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #1 (in kHz) + g_f_scl_2 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #2 (in kHz) + g_f_scl_3 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #3 (in kHz) + g_f_scl_4 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #4 (in kHz) + g_f_scl_5 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #5 (in kHz) + g_f_scl_6 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #6 (in kHz) + g_f_scl_7 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #7 (in kHz) + g_f_scl_8 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #8 (in kHz) + g_f_scl_9 : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #9 (in kHz) + g_f_scl_a : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #10 (in kHz) + g_f_scl_b : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #11 (in kHz) + g_f_scl_c : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #12 (in kHz) + g_f_scl_d : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #13 (in kHz) + g_f_scl_e : real := 100.0; -- Frequency of 'SCL' clock of I2C bus #14 (in kHz) + g_f_scl_f : real := 100.0 -- Frequency of 'SCL' clock of I2C bus #15 (in kHz) + ); + port + ( + ------------------------------------ + clk : in std_logic; -- Clock + s_rst : in std_logic; -- Synchronous reset (active high) + ------------------------------------ + ------------------------------------ + fsm_state : out std_logic_vector(3 downto 0); -- FSM state + bus_id : in natural range 0 to g_bus_num - 1; -- I2C Bus ID + ------------------------------------ + ------------------------------------ + mbc_wr : in std_logic; -- Bit command write indication (active high) + mbc : in mbc_type; -- Bit command + ------------------------------------ + ------------------------------------ + mbr_wr : out std_logic := '0'; -- Bit command response write indication (active high) + mbr : out mbr_type := mbr_done; -- Bit command response + ------------------------------------ + ------------------------------------ + scl_i : in std_logic; -- I2C Clock input + sda_i : in std_logic; -- I2C Data input + scl_i_d : in std_logic; -- I2C Clock input delayed for 1 clock cycle + scl_o : out std_logic := '1'; -- I2C Clock output + sda_o : out std_logic := '1' -- I2C Data output + ------------------------------------ + ); +end entity mbit; +--============================================================================== + +--============================================================================== +architecture rtl of mbit is + + type real_array is array (natural range <>) of real; + constant c_f_scl : real_array(0 to 15) := (g_f_scl_0, g_f_scl_1, g_f_scl_2, g_f_scl_3, + g_f_scl_4, g_f_scl_5, g_f_scl_6, g_f_scl_7, + g_f_scl_8, g_f_scl_9, g_f_scl_a, g_f_scl_b, + g_f_scl_c, g_f_scl_d, g_f_scl_e, g_f_scl_f); + + type timing_parameters_type is record + max_cnt : integer; -- Minimum number of 'clk' cycles in single 'SCL' cycle + fe_cnt : integer; -- Time for falling edge of 'SCL' + t_hd_sta_cnt : integer; -- Hold time (repeated) Start condition + t_vd_dat_cnt : integer; -- Data valid time + t_high_cnt : integer; -- 'SCL' high time + t_su_sto_cnt : integer; -- Set-up time for Stop condition + t_su_sta_cnt : integer; -- Set-up time for a repeated Start condition + t_su_dat_cnt : integer; -- Data set-up time + end record; + + type timing_parameters_type_array is array (0 to g_bus_num - 1) of timing_parameters_type; + + ------------------------------------------------------------------------------ + function get_tp(a_f_clk : real; a_f_scl : real_array(0 to 15)) return timing_parameters_type_array is + variable ret : timing_parameters_type_array; + variable v_t_scl : integer; + variable v_t_high : integer; + variable v_t_low : integer; + variable v_t_vd_dat : integer; + begin + for i in ret'range loop + v_t_scl := integer((a_f_clk/a_f_scl(i)) + 0.4999); -- number of 'clk' periods in an 'SCL' period + if (a_f_scl(i) <= 100.0) then + v_t_high := integer(real(v_t_scl)*0.401); -- 'SCL' high time + v_t_low := integer(real(v_t_scl)*0.47); -- 'SCL' low time + else + v_t_high := integer(real(v_t_scl)*0.241); -- 'SCL' high time + v_t_low := integer(real(v_t_scl)*0.52); -- 'SCL' low time + end if; + v_t_vd_dat := integer((a_f_clk*(0.5/1000.0)) + 0.4999); + -- + ret(i).max_cnt := v_t_scl - 1; + ret(i).fe_cnt := v_t_low - v_t_vd_dat + v_t_high - 1; + ret(i).t_hd_sta_cnt := v_t_high - 1; + ret(i).t_vd_dat_cnt := v_t_vd_dat - 1; + ret(i).t_high_cnt := v_t_high - 1; + ret(i).t_su_sto_cnt := v_t_high - 1; + ret(i).t_su_sta_cnt := v_t_low - 1; + ret(i).t_su_dat_cnt := v_t_low - v_t_vd_dat - 1; + end loop; + return ret; + end function get_tp; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + function get_max_cnt(a : timing_parameters_type_array) return integer is + variable ret : integer := 0; + begin + for i in a'range loop + if (ret < a(i).max_cnt) then + ret := a(i).max_cnt; + end if; + end loop; + return ret; + end function get_max_cnt; + ------------------------------------------------------------------------------ + + constant c_tp : timing_parameters_type_array := get_tp(g_f_clk, c_f_scl); + constant c_max_cnt : integer := get_max_cnt(c_tp); + + type state_type is + ( + s_idle, -- Idle + -- + s_start_a, -- Start condition generating + s_start_b, -- Start condition generating + s_start_c, -- Start condition generating + -- + s_rw_a, -- Bit Read/Write + s_rw_b, -- Bit Read/Write + s_rw_c, -- Bit Read/Write + s_rw_d, -- Bit Read/Write + s_rw_e, -- Bit Read/Write + -- + s_stop_a, -- Stop condition generating + s_stop_b, -- Stop condition generating + s_stop_c, -- Stop condition generating + -- + s_rstart_a, -- Preparation for Repeated Start + s_rstart_b, -- Preparation for Repeated Start + s_rstart_c -- Preparation for Repeated Start + ); + + ------------------------------------------------------------------------------ + -- Conversion from 'state_type' to 'std_logic_vector(3 downto 0)' + function to_std_logic_vector(a : state_type) return std_logic_vector is + begin + case (a) is + when s_idle => return "0000"; + when s_start_a => return "0001"; + when s_start_b => return "0010"; + when s_start_c => return "0011"; + when s_rw_a => return "0100"; + when s_rw_b => return "0101"; + when s_rw_c => return "0110"; + when s_rw_d => return "0111"; + when s_rw_e => return "1000"; + when s_stop_a => return "1001"; + when s_stop_b => return "1010"; + when s_stop_c => return "1011"; + when s_rstart_a => return "1100"; + when s_rstart_b => return "1101"; + when s_rstart_c => return "1110"; + end case; + end function to_std_logic_vector; + ------------------------------------------------------------------------------ + + signal state : state_type := s_idle; -- FSM state + signal cnt : integer range 0 to c_max_cnt := 0; -- Counter of clock cycles + signal d_reg : std_logic := '0'; -- Output data bit register + signal r_reg : std_logic := '0'; -- Read operation indication + signal i_reg : std_logic := '0'; -- Input data bit register + + signal scl_cnt : integer range 0 to c_max_cnt := 0; -- Counter of cycles when scl is stable + + -- Timing parameters: + signal max_cnt : integer range 0 to c_max_cnt := c_tp(0).max_cnt; + signal fe_cnt : integer range 0 to c_max_cnt := c_tp(0).fe_cnt; + signal t_hd_sta_cnt : integer range 0 to c_max_cnt := c_tp(0).t_hd_sta_cnt; + signal t_vd_dat_cnt : integer range 0 to c_max_cnt := c_tp(0).t_vd_dat_cnt; + signal t_high_cnt : integer range 0 to c_max_cnt := c_tp(0).t_high_cnt; + signal t_su_sto_cnt : integer range 0 to c_max_cnt := c_tp(0).t_su_sto_cnt; + signal t_su_sta_cnt : integer range 0 to c_max_cnt := c_tp(0).t_su_sta_cnt; + signal t_su_dat_cnt : integer range 0 to c_max_cnt := c_tp(0).t_su_dat_cnt; + +begin + + fsm_state <= to_std_logic_vector(state); + + ------------------------------------------------------------------------------ + -- Changing timing parameters: + tp_proc: + process(clk) + begin + if rising_edge(clk) then + if (s_rst = '1') then + max_cnt <= c_tp(0).max_cnt; + fe_cnt <= c_tp(0).fe_cnt; + t_hd_sta_cnt <= c_tp(0).t_hd_sta_cnt; + t_vd_dat_cnt <= c_tp(0).t_vd_dat_cnt; + t_high_cnt <= c_tp(0).t_high_cnt; + t_su_sto_cnt <= c_tp(0).t_su_sto_cnt; + t_su_sta_cnt <= c_tp(0).t_su_sta_cnt; + t_su_dat_cnt <= c_tp(0).t_su_dat_cnt; + else + max_cnt <= c_tp(bus_id).max_cnt; + fe_cnt <= c_tp(bus_id).fe_cnt; + t_hd_sta_cnt <= c_tp(bus_id).t_hd_sta_cnt; + t_vd_dat_cnt <= c_tp(bus_id).t_vd_dat_cnt; + t_high_cnt <= c_tp(bus_id).t_high_cnt; + t_su_sto_cnt <= c_tp(bus_id).t_su_sto_cnt; + t_su_sta_cnt <= c_tp(bus_id).t_su_sta_cnt; + t_su_dat_cnt <= c_tp(bus_id).t_su_dat_cnt; + end if; + end if; + end process tp_proc; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + -- Counting how long 'scl_i' input remains stable + scl_cnt_proc: + process(clk) + begin + if rising_edge(clk) then + if (s_rst = '1') then + scl_cnt <= 0; + else + if (scl_i_d /= scl_i) then + scl_cnt <= 1; + elsif (scl_cnt < max_cnt) then + scl_cnt <= scl_cnt + 1; + else + scl_cnt <= max_cnt; + end if; + end if; + end if; + end process scl_cnt_proc; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + -- Main Finite State Machine: + process(clk) + begin + if rising_edge(clk) then + if (s_rst = '1') then + state <= s_idle; + d_reg <= '0'; + i_reg <= '0'; + r_reg <= '0'; + cnt <= 0; + mbr_wr <= '0'; + mbr <= mbr_done; + else + -- Defaults: + if (cnt < max_cnt) then + cnt <= cnt + 1; + else + cnt <= max_cnt; + end if; + mbr_wr <= '0'; + ------ + + case state is + -- 'Idle' state ---------------------------------- + when s_idle => + if (mbc_wr = '1') then + case (mbc) is + when mbc_start => + state <= s_start_a; + when mbc_stop => + assert false report "Stop command without Start command!" severity error; + mbr_wr <= '1'; + mbr <= mbr_done; + when others => + assert false report "In 'Idle' state only Start command allowed!" severity error; + mbr_wr <= '1'; + mbr <= mbr_error; + end case; + cnt <= 0; + end if; + -- 'Idle' state ---------------------------------- + + -- 'Start A' state ------------------------------- + when s_start_a => + if (scl_i = '0')or(cnt = t_hd_sta_cnt) then -- t_{HD;STA} >= 4.0 us + state <= s_start_b; + end if; + -- 'Start A' state ------------------------------- + + -- 'Start B' state ------------------------------- + when s_start_b => + if (scl_i_d = '0')and(scl_cnt > t_vd_dat_cnt) then -- t_{VD;DAT} <= 3.45 us, t_{HD;DAT} >= 0 us; + state <= s_start_c; + mbr_wr <= '1'; + mbr <= mbr_done; + end if; + -- 'Start B' state ------------------------------- + + -- 'Start C' state ------------------------------- + when s_start_c => + if (mbc_wr = '1') then + case (mbc) is + when mbc_write_0 => + state <= s_rw_a; + d_reg <= '0'; -- data + r_reg <= '0'; -- read indication + when mbc_write_1 => + state <= s_rw_a; + d_reg <= '1'; -- data + r_reg <= '0'; -- read indication + when mbc_read => + state <= s_rw_a; + d_reg <= '1'; -- data + r_reg <= '1'; -- read indication + when mbc_stop => + state <= s_stop_a; + when mbc_start => + -- Second 'Start' command coming immediately after the first + -- one is ignored without an 'Error' response. + assert false report "Second Start command!" severity error; + mbr_wr <= '1'; + mbr <= mbr_done; + end case; + cnt <= 0; + end if; + -- 'Start C' state ------------------------------- + + -- 'Read/Write A' state -------------------------- + when s_rw_a => + if (cnt = t_su_dat_cnt) then -- t_{SU;DAT} >= 0.25 us + state <= s_rw_b; + end if; + -- 'Read/Write A' state -------------------------- + + -- 'Read/Write B' state -------------------------- + when s_rw_b => + if (scl_i = '1') then + state <= s_rw_c; + end if; + -- 'Read/Write B' state -------------------------- + + -- 'Read/Write C' state -------------------------- + when s_rw_c => + if (scl_i = '0')or((scl_cnt > t_high_cnt)and(cnt >= fe_cnt)) then -- t_{HIGH} >= 4.0 us; + state <= s_rw_d; + i_reg <= sda_i; + end if; + if (scl_i = '1')and(r_reg = '0')and(sda_i /= d_reg) then + mbr_wr <= '1'; + mbr <= mbr_arb_lost; -- Arbitration lost + state <= s_idle; + end if; + -- 'Read/Write C' state -------------------------- + + -- 'Read/Write D' state -------------------------- + when s_rw_d => + if (scl_i_d = '0')and(scl_cnt > t_vd_dat_cnt)and(cnt = max_cnt) then -- t_{VD;DAT} <= 3.45 us, t_{HD;DAT} >= 0 us; + state <= s_rw_e; + mbr_wr <= '1'; + if (r_reg = '0') then + mbr <= mbr_done; -- Successfull write + else + if (i_reg = '0') then + mbr <= mbr_bit_0; -- Bit 0 received + else + mbr <= mbr_bit_1; -- Bit 1 received + end if; + end if; + end if; + -- 'Read/Write D' state -------------------------- + + -- 'Read/Write E' state -------------------------- + when s_rw_e => + if (mbc_wr = '1') then + case (mbc) is + when mbc_write_0 => + state <= s_rw_a; + d_reg <= '0'; -- data + r_reg <= '0'; -- read indication + when mbc_write_1 => + state <= s_rw_a; + d_reg <= '1'; -- data + r_reg <= '0'; -- read indication + when mbc_read => + state <= s_rw_a; + d_reg <= '1'; -- data + r_reg <= '1'; -- read indication + when mbc_start => + state <= s_rstart_a; + when mbc_stop => + state <= s_stop_a; + end case; + cnt <= 0; + end if; + -- 'Read/Write E' state -------------------------- + + -- 'Stop A' state -------------------------------- + when s_stop_a => + if (cnt = t_su_dat_cnt) then -- t_{SU;DAT} >= 0.25 us + state <= s_stop_b; + end if; + -- 'Stop A' state -------------------------------- + + -- 'Stop B' state -------------------------------- + when s_stop_b => + if (scl_i = '1') then + state <= s_stop_c; + cnt <= 0; + end if; + -- 'Stop B' state -------------------------------- + + -- 'Stop C' state -------------------------------- + when s_stop_c => + if (cnt > t_su_sto_cnt) then -- t_{SU;STO} >= 4.0 us + state <= s_idle; + mbr_wr <= '1'; + mbr <= mbr_done; + cnt <= 0; + end if; + -- 'Stop C' state -------------------------------- + + -- 'Repeated Start A' state ---------------------- + when s_rstart_a => + if (cnt = t_su_dat_cnt) then -- t_{SU;DAT} >= 0.25 us + state <= s_rstart_b; + end if; + -- 'Repeated Start A' state ---------------------- + + -- 'Repeated Start B' state ---------------------- + when s_rstart_b => + if (scl_i = '1') then + state <= s_rstart_c; + end if; + -- 'Repeated Start B' state ---------------------- + + -- 'Repeated Start C' state ---------------------- + when s_rstart_c => + if (scl_i_d = '0')or((scl_cnt > t_su_sta_cnt)and(cnt = max_cnt)) then -- t_{SU;STA} >= 4.7 us + state <= s_start_a; + cnt <= 0; + end if; + if (scl_i = '1')and(sda_i = '0') then + mbr_wr <= '1'; + mbr <= mbr_arb_lost; -- Arbitration lost + state <= s_idle; + end if; + -- 'Repeated Start C' state ---------------------- + end case; + end if; + end if; + end process; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + scl_sda_proc: + process(clk) + begin + if rising_edge(clk) then + if (s_rst = '1') then + scl_o <= '1'; + sda_o <= '1'; + else + case state is + when s_idle => sda_o <= '1'; scl_o <= '1'; + when s_start_a => sda_o <= '0'; scl_o <= '1'; + when s_start_b => sda_o <= '0'; scl_o <= '0'; + when s_start_c => sda_o <= '0'; scl_o <= '0'; + when s_rw_a => sda_o <= d_reg; scl_o <= '0'; + when s_rw_b => sda_o <= d_reg; scl_o <= '1'; + when s_rw_c => sda_o <= d_reg; scl_o <= '1'; + when s_rw_d => sda_o <= d_reg; scl_o <= '0'; + when s_rw_e => sda_o <= d_reg; scl_o <= '0'; + when s_stop_a => sda_o <= '0'; scl_o <= '0'; + when s_stop_b => sda_o <= '0'; scl_o <= '1'; + when s_stop_c => sda_o <= '0'; scl_o <= '1'; + when s_rstart_a => sda_o <= '1'; scl_o <= '0'; + when s_rstart_b => sda_o <= '1'; scl_o <= '1'; + when s_rstart_c => sda_o <= '1'; scl_o <= '1'; + end case; + end if; + end if; + end process scl_sda_proc; + ------------------------------------------------------------------------------ + +end architecture rtl; +--============================================================================== +

trunk/src/mbit.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src/iicmb_int_pkg.vhd =================================================================== --- trunk/src/iicmb_int_pkg.vhd (nonexistent) +++ trunk/src/iicmb_int_pkg.vhd (revision 2) @@ -0,0 +1,107 @@ + +--============================================================================== +-- | +-- Project: IIC Multiple Bus Controller (IICMB) | +-- | +-- Module: Package for internal declarations. | +-- Version: | +-- 1.0, April 29, 2016 | +-- | +-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | +-- | +--============================================================================== +--============================================================================== +-- Copyright (c) 2016, Sergey Shuvalkin | +-- All rights reserved. | +-- | +-- Redistribution and use in source and binary forms, with or without | +-- modification, are permitted provided that the following conditions are met: | +-- | +-- 1. Redistributions of source code must retain the above copyright notice, | +-- this list of conditions and the following disclaimer. | +-- 2. Redistributions in binary form must reproduce the above copyright | +-- notice, this list of conditions and the following disclaimer in the | +-- documentation and/or other materials provided with the distribution. | +-- | +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | +-- POSSIBILITY OF SUCH DAMAGE. | +--============================================================================== + + +library ieee; +use ieee.std_logic_1164.all; + + +--============================================================================== +package iicmb_int_pkg is + + ------------------------------------------------------------------------------ + -- Bit-level master mode commands: + ------------------------------------------------------------------------------ + type mbc_type is + ( + mbc_start, -- Start --> Done | Arbitration Lost + mbc_stop, -- Stop --> Done + mbc_write_0, -- Write Bit 0 --> Done | Error + mbc_write_1, -- Write Bit 1 --> Done | Arbitration Lost | Error + mbc_read -- Read Bit --> Bit 0 Received | Bit 1 Received | Error + ); + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + -- Bit-level master mode responses: + ------------------------------------------------------------------------------ + type mbr_type is + ( + mbr_done, -- Done + mbr_arb_lost, -- Arbitration Lost + mbr_bit_0, -- Bit 0 Received + mbr_bit_1, -- Bit 1 Received + mbr_error -- Error + ); + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + -- Bit-level slave mode commands: + ------------------------------------------------------------------------------ + type sbc_type is + ( + sbc_idle, -- Idle + sbc_hold, -- Clock stretching + sbc_write_0, -- Write Bit 0 + sbc_write_1, -- Write Bit 1 + sbc_read -- Read Bit + ); + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + -- Bit-level slave mode responses: + ------------------------------------------------------------------------------ + type sbr_type is + ( + sbr_start, -- Start + sbr_stop, -- Stop + sbr_bit_0, -- Bit 0 received + sbr_bit_1 -- Bit 1 received + ); + ------------------------------------------------------------------------------ + +end package iicmb_int_pkg; +--============================================================================== + +--============================================================================== +package body iicmb_int_pkg is + + +end package body iicmb_int_pkg; +--============================================================================== +

trunk/src/iicmb_int_pkg.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sim/load_iicmb_m_tb =================================================================== --- trunk/sim/load_iicmb_m_tb (nonexistent) +++ trunk/sim/load_iicmb_m_tb (revision 2) @@ -0,0 +1,4 @@ +#!/bin/sh + +vsim work.iicmb_m_tb +

trunk/sim/load_iicmb_m_tb Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sim/load_iicmb_m_sq_tb =================================================================== --- trunk/sim/load_iicmb_m_sq_tb (nonexistent) +++ trunk/sim/load_iicmb_m_sq_tb (revision 2) @@ -0,0 +1,4 @@ +#!/bin/sh + +vsim work.iicmb_m_sq_tb +

trunk/sim/load_iicmb_m_sq_tb Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sim/modelsim.ini =================================================================== --- trunk/sim/modelsim.ini (nonexistent) +++ trunk/sim/modelsim.ini (revision 2) @@ -0,0 +1,884 @@ +; Copyright 1991-2007 Mentor Graphics Corporation +; +; All Rights Reserved. +; +; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF +; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. +; + +[Library] +others = $MODEL_TECH/../modelsim.ini +;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release +;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release + +;unisims_ver = $XILINX/../../ISE_lib/unisims_ver +;unimacro_ver = $XILINX/../../ISE_lib/unimacro_ver +;xilinxcorelib_ver = $XILINX/../../ISE_lib/XilinxCoreLib_ver +;simprims_ver = $XILINX/../../ISE_lib/simprims_ver +;secureip = $XILINX/../../ISE_lib/secureip +;unisim = $XILINX/../../ISE_lib/unisim +;unimacro = $XILINX/../../ISE_lib/unimacro +;xilinxcorelib = $XILINX/../../ISE_lib/XilinxCoreLib +;simprim = $XILINX/../../ISE_lib/simprim + +iicmb = iicmb +work = work + +[vcom] +; VHDL93 variable selects language version as the default. +; Default is VHDL-2002. +; Value of 0 or 1987 for VHDL-1987. +; Value of 1 or 1993 for VHDL-1993. +; Default or value of 2 or 2002 for VHDL-2002. +VHDL93 = 2002 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn off unbound-component warnings. Default is on. +; Show_Warning1 = 0 + +; Turn off process-without-a-wait-statement warnings. Default is on. +; Show_Warning2 = 0 + +; Turn off null-range warnings. Default is on. +; Show_Warning3 = 0 + +; Turn off no-space-in-time-literal warnings. Default is on. +; Show_Warning4 = 0 + +; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. +; Show_Warning5 = 0 + +; Turn off optimization for IEEE std_logic_1164 package. Default is on. +; Optimize_1164 = 0 + +; Turn on resolving of ambiguous function overloading in favor of the +; "explicit" function declaration (not the one automatically created by +; the compiler for each type declaration). Default is off. +; The .ini file has Explicit enabled so that std_logic_signed/unsigned +; will match the behavior of synthesis tools. +Explicit = 1 + +; Turn off acceleration of the VITAL packages. Default is to accelerate. +; NoVital = 1 + +; Turn off VITAL compliance checking. Default is checking on. +; NoVitalCheck = 1 + +; Ignore VITAL compliance checking errors. Default is to not ignore. +; IgnoreVitalErrors = 1 + +; Turn off VITAL compliance checking warnings. Default is to show warnings. +; Show_VitalChecksWarnings = 0 + +; Turn off PSL assertion warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Keep silent about case statement static warnings. +; Default is to give a warning. +; NoCaseStaticError = 1 + +; Keep silent about warnings caused by aggregates that are not locally static. +; Default is to give a warning. +; NoOthersStaticError = 1 + +; Treat as errors: +; case statement static warnings +; warnings caused by aggregates that are not locally static +; Overrides NoCaseStaticError, NoOthersStaticError settings. +; PedanticErrors = 1 + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on some limited synthesis rule compliance checking. Checks only: +; -- signals used (read) by a process must be in the sensitivity list +; CheckSynthesis = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Require the user to specify a configuration for all bindings, +; and do not generate a compile time default binding for the +; component. This will result in an elaboration error of +; 'component not bound' if the user fails to do so. Avoids the rare +; issue of a false dependency upon the unused default binding. +; RequireConfigForAllDefaultBinding = 1 + +; Perform default binding at compile time. +; Default is to do default binding at load time. +; BindAtCompile=1; + +; Inhibit range checking on subscripts of arrays. Range checking on +; scalars defined with subtypes is inhibited by default. +; NoIndexCheck = 1 + +; Inhibit range checks on all (implicit and explicit) assignments to +; scalar objects defined with subtypes. +; NoRangeCheck = 1 + +; Run the 0in tools from within the simulator. +; Default value set to 0. Please set it to 1 to invoke 0in. +; VcomZeroIn = 1 + +; Set the options to be passed to the 0in tools. +; Default value set to "". Please set it to appropriate options needed. +; VcomZeroInOptions = "" + +; Turn off code coverage in VHDL subprograms. Default is on. +; CoverageNoSub = 0 + +; Automatically exclude VHDL case statement default branches. +; Default is to not exclude. +; CoverExcludeDefault = 1 + +; Turn on code coverage in VHDL generate blocks. Default is off. +; CoverGenerate = 1 + +; Use this directory for compiler temporary files instead of "work/_temp" +; CompilerTempDir = /tmp + +[vlog] + +; Turn off inclusion of debugging info within design units. +; Default is to include debugging info. +; NoDebug = 1 + +; Turn on `protect compiler directive processing. +; Default is to ignore `protect directives. +; Protect = 1 + +; Turn off "Loading..." messages. Default is messages on. +; Quiet = 1 + +; Turn on Verilog hazard checking (order-dependent accessing of global vars). +; Default is off. +; Hazard = 1 + +; Turn on converting regular Verilog identifiers to uppercase. Allows case +; insensitivity for module names. Default is no conversion. +; UpCase = 1 + +; Activate optimizations on expressions that do not involve signals, +; waits, or function/procedure/task invocations. Default is off. +; ScalarOpts = 1 + +; Turns on lint-style checking. +; Show_Lint = 1 + +; Show source line containing error. Default is off. +; Show_source = 1 + +; Turn on bad option warning. Default is off. +; Show_BadOptionWarning = 1 + +; Revert back to IEEE 1364-1995 syntax, default is 0 (off). +vlog95compat = 0 + +; Turn off PSL warning messages. Default is to show warnings. +; Show_PslChecksWarnings = 0 + +; Enable parsing of embedded PSL assertions. Default is enabled. +; EmbeddedPsl = 0 + +; Set the threshold for automatically identifying sparse Verilog memories. +; A memory with depth equal to or more than the sparse memory threshold gets +; marked as sparse automatically, unless specified otherwise in source code. +; The default is 0 (i.e. no memory is automatically given sparse status) +; SparseMemThreshold = 1048576 + +; Set the maximum number of iterations permitted for a generate loop. +; Restricting this permits the implementation to recognize infinite +; generate loops. +; GenerateLoopIterationMax = 100000 + +; Set the maximum depth permitted for a recursive generate instantiation. +; Restricting this permits the implementation to recognize infinite +; recursions. +; GenerateRecursionDepthMax = 200 + +; Run the 0in tools from within the simulator. +; Default value set to 0. Please set it to 1 to invoke 0in. +; VlogZeroIn = 1 + +; Set the options to be passed to the 0in tools. +; Default value set to "". Please set it to appropriate options needed. +; VlogZeroInOptions = "" + +; Run the 0in tools from within the simulator. +; Default value set to 0. Please set it to 1 to invoke 0in. +; VoptZeroIn = 1 + +; Set the options to be passed to the 0in tools. +; Default value set to "". Please set it to appropriate options needed. +; VoptZeroInOptions = "" + +; Set the option to treat all files specified in a vlog invocation as a +; single compilation unit. The default value is set to 0 which will treat +; each file as a separate compilation unit as specified in the P1800 draft standard. +; MultiFileCompilationUnit = 1 + +; Automatically exclude Verilog case statement default branches. +; Default is to not exclude. +; CoverExcludeDefault = 1 + +; Turn on code coverage in VLOG generate blocks. Default is off. +; CoverGenerate = 1 + +; Specify the override for the default value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then LRM default +; value of 0 (zero) is used. This is a compile time option. +; SVCrossNumPrintMissingDefault = 0 + +; Setting following to 1 would cause creation of variables which +; would represent the value of Coverpoint expressions. This is used +; in conjunction with "SVCoverpointExprVariablePrefix" option +; in the modelsim.ini +; EnableSVCoverpointExprVariable = 0 + +; Specify the override for the prefix used in forming the variable names +; which represent the Coverpoint expressions. This is used in conjunction with +; "EnableSVCoverpointExprVariable" option of the modelsim.ini +; The default prefix is "expr". +; The variable name is +; variable name => _ +; SVCoverpointExprVariablePrefix = expr + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross option.goal (defined to be 100 in the LRM). +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" +; can override this value. +; SVCovergroupGoalDefault = 100 + +; Override for the default value of the SystemVerilog covergroup, +; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) +; NOTE: It does not override specific assignments in SystemVerilog +; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" +; can override this value. +; SVCovergroupTypeGoalDefault = 100 + +; Specify the override for the default value of "strobe" option for the +; Covergroup Type. This is a compile time option which forces "strobe" to +; a user specified default value and supersedes SystemVerilog specified +; default value of '0'(zero). NOTE: This can be overriden by a runtime +; modelsim.ini variable "SVCovergroupStrobeDefault". +; SVCovergroupStrobeDefault = 0 + +[sccom] +; Enable use of SCV include files and library. Default is off. +; UseScv = 1 + +; Add C++ compiler options to the sccom command line by using this variable. +; CppOptions = -g + +; Use custom C++ compiler located at this path rather than the default path. +; The path should point directly at a compiler executable. +; CppPath = /usr/bin/g++ + +; Enable verbose messages from sccom. Default is off. +; SccomVerbose = 1 + +; sccom logfile. Default is no logfile. +; SccomLogfile = sccom.log + +; Enable use of SC_MS include files and library. Default is off. +; UseScMs = 1 + +[vsim] + +; vopt flow +; Set to turn on automatic optimization of a design. +; Default is on +VoptFlow = 0 + +; vopt automatic SDF +; If automatic design optimization is on, enables automatic compilation +; of SDF files. +; Default is on, uncomment to turn off. +; VoptAutoSDFCompile = 0 + +; Simulator resolution +; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. +Resolution = 1 ps + +; User time unit for run commands +; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the +; unit specified for Resolution. For example, if Resolution is 100ps, +; then UserTimeUnit defaults to ps. +; Should generally be set to default. +UserTimeUnit = ps + +; Default run length +RunLength = 1000 ns + +; Maximum iterations that can be run without advancing simulation time +IterationLimit = 5000 + +; Control PSL and Verilog Assume directives during simulation +; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts +; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts +; SimulateAssumeDirectives = 1 + +; Control the simulation of PSL and SVA +; These switches can be overridden by the vsim command line switches: +; -psl, -nopsl, -sva, -nosva. +; Set SimulatePSL = 0 to disable PSL simulation +; Set SimulatePSL = 1 to enable PSL simulation (default) +; SimulatePSL = 1 +; Set SimulateSVA = 0 to disable SVA simulation +; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) +; SimulateSVA = 1 + +; Directives to license manager can be set either as single value or as +; space separated multi-values: +; vhdl Immediately reserve a VHDL license +; vlog Immediately reserve a Verilog license +; plus Immediately reserve a VHDL and Verilog license +; nomgc Do not look for Mentor Graphics Licenses +; nomti Do not look for Model Technology Licenses +; noqueue Do not wait in the license queue when a license is not available +; viewsim Try for viewer license but accept simulator license(s) instead +; of queuing for viewer license (PE ONLY) +; noviewer Disable checkout of msimviewer and vsim-viewer license +; features (PE ONLY) +; noslvhdl Disable checkout of qhsimvh and vsim license features +; noslvlog Disable checkout of qhsimvl and vsimvlog license features +; nomix Disable checkout of msimhdlmix and hdlmix license features +; nolnl Disable checkout of msimhdlsim and hdlsim license features +; mixedonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license +; features +; lnlonly Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix, +; hdlmix license features +; Single value: +; License = plus +; Multi-value: +; License = noqueue plus + +; Stop the simulator after a VHDL/Verilog immediate assertion message +; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal +BreakOnAssertion = 2 + +; VHDL assertion Message Format +; %S - Severity Level +; %R - Report Message +; %T - Time of assertion +; %D - Delta +; %I - Instance or Region pathname (if available) +; %i - Instance pathname with process +; %O - Process name +; %K - Kind of object path is to return: Instance, Signal, Process or Unknown +; %P - Instance or Region path without leaf process +; %F - File +; %L - Line number of assertion or, if assertion is in a subprogram, line +; from which the call is made +; %% - Print '%' character +; If specific format for assertion level is defined, use its format. +; If specific format is not defined for assertion level: +; - and if failure occurs during elaboration, use AssertionFormatBreakLine; +; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion +; level), use AssertionFormatBreak; +; - otherwise, use AssertionFormat. +; AssertionFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" +; AssertionFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" +; AssertionFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" +; AssertionFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" +; AssertionFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; AssertionFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" +; AssertionFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" + +; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages +; AssertFile = assert.log + + +; Simulation Breakpoint messages +; This flag controls the display of function names when reporting the location +; where the simulator stops do to a breakpoint or fatal error. +; Example w/function name: # Break in Process ctr at counter.vhd line 44 +; Example wo/function name: # Break at counter.vhd line 44 +ShowFunctions = 1 + + +; Default radix for all windows and commands. +; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned +DefaultRadix = symbolic + +; VSIM Startup command +; Startup = do startup.do + +; File for saving command transcript +TranscriptFile = transcript + +; File for saving command history +; CommandHistory = cmdhist.log + +; Specify whether paths in simulator commands should be described +; in VHDL or Verilog format. +; For VHDL, PathSeparator = / +; For Verilog, PathSeparator = . +; Must not be the same character as DatasetSeparator. +PathSeparator = / + +; Specify the dataset separator for fully rooted contexts. +; The default is ':'. For example: sim:/top +; Must not be the same character as PathSeparator. +DatasetSeparator = : + +; Specify a unique path separator for the Signal Spy set of functions. +; The default will be to use the PathSeparator variable. +; Must not be the same character as DatasetSeparator. +; SignalSpyPathSeparator = / + +; Disable VHDL assertion messages +; IgnoreNote = 1 +; IgnoreWarning = 1 +; IgnoreError = 1 +; IgnoreFailure = 1 + +; Disable System Verilog assertion messages +; Info and Warning are disabled by default +; IgnoreSVAInfo = 0 +; IgnoreSVAWarning = 0 +; IgnoreSVAError = 1 +; IgnoreSVAFatal = 1 + +; Default force kind. May be freeze, drive, deposit, or default +; or in other terms, fixed, wired, or charged. +; A value of "default" will use the signal kind to determine the +; force kind, drive for resolved signals, freeze for unresolved signals +; DefaultForceKind = freeze + +; If zero, open files when elaborated; otherwise, open files on +; first read or write. Default is 0. +; DelayFileOpen = 1 + +; Control VHDL files opened for write. +; 0 = Buffered, 1 = Unbuffered +UnbufferedOutput = 0 + +; Control the number of VHDL files open concurrently. +; This number should always be less than the current ulimit +; setting for max file descriptors. +; 0 = unlimited +ConcurrentFileLimit = 40 + +; Control the number of hierarchical regions displayed as +; part of a signal name shown in the Wave window. +; A value of zero tells VSIM to display the full name. +; The default is 0. +; WaveSignalNameWidth = 0 + +; Turn off warnings when changing VHDL constants and generics +; Default is 1 to generate warning messages +; WarnConstantChange = 0 + +; Turn off warnings from the std_logic_arith, std_logic_unsigned +; and std_logic_signed packages. +; StdArithNoWarnings = 1 + +; Turn off warnings from the IEEE numeric_std and numeric_bit packages. +; NumericStdNoWarnings = 1 + +; Control the format of the (VHDL) FOR generate statement label +; for each iteration. Do not quote it. +; The format string here must contain the conversion codes %s and %d, +; in that order, and no other conversion codes. The %s represents +; the generate_label; the %d represents the generate parameter value +; at a particular generate iteration (this is the position number if +; the generate parameter is of an enumeration type). Embedded whitespace +; is allowed (but discouraged); leading and trailing whitespace is ignored. +; Application of the format must result in a unique scope name over all +; such names in the design so that name lookup can function properly. +; GenerateFormat = %s__%d + +; Specify whether checkpoint files should be compressed. +; The default is 1 (compressed). +; CheckpointCompressMode = 0 + +; Specify whether to enable SystemVerilog DPI out-of-the-blue call. +; Out-of-the-blue call refers to a SystemVerilog export function call +; directly from a C function that don't have the proper context setup +; as done in DPI-C import C functions. When this is enabled, one can +; call a DPI export function (but not task) from any C code. +; The default is 0 (disabled). +; DpiOutOfTheBlue = 1 + +; List of dynamically loaded objects for Verilog PLI applications +; Veriuser = veriuser.sl + +; Specify default options for the restart command. Options can be one +; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions +; DefaultRestartOptions = -force + +; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs +; (> 500 megabyte memory footprint). Default is disabled. +; Specify number of megabytes to lock. +; LockedMemory = 1000 + +; HP-UX 11.00 ONLY - Use /usr/lib/libCsup_v2.sl for shared object loading. +; This is necessary when C++ files have been compiled with aCC's -AA option. +; The default behavior is to use /usr/lib/libCsup.sl. +; UseCsupV2 = 1 + +; Turn on (1) or off (0) WLF file compression. +; The default is 1 (compress WLF file). +; WLFCompress = 0 + +; Specify whether to save all design hierarchy (1) in the WLF file +; or only regions containing logged signals (0). +; The default is 0 (save only regions with logged signals). +; WLFSaveAllRegions = 1 + +; WLF file time limit. Limit WLF file by time, as closely as possible, +; to the specified amount of simulation time. When the limit is exceeded +; the earliest times get truncated from the file. +; If both time and size limits are specified the most restrictive is used. +; UserTimeUnits are used if time units are not specified. +; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} +; WLFTimeLimit = 0 + +; WLF file size limit. Limit WLF file size, as closely as possible, +; to the specified number of megabytes. If both time and size limits +; are specified then the most restrictive is used. +; The default is 0 (no limit). +; WLFSizeLimit = 1000 + +; Specify whether or not a WLF file should be deleted when the +; simulation ends. A value of 1 will cause the WLF file to be deleted. +; The default is 0 (do not delete WLF file when simulation ends). +; WLFDeleteOnQuit = 1 + +; Specify whether or not a WLF file should be optimized during +; simulation. If set to 0, the WLF file will not be optimized. +; The default is 1, optimize the WLF file. +; WLFOptimize = 0 + +; Specify the name of the WLF file. +; The default is vsim.wlf +; WLFFilename = vsim.wlf + +; WLF reader cache size limit. Specifies the internal WLF file cache size, +; in megabytes, for EACH open WLF file. A value of 0 turns off the +; WLF cache. +; The default setting is enabled to 256M per open WLF file. +; WLFCacheSize = 1000 + +; Specify the WLF file event collapse mode. +; 0 = Preserve all events and event order. (same as -wlfnocollapse) +; 1 = Only record values of logged objects at the end of a simulator iteration. +; (same as -wlfcollapsedelta) +; 2 = Only record values of logged objects at the end of a simulator time step. +; (same as -wlfcollapsetime) +; The default is 1. +; WLFCollapseMode = 0 + +; Turn on/off undebuggable SystemC type warnings. Default is on. +; ShowUndebuggableScTypeWarning = 0 + +; Turn on/off unassociated SystemC name warnings. Default is off. +; ShowUnassociatedScNameWarning = 1 + +; Set SystemC default time unit. +; Set to fs, ps, ns, us, ms, or sec with optional +; prefix of 1, 10, or 100. The default is 1 ns. +; The ScTimeUnit value is honored if it is coarser than Resolution. +; If ScTimeUnit is finer than Resolution, it is set to the value +; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, +; then the default time unit will be 1 ns. However if Resolution +; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. +ScTimeUnit = ns + +; Set the SCV relationship name that will be used to identify phase +; relations. If the name given to a transactor relation matches this +; name, the transactions involved will be treated as phase transactions +ScvPhaseRelationName = mti_phase + +; Customize the vsim kernel shutdown behavior at the end of the simulation. +; Some common causes of the end of simulation are $finish (implicit or explicit), +; sc_stop(), tf_dofinish(), and assertion failures. +; This should be set to "ask", "exit", or "stop". The default is "ask". +; "ask" -- In batch mode, the vsim kernel will abruptly exit. +; In GUI mode, a dialog box will pop up and ask for user confirmation +; whether or not to quit the simulation. +; "stop" -- Cause the simulation to stay loaded in memory. This can make some +; post-simulation tasks easier. +; "exit" -- The simulation will abruptly exit without asking for any confirmation. +; Note: these ini variables can be overriden by the vsim command +; line switch "-onfinish ". +OnFinish = ask + +; Print "simstats" result at the end of simulation before shutdown. +; If this is enabled, the simstats result will be printed out before shutdown. +; The default is off. +; PrintSimStats = 1 + +; Run simulator in assertion debug mode. Default is off. +; AssertionDebug = 1 + +; Turn on/off PSL/SVA concurrent assertion pass enable. Default is on. +; AssertionPassEnable = 0 + +; Turn on/off PSL/SVA concurrent assertion fail enable. Default is on. +; AssertionFailEnable = 0 + +; Set PSL/SVA concurrent assertion pass limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionPassLimit = 1 + +; Set PSL/SVA concurrent assertion fail limit. Default is -1. +; Any positive integer, -1 for infinity. +; AssertionFailLimit = 1 + +; Turn on/off PSL concurrent assertion pass log. Default is off. +; The flag does not affect SVA +; AssertionPassLog = 1 + +; Turn on/off PSL concurrent assertion fail log. Default is on. +; The flag does not affect SVA +; AssertionFailLog = 0 + +; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. +; 0 = Continue 1 = Break 2 = Exit +; AssertionFailAction = 1 + +; Turn on/off code coverage +; CodeCoverage = 0 + +; Count all code coverage condition and expression truth table rows that match. +; CoverCountAll = 1 + +; Turn on/off all PSL/SVA cover directive enables. Default is on. +; CoverEnable = 0 + +; Turn on/off PSL/SVA cover log. Default is off. +; CoverLog = 1 + +; Set "at_least" value for all PSL/SVA cover directives. Default is 1. +; CoverAtLeast = 2 + +; Set "limit" value for all PSL/SVA cover directives. Default is -1. +; Any positive integer, -1 for infinity. +; CoverLimit = 1 + +; Specify the coverage database filename. Default is "" (i.e. database is NOT automatically saved on close). +; UCDBFilename = vsim.ucdb + +; Specify the maximum limit for the number of Cross (bin) products reported +; in XML and UCDB report against a Cross. A warning is issued if the limit +; is crossed. +; MaxReportRhsSVCrossProducts = 1000 + +; Specify the override for the "auto_bin_max" option for the Covergroups. +; If not specified then value from Covergroup "option" is used. +; SVCoverpointAutoBinMax = 64 + +; Specify the override for the value of "cross_num_print_missing" +; option for the Cross in Covergroups. If not specified then value +; specified in the "option.cross_num_print_missing" is used. This +; is a runtime option. NOTE: This overrides any "cross_num_print_missing" +; value specified by user in source file and any SVCrossNumPrintMissingDefault +; specified in modelsim.ini. +; SVCrossNumPrintMissing = 0 + +; Specify the override for the value of "strobe" option for the +; Covergroup Type. If not specified then value in "type_option.strobe" +; will be used. This is runtime option which forces "strobe" to +; user specified value and supersedes user specified values in the +; SystemVerilog Code. NOTE: This also overrides the compile time +; default value override specified using "SVCovergroupStrobeDefault" +; SVCovergroupStrobe = 0 + +; Override for explicit assignments in source code to "option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". +; SVCovergroupGoal = 100 + +; Override for explicit assignments in source code to "type_option.goal" of +; SystemVerilog covergroup, coverpoint, and cross. It also overrides the +; default value of "type_option.goal" (defined to be 100 in the SystemVerilog +; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". +; SVCovergroupTypeGoal = 100 + +; Specify the maximum number of Coverpoint bins in whole design for +; all Covergroups. +; MaxSVCoverpointBinsDesign = 2147483648 + +; Specify maximum number of Coverpoint bins in any instance of a Covergroup +; MaxSVCoverpointBinsInst = 2147483648 + +; Specify the maximum number of Cross bins in whole design for +; all Covergroups. +; MaxSVCrossBinsDesign = 2147483648 + +; Specify maximum number of Cross bins in any instance of a Covergroup +; MaxSVCrossBinsInst = 2147483648 + +; Set weight for all PSL/SVA cover directives. Default is 1. +; CoverWeight = 2 + +; Check vsim plusargs. Default is 0 (off). +; 0 = Don't check plusargs +; 1 = Warning on unrecognized plusarg +; 2 = Error and exit on unrecognized plusarg +; CheckPlusargs = 1 + +; Load the specified shared objects with the RTLD_GLOBAL flag. +; This gives global visibility to all symbols in the shared objects, +; meaning that subsequently loaded shared objects can bind to symbols +; in the global shared objects. The list of shared objects should +; be whitespace delimited. This option is not supported on the +; Windows or AIX platforms. +; GlobalSharedObjectList = example1.so example2.so example3.so + +; Run the 0in tools from within the simulator. +; Default value set to 0. Please set it to 1 to invoke 0in. +; VsimZeroIn = 1 + +; Set the options to be passed to the 0in tools. +; Default value set to "". Please set it to appropriate options needed. +; VsimZeroInOptions = "" + +; Initial seed for the Random Number Generator (RNG) of the root thread (SystemVerilog). +; Sv_Seed = 0 + +; Maximum size of dynamic arrays that are resized during randomize(). +; The default is 1000. A value of 0 indicates no limit. +; SolveArrayResizeMax = 1000 + +; Error message severity when randomize() failure is detected (SystemVerilog). +; The default is 0 (no error). +; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal +; SolveFailSeverity = 0 + +; Enable/disable debug information for randomize() failures (SystemVerilog). +; The default is 0 (disabled). Set to 1 to enable. +; SolveFailDebug = 0 + +; When SolveFailDebug is enabled, this value specifies the maximum number of +; constraint subsets that will be tested for conflicts. +; The default is 0 (no limit). +; SolveFailDebugLimit = 0 + +; When SolveFailDebug is enabled, this value specifies the maximum size of +; constraint subsets that will be tested for conflicts. +; The default value is 0 (no limit). +; SolveFailDebugMaxSet = 0 + +; Maximum size of the solution graph that may be generated during randomize(). +; This value can be used to force randomize() to abort if the complexity of +; the constraint scenario (both in memory and time spent during evaluation) +; exceeds the specified limit. This value is specified in 1000s of nodes. +; The default is 10000. A value of 0 indicates no limit. +; SolveGraphMaxSize = 10000 + +; Use SolveFlags to specify options that will guide the behavior of the +; constraint solver. These options may improve the performance of the +; constraint solver for some testcases, and decrease the performance of +; the constraint solver for others. +; The default value is "" (no options). +; +; Valid flags are: +; i = disable bit interleaving for >, >=, <, <= constraints +; r = reverse bit interleaving +; +; SolveFlags = + +; Specify random sequence compatiblity with a prior letter release. This +; option is used to get the same random sequences during simulation as +; as a prior letter release. Only prior letter releases (of the current +; number release) are allowed. +; Note: To achieve the same random sequences, solver optimizations and/or +; bug fixes introduced since the specified release may be disabled - +; yielding the performance / behavior of the prior release. +; Default value set to "" (random compatibility not required). +; SolveRev = + +; Environment variable expansion of command line arguments has been depricated +; in favor shell level expansion. Universal environment variable expansion +; inside -f files is support and continued support for MGC Location Maps provide +; alternative methods for handling flexible pathnames. +; The following line may be uncommented and the value set to 1 to re-enable this +; deprecated behavior. The default value is 0. +; DeprecatedEnvironmentVariableExpansion = 0 + +; Retroactive Recording uses a limited number of private data channels in the WLF +; file. Too many channels degrade WLF performance. If the limit is reached, +; simulation ends with a fatal error. You may change this limit as needed, but be +; aware of the implications of too many channels. The value must be an integer +; greater than or equal to zero, where zero disables all retroactive recording. +; RetroChannelLimit = 20 + +; Options to give vopt when code coverage is turned on. +; Default is "+acc=lprnb -opt=-merge -opt=-suppressAlways" +; VoptCoverageOptions = +acc=lprnb -opt=-merge -opt=-suppressAlways + +; Turn on/off collapsing of bus ports in VCD dumpports output +DumpportsCollapse = 0 + +[lmc] +; The simulator's interface to Logic Modeling's SmartModel SWIFT software +libsm = $MODEL_TECH/libsm.sl +; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) +; libsm = $MODEL_TECH/libsm.dll +; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) +; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl +; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) +; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o +; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) +; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so +; Logic Modeling's SmartModel SWIFT software (Windows NT) +; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll +; Logic Modeling's SmartModel SWIFT software (Linux) +; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so + +; The simulator's interface to Logic Modeling's hardware modeler SFI software +libhm = $MODEL_TECH/libhm.sl +; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) +; libhm = $MODEL_TECH/libhm.dll +; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) +; libsfi = /lib/hp700/libsfi.sl +; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) +; libsfi = /lib/rs6000/libsfi.a +; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) +; libsfi = /lib/sun4.solaris/libsfi.so +; Logic Modeling's hardware modeler SFI software (Windows NT) +; libsfi = /lib/pcnt/lm_sfi.dll +; Logic Modeling's hardware modeler SFI software (Linux) +; libsfi = /lib/linux/libsfi.so + +[msg_system] +; Change a message severity or suppress a message. +; The format is: = [,...] +; Examples: +; note = 3009 +; warning = 3033 +; error = 3010,3016 +; fatal = 3016,3033 +; suppress = 3009,3016,3043 +; The command verror can be used to get the complete +; description of a message. + +; Control transcripting of elaboration/runtime messages. +; The default is to have messages appear in the transcript and +; recorded in the wlf file (messages that are recorded in the +; wlf file can be viewed in the MsgViewer). The other settings +; are to send messages only to the transcript or only to the +; wlf file. The valid values are +; both {default} +; tran {transcript only} +; wlf {wlf file only} +; msgmode = both

trunk/sim/modelsim.ini Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sim/include.mk =================================================================== --- trunk/sim/include.mk (nonexistent) +++ trunk/sim/include.mk (revision 2) @@ -0,0 +1,177 @@ + +# Should be defined externally: +# IICMB_DIR -- Directory of the IICMB project sources +# LIB_IICMB -- Design library for IICMB core +# LIB_IICMB_TB -- Design library for IICMB testbenches + + +# We have to explicitly introduce both primary and secondary units in order to +# be able to consistently recompile the sources. +LIB_IICMB__iicmb_pkg = $(LIB_IICMB)/iicmb_pkg/_primary.dat +LIB_IICMB__iicmb_pkg__body = $(LIB_IICMB)/iicmb_pkg/body.dat +LIB_IICMB__iicmb_int_pkg = $(LIB_IICMB)/iicmb_int_pkg/_primary.dat +LIB_IICMB__iicmb_int_pkg__body = $(LIB_IICMB)/iicmb_int_pkg/body.dat +LIB_IICMB__wishbone = $(LIB_IICMB)/wishbone/_primary.dat +LIB_IICMB__wishbone__rtl = $(LIB_IICMB)/wishbone/rtl.dat +LIB_IICMB__avalon_mm = $(LIB_IICMB)/avalon_mm/_primary.dat +LIB_IICMB__avalon_mm__rtl = $(LIB_IICMB)/avalon_mm/rtl.dat +LIB_IICMB__sequencer = $(LIB_IICMB)/sequencer/_primary.dat +LIB_IICMB__sequencer__rtl = $(LIB_IICMB)/sequencer/rtl.dat +LIB_IICMB__regblock = $(LIB_IICMB)/regblock/_primary.dat +LIB_IICMB__regblock__rtl = $(LIB_IICMB)/regblock/rtl.dat +LIB_IICMB__mbyte = $(LIB_IICMB)/mbyte/_primary.dat +LIB_IICMB__mbyte__rtl = $(LIB_IICMB)/mbyte/rtl.dat +LIB_IICMB__mbit = $(LIB_IICMB)/mbit/_primary.dat +LIB_IICMB__mbit__rtl = $(LIB_IICMB)/mbit/rtl.dat +LIB_IICMB__bus_state = $(LIB_IICMB)/bus_state/_primary.dat +LIB_IICMB__bus_state__rtl = $(LIB_IICMB)/bus_state/rtl.dat +LIB_IICMB__filter = $(LIB_IICMB)/filter/_primary.dat +LIB_IICMB__filter__rtl = $(LIB_IICMB)/filter/rtl.dat +LIB_IICMB__conditioner = $(LIB_IICMB)/conditioner/_primary.dat +LIB_IICMB__conditioner__str = $(LIB_IICMB)/conditioner/str.dat +LIB_IICMB__conditioner_mux = $(LIB_IICMB)/conditioner_mux/_primary.dat +LIB_IICMB__conditioner_mux__str = $(LIB_IICMB)/conditioner_mux/str.dat +LIB_IICMB__iicmb_m = $(LIB_IICMB)/iicmb_m/_primary.dat +LIB_IICMB__iicmb_m__str = $(LIB_IICMB)/iicmb_m/str.dat +LIB_IICMB__iicmb_m_wb = $(LIB_IICMB)/iicmb_m_wb/_primary.dat +LIB_IICMB__iicmb_m_wb__str = $(LIB_IICMB)/iicmb_m_wb/str.dat +LIB_IICMB__iicmb_m_av = $(LIB_IICMB)/iicmb_m_av/_primary.dat +LIB_IICMB__iicmb_m_av__str = $(LIB_IICMB)/iicmb_m_av/str.dat +LIB_IICMB__iicmb_m_sq = $(LIB_IICMB)/iicmb_m_sq/_primary.dat +LIB_IICMB__iicmb_m_sq__str = $(LIB_IICMB)/iicmb_m_sq/str.dat + +# Testbench targets: +LIB_IICMB_TB__i2c_slave_model = $(LIB_IICMB_TB)/i2c_slave_model/_primary.dat +LIB_IICMB_TB__test = $(LIB_IICMB_TB)/test/_primary.dat +LIB_IICMB_TB__test__body = $(LIB_IICMB_TB)/test/body.dat +LIB_IICMB_TB__wire_mdl = $(LIB_IICMB_TB)/wire_mdl/_primary.dat +LIB_IICMB_TB__wire_mdl__beh = $(LIB_IICMB_TB)/wire_mdl/beh.dat +LIB_IICMB_TB__iicmb_m_tb = $(LIB_IICMB_TB)/iicmb_m_tb/_primary.dat +LIB_IICMB_TB__iicmb_m_tb__beh = $(LIB_IICMB_TB)/iicmb_m_tb/beh.dat +LIB_IICMB_TB__iicmb_m_wb_tb = $(LIB_IICMB_TB)/iicmb_m_wb_tb/_primary.dat +LIB_IICMB_TB__iicmb_m_wb_tb__beh = $(LIB_IICMB_TB)/iicmb_m_wb_tb/beh.dat +LIB_IICMB_TB__iicmb_m_sq_tb = $(LIB_IICMB_TB)/iicmb_m_sq_tb/_primary.dat +LIB_IICMB_TB__iicmb_m_sq_tb__beh = $(LIB_IICMB_TB)/iicmb_m_sq_tb/beh.dat +LIB_IICMB_TB__iicmb_m_sq_arb_tb = $(LIB_IICMB_TB)/iicmb_m_sq_arb_tb/_primary.dat +LIB_IICMB_TB__iicmb_m_sq_arb_tb__beh = $(LIB_IICMB_TB)/iicmb_m_sq_arb_tb/beh.dat + + +$(LIB_IICMB) : + vlib -type directory $(LIB_IICMB) + +$(LIB_IICMB_TB) : + vlib -type directory $(LIB_IICMB_TB) + +$(LIB_IICMB__iicmb_pkg) $(LIB_IICMB__iicmb_pkg__body) : $(IICMB_DIR)/src/iicmb_pkg.vhd | $(LIB_IICMB) + $(VCOM) -work $(LIB_IICMB) -2002 -O0 -quiet -explicit -check_synthesis $< + +$(LIB_IICMB__iicmb_int_pkg) $(LIB_IICMB__iicmb_int_pkg__body) : $(IICMB_DIR)/src/iicmb_int_pkg.vhd | $(LIB_IICMB) + $(VCOM) -work $(LIB_IICMB) -2002 -O0 -quiet -explicit -check_synthesis $< + +$(LIB_IICMB__regblock) $(LIB_IICMB__regblock__rtl) : $(IICMB_DIR)/src/regblock.vhd $(LIB_IICMB__iicmb_pkg) | $(LIB_IICMB) + $(VCOM) -work $(LIB_IICMB) -2002 -O0 -quiet -explicit -check_synthesis $< + +$(LIB_IICMB__avalon_mm) $(LIB_IICMB__avalon_mm__rtl) : $(IICMB_DIR)/src/avalon_mm.vhd | $(LIB_IICMB) + $(VCOM) -work $(LIB_IICMB) -2002 -O0 -quiet -explicit -check_synthesis $< + +$(LIB_IICMB__sequencer) $(LIB_IICMB__sequencer__rtl) : $(IICMB_DIR)/src/sequencer.vhd $(LIB_IICMB__iicmb_pkg) | $(LIB_IICMB) + $(VCOM) -work $(LIB_IICMB) -2002 -O0 -quiet -explicit -check_synthesis $< + +$(LIB_IICMB__wishbone) $(LIB_IICMB__wishbone__rtl) : $(IICMB_DIR)/src/wishbone.vhd | $(LIB_IICMB) + $(VCOM) -work $(LIB_IICMB) -2002 -O0 -quiet -explicit -check_synthesis $< + +$(LIB_IICMB__mbyte) $(LIB_IICMB__mbyte__rtl) : $(IICMB_DIR)/src/mbyte.vhd $(LIB_IICMB__iicmb_pkg) $(LIB_IICMB__iicmb_int_pkg) | $(LIB_IICMB) + $(VCOM) -work $(LIB_IICMB) -2002 -O0 -quiet -explicit -check_synthesis $< + +$(LIB_IICMB__mbit) $(LIB_IICMB__mbit__rtl) : $(IICMB_DIR)/src/mbit.vhd $(LIB_IICMB__iicmb_int_pkg) | $(LIB_IICMB) + $(VCOM) -work $(LIB_IICMB) -2002 -O0 -quiet -explicit -check_synthesis $< + +$(LIB_IICMB__bus_state) $(LIB_IICMB__bus_state__rtl) : $(IICMB_DIR)/src/bus_state.vhd | $(LIB_IICMB) + $(VCOM) -work $(LIB_IICMB) -2002 -O0 -quiet -explicit -check_synthesis $< + +$(LIB_IICMB__filter) $(LIB_IICMB__filter__rtl) : $(IICMB_DIR)/src/filter.vhd | $(LIB_IICMB) + $(VCOM) -work $(LIB_IICMB) -2002 -O0 -quiet -explicit -check_synthesis $< + +$(LIB_IICMB__conditioner) $(LIB_IICMB__conditioner__str) : $(IICMB_DIR)/src/conditioner.vhd | $(LIB_IICMB) + $(VCOM) -work $(LIB_IICMB) -2002 -O0 -quiet -explicit -check_synthesis $< + +$(LIB_IICMB__conditioner_mux) $(LIB_IICMB__conditioner_mux__str) : $(IICMB_DIR)/src/conditioner_mux.vhd | $(LIB_IICMB) + $(VCOM) -work $(LIB_IICMB) -2002 -O0 -quiet -explicit -check_synthesis $< + +$(LIB_IICMB__iicmb_m) $(LIB_IICMB__iicmb_m__str) : $(IICMB_DIR)/src/iicmb_m.vhd $(LIB_IICMB__iicmb_pkg) $(LIB_IICMB__iicmb_int_pkg) | $(LIB_IICMB) + $(VCOM) -work $(LIB_IICMB) -2002 -O0 -quiet -explicit -check_synthesis $< + +$(LIB_IICMB__iicmb_m_wb) $(LIB_IICMB__iicmb_m_wb__str) : $(IICMB_DIR)/src/iicmb_m_wb.vhd | $(LIB_IICMB) + $(VCOM) -work $(LIB_IICMB) -2002 -O0 -quiet -explicit -check_synthesis $< + +$(LIB_IICMB__iicmb_m_av) $(LIB_IICMB__iicmb_m_av__str) : $(IICMB_DIR)/src/iicmb_m_av.vhd | $(LIB_IICMB) + $(VCOM) -work $(LIB_IICMB) -2002 -O0 -quiet -explicit -check_synthesis $< + +$(LIB_IICMB__iicmb_m_sq) $(LIB_IICMB__iicmb_m_sq__str) : $(IICMB_DIR)/src/iicmb_m_sq.vhd | $(LIB_IICMB) + $(VCOM) -work $(LIB_IICMB) -2002 -O0 -quiet -explicit -check_synthesis $< + + +$(LIB_IICMB_TB__i2c_slave_model) : $(IICMB_DIR)/src_tb/i2c_slave_model.v $(IICMB_DIR)/src_tb/timescale.v | $(LIB_IICMB_TB) + $(VLOG) -work $(LIB_IICMB_TB) -O0 -quiet +incdir+$(IICMB_DIR)/src_tb $< + + +$(LIB_IICMB_TB__test) $(LIB_IICMB_TB__test__body) : $(IICMB_DIR)/src_tb/test.vhd | $(LIB_IICMB_TB) + $(VCOM) -work $(LIB_IICMB_TB) -2002 -O0 -quiet -explicit $< + +$(LIB_IICMB_TB__wire_mdl) $(LIB_IICMB_TB__wire_mdl__beh) : $(IICMB_DIR)/src_tb/wire_mdl.vhd | $(LIB_IICMB_TB) + $(VCOM) -work $(LIB_IICMB_TB) -2002 -O0 -quiet -explicit $< + +$(LIB_IICMB_TB__iicmb_m_tb) $(LIB_IICMB_TB__iicmb_m_tb__beh) : $(IICMB_DIR)/src_tb/iicmb_m_tb.vhd $(LIB_IICMB__iicmb_pkg) $(LIB_IICMB__test) | $(LIB_IICMB_TB) + $(VCOM) -work $(LIB_IICMB_TB) -2002 -O0 -quiet -explicit $< + +$(LIB_IICMB_TB__iicmb_m_wb_tb) $(LIB_IICMB_TB__iicmb_m_wb_tb__beh) : $(IICMB_DIR)/src_tb/iicmb_m_wb_tb.vhd $(LIB_IICMB__iicmb_pkg) $(LIB_IICMB__test) | $(LIB_IICMB_TB) + $(VCOM) -work $(LIB_IICMB_TB) -2002 -O0 -quiet -explicit $< + +$(LIB_IICMB_TB__iicmb_m_sq_tb) $(LIB_IICMB_TB__iicmb_m_sq_tb__beh) : $(IICMB_DIR)/src_tb/iicmb_m_sq_tb.vhd $(LIB_IICMB__iicmb_pkg) $(LIB_IICMB__test) | $(LIB_IICMB_TB) + $(VCOM) -work $(LIB_IICMB_TB) -2002 -O0 -quiet -explicit $< + +$(LIB_IICMB_TB__iicmb_m_sq_arb_tb) $(LIB_IICMB_TB__iicmb_m_sq_arb_tb__beh) : $(IICMB_DIR)/src_tb/iicmb_m_sq_arb_tb.vhd $(LIB_IICMB__iicmb_pkg) $(LIB_IICMB__test) | $(LIB_IICMB_TB) + $(VCOM) -work $(LIB_IICMB_TB) -2002 -O0 -quiet -explicit $< + + + +IICMB_TGTS = \ + $(LIB_IICMB__avalon_mm) $(LIB_IICMB__avalon_mm__rtl) \ + $(LIB_IICMB__sequencer) $(LIB_IICMB__sequencer__rtl) \ + $(LIB_IICMB__wishbone) $(LIB_IICMB__wishbone__rtl) \ + $(LIB_IICMB__regblock) $(LIB_IICMB__regblock__rtl) \ + $(LIB_IICMB__mbyte) $(LIB_IICMB__mbyte__rtl) \ + $(LIB_IICMB__mbit) $(LIB_IICMB__mbit__rtl) \ + $(LIB_IICMB__bus_state) $(LIB_IICMB__bus_state__rtl) \ + $(LIB_IICMB__filter) $(LIB_IICMB__filter__rtl) \ + $(LIB_IICMB__conditioner) $(LIB_IICMB__conditioner__str) \ + $(LIB_IICMB__conditioner_mux) $(LIB_IICMB__conditioner_mux__str) \ + $(LIB_IICMB__iicmb_m) $(LIB_IICMB__iicmb_m__str) \ + $(LIB_IICMB__iicmb_m_wb) $(LIB_IICMB__iicmb_m_wb__str) \ + $(LIB_IICMB__iicmb_m_av) $(LIB_IICMB__iicmb_m_av__str) \ + $(LIB_IICMB__iicmb_m_sq) $(LIB_IICMB__iicmb_m_sq__str) \ + + +IICMB_TB_TGTS = \ + $(LIB_IICMB_TB__i2c_slave_model) \ + $(LIB_IICMB_TB__test) $(LIB_IICMB_TB__test__body) \ + $(LIB_IICMB_TB__wire_mdl) $(LIB_IICMB_TB__wire_mdl__beh) \ + $(LIB_IICMB_TB__iicmb_m_tb) $(LIB_IICMB_TB__iicmb_m_tb__beh) \ + $(LIB_IICMB_TB__iicmb_m_wb_tb) $(LIB_IICMB_TB__iicmb_m_wb_tb__beh) \ + $(LIB_IICMB_TB__iicmb_m_sq_tb) $(LIB_IICMB_TB__iicmb_m_sq_tb__beh) \ + $(LIB_IICMB_TB__iicmb_m_sq_arb_tb) $(LIB_IICMB_TB__iicmb_m_sq_arb_tb__beh) \ + + + +.PHONY : clean_iicmb +clean_iicmb : + if [ -d $(LIB_IICMB) ]; then rm -rf $(LIB_IICMB); fi; + +.PHONY : clean_iicmb_tb +clean_iicmb_tb : + if [ -d $(LIB_IICMB_TB) ]; then rm -rf $(LIB_IICMB_TB); fi; + + +ALL_TARGETS := $(ALL_TARGETS) $(IICMB_TGTS) $(IICMB_TB_TGTS) +CLEAN_TARGETS := $(CLEAN_TARGETS) clean_iicmb clean_iicmb_tb +

trunk/sim/include.mk Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sim/load_iicmb_m_sq_arb_tb =================================================================== --- trunk/sim/load_iicmb_m_sq_arb_tb (nonexistent) +++ trunk/sim/load_iicmb_m_sq_arb_tb (revision 2) @@ -0,0 +1,4 @@ +#!/bin/sh + +vsim work.iicmb_m_sq_arb_tb +

trunk/sim/load_iicmb_m_sq_arb_tb Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sim/load_iicmb_m_wb_tb =================================================================== --- trunk/sim/load_iicmb_m_wb_tb (nonexistent) +++ trunk/sim/load_iicmb_m_wb_tb (revision 2) @@ -0,0 +1,4 @@ +#!/bin/sh + +vsim work.iicmb_m_wb_tb +

trunk/sim/load_iicmb_m_wb_tb Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/sim/Makefile =================================================================== --- trunk/sim/Makefile (nonexistent) +++ trunk/sim/Makefile (revision 2) @@ -0,0 +1,28 @@ + +# Makefile for IICMB project + +# VHDL compiler name: +VCOM = vcom + +# Verilog compiler name: +VLOG = vlog + +# path to the sources: +IICMB_DIR = .. + +# paths to compiled libraries: +LIB_IICMB = iicmb +LIB_IICMB_TB = work + + +include ./include.mk + + +.PHONY : all +all : $(ALL_TARGETS) + + +.PHONY : clean +clean : $(CLEAN_TARGETS) + rm -rf transcript vsim.wlf; +

trunk/sim/Makefile Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src_tb/test.vhd =================================================================== --- trunk/src_tb/test.vhd (nonexistent) +++ trunk/src_tb/test.vhd (revision 2) @@ -0,0 +1,1259 @@ + +--============================================================================== +-- | +-- Project: IIC Multiple Bus Controller (IICMB) | +-- | +-- Module: Test package. | +-- Version: | +-- 1.0, April 29, 2016 | +-- | +-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | +-- | +--============================================================================== +--============================================================================== +-- Copyright (c) 2016, Sergey Shuvalkin | +-- All rights reserved. | +-- | +-- Redistribution and use in source and binary forms, with or without | +-- modification, are permitted provided that the following conditions are met: | +-- | +-- 1. Redistributions of source code must retain the above copyright notice, | +-- this list of conditions and the following disclaimer. | +-- 2. Redistributions in binary form must reproduce the above copyright | +-- notice, this list of conditions and the following disclaimer in the | +-- documentation and/or other materials provided with the distribution. | +-- | +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | +-- POSSIBILITY OF SUCH DAMAGE. | +--============================================================================== + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + + +--============================================================================== +package test is + + type integer_array is array (natural range <>) of integer; + type integer_array_ptr is access integer_array; + type string_ptr is access string; + + type char_file is file of character; + ------------------------------------------------------------------------------ + -- The file type declaration above implicitly defines the following operations: + -- procedure file_open ( file f : char_file; name : in string; open_kind : in file_open_kind := read_mode); + -- procedure file_open (status : out file_open_status; file f : char_file; name : in string; open_kind : in file_open_kind := read_mode); + -- procedure file_close(file f : char_file); + -- procedure read (file f : char_file; value : out character); + -- procedure write(file f : char_file; value : in character); + -- function endfile(file f : char_file) return boolean; + ------------------------------------------------------------------------------ + + file stdin : char_file open read_mode is "STD_INPUT"; + file stdout : char_file open write_mode is "STD_OUTPUT"; + + ------------------------------------------------------------------------------ + -- Printing to a file and stdout: + constant newline : string := "" & lf; + + procedure fprint_string(file f : char_file; value : in string); + procedure print_string(value : in string); + --function to_string(value : in integer; width : in positive := 1) return string; + --function to_string(value : in std_logic_vector) return string; + + ------------------------------------------------------------------------------ + -- Function for converting integer to string: + function to_string(value : in integer; + format : in string := "d"; + width : in natural := 0; + prec : in natural := 0) return string; + function to_string(value : in std_logic; + format : in string := "b"; + width : in natural := 0; + prec : in natural := 0) return string; + function to_string(value : in std_logic_vector; + format : in string := "x"; + width : in natural := 0; + prec : in natural := 0) return string; + -- + -- format string: [FLAGS][WIDTH][.PREC]TYPE + -- + -- * FLAGS + -- an optional sequence of characters which control output + -- justification, numeric signs, trailing zeroes, and octal and hex + -- prefixes. The flag characters are minus (`-'), plus (`+'), space + -- ( ), zero (`0'), and sharp (`#'). They can appear in any + -- combination. + -- + -- `-' The result of the conversion is left justified, and the right + -- is padded with blanks. If you do not use this flag, the + -- result is right justified, and padded on the left. + -- + -- `+' The result of a signed conversion (as determined by TYPE) + -- will always begin with a plus or minus sign. (If you do not + -- use this flag, positive values do not begin with a plus sign.) + -- + -- `" " (space)' + -- If the first character of a signed conversion specification + -- is not a sign, or if a signed conversion results in no + -- characters, the result will begin with a space. If the space + -- ( ) flag and the plus (`+') flag both appear, the space flag + -- is ignored. + -- + -- `0' Leading zeroes are used to pad the field width (following any + -- indication of sign or base); no spaces are used for padding. + -- If the zero (`0') and minus (`-') flags both appear, the zero + -- (`0') flag will be ignored. If a precision PREC is specified, + -- the zero (`0') flag is ignored. Note that `0' is interpreted + -- as a flag, not as the beginning of a field width. + -- + -- `#' The result is to be converted to an alternative form, + -- depending on the conversion type character: + -- + -- `b' result will have a `b' prefix. + -- + -- `o' increases precision to force the first digit of the + -- result to be a zero. + -- + -- `x' result will have a `0x' prefix. + -- + -- `X' result will have a `0X' prefix. + -- + -- `all others' + -- ignored. + -- + -- * WIDTH + -- WIDTH is an optional minimum field width. You can either specify + -- it directly as a decimal integer, or indirectly by using instead + -- an asterisk (`*'), in which case the 'width' argument is used as + -- the field width. + -- + -- * PREC + -- an optional field; if present, it is introduced with "." (a + -- period). This field gives the minimum number of digits of an + -- integer to print. You can specify the precision either directly as + -- a decimal integer or indirectly by using an asterisk (`*'), in which + -- case a 'prec' argument is used as the precision. If only a period + -- is specified the precision is zero. + -- + -- * TYPE + -- TYPE field specifies what kind of conversion to_string() performs. + -- Here is a table of these: + -- + -- `b' prints a unsigned binary integer; + -- + -- `d' prints a signed decimal integer; (same as `i') + -- + -- `i' prints a signed decimal integer; (same as `d') + -- + -- `o' prints an unsigned octal integer; + -- + -- `u' prints an unsigned decimal integer; + -- + -- `x' prints an unsigned hexadecimal integer (using `abcdef' as + -- digits beyond `9'); + -- + -- `X' prints an unsigned hexadecimal integer (using `ABCDEF' as + -- digits beyond `9'); + ------------------------------------------------------------------------------ + + + ------------------------------------------------------------------------------ + -- format: [FLAGS][WIDTH][.PREC][SIZE][TYPE] + -- + -- * FLAGS + -- + -- an optional sequence of characters which control output + -- justification, numeric signs, decimal points, trailing zeroes, and + -- octal and hex prefixes. The flag characters are minus (`-'), plus + -- (`+'), space ( ), zero (`0'), and sharp (`#'). They can appear in + -- any combination. + -- + -- `-' + -- The result of the conversion is left justified, and the right + -- is padded with blanks. If you do not use this flag, the + -- result is right justified, and padded on the left. + -- + -- `+' + -- The result of a signed conversion (as determined by TYPE) + -- will always begin with a plus or minus sign. (If you do not + -- use this flag, positive values do not begin with a plus sign.) + -- + -- `" " (space)' + -- If the first character of a signed conversion specification + -- is not a sign, or if a signed conversion results in no + -- characters, the result will begin with a space. If the space + -- ( ) flag and the plus (`+') flag both appear, the space flag + -- is ignored. + -- + -- `0' + -- If the TYPE character is `d', `i', `o', `u', `x', `X', `e', + -- `E', `f', `g', or `G': leading zeroes, are used to pad the + -- field width (following any indication of sign or base); no + -- spaces are used for padding. If the zero (`0') and minus + -- (`-') flags both appear, the zero (`0') flag will be ignored. + -- For `d', `i', `o', `u', `x', and `X' conversions, if a + -- precision PREC is specified, the zero (`0') flag is ignored. + -- Note that `0' is interpreted as a flag, not as the beginning + -- of a field width. + -- + -- `#' + -- The result is to be converted to an alternative form, + -- according to the next character: + -- + -- `0' + -- increases precision to force the first digit of the + -- result to be a zero. + -- + -- `x' + -- a non-zero result will have a `0x' prefix. + -- + -- `X' + -- a non-zero result will have a `0X' prefix. + -- + -- `e, E or f' + -- The result will always contain a decimal point even if + -- no digits follow the point. (Normally, a decimal point + -- appears only if a digit follows it.) Trailing zeroes + -- are removed. + -- + -- `g or G' + -- same as `e' or `E', but trailing zeroes are not removed. + -- + -- `all others' + -- undefined. + -- + -- * WIDTH + -- + -- WIDTH is an optional minimum field width. You can either specify + -- it directly as a decimal integer, or indirectly by using instead + -- an asterisk (`*'), in which case an `int' argument is used as the + -- field width. Negative field widths are not supported; if you + -- attempt to specify a negative field width, it is interpreted as a + -- minus (`-') flag followed by a positive field width. + -- + -- * PREC + -- + -- an optional field; if present, it is introduced with ``.'' (a + -- period). This field gives the maximum number of characters to + -- print in a conversion; the minimum number of digits of an integer + -- to print, for conversions with TYPE `d', `i', `o', `u', `x', and + -- `X'; the maximum number of significant digits, for the `g' and `G' + -- conversions; or the number of digits to print after the decimal + -- point, for `e', `E', and `f' conversions. You can specify the + -- precision either directly as a decimal integer or indirectly by + -- using an asterisk (`*'), in which case an `int' argument is used + -- as the precision. Supplying a negative precision is equivalent to + -- omitting the precision. If only a period is specified the + -- precision is zero. If a precision appears with any other + -- conversion TYPE than those listed here, the behavior is undefined. + -- + -- * SIZE + -- + -- `h', `l', and `L' are optional size characters which override the + -- default way that `printf' interprets the data type of the + -- corresponding argument. `h' forces the following `d', `i', `o', + -- `u', `x' or `X' conversion TYPE to apply to a `short' or `unsigned + -- short'. `h' also forces a following `n' TYPE to apply to a pointer + -- to a `short'. Similarily, an `l' forces the following `d', `i', + -- `o', `u', `x' or `X' conversion TYPE to apply to a `long' or + -- `unsigned long'. `l' also forces a following `n' TYPE to apply to + -- a pointer to a `long'. `l' with `c', `s' is equivalent to `C', + -- `S' respectively. If an `h' or an `l' appears with another + -- conversion specifier, the behavior is undefined. `L' forces a + -- following `e', `E', `f', `g' or `G' conversion TYPE to apply to a + -- `long double' argument. If `L' appears with any other conversion + -- TYPE, the behavior is undefined. + -- + -- * TYPE + -- + -- TYPE specifies what kind of conversion `printf' performs. Here is + -- a table of these: + -- + -- `%' + -- prints the percent character (`%') + -- + -- `c' + -- prints ARG as single character + -- + -- `C' + -- prints wchar_t ARG as single multibyte character + -- + -- `s' + -- prints characters until precision is reached or a null + -- terminator is encountered; takes a string pointer + -- + -- `S' + -- converts wchar_t characters to multibyte output characters + -- until precision is reached or a null wchar_t terminator is + -- encountered; takes a wchar_t pointer + -- + -- `d' + -- prints a signed decimal integer; takes an `int' (same as `i') + -- + -- `i' + -- prints a signed decimal integer; takes an `int' (same as `d') + -- + -- `o' + -- prints a signed octal integer; takes an `int' + -- + -- `u' + -- prints an unsigned decimal integer; takes an `int' + -- + -- `x' + -- prints an unsigned hexadecimal integer (using `abcdef' as + -- digits beyond `9'); takes an `int' + -- + -- `X' + -- prints an unsigned hexadecimal integer (using `ABCDEF' as + -- digits beyond `9'); takes an `int' + -- + -- `f' + -- prints a signed value of the form `[-]9999.9999'; takes a + -- floating-point number + -- + -- `e' + -- prints a signed value of the form + -- `[-]9.9999e[+|-]999'; takes a floating-point number + -- + -- `E' + -- prints the same way as `e', but using `E' to introduce the + -- exponent; takes a floating-point number + -- + -- `g' + -- prints a signed value in either `f' or `e' form, based on + -- given value and precision--trailing zeros and the decimal + -- point are printed only if necessary; takes a floating-point + -- number + -- + -- `G' + -- prints the same way as `g', but using `E' for the exponent if + -- an exponent is needed; takes a floating-point number + -- + -- `n' + -- stores (in the same object) a count of the characters written; + -- takes a pointer to `int' + -- + -- `p' + -- prints a pointer in an implementation-defined format. This + -- implementation treats the pointer as an `unsigned long' (same + -- as `Lu'). + ------------------------------------------------------------------------------ + + -- Conversion functions + function to_integer (value : in string) return integer; + + + + + procedure read_identifier(file f : char_file; value : inout string_ptr); + procedure read_integer(file f : char_file; value : out integer); + procedure find_token(file f : char_file; value : in string); + ------------------------------------------------------------------------------ + + + ------------------------------------------------------------------------------ + -- Working with commands: + ------------------------------------------------------------------------------ + -- First level of abstraction: tokens. + constant max_token_size : integer := 80; + type token_kind is + ( + name, + integer_number, + end_of_line, + end_of_file, + start_of_comment, + separator, + not_recognized + ); + + type token is record + kind : token_kind; + value_ptr : string_ptr; + end record; + + procedure read_token(file f : char_file; value : inout token); + procedure write_token(file f : char_file; value : inout token); + -- + + ------------------------------------------------------------------------------ + -- Second level of abstraction: commands. + -- Maximum number of arguments in a command: + constant max_args_in_command : integer := 4*1024; + + -- Command type: + type command is record + time_cnt : natural; -- The time, when the command should be applied + id : string_ptr; -- Pointer to the command ID. + arg : integer_array_ptr; -- Pointer to the array of arguments. + end record; + + procedure read_command(file f : char_file; id : in string; cmd : inout command); + + type command_list_elem; + type command_list_elem_ptr is access command_list_elem; + type command_list_elem is record + cmd : command; + prv : command_list_elem_ptr; + nxt : command_list_elem_ptr; + end record; + type command_list is record + number : natural; + first : command_list_elem_ptr; + last : command_list_elem_ptr; + end record; + procedure init_command_list(fname : in string; variable clist : inout command_list; block_id : in string); + procedure put_command(variable clist : inout command_list; cmd : inout command); + procedure get_command(variable clist : inout command_list; cmd : inout command); + ------------------------------------------------------------------------------ + +end test; +--============================================================================== + +--============================================================================== +package body test is + + constant hexadecimal_chars : string(1 to 32) := "0123456789abcdef0123456789ABCDEF"; + + ------------------------------------------------------------------------------ + function to_character(value : in std_logic) return character is + begin + case value is + when 'U' => return 'U'; + when 'X' => return 'X'; + when '0' => return '0'; + when '1' => return '1'; + when 'Z' => return 'Z'; + when 'W' => return 'W'; + when 'L' => return 'L'; + when 'H' => return 'H'; + when '-' => return '-'; + end case; + end function to_character; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + procedure fprint_string (file f : char_file; value : in string) is + begin + for i in value'low to value'high loop + write(f, value(i)); + end loop; + end procedure fprint_string; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + procedure print_string(value : in string) is + begin + fprint_string(stdout, value); + end procedure print_string; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + procedure read_integer(file f : char_file; value : out integer) is + variable buf : string(1 to 256); + variable ch0 : character; + variable idx : positive; + begin + -- Searching for first character: + while true loop + assert not(endfile(f)) report "read_integer(): Unexpected End Of File." severity failure; + read(f, ch0); + exit when ((ch0 >= '0')and(ch0 <= '9'))or(ch0 = '-'); + end loop; + + buf(1) := ch0; + idx := 2; + + -- Reading other characters: + while (not(endfile(f))) loop + read(f, ch0); + if ((ch0 >= '0')and(ch0 <= '9'))or((ch0 >= 'a')and(ch0 <= 'f'))or((ch0 >= 'A')and(ch0 <= 'F'))or(ch0 = 'x') then + buf(idx) := ch0; + idx := idx + 1; + else + exit; + end if; + end loop; + value := to_integer(buf(1 to idx - 1)); + end procedure read_integer; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + procedure read_identifier(file f : char_file; value : inout string_ptr) is + variable buf : string(1 to 256); + variable ch0 : character; + variable idx : positive; + begin + -- Searching for first character: + while true loop + assert not(endfile(f)) report "read_identifier(): Unexpected End Of File." severity failure; + read(f, ch0); + exit when ((ch0 >= 'A')and(ch0 <= 'Z'))or((ch0 >= 'a')and(ch0 <= 'z'))or(ch0 = '_'); + end loop; + + buf(1) := ch0; + idx := 2; + + -- Reading other characters: + while (not(endfile(f))) loop + read(f, ch0); + if ((ch0 >= 'A')and(ch0 <= 'Z'))or((ch0 >= 'a')and(ch0 <= 'z'))or((ch0 >= '0')and(ch0 <= '9'))or(ch0 = '_') then + buf(idx) := ch0; + idx := idx + 1; + else + exit; + end if; + end loop; + deallocate(value); + value := new string'(buf(1 to idx - 1)); + end procedure read_identifier; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + procedure find_token(file f : char_file; value : in string) is + variable ch0 : character; + variable idx : positive; + begin + idx := value'low; + while true loop + assert not(endfile(f)) report "find_token(" & value & "): Unexpected End Of File." severity failure; + read(f, ch0); + if (ch0 = value(idx)) then + exit when (idx = value'high); + idx := idx + 1; + else + idx := value'low; + end if; + end loop; + end procedure find_token; + ------------------------------------------------------------------------------ + + + ------------------------------------------------------------------------------ + function to_integer(value : in string) return integer is + variable value_local : integer := 0; + variable start_idx : positive; + variable negative : boolean; + begin + if (value'right > 2)and(value(1) = '0')and(value(2) = 'x') then -- hex format + start_idx := 3; + + for i in start_idx to value'right loop + if (value(i) >= 'a')and(value(i) <= 'f') then + value_local := (16 * value_local) + (character'pos(value(i)) - character'pos('a') + 10); + elsif (value(i) >= 'A')and(value(i) <= 'F') then + value_local := (16 * value_local) + (character'pos(value(i)) - character'pos('A') + 10); + else + value_local := (16 * value_local) + (character'pos(value(i)) - character'pos('0')); + end if; + end loop; + else + if (value(1) = '-') then + negative := true; + start_idx := 2; + else + negative := false; + start_idx := 1; + end if; + + for i in start_idx to value'right loop + value_local := (10 * value_local) + (character'pos(value(i)) - character'pos('0')); + end loop; + + if (negative) then + value_local := (-1) * value_local; + end if; + end if; + + return value_local; + end function to_integer; + ------------------------------------------------------------------------------ + + --function to_string(value : in integer; width : in positive := 1) return string is + -- variable idx : positive; + -- variable buf : string(1 to 80); + -- variable negative : boolean := (value < 0); + -- variable value_local : integer := abs(value); + --begin + -- idx := 80; + + -- if (value_local = 0) then + -- buf(idx) := '0'; + -- idx := idx - 1; + -- end if; + + -- while (value_local /= 0) loop + -- buf(idx) := character'val((value_local rem 10) + character'pos('0')); + -- value_local := value_local / 10; + -- idx := idx - 1; + -- end loop; + + -- if (negative) then + -- buf(idx) := '-'; + -- idx := idx - 1; + -- end if; + + -- while ((80 - idx) < width) loop + -- buf(idx) := ' '; + -- idx := idx - 1; + -- end loop; + + -- buf(1 to (80 - idx)) := buf((1 + idx) to 80); + + -- return buf(1 to (80 - idx)); + --end function to_string; + + --function to_string(value : in std_logic_vector) return string is + -- variable res_string : string((((value'length + 3)/4) + 2) downto 1); + -- variable res_idx : positive; + -- variable hex_digit : integer; + --begin + + -- hex_digit := 0; + -- res_idx := 1; + -- for idx in value'right to value'left loop + -- if (value(idx) = '1') then + -- hex_digit := hex_digit + 2**((idx - value'right) rem 4); + -- elsif (value(idx) /= '0') then + -- hex_digit := hex_digit + 100; + -- end if; + -- if (((idx - value'right) rem 4) = 3)or(idx = value'left) then + -- case hex_digit is + -- when 0 => res_string(res_idx) := '0'; + -- when 1 => res_string(res_idx) := '1'; + -- when 2 => res_string(res_idx) := '2'; + -- when 3 => res_string(res_idx) := '3'; + -- when 4 => res_string(res_idx) := '4'; + -- when 5 => res_string(res_idx) := '5'; + -- when 6 => res_string(res_idx) := '6'; + -- when 7 => res_string(res_idx) := '7'; + -- when 8 => res_string(res_idx) := '8'; + -- when 9 => res_string(res_idx) := '9'; + -- when 10 => res_string(res_idx) := 'A'; + -- when 11 => res_string(res_idx) := 'B'; + -- when 12 => res_string(res_idx) := 'C'; + -- when 13 => res_string(res_idx) := 'D'; + -- when 14 => res_string(res_idx) := 'E'; + -- when 15 => res_string(res_idx) := 'F'; + -- when others => res_string(res_idx) := 'X'; + -- end case; + -- hex_digit := 0; + -- res_idx := res_idx + 1; + -- end if; + -- end loop; + -- res_string(res_string'left) := '0'; + -- res_string(res_string'left - 1) := 'x'; + + -- return res_string; + --end function to_string; + + + ------------------------------------------------------------------------------ + -- Working with commands: + ------------------------------------------------------------------------------ + -- First level of abstraction: tokens. + procedure read_token(file f : char_file; value : inout token) is + variable ch0 : character; + variable idx : integer := 1; + variable end_of_token : boolean := false; + variable buf : string(1 to max_token_size); + variable kind : token_kind; + begin + deallocate(value.value_ptr); + while (idx <= max_token_size)and(end_of_token = false) loop + if (idx = 1) then + if endfile(f) then + kind := end_of_file; + end_of_token := true; + else + read(f, ch0); + next when (ch0 = ' ')or(ch0 = ht); + buf(idx) := ch0; + idx := idx + 1; + + if (ch0 = '#') then + kind := start_of_comment; + end_of_token := true; + elsif ((ch0 >= '0')and(ch0 <= '9'))or(ch0 = '-') then + kind := integer_number; + elsif ((ch0 >= 'A')and(ch0 <= 'Z'))or((ch0 >= 'a')and(ch0 <= 'z'))or(ch0 = '_') then + kind := name; + elsif (ch0 = cr) then + kind := end_of_line; + elsif (ch0 = lf) then + kind := end_of_line; + end_of_token := true; + elsif (ch0 = ',')or(ch0 = '(')or(ch0 = ')')or(ch0 = '{')or(ch0 = '}')or(ch0 = ':') then + kind := separator; + end_of_token := true; + else + kind := not_recognized; + end_of_token := true; + end if; + end if; + else + if endfile(f) then + end_of_token := true; + else + read(f, ch0); + case kind is + when integer_number => + if ((ch0 >= '0')and(ch0 <= '9'))or((ch0 >= 'a')and(ch0 <= 'f'))or((ch0 >= 'A')and(ch0 <= 'F'))or(ch0 = 'x') then + buf(idx) := ch0; + idx := idx + 1; + else + end_of_token := true; + end if; + when name => + if ((ch0 >= 'A')and(ch0 <= 'Z'))or((ch0 >= 'a')and(ch0 <= 'z'))or((ch0 >= '0')and(ch0 <= '9'))or(ch0 = '_') then + buf(idx) := ch0; + idx := idx + 1; + else + end_of_token := true; + end if; + when end_of_line => + if (ch0 = lf) then + buf(idx) := ch0; + idx := idx + 1; + end if; + end_of_token := true; + when others => + end_of_token := true; + end case; + end if; + end if; + end loop; + + value.kind := kind; + value.value_ptr := new string'(buf(1 to idx - 1)); + end procedure read_token; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + procedure write_token(file f : char_file; value : inout token) is + begin + fprint_string(f, value.value_ptr.all & ' '); + end procedure write_token; + ------------------------------------------------------------------------------ + -- + + ------------------------------------------------------------------------------ + -- Second level of abstraction: commands. + -- <{> ... <}> + procedure read_command(file f : char_file; id : in string; cmd : inout command) is + variable tmp_token : token; + variable token_idx : integer := 1; + variable arg_idx : integer := 1; + variable tmp_array : integer_array(1 to max_args_in_command); + begin + while true loop + read_token(f, tmp_token); + + case tmp_token.kind is + when name => + assert (token_idx /= 1) report "read_command(): identifier " & + tmp_token.value_ptr.all & " found where should be an integer number." severity failure; + assert (token_idx /= 4) report "read_command(): identifier " & + tmp_token.value_ptr.all & " found where should be an { brace." severity failure; + assert (token_idx /= 5) report "read_command(): identifier " & + tmp_token.value_ptr.all & " found where should be an } brace or an integer number." severity failure; + if (token_idx = 2) then + if (tmp_token.value_ptr.all /= id) then -- Not our command, go to the end. + while true loop + read_token(f, tmp_token); + exit when (tmp_token.kind = separator)or(tmp_token.value_ptr.all = "}"); + end loop; + token_idx := 1; + else + token_idx := 3; + end if; + else + deallocate(cmd.id); + cmd.id := new string'(tmp_token.value_ptr.all); + token_idx := 4; + end if; + + when integer_number => + assert (token_idx /= 2) report "read_command(): integer number " & + tmp_token.value_ptr.all & " found where should be an identifier." severity failure; + assert (token_idx /= 3) report "read_command(): integer number " & + tmp_token.value_ptr.all & " found where should be an identifier." severity failure; + assert (token_idx /= 4) report "read_command(): integer number " & + tmp_token.value_ptr.all & " found where should be an { brace." severity failure; + if (token_idx = 1) then + cmd.time_cnt := to_integer(tmp_token.value_ptr.all); + token_idx := 2; + else + tmp_array(arg_idx) := to_integer(tmp_token.value_ptr.all); + arg_idx := arg_idx + 1; + end if; + + when end_of_line => + null; + + when end_of_file => + exit; + + when start_of_comment => + while true loop + read_token(f, tmp_token); + exit when (tmp_token.kind = end_of_line)or(tmp_token.kind = end_of_file); + end loop; + + when separator => + if (token_idx = 4)and(tmp_token.value_ptr.all = "{") then + token_idx := 5; + elsif (token_idx = 5)and(tmp_token.value_ptr.all = "}") then + token_idx := 6; + exit; + end if; + + when not_recognized => + assert false report "read_command(): unknown pattern " & tmp_token.value_ptr.all & " found." severity failure; + end case; + end loop; + + assert (token_idx = 1)or(token_idx = 6) report "read_command(): Unexpected End of File." severity failure; + + if (token_idx = 1) then + cmd.time_cnt := 0; + deallocate(cmd.id); + cmd.id := new string'("stop"); + deallocate(cmd.arg); + else + deallocate(cmd.arg); + cmd.arg := new integer_array'(tmp_array(1 to arg_idx - 1)); + end if; + end procedure read_command; + ------------------------------------------------------------------------------ + + + ------------------------------------------------------------------------------ + procedure put_command(variable clist : inout command_list; cmd : inout command) is + variable new_le : command_list_elem_ptr; + variable tmp : command_list_elem_ptr; + begin + new_le := new command_list_elem; + new_le.all.cmd.time_cnt := cmd.time_cnt; + new_le.all.cmd.id := new string'(cmd.id.all); + new_le.all.cmd.arg := new integer_array'(cmd.arg.all); + + if (clist.number = 0) then + -- The command list is empty. + new_le.all.prv := null; + new_le.all.nxt := null; + clist.first := new_le; + clist.last := new_le; + else + -- The command list is not empty. + new_le.all.prv := clist.last; + new_le.all.nxt := null; + clist.last.all.nxt := new_le; + clist.last := new_le; + end if; + clist.number := clist.number + 1; + end procedure put_command; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + procedure init_command_list(fname : in string; variable clist : inout command_list; block_id : in string) is + file cmd_data : char_file; + variable cmd : command; + begin + file_open(cmd_data, fname, read_mode); + + clist.number := 0; + clist.first := null; + clist.last := null; + + while (true) loop + read_command(cmd_data, block_id, cmd); + exit when (cmd.id.all = "stop"); + put_command(clist, cmd); + end loop; + + deallocate(cmd.id); + deallocate(cmd.arg); + file_close(cmd_data); + end procedure init_command_list; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + procedure get_command(variable clist : inout command_list; cmd : inout command) is + variable old_el : command_list_elem_ptr; + begin + deallocate(cmd.id); + deallocate(cmd.arg); + if (clist.number = 0) then + cmd.time_cnt := 0; + cmd.id := new string'("stop"); + else + if (clist.number = 1) then + old_el := clist.first; + clist.number := clist.number - 1; + clist.first := null; + clist.last := null; + else + old_el := clist.first; + clist.number := clist.number - 1; + clist.first := clist.first.all.nxt; + old_el.all.nxt.all.prv := null; + end if; + cmd.time_cnt := old_el.all.cmd.time_cnt; + cmd.id := new string'(old_el.all.cmd.id.all); + cmd.arg := new integer_array'(old_el.all.cmd.arg.all); + deallocate(old_el.all.cmd.id); + deallocate(old_el.all.cmd.arg); + deallocate(old_el); + end if; + end procedure get_command; + ------------------------------------------------------------------------------ + + + + + ------------------------------------------------------------------------------ + function to_string(value : in std_logic; + format : in string := "b"; + width : in natural := 0; + prec : in natural := 0) return string is + begin + return to_string("" & value, format, width, prec); + end function to_string; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + function sel(arg0 : boolean; arg1 : integer; arg2 : integer) return integer is + begin + if (arg0) then return arg1; else return arg2; end if; + end function sel; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + function sel(arg0 : boolean; arg1 : std_logic; arg2 : std_logic) return std_logic is + begin + if (arg0) then return arg1; else return arg2; end if; + end function sel; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + function sel(arg0 : boolean; arg1 : character; arg2 : character) return character is + begin + if (arg0) then return arg1; else return arg2; end if; + end function sel; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + function max(arg0 : integer; arg1 : integer) return integer is + begin + return sel(arg0 > arg1, arg0, arg1); + end function max; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + function signed_num_bits(arg : integer) return positive is + variable nbits : natural := 1; + variable n : natural := sel(arg < 0, -(arg + 1), arg); + begin + while (n > 0) loop + nbits := nbits + 1; + n := n / 2; + end loop; + return nbits; + end function signed_num_bits; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + function to_string(value : in integer; + format : in string := "d"; + width : in natural := 0; + prec : in natural := 0) return string is + variable tmp : std_logic_vector(signed_num_bits(integer'high) - 1 downto 0); + variable negative : std_logic := sel(value < 0, '1', '0'); + variable n : natural := sel(value < 0, -(value + 1), value); + begin + for i in tmp'right to tmp'left loop + tmp(i) := sel(((n mod 2) = 0), negative, not(negative)); + n := n / 2; + end loop; + return to_string(tmp, format, width, prec); + end function to_string; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + function to_string(value : in std_logic_vector; + format : in string := "x"; + width : in natural := 0; + prec : in natural := 0) return string is + -- Flags: + variable minus_flag : boolean := false; + variable plus_flag : boolean := false; + variable space_flag : boolean := false; + variable zero_flag : boolean := false; + variable sharp_flag : boolean := false; + -- Width: + variable width_local : natural := 0; + -- Precision: + variable prec_local : natural := 0; + -- Conversion Type: + type conversion_type_type is (unsigned_binary, signed_decimal, unsigned_octal, unsigned_decimal, unsigned_hexadecimal_0, unsigned_hexadecimal_1); + variable type_local : conversion_type_type := signed_decimal; + -- + -- + variable value_local : std_logic_vector(value'length - 1 downto 0); + variable idx : integer; + variable number_buffer : string(1 to value'length); + variable sign_buffer : string(1 to 2); + variable result_ptr : string_ptr; + -- + variable space_padding_0 : integer; + variable sign_chars : integer; + variable zero_padding : integer; + variable number_chars : integer; + variable space_padding_1 : integer; + begin + idx := format'low; + + -- Parse format string: + ---- Read flags: + while (true) loop + case format(idx) is + when '-' => + if (minus_flag) then report "'-' flag was aready set before" severity warning; else minus_flag := true; end if; + when '+' => + if (plus_flag ) then report "'+' flag was aready set before" severity warning; else plus_flag := true; end if; + when ' ' => + if (space_flag) then report "' ' flag was aready set before" severity warning; else space_flag := true; end if; + when '0' => + if (zero_flag ) then report "'0' flag was aready set before" severity warning; else zero_flag := true; end if; + when '#' => + if (sharp_flag) then report "'#' flag was aready set before" severity warning; else sharp_flag := true; end if; + when others => exit; + end case; + if (idx < format'high) then idx := idx + 1; else report "Unexpected end of format string." severity error; end if; + end loop; + + if (space_flag and plus_flag) then + report "' ' flag is ignored due to presence of '+' flag" severity warning; + space_flag := false; + end if; + + if (minus_flag and zero_flag) then + report "'0' flag is ignored due to presence of '-' flag" severity warning; + zero_flag := false; + end if; + + ---- Read width: + if (format(idx) = '*') then + width_local := width; + if (idx < format'high) then idx := idx + 1; else report "Unexpected end of format string." severity error; end if; + else + while (true) loop + case format(idx) is + when '0' | '1' | '2' | '3' | '4' | '5' | '6' | '7' | '8' | '9' => + width_local := (width_local * 10) + (character'pos(format(idx)) - character'pos('0')); + if (idx < format'high) then idx := idx + 1; else report "Unexpected end of format string." severity error; end if; + when others => exit; + end case; + end loop; + end if; + + ---- Read precision: + if (format(idx) = '.') then + prec_local := 0; + if (zero_flag) then + report "'0' flag is ignored due to presence of PREC field" severity warning; + zero_flag := false; + end if; + if (idx < format'high) then idx := idx + 1; else report "Unexpected end of format string." severity error; end if; + if (format(idx) = '*') then + prec_local := prec; + if (idx < format'high) then idx := idx + 1; else report "Unexpected end of format string." severity error; end if; + else + while (true) loop + case format(idx) is + when '0' | '1' | '2' | '3' | '4' | '5' | '6' | '7' | '8' | '9' => + prec_local := (prec_local * 10) + (character'pos(format(idx)) - character'pos('0')); + if (idx < format'high) then idx := idx + 1; else report "Unexpected end of format string." severity error; end if; + when others => exit; + end case; + end loop; + end if; + end if; + + ---- Read type: + case format(idx) is + when 'b' => + type_local := unsigned_binary; + when 'd' | 'i' => + type_local := signed_decimal; + if (sharp_flag) then + report "'#' flag is ignored due to signed decimal conversion type" severity warning; + sharp_flag := false; + end if; + when 'o' => + type_local := unsigned_octal; + when 'u' => + type_local := unsigned_decimal; + if (sharp_flag) then + report "'#' flag is ignored due to unsigned decimal conversion type" severity warning; + sharp_flag := false; + end if; + when 'x' => + type_local := unsigned_hexadecimal_0; + when 'X' => + type_local := unsigned_hexadecimal_1; + when others => + report "Unknown conversion type character: " & format(idx) severity error; + type_local := signed_decimal; + end case; + assert (idx = format'high) report "Extra characters in format string" severity warning; + + ---- Obtain number string: + case type_local is + when unsigned_binary => + -- Fill number buffer: + value_local := value; + idx := 1; + + while (true) loop + number_buffer(idx) := to_character(value_local(0)); + value_local := '0' & value_local(value_local'high downto 1); + idx := idx + 1; + exit when (value_local = (value_local'range => '0')); + end loop; + + -- Fill sign buffer: + if (sharp_flag) then + sign_chars := 1; + sign_buffer(1) := 'b'; + else + sign_chars := 0; + end if; + + when signed_decimal => + -- Fill number buffer: + value_local := std_logic_vector(abs(signed(value))); + idx := 1; + + while (true) loop + number_buffer(idx) := hexadecimal_chars(to_integer(unsigned(value_local) rem 10) + 1); + value_local := std_logic_vector(unsigned(value_local) / 10); + idx := idx + 1; + exit when (value_local = (value_local'range => '0')); + end loop; + + -- Fill sign buffer: + if (signed(value) < 0) then + sign_buffer(1) := '-'; + elsif (plus_flag) then + sign_buffer(1) := '+'; + else + sign_buffer(1) := ' '; + end if; + sign_chars := sel(signed(value) < 0, 1, sel(plus_flag or space_flag, 1, 0)); + + when unsigned_octal => + -- Fill number buffer: + value_local := value; + idx := 1; + + while (true) loop + number_buffer(idx) := hexadecimal_chars(to_integer(unsigned(value_local) rem 8) + 1); + value_local := std_logic_vector(unsigned(value_local) / 8); + idx := idx + 1; + exit when (value_local = (value_local'range => '0')); + end loop; + + -- Fill sign buffer: + sign_chars := 0; + prec_local := sel(sharp_flag and (prec_local < idx), idx, prec_local); + + when unsigned_decimal => + -- Fill number buffer: + value_local := value; + idx := 1; + + while (true) loop + number_buffer(idx) := hexadecimal_chars(to_integer(unsigned(value_local) rem 10) + 1); + value_local := std_logic_vector(unsigned(value_local) / 10); + idx := idx + 1; + exit when (value_local = (value_local'range => '0')); + end loop; + + -- Fill sign buffer: + sign_chars := 0; + + when unsigned_hexadecimal_0 | unsigned_hexadecimal_1 => + -- Fill number buffer: + value_local := value; + idx := 1; + + while (true) loop + number_buffer(idx) := hexadecimal_chars(to_integer(unsigned(value_local) rem 16) + sel(type_local = unsigned_hexadecimal_0, 1, 17)); + value_local := std_logic_vector(unsigned(value_local) / 16); + idx := idx + 1; + exit when (value_local = (value_local'range => '0')); + end loop; + + -- Fill sign buffer: + if (sharp_flag) then + sign_chars := 2; + sign_buffer(1) := '0'; + sign_buffer(2) := sel(type_local = unsigned_hexadecimal_0, 'x', 'X'); + else + sign_chars := 0; + end if; + + end case; + + -- + number_chars := idx - 1; + zero_padding := max(prec_local - number_chars, 0); + space_padding_0 := sel(minus_flag, 0, max(width_local - (sign_chars + zero_padding + number_chars), 0)); + space_padding_1 := sel(minus_flag, max(width_local - (sign_chars + zero_padding + number_chars), 0), 0); + + -- + result_ptr := new string(1 to space_padding_0 + sign_chars + zero_padding + number_chars + space_padding_1); + + -- fill the space padding 0: + for i in 1 to space_padding_0 loop + result_ptr.all(i) := ' '; + end loop; + -- put sign chars: + for i in 1 to sign_chars loop + result_ptr.all(space_padding_0 + i) := sign_buffer(i); + end loop; + -- fill zero poadding: + for i in 1 to zero_padding loop + result_ptr.all(space_padding_0 + sign_chars + i) := '0'; + end loop; + -- put number chars: + for i in 1 to number_chars loop + result_ptr.all(space_padding_0 + sign_chars + zero_padding + i) := number_buffer(idx - i); + end loop; + -- fill the space padding 1: + for i in 1 to space_padding_1 loop + result_ptr.all(space_padding_0 + sign_chars + zero_padding + number_chars + i) := ' '; + end loop; + + return result_ptr.all; + + end function to_string; + ------------------------------------------------------------------------------ + +end test; +--============================================================================== +

trunk/src_tb/test.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src_tb/wire_mdl.vhd =================================================================== --- trunk/src_tb/wire_mdl.vhd (nonexistent) +++ trunk/src_tb/wire_mdl.vhd (revision 2) @@ -0,0 +1,119 @@ + +--============================================================================== +-- | +-- Project: IIC Multiple Bus Controller (IICMB) | +-- | +-- Module: Wire model. | +-- Version: | +-- 1.0, April 29, 2016 | +-- | +-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | +-- | +--============================================================================== +--============================================================================== +-- Copyright (c) 2016, Sergey Shuvalkin | +-- All rights reserved. | +-- | +-- Redistribution and use in source and binary forms, with or without | +-- modification, are permitted provided that the following conditions are met: | +-- | +-- 1. Redistributions of source code must retain the above copyright notice, | +-- this list of conditions and the following disclaimer. | +-- 2. Redistributions in binary form must reproduce the above copyright | +-- notice, this list of conditions and the following disclaimer in the | +-- documentation and/or other materials provided with the distribution. | +-- | +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | +-- POSSIBILITY OF SUCH DAMAGE. | +--============================================================================== + + +library ieee; +use ieee.math_real.uniform; +use ieee.math_real.exp; + + +--============================================================================== +entity wire_mdl is + generic + ( + g_resistance_0 : real := 1.0; -- In Ohms + g_resistance_1 : real := 1.0; -- In Ohms + g_capacitance : real := 1.0; -- In pF + g_initial_level : bit := '0' + ); + port + ( + sig_in : in bit; + sig_out : out real; + sig_out_l : out bit + ); +end entity wire_mdl; +--============================================================================== + +--============================================================================== +architecture beh of wire_mdl is + + -- We use picoseconds and picofarads in calculations + constant c_time_delta : time := 2011 ps; + constant c_time_delta_real : real := real(c_time_delta / 1 ps); + + function to_real(a : bit) return real is + begin + if (a = '0') then + return 0.0; + else + return 1.0; + end if; + end function to_real; + + signal u_c : real := to_real(g_initial_level); -- current voltage + +begin + + ------------------------------------------------------------------------------ + sig_out_proc: + process + variable v_target : real; + variable v_resistance : real; + variable seed_0 : positive := 1137938; + variable seed_1 : positive := 1010110111; + variable random_value : real; + begin + -- Get target voltage + v_target := to_real(sig_in); + + -- Get resistance, depending on target voltage + if (sig_in = '1') then + v_resistance := g_resistance_1; + else + v_resistance := g_resistance_0; + end if; + + -- Calculate next voltage level: + u_c <= v_target - (v_target - u_c)*exp((-c_time_delta_real)/(g_capacitance * v_resistance)); + + ieee.math_real.uniform(seed_0, seed_1, random_value); + if (u_c >= random_value) then + sig_out_l <= '1'; + else + sig_out_l <= '0'; + end if; + wait for c_time_delta; + end process sig_out_proc; + ------------------------------------------------------------------------------ + + sig_out <= u_c; + +end architecture beh; +--============================================================================== +

trunk/src_tb/wire_mdl.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src_tb/iicmb_m_tb.vhd =================================================================== --- trunk/src_tb/iicmb_m_tb.vhd (nonexistent) +++ trunk/src_tb/iicmb_m_tb.vhd (revision 2) @@ -0,0 +1,308 @@ + +--============================================================================== +-- | +-- Project: IIC Multiple Bus Controller (IICMB) | +-- | +-- Module: Testbench for 'iicmb_m'. | +-- Version: | +-- 1.0, April 29, 2016 | +-- | +-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | +-- | +--============================================================================== +--============================================================================== +-- Copyright (c) 2016, Sergey Shuvalkin | +-- All rights reserved. | +-- | +-- Redistribution and use in source and binary forms, with or without | +-- modification, are permitted provided that the following conditions are met: | +-- | +-- 1. Redistributions of source code must retain the above copyright notice, | +-- this list of conditions and the following disclaimer. | +-- 2. Redistributions in binary form must reproduce the above copyright | +-- notice, this list of conditions and the following disclaimer in the | +-- documentation and/or other materials provided with the distribution. | +-- | +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | +-- POSSIBILITY OF SUCH DAMAGE. | +--============================================================================== + + +library ieee; +use ieee.std_logic_1164.all; + +library iicmb; +use iicmb.iicmb_pkg.all; + +use work.test.all; + + +--============================================================================== +entity iicmb_m_tb is +end entity iicmb_m_tb; +--============================================================================== + +--============================================================================== +architecture beh of iicmb_m_tb is + + constant c_f_clk : real := 100000.0; -- in kHz + constant c_f_scl_0 : real := 100.0; -- in kHz + constant c_f_scl_1 : real := 100.0; -- in kHz + constant c_f_scl_2 : real := 100.0; -- in kHz + constant c_f_scl_3 : real := 100.0; -- in kHz + constant c_p_clk : time := integer(1000000000.0/c_f_clk) * 1 ps; + + constant c_bus_num : positive := 1; + + ------------------------------------------------------------------------------ + component iicmb_m is + generic + ( + g_bus_num : positive range 1 to 16 := 1; + g_f_clk : real := 100000.0; + g_f_scl_0 : real := 100.0; + g_f_scl_1 : real := 100.0; + g_f_scl_2 : real := 100.0; + g_f_scl_3 : real := 100.0; + g_f_scl_4 : real := 100.0; + g_f_scl_5 : real := 100.0; + g_f_scl_6 : real := 100.0; + g_f_scl_7 : real := 100.0; + g_f_scl_8 : real := 100.0; + g_f_scl_9 : real := 100.0; + g_f_scl_a : real := 100.0; + g_f_scl_b : real := 100.0; + g_f_scl_c : real := 100.0; + g_f_scl_d : real := 100.0; + g_f_scl_e : real := 100.0; + g_f_scl_f : real := 100.0 + ); + port + ( + clk : in std_logic; + s_rst : in std_logic; + busy : out std_logic; + captured : out std_logic; + bus_id : out std_logic_vector(3 downto 0); + bit_state : out std_logic_vector(3 downto 0); + byte_state : out std_logic_vector(3 downto 0); + mcmd_wr : in std_logic; + mcmd_id : in std_logic_vector(2 downto 0); + mcmd_data : in std_logic_vector(7 downto 0); + mrsp_wr : out std_logic; + mrsp_id : out std_logic_vector(2 downto 0); + mrsp_data : out std_logic_vector(7 downto 0); + scl_i : in std_logic_vector(0 to g_bus_num - 1); + sda_i : in std_logic_vector(0 to g_bus_num - 1); + scl_o : out std_logic_vector(0 to g_bus_num - 1); + sda_o : out std_logic_vector(0 to g_bus_num - 1) + ); + end component iicmb_m; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + component wire_mdl is + generic + ( + g_resistance_0 : real := 1.0; -- In Ohms + g_resistance_1 : real := 1.0; -- In Ohms + g_capacitance : real := 1.0; -- In pF + g_initial_level : bit := '0' + ); + port + ( + sig_in : in bit; + sig_out : out real; + sig_out_l : out bit + ); + end component wire_mdl; + ------------------------------------------------------------------------------ + + signal clk : std_logic := '0'; + signal s_rst : std_logic := '1'; + + signal busy : std_logic; + signal captured : std_logic; + signal bus_id : std_logic_vector(3 downto 0); + signal bit_state : std_logic_vector(3 downto 0); + signal byte_state : std_logic_vector(3 downto 0); + signal mcmd_wr : std_logic; + signal mcmd_id : std_logic_vector(2 downto 0); + signal mcmd_data : std_logic_vector(7 downto 0); + signal mrsp_wr : std_logic; + signal mrsp_id : std_logic_vector(2 downto 0); + signal mrsp_data : std_logic_vector(7 downto 0); + signal scl_o : std_logic_vector(0 to c_bus_num - 1); + signal scl : std_logic_vector(0 to c_bus_num - 1); + signal sda_o : std_logic_vector(0 to c_bus_num - 1); + signal sda : std_logic_vector(0 to c_bus_num - 1); + + type real_vector is array (natural range <>) of real; + signal scl_real : real_vector(0 to c_bus_num - 1); + signal sda_real : real_vector(0 to c_bus_num - 1); + signal scl_quant : bit_vector(0 to c_bus_num - 1); + signal sda_quant : bit_vector(0 to c_bus_num - 1); + signal scl_nquant : bit_vector(0 to c_bus_num - 1); + signal sda_nquant : bit_vector(0 to c_bus_num - 1); + +begin + + clk <= not(clk) after c_p_clk / 2; + s_rst <= '1', '0' after 113 ns; + + ------------------------------------------------------------------------------ + process + procedure issue_command(a : std_logic_vector(2 downto 0)) is + begin + mcmd_wr <= '1'; + mcmd_id <= a; + wait until rising_edge(clk); + mcmd_wr <= '0'; + wait until rising_edge(clk)and(mrsp_wr = '1'); + end procedure issue_command; + procedure send_byte(a : std_logic_vector(7 downto 0)) is + begin + mcmd_wr <= '1'; + mcmd_id <= mcmd_write; + mcmd_data <= a; + wait until rising_edge(clk); + mcmd_wr <= '0'; + wait until rising_edge(clk)and(mrsp_wr = '1'); + end procedure send_byte; + begin + -- Initial delay: + mcmd_wr <= '0'; + mcmd_id <= mcmd_set_bus; + mcmd_data <= (others => '0'); + wait for 20000 ns; + + -- + issue_command(mcmd_start); + send_byte(x"5A"); + issue_command(mcmd_start); + send_byte(x"AA"); + issue_command(mcmd_read_ack); + issue_command(mcmd_read_nak); + issue_command(mcmd_stop); + + -- Halt: + mcmd_wr <= '0'; + mcmd_id <= mcmd_set_bus; + mcmd_data <= (others => '0'); + wait; + end process; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + dut : iicmb_m + generic map + ( + g_bus_num => c_bus_num, + g_f_clk => c_f_clk, + g_f_scl_0 => c_f_scl_0, + g_f_scl_1 => c_f_scl_1, + g_f_scl_2 => c_f_scl_2, + g_f_scl_3 => c_f_scl_3 + ) + port map + ( + clk => clk, + s_rst => s_rst, + busy => busy, + captured => captured, + bus_id => bus_id, + bit_state => bit_state, + byte_state => byte_state, + mcmd_wr => mcmd_wr, + mcmd_id => mcmd_id, + mcmd_data => mcmd_data, + mrsp_wr => mrsp_wr, + mrsp_id => mrsp_id, + mrsp_data => mrsp_data, + scl_i => to_stdlogicvector(scl_quant), + sda_i => to_stdlogicvector(sda_quant), + scl_o => scl_o, + sda_o => sda_o + ); + ------------------------------------------------------------------------------ + + --**************************************************************************** + bus_gen: + for i in 0 to c_bus_num - 1 generate + scl(i) <= '0' when (scl_o(i) = '0') else 'Z'; + sda(i) <= '0' when (sda_o(i) = '0') else 'Z'; + + ---------------------------------------------------------------------------- + wire_mdl_inst_0 : wire_mdl + generic map + ( + g_resistance_0 => 40.0, + g_resistance_1 => 4000.0, + g_capacitance => 200.0, -- In pF + g_initial_level => '1' + ) + port map + ( + sig_in => scl_nquant(i), + sig_out => scl_real(i), + sig_out_l => scl_quant(i) + ); + ---------------------------------------------------------------------------- + + ---------------------------------------------------------------------------- + wire_mdl_inst_1 : wire_mdl + generic map + ( + g_resistance_0 => 40.0, + g_resistance_1 => 4000.0, + g_capacitance => 200.0, -- In pF + g_initial_level => '1' + ) + port map + ( + sig_in => sda_nquant(i), + sig_out => sda_real(i), + sig_out_l => sda_quant(i) + ); + ---------------------------------------------------------------------------- + end generate bus_gen; + --**************************************************************************** + + scl <= (others => 'H'); -- Pull up + sda <= (others => 'H'); -- Pull up + + scl_nquant <= to_bitvector(to_x01(scl)); + sda_nquant <= to_bitvector(to_x01(sda)); + + ------------------------------------------------------------------------------ + process(clk) + begin + if rising_edge(clk) then + if (s_rst = '1') then + else + if (mrsp_wr = '1') then + case (mrsp_id) is + when mrsp_done => print_string("Response: Done" & newline); + when mrsp_nak => print_string("Response: Nak" & newline); + when mrsp_arb_lost => print_string("Response: Arbitration lost" & newline); + when mrsp_error => print_string("Response: Error" & newline); + when mrsp_byte => print_string("Response: Byte received: " & "0x" & to_string(mrsp_data, "X") & newline); + when others => print_string("Undefined response!!!" & newline); + end case; + end if; + end if; + end if; + end process; + +end architecture beh; +--============================================================================== +

trunk/src_tb/iicmb_m_tb.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src_tb/iicmb_m_sq_tb.vhd =================================================================== --- trunk/src_tb/iicmb_m_sq_tb.vhd (nonexistent) +++ trunk/src_tb/iicmb_m_sq_tb.vhd (revision 2) @@ -0,0 +1,286 @@ + +--============================================================================== +-- | +-- Project: IIC Multiple Bus Controller (IICMB) | +-- | +-- Module: Testbench for 'iicmb_m_sq'. | +-- Version: | +-- 1.0, April 29, 2016 | +-- | +-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | +-- | +--============================================================================== +--============================================================================== +-- Copyright (c) 2016, Sergey Shuvalkin | +-- All rights reserved. | +-- | +-- Redistribution and use in source and binary forms, with or without | +-- modification, are permitted provided that the following conditions are met: | +-- | +-- 1. Redistributions of source code must retain the above copyright notice, | +-- this list of conditions and the following disclaimer. | +-- 2. Redistributions in binary form must reproduce the above copyright | +-- notice, this list of conditions and the following disclaimer in the | +-- documentation and/or other materials provided with the distribution. | +-- | +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | +-- POSSIBILITY OF SUCH DAMAGE. | +--============================================================================== + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library iicmb; +use iicmb.iicmb_pkg.all; + +use work.test.all; + + +--============================================================================== +entity iicmb_m_sq_tb is +end entity iicmb_m_sq_tb; +--============================================================================== + +--============================================================================== +architecture beh of iicmb_m_sq_tb is + + constant c_f_clk : real := 100000.0; -- in kHz + constant c_f_scl_0 : real := 100.0; -- in kHz + constant c_f_scl_1 : real := 100.0; -- in kHz + constant c_f_scl_2 : real := 400.0; -- in kHz + constant c_f_scl_3 : real := 100.0; -- in kHz + constant c_p_clk : time := integer(1000000000.0/c_f_clk) * 1 ps; -- Period of 'clk' in ps. + + constant c_bus_num : positive := 4; + + ------------------------------------------------------------------------------ + component iicmb_m_sq is + generic + ( + g_bus_num : positive range 1 to 16 := 1; + g_f_clk : real := 100000.0; + g_f_scl_0 : real := 100.0; + g_f_scl_1 : real := 100.0; + g_f_scl_2 : real := 100.0; + g_f_scl_3 : real := 100.0; + g_f_scl_4 : real := 100.0; + g_f_scl_5 : real := 100.0; + g_f_scl_6 : real := 100.0; + g_f_scl_7 : real := 100.0; + g_f_scl_8 : real := 100.0; + g_f_scl_9 : real := 100.0; + g_f_scl_a : real := 100.0; + g_f_scl_b : real := 100.0; + g_f_scl_c : real := 100.0; + g_f_scl_d : real := 100.0; + g_f_scl_e : real := 100.0; + g_f_scl_f : real := 100.0; + g_cmd : seq_cmd_type_array := c_empty_array + ); + port + ( + clk : in std_logic; + s_rst : in std_logic; + cs_start : in std_logic; + cs_busy : out std_logic; + cs_status : out std_logic_vector(2 downto 0); + scl_i : in std_logic_vector(0 to g_bus_num - 1); + sda_i : in std_logic_vector(0 to g_bus_num - 1); + scl_o : out std_logic_vector(0 to g_bus_num - 1); + sda_o : out std_logic_vector(0 to g_bus_num - 1) + ); + end component iicmb_m_sq; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + component wire_mdl is + generic + ( + g_resistance_0 : real := 1.0; -- In Ohms + g_resistance_1 : real := 1.0; -- In Ohms + g_capacitance : real := 1.0; -- In pF + g_initial_level : bit := '0' + ); + port + ( + sig_in : in bit; + sig_out : out real; + sig_out_l : out bit + ); + end component wire_mdl; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + component i2c_slave_model is + generic + ( + i2c_adr : std_logic_vector(6 downto 0) + ); + port + ( + scl : inout std_logic; + sda : inout std_logic + ); + end component i2c_slave_model; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + function get_slave_addr(n : natural) return std_logic_vector is + variable ret : std_logic_vector(6 downto 0); + begin + ret := "010" & std_logic_vector(to_unsigned(n, 4)); + return ret; + end function get_slave_addr; + ------------------------------------------------------------------------------ + + signal cs_start : std_logic := '0'; + signal cs_busy : std_logic; + signal cs_status : std_logic_vector(2 downto 0); + + signal clk : std_logic := '0'; + signal s_rst : std_logic := '1'; + + signal scl_o : std_logic_vector(0 to c_bus_num - 1) := (others => '1'); + signal scl : std_logic_vector(0 to c_bus_num - 1) := (others => 'H'); + signal sda_o : std_logic_vector(0 to c_bus_num - 1) := (others => '1'); + signal sda : std_logic_vector(0 to c_bus_num - 1) := (others => 'H'); + + type real_vector is array (natural range <>) of real; + signal scl_real : real_vector(0 to c_bus_num - 1); + signal sda_real : real_vector(0 to c_bus_num - 1); + signal scl_quant : bit_vector(0 to c_bus_num - 1); + signal sda_quant : bit_vector(0 to c_bus_num - 1); + signal scl_nquant : bit_vector(0 to c_bus_num - 1) := (others => '1'); + signal sda_nquant : bit_vector(0 to c_bus_num - 1) := (others => '1'); + signal irq : std_logic; + +begin + + clk <= not(clk) after c_p_clk / 2; + s_rst <= '1', '0' after 113 ns; + + ------------------------------------------------------------------------------ + -- Generate signal to launch the sequencer + process + begin + cs_start <= '0'; + wait for 2000 ns; + wait until rising_edge(clk); + cs_start <= '1'; + wait until rising_edge(clk); + cs_start <= '0'; + wait; + end process; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + dut : iicmb_m_sq + generic map + ( + g_bus_num => c_bus_num, + g_f_clk => c_f_clk, + g_f_scl_0 => c_f_scl_0, + g_f_scl_1 => c_f_scl_1, + g_f_scl_2 => c_f_scl_2, + g_f_scl_3 => c_f_scl_3, + g_cmd => + ( + scmd_wait(1), -- Wait for 1 ms + scmd_set_bus(1), -- Select bus #1 + scmd_write_byte("0100001", x"00", x"4A"), -- Write byte + scmd_write_byte("0100001", x"01", x"67"), -- Write byte + scmd_wait(1), -- Wait for 1 ms + scmd_set_bus(2), -- Select bus #2 + scmd_write_byte("0100010", x"02", x"59"), -- Write byte + scmd_write_byte("0100010", x"03", x"AB") -- Write byte + ) + ) + port map + ( + clk => clk, + s_rst => s_rst, + cs_start => cs_start, + cs_busy => cs_busy, + cs_status => cs_status, + scl_i => to_stdlogicvector(scl_quant), + sda_i => to_stdlogicvector(sda_quant), + scl_o => scl_o, + sda_o => sda_o + ); + ------------------------------------------------------------------------------ + + --**************************************************************************** + bus_gen: + for i in 0 to c_bus_num - 1 generate + scl(i) <= '0' when (scl_o(i) = '0') else 'Z'; + sda(i) <= '0' when (sda_o(i) = '0') else 'Z'; + + ---------------------------------------------------------------------------- + wire_mdl_inst_0 : wire_mdl + generic map + ( + g_resistance_0 => 40.0, + g_resistance_1 => 4000.0, + g_capacitance => 200.0, -- In pF + g_initial_level => '1' + ) + port map + ( + sig_in => scl_nquant(i), + sig_out => scl_real(i), + sig_out_l => scl_quant(i) + ); + ---------------------------------------------------------------------------- + + ---------------------------------------------------------------------------- + wire_mdl_inst_1 : wire_mdl + generic map + ( + g_resistance_0 => 40.0, + g_resistance_1 => 4000.0, + g_capacitance => 200.0, -- In pF + g_initial_level => '1' + ) + port map + ( + sig_in => sda_nquant(i), + sig_out => sda_real(i), + sig_out_l => sda_quant(i) + ); + ---------------------------------------------------------------------------- + + ---------------------------------------------------------------------------- + i2c_slave_model_inst0 : i2c_slave_model + generic map + ( + i2c_adr => get_slave_addr(i) + ) + port map + ( + scl => scl(i), + sda => sda(i) + ); + ---------------------------------------------------------------------------- + end generate bus_gen; + --**************************************************************************** + + scl <= (others => 'H'); -- Pull-up + sda <= (others => 'H'); -- Pull-up + + scl_nquant <= to_bitvector(to_x01(scl)); + sda_nquant <= to_bitvector(to_x01(sda)); + +end architecture beh; +--============================================================================== +

trunk/src_tb/iicmb_m_sq_tb.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src_tb/timescale.v =================================================================== --- trunk/src_tb/timescale.v (nonexistent) +++ trunk/src_tb/timescale.v (revision 2) @@ -0,0 +1,2 @@ +`timescale 1ns / 10ps +

trunk/src_tb/timescale.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src_tb/iicmb_m_sq_arb_tb.vhd =================================================================== --- trunk/src_tb/iicmb_m_sq_arb_tb.vhd (nonexistent) +++ trunk/src_tb/iicmb_m_sq_arb_tb.vhd (revision 2) @@ -0,0 +1,311 @@ + +--============================================================================== +-- | +-- Project: IIC Multiple Bus Controller (IICMB) | +-- | +-- Module: Testbench for iicmb_m_sq. Testing arbitration and clock | +-- synchronization. | +-- Version: | +-- 1.0, April 29, 2016 | +-- | +-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | +-- | +--============================================================================== +--============================================================================== +-- Copyright (c) 2016, Sergey Shuvalkin | +-- All rights reserved. | +-- | +-- Redistribution and use in source and binary forms, with or without | +-- modification, are permitted provided that the following conditions are met: | +-- | +-- 1. Redistributions of source code must retain the above copyright notice, | +-- this list of conditions and the following disclaimer. | +-- 2. Redistributions in binary form must reproduce the above copyright | +-- notice, this list of conditions and the following disclaimer in the | +-- documentation and/or other materials provided with the distribution. | +-- | +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | +-- POSSIBILITY OF SUCH DAMAGE. | +--============================================================================== + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library iicmb; +use iicmb.iicmb_pkg.all; + +use work.test.all; + + +--============================================================================== +entity iicmb_m_sq_arb_tb is +end entity iicmb_m_sq_arb_tb; +--============================================================================== + +--============================================================================== +architecture beh of iicmb_m_sq_arb_tb is + + constant c_f_clk : real := 100000.0; -- in kHz + constant c_f_scl_0 : real := 100.0; -- in kHz + constant c_f_scl_1 : real := 66.0; -- in kHz + constant c_p_clk : time := integer(1000000000.0/c_f_clk) * 1 ps; -- Period of 'clk' in ps. + + ------------------------------------------------------------------------------ + component iicmb_m_sq is + generic + ( + g_bus_num : positive range 1 to 16 := 1; + g_f_clk : real := 100000.0; + g_f_scl_0 : real := 100.0; + g_f_scl_1 : real := 100.0; + g_f_scl_2 : real := 100.0; + g_f_scl_3 : real := 100.0; + g_f_scl_4 : real := 100.0; + g_f_scl_5 : real := 100.0; + g_f_scl_6 : real := 100.0; + g_f_scl_7 : real := 100.0; + g_f_scl_8 : real := 100.0; + g_f_scl_9 : real := 100.0; + g_f_scl_a : real := 100.0; + g_f_scl_b : real := 100.0; + g_f_scl_c : real := 100.0; + g_f_scl_d : real := 100.0; + g_f_scl_e : real := 100.0; + g_f_scl_f : real := 100.0; + g_cmd : seq_cmd_type_array := c_empty_array + ); + port + ( + clk : in std_logic; + s_rst : in std_logic; + cs_start : in std_logic; + cs_busy : out std_logic; + cs_status : out std_logic_vector(2 downto 0); + scl_i : in std_logic_vector(0 to g_bus_num - 1); + sda_i : in std_logic_vector(0 to g_bus_num - 1); + scl_o : out std_logic_vector(0 to g_bus_num - 1); + sda_o : out std_logic_vector(0 to g_bus_num - 1) + ); + end component iicmb_m_sq; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + component wire_mdl is + generic + ( + g_resistance_0 : real := 1.0; -- In Ohms + g_resistance_1 : real := 1.0; -- In Ohms + g_capacitance : real := 1.0; -- In pF + g_initial_level : bit := '0' + ); + port + ( + sig_in : in bit; + sig_out : out real; + sig_out_l : out bit + ); + end component wire_mdl; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + component i2c_slave_model is + generic + ( + i2c_adr : std_logic_vector(6 downto 0) + ); + port + ( + scl : inout std_logic; + sda : inout std_logic + ); + end component i2c_slave_model; + ------------------------------------------------------------------------------ + + signal clk : std_logic := '0'; + signal s_rst : std_logic := '1'; + + signal cs_start_0 : std_logic := '0'; + signal cs_busy_0 : std_logic; + signal cs_status_0 : std_logic_vector(2 downto 0); + + signal cs_start_1 : std_logic := '0'; + signal cs_busy_1 : std_logic; + signal cs_status_1 : std_logic_vector(2 downto 0); + + signal scl_o_0 : std_logic_vector(0 to 0) := (others => '1'); + signal sda_o_0 : std_logic_vector(0 to 0) := (others => '1'); + signal scl_o_1 : std_logic_vector(0 to 0) := (others => '1'); + signal sda_o_1 : std_logic_vector(0 to 0) := (others => '1'); + signal scl : std_logic_vector(0 to 0) := (others => 'H'); + signal sda : std_logic_vector(0 to 0) := (others => 'H'); + + type real_vector is array (natural range <>) of real; + signal scl_real : real_vector(0 to 0); + signal sda_real : real_vector(0 to 0); + signal scl_quant : bit_vector(0 to 0); + signal sda_quant : bit_vector(0 to 0); + signal scl_nquant : bit_vector(0 to 0) := (others => '1'); + signal sda_nquant : bit_vector(0 to 0) := (others => '1'); + +begin + + clk <= not(clk) after c_p_clk / 2; + s_rst <= '1', '0' after 113 ns; + + ------------------------------------------------------------------------------ + -- Generate signal to launch the sequencer #0 + process + begin + cs_start_0 <= '0'; + wait for 2000 ns; + wait until rising_edge(clk); + cs_start_0 <= '1'; + wait until rising_edge(clk); + cs_start_0 <= '0'; + wait; + end process; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + -- Generate signal to launch the sequencer #1 + process + begin + cs_start_1 <= '0'; + wait for 2000 ns; + wait until rising_edge(clk); + cs_start_1 <= '1'; + wait until rising_edge(clk); + cs_start_1 <= '0'; + wait; + end process; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + dut_inst0 : iicmb_m_sq + generic map + ( + g_bus_num => 1, + g_f_clk => c_f_clk, + g_f_scl_0 => c_f_scl_0, + g_cmd => + ( + scmd_wait(1), -- Wait for 1 ms + scmd_set_bus(0), -- Select bus #0 + scmd_write_byte("0100001", x"03", x"4A"), -- Write byte + scmd_write_byte("0100001", x"05", x"27") -- Write byte + ) + ) + port map + ( + clk => clk, + s_rst => s_rst, + cs_start => cs_start_0, + cs_busy => cs_busy_0, + cs_status => cs_status_0, + scl_i => to_stdlogicvector(scl_quant), + sda_i => to_stdlogicvector(sda_quant), + scl_o => scl_o_0, + sda_o => sda_o_0 + ); + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + dut_inst1 : iicmb_m_sq + generic map + ( + g_bus_num => 1, + g_f_clk => c_f_clk, + g_f_scl_0 => c_f_scl_1, + g_cmd => + ( + scmd_wait(1), -- Wait for 1 ms + scmd_set_bus(0), -- Select bus #0 + scmd_write_byte("0100001", x"03", x"4A"), -- Write byte + scmd_write_byte("0100001", x"05", x"67") -- Write byte + ) + ) + port map + ( + clk => clk, + s_rst => s_rst, + cs_start => cs_start_1, + cs_busy => cs_busy_1, + cs_status => cs_status_1, + scl_i => to_stdlogicvector(scl_quant), + sda_i => to_stdlogicvector(sda_quant), + scl_o => scl_o_1, + sda_o => sda_o_1 + ); + ------------------------------------------------------------------------------ + + scl(0) <= '0' when (scl_o_0(0) = '0') else 'Z'; + sda(0) <= '0' when (sda_o_0(0) = '0') else 'Z'; + scl(0) <= '0' when (scl_o_1(0) = '0') else 'Z'; + sda(0) <= '0' when (sda_o_1(0) = '0') else 'Z'; + scl(0) <= 'H'; -- Pull-up + sda(0) <= 'H'; -- Pull-up + + ---------------------------------------------------------------------------- + wire_mdl_inst_0 : wire_mdl + generic map + ( + g_resistance_0 => 40.0, + g_resistance_1 => 4000.0, + g_capacitance => 200.0, -- In pF + g_initial_level => '1' + ) + port map + ( + sig_in => scl_nquant(0), + sig_out => scl_real(0), + sig_out_l => scl_quant(0) + ); + ---------------------------------------------------------------------------- + + ---------------------------------------------------------------------------- + wire_mdl_inst_1 : wire_mdl + generic map + ( + g_resistance_0 => 40.0, + g_resistance_1 => 4000.0, + g_capacitance => 200.0, -- In pF + g_initial_level => '1' + ) + port map + ( + sig_in => sda_nquant(0), + sig_out => sda_real(0), + sig_out_l => sda_quant(0) + ); + ---------------------------------------------------------------------------- + + ---------------------------------------------------------------------------- + i2c_slave_model_inst0 : i2c_slave_model + generic map + ( + i2c_adr => "0100001" + ) + port map + ( + scl => scl(0), + sda => sda(0) + ); + ---------------------------------------------------------------------------- + + scl_nquant <= to_bitvector(to_x01(scl)); + sda_nquant <= to_bitvector(to_x01(sda)); + +end architecture beh; +--============================================================================== +

trunk/src_tb/iicmb_m_sq_arb_tb.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src_tb/i2c_slave_model.v =================================================================== --- trunk/src_tb/i2c_slave_model.v (nonexistent) +++ trunk/src_tb/i2c_slave_model.v (revision 2) @@ -0,0 +1,357 @@ +///////////////////////////////////////////////////////////////////// +//// //// +//// WISHBONE rev.B2 compliant synthesizable I2C Slave model //// +//// //// +//// //// +//// Authors: Richard Herveille (richard@asics.ws) www.asics.ws //// +//// John Sheahan (jrsheahan@optushome.com.au) //// +//// //// +//// Downloaded from: http://www.opencores.org/projects/i2c/ //// +//// //// +///////////////////////////////////////////////////////////////////// +//// //// +//// Copyright (C) 2001,2002 Richard Herveille //// +//// richard@asics.ws //// +//// //// +//// This source file may be used and distributed without //// +//// restriction provided that this copyright statement is not //// +//// removed from the file and that any derivative work contains //// +//// the original copyright notice and the associated disclaimer.//// +//// //// +//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY //// +//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED //// +//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS //// +//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR //// +//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, //// +//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES //// +//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE //// +//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR //// +//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF //// +//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT //// +//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT //// +//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE //// +//// POSSIBILITY OF SUCH DAMAGE. //// +//// //// +///////////////////////////////////////////////////////////////////// + +// CVS Log +// +// $Id: i2c_slave_model.v,v 1.7 2006-09-04 09:08:51 rherveille Exp $ +// +// $Date: 2006-09-04 09:08:51 $ +// $Revision: 1.7 $ +// $Author: rherveille $ +// $Locker: $ +// $State: Exp $ +// +// Change History: +// $Log: not supported by cvs2svn $ +// Revision 1.6 2005/02/28 11:33:48 rherveille +// Fixed Tsu:sta timing check. +// Added Thd:sta timing check. +// +// Revision 1.5 2003/12/05 11:05:19 rherveille +// Fixed slave address MSB='1' bug +// +// Revision 1.4 2003/09/11 08:25:37 rherveille +// Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. +// +// Revision 1.3 2002/10/30 18:11:06 rherveille +// Added timing tests to i2c_model. +// Updated testbench. +// +// Revision 1.2 2002/03/17 10:26:38 rherveille +// Fixed some race conditions in the i2c-slave model. +// Added debug information. +// Added headers. +// + +`include "timescale.v" + +module i2c_slave_model (scl, sda); + + // + // parameters + // + parameter I2C_ADR = 7'b001_0000; + + // + // input && outpus + // + input scl; + inout sda; + + // + // Variable declaration + // + wire debug = 1'b1; + + reg [7:0] mem [3:0]; // initiate memory + reg [7:0] mem_adr; // memory address + reg [7:0] mem_do; // memory data output + + reg sta, d_sta; + reg sto, d_sto; + + reg [7:0] sr; // 8bit shift register + reg rw; // read/write direction + + wire my_adr; // my address called ?? + wire i2c_reset; // i2c-statemachine reset + reg [2:0] bit_cnt; // 3bit downcounter + wire acc_done; // 8bits transfered + reg ld; // load downcounter + + reg sda_o = 1'b1; // sda-drive level + wire sda_dly; // delayed version of sda + + // statemachine declaration + parameter idle = 3'b000; + parameter slave_ack = 3'b001; + parameter get_mem_adr = 3'b010; + parameter gma_ack = 3'b011; + parameter data = 3'b100; + parameter data_ack = 3'b101; + + reg [2:0] state; // synopsys enum_state + + // + // module body + // + + initial + begin + sda_o = 1'b1; + state = idle; + end + + // generate shift register + always @(posedge scl) + sr <= #1 {sr[6:0],sda}; + + //detect my_address + assign my_adr = (sr[7:1] == I2C_ADR); + // FIXME: This should not be a generic assign, but rather + // qualified on address transfer phase and probably reset by stop + + //generate bit-counter + always @(posedge scl) + if(ld) + bit_cnt <= #1 3'b111; + else + bit_cnt <= #1 bit_cnt - 3'h1; + + //generate access done signal + assign acc_done = !(|bit_cnt); + + // generate delayed version of sda + // this model assumes a hold time for sda after the falling edge of scl. + // According to the Phillips i2c spec, there s/b a 0 ns hold time for sda + // with regards to scl. If the data changes coincident with the clock, the + // acknowledge is missed + // Fix by Michael Sosnoski + assign #1 sda_dly = sda; + + + //detect start condition + always @(negedge sda) + if(scl) + begin + sta <= #1 1'b1; + d_sta <= #1 1'b0; + sto <= #1 1'b0; + + if(debug) + $display("DEBUG i2c_slave; start condition detected at %t", $time); + end + else + sta <= #1 1'b0; + + always @(posedge scl) + d_sta <= #1 sta; + + // detect stop condition + always @(posedge sda) + if(scl) + begin + sta <= #1 1'b0; + sto <= #1 1'b1; + + if(debug && ($time != 0)) + $display("DEBUG i2c_slave; stop condition detected at %t", $time); + end + else + sto <= #1 1'b0; + + //generate i2c_reset signal + assign i2c_reset = sta || sto; + + // generate statemachine + always @(negedge scl or posedge sto) + if (sto || (sta && !d_sta) ) + begin + state <= #1 idle; // reset statemachine + + sda_o <= #1 1'b1; + ld <= #1 1'b1; + end + else + begin + // initial settings + sda_o <= #1 1'b1; + ld <= #1 1'b0; + + case(state) // synopsys full_case parallel_case + idle: // idle state + if (acc_done && my_adr) + begin + state <= #1 slave_ack; + rw <= #1 sr[0]; + sda_o <= #1 1'b0; // generate i2c_ack + + #2; + if(debug && rw) + $display("DEBUG i2c_slave; command byte received (read) at %t", $time); + if(debug && !rw) + $display("DEBUG i2c_slave; command byte received (write) at %t", $time); + + if(rw) + begin + mem_do <= #1 mem[mem_adr]; + + if(debug) + begin + #2 $display("DEBUG i2c_slave; data block read %x from address %x (1)", mem_do, mem_adr); + #2 $display("DEBUG i2c_slave; memcheck [0]=%x, [1]=%x, [2]=%x", mem[4'h0], mem[4'h1], mem[4'h2]); + end + end + end + + slave_ack: + begin + if(rw) + begin + state <= #1 data; + sda_o <= #1 mem_do[7]; + end + else + state <= #1 get_mem_adr; + + ld <= #1 1'b1; + end + + get_mem_adr: // wait for memory address + if(acc_done) + begin + state <= #1 gma_ack; + mem_adr <= #1 sr; // store memory address + sda_o <= #1 !(sr <= 15); // generate i2c_ack, for valid address + + if(debug) + #1 $display("DEBUG i2c_slave; address received. adr=%x, ack=%b", sr, sda_o); + end + + gma_ack: + begin + state <= #1 data; + ld <= #1 1'b1; + end + + data: // receive or drive data + begin + if(rw) + sda_o <= #1 mem_do[7]; + + if(acc_done) + begin + state <= #1 data_ack; + mem_adr <= #2 mem_adr + 8'h1; + sda_o <= #1 (rw && (mem_adr <= 15) ); // send ack on write, receive ack on read + + if(rw) + begin + #3 mem_do <= mem[mem_adr]; + + if(debug) + #5 $display("DEBUG i2c_slave; data block read %x from address %x (2)", mem_do, mem_adr); + end + + if(!rw) + begin + mem[ mem_adr[3:0] ] <= #1 sr; // store data in memory + + if(debug) + #2 $display("DEBUG i2c_slave; data block write %x to address %x", sr, mem_adr); + end + end + end + + data_ack: + begin + ld <= #1 1'b1; + + if(rw) + if(sr[0]) // read operation && master send NACK + begin + state <= #1 idle; + sda_o <= #1 1'b1; + end + else + begin + state <= #1 data; + sda_o <= #1 mem_do[7]; + end + else + begin + state <= #1 data; + sda_o <= #1 1'b1; + end + end + + endcase + end + + // read data from memory + always @(posedge scl) + if(!acc_done && rw) + mem_do <= #1 {mem_do[6:0], 1'b1}; // insert 1'b1 for host ack generation + + // generate tri-states + assign sda = sda_o ? 1'bz : 1'b0; + + + // + // Timing checks + // + + wire tst_sto = sto; + wire tst_sta = sta; + + specify + specparam normal_scl_low = 4700, + normal_scl_high = 4000, + normal_tsu_sta = 4700, + normal_thd_sta = 4000, + normal_tsu_sto = 4000, + normal_tbuf = 4700, + + fast_scl_low = 1300, + fast_scl_high = 600, + fast_tsu_sta = 1300, + fast_thd_sta = 600, + fast_tsu_sto = 600, + fast_tbuf = 1300; + + $width(negedge scl, normal_scl_low); // scl low time + $width(posedge scl, normal_scl_high); // scl high time + + $setup(posedge scl, negedge sda &&& scl, normal_tsu_sta); // setup start + $setup(negedge sda &&& scl, negedge scl, normal_thd_sta); // hold start + $setup(posedge scl, posedge sda &&& scl, normal_tsu_sto); // setup stop + + $setup(posedge tst_sta, posedge tst_sto, normal_tbuf); // stop to start time + endspecify + +endmodule + +

trunk/src_tb/i2c_slave_model.v Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: trunk/src_tb/iicmb_m_wb_tb.vhd =================================================================== --- trunk/src_tb/iicmb_m_wb_tb.vhd (nonexistent) +++ trunk/src_tb/iicmb_m_wb_tb.vhd (revision 2) @@ -0,0 +1,453 @@ + +--============================================================================== +-- | +-- Project: IIC Multiple Bus Controller (IICMB) | +-- | +-- Module: Testbench for 'iicmb_m_wb'. | +-- Version: | +-- 1.0, April 29, 2016 | +-- | +-- Author: Sergey Shuvalkin, (sshuv2@opencores.org) | +-- | +--============================================================================== +--============================================================================== +-- Copyright (c) 2016, Sergey Shuvalkin | +-- All rights reserved. | +-- | +-- Redistribution and use in source and binary forms, with or without | +-- modification, are permitted provided that the following conditions are met: | +-- | +-- 1. Redistributions of source code must retain the above copyright notice, | +-- this list of conditions and the following disclaimer. | +-- 2. Redistributions in binary form must reproduce the above copyright | +-- notice, this list of conditions and the following disclaimer in the | +-- documentation and/or other materials provided with the distribution. | +-- | +-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" | +-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE | +-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE | +-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE | +-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR | +-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF | +-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS | +-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN | +-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) | +-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | +-- POSSIBILITY OF SUCH DAMAGE. | +--============================================================================== + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library iicmb; +use iicmb.iicmb_pkg.all; + +use work.test.all; + + +--============================================================================== +entity iicmb_m_wb_tb is +end entity iicmb_m_wb_tb; +--============================================================================== + +--============================================================================== +architecture beh of iicmb_m_wb_tb is + + constant c_f_clk : real := 100000.0; -- in kHz + constant c_f_scl_0 : real := 100.0; -- in kHz + constant c_f_scl_1 : real := 100.0; -- in kHz + constant c_f_scl_2 : real := 100.0; -- in kHz + constant c_f_scl_3 : real := 100.0; -- in kHz + constant c_p_clk : time := integer(1000000000.0/c_f_clk) * 1 ps; + + constant c_bus_num : positive := 4; + + ------------------------------------------------------------------------------ + component iicmb_m_wb is + generic + ( + g_bus_num : positive range 1 to 16 := 1; + g_f_clk : real := 100000.0; + g_f_scl_0 : real := 100.0; + g_f_scl_1 : real := 100.0; + g_f_scl_2 : real := 100.0; + g_f_scl_3 : real := 100.0; + g_f_scl_4 : real := 100.0; + g_f_scl_5 : real := 100.0; + g_f_scl_6 : real := 100.0; + g_f_scl_7 : real := 100.0; + g_f_scl_8 : real := 100.0; + g_f_scl_9 : real := 100.0; + g_f_scl_a : real := 100.0; + g_f_scl_b : real := 100.0; + g_f_scl_c : real := 100.0; + g_f_scl_d : real := 100.0; + g_f_scl_e : real := 100.0; + g_f_scl_f : real := 100.0 + ); + port + ( + clk_i : in std_logic; + rst_i : in std_logic; + cyc_i : in std_logic; + stb_i : in std_logic; + ack_o : out std_logic; + adr_i : in std_logic_vector(1 downto 0); + we_i : in std_logic; + dat_i : in std_logic_vector(7 downto 0); + dat_o : out std_logic_vector(7 downto 0); + irq : out std_logic; + scl_i : in std_logic_vector(0 to g_bus_num - 1); + sda_i : in std_logic_vector(0 to g_bus_num - 1); + scl_o : out std_logic_vector(0 to g_bus_num - 1); + sda_o : out std_logic_vector(0 to g_bus_num - 1) + ); + end component iicmb_m_wb; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + component wire_mdl is + generic + ( + g_resistance_0 : real := 1.0; -- In Ohms + g_resistance_1 : real := 1.0; -- In Ohms + g_capacitance : real := 1.0; -- In pF + g_initial_level : bit := '0' + ); + port + ( + sig_in : in bit; + sig_out : out real; + sig_out_l : out bit + ); + end component wire_mdl; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + component i2c_slave_model is + generic + ( + i2c_adr : std_logic_vector(6 downto 0) + ); + port + ( + scl : inout std_logic; + sda : inout std_logic + ); + end component i2c_slave_model; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + function get_slave_addr(n : natural) return std_logic_vector is + variable ret : std_logic_vector(6 downto 0); + begin + ret := "010" & std_logic_vector(to_unsigned(n, 4)); + return ret; + end function get_slave_addr; + ------------------------------------------------------------------------------ + + signal clk_i : std_logic := '0'; + signal rst_i : std_logic := '1'; + signal cyc_i : std_logic := '0'; + signal stb_i : std_logic := '0'; + signal ack_o : std_logic; + signal adr_i : std_logic_vector(1 downto 0) := "00"; + signal we_i : std_logic := '0'; + signal dat_i : std_logic_vector(7 downto 0) := "00000000"; + signal dat_o : std_logic_vector(7 downto 0); + + signal scl_o : std_logic_vector(0 to c_bus_num - 1) := (others => '1'); + signal scl : std_logic_vector(0 to c_bus_num - 1) := (others => 'H'); + signal sda_o : std_logic_vector(0 to c_bus_num - 1) := (others => '1'); + signal sda : std_logic_vector(0 to c_bus_num - 1) := (others => 'H'); + + type real_vector is array (natural range <>) of real; + signal scl_real : real_vector(0 to c_bus_num - 1); + signal sda_real : real_vector(0 to c_bus_num - 1); + signal scl_quant : bit_vector(0 to c_bus_num - 1); + signal sda_quant : bit_vector(0 to c_bus_num - 1); + signal scl_nquant : bit_vector(0 to c_bus_num - 1) := (others => '1'); + signal sda_nquant : bit_vector(0 to c_bus_num - 1) := (others => '1'); + signal irq : std_logic; + + ---- Byte-wide commands: + constant wb_m_set_bus : std_logic_vector(7 downto 0) := "00000" & mcmd_set_bus; + constant wb_m_write : std_logic_vector(7 downto 0) := "00000" & mcmd_write; + constant wb_m_read_ack : std_logic_vector(7 downto 0) := "00000" & mcmd_read_ack; + constant wb_m_read_nak : std_logic_vector(7 downto 0) := "00000" & mcmd_read_nak; + constant wb_m_start : std_logic_vector(7 downto 0) := "00000" & mcmd_start; + constant wb_m_stop : std_logic_vector(7 downto 0) := "00000" & mcmd_stop; + constant wb_m_wait : std_logic_vector(7 downto 0) := "00000" & mcmd_wait; + +begin + + clk_i <= not(clk_i) after c_p_clk / 2; + rst_i <= '1', '0' after 113 ns; + + ------------------------------------------------------------------------------ + -- Wishbone bus activity process: + process + ---------------------------------------------------------------------------- + procedure wb_write(addr : in std_logic_vector(1 downto 0); data : in std_logic_vector(7 downto 0)) is + begin + cyc_i <= '1'; + stb_i <= '1'; + adr_i <= addr; + we_i <= '1'; + dat_i <= data; + wait until rising_edge(clk_i)and(ack_o = '1'); + cyc_i <= '0'; + stb_i <= '0'; + print_string("Wishbone Write: 0x" & to_string(addr, "X", 2) & " : " & "0x" & to_string(data, "X", 2) & newline); + end procedure wb_write; + ---------------------------------------------------------------------------- + ---------------------------------------------------------------------------- + procedure wb_read(addr : in std_logic_vector(1 downto 0); data : out std_logic_vector(7 downto 0)) is + begin + cyc_i <= '1'; + stb_i <= '1'; + adr_i <= addr; + we_i <= '0'; + wait until rising_edge(clk_i)and(ack_o = '1'); + data := dat_o; + cyc_i <= '0'; + stb_i <= '0'; + print_string("Wishbone Read : 0x" & to_string(addr, "X", 2) & " : " & "0x" & to_string(dat_o, "X", 2) & newline); + end procedure wb_read; + ---------------------------------------------------------------------------- + ---------------------------------------------------------------------------- + procedure wb_wait(n : in positive) is + begin + print_string("Wishbone Waiting for " & integer'image(n) & " cycles." & newline); + cyc_i <= '0'; + stb_i <= '0'; + for i in 0 to n - 1 loop + wait until rising_edge(clk_i); + end loop; + end procedure wb_wait; + ---------------------------------------------------------------------------- + ---------------------------------------------------------------------------- + procedure wb_halt is + begin + print_string("Wishbone Halted" & newline); + cyc_i <= '0'; + stb_i <= '0'; + wait; + end procedure wb_halt; + ---------------------------------------------------------------------------- + procedure i2c_write_byte(slave_addr : in std_logic_vector(6 downto 0); addr : in std_logic_vector(7 downto 0); data : in std_logic_vector(7 downto 0)) is + variable v_tmp : std_logic_vector(7 downto 0); + begin + wb_write("10", wb_m_start); + wait until rising_edge(clk_i)and(irq = '1'); + wb_read("10", v_tmp); + assert (v_tmp(7) = '1') report "Something gone wrong" severity error; + -- + wb_write("01", slave_addr & "0"); + wb_write("10", wb_m_write); + wait until rising_edge(clk_i)and(irq = '1'); + wb_read("10", v_tmp); + assert (v_tmp(7) = '1') report "Something gone wrong" severity error; + -- + wb_write("01", addr); + wb_write("10", wb_m_write); + wait until rising_edge(clk_i)and(irq = '1'); + wb_read("10", v_tmp); + assert (v_tmp(7) = '1') report "Something gone wrong" severity error; + -- + wb_write("01", data); + wb_write("10", wb_m_write); + wait until rising_edge(clk_i)and(irq = '1'); + wb_read("10", v_tmp); + assert (v_tmp(7) = '1') report "Something gone wrong" severity error; + -- + wb_write("10", wb_m_stop); + wait until rising_edge(clk_i)and(irq = '1'); + wb_read("10", v_tmp); + assert (v_tmp(7) = '1') report "Something gone wrong" severity error; + end procedure i2c_write_byte; + ---------------------------------------------------------------------------- + ---------------------------------------------------------------------------- + procedure i2c_read_byte(slave_addr : in std_logic_vector(6 downto 0); addr : in std_logic_vector(7 downto 0); data : out std_logic_vector(7 downto 0)) is + variable v_tmp : std_logic_vector(7 downto 0); + begin + wb_write("10", wb_m_start); + wait until rising_edge(clk_i)and(irq = '1'); + wb_read("10", v_tmp); + assert (v_tmp(7) = '1') report "Something gone wrong" severity error; + -- + wb_write("01", slave_addr & "0"); + wb_write("10", wb_m_write); + wait until rising_edge(clk_i)and(irq = '1'); + wb_read("10", v_tmp); + assert (v_tmp(7) = '1') report "Something gone wrong" severity error; + -- + wb_write("01", addr); + wb_write("10", wb_m_write); + wait until rising_edge(clk_i)and(irq = '1'); + wb_read("10", v_tmp); + assert (v_tmp(7) = '1') report "Something gone wrong" severity error; + -- + wb_write("10", wb_m_start); + wait until rising_edge(clk_i)and(irq = '1'); + wb_read("10", v_tmp); + assert (v_tmp(7) = '1') report "Something gone wrong" severity error; + -- + wb_write("01", slave_addr & "1"); + wb_write("10", wb_m_write); + wait until rising_edge(clk_i)and(irq = '1'); + wb_read("10", v_tmp); + assert (v_tmp(7) = '1') report "Something gone wrong" severity error; + -- + wb_write("10", wb_m_read_nak); + wait until rising_edge(clk_i)and(irq = '1'); + wb_read("10", v_tmp); + assert (v_tmp(7) = '1') report "Something gone wrong" severity error; + wb_read("01", data); + -- + wb_write("10", wb_m_stop); + wait until rising_edge(clk_i)and(irq = '1'); + wb_read("10", v_tmp); + assert (v_tmp(7) = '1') report "Something gone wrong" severity error; + end procedure i2c_read_byte; + ---------------------------------------------------------------------------- + variable v_data : std_logic_vector(7 downto 0); + begin + -- Initial delay: + wb_wait(100); + + -- + wb_read("00", v_data); + wb_read("01", v_data); + wb_read("10", v_data); + wb_wait(1); + wb_read("11", v_data); + -- + wb_wait(10); + -- Enable controller and interrupts + wb_write("00", "11000000"); + wb_read("00", v_data); + -- + -- Select Bus #1 + wb_wait(10); + wb_write("01", "00000001"); + wb_write("10", wb_m_set_bus); + wb_wait(1); + wb_read("10", v_data); + -- + + -- + wb_wait(10); + i2c_write_byte(get_slave_addr(1), x"00", x"4A"); + i2c_write_byte(get_slave_addr(1), x"01", x"67"); + -- + + -- + wb_wait(10); + i2c_read_byte(get_slave_addr(1), x"00", v_data); + print_string("Data read: " & to_string(v_data, "X", 2) & newline); + i2c_read_byte(get_slave_addr(1), x"01", v_data); + print_string("Data read: " & to_string(v_data, "X", 2) & newline); + -- + + -- Halt bus activity + wb_halt; + end process; + ------------------------------------------------------------------------------ + + ------------------------------------------------------------------------------ + dut : iicmb_m_wb + generic map + ( + g_bus_num => c_bus_num, + g_f_clk => c_f_clk, + g_f_scl_0 => c_f_scl_0, + g_f_scl_1 => c_f_scl_1, + g_f_scl_2 => c_f_scl_2, + g_f_scl_3 => c_f_scl_3 + ) + port map + ( + clk_i => clk_i, + rst_i => rst_i, + cyc_i => cyc_i, + stb_i => stb_i, + ack_o => ack_o, + adr_i => adr_i, + we_i => we_i, + dat_i => dat_i, + dat_o => dat_o, + irq => irq, + scl_i => to_stdlogicvector(scl_quant), + sda_i => to_stdlogicvector(sda_quant), + scl_o => scl_o, + sda_o => sda_o + ); + ------------------------------------------------------------------------------ + + --**************************************************************************** + bus_gen: + for i in 0 to c_bus_num - 1 generate + scl(i) <= '0' when (scl_o(i) = '0') else 'Z'; + sda(i) <= '0' when (sda_o(i) = '0') else 'Z'; + + ---------------------------------------------------------------------------- + wire_mdl_inst_0 : wire_mdl + generic map + ( + g_resistance_0 => 40.0, + g_resistance_1 => 4000.0, + g_capacitance => 200.0, -- In pF + g_initial_level => '1' + ) + port map + ( + sig_in => scl_nquant(i), + sig_out => scl_real(i), + sig_out_l => scl_quant(i) + ); + ---------------------------------------------------------------------------- + + ---------------------------------------------------------------------------- + wire_mdl_inst_1 : wire_mdl + generic map + ( + g_resistance_0 => 40.0, + g_resistance_1 => 4000.0, + g_capacitance => 200.0, -- In pF + g_initial_level => '1' + ) + port map + ( + sig_in => sda_nquant(i), + sig_out => sda_real(i), + sig_out_l => sda_quant(i) + ); + ---------------------------------------------------------------------------- + + ---------------------------------------------------------------------------- + i2c_slave_model_inst0 : i2c_slave_model + generic map + ( + i2c_adr => get_slave_addr(i) + ) + port map + ( + scl => scl(i), + sda => sda(i) + ); + ---------------------------------------------------------------------------- + end generate bus_gen; + --**************************************************************************** + + scl <= (others => 'H'); -- Pull up + sda <= (others => 'H'); -- Pull up + + scl_nquant <= to_bitvector(to_x01(scl)); + sda_nquant <= to_bitvector(to_x01(sda)); + +end architecture beh; +--============================================================================== +

trunk/src_tb/iicmb_m_wb_tb.vhd Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property

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