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/trunk/doc/src/opencores_logo_text.eps File deleted

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trunk/doc/src/opencores_logo.eps Property changes : Deleted: svn:executable ## -1 +0,0 ## -* \ No newline at end of property Index: trunk/doc/src/opencores_logo_text.svg =================================================================== --- trunk/doc/src/opencores_logo_text.svg (nonexistent) +++ trunk/doc/src/opencores_logo_text.svg (revision 3) @@ -0,0 +1,152 @@ + + + + Index: trunk/doc/src/iicmb_mb.odt =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/doc/src/opencores_logo.svg =================================================================== --- trunk/doc/src/opencores_logo.svg (nonexistent) +++ trunk/doc/src/opencores_logo.svg (revision 3) @@ -0,0 +1,96 @@ + + + + Index: trunk/doc/iicmb_mb.pdf =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/src/avalon_mm.vhd =================================================================== --- trunk/src/avalon_mm.vhd (revision 2) +++ trunk/src/avalon_mm.vhd (revision 3) @@ -46,25 +46,25 @@ port ( ------------------------------------ - clk : in std_logic; -- Clock input - s_rst : in std_logic; -- Synchronous reset (active high) + clk : in std_logic; -- Clock input + s_rst : in std_logic; -- Synchronous reset (active high) ------------------------------------ ------------------------------------ -- Avalon-MM slave interface: - waitrequest : out std_logic; - readdata : out std_logic_vector(31 downto 0); - readdatavalid : out std_logic; - writedata : in std_logic_vector(31 downto 0); - write : in std_logic; - read : in std_logic; - byteenable : in std_logic_vector( 3 downto 0); + waitrequest : out std_logic; -- Wait request + readdata : out std_logic_vector(31 downto 0); -- Data from slave to master + readdatavalid : out std_logic; -- Data validity indication + writedata : in std_logic_vector(31 downto 0); -- Data from master to slave + write : in std_logic; -- Asserted to indicate write transfer + read : in std_logic; -- Asserted to indicate read transfer + byteenable : in std_logic_vector( 3 downto 0); -- Enables specific byte lane(s) ------------------------------------ ------------------------------------ -- Regblock interface: - wr : out std_logic_vector( 3 downto 0); -- Write (active high) - rd : out std_logic_vector( 3 downto 0); -- Read (active high) - idata : out std_logic_vector(31 downto 0); -- Data from System Bus - odata : in std_logic_vector(31 downto 0) -- Data to System Bus + wr : out std_logic_vector( 3 downto 0); -- Write (active high) + rd : out std_logic_vector( 3 downto 0); -- Read (active high) + idata : out std_logic_vector(31 downto 0); -- Data from System Bus + odata : in std_logic_vector(31 downto 0) -- Data for System Bus ------------------------------------ ); end entity avalon_mm; Index: trunk/src/wishbone.vhd =================================================================== --- trunk/src/wishbone.vhd (revision 2) +++ trunk/src/wishbone.vhd (revision 3) @@ -46,25 +46,25 @@ port ( ------------------------------------ - clk_i : in std_logic; -- Clock input - rst_i : in std_logic; -- Synchronous reset (active high) + clk_i : in std_logic; -- Clock input + rst_i : in std_logic; -- Synchronous reset (active high) ------------------------------------ ------------------------------------ -- Wishbone slave interface: - cyc_i : in std_logic; -- - stb_i : in std_logic; -- - ack_o : out std_logic; -- - adr_i : in std_logic_vector( 1 downto 0); -- Low bits of Wishbone address - we_i : in std_logic; -- - dat_i : in std_logic_vector( 7 downto 0); -- Data input - dat_o : out std_logic_vector( 7 downto 0); -- Data output + cyc_i : in std_logic; -- Valid bus cycle indication + stb_i : in std_logic; -- Slave selection + ack_o : out std_logic; -- Acknowledge output + adr_i : in std_logic_vector( 1 downto 0); -- Low bits of Wishbone address + we_i : in std_logic; -- Write enable + dat_i : in std_logic_vector( 7 downto 0); -- Data input + dat_o : out std_logic_vector( 7 downto 0); -- Data output ------------------------------------ ------------------------------------ -- Regblock interface: - wr : out std_logic_vector( 3 downto 0); -- Write (active high) - rd : out std_logic_vector( 3 downto 0); -- Read (active high) - idata : out std_logic_vector(31 downto 0); -- Data from System Bus - odata : in std_logic_vector(31 downto 0) -- Data to System Bus + wr : out std_logic_vector( 3 downto 0); -- Write (active high) + rd : out std_logic_vector( 3 downto 0); -- Read (active high) + idata : out std_logic_vector(31 downto 0); -- Data from System Bus + odata : in std_logic_vector(31 downto 0) -- Data to System Bus ------------------------------------ ); end entity wishbone; Index: trunk/src/iicmb_m_av.vhd =================================================================== --- trunk/src/iicmb_m_av.vhd (revision 2) +++ trunk/src/iicmb_m_av.vhd (revision 3) @@ -73,13 +73,13 @@ clk : in std_logic; -- Clock s_rst : in std_logic; -- Synchronous reset (active high) ------------- - waitrequest : out std_logic; - readdata : out std_logic_vector(31 downto 0); - readdatavalid : out std_logic; - writedata : in std_logic_vector(31 downto 0); - write : in std_logic; - read : in std_logic; - byteenable : in std_logic_vector( 3 downto 0); + waitrequest : out std_logic; -- Wait request + readdata : out std_logic_vector(31 downto 0); -- Data from slave to master + readdatavalid : out std_logic; -- Data validity indication + writedata : in std_logic_vector(31 downto 0); -- Data from master to slave + write : in std_logic; -- Asserted to indicate write transfer + read : in std_logic; -- Asserted to indicate read transfer + byteenable : in std_logic_vector( 3 downto 0); -- Enables specific byte lane(s) ------------------------------------ ------------------------------------ -- Interrupt request: Index: trunk/src/iicmb_m_wb.vhd =================================================================== --- trunk/src/iicmb_m_wb.vhd (revision 2) +++ trunk/src/iicmb_m_wb.vhd (revision 3) @@ -73,11 +73,11 @@ clk_i : in std_logic; -- Clock rst_i : in std_logic; -- Synchronous reset (active high) ------------- - cyc_i : in std_logic; -- - stb_i : in std_logic; -- - ack_o : out std_logic; -- + cyc_i : in std_logic; -- Valid bus cycle indication + stb_i : in std_logic; -- Slave selection + ack_o : out std_logic; -- Acknowledge output adr_i : in std_logic_vector(1 downto 0); -- Low bits of Wishbone address - we_i : in std_logic; -- + we_i : in std_logic; -- Write enable dat_i : in std_logic_vector(7 downto 0); -- Data input dat_o : out std_logic_vector(7 downto 0); -- Data output ------------------------------------