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  • This comparison shows the changes necessary to convert path 
    /ion
    from Rev 233 to Rev 234
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  •

Rev 233 → Rev 234

/trunk/vhdl/SoC/mips_soc.vhdl
119,6 → 119,10
uart_rxd : in std_logic;
uart_txd : out std_logic;
-- I/O ports
p0_out : out std_logic_vector(31 downto 0);
p1_in : in std_logic_vector(31 downto 0);
-- Debug info register output
debug_info : out t_debug_info
);
153,6 → 157,11
signal uart_irq : std_logic;
signal uart_rd_byte : std_logic_vector(7 downto 0);
 
-- I/O registers
signal p0_reg : std_logic_vector(31 downto 0);
signal p1_reg : std_logic_vector(31 downto 0);
signal gpio_rd_data : std_logic_vector(31 downto 0);
 
-- Bootstrap code BRAM
constant BOOT_BRAM_ADDR_SIZE : integer := log2(BOOT_BRAM_SIZE);
subtype t_boot_bram_address is std_logic_vector(BOOT_BRAM_ADDR_SIZE-1 downto 0);
315,13 → 324,58
 
--------------------------------------------------------------------------------
-- GPIO registers
 
gpio_output_registers:
process(clk)
begin
if clk'event and clk='1' then
if reset='1' then
p0_reg <= (others => '0');
else
if mpu_io_wr_addr(19 downto 12)=X"01" then
if mpu_io_byte_we(0)='1' then
p0_reg( 7 downto 0) <= mpu_io_wr_data( 7 downto 0);
end if;
if mpu_io_byte_we(1)='1' then
p0_reg(15 downto 8) <= mpu_io_wr_data(15 downto 8);
end if;
if mpu_io_byte_we(2)='1' then
p0_reg(23 downto 16) <= mpu_io_wr_data(23 downto 16);
end if;
if mpu_io_byte_we(3)='1' then
p0_reg(31 downto 24) <= mpu_io_wr_data(31 downto 24);
end if;
end if;
end if;
end if;
end process gpio_output_registers;
 
p0_out <= p0_reg;
 
gpio_input_registers:
process(clk)
begin
-- Note the input register needs no reset value.
if clk'event and clk='1' then
p1_reg <= p1_in;
end if;
end process gpio_input_registers;
 
with mpu_io_rd_addr(2) select gpio_rd_data <=
p0_reg when '0',
p1_reg when others;
 
--------------------------------------------------------------------------------
-- I/O port multiplexor
-- IO Rd mux: either the UART data/status word or the IO coming from outside
mpu_io_rd_data <=
X"000000" & uart_rd_byte when mpu_io_rd_addr(19 downto 12)=X"00" else
io_rd_data;
with mpu_io_rd_addr(19 downto 12) select mpu_io_rd_data <=
X"000000" & uart_rd_byte when X"00",
gpio_rd_data when X"01",
io_rd_data when others;
 
-- io_rd_data
io_rd_addr <= mpu_io_rd_addr;
/trunk/vhdl/demo/c2sb_demo.vhdl
118,6 → 118,9
-- I/O registers
 
 
signal p0_out : std_logic_vector(31 downto 0);
signal p1_in : std_logic_vector(31 downto 0);
 
signal sd_clk_reg : std_logic;
signal sd_cs_reg : std_logic;
signal sd_cmd_reg : std_logic;
125,10 → 128,9
 
 
-- CPU access to hex display
signal reg_display : std_logic_vector(31 downto 0);
signal reg_display : std_logic_vector(15 downto 0);
 
 
 
--##############################################################################
-- DE-1 board interface signals
 
168,12 → 170,6
-- );
--end component;
 
-- SD control signals
signal sd_in : std_logic;
signal reg_sd_dout : std_logic;
signal reg_sd_clk : std_logic;
signal reg_sd_cs : std_logic;
 
-- MPU interface signals
signal data_uart : std_logic_vector(31 downto 0);
signal data_uart_status : std_logic_vector(31 downto 0);
180,12 → 176,12
signal uart_tx_rdy : std_logic := '1';
signal uart_rx_rdy : std_logic := '1';
 
signal io_rd_data : std_logic_vector(31 downto 0);
signal io_rd_addr : std_logic_vector(31 downto 2);
signal io_wr_addr : std_logic_vector(31 downto 2);
signal io_wr_data : std_logic_vector(31 downto 0);
signal io_rd_vma : std_logic;
signal io_byte_we : std_logic_vector(3 downto 0);
--signal io_rd_data : std_logic_vector(31 downto 0);
--signal io_rd_addr : std_logic_vector(31 downto 2);
--signal io_wr_addr : std_logic_vector(31 downto 2);
--signal io_wr_data : std_logic_vector(31 downto 0);
--signal io_rd_vma : std_logic;
--signal io_byte_we : std_logic_vector(3 downto 0);
 
signal mpu_sram_address : std_logic_vector(SRAM_ADDR_SIZE-1 downto 0);
signal mpu_sram_data_rd : std_logic_vector(15 downto 0);
234,13 → 230,13
port map (
interrupt => "00000000",
 
-- interface to FPGA i/o devices
io_rd_data => io_rd_data,
io_rd_addr => io_rd_addr,
io_wr_addr => io_wr_addr,
io_wr_data => io_wr_data,
io_rd_vma => io_rd_vma,
io_byte_we => io_byte_we,
-- interface to off-SoC, on-FPGA i/o devices: UNUSED
io_rd_data => X"00000000",
io_rd_addr => OPEN,
io_wr_addr => OPEN,
io_wr_data => OPEN,
io_rd_vma => OPEN,
io_byte_we => OPEN,
 
-- interface to asynchronous 16-bit-wide EXTERNAL SRAM
sram_address => mpu_sram_address,
252,6 → 248,9
uart_rxd => rxd,
uart_txd => txd,
 
p0_out => p0_out,
p1_in => p1_in,
debug_info => debug_info,
clk => clk,
260,48 → 259,18
 
 
--##############################################################################
-- I/O registers
-- GPIO and LEDs
--##############################################################################
 
hex_display_register:
process(clk)
begin
if clk'event and clk='1' then
if io_byte_we/="0000" and io_wr_addr(15 downto 12)=X"2" then
--reg_display(15 downto 0) <= io_wr_data(15 downto 0);
reg_display <= mpu_sram_address;
end if;
end if;
end process hex_display_register;
sd_control_register:
process(clk)
begin
if clk'event and clk='1' then
if io_byte_we/="0000" and io_wr_addr(15 downto 12)=X"1" then
if io_wr_addr(5)='1' then
sd_clk_reg <= io_wr_addr(4);
end if;
if io_wr_addr(7)='1' then
sd_cs_reg <= io_wr_addr(6);
end if;
if io_wr_addr(11)='1' then
sd_do_reg <= io_wr_data(0);
end if;
end if;
end if;
end process sd_control_register;
---- LEDS -- We'll use the LEDs to display debug info --------------------------
 
-- HEX display is mostly unused
reg_display <= p0_out(31 downto 16);
 
-- Show the SD interface signals on the green leds for debug
reg_gleds <= sd_clk_reg & sd_in & sd_do_reg & "000" & sd_cmd_reg & sd_cs_reg;
reg_gleds <= p1_in(0) & "0000" & p0_out(2 downto 0);
 
io_rd_data(0) <= sd_in;
io_rd_data(31 downto 22) <= switches;
 
 
 
-- red leds (light with '1') -- some CPU control signals
-- Red leds (light with '1') -- some CPU control signals
red_leds(0) <= debug_info.cache_enabled;
red_leds(1) <= debug_info.unmapped_access;
red_leds(2) <= '0';
441,7 → 410,6
-- locked => pll_locked
-- );
--
----clk <= clk_1hz when reg_display(31 downto 27)="10110" else clk_pll;
--clk <= clk_pll;
--end generate;
 
459,11 → 427,9
--##############################################################################
 
-- Show contents of debug register in hex display
display_data <=
reg_display(15 downto 0) when switches(0)='0' else
reg_display(31 downto 16);
display_data <= reg_display;
 
 
-- 7-segment encoders; the dev board displays are not multiplexed or encoded
hex3 <= nibble_to_7seg(display_data(15 downto 12));
hex2 <= nibble_to_7seg(display_data(11 downto 8));
475,10 → 441,10
--##############################################################################
 
-- Connect to FFs for use in bit-banged interface (still unused)
sd_cs <= sd_cs_reg;
sd_cmd <= sd_do_reg;
sd_clk <= sd_clk_reg;
sd_in <= sd_data;
sd_cs <= p0_out(0); -- SPI CS
sd_cmd <= p0_out(2); -- SPI DI
sd_clk <= p0_out(1); -- SPI SCLK
p1_in(0) <= sd_data; -- SPI DO
 
 
--##############################################################################

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