URL
https://opencores.org/ocsvn/lcd_to_hdmi_output_ip/lcd_to_hdmi_output_ip/trunk
Subversion Repositories lcd_to_hdmi_output_ip
Compare Revisions
- This comparison shows the changes necessary to convert path
/lcd_to_hdmi_output_ip
- from Rev 3 to Rev 4
- ↔ Reverse comparison
Rev 3 → Rev 4
/doc/README.md
0,0 → 1,12
# Verilog HDMI output IP. |
|
This is a very simple HDMI output IP that is driven by a LCD IP. |
|
Is accepting RGB 8 bit/color vertical and horizontal synchronization, data enable and a reference clock that is 5x the LCD clock. |
The outputs are the three serial channels the clock channel and the LCD clock that is equal to reference clock / 5. |
|
The LCD clock provided by the HDMI IP is used to clocking the LCD IP. |
|
The RGB and sinchronization signals are provided by an LCD IP. |
|
The maximum obtained resolution is 1440x900 at less that 60 Hz, maximum 1 gigabit/second/line for Artix7 -1 grade device. |