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URL https://opencores.org/ocsvn/lpffir/lpffir/trunk

Subversion Repositories lpffir

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /lpffir
    from Rev 6 to Rev 7
    ↔ Reverse comparison
  •

Rev 6 → Rev 7

/trunk/bench/systemc/main.cpp
61,10 → 61,10
sc_time T(10,SC_NS);
sc_time Tsim = T * 15 ;
sc_clock clk("clk",T);
sc_signal<bool> rst("rst");
sc_signal<bool> rstn("rstn");
Vbench uut("top");
uut.clk (clk);
uut.rst(rst);
uut.rstn(rstn);
 
#ifdef TRACE
// Verilator trace file, depth
72,9 → 72,9
tfp->open("simu.vcd");
#endif
 
rst = 1;
rstn = 0;
sc_start(10*T);
rst = 0;
rstn = 1;
sc_start(Tsim);
 
#ifdef TRACE
/trunk/bench/verilog/bench.sv
45,22 → 45,35
// Verilog test bench
module bench (
input clk,
input rst
input rstn
);
 
// Test case #1: check impulse response of low-pass filter.
logic rx_tready;
logic tx_tlast;
logic tx_tvalid;
logic [15:0] in = (count == 1) ? 1:0;
logic [15:0] out;
reg [31:0] count;
 
always_ff @(posedge clk or posedge rst)
if (rst)
always_ff @(posedge clk or posedge rstn)
if (!rstn)
count <= 0;
else
count <= count + 1;
 
// unit under test(UUT)
lpffir_core lpffir_core(.x_i(in),.clk_i(clk),.y_o(out));
lpffir_axis lpffir_axis (
.aclk_i(clk),
.aresetn_i(rstn),
.rx_tlast_i(0),
.rx_tvalid_i(1),
.rx_tready_o(rx_tready),
.rx_tdate_i(in),
.tx_tlast_o(tx_tlast),
.tx_tvalid_o(tx_tvalid),
.tx_tready_i(1),
.tx_tdate_o(out)
);
 
// Test case log
initial begin
71,8 → 84,8
$display("----- ------");
end
 
always_ff @(posedge clk or posedge rst)
if(!rst)
always_ff @(posedge clk or posedge rstn)
if(rstn)
$display(" %0d %0d", in, out);
 
endmodule
/trunk/rtl/lpffir_axis.sv
0,0 → 1,77
//////////////////////////////////////////////////////////////////////
//// ////
//// Low Pass Filter FIR with AXI-Stream Interface ////
//// ////
//// This file is part of the LPFFIR project ////
//// https://opencores.org/projects/lpffir ////
//// ////
//// Description ////
//// Implementation of AXI-Stream (AXIS) protocol rapper ////
/// of LPFFIR IP core according to ////
//// LPFFIR IP core specification document. ////
//// ////
//// To Do: ////
//// - ////
//// ////
//// Author: ////
//// - Vladimir Armstrong, vladimirarmstrong@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2019 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
module lpffir_axis (
input aclk_i,
input aresetn_i,
// AXI-Stream RX interface
input rx_tlast_i,
input rx_tvalid_i,
output logic rx_tready_o,
input [15:0] rx_tdate_i,
// AXI-Stream TX interface
output logic tx_tlast_o,
output reg tx_tvalid_o,
input tx_tready_i,
output logic [15:0] tx_tdate_o
);
 
logic lpffir_en = rx_tvalid_i && tx_tready_i;
 
// AXI-Stream interface
assign rx_tready_o = lpffir_en;
assign tx_tvalid_o = lpffir_en;
assign tx_tlast_o = rx_tlast_i;
 
// LPFFIR
lpffir_core lpffir_core(
.clk_i(aclk_i),
.rstn_i(aresetn_i),
.en_i(lpffir_en),
.x_i(rx_tdate_i),
.y_o(tx_tdate_o)
);
 
endmodule
/trunk/rtl/lpffir_core.sv
43,27 → 43,29
//////////////////////////////////////////////////////////////////////
 
module lpffir_core (
input [15:0] x_i,
input clk_i,
output logic [15:0] y_o
);
input clk_i,
input rstn_i,
input en_i,
input [15:0] x_i,
output logic [15:0] y_o
);
 
reg [15:0] x1;
reg [15:0] x2;
reg [15:0] x3;
reg [15:0] x4;
reg [15:0] x5;
reg [15:0] x1;
reg [15:0] x2;
reg [15:0] x3;
reg [15:0] x4;
reg [15:0] x5;
 
logic [15:0] h0;
logic [15:0] h1;
logic [15:0] h2;
logic [15:0] h01;
logic [15:0] h0;
logic [15:0] h1;
logic [15:0] h2;
logic [15:0] h01;
 
logic co0;
logic co1;
logic co2;
logic co3;
logic co4;
logic co0;
logic co1;
logic co2;
logic co3;
logic co4;
 
// Linear-phase FIR structure
rca rca_inst0 (.a(x_i),.b(x5),.ci(0),.co(co0),.s(h0));
72,13 → 74,22
rca rca_inst3 (.a(h0),.b(h1),.ci(0),.co(co3),.s(h01));
rca rca_inst4 (.a(h01),.b(h2),.ci(0),.co(co4),.s(y_o));
 
always_ff @(posedge clk_i)
begin
x1 <= x_i;
x2 <= x1;
x3 <= x2;
x4 <= x3;
x5 <= x4;
end
always_ff @(posedge clk_i or posedge rstn_i)
if(!rstn_i)
begin
x1 <= 0;
x2 <= 0;
x3 <= 0;
x4 <= 0;
x5 <= 0;
end
else if (en_i)
begin
x1 <= x_i;
x2 <= x1;
x3 <= x2;
x4 <= x3;
x5 <= x4;
end
 
endmodule
/trunk/sim/rtl_sim/run/wave.gtkw
1,25 → 1,34
[*]
[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
[*] Sun Dec 30 18:25:07 2018
[*] Wed Mar 27 19:49:17 2019
[*]
[dumpfile] "/home/vlad/opencore/lpffir/trunk/sim/rtl_sim/run/simu.vcd"
[dumpfile_mtime] "Sun Dec 30 17:30:49 2018"
[dumpfile_size] 38184
[savefile] "/home/vlad/opencore/lpffir/trunk/sim/rtl_sim/run/wave.gtkw"
[timestart] 96600
[size] 2426 847
[pos] -2397 579
*-13.116134 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[dumpfile] "/home/vlad/opencores/lpffir/2019.03.27/trunk/sim/rtl_sim/run/simu.vcd"
[dumpfile_mtime] "Wed Mar 27 19:45:49 2019"
[dumpfile_size] 39999
[savefile] "/home/vlad/opencores/lpffir/2019.03.27/trunk/sim/rtl_sim/run/wave.gtkw"
[timestart] 0
[size] 1820 1104
[pos] -1935 862
*-15.116134 160000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] top.
[treeopen] top.bench.
[sst_width] 229
[signals_width] 202
[sst_expanded] 1
[sst_vpaned_height] 227
[sst_vpaned_height] 312
@28
top.bench.lpffir_core.clk_i
top.bench.lpffir_axis.aclk_i
top.bench.lpffir_axis.aresetn_i
top.bench.lpffir_axis.rx_tlast_i
top.bench.lpffir_axis.rx_tready_o
top.bench.lpffir_axis.rx_tvalid_i
@22
top.bench.lpffir_core.x_i[15:0]
top.bench.lpffir_core.y_o[15:0]
top.bench.lpffir_axis.rx_tdate_i[15:0]
@28
top.bench.lpffir_axis.tx_tlast_o
top.bench.lpffir_axis.tx_tready_i
top.bench.lpffir_axis.tx_tvalid_o
@23
top.bench.lpffir_axis.tx_tdate_o[15:0]
[pattern_trace] 1
[pattern_trace] 0

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