URL
https://opencores.org/ocsvn/m32632/m32632/trunk
Subversion Repositories m32632
Compare Revisions
- This comparison shows the changes necessary to convert path
/m32632
- from Rev 47 to Rev 48
- ↔ Reverse comparison
Rev 47 → Rev 48
/trunk/rtl/DATENPFAD.v
4,13 → 4,16
// http://opencores.org/project,m32632 |
// |
// Filename: DATENPFAD.v |
// Version: 3.0 Cache Interface reworked |
// History: 2.1 bug fix of 26 November 2016 |
// Project: M32632 |
// Version: 3.1 bug fix of 25 February 2019 |
// History: 3.0 Cache Interface reworked |
// 2.1 bug fix of 26 November 2016 |
// 1.1 bug fix of 7 October 2015 |
// 1.0 first release of 30 Mai 2015 |
// Date: 2 December 2018 |
// Author: Udo Moeller |
// Date: 8 July 2017 |
// |
// Copyright (C) 2018 Udo Moeller |
// Copyright (C) 2019 Udo Moeller |
// |
// This source file may be used and distributed without |
// restriction provided that this copyright statement is not |
43,7 → 46,7
module DATENPFAD( BCLK, BRESET, WREN, IO_READY, LD_DIN, LD_IMME, WR_REG, IC_USER, ACC_FELD, ACC_STAT, DIN, DISP, IC_TEX, |
IMME_Q, INFO_AU, LD_OUT, DETOIP, MMU_UPDATE, OPER, PC_ARCHI, PC_ICACHE, RDAA, RDAB, START, WMASKE, |
WRADR, DONE, Y_INIT, WRITE_OUT, READ_OUT, ZTEST, RMW, QWATWO, ACC_DONE, CTRL_QW, PTB_SEL, PTB_WR, ACB_ZERO, |
ABORT, SAVE_PC, CFG, CINV, DP_Q, IVAR, MCR, PACKET, PC_NEW, PSR, SIZE, STRING, TRAPS, VADR, RWVFLAG, |
ABORT, SAVE_PC, CFG, CINV, DP_Q, IVAR, IVAR_MUX, MCR, PACKET, PC_NEW, PSR, SIZE, STRING, TRAPS, VADR, RWVFLAG, |
DBG_HIT, DBG_IN, COP_GO, COP_OP, COP_IN, COP_DONE, COP_OUT); |
|
input BCLK; |
96,6 → 99,7
output [3:0] CINV; |
output [63:0] DP_Q; |
output [1:0] IVAR; |
output IVAR_MUX; |
output [3:0] MCR; |
output [3:0] PACKET; |
output [31:0] PC_NEW; |
145,7 → 149,6
wire [31:0] I_OUT; |
wire [31:0] FP_OUT; |
wire DOWR; |
wire [31:0] DEST1,DEST2; |
wire ENWR; |
wire [3:0] OVF_BCD; |
wire [3:0] DSR; |
325,6 → 328,7
.CFG(CFG), |
.CINV(CINV), |
.IVAR(IVAR), |
.IVAR_MUX(IVAR_MUX), |
.Y_INIT(Y_INIT), |
.MCR(MCR), |
.DBG_TRAPS(TRAPS[5:3]), |
/trunk/rtl/ICACHE.v
4,12 → 4,15
// http://opencores.org/project,m32632 |
// |
// Filename: ICACHE.v |
// Version: 3.0 Cache Interface reworked |
// History: 2.0 50 MHz release of 14 August 2016 |
// Project: M32632 |
// Version: 3.1 bug fix of 25 February 2019 |
// History: 3.0 Cache Interface reworked |
// 2.0 50 MHz release of 14 August 2016 |
// 1.0 first release of 30 Mai 2015 |
// Date: 2 December 2018 |
// Author: Udo Moeller |
// Date: 8 July 2017 |
// |
// Copyright (C) 2018 Udo Moeller |
// Copyright (C) 2019 Udo Moeller |
// |
// This source file may be used and distributed without |
// restriction provided that this copyright statement is not |
40,7 → 43,7
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
|
module ICACHE( BCLK, DRAMSZ, MDONE, BRESET, READ_I, IO_READY, PSR_USER, DATA_HOLD, PTB_WR, PTB_SEL, DRAM_WR, |
KDET, HOLD, CFG, DRAM_Q, CINVAL, IC_SIGS, IO_Q, IVAR, KOLLI_A, MCR_FLAGS, MMU_DIN, VADR, |
KDET, HOLD, CFG, DRAM_Q, CINVAL, IC_SIGS, IO_Q, IVAR, IVAR_MUX, VADR_D, KOLLI_A, MCR_FLAGS, MMU_DIN, VADR_I, |
INHIBIT, IO_RD, DRAM_ACC, INIT_RUN, PROT_ERROR, ACC_OK, IC_PREQ, KOLLISION, ENA_HK, STOP_CINV, |
DRAM_A, IC_DQ, IC_VA, ICTODC, IO_A, ENDRAM ); |
|
63,10 → 66,12
input [1:0] IC_SIGS; |
input [31:0] IO_Q; |
input [1:0] IVAR; |
input IVAR_MUX; |
input [31:12] VADR_D; |
input [28:4] KOLLI_A; |
input [3:0] MCR_FLAGS; |
input [23:0] MMU_DIN; |
input [31:0] VADR; |
input [31:0] VADR_I; |
input INHIBIT; |
input ENA_HK; |
input ENDRAM; |
92,9 → 97,10
reg DFF_HDFF1; |
reg DFF_IRD_REG; |
|
wire [4:0] A_CV; |
wire [31:0] VADR; |
wire [4:0] A_CV; |
wire ACOK; |
wire [4:0] ACV; |
wire [4:0] ACV; |
wire AUX_DAT; |
wire CA_HIT; |
wire CA_SET; |
212,6 → 218,9
|
assign ICTODC[3] = USER; |
|
assign VADR[31:12] = IVAR_MUX ? VADR_D : VADR_I[31:12]; |
assign VADR[11:0] = VADR_I[11:0]; |
|
always @(posedge BCLK) VADR_R <= VADR; |
|
always @(posedge BCLK) DFF_IRD_REG <= IO_RD; |
/trunk/rtl/M32632.v
4,14 → 4,17
// http://opencores.org/project,m32632 |
// |
// Filename: M32632.v |
// Version: 3.0 Cache Interface reworked |
// History: 2.1 bug fix of 26 November 2016 |
// Project: M32632 |
// Version: 3.1 bug fix of 25 February 2019 |
// History: 3.0 Cache Interface reworked |
// 2.1 bug fix of 26 November 2016 |
// 2.0 50 MHz release of 14 August 2016 |
// 1.1 bug fix of 7 October 2015 |
// 1.0 first release of 30 Mai 2015 |
// Date: 2 December 2018 |
// Author: Udo Moeller |
// Date: 8 July 2017 |
// |
// Copyright (C) 2018 Udo Moeller |
// Copyright (C) 2019 Udo Moeller |
// |
// This source file may be used and distributed without |
// restriction provided that this copyright statement is not |
113,6 → 116,7
wire [3:0] ICTODC; |
wire [6:0] INFO_AU; |
wire [1:0] IVAR; |
wire IVAR_MUX; |
wire KDET; |
wire [28:4] KOLLI_A; |
wire [3:0] MCR; |
282,6 → 286,7
.CINV(CINV), |
.DP_Q(DP_Q), |
.IVAR(IVAR), |
.IVAR_MUX(IVAR_MUX), |
.MCR(MCR), |
.PACKET(PACKET), |
.PC_NEW(PC_NEW), |
323,10 → 328,12
.IC_SIGS(IC_SIGS), |
.IO_Q(IO_Q), |
.IVAR(IVAR), |
.IVAR_MUX(IVAR_MUX), |
.VADR_D(VADR[31:12]), |
.KOLLI_A(KOLLI_A), |
.MCR_FLAGS(MCR), |
.MMU_DIN(MMU_DIN), |
.VADR(PC_ICACHE), |
.VADR_I(PC_ICACHE), |
.INHIBIT(IC_INHIBIT), |
.DRAM_ACC(IC_ACC), |
.IO_RD(I_IORD), |
/trunk/rtl/REGISTERS.v
4,11 → 4,13
// http://opencores.org/project,m32632 |
// |
// Filename: REGISTERS.v |
// Version: 3.0 |
// Project: M32632 |
// Version: 3.1 bug fix of 25 February 2019 |
// History: 1.0 first release of 30 Mai 2015 |
// Date: 2 December 2018 |
// Author: Udo Moeller |
// Date: 8 July 2017 |
// |
// Copyright (C) 2018 Udo Moeller |
// Copyright (C) 2019 Udo Moeller |
// |
// This source file may be used and distributed without |
// restriction provided that this copyright statement is not |
46,7 → 48,7
// |
// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ |
module CONFIG_REGS ( BCLK, BRESET, WREN, LD_OUT, OPCODE, SRC1, WRADR, PC_ARCHI, USER, PCMATCH, DBG_HIT, READ, |
CFG, MCR, PTB_WR, PTB_SEL, IVAR, CINV, Y_INIT, DSR, DBG_TRAPS, DBG_IN ); |
CFG, MCR, PTB_WR, PTB_SEL, IVAR, IVAR_MUX, CINV, Y_INIT, DSR, DBG_TRAPS, DBG_IN ); |
|
input BCLK,BRESET; |
input WREN,LD_OUT; |
64,6 → 66,7
output PTB_WR; |
output PTB_SEL; |
output [1:0] IVAR; |
output IVAR_MUX; |
output [3:0] CINV; |
output Y_INIT; |
output [3:0] DSR; |
97,7 → 100,8
if (!BRESET) MCR <= 4'h0; |
else if (ld_mcr) MCR <= SRC1[3:0]; |
|
always @(posedge BCLK) ivarreg <= op_ok & (WRADR[5:1] == 5'd7) & WREN; // IVAR0/1 = Reg. Nr. 14/15 |
assign IVAR_MUX = op_ok & (WRADR[5:1] == 5'd7) & WREN; // IVAR0/1 = Reg. Nr. 14/15 |
always @(posedge BCLK) ivarreg <= IVAR_MUX; |
assign IVAR = {ivarreg,PTB_SEL}; |
|
always @(posedge BCLK) PTB_WR <= op_ok & (WRADR[5:1] == 5'd6) & WREN; // PTB0/1 = Reg. Nr. 12/13 |